include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/types.h>
  11 #include <linux/uuid.h>
  12
  13 /* NQN names in commands fields specified one size */
  14 #define NVMF_NQN_FIELD_LEN      256
  15
  16 /* However the max length of a qualified name is another size */
  17 #define NVMF_NQN_SIZE           223
  18
  19 #define NVMF_TRSVCID_SIZE       32
  20 #define NVMF_TRADDR_SIZE        256
  21 #define NVMF_TSAS_SIZE          256
  22
  23 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  24
  25 #define NVME_RDMA_IP_PORT       4420
  26
  27 #define NVME_NSID_ALL           0xffffffff
  28
  29 enum nvme_subsys_type {
  30         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  31         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  32 };
  33
  34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  35 enum {
  36         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  37         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  38         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  39         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  40         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  41 };
  42
  43 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  44 enum {
  45         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  46         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  47         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  48         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  49         NVMF_TRTYPE_MAX,
  50 };
  51
  52 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  53 enum {
  54         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  55         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  56         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  57 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  58         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  59
  60         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  61 };
  62
  63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  64  * RDMA_QPTYPE field
  65  */
  66 enum {
  67         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  68         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  69 };
  70
  71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  72  * RDMA_QPTYPE field
  73  */
  74 enum {
  75         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  76         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  77         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  78         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  79         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  80 };
  81
  82 /* RDMA Connection Management Service Type codes for Discovery Log Page
  83  * entry TSAS RDMA_CMS field
  84  */
  85 enum {
  86         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  87 };
  88
  89 #define NVME_AQ_DEPTH           32
  90 #define NVME_NR_AEN_COMMANDS    1
  91 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  92
  93 /*
  94  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  95  * NVM-Express 1.2 specification, section 4.1.2.
  96  */
  97 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
  98
  99 enum {
 100         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 101         NVME_REG_VS     = 0x0008,       /* Version */
 102         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 103         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 104         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 105         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 106         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 107         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 108         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 109         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 110         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 111         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 112         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 113 };
 114
 115 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 116 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 117 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 118 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 119 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 120 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 121
 122 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 123 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 124
 125 enum {
 126         NVME_CMBSZ_SQS          = 1 << 0,
 127         NVME_CMBSZ_CQS          = 1 << 1,
 128         NVME_CMBSZ_LISTS        = 1 << 2,
 129         NVME_CMBSZ_RDS          = 1 << 3,
 130         NVME_CMBSZ_WDS          = 1 << 4,
 131
 132         NVME_CMBSZ_SZ_SHIFT     = 12,
 133         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 134
 135         NVME_CMBSZ_SZU_SHIFT    = 8,
 136         NVME_CMBSZ_SZU_MASK     = 0xf,
 137 };
 138
 139 /*
 140  * Submission and Completion Queue Entry Sizes for the NVM command set.
 141  * (In bytes and specified as a power of two (2^n)).
 142  */
 143 #define NVME_NVM_IOSQES         6
 144 #define NVME_NVM_IOCQES         4
 145
 146 enum {
 147         NVME_CC_ENABLE          = 1 << 0,
 148         NVME_CC_CSS_NVM         = 0 << 4,
 149         NVME_CC_EN_SHIFT        = 0,
 150         NVME_CC_CSS_SHIFT       = 4,
 151         NVME_CC_MPS_SHIFT       = 7,
 152         NVME_CC_AMS_SHIFT       = 11,
 153         NVME_CC_SHN_SHIFT       = 14,
 154         NVME_CC_IOSQES_SHIFT    = 16,
 155         NVME_CC_IOCQES_SHIFT    = 20,
 156         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 157         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 158         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 159         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 160         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 161         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 162         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 163         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 164         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 165         NVME_CSTS_RDY           = 1 << 0,
 166         NVME_CSTS_CFS           = 1 << 1,
 167         NVME_CSTS_NSSRO         = 1 << 4,
 168         NVME_CSTS_PP            = 1 << 5,
 169         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 170         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 171         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 172         NVME_CSTS_SHST_MASK     = 3 << 2,
 173 };
 174
 175 struct nvme_id_power_state {
 176         __le16                  max_power;      /* centiwatts */
 177         __u8                    rsvd2;
 178         __u8                    flags;
 179         __le32                  entry_lat;      /* microseconds */
 180         __le32                  exit_lat;       /* microseconds */
 181         __u8                    read_tput;
 182         __u8                    read_lat;
 183         __u8                    write_tput;
 184         __u8                    write_lat;
 185         __le16                  idle_power;
 186         __u8                    idle_scale;
 187         __u8                    rsvd19;
 188         __le16                  active_power;
 189         __u8                    active_work_scale;
 190         __u8                    rsvd23[9];
 191 };
 192
 193 enum {
 194         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 195         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 196 };
 197
 198 enum nvme_ctrl_attr {
 199         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 200         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 201 };
 202
 203 struct nvme_id_ctrl {
 204         __le16                  vid;
 205         __le16                  ssvid;
 206         char                    sn[20];
 207         char                    mn[40];
 208         char                    fr[8];
 209         __u8                    rab;
 210         __u8                    ieee[3];
 211         __u8                    cmic;
 212         __u8                    mdts;
 213         __le16                  cntlid;
 214         __le32                  ver;
 215         __le32                  rtd3r;
 216         __le32                  rtd3e;
 217         __le32                  oaes;
 218         __le32                  ctratt;
 219         __u8                    rsvd100[28];
 220         __le16                  crdt1;
 221         __le16                  crdt2;
 222         __le16                  crdt3;
 223         __u8                    rsvd134[122];
 224         __le16                  oacs;
 225         __u8                    acl;
 226         __u8                    aerl;
 227         __u8                    frmw;
 228         __u8                    lpa;
 229         __u8                    elpe;
 230         __u8                    npss;
 231         __u8                    avscc;
 232         __u8                    apsta;
 233         __le16                  wctemp;
 234         __le16                  cctemp;
 235         __le16                  mtfa;
 236         __le32                  hmpre;
 237         __le32                  hmmin;
 238         __u8                    tnvmcap[16];
 239         __u8                    unvmcap[16];
 240         __le32                  rpmbs;
 241         __le16                  edstt;
 242         __u8                    dsto;
 243         __u8                    fwug;
 244         __le16                  kas;
 245         __le16                  hctma;
 246         __le16                  mntmt;
 247         __le16                  mxtmt;
 248         __le32                  sanicap;
 249         __le32                  hmminds;
 250         __le16                  hmmaxd;
 251         __u8                    rsvd338[4];
 252         __u8                    anatt;
 253         __u8                    anacap;
 254         __le32                  anagrpmax;
 255         __le32                  nanagrpid;
 256         __u8                    rsvd352[160];
 257         __u8                    sqes;
 258         __u8                    cqes;
 259         __le16                  maxcmd;
 260         __le32                  nn;
 261         __le16                  oncs;
 262         __le16                  fuses;
 263         __u8                    fna;
 264         __u8                    vwc;
 265         __le16                  awun;
 266         __le16                  awupf;
 267         __u8                    nvscc;
 268         __u8                    nwpc;
 269         __le16                  acwu;
 270         __u8                    rsvd534[2];
 271         __le32                  sgls;
 272         __le32                  mnan;
 273         __u8                    rsvd544[224];
 274         char                    subnqn[256];
 275         __u8                    rsvd1024[768];
 276         __le32                  ioccsz;
 277         __le32                  iorcsz;
 278         __le16                  icdoff;
 279         __u8                    ctrattr;
 280         __u8                    msdbd;
 281         __u8                    rsvd1804[244];
 282         struct nvme_id_power_state      psd[32];
 283         __u8                    vs[1024];
 284 };
 285
 286 enum {
 287         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 288         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 289         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 290         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 291         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 292         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 293         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 294         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 295         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 296         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 297 };
 298
 299 struct nvme_lbaf {
 300         __le16                  ms;
 301         __u8                    ds;
 302         __u8                    rp;
 303 };
 304
 305 struct nvme_id_ns {
 306         __le64                  nsze;
 307         __le64                  ncap;
 308         __le64                  nuse;
 309         __u8                    nsfeat;
 310         __u8                    nlbaf;
 311         __u8                    flbas;
 312         __u8                    mc;
 313         __u8                    dpc;
 314         __u8                    dps;
 315         __u8                    nmic;
 316         __u8                    rescap;
 317         __u8                    fpi;
 318         __u8                    rsvd33;
 319         __le16                  nawun;
 320         __le16                  nawupf;
 321         __le16                  nacwu;
 322         __le16                  nabsn;
 323         __le16                  nabo;
 324         __le16                  nabspf;
 325         __le16                  noiob;
 326         __u8                    nvmcap[16];
 327         __u8                    rsvd64[28];
 328         __le32                  anagrpid;
 329         __u8                    rsvd96[3];
 330         __u8                    nsattr;
 331         __u8                    rsvd100[4];
 332         __u8                    nguid[16];
 333         __u8                    eui64[8];
 334         struct nvme_lbaf        lbaf[16];
 335         __u8                    rsvd192[192];
 336         __u8                    vs[3712];
 337 };
 338
 339 enum {
 340         NVME_ID_CNS_NS                  = 0x00,
 341         NVME_ID_CNS_CTRL                = 0x01,
 342         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 343         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 344         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 345         NVME_ID_CNS_NS_PRESENT          = 0x11,
 346         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 347         NVME_ID_CNS_CTRL_LIST           = 0x13,
 348 };
 349
 350 enum {
 351         NVME_DIR_IDENTIFY               = 0x00,
 352         NVME_DIR_STREAMS                = 0x01,
 353         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 354         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 355         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 356         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 357         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 358         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 359         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 360         NVME_DIR_ENDIR                  = 0x01,
 361 };
 362
 363 enum {
 364         NVME_NS_FEAT_THIN       = 1 << 0,
 365         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 366         NVME_NS_FLBAS_META_EXT  = 0x10,
 367         NVME_LBAF_RP_BEST       = 0,
 368         NVME_LBAF_RP_BETTER     = 1,
 369         NVME_LBAF_RP_GOOD       = 2,
 370         NVME_LBAF_RP_DEGRADED   = 3,
 371         NVME_NS_DPC_PI_LAST     = 1 << 4,
 372         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 373         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 374         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 375         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 376         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 377         NVME_NS_DPS_PI_MASK     = 0x7,
 378         NVME_NS_DPS_PI_TYPE1    = 1,
 379         NVME_NS_DPS_PI_TYPE2    = 2,
 380         NVME_NS_DPS_PI_TYPE3    = 3,
 381 };
 382
 383 struct nvme_ns_id_desc {
 384         __u8 nidt;
 385         __u8 nidl;
 386         __le16 reserved;
 387 };
 388
 389 #define NVME_NIDT_EUI64_LEN     8
 390 #define NVME_NIDT_NGUID_LEN     16
 391 #define NVME_NIDT_UUID_LEN      16
 392
 393 enum {
 394         NVME_NIDT_EUI64         = 0x01,
 395         NVME_NIDT_NGUID         = 0x02,
 396         NVME_NIDT_UUID          = 0x03,
 397 };
 398
 399 struct nvme_smart_log {
 400         __u8                    critical_warning;
 401         __u8                    temperature[2];
 402         __u8                    avail_spare;
 403         __u8                    spare_thresh;
 404         __u8                    percent_used;
 405         __u8                    rsvd6[26];
 406         __u8                    data_units_read[16];
 407         __u8                    data_units_written[16];
 408         __u8                    host_reads[16];
 409         __u8                    host_writes[16];
 410         __u8                    ctrl_busy_time[16];
 411         __u8                    power_cycles[16];
 412         __u8                    power_on_hours[16];
 413         __u8                    unsafe_shutdowns[16];
 414         __u8                    media_errors[16];
 415         __u8                    num_err_log_entries[16];
 416         __le32                  warning_temp_time;
 417         __le32                  critical_comp_time;
 418         __le16                  temp_sensor[8];
 419         __u8                    rsvd216[296];
 420 };
 421
 422 struct nvme_fw_slot_info_log {
 423         __u8                    afi;
 424         __u8                    rsvd1[7];
 425         __le64                  frs[7];
 426         __u8                    rsvd64[448];
 427 };
 428
 429 enum {
 430         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 431         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 432         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 433         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 434         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 435         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 436 };
 437
 438 struct nvme_effects_log {
 439         __le32 acs[256];
 440         __le32 iocs[256];
 441         __u8   resv[2048];
 442 };
 443
 444 enum nvme_ana_state {
 445         NVME_ANA_OPTIMIZED              = 0x01,
 446         NVME_ANA_NONOPTIMIZED           = 0x02,
 447         NVME_ANA_INACCESSIBLE           = 0x03,
 448         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 449         NVME_ANA_CHANGE                 = 0x0f,
 450 };
 451
 452 struct nvme_ana_group_desc {
 453         __le32  grpid;
 454         __le32  nnsids;
 455         __le64  chgcnt;
 456         __u8    state;
 457         __u8    rsvd17[15];
 458         __le32  nsids[];
 459 };
 460
 461 /* flag for the log specific field of the ANA log */
 462 #define NVME_ANA_LOG_RGO        (1 << 0)
 463
 464 struct nvme_ana_rsp_hdr {
 465         __le64  chgcnt;
 466         __le16  ngrps;
 467         __le16  rsvd10[3];
 468 };
 469
 470 enum {
 471         NVME_SMART_CRIT_SPARE           = 1 << 0,
 472         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 473         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 474         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 475         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 476 };
 477
 478 enum {
 479         NVME_AER_ERROR                  = 0,
 480         NVME_AER_SMART                  = 1,
 481         NVME_AER_NOTICE                 = 2,
 482         NVME_AER_CSS                    = 6,
 483         NVME_AER_VS                     = 7,
 484 };
 485
 486 enum {
 487         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 488         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 489         NVME_AER_NOTICE_ANA             = 0x03,
 490         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 491 };
 492
 493 enum {
 494         NVME_AEN_BIT_NS_ATTR            = 8,
 495         NVME_AEN_BIT_FW_ACT             = 9,
 496         NVME_AEN_BIT_ANA_CHANGE         = 11,
 497         NVME_AEN_BIT_DISC_CHANGE        = 31,
 498 };
 499
 500 enum {
 501         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 502         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 503         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 504         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 505 };
 506
 507 struct nvme_lba_range_type {
 508         __u8                    type;
 509         __u8                    attributes;
 510         __u8                    rsvd2[14];
 511         __u64                   slba;
 512         __u64                   nlb;
 513         __u8                    guid[16];
 514         __u8                    rsvd48[16];
 515 };
 516
 517 enum {
 518         NVME_LBART_TYPE_FS      = 0x01,
 519         NVME_LBART_TYPE_RAID    = 0x02,
 520         NVME_LBART_TYPE_CACHE   = 0x03,
 521         NVME_LBART_TYPE_SWAP    = 0x04,
 522
 523         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 524         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 525 };
 526
 527 struct nvme_reservation_status {
 528         __le32  gen;
 529         __u8    rtype;
 530         __u8    regctl[2];
 531         __u8    resv5[2];
 532         __u8    ptpls;
 533         __u8    resv10[13];
 534         struct {
 535                 __le16  cntlid;
 536                 __u8    rcsts;
 537                 __u8    resv3[5];
 538                 __le64  hostid;
 539                 __le64  rkey;
 540         } regctl_ds[];
 541 };
 542
 543 enum nvme_async_event_type {
 544         NVME_AER_TYPE_ERROR     = 0,
 545         NVME_AER_TYPE_SMART     = 1,
 546         NVME_AER_TYPE_NOTICE    = 2,
 547 };
 548
 549 /* I/O commands */
 550
 551 enum nvme_opcode {
 552         nvme_cmd_flush          = 0x00,
 553         nvme_cmd_write          = 0x01,
 554         nvme_cmd_read           = 0x02,
 555         nvme_cmd_write_uncor    = 0x04,
 556         nvme_cmd_compare        = 0x05,
 557         nvme_cmd_write_zeroes   = 0x08,
 558         nvme_cmd_dsm            = 0x09,
 559         nvme_cmd_resv_register  = 0x0d,
 560         nvme_cmd_resv_report    = 0x0e,
 561         nvme_cmd_resv_acquire   = 0x11,
 562         nvme_cmd_resv_release   = 0x15,
 563 };
 564
 565 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 566 #define show_nvm_opcode_name(val)                               \
 567         __print_symbolic(val,                                   \
 568                 nvme_opcode_name(nvme_cmd_flush),               \
 569                 nvme_opcode_name(nvme_cmd_write),               \
 570                 nvme_opcode_name(nvme_cmd_read),                \
 571                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 572                 nvme_opcode_name(nvme_cmd_compare),             \
 573                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 574                 nvme_opcode_name(nvme_cmd_dsm),                 \
 575                 nvme_opcode_name(nvme_cmd_resv_register),       \
 576                 nvme_opcode_name(nvme_cmd_resv_report),         \
 577                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 578                 nvme_opcode_name(nvme_cmd_resv_release))
 579
 580
 581 /*
 582  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 583  *
 584  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 585  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 586  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 587  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 588  *                            request subtype
 589  */
 590 enum {
 591         NVME_SGL_FMT_ADDRESS            = 0x00,
 592         NVME_SGL_FMT_OFFSET             = 0x01,
 593         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 594         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 595 };
 596
 597 /*
 598  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 599  *
 600  * For struct nvme_sgl_desc:
 601  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 602  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 603  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 604  *
 605  * For struct nvme_keyed_sgl_desc:
 606  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 607  *
 608  * Transport-specific SGL types:
 609  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 610  */
 611 enum {
 612         NVME_SGL_FMT_DATA_DESC          = 0x00,
 613         NVME_SGL_FMT_SEG_DESC           = 0x02,
 614         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 615         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 616         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 617 };
 618
 619 struct nvme_sgl_desc {
 620         __le64  addr;
 621         __le32  length;
 622         __u8    rsvd[3];
 623         __u8    type;
 624 };
 625
 626 struct nvme_keyed_sgl_desc {
 627         __le64  addr;
 628         __u8    length[3];
 629         __u8    key[4];
 630         __u8    type;
 631 };
 632
 633 union nvme_data_ptr {
 634         struct {
 635                 __le64  prp1;
 636                 __le64  prp2;
 637         };
 638         struct nvme_sgl_desc    sgl;
 639         struct nvme_keyed_sgl_desc ksgl;
 640 };
 641
 642 /*
 643  * Lowest two bits of our flags field (FUSE field in the spec):
 644  *
 645  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 646  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 647  *
 648  * Highest two bits in our flags field (PSDT field in the spec):
 649  *
 650  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 651  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 652  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 653  *      If used, MPTR contains an address of an SGL segment containing
 654  *      exactly 1 SGL descriptor (qword aligned).
 655  */
 656 enum {
 657         NVME_CMD_FUSE_FIRST     = (1 << 0),
 658         NVME_CMD_FUSE_SECOND    = (1 << 1),
 659
 660         NVME_CMD_SGL_METABUF    = (1 << 6),
 661         NVME_CMD_SGL_METASEG    = (1 << 7),
 662         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 663 };
 664
 665 struct nvme_common_command {
 666         __u8                    opcode;
 667         __u8                    flags;
 668         __u16                   command_id;
 669         __le32                  nsid;
 670         __le32                  cdw2[2];
 671         __le64                  metadata;
 672         union nvme_data_ptr     dptr;
 673         __le32                  cdw10;
 674         __le32                  cdw11;
 675         __le32                  cdw12;
 676         __le32                  cdw13;
 677         __le32                  cdw14;
 678         __le32                  cdw15;
 679 };
 680
 681 struct nvme_rw_command {
 682         __u8                    opcode;
 683         __u8                    flags;
 684         __u16                   command_id;
 685         __le32                  nsid;
 686         __u64                   rsvd2;
 687         __le64                  metadata;
 688         union nvme_data_ptr     dptr;
 689         __le64                  slba;
 690         __le16                  length;
 691         __le16                  control;
 692         __le32                  dsmgmt;
 693         __le32                  reftag;
 694         __le16                  apptag;
 695         __le16                  appmask;
 696 };
 697
 698 enum {
 699         NVME_RW_LR                      = 1 << 15,
 700         NVME_RW_FUA                     = 1 << 14,
 701         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 702         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 703         NVME_RW_DSM_FREQ_RARE           = 2,
 704         NVME_RW_DSM_FREQ_READS          = 3,
 705         NVME_RW_DSM_FREQ_WRITES         = 4,
 706         NVME_RW_DSM_FREQ_RW             = 5,
 707         NVME_RW_DSM_FREQ_ONCE           = 6,
 708         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 709         NVME_RW_DSM_FREQ_TEMP           = 8,
 710         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 711         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 712         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 713         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 714         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 715         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 716         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 717         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 718         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 719         NVME_RW_PRINFO_PRACT            = 1 << 13,
 720         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 721 };
 722
 723 struct nvme_dsm_cmd {
 724         __u8                    opcode;
 725         __u8                    flags;
 726         __u16                   command_id;
 727         __le32                  nsid;
 728         __u64                   rsvd2[2];
 729         union nvme_data_ptr     dptr;
 730         __le32                  nr;
 731         __le32                  attributes;
 732         __u32                   rsvd12[4];
 733 };
 734
 735 enum {
 736         NVME_DSMGMT_IDR         = 1 << 0,
 737         NVME_DSMGMT_IDW         = 1 << 1,
 738         NVME_DSMGMT_AD          = 1 << 2,
 739 };
 740
 741 #define NVME_DSM_MAX_RANGES     256
 742
 743 struct nvme_dsm_range {
 744         __le32                  cattr;
 745         __le32                  nlb;
 746         __le64                  slba;
 747 };
 748
 749 struct nvme_write_zeroes_cmd {
 750         __u8                    opcode;
 751         __u8                    flags;
 752         __u16                   command_id;
 753         __le32                  nsid;
 754         __u64                   rsvd2;
 755         __le64                  metadata;
 756         union nvme_data_ptr     dptr;
 757         __le64                  slba;
 758         __le16                  length;
 759         __le16                  control;
 760         __le32                  dsmgmt;
 761         __le32                  reftag;
 762         __le16                  apptag;
 763         __le16                  appmask;
 764 };
 765
 766 /* Features */
 767
 768 struct nvme_feat_auto_pst {
 769         __le64 entries[32];
 770 };
 771
 772 enum {
 773         NVME_HOST_MEM_ENABLE    = (1 << 0),
 774         NVME_HOST_MEM_RETURN    = (1 << 1),
 775 };
 776
 777 struct nvme_feat_host_behavior {
 778         __u8 acre;
 779         __u8 resv1[511];
 780 };
 781
 782 enum {
 783         NVME_ENABLE_ACRE        = 1,
 784 };
 785
 786 /* Admin commands */
 787
 788 enum nvme_admin_opcode {
 789         nvme_admin_delete_sq            = 0x00,
 790         nvme_admin_create_sq            = 0x01,
 791         nvme_admin_get_log_page         = 0x02,
 792         nvme_admin_delete_cq            = 0x04,
 793         nvme_admin_create_cq            = 0x05,
 794         nvme_admin_identify             = 0x06,
 795         nvme_admin_abort_cmd            = 0x08,
 796         nvme_admin_set_features         = 0x09,
 797         nvme_admin_get_features         = 0x0a,
 798         nvme_admin_async_event          = 0x0c,
 799         nvme_admin_ns_mgmt              = 0x0d,
 800         nvme_admin_activate_fw          = 0x10,
 801         nvme_admin_download_fw          = 0x11,
 802         nvme_admin_ns_attach            = 0x15,
 803         nvme_admin_keep_alive           = 0x18,
 804         nvme_admin_directive_send       = 0x19,
 805         nvme_admin_directive_recv       = 0x1a,
 806         nvme_admin_dbbuf                = 0x7C,
 807         nvme_admin_format_nvm           = 0x80,
 808         nvme_admin_security_send        = 0x81,
 809         nvme_admin_security_recv        = 0x82,
 810         nvme_admin_sanitize_nvm         = 0x84,
 811 };
 812
 813 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
 814 #define show_admin_opcode_name(val)                                     \
 815         __print_symbolic(val,                                           \
 816                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
 817                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
 818                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
 819                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
 820                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
 821                 nvme_admin_opcode_name(nvme_admin_identify),            \
 822                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
 823                 nvme_admin_opcode_name(nvme_admin_set_features),        \
 824                 nvme_admin_opcode_name(nvme_admin_get_features),        \
 825                 nvme_admin_opcode_name(nvme_admin_async_event),         \
 826                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
 827                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
 828                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
 829                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
 830                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
 831                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
 832                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
 833                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
 834                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
 835                 nvme_admin_opcode_name(nvme_admin_security_send),       \
 836                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
 837                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm))
 838
 839 enum {
 840         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 841         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 842         NVME_SQ_PRIO_URGENT     = (0 << 1),
 843         NVME_SQ_PRIO_HIGH       = (1 << 1),
 844         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 845         NVME_SQ_PRIO_LOW        = (3 << 1),
 846         NVME_FEAT_ARBITRATION   = 0x01,
 847         NVME_FEAT_POWER_MGMT    = 0x02,
 848         NVME_FEAT_LBA_RANGE     = 0x03,
 849         NVME_FEAT_TEMP_THRESH   = 0x04,
 850         NVME_FEAT_ERR_RECOVERY  = 0x05,
 851         NVME_FEAT_VOLATILE_WC   = 0x06,
 852         NVME_FEAT_NUM_QUEUES    = 0x07,
 853         NVME_FEAT_IRQ_COALESCE  = 0x08,
 854         NVME_FEAT_IRQ_CONFIG    = 0x09,
 855         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 856         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 857         NVME_FEAT_AUTO_PST      = 0x0c,
 858         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 859         NVME_FEAT_TIMESTAMP     = 0x0e,
 860         NVME_FEAT_KATO          = 0x0f,
 861         NVME_FEAT_HCTM          = 0x10,
 862         NVME_FEAT_NOPSC         = 0x11,
 863         NVME_FEAT_RRL           = 0x12,
 864         NVME_FEAT_PLM_CONFIG    = 0x13,
 865         NVME_FEAT_PLM_WINDOW    = 0x14,
 866         NVME_FEAT_HOST_BEHAVIOR = 0x16,
 867         NVME_FEAT_SW_PROGRESS   = 0x80,
 868         NVME_FEAT_HOST_ID       = 0x81,
 869         NVME_FEAT_RESV_MASK     = 0x82,
 870         NVME_FEAT_RESV_PERSIST  = 0x83,
 871         NVME_FEAT_WRITE_PROTECT = 0x84,
 872         NVME_LOG_ERROR          = 0x01,
 873         NVME_LOG_SMART          = 0x02,
 874         NVME_LOG_FW_SLOT        = 0x03,
 875         NVME_LOG_CHANGED_NS     = 0x04,
 876         NVME_LOG_CMD_EFFECTS    = 0x05,
 877         NVME_LOG_ANA            = 0x0c,
 878         NVME_LOG_DISC           = 0x70,
 879         NVME_LOG_RESERVATION    = 0x80,
 880         NVME_FWACT_REPL         = (0 << 3),
 881         NVME_FWACT_REPL_ACTV    = (1 << 3),
 882         NVME_FWACT_ACTV         = (2 << 3),
 883 };
 884
 885 /* NVMe Namespace Write Protect State */
 886 enum {
 887         NVME_NS_NO_WRITE_PROTECT = 0,
 888         NVME_NS_WRITE_PROTECT,
 889         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
 890         NVME_NS_WRITE_PROTECT_PERMANENT,
 891 };
 892
 893 #define NVME_MAX_CHANGED_NAMESPACES     1024
 894
 895 struct nvme_identify {
 896         __u8                    opcode;
 897         __u8                    flags;
 898         __u16                   command_id;
 899         __le32                  nsid;
 900         __u64                   rsvd2[2];
 901         union nvme_data_ptr     dptr;
 902         __u8                    cns;
 903         __u8                    rsvd3;
 904         __le16                  ctrlid;
 905         __u32                   rsvd11[5];
 906 };
 907
 908 #define NVME_IDENTIFY_DATA_SIZE 4096
 909
 910 struct nvme_features {
 911         __u8                    opcode;
 912         __u8                    flags;
 913         __u16                   command_id;
 914         __le32                  nsid;
 915         __u64                   rsvd2[2];
 916         union nvme_data_ptr     dptr;
 917         __le32                  fid;
 918         __le32                  dword11;
 919         __le32                  dword12;
 920         __le32                  dword13;
 921         __le32                  dword14;
 922         __le32                  dword15;
 923 };
 924
 925 struct nvme_host_mem_buf_desc {
 926         __le64                  addr;
 927         __le32                  size;
 928         __u32                   rsvd;
 929 };
 930
 931 struct nvme_create_cq {
 932         __u8                    opcode;
 933         __u8                    flags;
 934         __u16                   command_id;
 935         __u32                   rsvd1[5];
 936         __le64                  prp1;
 937         __u64                   rsvd8;
 938         __le16                  cqid;
 939         __le16                  qsize;
 940         __le16                  cq_flags;
 941         __le16                  irq_vector;
 942         __u32                   rsvd12[4];
 943 };
 944
 945 struct nvme_create_sq {
 946         __u8                    opcode;
 947         __u8                    flags;
 948         __u16                   command_id;
 949         __u32                   rsvd1[5];
 950         __le64                  prp1;
 951         __u64                   rsvd8;
 952         __le16                  sqid;
 953         __le16                  qsize;
 954         __le16                  sq_flags;
 955         __le16                  cqid;
 956         __u32                   rsvd12[4];
 957 };
 958
 959 struct nvme_delete_queue {
 960         __u8                    opcode;
 961         __u8                    flags;
 962         __u16                   command_id;
 963         __u32                   rsvd1[9];
 964         __le16                  qid;
 965         __u16                   rsvd10;
 966         __u32                   rsvd11[5];
 967 };
 968
 969 struct nvme_abort_cmd {
 970         __u8                    opcode;
 971         __u8                    flags;
 972         __u16                   command_id;
 973         __u32                   rsvd1[9];
 974         __le16                  sqid;
 975         __u16                   cid;
 976         __u32                   rsvd11[5];
 977 };
 978
 979 struct nvme_download_firmware {
 980         __u8                    opcode;
 981         __u8                    flags;
 982         __u16                   command_id;
 983         __u32                   rsvd1[5];
 984         union nvme_data_ptr     dptr;
 985         __le32                  numd;
 986         __le32                  offset;
 987         __u32                   rsvd12[4];
 988 };
 989
 990 struct nvme_format_cmd {
 991         __u8                    opcode;
 992         __u8                    flags;
 993         __u16                   command_id;
 994         __le32                  nsid;
 995         __u64                   rsvd2[4];
 996         __le32                  cdw10;
 997         __u32                   rsvd11[5];
 998 };
 999
1000 struct nvme_get_log_page_command {
1001         __u8                    opcode;
1002         __u8                    flags;
1003         __u16                   command_id;
1004         __le32                  nsid;
1005         __u64                   rsvd2[2];
1006         union nvme_data_ptr     dptr;
1007         __u8                    lid;
1008         __u8                    lsp; /* upper 4 bits reserved */
1009         __le16                  numdl;
1010         __le16                  numdu;
1011         __u16                   rsvd11;
1012         union {
1013                 struct {
1014                         __le32 lpol;
1015                         __le32 lpou;
1016                 };
1017                 __le64 lpo;
1018         };
1019         __u32                   rsvd14[2];
1020 };
1021
1022 struct nvme_directive_cmd {
1023         __u8                    opcode;
1024         __u8                    flags;
1025         __u16                   command_id;
1026         __le32                  nsid;
1027         __u64                   rsvd2[2];
1028         union nvme_data_ptr     dptr;
1029         __le32                  numd;
1030         __u8                    doper;
1031         __u8                    dtype;
1032         __le16                  dspec;
1033         __u8                    endir;
1034         __u8                    tdtype;
1035         __u16                   rsvd15;
1036
1037         __u32                   rsvd16[3];
1038 };
1039
1040 /*
1041  * Fabrics subcommands.
1042  */
1043 enum nvmf_fabrics_opcode {
1044         nvme_fabrics_command            = 0x7f,
1045 };
1046
1047 enum nvmf_capsule_command {
1048         nvme_fabrics_type_property_set  = 0x00,
1049         nvme_fabrics_type_connect       = 0x01,
1050         nvme_fabrics_type_property_get  = 0x04,
1051 };
1052
1053 #define nvme_fabrics_type_name(type)   { type, #type }
1054 #define show_fabrics_type_name(type)                                    \
1055         __print_symbolic(type,                                          \
1056                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1057                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1058                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1059
1060 /*
1061  * If not fabrics command, fctype will be ignored.
1062  */
1063 #define show_opcode_name(qid, opcode, fctype)                   \
1064         ((opcode) == nvme_fabrics_command ?                     \
1065          show_fabrics_type_name(fctype) :                       \
1066         ((qid) ?                                                \
1067          show_nvm_opcode_name(opcode) :                         \
1068          show_admin_opcode_name(opcode)))
1069
1070 struct nvmf_common_command {
1071         __u8    opcode;
1072         __u8    resv1;
1073         __u16   command_id;
1074         __u8    fctype;
1075         __u8    resv2[35];
1076         __u8    ts[24];
1077 };
1078
1079 /*
1080  * The legal cntlid range a NVMe Target will provide.
1081  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1082  * Devices based on earlier specs did not have the subsystem concept;
1083  * therefore, those devices had their cntlid value set to 0 as a result.
1084  */
1085 #define NVME_CNTLID_MIN         1
1086 #define NVME_CNTLID_MAX         0xffef
1087 #define NVME_CNTLID_DYNAMIC     0xffff
1088
1089 #define MAX_DISC_LOGS   255
1090
1091 /* Discovery log page entry */
1092 struct nvmf_disc_rsp_page_entry {
1093         __u8            trtype;
1094         __u8            adrfam;
1095         __u8            subtype;
1096         __u8            treq;
1097         __le16          portid;
1098         __le16          cntlid;
1099         __le16          asqsz;
1100         __u8            resv8[22];
1101         char            trsvcid[NVMF_TRSVCID_SIZE];
1102         __u8            resv64[192];
1103         char            subnqn[NVMF_NQN_FIELD_LEN];
1104         char            traddr[NVMF_TRADDR_SIZE];
1105         union tsas {
1106                 char            common[NVMF_TSAS_SIZE];
1107                 struct rdma {
1108                         __u8    qptype;
1109                         __u8    prtype;
1110                         __u8    cms;
1111                         __u8    resv3[5];
1112                         __u16   pkey;
1113                         __u8    resv10[246];
1114                 } rdma;
1115         } tsas;
1116 };
1117
1118 /* Discovery log page header */
1119 struct nvmf_disc_rsp_page_hdr {
1120         __le64          genctr;
1121         __le64          numrec;
1122         __le16          recfmt;
1123         __u8            resv14[1006];
1124         struct nvmf_disc_rsp_page_entry entries[0];
1125 };
1126
1127 enum {
1128         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1129 };
1130
1131 struct nvmf_connect_command {
1132         __u8            opcode;
1133         __u8            resv1;
1134         __u16           command_id;
1135         __u8            fctype;
1136         __u8            resv2[19];
1137         union nvme_data_ptr dptr;
1138         __le16          recfmt;
1139         __le16          qid;
1140         __le16          sqsize;
1141         __u8            cattr;
1142         __u8            resv3;
1143         __le32          kato;
1144         __u8            resv4[12];
1145 };
1146
1147 struct nvmf_connect_data {
1148         uuid_t          hostid;
1149         __le16          cntlid;
1150         char            resv4[238];
1151         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1152         char            hostnqn[NVMF_NQN_FIELD_LEN];
1153         char            resv5[256];
1154 };
1155
1156 struct nvmf_property_set_command {
1157         __u8            opcode;
1158         __u8            resv1;
1159         __u16           command_id;
1160         __u8            fctype;
1161         __u8            resv2[35];
1162         __u8            attrib;
1163         __u8            resv3[3];
1164         __le32          offset;
1165         __le64          value;
1166         __u8            resv4[8];
1167 };
1168
1169 struct nvmf_property_get_command {
1170         __u8            opcode;
1171         __u8            resv1;
1172         __u16           command_id;
1173         __u8            fctype;
1174         __u8            resv2[35];
1175         __u8            attrib;
1176         __u8            resv3[3];
1177         __le32          offset;
1178         __u8            resv4[16];
1179 };
1180
1181 struct nvme_dbbuf {
1182         __u8                    opcode;
1183         __u8                    flags;
1184         __u16                   command_id;
1185         __u32                   rsvd1[5];
1186         __le64                  prp1;
1187         __le64                  prp2;
1188         __u32                   rsvd12[6];
1189 };
1190
1191 struct streams_directive_params {
1192         __le16  msl;
1193         __le16  nssa;
1194         __le16  nsso;
1195         __u8    rsvd[10];
1196         __le32  sws;
1197         __le16  sgs;
1198         __le16  nsa;
1199         __le16  nso;
1200         __u8    rsvd2[6];
1201 };
1202
1203 struct nvme_command {
1204         union {
1205                 struct nvme_common_command common;
1206                 struct nvme_rw_command rw;
1207                 struct nvme_identify identify;
1208                 struct nvme_features features;
1209                 struct nvme_create_cq create_cq;
1210                 struct nvme_create_sq create_sq;
1211                 struct nvme_delete_queue delete_queue;
1212                 struct nvme_download_firmware dlfw;
1213                 struct nvme_format_cmd format;
1214                 struct nvme_dsm_cmd dsm;
1215                 struct nvme_write_zeroes_cmd write_zeroes;
1216                 struct nvme_abort_cmd abort;
1217                 struct nvme_get_log_page_command get_log_page;
1218                 struct nvmf_common_command fabrics;
1219                 struct nvmf_connect_command connect;
1220                 struct nvmf_property_set_command prop_set;
1221                 struct nvmf_property_get_command prop_get;
1222                 struct nvme_dbbuf dbbuf;
1223                 struct nvme_directive_cmd directive;
1224         };
1225 };
1226
1227 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1228 {
1229         return cmd->common.opcode == nvme_fabrics_command;
1230 }
1231
1232 struct nvme_error_slot {
1233         __le64          error_count;
1234         __le16          sqid;
1235         __le16          cmdid;
1236         __le16          status_field;
1237         __le16          param_error_location;
1238         __le64          lba;
1239         __le32          nsid;
1240         __u8            vs;
1241         __u8            resv[3];
1242         __le64          cs;
1243         __u8            resv2[24];
1244 };
1245
1246 static inline bool nvme_is_write(struct nvme_command *cmd)
1247 {
1248         /*
1249          * What a mess...
1250          *
1251          * Why can't we simply have a Fabrics In and Fabrics out command?
1252          */
1253         if (unlikely(nvme_is_fabrics(cmd)))
1254                 return cmd->fabrics.fctype & 1;
1255         return cmd->common.opcode & 1;
1256 }
1257
1258 enum {
1259         /*
1260          * Generic Command Status:
1261          */
1262         NVME_SC_SUCCESS                 = 0x0,
1263         NVME_SC_INVALID_OPCODE          = 0x1,
1264         NVME_SC_INVALID_FIELD           = 0x2,
1265         NVME_SC_CMDID_CONFLICT          = 0x3,
1266         NVME_SC_DATA_XFER_ERROR         = 0x4,
1267         NVME_SC_POWER_LOSS              = 0x5,
1268         NVME_SC_INTERNAL                = 0x6,
1269         NVME_SC_ABORT_REQ               = 0x7,
1270         NVME_SC_ABORT_QUEUE             = 0x8,
1271         NVME_SC_FUSED_FAIL              = 0x9,
1272         NVME_SC_FUSED_MISSING           = 0xa,
1273         NVME_SC_INVALID_NS              = 0xb,
1274         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1275         NVME_SC_SGL_INVALID_LAST        = 0xd,
1276         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1277         NVME_SC_SGL_INVALID_DATA        = 0xf,
1278         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1279         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1280
1281         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1282         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1283
1284         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1285
1286         NVME_SC_LBA_RANGE               = 0x80,
1287         NVME_SC_CAP_EXCEEDED            = 0x81,
1288         NVME_SC_NS_NOT_READY            = 0x82,
1289         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1290
1291         /*
1292          * Command Specific Status:
1293          */
1294         NVME_SC_CQ_INVALID              = 0x100,
1295         NVME_SC_QID_INVALID             = 0x101,
1296         NVME_SC_QUEUE_SIZE              = 0x102,
1297         NVME_SC_ABORT_LIMIT             = 0x103,
1298         NVME_SC_ABORT_MISSING           = 0x104,
1299         NVME_SC_ASYNC_LIMIT             = 0x105,
1300         NVME_SC_FIRMWARE_SLOT           = 0x106,
1301         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1302         NVME_SC_INVALID_VECTOR          = 0x108,
1303         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1304         NVME_SC_INVALID_FORMAT          = 0x10a,
1305         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1306         NVME_SC_INVALID_QUEUE           = 0x10c,
1307         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1308         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1309         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1310         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1311         NVME_SC_FW_NEEDS_RESET          = 0x111,
1312         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1313         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1314         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1315         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1316         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1317         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1318         NVME_SC_NS_IS_PRIVATE           = 0x119,
1319         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1320         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1321         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1322
1323         /*
1324          * I/O Command Set Specific - NVM commands:
1325          */
1326         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1327         NVME_SC_INVALID_PI              = 0x181,
1328         NVME_SC_READ_ONLY               = 0x182,
1329         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1330
1331         /*
1332          * I/O Command Set Specific - Fabrics commands:
1333          */
1334         NVME_SC_CONNECT_FORMAT          = 0x180,
1335         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1336         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1337         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1338         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1339
1340         NVME_SC_DISCOVERY_RESTART       = 0x190,
1341         NVME_SC_AUTH_REQUIRED           = 0x191,
1342
1343         /*
1344          * Media and Data Integrity Errors:
1345          */
1346         NVME_SC_WRITE_FAULT             = 0x280,
1347         NVME_SC_READ_ERROR              = 0x281,
1348         NVME_SC_GUARD_CHECK             = 0x282,
1349         NVME_SC_APPTAG_CHECK            = 0x283,
1350         NVME_SC_REFTAG_CHECK            = 0x284,
1351         NVME_SC_COMPARE_FAILED          = 0x285,
1352         NVME_SC_ACCESS_DENIED           = 0x286,
1353         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1354
1355         /*
1356          * Path-related Errors:
1357          */
1358         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1359         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1360         NVME_SC_ANA_TRANSITION          = 0x303,
1361         NVME_SC_HOST_PATH_ERROR         = 0x370,
1362
1363         NVME_SC_CRD                     = 0x1800,
1364         NVME_SC_DNR                     = 0x4000,
1365 };
1366
1367 struct nvme_completion {
1368         /*
1369          * Used by Admin and Fabrics commands to return data:
1370          */
1371         union nvme_result {
1372                 __le16  u16;
1373                 __le32  u32;
1374                 __le64  u64;
1375         } result;
1376         __le16  sq_head;        /* how much of this queue may be reclaimed */
1377         __le16  sq_id;          /* submission queue that generated this entry */
1378         __u16   command_id;     /* of the command which completed */
1379         __le16  status;         /* did the command fail, and if so, why? */
1380 };
1381
1382 #define NVME_VS(major, minor, tertiary) \
1383         (((major) << 16) | ((minor) << 8) | (tertiary))
1384
1385 #define NVME_MAJOR(ver)         ((ver) >> 16)
1386 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1387 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1388
1389 #endif /* _LINUX_NVME_H */