include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/types.h>
  11 #include <linux/uuid.h>
  12
  13 /* NQN names in commands fields specified one size */
  14 #define NVMF_NQN_FIELD_LEN      256
  15
  16 /* However the max length of a qualified name is another size */
  17 #define NVMF_NQN_SIZE           223
  18
  19 #define NVMF_TRSVCID_SIZE       32
  20 #define NVMF_TRADDR_SIZE        256
  21 #define NVMF_TSAS_SIZE          256
  22
  23 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  24
  25 #define NVME_RDMA_IP_PORT       4420
  26
  27 #define NVME_NSID_ALL           0xffffffff
  28
  29 enum nvme_subsys_type {
  30         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  31         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  32 };
  33
  34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  35 enum {
  36         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  37         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  38         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  39         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  40         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  41         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  42         NVMF_ADDR_FAMILY_MAX,
  43 };
  44
  45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  46 enum {
  47         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  48         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  49         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  50         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  51         NVMF_TRTYPE_MAX,
  52 };
  53
  54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  55 enum {
  56         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  57         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  58         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  60         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  61
  62         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  63 };
  64
  65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  66  * RDMA_QPTYPE field
  67  */
  68 enum {
  69         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  70         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  71 };
  72
  73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  74  * RDMA_QPTYPE field
  75  */
  76 enum {
  77         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  78         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  79         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  80         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  81         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  82 };
  83
  84 /* RDMA Connection Management Service Type codes for Discovery Log Page
  85  * entry TSAS RDMA_CMS field
  86  */
  87 enum {
  88         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  89 };
  90
  91 #define NVME_AQ_DEPTH           32
  92 #define NVME_NR_AEN_COMMANDS    1
  93 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  94
  95 /*
  96  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  97  * NVM-Express 1.2 specification, section 4.1.2.
  98  */
  99 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 100
 101 enum {
 102         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 103         NVME_REG_VS     = 0x0008,       /* Version */
 104         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 105         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 106         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 107         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 108         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 109         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 110         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 111         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 112         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 113         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 114         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 115         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 116         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 117                                          * Location
 118                                          */
 119         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 120                                          * Space Control
 121                                          */
 122         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 123         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 124         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 125         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 126                                          * Buffer Size
 127                                          */
 128         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 129                                          * Write Throughput
 130                                          */
 131         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 132 };
 133
 134 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 135 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 136 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 137 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 138 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 139 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 140 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 141 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 142
 143 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 144 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 145
 146 enum {
 147         NVME_CMBSZ_SQS          = 1 << 0,
 148         NVME_CMBSZ_CQS          = 1 << 1,
 149         NVME_CMBSZ_LISTS        = 1 << 2,
 150         NVME_CMBSZ_RDS          = 1 << 3,
 151         NVME_CMBSZ_WDS          = 1 << 4,
 152
 153         NVME_CMBSZ_SZ_SHIFT     = 12,
 154         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 155
 156         NVME_CMBSZ_SZU_SHIFT    = 8,
 157         NVME_CMBSZ_SZU_MASK     = 0xf,
 158 };
 159
 160 /*
 161  * Submission and Completion Queue Entry Sizes for the NVM command set.
 162  * (In bytes and specified as a power of two (2^n)).
 163  */
 164 #define NVME_ADM_SQES       6
 165 #define NVME_NVM_IOSQES         6
 166 #define NVME_NVM_IOCQES         4
 167
 168 enum {
 169         NVME_CC_ENABLE          = 1 << 0,
 170         NVME_CC_EN_SHIFT        = 0,
 171         NVME_CC_CSS_SHIFT       = 4,
 172         NVME_CC_MPS_SHIFT       = 7,
 173         NVME_CC_AMS_SHIFT       = 11,
 174         NVME_CC_SHN_SHIFT       = 14,
 175         NVME_CC_IOSQES_SHIFT    = 16,
 176         NVME_CC_IOCQES_SHIFT    = 20,
 177         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 178         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 179         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 180         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 181         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 182         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 183         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 184         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 185         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 186         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 187         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 188         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 189         NVME_CAP_CSS_NVM        = 1 << 0,
 190         NVME_CAP_CSS_CSI        = 1 << 6,
 191         NVME_CSTS_RDY           = 1 << 0,
 192         NVME_CSTS_CFS           = 1 << 1,
 193         NVME_CSTS_NSSRO         = 1 << 4,
 194         NVME_CSTS_PP            = 1 << 5,
 195         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 196         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 197         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 198         NVME_CSTS_SHST_MASK     = 3 << 2,
 199         NVME_CMBMSC_CRE         = 1 << 0,
 200         NVME_CMBMSC_CMSE        = 1 << 1,
 201 };
 202
 203 struct nvme_id_power_state {
 204         __le16                  max_power;      /* centiwatts */
 205         __u8                    rsvd2;
 206         __u8                    flags;
 207         __le32                  entry_lat;      /* microseconds */
 208         __le32                  exit_lat;       /* microseconds */
 209         __u8                    read_tput;
 210         __u8                    read_lat;
 211         __u8                    write_tput;
 212         __u8                    write_lat;
 213         __le16                  idle_power;
 214         __u8                    idle_scale;
 215         __u8                    rsvd19;
 216         __le16                  active_power;
 217         __u8                    active_work_scale;
 218         __u8                    rsvd23[9];
 219 };
 220
 221 enum {
 222         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 223         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 224 };
 225
 226 enum nvme_ctrl_attr {
 227         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 228         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 229 };
 230
 231 struct nvme_id_ctrl {
 232         __le16                  vid;
 233         __le16                  ssvid;
 234         char                    sn[20];
 235         char                    mn[40];
 236         char                    fr[8];
 237         __u8                    rab;
 238         __u8                    ieee[3];
 239         __u8                    cmic;
 240         __u8                    mdts;
 241         __le16                  cntlid;
 242         __le32                  ver;
 243         __le32                  rtd3r;
 244         __le32                  rtd3e;
 245         __le32                  oaes;
 246         __le32                  ctratt;
 247         __u8                    rsvd100[28];
 248         __le16                  crdt1;
 249         __le16                  crdt2;
 250         __le16                  crdt3;
 251         __u8                    rsvd134[122];
 252         __le16                  oacs;
 253         __u8                    acl;
 254         __u8                    aerl;
 255         __u8                    frmw;
 256         __u8                    lpa;
 257         __u8                    elpe;
 258         __u8                    npss;
 259         __u8                    avscc;
 260         __u8                    apsta;
 261         __le16                  wctemp;
 262         __le16                  cctemp;
 263         __le16                  mtfa;
 264         __le32                  hmpre;
 265         __le32                  hmmin;
 266         __u8                    tnvmcap[16];
 267         __u8                    unvmcap[16];
 268         __le32                  rpmbs;
 269         __le16                  edstt;
 270         __u8                    dsto;
 271         __u8                    fwug;
 272         __le16                  kas;
 273         __le16                  hctma;
 274         __le16                  mntmt;
 275         __le16                  mxtmt;
 276         __le32                  sanicap;
 277         __le32                  hmminds;
 278         __le16                  hmmaxd;
 279         __u8                    rsvd338[4];
 280         __u8                    anatt;
 281         __u8                    anacap;
 282         __le32                  anagrpmax;
 283         __le32                  nanagrpid;
 284         __u8                    rsvd352[160];
 285         __u8                    sqes;
 286         __u8                    cqes;
 287         __le16                  maxcmd;
 288         __le32                  nn;
 289         __le16                  oncs;
 290         __le16                  fuses;
 291         __u8                    fna;
 292         __u8                    vwc;
 293         __le16                  awun;
 294         __le16                  awupf;
 295         __u8                    nvscc;
 296         __u8                    nwpc;
 297         __le16                  acwu;
 298         __u8                    rsvd534[2];
 299         __le32                  sgls;
 300         __le32                  mnan;
 301         __u8                    rsvd544[224];
 302         char                    subnqn[256];
 303         __u8                    rsvd1024[768];
 304         __le32                  ioccsz;
 305         __le32                  iorcsz;
 306         __le16                  icdoff;
 307         __u8                    ctrattr;
 308         __u8                    msdbd;
 309         __u8                    rsvd1804[244];
 310         struct nvme_id_power_state      psd[32];
 311         __u8                    vs[1024];
 312 };
 313
 314 enum {
 315         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 316         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 317         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 318         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 319         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 320         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 321         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 322         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 323         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 324         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 325         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 326         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 327         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 328         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 329         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 330         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 331         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 332         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 333         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 334         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 335         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 336 };
 337
 338 struct nvme_lbaf {
 339         __le16                  ms;
 340         __u8                    ds;
 341         __u8                    rp;
 342 };
 343
 344 struct nvme_id_ns {
 345         __le64                  nsze;
 346         __le64                  ncap;
 347         __le64                  nuse;
 348         __u8                    nsfeat;
 349         __u8                    nlbaf;
 350         __u8                    flbas;
 351         __u8                    mc;
 352         __u8                    dpc;
 353         __u8                    dps;
 354         __u8                    nmic;
 355         __u8                    rescap;
 356         __u8                    fpi;
 357         __u8                    dlfeat;
 358         __le16                  nawun;
 359         __le16                  nawupf;
 360         __le16                  nacwu;
 361         __le16                  nabsn;
 362         __le16                  nabo;
 363         __le16                  nabspf;
 364         __le16                  noiob;
 365         __u8                    nvmcap[16];
 366         __le16                  npwg;
 367         __le16                  npwa;
 368         __le16                  npdg;
 369         __le16                  npda;
 370         __le16                  nows;
 371         __u8                    rsvd74[18];
 372         __le32                  anagrpid;
 373         __u8                    rsvd96[3];
 374         __u8                    nsattr;
 375         __le16                  nvmsetid;
 376         __le16                  endgid;
 377         __u8                    nguid[16];
 378         __u8                    eui64[8];
 379         struct nvme_lbaf        lbaf[16];
 380         __u8                    rsvd192[192];
 381         __u8                    vs[3712];
 382 };
 383
 384 struct nvme_zns_lbafe {
 385         __le64                  zsze;
 386         __u8                    zdes;
 387         __u8                    rsvd9[7];
 388 };
 389
 390 struct nvme_id_ns_zns {
 391         __le16                  zoc;
 392         __le16                  ozcs;
 393         __le32                  mar;
 394         __le32                  mor;
 395         __le32                  rrl;
 396         __le32                  frl;
 397         __u8                    rsvd20[2796];
 398         struct nvme_zns_lbafe   lbafe[16];
 399         __u8                    rsvd3072[768];
 400         __u8                    vs[256];
 401 };
 402
 403 struct nvme_id_ctrl_zns {
 404         __u8    zasl;
 405         __u8    rsvd1[4095];
 406 };
 407
 408 enum {
 409         NVME_ID_CNS_NS                  = 0x00,
 410         NVME_ID_CNS_CTRL                = 0x01,
 411         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 412         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 413         NVME_ID_CNS_CS_NS               = 0x05,
 414         NVME_ID_CNS_CS_CTRL             = 0x06,
 415         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 416         NVME_ID_CNS_NS_PRESENT          = 0x11,
 417         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 418         NVME_ID_CNS_CTRL_LIST           = 0x13,
 419         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 420         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 421         NVME_ID_CNS_UUID_LIST           = 0x17,
 422 };
 423
 424 enum {
 425         NVME_CSI_NVM                    = 0,
 426         NVME_CSI_ZNS                    = 2,
 427 };
 428
 429 enum {
 430         NVME_DIR_IDENTIFY               = 0x00,
 431         NVME_DIR_STREAMS                = 0x01,
 432         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 433         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 434         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 435         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 436         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 437         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 438         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 439         NVME_DIR_ENDIR                  = 0x01,
 440 };
 441
 442 enum {
 443         NVME_NS_FEAT_THIN       = 1 << 0,
 444         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 445         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 446         NVME_NS_ATTR_RO         = 1 << 0,
 447         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 448         NVME_NS_FLBAS_META_EXT  = 0x10,
 449         NVME_NS_NMIC_SHARED     = 1 << 0,
 450         NVME_LBAF_RP_BEST       = 0,
 451         NVME_LBAF_RP_BETTER     = 1,
 452         NVME_LBAF_RP_GOOD       = 2,
 453         NVME_LBAF_RP_DEGRADED   = 3,
 454         NVME_NS_DPC_PI_LAST     = 1 << 4,
 455         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 456         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 457         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 458         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 459         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 460         NVME_NS_DPS_PI_MASK     = 0x7,
 461         NVME_NS_DPS_PI_TYPE1    = 1,
 462         NVME_NS_DPS_PI_TYPE2    = 2,
 463         NVME_NS_DPS_PI_TYPE3    = 3,
 464 };
 465
 466 /* Identify Namespace Metadata Capabilities (MC): */
 467 enum {
 468         NVME_MC_EXTENDED_LBA    = (1 << 0),
 469         NVME_MC_METADATA_PTR    = (1 << 1),
 470 };
 471
 472 struct nvme_ns_id_desc {
 473         __u8 nidt;
 474         __u8 nidl;
 475         __le16 reserved;
 476 };
 477
 478 #define NVME_NIDT_EUI64_LEN     8
 479 #define NVME_NIDT_NGUID_LEN     16
 480 #define NVME_NIDT_UUID_LEN      16
 481 #define NVME_NIDT_CSI_LEN       1
 482
 483 enum {
 484         NVME_NIDT_EUI64         = 0x01,
 485         NVME_NIDT_NGUID         = 0x02,
 486         NVME_NIDT_UUID          = 0x03,
 487         NVME_NIDT_CSI           = 0x04,
 488 };
 489
 490 struct nvme_smart_log {
 491         __u8                    critical_warning;
 492         __u8                    temperature[2];
 493         __u8                    avail_spare;
 494         __u8                    spare_thresh;
 495         __u8                    percent_used;
 496         __u8                    endu_grp_crit_warn_sumry;
 497         __u8                    rsvd7[25];
 498         __u8                    data_units_read[16];
 499         __u8                    data_units_written[16];
 500         __u8                    host_reads[16];
 501         __u8                    host_writes[16];
 502         __u8                    ctrl_busy_time[16];
 503         __u8                    power_cycles[16];
 504         __u8                    power_on_hours[16];
 505         __u8                    unsafe_shutdowns[16];
 506         __u8                    media_errors[16];
 507         __u8                    num_err_log_entries[16];
 508         __le32                  warning_temp_time;
 509         __le32                  critical_comp_time;
 510         __le16                  temp_sensor[8];
 511         __le32                  thm_temp1_trans_count;
 512         __le32                  thm_temp2_trans_count;
 513         __le32                  thm_temp1_total_time;
 514         __le32                  thm_temp2_total_time;
 515         __u8                    rsvd232[280];
 516 };
 517
 518 struct nvme_fw_slot_info_log {
 519         __u8                    afi;
 520         __u8                    rsvd1[7];
 521         __le64                  frs[7];
 522         __u8                    rsvd64[448];
 523 };
 524
 525 enum {
 526         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 527         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 528         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 529         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 530         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 531         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 532         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 533 };
 534
 535 struct nvme_effects_log {
 536         __le32 acs[256];
 537         __le32 iocs[256];
 538         __u8   resv[2048];
 539 };
 540
 541 enum nvme_ana_state {
 542         NVME_ANA_OPTIMIZED              = 0x01,
 543         NVME_ANA_NONOPTIMIZED           = 0x02,
 544         NVME_ANA_INACCESSIBLE           = 0x03,
 545         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 546         NVME_ANA_CHANGE                 = 0x0f,
 547 };
 548
 549 struct nvme_ana_group_desc {
 550         __le32  grpid;
 551         __le32  nnsids;
 552         __le64  chgcnt;
 553         __u8    state;
 554         __u8    rsvd17[15];
 555         __le32  nsids[];
 556 };
 557
 558 /* flag for the log specific field of the ANA log */
 559 #define NVME_ANA_LOG_RGO        (1 << 0)
 560
 561 struct nvme_ana_rsp_hdr {
 562         __le64  chgcnt;
 563         __le16  ngrps;
 564         __le16  rsvd10[3];
 565 };
 566
 567 struct nvme_zone_descriptor {
 568         __u8            zt;
 569         __u8            zs;
 570         __u8            za;
 571         __u8            rsvd3[5];
 572         __le64          zcap;
 573         __le64          zslba;
 574         __le64          wp;
 575         __u8            rsvd32[32];
 576 };
 577
 578 enum {
 579         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 580 };
 581
 582 struct nvme_zone_report {
 583         __le64          nr_zones;
 584         __u8            resv8[56];
 585         struct nvme_zone_descriptor entries[];
 586 };
 587
 588 enum {
 589         NVME_SMART_CRIT_SPARE           = 1 << 0,
 590         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 591         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 592         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 593         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 594 };
 595
 596 enum {
 597         NVME_AER_ERROR                  = 0,
 598         NVME_AER_SMART                  = 1,
 599         NVME_AER_NOTICE                 = 2,
 600         NVME_AER_CSS                    = 6,
 601         NVME_AER_VS                     = 7,
 602 };
 603
 604 enum {
 605         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 606         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 607         NVME_AER_NOTICE_ANA             = 0x03,
 608         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 609 };
 610
 611 enum {
 612         NVME_AEN_BIT_NS_ATTR            = 8,
 613         NVME_AEN_BIT_FW_ACT             = 9,
 614         NVME_AEN_BIT_ANA_CHANGE         = 11,
 615         NVME_AEN_BIT_DISC_CHANGE        = 31,
 616 };
 617
 618 enum {
 619         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 620         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 621         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 622         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 623 };
 624
 625 struct nvme_lba_range_type {
 626         __u8                    type;
 627         __u8                    attributes;
 628         __u8                    rsvd2[14];
 629         __u64                   slba;
 630         __u64                   nlb;
 631         __u8                    guid[16];
 632         __u8                    rsvd48[16];
 633 };
 634
 635 enum {
 636         NVME_LBART_TYPE_FS      = 0x01,
 637         NVME_LBART_TYPE_RAID    = 0x02,
 638         NVME_LBART_TYPE_CACHE   = 0x03,
 639         NVME_LBART_TYPE_SWAP    = 0x04,
 640
 641         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 642         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 643 };
 644
 645 struct nvme_reservation_status {
 646         __le32  gen;
 647         __u8    rtype;
 648         __u8    regctl[2];
 649         __u8    resv5[2];
 650         __u8    ptpls;
 651         __u8    resv10[13];
 652         struct {
 653                 __le16  cntlid;
 654                 __u8    rcsts;
 655                 __u8    resv3[5];
 656                 __le64  hostid;
 657                 __le64  rkey;
 658         } regctl_ds[];
 659 };
 660
 661 enum nvme_async_event_type {
 662         NVME_AER_TYPE_ERROR     = 0,
 663         NVME_AER_TYPE_SMART     = 1,
 664         NVME_AER_TYPE_NOTICE    = 2,
 665 };
 666
 667 /* I/O commands */
 668
 669 enum nvme_opcode {
 670         nvme_cmd_flush          = 0x00,
 671         nvme_cmd_write          = 0x01,
 672         nvme_cmd_read           = 0x02,
 673         nvme_cmd_write_uncor    = 0x04,
 674         nvme_cmd_compare        = 0x05,
 675         nvme_cmd_write_zeroes   = 0x08,
 676         nvme_cmd_dsm            = 0x09,
 677         nvme_cmd_verify         = 0x0c,
 678         nvme_cmd_resv_register  = 0x0d,
 679         nvme_cmd_resv_report    = 0x0e,
 680         nvme_cmd_resv_acquire   = 0x11,
 681         nvme_cmd_resv_release   = 0x15,
 682         nvme_cmd_zone_mgmt_send = 0x79,
 683         nvme_cmd_zone_mgmt_recv = 0x7a,
 684         nvme_cmd_zone_append    = 0x7d,
 685 };
 686
 687 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 688 #define show_nvm_opcode_name(val)                               \
 689         __print_symbolic(val,                                   \
 690                 nvme_opcode_name(nvme_cmd_flush),               \
 691                 nvme_opcode_name(nvme_cmd_write),               \
 692                 nvme_opcode_name(nvme_cmd_read),                \
 693                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 694                 nvme_opcode_name(nvme_cmd_compare),             \
 695                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 696                 nvme_opcode_name(nvme_cmd_dsm),                 \
 697                 nvme_opcode_name(nvme_cmd_resv_register),       \
 698                 nvme_opcode_name(nvme_cmd_resv_report),         \
 699                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 700                 nvme_opcode_name(nvme_cmd_resv_release),        \
 701                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 702                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 703                 nvme_opcode_name(nvme_cmd_zone_append))
 704
 705
 706
 707 /*
 708  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 709  *
 710  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 711  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 712  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 713  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 714  *                            request subtype
 715  */
 716 enum {
 717         NVME_SGL_FMT_ADDRESS            = 0x00,
 718         NVME_SGL_FMT_OFFSET             = 0x01,
 719         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 720         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 721 };
 722
 723 /*
 724  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 725  *
 726  * For struct nvme_sgl_desc:
 727  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 728  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 729  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 730  *
 731  * For struct nvme_keyed_sgl_desc:
 732  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 733  *
 734  * Transport-specific SGL types:
 735  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 736  */
 737 enum {
 738         NVME_SGL_FMT_DATA_DESC          = 0x00,
 739         NVME_SGL_FMT_SEG_DESC           = 0x02,
 740         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 741         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 742         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 743 };
 744
 745 struct nvme_sgl_desc {
 746         __le64  addr;
 747         __le32  length;
 748         __u8    rsvd[3];
 749         __u8    type;
 750 };
 751
 752 struct nvme_keyed_sgl_desc {
 753         __le64  addr;
 754         __u8    length[3];
 755         __u8    key[4];
 756         __u8    type;
 757 };
 758
 759 union nvme_data_ptr {
 760         struct {
 761                 __le64  prp1;
 762                 __le64  prp2;
 763         };
 764         struct nvme_sgl_desc    sgl;
 765         struct nvme_keyed_sgl_desc ksgl;
 766 };
 767
 768 /*
 769  * Lowest two bits of our flags field (FUSE field in the spec):
 770  *
 771  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 772  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 773  *
 774  * Highest two bits in our flags field (PSDT field in the spec):
 775  *
 776  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 777  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 778  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 779  *      If used, MPTR contains an address of an SGL segment containing
 780  *      exactly 1 SGL descriptor (qword aligned).
 781  */
 782 enum {
 783         NVME_CMD_FUSE_FIRST     = (1 << 0),
 784         NVME_CMD_FUSE_SECOND    = (1 << 1),
 785
 786         NVME_CMD_SGL_METABUF    = (1 << 6),
 787         NVME_CMD_SGL_METASEG    = (1 << 7),
 788         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 789 };
 790
 791 struct nvme_common_command {
 792         __u8                    opcode;
 793         __u8                    flags;
 794         __u16                   command_id;
 795         __le32                  nsid;
 796         __le32                  cdw2[2];
 797         __le64                  metadata;
 798         union nvme_data_ptr     dptr;
 799         __le32                  cdw10;
 800         __le32                  cdw11;
 801         __le32                  cdw12;
 802         __le32                  cdw13;
 803         __le32                  cdw14;
 804         __le32                  cdw15;
 805 };
 806
 807 struct nvme_rw_command {
 808         __u8                    opcode;
 809         __u8                    flags;
 810         __u16                   command_id;
 811         __le32                  nsid;
 812         __u64                   rsvd2;
 813         __le64                  metadata;
 814         union nvme_data_ptr     dptr;
 815         __le64                  slba;
 816         __le16                  length;
 817         __le16                  control;
 818         __le32                  dsmgmt;
 819         __le32                  reftag;
 820         __le16                  apptag;
 821         __le16                  appmask;
 822 };
 823
 824 enum {
 825         NVME_RW_LR                      = 1 << 15,
 826         NVME_RW_FUA                     = 1 << 14,
 827         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 828         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 829         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 830         NVME_RW_DSM_FREQ_RARE           = 2,
 831         NVME_RW_DSM_FREQ_READS          = 3,
 832         NVME_RW_DSM_FREQ_WRITES         = 4,
 833         NVME_RW_DSM_FREQ_RW             = 5,
 834         NVME_RW_DSM_FREQ_ONCE           = 6,
 835         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 836         NVME_RW_DSM_FREQ_TEMP           = 8,
 837         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 838         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 839         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 840         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 841         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 842         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 843         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 844         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 845         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 846         NVME_RW_PRINFO_PRACT            = 1 << 13,
 847         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 848 };
 849
 850 struct nvme_dsm_cmd {
 851         __u8                    opcode;
 852         __u8                    flags;
 853         __u16                   command_id;
 854         __le32                  nsid;
 855         __u64                   rsvd2[2];
 856         union nvme_data_ptr     dptr;
 857         __le32                  nr;
 858         __le32                  attributes;
 859         __u32                   rsvd12[4];
 860 };
 861
 862 enum {
 863         NVME_DSMGMT_IDR         = 1 << 0,
 864         NVME_DSMGMT_IDW         = 1 << 1,
 865         NVME_DSMGMT_AD          = 1 << 2,
 866 };
 867
 868 #define NVME_DSM_MAX_RANGES     256
 869
 870 struct nvme_dsm_range {
 871         __le32                  cattr;
 872         __le32                  nlb;
 873         __le64                  slba;
 874 };
 875
 876 struct nvme_write_zeroes_cmd {
 877         __u8                    opcode;
 878         __u8                    flags;
 879         __u16                   command_id;
 880         __le32                  nsid;
 881         __u64                   rsvd2;
 882         __le64                  metadata;
 883         union nvme_data_ptr     dptr;
 884         __le64                  slba;
 885         __le16                  length;
 886         __le16                  control;
 887         __le32                  dsmgmt;
 888         __le32                  reftag;
 889         __le16                  apptag;
 890         __le16                  appmask;
 891 };
 892
 893 enum nvme_zone_mgmt_action {
 894         NVME_ZONE_CLOSE         = 0x1,
 895         NVME_ZONE_FINISH        = 0x2,
 896         NVME_ZONE_OPEN          = 0x3,
 897         NVME_ZONE_RESET         = 0x4,
 898         NVME_ZONE_OFFLINE       = 0x5,
 899         NVME_ZONE_SET_DESC_EXT  = 0x10,
 900 };
 901
 902 struct nvme_zone_mgmt_send_cmd {
 903         __u8                    opcode;
 904         __u8                    flags;
 905         __u16                   command_id;
 906         __le32                  nsid;
 907         __le32                  cdw2[2];
 908         __le64                  metadata;
 909         union nvme_data_ptr     dptr;
 910         __le64                  slba;
 911         __le32                  cdw12;
 912         __u8                    zsa;
 913         __u8                    select_all;
 914         __u8                    rsvd13[2];
 915         __le32                  cdw14[2];
 916 };
 917
 918 struct nvme_zone_mgmt_recv_cmd {
 919         __u8                    opcode;
 920         __u8                    flags;
 921         __u16                   command_id;
 922         __le32                  nsid;
 923         __le64                  rsvd2[2];
 924         union nvme_data_ptr     dptr;
 925         __le64                  slba;
 926         __le32                  numd;
 927         __u8                    zra;
 928         __u8                    zrasf;
 929         __u8                    pr;
 930         __u8                    rsvd13;
 931         __le32                  cdw14[2];
 932 };
 933
 934 enum {
 935         NVME_ZRA_ZONE_REPORT            = 0,
 936         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
 937         NVME_REPORT_ZONE_PARTIAL        = 1,
 938 };
 939
 940 /* Features */
 941
 942 enum {
 943         NVME_TEMP_THRESH_MASK           = 0xffff,
 944         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
 945         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
 946 };
 947
 948 struct nvme_feat_auto_pst {
 949         __le64 entries[32];
 950 };
 951
 952 enum {
 953         NVME_HOST_MEM_ENABLE    = (1 << 0),
 954         NVME_HOST_MEM_RETURN    = (1 << 1),
 955 };
 956
 957 struct nvme_feat_host_behavior {
 958         __u8 acre;
 959         __u8 resv1[511];
 960 };
 961
 962 enum {
 963         NVME_ENABLE_ACRE        = 1,
 964 };
 965
 966 /* Admin commands */
 967
 968 enum nvme_admin_opcode {
 969         nvme_admin_delete_sq            = 0x00,
 970         nvme_admin_create_sq            = 0x01,
 971         nvme_admin_get_log_page         = 0x02,
 972         nvme_admin_delete_cq            = 0x04,
 973         nvme_admin_create_cq            = 0x05,
 974         nvme_admin_identify             = 0x06,
 975         nvme_admin_abort_cmd            = 0x08,
 976         nvme_admin_set_features         = 0x09,
 977         nvme_admin_get_features         = 0x0a,
 978         nvme_admin_async_event          = 0x0c,
 979         nvme_admin_ns_mgmt              = 0x0d,
 980         nvme_admin_activate_fw          = 0x10,
 981         nvme_admin_download_fw          = 0x11,
 982         nvme_admin_dev_self_test        = 0x14,
 983         nvme_admin_ns_attach            = 0x15,
 984         nvme_admin_keep_alive           = 0x18,
 985         nvme_admin_directive_send       = 0x19,
 986         nvme_admin_directive_recv       = 0x1a,
 987         nvme_admin_virtual_mgmt         = 0x1c,
 988         nvme_admin_nvme_mi_send         = 0x1d,
 989         nvme_admin_nvme_mi_recv         = 0x1e,
 990         nvme_admin_dbbuf                = 0x7C,
 991         nvme_admin_format_nvm           = 0x80,
 992         nvme_admin_security_send        = 0x81,
 993         nvme_admin_security_recv        = 0x82,
 994         nvme_admin_sanitize_nvm         = 0x84,
 995         nvme_admin_get_lba_status       = 0x86,
 996         nvme_admin_vendor_start         = 0xC0,
 997 };
 998
 999 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1000 #define show_admin_opcode_name(val)                                     \
1001         __print_symbolic(val,                                           \
1002                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1003                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1004                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1005                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1006                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1007                 nvme_admin_opcode_name(nvme_admin_identify),            \
1008                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1009                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1010                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1011                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1012                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1013                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1014                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1015                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1016                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1017                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1018                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1019                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1020                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1021                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1022                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1023                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1024                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1025
1026 enum {
1027         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1028         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1029         NVME_SQ_PRIO_URGENT     = (0 << 1),
1030         NVME_SQ_PRIO_HIGH       = (1 << 1),
1031         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1032         NVME_SQ_PRIO_LOW        = (3 << 1),
1033         NVME_FEAT_ARBITRATION   = 0x01,
1034         NVME_FEAT_POWER_MGMT    = 0x02,
1035         NVME_FEAT_LBA_RANGE     = 0x03,
1036         NVME_FEAT_TEMP_THRESH   = 0x04,
1037         NVME_FEAT_ERR_RECOVERY  = 0x05,
1038         NVME_FEAT_VOLATILE_WC   = 0x06,
1039         NVME_FEAT_NUM_QUEUES    = 0x07,
1040         NVME_FEAT_IRQ_COALESCE  = 0x08,
1041         NVME_FEAT_IRQ_CONFIG    = 0x09,
1042         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1043         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1044         NVME_FEAT_AUTO_PST      = 0x0c,
1045         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1046         NVME_FEAT_TIMESTAMP     = 0x0e,
1047         NVME_FEAT_KATO          = 0x0f,
1048         NVME_FEAT_HCTM          = 0x10,
1049         NVME_FEAT_NOPSC         = 0x11,
1050         NVME_FEAT_RRL           = 0x12,
1051         NVME_FEAT_PLM_CONFIG    = 0x13,
1052         NVME_FEAT_PLM_WINDOW    = 0x14,
1053         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1054         NVME_FEAT_SANITIZE      = 0x17,
1055         NVME_FEAT_SW_PROGRESS   = 0x80,
1056         NVME_FEAT_HOST_ID       = 0x81,
1057         NVME_FEAT_RESV_MASK     = 0x82,
1058         NVME_FEAT_RESV_PERSIST  = 0x83,
1059         NVME_FEAT_WRITE_PROTECT = 0x84,
1060         NVME_FEAT_VENDOR_START  = 0xC0,
1061         NVME_FEAT_VENDOR_END    = 0xFF,
1062         NVME_LOG_ERROR          = 0x01,
1063         NVME_LOG_SMART          = 0x02,
1064         NVME_LOG_FW_SLOT        = 0x03,
1065         NVME_LOG_CHANGED_NS     = 0x04,
1066         NVME_LOG_CMD_EFFECTS    = 0x05,
1067         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1068         NVME_LOG_TELEMETRY_HOST = 0x07,
1069         NVME_LOG_TELEMETRY_CTRL = 0x08,
1070         NVME_LOG_ENDURANCE_GROUP = 0x09,
1071         NVME_LOG_ANA            = 0x0c,
1072         NVME_LOG_DISC           = 0x70,
1073         NVME_LOG_RESERVATION    = 0x80,
1074         NVME_FWACT_REPL         = (0 << 3),
1075         NVME_FWACT_REPL_ACTV    = (1 << 3),
1076         NVME_FWACT_ACTV         = (2 << 3),
1077 };
1078
1079 /* NVMe Namespace Write Protect State */
1080 enum {
1081         NVME_NS_NO_WRITE_PROTECT = 0,
1082         NVME_NS_WRITE_PROTECT,
1083         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1084         NVME_NS_WRITE_PROTECT_PERMANENT,
1085 };
1086
1087 #define NVME_MAX_CHANGED_NAMESPACES     1024
1088
1089 struct nvme_identify {
1090         __u8                    opcode;
1091         __u8                    flags;
1092         __u16                   command_id;
1093         __le32                  nsid;
1094         __u64                   rsvd2[2];
1095         union nvme_data_ptr     dptr;
1096         __u8                    cns;
1097         __u8                    rsvd3;
1098         __le16                  ctrlid;
1099         __u8                    rsvd11[3];
1100         __u8                    csi;
1101         __u32                   rsvd12[4];
1102 };
1103
1104 #define NVME_IDENTIFY_DATA_SIZE 4096
1105
1106 struct nvme_features {
1107         __u8                    opcode;
1108         __u8                    flags;
1109         __u16                   command_id;
1110         __le32                  nsid;
1111         __u64                   rsvd2[2];
1112         union nvme_data_ptr     dptr;
1113         __le32                  fid;
1114         __le32                  dword11;
1115         __le32                  dword12;
1116         __le32                  dword13;
1117         __le32                  dword14;
1118         __le32                  dword15;
1119 };
1120
1121 struct nvme_host_mem_buf_desc {
1122         __le64                  addr;
1123         __le32                  size;
1124         __u32                   rsvd;
1125 };
1126
1127 struct nvme_create_cq {
1128         __u8                    opcode;
1129         __u8                    flags;
1130         __u16                   command_id;
1131         __u32                   rsvd1[5];
1132         __le64                  prp1;
1133         __u64                   rsvd8;
1134         __le16                  cqid;
1135         __le16                  qsize;
1136         __le16                  cq_flags;
1137         __le16                  irq_vector;
1138         __u32                   rsvd12[4];
1139 };
1140
1141 struct nvme_create_sq {
1142         __u8                    opcode;
1143         __u8                    flags;
1144         __u16                   command_id;
1145         __u32                   rsvd1[5];
1146         __le64                  prp1;
1147         __u64                   rsvd8;
1148         __le16                  sqid;
1149         __le16                  qsize;
1150         __le16                  sq_flags;
1151         __le16                  cqid;
1152         __u32                   rsvd12[4];
1153 };
1154
1155 struct nvme_delete_queue {
1156         __u8                    opcode;
1157         __u8                    flags;
1158         __u16                   command_id;
1159         __u32                   rsvd1[9];
1160         __le16                  qid;
1161         __u16                   rsvd10;
1162         __u32                   rsvd11[5];
1163 };
1164
1165 struct nvme_abort_cmd {
1166         __u8                    opcode;
1167         __u8                    flags;
1168         __u16                   command_id;
1169         __u32                   rsvd1[9];
1170         __le16                  sqid;
1171         __u16                   cid;
1172         __u32                   rsvd11[5];
1173 };
1174
1175 struct nvme_download_firmware {
1176         __u8                    opcode;
1177         __u8                    flags;
1178         __u16                   command_id;
1179         __u32                   rsvd1[5];
1180         union nvme_data_ptr     dptr;
1181         __le32                  numd;
1182         __le32                  offset;
1183         __u32                   rsvd12[4];
1184 };
1185
1186 struct nvme_format_cmd {
1187         __u8                    opcode;
1188         __u8                    flags;
1189         __u16                   command_id;
1190         __le32                  nsid;
1191         __u64                   rsvd2[4];
1192         __le32                  cdw10;
1193         __u32                   rsvd11[5];
1194 };
1195
1196 struct nvme_get_log_page_command {
1197         __u8                    opcode;
1198         __u8                    flags;
1199         __u16                   command_id;
1200         __le32                  nsid;
1201         __u64                   rsvd2[2];
1202         union nvme_data_ptr     dptr;
1203         __u8                    lid;
1204         __u8                    lsp; /* upper 4 bits reserved */
1205         __le16                  numdl;
1206         __le16                  numdu;
1207         __u16                   rsvd11;
1208         union {
1209                 struct {
1210                         __le32 lpol;
1211                         __le32 lpou;
1212                 };
1213                 __le64 lpo;
1214         };
1215         __u8                    rsvd14[3];
1216         __u8                    csi;
1217         __u32                   rsvd15;
1218 };
1219
1220 struct nvme_directive_cmd {
1221         __u8                    opcode;
1222         __u8                    flags;
1223         __u16                   command_id;
1224         __le32                  nsid;
1225         __u64                   rsvd2[2];
1226         union nvme_data_ptr     dptr;
1227         __le32                  numd;
1228         __u8                    doper;
1229         __u8                    dtype;
1230         __le16                  dspec;
1231         __u8                    endir;
1232         __u8                    tdtype;
1233         __u16                   rsvd15;
1234
1235         __u32                   rsvd16[3];
1236 };
1237
1238 /*
1239  * Fabrics subcommands.
1240  */
1241 enum nvmf_fabrics_opcode {
1242         nvme_fabrics_command            = 0x7f,
1243 };
1244
1245 enum nvmf_capsule_command {
1246         nvme_fabrics_type_property_set  = 0x00,
1247         nvme_fabrics_type_connect       = 0x01,
1248         nvme_fabrics_type_property_get  = 0x04,
1249 };
1250
1251 #define nvme_fabrics_type_name(type)   { type, #type }
1252 #define show_fabrics_type_name(type)                                    \
1253         __print_symbolic(type,                                          \
1254                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1255                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1256                 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1257
1258 /*
1259  * If not fabrics command, fctype will be ignored.
1260  */
1261 #define show_opcode_name(qid, opcode, fctype)                   \
1262         ((opcode) == nvme_fabrics_command ?                     \
1263          show_fabrics_type_name(fctype) :                       \
1264         ((qid) ?                                                \
1265          show_nvm_opcode_name(opcode) :                         \
1266          show_admin_opcode_name(opcode)))
1267
1268 struct nvmf_common_command {
1269         __u8    opcode;
1270         __u8    resv1;
1271         __u16   command_id;
1272         __u8    fctype;
1273         __u8    resv2[35];
1274         __u8    ts[24];
1275 };
1276
1277 /*
1278  * The legal cntlid range a NVMe Target will provide.
1279  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1280  * Devices based on earlier specs did not have the subsystem concept;
1281  * therefore, those devices had their cntlid value set to 0 as a result.
1282  */
1283 #define NVME_CNTLID_MIN         1
1284 #define NVME_CNTLID_MAX         0xffef
1285 #define NVME_CNTLID_DYNAMIC     0xffff
1286
1287 #define MAX_DISC_LOGS   255
1288
1289 /* Discovery log page entry */
1290 struct nvmf_disc_rsp_page_entry {
1291         __u8            trtype;
1292         __u8            adrfam;
1293         __u8            subtype;
1294         __u8            treq;
1295         __le16          portid;
1296         __le16          cntlid;
1297         __le16          asqsz;
1298         __u8            resv8[22];
1299         char            trsvcid[NVMF_TRSVCID_SIZE];
1300         __u8            resv64[192];
1301         char            subnqn[NVMF_NQN_FIELD_LEN];
1302         char            traddr[NVMF_TRADDR_SIZE];
1303         union tsas {
1304                 char            common[NVMF_TSAS_SIZE];
1305                 struct rdma {
1306                         __u8    qptype;
1307                         __u8    prtype;
1308                         __u8    cms;
1309                         __u8    resv3[5];
1310                         __u16   pkey;
1311                         __u8    resv10[246];
1312                 } rdma;
1313         } tsas;
1314 };
1315
1316 /* Discovery log page header */
1317 struct nvmf_disc_rsp_page_hdr {
1318         __le64          genctr;
1319         __le64          numrec;
1320         __le16          recfmt;
1321         __u8            resv14[1006];
1322         struct nvmf_disc_rsp_page_entry entries[];
1323 };
1324
1325 enum {
1326         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1327 };
1328
1329 struct nvmf_connect_command {
1330         __u8            opcode;
1331         __u8            resv1;
1332         __u16           command_id;
1333         __u8            fctype;
1334         __u8            resv2[19];
1335         union nvme_data_ptr dptr;
1336         __le16          recfmt;
1337         __le16          qid;
1338         __le16          sqsize;
1339         __u8            cattr;
1340         __u8            resv3;
1341         __le32          kato;
1342         __u8            resv4[12];
1343 };
1344
1345 struct nvmf_connect_data {
1346         uuid_t          hostid;
1347         __le16          cntlid;
1348         char            resv4[238];
1349         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1350         char            hostnqn[NVMF_NQN_FIELD_LEN];
1351         char            resv5[256];
1352 };
1353
1354 struct nvmf_property_set_command {
1355         __u8            opcode;
1356         __u8            resv1;
1357         __u16           command_id;
1358         __u8            fctype;
1359         __u8            resv2[35];
1360         __u8            attrib;
1361         __u8            resv3[3];
1362         __le32          offset;
1363         __le64          value;
1364         __u8            resv4[8];
1365 };
1366
1367 struct nvmf_property_get_command {
1368         __u8            opcode;
1369         __u8            resv1;
1370         __u16           command_id;
1371         __u8            fctype;
1372         __u8            resv2[35];
1373         __u8            attrib;
1374         __u8            resv3[3];
1375         __le32          offset;
1376         __u8            resv4[16];
1377 };
1378
1379 struct nvme_dbbuf {
1380         __u8                    opcode;
1381         __u8                    flags;
1382         __u16                   command_id;
1383         __u32                   rsvd1[5];
1384         __le64                  prp1;
1385         __le64                  prp2;
1386         __u32                   rsvd12[6];
1387 };
1388
1389 struct streams_directive_params {
1390         __le16  msl;
1391         __le16  nssa;
1392         __le16  nsso;
1393         __u8    rsvd[10];
1394         __le32  sws;
1395         __le16  sgs;
1396         __le16  nsa;
1397         __le16  nso;
1398         __u8    rsvd2[6];
1399 };
1400
1401 struct nvme_command {
1402         union {
1403                 struct nvme_common_command common;
1404                 struct nvme_rw_command rw;
1405                 struct nvme_identify identify;
1406                 struct nvme_features features;
1407                 struct nvme_create_cq create_cq;
1408                 struct nvme_create_sq create_sq;
1409                 struct nvme_delete_queue delete_queue;
1410                 struct nvme_download_firmware dlfw;
1411                 struct nvme_format_cmd format;
1412                 struct nvme_dsm_cmd dsm;
1413                 struct nvme_write_zeroes_cmd write_zeroes;
1414                 struct nvme_zone_mgmt_send_cmd zms;
1415                 struct nvme_zone_mgmt_recv_cmd zmr;
1416                 struct nvme_abort_cmd abort;
1417                 struct nvme_get_log_page_command get_log_page;
1418                 struct nvmf_common_command fabrics;
1419                 struct nvmf_connect_command connect;
1420                 struct nvmf_property_set_command prop_set;
1421                 struct nvmf_property_get_command prop_get;
1422                 struct nvme_dbbuf dbbuf;
1423                 struct nvme_directive_cmd directive;
1424         };
1425 };
1426
1427 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1428 {
1429         return cmd->common.opcode == nvme_fabrics_command;
1430 }
1431
1432 struct nvme_error_slot {
1433         __le64          error_count;
1434         __le16          sqid;
1435         __le16          cmdid;
1436         __le16          status_field;
1437         __le16          param_error_location;
1438         __le64          lba;
1439         __le32          nsid;
1440         __u8            vs;
1441         __u8            resv[3];
1442         __le64          cs;
1443         __u8            resv2[24];
1444 };
1445
1446 static inline bool nvme_is_write(struct nvme_command *cmd)
1447 {
1448         /*
1449          * What a mess...
1450          *
1451          * Why can't we simply have a Fabrics In and Fabrics out command?
1452          */
1453         if (unlikely(nvme_is_fabrics(cmd)))
1454                 return cmd->fabrics.fctype & 1;
1455         return cmd->common.opcode & 1;
1456 }
1457
1458 enum {
1459         /*
1460          * Generic Command Status:
1461          */
1462         NVME_SC_SUCCESS                 = 0x0,
1463         NVME_SC_INVALID_OPCODE          = 0x1,
1464         NVME_SC_INVALID_FIELD           = 0x2,
1465         NVME_SC_CMDID_CONFLICT          = 0x3,
1466         NVME_SC_DATA_XFER_ERROR         = 0x4,
1467         NVME_SC_POWER_LOSS              = 0x5,
1468         NVME_SC_INTERNAL                = 0x6,
1469         NVME_SC_ABORT_REQ               = 0x7,
1470         NVME_SC_ABORT_QUEUE             = 0x8,
1471         NVME_SC_FUSED_FAIL              = 0x9,
1472         NVME_SC_FUSED_MISSING           = 0xa,
1473         NVME_SC_INVALID_NS              = 0xb,
1474         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1475         NVME_SC_SGL_INVALID_LAST        = 0xd,
1476         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1477         NVME_SC_SGL_INVALID_DATA        = 0xf,
1478         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1479         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1480         NVME_SC_CMB_INVALID_USE         = 0x12,
1481         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1482         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1483         NVME_SC_OP_DENIED               = 0x15,
1484         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1485         NVME_SC_RESERVED                = 0x17,
1486         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1487         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1488         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1489         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1490         NVME_SC_SANITIZE_FAILED         = 0x1C,
1491         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1492         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1493         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1494         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1495         NVME_SC_CMD_INTERRUPTED         = 0x21,
1496         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1497
1498         NVME_SC_LBA_RANGE               = 0x80,
1499         NVME_SC_CAP_EXCEEDED            = 0x81,
1500         NVME_SC_NS_NOT_READY            = 0x82,
1501         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1502         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1503
1504         /*
1505          * Command Specific Status:
1506          */
1507         NVME_SC_CQ_INVALID              = 0x100,
1508         NVME_SC_QID_INVALID             = 0x101,
1509         NVME_SC_QUEUE_SIZE              = 0x102,
1510         NVME_SC_ABORT_LIMIT             = 0x103,
1511         NVME_SC_ABORT_MISSING           = 0x104,
1512         NVME_SC_ASYNC_LIMIT             = 0x105,
1513         NVME_SC_FIRMWARE_SLOT           = 0x106,
1514         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1515         NVME_SC_INVALID_VECTOR          = 0x108,
1516         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1517         NVME_SC_INVALID_FORMAT          = 0x10a,
1518         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1519         NVME_SC_INVALID_QUEUE           = 0x10c,
1520         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1521         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1522         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1523         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1524         NVME_SC_FW_NEEDS_RESET          = 0x111,
1525         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1526         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1527         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1528         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1529         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1530         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1531         NVME_SC_NS_IS_PRIVATE           = 0x119,
1532         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1533         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1534         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1535         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1536         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1537         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1538         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1539         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1540         NVME_SC_RES_ID_INVALID          = 0x122,
1541         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1542         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1543         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1544
1545         /*
1546          * I/O Command Set Specific - NVM commands:
1547          */
1548         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1549         NVME_SC_INVALID_PI              = 0x181,
1550         NVME_SC_READ_ONLY               = 0x182,
1551         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1552
1553         /*
1554          * I/O Command Set Specific - Fabrics commands:
1555          */
1556         NVME_SC_CONNECT_FORMAT          = 0x180,
1557         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1558         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1559         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1560         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1561
1562         NVME_SC_DISCOVERY_RESTART       = 0x190,
1563         NVME_SC_AUTH_REQUIRED           = 0x191,
1564
1565         /*
1566          * I/O Command Set Specific - Zoned commands:
1567          */
1568         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1569         NVME_SC_ZONE_FULL               = 0x1b9,
1570         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1571         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1572         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1573         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1574         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1575         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1576
1577         /*
1578          * Media and Data Integrity Errors:
1579          */
1580         NVME_SC_WRITE_FAULT             = 0x280,
1581         NVME_SC_READ_ERROR              = 0x281,
1582         NVME_SC_GUARD_CHECK             = 0x282,
1583         NVME_SC_APPTAG_CHECK            = 0x283,
1584         NVME_SC_REFTAG_CHECK            = 0x284,
1585         NVME_SC_COMPARE_FAILED          = 0x285,
1586         NVME_SC_ACCESS_DENIED           = 0x286,
1587         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1588
1589         /*
1590          * Path-related Errors:
1591          */
1592         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1593         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1594         NVME_SC_ANA_TRANSITION          = 0x303,
1595         NVME_SC_HOST_PATH_ERROR         = 0x370,
1596         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1597
1598         NVME_SC_CRD                     = 0x1800,
1599         NVME_SC_DNR                     = 0x4000,
1600 };
1601
1602 struct nvme_completion {
1603         /*
1604          * Used by Admin and Fabrics commands to return data:
1605          */
1606         union nvme_result {
1607                 __le16  u16;
1608                 __le32  u32;
1609                 __le64  u64;
1610         } result;
1611         __le16  sq_head;        /* how much of this queue may be reclaimed */
1612         __le16  sq_id;          /* submission queue that generated this entry */
1613         __u16   command_id;     /* of the command which completed */
1614         __le16  status;         /* did the command fail, and if so, why? */
1615 };
1616
1617 #define NVME_VS(major, minor, tertiary) \
1618         (((major) << 16) | ((minor) << 8) | (tertiary))
1619
1620 #define NVME_MAJOR(ver)         ((ver) >> 16)
1621 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1622 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1623
1624 #endif /* _LINUX_NVME_H */