1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
10 #include <linux/types.h>
11 #include <linux/uuid.h>
13 /* NQN names in commands fields specified one size */
14 #define NVMF_NQN_FIELD_LEN 256
16 /* However the max length of a qualified name is another size */
17 #define NVMF_NQN_SIZE 223
19 #define NVMF_TRSVCID_SIZE 32
20 #define NVMF_TRADDR_SIZE 256
21 #define NVMF_TSAS_SIZE 256
23 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
25 #define NVME_RDMA_IP_PORT 4420
27 #define NVME_NSID_ALL 0xffffffff
29 enum nvme_subsys_type {
30 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
31 NVME_NQN_NVME = 2, /* NVME type target subsystem */
34 /* Address Family codes for Discovery Log Page entry ADRFAM field */
36 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
37 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
38 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
39 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
40 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
41 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
45 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
47 NVMF_TRTYPE_RDMA = 1, /* RDMA */
48 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
49 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
50 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
54 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
56 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
57 NVMF_TREQ_REQUIRED = 1, /* Required */
58 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
59 #define NVME_TREQ_SECURE_CHANNEL_MASK \
60 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
62 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
65 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
69 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
70 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
73 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
77 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
78 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
79 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
80 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
81 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
84 /* RDMA Connection Management Service Type codes for Discovery Log Page
85 * entry TSAS RDMA_CMS field
88 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
91 #define NVME_AQ_DEPTH 32
92 #define NVME_NR_AEN_COMMANDS 1
93 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
96 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
97 * NVM-Express 1.2 specification, section 4.1.2.
99 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
102 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
103 NVME_REG_VS = 0x0008, /* Version */
104 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
105 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
106 NVME_REG_CC = 0x0014, /* Controller Configuration */
107 NVME_REG_CSTS = 0x001c, /* Controller Status */
108 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
109 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
110 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
111 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
112 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
113 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
114 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
115 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
116 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
119 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
120 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
121 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
122 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
125 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
128 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
131 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
132 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
133 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
134 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
135 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
136 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
138 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
139 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
142 NVME_CMBSZ_SQS = 1 << 0,
143 NVME_CMBSZ_CQS = 1 << 1,
144 NVME_CMBSZ_LISTS = 1 << 2,
145 NVME_CMBSZ_RDS = 1 << 3,
146 NVME_CMBSZ_WDS = 1 << 4,
148 NVME_CMBSZ_SZ_SHIFT = 12,
149 NVME_CMBSZ_SZ_MASK = 0xfffff,
151 NVME_CMBSZ_SZU_SHIFT = 8,
152 NVME_CMBSZ_SZU_MASK = 0xf,
156 * Submission and Completion Queue Entry Sizes for the NVM command set.
157 * (In bytes and specified as a power of two (2^n)).
159 #define NVME_ADM_SQES 6
160 #define NVME_NVM_IOSQES 6
161 #define NVME_NVM_IOCQES 4
164 NVME_CC_ENABLE = 1 << 0,
165 NVME_CC_CSS_NVM = 0 << 4,
166 NVME_CC_EN_SHIFT = 0,
167 NVME_CC_CSS_SHIFT = 4,
168 NVME_CC_MPS_SHIFT = 7,
169 NVME_CC_AMS_SHIFT = 11,
170 NVME_CC_SHN_SHIFT = 14,
171 NVME_CC_IOSQES_SHIFT = 16,
172 NVME_CC_IOCQES_SHIFT = 20,
173 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
174 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
175 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
176 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
177 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
178 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
179 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
180 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
181 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
182 NVME_CSTS_RDY = 1 << 0,
183 NVME_CSTS_CFS = 1 << 1,
184 NVME_CSTS_NSSRO = 1 << 4,
185 NVME_CSTS_PP = 1 << 5,
186 NVME_CSTS_SHST_NORMAL = 0 << 2,
187 NVME_CSTS_SHST_OCCUR = 1 << 2,
188 NVME_CSTS_SHST_CMPLT = 2 << 2,
189 NVME_CSTS_SHST_MASK = 3 << 2,
192 struct nvme_id_power_state {
193 __le16 max_power; /* centiwatts */
196 __le32 entry_lat; /* microseconds */
197 __le32 exit_lat; /* microseconds */
206 __u8 active_work_scale;
211 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
212 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
215 enum nvme_ctrl_attr {
216 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
217 NVME_CTRL_ATTR_TBKAS = (1 << 6),
220 struct nvme_id_ctrl {
299 struct nvme_id_power_state psd[32];
304 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
305 NVME_CTRL_CMIC_ANA = 1 << 3,
306 NVME_CTRL_ONCS_COMPARE = 1 << 0,
307 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
308 NVME_CTRL_ONCS_DSM = 1 << 2,
309 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
310 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
311 NVME_CTRL_VWC_PRESENT = 1 << 0,
312 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
313 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
314 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
315 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
316 NVME_CTRL_CTRATT_128_ID = 1 << 0,
317 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
318 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
319 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
320 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
321 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
322 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
323 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
367 struct nvme_lbaf lbaf[16];
373 NVME_ID_CNS_NS = 0x00,
374 NVME_ID_CNS_CTRL = 0x01,
375 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
376 NVME_ID_CNS_NS_DESC_LIST = 0x03,
377 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
378 NVME_ID_CNS_NS_PRESENT = 0x11,
379 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
380 NVME_ID_CNS_CTRL_LIST = 0x13,
381 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
382 NVME_ID_CNS_NS_GRANULARITY = 0x16,
383 NVME_ID_CNS_UUID_LIST = 0x17,
387 NVME_DIR_IDENTIFY = 0x00,
388 NVME_DIR_STREAMS = 0x01,
389 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
390 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
391 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
392 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
393 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
394 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
395 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
396 NVME_DIR_ENDIR = 0x01,
400 NVME_NS_FEAT_THIN = 1 << 0,
401 NVME_NS_FEAT_ATOMICS = 1 << 1,
402 NVME_NS_FEAT_IO_OPT = 1 << 4,
403 NVME_NS_ATTR_RO = 1 << 0,
404 NVME_NS_FLBAS_LBA_MASK = 0xf,
405 NVME_NS_FLBAS_META_EXT = 0x10,
406 NVME_NS_NMIC_SHARED = 1 << 0,
407 NVME_LBAF_RP_BEST = 0,
408 NVME_LBAF_RP_BETTER = 1,
409 NVME_LBAF_RP_GOOD = 2,
410 NVME_LBAF_RP_DEGRADED = 3,
411 NVME_NS_DPC_PI_LAST = 1 << 4,
412 NVME_NS_DPC_PI_FIRST = 1 << 3,
413 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
414 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
415 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
416 NVME_NS_DPS_PI_FIRST = 1 << 3,
417 NVME_NS_DPS_PI_MASK = 0x7,
418 NVME_NS_DPS_PI_TYPE1 = 1,
419 NVME_NS_DPS_PI_TYPE2 = 2,
420 NVME_NS_DPS_PI_TYPE3 = 3,
423 /* Identify Namespace Metadata Capabilities (MC): */
425 NVME_MC_EXTENDED_LBA = (1 << 0),
426 NVME_MC_METADATA_PTR = (1 << 1),
429 struct nvme_ns_id_desc {
435 #define NVME_NIDT_EUI64_LEN 8
436 #define NVME_NIDT_NGUID_LEN 16
437 #define NVME_NIDT_UUID_LEN 16
440 NVME_NIDT_EUI64 = 0x01,
441 NVME_NIDT_NGUID = 0x02,
442 NVME_NIDT_UUID = 0x03,
445 struct nvme_smart_log {
446 __u8 critical_warning;
451 __u8 endu_grp_crit_warn_sumry;
453 __u8 data_units_read[16];
454 __u8 data_units_written[16];
456 __u8 host_writes[16];
457 __u8 ctrl_busy_time[16];
458 __u8 power_cycles[16];
459 __u8 power_on_hours[16];
460 __u8 unsafe_shutdowns[16];
461 __u8 media_errors[16];
462 __u8 num_err_log_entries[16];
463 __le32 warning_temp_time;
464 __le32 critical_comp_time;
465 __le16 temp_sensor[8];
466 __le32 thm_temp1_trans_count;
467 __le32 thm_temp2_trans_count;
468 __le32 thm_temp1_total_time;
469 __le32 thm_temp2_total_time;
473 struct nvme_fw_slot_info_log {
481 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
482 NVME_CMD_EFFECTS_LBCC = 1 << 1,
483 NVME_CMD_EFFECTS_NCC = 1 << 2,
484 NVME_CMD_EFFECTS_NIC = 1 << 3,
485 NVME_CMD_EFFECTS_CCC = 1 << 4,
486 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
487 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
490 struct nvme_effects_log {
496 enum nvme_ana_state {
497 NVME_ANA_OPTIMIZED = 0x01,
498 NVME_ANA_NONOPTIMIZED = 0x02,
499 NVME_ANA_INACCESSIBLE = 0x03,
500 NVME_ANA_PERSISTENT_LOSS = 0x04,
501 NVME_ANA_CHANGE = 0x0f,
504 struct nvme_ana_group_desc {
513 /* flag for the log specific field of the ANA log */
514 #define NVME_ANA_LOG_RGO (1 << 0)
516 struct nvme_ana_rsp_hdr {
523 NVME_SMART_CRIT_SPARE = 1 << 0,
524 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
525 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
526 NVME_SMART_CRIT_MEDIA = 1 << 3,
527 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
539 NVME_AER_NOTICE_NS_CHANGED = 0x00,
540 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
541 NVME_AER_NOTICE_ANA = 0x03,
542 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
546 NVME_AEN_BIT_NS_ATTR = 8,
547 NVME_AEN_BIT_FW_ACT = 9,
548 NVME_AEN_BIT_ANA_CHANGE = 11,
549 NVME_AEN_BIT_DISC_CHANGE = 31,
553 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
554 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
555 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
556 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
559 struct nvme_lba_range_type {
570 NVME_LBART_TYPE_FS = 0x01,
571 NVME_LBART_TYPE_RAID = 0x02,
572 NVME_LBART_TYPE_CACHE = 0x03,
573 NVME_LBART_TYPE_SWAP = 0x04,
575 NVME_LBART_ATTRIB_TEMP = 1 << 0,
576 NVME_LBART_ATTRIB_HIDE = 1 << 1,
579 struct nvme_reservation_status {
595 enum nvme_async_event_type {
596 NVME_AER_TYPE_ERROR = 0,
597 NVME_AER_TYPE_SMART = 1,
598 NVME_AER_TYPE_NOTICE = 2,
604 nvme_cmd_flush = 0x00,
605 nvme_cmd_write = 0x01,
606 nvme_cmd_read = 0x02,
607 nvme_cmd_write_uncor = 0x04,
608 nvme_cmd_compare = 0x05,
609 nvme_cmd_write_zeroes = 0x08,
611 nvme_cmd_verify = 0x0c,
612 nvme_cmd_resv_register = 0x0d,
613 nvme_cmd_resv_report = 0x0e,
614 nvme_cmd_resv_acquire = 0x11,
615 nvme_cmd_resv_release = 0x15,
618 #define nvme_opcode_name(opcode) { opcode, #opcode }
619 #define show_nvm_opcode_name(val) \
620 __print_symbolic(val, \
621 nvme_opcode_name(nvme_cmd_flush), \
622 nvme_opcode_name(nvme_cmd_write), \
623 nvme_opcode_name(nvme_cmd_read), \
624 nvme_opcode_name(nvme_cmd_write_uncor), \
625 nvme_opcode_name(nvme_cmd_compare), \
626 nvme_opcode_name(nvme_cmd_write_zeroes), \
627 nvme_opcode_name(nvme_cmd_dsm), \
628 nvme_opcode_name(nvme_cmd_resv_register), \
629 nvme_opcode_name(nvme_cmd_resv_report), \
630 nvme_opcode_name(nvme_cmd_resv_acquire), \
631 nvme_opcode_name(nvme_cmd_resv_release))
635 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
637 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
638 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
639 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
640 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
644 NVME_SGL_FMT_ADDRESS = 0x00,
645 NVME_SGL_FMT_OFFSET = 0x01,
646 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
647 NVME_SGL_FMT_INVALIDATE = 0x0f,
651 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
653 * For struct nvme_sgl_desc:
654 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
655 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
656 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
658 * For struct nvme_keyed_sgl_desc:
659 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
661 * Transport-specific SGL types:
662 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
665 NVME_SGL_FMT_DATA_DESC = 0x00,
666 NVME_SGL_FMT_SEG_DESC = 0x02,
667 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
668 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
669 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
672 struct nvme_sgl_desc {
679 struct nvme_keyed_sgl_desc {
686 union nvme_data_ptr {
691 struct nvme_sgl_desc sgl;
692 struct nvme_keyed_sgl_desc ksgl;
696 * Lowest two bits of our flags field (FUSE field in the spec):
698 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
699 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
701 * Highest two bits in our flags field (PSDT field in the spec):
703 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
704 * If used, MPTR contains addr of single physical buffer (byte aligned).
705 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
706 * If used, MPTR contains an address of an SGL segment containing
707 * exactly 1 SGL descriptor (qword aligned).
710 NVME_CMD_FUSE_FIRST = (1 << 0),
711 NVME_CMD_FUSE_SECOND = (1 << 1),
713 NVME_CMD_SGL_METABUF = (1 << 6),
714 NVME_CMD_SGL_METASEG = (1 << 7),
715 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
718 struct nvme_common_command {
725 union nvme_data_ptr dptr;
734 struct nvme_rw_command {
741 union nvme_data_ptr dptr;
752 NVME_RW_LR = 1 << 15,
753 NVME_RW_FUA = 1 << 14,
754 NVME_RW_DSM_FREQ_UNSPEC = 0,
755 NVME_RW_DSM_FREQ_TYPICAL = 1,
756 NVME_RW_DSM_FREQ_RARE = 2,
757 NVME_RW_DSM_FREQ_READS = 3,
758 NVME_RW_DSM_FREQ_WRITES = 4,
759 NVME_RW_DSM_FREQ_RW = 5,
760 NVME_RW_DSM_FREQ_ONCE = 6,
761 NVME_RW_DSM_FREQ_PREFETCH = 7,
762 NVME_RW_DSM_FREQ_TEMP = 8,
763 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
764 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
765 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
766 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
767 NVME_RW_DSM_SEQ_REQ = 1 << 6,
768 NVME_RW_DSM_COMPRESSED = 1 << 7,
769 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
770 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
771 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
772 NVME_RW_PRINFO_PRACT = 1 << 13,
773 NVME_RW_DTYPE_STREAMS = 1 << 4,
776 struct nvme_dsm_cmd {
782 union nvme_data_ptr dptr;
789 NVME_DSMGMT_IDR = 1 << 0,
790 NVME_DSMGMT_IDW = 1 << 1,
791 NVME_DSMGMT_AD = 1 << 2,
794 #define NVME_DSM_MAX_RANGES 256
796 struct nvme_dsm_range {
802 struct nvme_write_zeroes_cmd {
809 union nvme_data_ptr dptr;
822 NVME_TEMP_THRESH_MASK = 0xffff,
823 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
824 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
827 struct nvme_feat_auto_pst {
832 NVME_HOST_MEM_ENABLE = (1 << 0),
833 NVME_HOST_MEM_RETURN = (1 << 1),
836 struct nvme_feat_host_behavior {
842 NVME_ENABLE_ACRE = 1,
847 enum nvme_admin_opcode {
848 nvme_admin_delete_sq = 0x00,
849 nvme_admin_create_sq = 0x01,
850 nvme_admin_get_log_page = 0x02,
851 nvme_admin_delete_cq = 0x04,
852 nvme_admin_create_cq = 0x05,
853 nvme_admin_identify = 0x06,
854 nvme_admin_abort_cmd = 0x08,
855 nvme_admin_set_features = 0x09,
856 nvme_admin_get_features = 0x0a,
857 nvme_admin_async_event = 0x0c,
858 nvme_admin_ns_mgmt = 0x0d,
859 nvme_admin_activate_fw = 0x10,
860 nvme_admin_download_fw = 0x11,
861 nvme_admin_dev_self_test = 0x14,
862 nvme_admin_ns_attach = 0x15,
863 nvme_admin_keep_alive = 0x18,
864 nvme_admin_directive_send = 0x19,
865 nvme_admin_directive_recv = 0x1a,
866 nvme_admin_virtual_mgmt = 0x1c,
867 nvme_admin_nvme_mi_send = 0x1d,
868 nvme_admin_nvme_mi_recv = 0x1e,
869 nvme_admin_dbbuf = 0x7C,
870 nvme_admin_format_nvm = 0x80,
871 nvme_admin_security_send = 0x81,
872 nvme_admin_security_recv = 0x82,
873 nvme_admin_sanitize_nvm = 0x84,
874 nvme_admin_get_lba_status = 0x86,
877 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
878 #define show_admin_opcode_name(val) \
879 __print_symbolic(val, \
880 nvme_admin_opcode_name(nvme_admin_delete_sq), \
881 nvme_admin_opcode_name(nvme_admin_create_sq), \
882 nvme_admin_opcode_name(nvme_admin_get_log_page), \
883 nvme_admin_opcode_name(nvme_admin_delete_cq), \
884 nvme_admin_opcode_name(nvme_admin_create_cq), \
885 nvme_admin_opcode_name(nvme_admin_identify), \
886 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
887 nvme_admin_opcode_name(nvme_admin_set_features), \
888 nvme_admin_opcode_name(nvme_admin_get_features), \
889 nvme_admin_opcode_name(nvme_admin_async_event), \
890 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
891 nvme_admin_opcode_name(nvme_admin_activate_fw), \
892 nvme_admin_opcode_name(nvme_admin_download_fw), \
893 nvme_admin_opcode_name(nvme_admin_ns_attach), \
894 nvme_admin_opcode_name(nvme_admin_keep_alive), \
895 nvme_admin_opcode_name(nvme_admin_directive_send), \
896 nvme_admin_opcode_name(nvme_admin_directive_recv), \
897 nvme_admin_opcode_name(nvme_admin_dbbuf), \
898 nvme_admin_opcode_name(nvme_admin_format_nvm), \
899 nvme_admin_opcode_name(nvme_admin_security_send), \
900 nvme_admin_opcode_name(nvme_admin_security_recv), \
901 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
902 nvme_admin_opcode_name(nvme_admin_get_lba_status))
905 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
906 NVME_CQ_IRQ_ENABLED = (1 << 1),
907 NVME_SQ_PRIO_URGENT = (0 << 1),
908 NVME_SQ_PRIO_HIGH = (1 << 1),
909 NVME_SQ_PRIO_MEDIUM = (2 << 1),
910 NVME_SQ_PRIO_LOW = (3 << 1),
911 NVME_FEAT_ARBITRATION = 0x01,
912 NVME_FEAT_POWER_MGMT = 0x02,
913 NVME_FEAT_LBA_RANGE = 0x03,
914 NVME_FEAT_TEMP_THRESH = 0x04,
915 NVME_FEAT_ERR_RECOVERY = 0x05,
916 NVME_FEAT_VOLATILE_WC = 0x06,
917 NVME_FEAT_NUM_QUEUES = 0x07,
918 NVME_FEAT_IRQ_COALESCE = 0x08,
919 NVME_FEAT_IRQ_CONFIG = 0x09,
920 NVME_FEAT_WRITE_ATOMIC = 0x0a,
921 NVME_FEAT_ASYNC_EVENT = 0x0b,
922 NVME_FEAT_AUTO_PST = 0x0c,
923 NVME_FEAT_HOST_MEM_BUF = 0x0d,
924 NVME_FEAT_TIMESTAMP = 0x0e,
925 NVME_FEAT_KATO = 0x0f,
926 NVME_FEAT_HCTM = 0x10,
927 NVME_FEAT_NOPSC = 0x11,
928 NVME_FEAT_RRL = 0x12,
929 NVME_FEAT_PLM_CONFIG = 0x13,
930 NVME_FEAT_PLM_WINDOW = 0x14,
931 NVME_FEAT_HOST_BEHAVIOR = 0x16,
932 NVME_FEAT_SANITIZE = 0x17,
933 NVME_FEAT_SW_PROGRESS = 0x80,
934 NVME_FEAT_HOST_ID = 0x81,
935 NVME_FEAT_RESV_MASK = 0x82,
936 NVME_FEAT_RESV_PERSIST = 0x83,
937 NVME_FEAT_WRITE_PROTECT = 0x84,
938 NVME_LOG_ERROR = 0x01,
939 NVME_LOG_SMART = 0x02,
940 NVME_LOG_FW_SLOT = 0x03,
941 NVME_LOG_CHANGED_NS = 0x04,
942 NVME_LOG_CMD_EFFECTS = 0x05,
943 NVME_LOG_DEVICE_SELF_TEST = 0x06,
944 NVME_LOG_TELEMETRY_HOST = 0x07,
945 NVME_LOG_TELEMETRY_CTRL = 0x08,
946 NVME_LOG_ENDURANCE_GROUP = 0x09,
948 NVME_LOG_DISC = 0x70,
949 NVME_LOG_RESERVATION = 0x80,
950 NVME_FWACT_REPL = (0 << 3),
951 NVME_FWACT_REPL_ACTV = (1 << 3),
952 NVME_FWACT_ACTV = (2 << 3),
955 /* NVMe Namespace Write Protect State */
957 NVME_NS_NO_WRITE_PROTECT = 0,
958 NVME_NS_WRITE_PROTECT,
959 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
960 NVME_NS_WRITE_PROTECT_PERMANENT,
963 #define NVME_MAX_CHANGED_NAMESPACES 1024
965 struct nvme_identify {
971 union nvme_data_ptr dptr;
978 #define NVME_IDENTIFY_DATA_SIZE 4096
980 struct nvme_features {
986 union nvme_data_ptr dptr;
995 struct nvme_host_mem_buf_desc {
1001 struct nvme_create_cq {
1015 struct nvme_create_sq {
1029 struct nvme_delete_queue {
1039 struct nvme_abort_cmd {
1049 struct nvme_download_firmware {
1054 union nvme_data_ptr dptr;
1060 struct nvme_format_cmd {
1070 struct nvme_get_log_page_command {
1076 union nvme_data_ptr dptr;
1078 __u8 lsp; /* upper 4 bits reserved */
1092 struct nvme_directive_cmd {
1098 union nvme_data_ptr dptr;
1111 * Fabrics subcommands.
1113 enum nvmf_fabrics_opcode {
1114 nvme_fabrics_command = 0x7f,
1117 enum nvmf_capsule_command {
1118 nvme_fabrics_type_property_set = 0x00,
1119 nvme_fabrics_type_connect = 0x01,
1120 nvme_fabrics_type_property_get = 0x04,
1123 #define nvme_fabrics_type_name(type) { type, #type }
1124 #define show_fabrics_type_name(type) \
1125 __print_symbolic(type, \
1126 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1127 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1128 nvme_fabrics_type_name(nvme_fabrics_type_property_get))
1131 * If not fabrics command, fctype will be ignored.
1133 #define show_opcode_name(qid, opcode, fctype) \
1134 ((opcode) == nvme_fabrics_command ? \
1135 show_fabrics_type_name(fctype) : \
1137 show_nvm_opcode_name(opcode) : \
1138 show_admin_opcode_name(opcode)))
1140 struct nvmf_common_command {
1150 * The legal cntlid range a NVMe Target will provide.
1151 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1152 * Devices based on earlier specs did not have the subsystem concept;
1153 * therefore, those devices had their cntlid value set to 0 as a result.
1155 #define NVME_CNTLID_MIN 1
1156 #define NVME_CNTLID_MAX 0xffef
1157 #define NVME_CNTLID_DYNAMIC 0xffff
1159 #define MAX_DISC_LOGS 255
1161 /* Discovery log page entry */
1162 struct nvmf_disc_rsp_page_entry {
1171 char trsvcid[NVMF_TRSVCID_SIZE];
1173 char subnqn[NVMF_NQN_FIELD_LEN];
1174 char traddr[NVMF_TRADDR_SIZE];
1176 char common[NVMF_TSAS_SIZE];
1188 /* Discovery log page header */
1189 struct nvmf_disc_rsp_page_hdr {
1194 struct nvmf_disc_rsp_page_entry entries[];
1198 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1201 struct nvmf_connect_command {
1207 union nvme_data_ptr dptr;
1217 struct nvmf_connect_data {
1221 char subsysnqn[NVMF_NQN_FIELD_LEN];
1222 char hostnqn[NVMF_NQN_FIELD_LEN];
1226 struct nvmf_property_set_command {
1239 struct nvmf_property_get_command {
1261 struct streams_directive_params {
1273 struct nvme_command {
1275 struct nvme_common_command common;
1276 struct nvme_rw_command rw;
1277 struct nvme_identify identify;
1278 struct nvme_features features;
1279 struct nvme_create_cq create_cq;
1280 struct nvme_create_sq create_sq;
1281 struct nvme_delete_queue delete_queue;
1282 struct nvme_download_firmware dlfw;
1283 struct nvme_format_cmd format;
1284 struct nvme_dsm_cmd dsm;
1285 struct nvme_write_zeroes_cmd write_zeroes;
1286 struct nvme_abort_cmd abort;
1287 struct nvme_get_log_page_command get_log_page;
1288 struct nvmf_common_command fabrics;
1289 struct nvmf_connect_command connect;
1290 struct nvmf_property_set_command prop_set;
1291 struct nvmf_property_get_command prop_get;
1292 struct nvme_dbbuf dbbuf;
1293 struct nvme_directive_cmd directive;
1297 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1299 return cmd->common.opcode == nvme_fabrics_command;
1302 struct nvme_error_slot {
1306 __le16 status_field;
1307 __le16 param_error_location;
1316 static inline bool nvme_is_write(struct nvme_command *cmd)
1321 * Why can't we simply have a Fabrics In and Fabrics out command?
1323 if (unlikely(nvme_is_fabrics(cmd)))
1324 return cmd->fabrics.fctype & 1;
1325 return cmd->common.opcode & 1;
1330 * Generic Command Status:
1332 NVME_SC_SUCCESS = 0x0,
1333 NVME_SC_INVALID_OPCODE = 0x1,
1334 NVME_SC_INVALID_FIELD = 0x2,
1335 NVME_SC_CMDID_CONFLICT = 0x3,
1336 NVME_SC_DATA_XFER_ERROR = 0x4,
1337 NVME_SC_POWER_LOSS = 0x5,
1338 NVME_SC_INTERNAL = 0x6,
1339 NVME_SC_ABORT_REQ = 0x7,
1340 NVME_SC_ABORT_QUEUE = 0x8,
1341 NVME_SC_FUSED_FAIL = 0x9,
1342 NVME_SC_FUSED_MISSING = 0xa,
1343 NVME_SC_INVALID_NS = 0xb,
1344 NVME_SC_CMD_SEQ_ERROR = 0xc,
1345 NVME_SC_SGL_INVALID_LAST = 0xd,
1346 NVME_SC_SGL_INVALID_COUNT = 0xe,
1347 NVME_SC_SGL_INVALID_DATA = 0xf,
1348 NVME_SC_SGL_INVALID_METADATA = 0x10,
1349 NVME_SC_SGL_INVALID_TYPE = 0x11,
1351 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1352 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1354 NVME_SC_SANITIZE_FAILED = 0x1C,
1355 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1357 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1358 NVME_SC_CMD_INTERRUPTED = 0x21,
1360 NVME_SC_LBA_RANGE = 0x80,
1361 NVME_SC_CAP_EXCEEDED = 0x81,
1362 NVME_SC_NS_NOT_READY = 0x82,
1363 NVME_SC_RESERVATION_CONFLICT = 0x83,
1366 * Command Specific Status:
1368 NVME_SC_CQ_INVALID = 0x100,
1369 NVME_SC_QID_INVALID = 0x101,
1370 NVME_SC_QUEUE_SIZE = 0x102,
1371 NVME_SC_ABORT_LIMIT = 0x103,
1372 NVME_SC_ABORT_MISSING = 0x104,
1373 NVME_SC_ASYNC_LIMIT = 0x105,
1374 NVME_SC_FIRMWARE_SLOT = 0x106,
1375 NVME_SC_FIRMWARE_IMAGE = 0x107,
1376 NVME_SC_INVALID_VECTOR = 0x108,
1377 NVME_SC_INVALID_LOG_PAGE = 0x109,
1378 NVME_SC_INVALID_FORMAT = 0x10a,
1379 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1380 NVME_SC_INVALID_QUEUE = 0x10c,
1381 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1382 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1383 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1384 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1385 NVME_SC_FW_NEEDS_RESET = 0x111,
1386 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1387 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1388 NVME_SC_OVERLAPPING_RANGE = 0x114,
1389 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1390 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1391 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1392 NVME_SC_NS_IS_PRIVATE = 0x119,
1393 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1394 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1395 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1396 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1397 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1400 * I/O Command Set Specific - NVM commands:
1402 NVME_SC_BAD_ATTRIBUTES = 0x180,
1403 NVME_SC_INVALID_PI = 0x181,
1404 NVME_SC_READ_ONLY = 0x182,
1405 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1408 * I/O Command Set Specific - Fabrics commands:
1410 NVME_SC_CONNECT_FORMAT = 0x180,
1411 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1412 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1413 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1414 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1416 NVME_SC_DISCOVERY_RESTART = 0x190,
1417 NVME_SC_AUTH_REQUIRED = 0x191,
1420 * Media and Data Integrity Errors:
1422 NVME_SC_WRITE_FAULT = 0x280,
1423 NVME_SC_READ_ERROR = 0x281,
1424 NVME_SC_GUARD_CHECK = 0x282,
1425 NVME_SC_APPTAG_CHECK = 0x283,
1426 NVME_SC_REFTAG_CHECK = 0x284,
1427 NVME_SC_COMPARE_FAILED = 0x285,
1428 NVME_SC_ACCESS_DENIED = 0x286,
1429 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1432 * Path-related Errors:
1434 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1435 NVME_SC_ANA_INACCESSIBLE = 0x302,
1436 NVME_SC_ANA_TRANSITION = 0x303,
1437 NVME_SC_HOST_PATH_ERROR = 0x370,
1438 NVME_SC_HOST_ABORTED_CMD = 0x371,
1440 NVME_SC_CRD = 0x1800,
1441 NVME_SC_DNR = 0x4000,
1444 struct nvme_completion {
1446 * Used by Admin and Fabrics commands to return data:
1453 __le16 sq_head; /* how much of this queue may be reclaimed */
1454 __le16 sq_id; /* submission queue that generated this entry */
1455 __u16 command_id; /* of the command which completed */
1456 __le16 status; /* did the command fail, and if so, why? */
1459 #define NVME_VS(major, minor, tertiary) \
1460 (((major) << 16) | ((minor) << 8) | (tertiary))
1462 #define NVME_MAJOR(ver) ((ver) >> 16)
1463 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1464 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1466 #endif /* _LINUX_NVME_H */