include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _LINUX_NVME_H
  16 #define _LINUX_NVME_H
  17
  18 #include <linux/types.h>
  19 #include <linux/uuid.h>
  20
  21 /* NQN names in commands fields specified one size */
  22 #define NVMF_NQN_FIELD_LEN      256
  23
  24 /* However the max length of a qualified name is another size */
  25 #define NVMF_NQN_SIZE           223
  26
  27 #define NVMF_TRSVCID_SIZE       32
  28 #define NVMF_TRADDR_SIZE        256
  29 #define NVMF_TSAS_SIZE          256
  30
  31 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  32
  33 #define NVME_RDMA_IP_PORT       4420
  34
  35 #define NVME_NSID_ALL           0xffffffff
  36
  37 enum nvme_subsys_type {
  38         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  39         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  40 };
  41
  42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  43 enum {
  44         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  45         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  46         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  47         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  48         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  49 };
  50
  51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  52 enum {
  53         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  54         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  55         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  56         NVMF_TRTYPE_MAX,
  57 };
  58
  59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  60 enum {
  61         NVMF_TREQ_NOT_SPECIFIED = 0,    /* Not specified */
  62         NVMF_TREQ_REQUIRED      = 1,    /* Required */
  63         NVMF_TREQ_NOT_REQUIRED  = 2,    /* Not Required */
  64 };
  65
  66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  67  * RDMA_QPTYPE field
  68  */
  69 enum {
  70         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  71         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  72 };
  73
  74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  75  * RDMA_QPTYPE field
  76  */
  77 enum {
  78         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  79         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
  80         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
  81         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
  82         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
  83 };
  84
  85 /* RDMA Connection Management Service Type codes for Discovery Log Page
  86  * entry TSAS RDMA_CMS field
  87  */
  88 enum {
  89         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
  90 };
  91
  92 #define NVME_AQ_DEPTH           32
  93 #define NVME_NR_AEN_COMMANDS    1
  94 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
  95
  96 /*
  97  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
  98  * NVM-Express 1.2 specification, section 4.1.2.
  99  */
 100 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 101
 102 enum {
 103         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 104         NVME_REG_VS     = 0x0008,       /* Version */
 105         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 106         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 107         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 108         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 109         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 110         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 111         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 112         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 113         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 114         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 115         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 116 };
 117
 118 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 119 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 120 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 121 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 122 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 123 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 124
 125 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 126 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 127
 128 enum {
 129         NVME_CMBSZ_SQS          = 1 << 0,
 130         NVME_CMBSZ_CQS          = 1 << 1,
 131         NVME_CMBSZ_LISTS        = 1 << 2,
 132         NVME_CMBSZ_RDS          = 1 << 3,
 133         NVME_CMBSZ_WDS          = 1 << 4,
 134
 135         NVME_CMBSZ_SZ_SHIFT     = 12,
 136         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 137
 138         NVME_CMBSZ_SZU_SHIFT    = 8,
 139         NVME_CMBSZ_SZU_MASK     = 0xf,
 140 };
 141
 142 /*
 143  * Submission and Completion Queue Entry Sizes for the NVM command set.
 144  * (In bytes and specified as a power of two (2^n)).
 145  */
 146 #define NVME_NVM_IOSQES         6
 147 #define NVME_NVM_IOCQES         4
 148
 149 enum {
 150         NVME_CC_ENABLE          = 1 << 0,
 151         NVME_CC_CSS_NVM         = 0 << 4,
 152         NVME_CC_EN_SHIFT        = 0,
 153         NVME_CC_CSS_SHIFT       = 4,
 154         NVME_CC_MPS_SHIFT       = 7,
 155         NVME_CC_AMS_SHIFT       = 11,
 156         NVME_CC_SHN_SHIFT       = 14,
 157         NVME_CC_IOSQES_SHIFT    = 16,
 158         NVME_CC_IOCQES_SHIFT    = 20,
 159         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 160         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 161         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 162         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 163         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 164         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 165         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 166         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 167         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 168         NVME_CSTS_RDY           = 1 << 0,
 169         NVME_CSTS_CFS           = 1 << 1,
 170         NVME_CSTS_NSSRO         = 1 << 4,
 171         NVME_CSTS_PP            = 1 << 5,
 172         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 173         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 174         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 175         NVME_CSTS_SHST_MASK     = 3 << 2,
 176 };
 177
 178 struct nvme_id_power_state {
 179         __le16                  max_power;      /* centiwatts */
 180         __u8                    rsvd2;
 181         __u8                    flags;
 182         __le32                  entry_lat;      /* microseconds */
 183         __le32                  exit_lat;       /* microseconds */
 184         __u8                    read_tput;
 185         __u8                    read_lat;
 186         __u8                    write_tput;
 187         __u8                    write_lat;
 188         __le16                  idle_power;
 189         __u8                    idle_scale;
 190         __u8                    rsvd19;
 191         __le16                  active_power;
 192         __u8                    active_work_scale;
 193         __u8                    rsvd23[9];
 194 };
 195
 196 enum {
 197         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 198         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 199 };
 200
 201 struct nvme_id_ctrl {
 202         __le16                  vid;
 203         __le16                  ssvid;
 204         char                    sn[20];
 205         char                    mn[40];
 206         char                    fr[8];
 207         __u8                    rab;
 208         __u8                    ieee[3];
 209         __u8                    cmic;
 210         __u8                    mdts;
 211         __le16                  cntlid;
 212         __le32                  ver;
 213         __le32                  rtd3r;
 214         __le32                  rtd3e;
 215         __le32                  oaes;
 216         __le32                  ctratt;
 217         __u8                    rsvd100[156];
 218         __le16                  oacs;
 219         __u8                    acl;
 220         __u8                    aerl;
 221         __u8                    frmw;
 222         __u8                    lpa;
 223         __u8                    elpe;
 224         __u8                    npss;
 225         __u8                    avscc;
 226         __u8                    apsta;
 227         __le16                  wctemp;
 228         __le16                  cctemp;
 229         __le16                  mtfa;
 230         __le32                  hmpre;
 231         __le32                  hmmin;
 232         __u8                    tnvmcap[16];
 233         __u8                    unvmcap[16];
 234         __le32                  rpmbs;
 235         __le16                  edstt;
 236         __u8                    dsto;
 237         __u8                    fwug;
 238         __le16                  kas;
 239         __le16                  hctma;
 240         __le16                  mntmt;
 241         __le16                  mxtmt;
 242         __le32                  sanicap;
 243         __le32                  hmminds;
 244         __le16                  hmmaxd;
 245         __u8                    rsvd338[174];
 246         __u8                    sqes;
 247         __u8                    cqes;
 248         __le16                  maxcmd;
 249         __le32                  nn;
 250         __le16                  oncs;
 251         __le16                  fuses;
 252         __u8                    fna;
 253         __u8                    vwc;
 254         __le16                  awun;
 255         __le16                  awupf;
 256         __u8                    nvscc;
 257         __u8                    rsvd531;
 258         __le16                  acwu;
 259         __u8                    rsvd534[2];
 260         __le32                  sgls;
 261         __u8                    rsvd540[228];
 262         char                    subnqn[256];
 263         __u8                    rsvd1024[768];
 264         __le32                  ioccsz;
 265         __le32                  iorcsz;
 266         __le16                  icdoff;
 267         __u8                    ctrattr;
 268         __u8                    msdbd;
 269         __u8                    rsvd1804[244];
 270         struct nvme_id_power_state      psd[32];
 271         __u8                    vs[1024];
 272 };
 273
 274 enum {
 275         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 276         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 277         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 278         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 279         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 280         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 281         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 282         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 283         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 284         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 285 };
 286
 287 struct nvme_lbaf {
 288         __le16                  ms;
 289         __u8                    ds;
 290         __u8                    rp;
 291 };
 292
 293 struct nvme_id_ns {
 294         __le64                  nsze;
 295         __le64                  ncap;
 296         __le64                  nuse;
 297         __u8                    nsfeat;
 298         __u8                    nlbaf;
 299         __u8                    flbas;
 300         __u8                    mc;
 301         __u8                    dpc;
 302         __u8                    dps;
 303         __u8                    nmic;
 304         __u8                    rescap;
 305         __u8                    fpi;
 306         __u8                    rsvd33;
 307         __le16                  nawun;
 308         __le16                  nawupf;
 309         __le16                  nacwu;
 310         __le16                  nabsn;
 311         __le16                  nabo;
 312         __le16                  nabspf;
 313         __le16                  noiob;
 314         __u8                    nvmcap[16];
 315         __u8                    rsvd64[40];
 316         __u8                    nguid[16];
 317         __u8                    eui64[8];
 318         struct nvme_lbaf        lbaf[16];
 319         __u8                    rsvd192[192];
 320         __u8                    vs[3712];
 321 };
 322
 323 enum {
 324         NVME_ID_CNS_NS                  = 0x00,
 325         NVME_ID_CNS_CTRL                = 0x01,
 326         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 327         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 328         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 329         NVME_ID_CNS_NS_PRESENT          = 0x11,
 330         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 331         NVME_ID_CNS_CTRL_LIST           = 0x13,
 332 };
 333
 334 enum {
 335         NVME_DIR_IDENTIFY               = 0x00,
 336         NVME_DIR_STREAMS                = 0x01,
 337         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 338         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 339         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 340         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 341         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 342         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 343         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 344         NVME_DIR_ENDIR                  = 0x01,
 345 };
 346
 347 enum {
 348         NVME_NS_FEAT_THIN       = 1 << 0,
 349         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 350         NVME_NS_FLBAS_META_EXT  = 0x10,
 351         NVME_LBAF_RP_BEST       = 0,
 352         NVME_LBAF_RP_BETTER     = 1,
 353         NVME_LBAF_RP_GOOD       = 2,
 354         NVME_LBAF_RP_DEGRADED   = 3,
 355         NVME_NS_DPC_PI_LAST     = 1 << 4,
 356         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 357         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 358         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 359         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 360         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 361         NVME_NS_DPS_PI_MASK     = 0x7,
 362         NVME_NS_DPS_PI_TYPE1    = 1,
 363         NVME_NS_DPS_PI_TYPE2    = 2,
 364         NVME_NS_DPS_PI_TYPE3    = 3,
 365 };
 366
 367 struct nvme_ns_id_desc {
 368         __u8 nidt;
 369         __u8 nidl;
 370         __le16 reserved;
 371 };
 372
 373 #define NVME_NIDT_EUI64_LEN     8
 374 #define NVME_NIDT_NGUID_LEN     16
 375 #define NVME_NIDT_UUID_LEN      16
 376
 377 enum {
 378         NVME_NIDT_EUI64         = 0x01,
 379         NVME_NIDT_NGUID         = 0x02,
 380         NVME_NIDT_UUID          = 0x03,
 381 };
 382
 383 struct nvme_smart_log {
 384         __u8                    critical_warning;
 385         __u8                    temperature[2];
 386         __u8                    avail_spare;
 387         __u8                    spare_thresh;
 388         __u8                    percent_used;
 389         __u8                    rsvd6[26];
 390         __u8                    data_units_read[16];
 391         __u8                    data_units_written[16];
 392         __u8                    host_reads[16];
 393         __u8                    host_writes[16];
 394         __u8                    ctrl_busy_time[16];
 395         __u8                    power_cycles[16];
 396         __u8                    power_on_hours[16];
 397         __u8                    unsafe_shutdowns[16];
 398         __u8                    media_errors[16];
 399         __u8                    num_err_log_entries[16];
 400         __le32                  warning_temp_time;
 401         __le32                  critical_comp_time;
 402         __le16                  temp_sensor[8];
 403         __u8                    rsvd216[296];
 404 };
 405
 406 struct nvme_fw_slot_info_log {
 407         __u8                    afi;
 408         __u8                    rsvd1[7];
 409         __le64                  frs[7];
 410         __u8                    rsvd64[448];
 411 };
 412
 413 enum {
 414         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 415         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 416         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 417         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 418         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 419         NVME_CMD_EFFECTS_CSE_MASK       = 3 << 16,
 420 };
 421
 422 struct nvme_effects_log {
 423         __le32 acs[256];
 424         __le32 iocs[256];
 425         __u8   resv[2048];
 426 };
 427
 428 enum {
 429         NVME_SMART_CRIT_SPARE           = 1 << 0,
 430         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 431         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 432         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 433         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 434 };
 435
 436 enum {
 437         NVME_AER_ERROR                  = 0,
 438         NVME_AER_SMART                  = 1,
 439         NVME_AER_NOTICE                 = 2,
 440         NVME_AER_CSS                    = 6,
 441         NVME_AER_VS                     = 7,
 442 };
 443
 444 enum {
 445         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 446         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 447 };
 448
 449 enum {
 450         NVME_AEN_CFG_NS_ATTR            = 1 << 8,
 451         NVME_AEN_CFG_FW_ACT             = 1 << 9,
 452 };
 453
 454 struct nvme_lba_range_type {
 455         __u8                    type;
 456         __u8                    attributes;
 457         __u8                    rsvd2[14];
 458         __u64                   slba;
 459         __u64                   nlb;
 460         __u8                    guid[16];
 461         __u8                    rsvd48[16];
 462 };
 463
 464 enum {
 465         NVME_LBART_TYPE_FS      = 0x01,
 466         NVME_LBART_TYPE_RAID    = 0x02,
 467         NVME_LBART_TYPE_CACHE   = 0x03,
 468         NVME_LBART_TYPE_SWAP    = 0x04,
 469
 470         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 471         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 472 };
 473
 474 struct nvme_reservation_status {
 475         __le32  gen;
 476         __u8    rtype;
 477         __u8    regctl[2];
 478         __u8    resv5[2];
 479         __u8    ptpls;
 480         __u8    resv10[13];
 481         struct {
 482                 __le16  cntlid;
 483                 __u8    rcsts;
 484                 __u8    resv3[5];
 485                 __le64  hostid;
 486                 __le64  rkey;
 487         } regctl_ds[];
 488 };
 489
 490 enum nvme_async_event_type {
 491         NVME_AER_TYPE_ERROR     = 0,
 492         NVME_AER_TYPE_SMART     = 1,
 493         NVME_AER_TYPE_NOTICE    = 2,
 494 };
 495
 496 /* I/O commands */
 497
 498 enum nvme_opcode {
 499         nvme_cmd_flush          = 0x00,
 500         nvme_cmd_write          = 0x01,
 501         nvme_cmd_read           = 0x02,
 502         nvme_cmd_write_uncor    = 0x04,
 503         nvme_cmd_compare        = 0x05,
 504         nvme_cmd_write_zeroes   = 0x08,
 505         nvme_cmd_dsm            = 0x09,
 506         nvme_cmd_resv_register  = 0x0d,
 507         nvme_cmd_resv_report    = 0x0e,
 508         nvme_cmd_resv_acquire   = 0x11,
 509         nvme_cmd_resv_release   = 0x15,
 510 };
 511
 512 /*
 513  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 514  *
 515  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 516  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 517  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 518  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 519  *                            request subtype
 520  */
 521 enum {
 522         NVME_SGL_FMT_ADDRESS            = 0x00,
 523         NVME_SGL_FMT_OFFSET             = 0x01,
 524         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 525         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 526 };
 527
 528 /*
 529  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 530  *
 531  * For struct nvme_sgl_desc:
 532  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 533  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 534  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 535  *
 536  * For struct nvme_keyed_sgl_desc:
 537  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 538  *
 539  * Transport-specific SGL types:
 540  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 541  */
 542 enum {
 543         NVME_SGL_FMT_DATA_DESC          = 0x00,
 544         NVME_SGL_FMT_SEG_DESC           = 0x02,
 545         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 546         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 547         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 548 };
 549
 550 struct nvme_sgl_desc {
 551         __le64  addr;
 552         __le32  length;
 553         __u8    rsvd[3];
 554         __u8    type;
 555 };
 556
 557 struct nvme_keyed_sgl_desc {
 558         __le64  addr;
 559         __u8    length[3];
 560         __u8    key[4];
 561         __u8    type;
 562 };
 563
 564 union nvme_data_ptr {
 565         struct {
 566                 __le64  prp1;
 567                 __le64  prp2;
 568         };
 569         struct nvme_sgl_desc    sgl;
 570         struct nvme_keyed_sgl_desc ksgl;
 571 };
 572
 573 /*
 574  * Lowest two bits of our flags field (FUSE field in the spec):
 575  *
 576  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 577  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 578  *
 579  * Highest two bits in our flags field (PSDT field in the spec):
 580  *
 581  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 582  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 583  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 584  *      If used, MPTR contains an address of an SGL segment containing
 585  *      exactly 1 SGL descriptor (qword aligned).
 586  */
 587 enum {
 588         NVME_CMD_FUSE_FIRST     = (1 << 0),
 589         NVME_CMD_FUSE_SECOND    = (1 << 1),
 590
 591         NVME_CMD_SGL_METABUF    = (1 << 6),
 592         NVME_CMD_SGL_METASEG    = (1 << 7),
 593         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 594 };
 595
 596 struct nvme_common_command {
 597         __u8                    opcode;
 598         __u8                    flags;
 599         __u16                   command_id;
 600         __le32                  nsid;
 601         __le32                  cdw2[2];
 602         __le64                  metadata;
 603         union nvme_data_ptr     dptr;
 604         __le32                  cdw10[6];
 605 };
 606
 607 struct nvme_rw_command {
 608         __u8                    opcode;
 609         __u8                    flags;
 610         __u16                   command_id;
 611         __le32                  nsid;
 612         __u64                   rsvd2;
 613         __le64                  metadata;
 614         union nvme_data_ptr     dptr;
 615         __le64                  slba;
 616         __le16                  length;
 617         __le16                  control;
 618         __le32                  dsmgmt;
 619         __le32                  reftag;
 620         __le16                  apptag;
 621         __le16                  appmask;
 622 };
 623
 624 enum {
 625         NVME_RW_LR                      = 1 << 15,
 626         NVME_RW_FUA                     = 1 << 14,
 627         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 628         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 629         NVME_RW_DSM_FREQ_RARE           = 2,
 630         NVME_RW_DSM_FREQ_READS          = 3,
 631         NVME_RW_DSM_FREQ_WRITES         = 4,
 632         NVME_RW_DSM_FREQ_RW             = 5,
 633         NVME_RW_DSM_FREQ_ONCE           = 6,
 634         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 635         NVME_RW_DSM_FREQ_TEMP           = 8,
 636         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 637         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 638         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 639         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 640         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 641         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 642         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 643         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 644         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 645         NVME_RW_PRINFO_PRACT            = 1 << 13,
 646         NVME_RW_DTYPE_STREAMS           = 1 << 4,
 647 };
 648
 649 struct nvme_dsm_cmd {
 650         __u8                    opcode;
 651         __u8                    flags;
 652         __u16                   command_id;
 653         __le32                  nsid;
 654         __u64                   rsvd2[2];
 655         union nvme_data_ptr     dptr;
 656         __le32                  nr;
 657         __le32                  attributes;
 658         __u32                   rsvd12[4];
 659 };
 660
 661 enum {
 662         NVME_DSMGMT_IDR         = 1 << 0,
 663         NVME_DSMGMT_IDW         = 1 << 1,
 664         NVME_DSMGMT_AD          = 1 << 2,
 665 };
 666
 667 #define NVME_DSM_MAX_RANGES     256
 668
 669 struct nvme_dsm_range {
 670         __le32                  cattr;
 671         __le32                  nlb;
 672         __le64                  slba;
 673 };
 674
 675 struct nvme_write_zeroes_cmd {
 676         __u8                    opcode;
 677         __u8                    flags;
 678         __u16                   command_id;
 679         __le32                  nsid;
 680         __u64                   rsvd2;
 681         __le64                  metadata;
 682         union nvme_data_ptr     dptr;
 683         __le64                  slba;
 684         __le16                  length;
 685         __le16                  control;
 686         __le32                  dsmgmt;
 687         __le32                  reftag;
 688         __le16                  apptag;
 689         __le16                  appmask;
 690 };
 691
 692 /* Features */
 693
 694 struct nvme_feat_auto_pst {
 695         __le64 entries[32];
 696 };
 697
 698 enum {
 699         NVME_HOST_MEM_ENABLE    = (1 << 0),
 700         NVME_HOST_MEM_RETURN    = (1 << 1),
 701 };
 702
 703 /* Admin commands */
 704
 705 enum nvme_admin_opcode {
 706         nvme_admin_delete_sq            = 0x00,
 707         nvme_admin_create_sq            = 0x01,
 708         nvme_admin_get_log_page         = 0x02,
 709         nvme_admin_delete_cq            = 0x04,
 710         nvme_admin_create_cq            = 0x05,
 711         nvme_admin_identify             = 0x06,
 712         nvme_admin_abort_cmd            = 0x08,
 713         nvme_admin_set_features         = 0x09,
 714         nvme_admin_get_features         = 0x0a,
 715         nvme_admin_async_event          = 0x0c,
 716         nvme_admin_ns_mgmt              = 0x0d,
 717         nvme_admin_activate_fw          = 0x10,
 718         nvme_admin_download_fw          = 0x11,
 719         nvme_admin_ns_attach            = 0x15,
 720         nvme_admin_keep_alive           = 0x18,
 721         nvme_admin_directive_send       = 0x19,
 722         nvme_admin_directive_recv       = 0x1a,
 723         nvme_admin_dbbuf                = 0x7C,
 724         nvme_admin_format_nvm           = 0x80,
 725         nvme_admin_security_send        = 0x81,
 726         nvme_admin_security_recv        = 0x82,
 727         nvme_admin_sanitize_nvm         = 0x84,
 728 };
 729
 730 enum {
 731         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 732         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 733         NVME_SQ_PRIO_URGENT     = (0 << 1),
 734         NVME_SQ_PRIO_HIGH       = (1 << 1),
 735         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 736         NVME_SQ_PRIO_LOW        = (3 << 1),
 737         NVME_FEAT_ARBITRATION   = 0x01,
 738         NVME_FEAT_POWER_MGMT    = 0x02,
 739         NVME_FEAT_LBA_RANGE     = 0x03,
 740         NVME_FEAT_TEMP_THRESH   = 0x04,
 741         NVME_FEAT_ERR_RECOVERY  = 0x05,
 742         NVME_FEAT_VOLATILE_WC   = 0x06,
 743         NVME_FEAT_NUM_QUEUES    = 0x07,
 744         NVME_FEAT_IRQ_COALESCE  = 0x08,
 745         NVME_FEAT_IRQ_CONFIG    = 0x09,
 746         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 747         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 748         NVME_FEAT_AUTO_PST      = 0x0c,
 749         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 750         NVME_FEAT_TIMESTAMP     = 0x0e,
 751         NVME_FEAT_KATO          = 0x0f,
 752         NVME_FEAT_SW_PROGRESS   = 0x80,
 753         NVME_FEAT_HOST_ID       = 0x81,
 754         NVME_FEAT_RESV_MASK     = 0x82,
 755         NVME_FEAT_RESV_PERSIST  = 0x83,
 756         NVME_LOG_ERROR          = 0x01,
 757         NVME_LOG_SMART          = 0x02,
 758         NVME_LOG_FW_SLOT        = 0x03,
 759         NVME_LOG_CHANGED_NS     = 0x04,
 760         NVME_LOG_CMD_EFFECTS    = 0x05,
 761         NVME_LOG_DISC           = 0x70,
 762         NVME_LOG_RESERVATION    = 0x80,
 763         NVME_FWACT_REPL         = (0 << 3),
 764         NVME_FWACT_REPL_ACTV    = (1 << 3),
 765         NVME_FWACT_ACTV         = (2 << 3),
 766 };
 767
 768 #define NVME_MAX_CHANGED_NAMESPACES     1024
 769
 770 struct nvme_identify {
 771         __u8                    opcode;
 772         __u8                    flags;
 773         __u16                   command_id;
 774         __le32                  nsid;
 775         __u64                   rsvd2[2];
 776         union nvme_data_ptr     dptr;
 777         __u8                    cns;
 778         __u8                    rsvd3;
 779         __le16                  ctrlid;
 780         __u32                   rsvd11[5];
 781 };
 782
 783 #define NVME_IDENTIFY_DATA_SIZE 4096
 784
 785 struct nvme_features {
 786         __u8                    opcode;
 787         __u8                    flags;
 788         __u16                   command_id;
 789         __le32                  nsid;
 790         __u64                   rsvd2[2];
 791         union nvme_data_ptr     dptr;
 792         __le32                  fid;
 793         __le32                  dword11;
 794         __le32                  dword12;
 795         __le32                  dword13;
 796         __le32                  dword14;
 797         __le32                  dword15;
 798 };
 799
 800 struct nvme_host_mem_buf_desc {
 801         __le64                  addr;
 802         __le32                  size;
 803         __u32                   rsvd;
 804 };
 805
 806 struct nvme_create_cq {
 807         __u8                    opcode;
 808         __u8                    flags;
 809         __u16                   command_id;
 810         __u32                   rsvd1[5];
 811         __le64                  prp1;
 812         __u64                   rsvd8;
 813         __le16                  cqid;
 814         __le16                  qsize;
 815         __le16                  cq_flags;
 816         __le16                  irq_vector;
 817         __u32                   rsvd12[4];
 818 };
 819
 820 struct nvme_create_sq {
 821         __u8                    opcode;
 822         __u8                    flags;
 823         __u16                   command_id;
 824         __u32                   rsvd1[5];
 825         __le64                  prp1;
 826         __u64                   rsvd8;
 827         __le16                  sqid;
 828         __le16                  qsize;
 829         __le16                  sq_flags;
 830         __le16                  cqid;
 831         __u32                   rsvd12[4];
 832 };
 833
 834 struct nvme_delete_queue {
 835         __u8                    opcode;
 836         __u8                    flags;
 837         __u16                   command_id;
 838         __u32                   rsvd1[9];
 839         __le16                  qid;
 840         __u16                   rsvd10;
 841         __u32                   rsvd11[5];
 842 };
 843
 844 struct nvme_abort_cmd {
 845         __u8                    opcode;
 846         __u8                    flags;
 847         __u16                   command_id;
 848         __u32                   rsvd1[9];
 849         __le16                  sqid;
 850         __u16                   cid;
 851         __u32                   rsvd11[5];
 852 };
 853
 854 struct nvme_download_firmware {
 855         __u8                    opcode;
 856         __u8                    flags;
 857         __u16                   command_id;
 858         __u32                   rsvd1[5];
 859         union nvme_data_ptr     dptr;
 860         __le32                  numd;
 861         __le32                  offset;
 862         __u32                   rsvd12[4];
 863 };
 864
 865 struct nvme_format_cmd {
 866         __u8                    opcode;
 867         __u8                    flags;
 868         __u16                   command_id;
 869         __le32                  nsid;
 870         __u64                   rsvd2[4];
 871         __le32                  cdw10;
 872         __u32                   rsvd11[5];
 873 };
 874
 875 struct nvme_get_log_page_command {
 876         __u8                    opcode;
 877         __u8                    flags;
 878         __u16                   command_id;
 879         __le32                  nsid;
 880         __u64                   rsvd2[2];
 881         union nvme_data_ptr     dptr;
 882         __u8                    lid;
 883         __u8                    rsvd10;
 884         __le16                  numdl;
 885         __le16                  numdu;
 886         __u16                   rsvd11;
 887         __le32                  lpol;
 888         __le32                  lpou;
 889         __u32                   rsvd14[2];
 890 };
 891
 892 struct nvme_directive_cmd {
 893         __u8                    opcode;
 894         __u8                    flags;
 895         __u16                   command_id;
 896         __le32                  nsid;
 897         __u64                   rsvd2[2];
 898         union nvme_data_ptr     dptr;
 899         __le32                  numd;
 900         __u8                    doper;
 901         __u8                    dtype;
 902         __le16                  dspec;
 903         __u8                    endir;
 904         __u8                    tdtype;
 905         __u16                   rsvd15;
 906
 907         __u32                   rsvd16[3];
 908 };
 909
 910 /*
 911  * Fabrics subcommands.
 912  */
 913 enum nvmf_fabrics_opcode {
 914         nvme_fabrics_command            = 0x7f,
 915 };
 916
 917 enum nvmf_capsule_command {
 918         nvme_fabrics_type_property_set  = 0x00,
 919         nvme_fabrics_type_connect       = 0x01,
 920         nvme_fabrics_type_property_get  = 0x04,
 921 };
 922
 923 struct nvmf_common_command {
 924         __u8    opcode;
 925         __u8    resv1;
 926         __u16   command_id;
 927         __u8    fctype;
 928         __u8    resv2[35];
 929         __u8    ts[24];
 930 };
 931
 932 /*
 933  * The legal cntlid range a NVMe Target will provide.
 934  * Note that cntlid of value 0 is considered illegal in the fabrics world.
 935  * Devices based on earlier specs did not have the subsystem concept;
 936  * therefore, those devices had their cntlid value set to 0 as a result.
 937  */
 938 #define NVME_CNTLID_MIN         1
 939 #define NVME_CNTLID_MAX         0xffef
 940 #define NVME_CNTLID_DYNAMIC     0xffff
 941
 942 #define MAX_DISC_LOGS   255
 943
 944 /* Discovery log page entry */
 945 struct nvmf_disc_rsp_page_entry {
 946         __u8            trtype;
 947         __u8            adrfam;
 948         __u8            subtype;
 949         __u8            treq;
 950         __le16          portid;
 951         __le16          cntlid;
 952         __le16          asqsz;
 953         __u8            resv8[22];
 954         char            trsvcid[NVMF_TRSVCID_SIZE];
 955         __u8            resv64[192];
 956         char            subnqn[NVMF_NQN_FIELD_LEN];
 957         char            traddr[NVMF_TRADDR_SIZE];
 958         union tsas {
 959                 char            common[NVMF_TSAS_SIZE];
 960                 struct rdma {
 961                         __u8    qptype;
 962                         __u8    prtype;
 963                         __u8    cms;
 964                         __u8    resv3[5];
 965                         __u16   pkey;
 966                         __u8    resv10[246];
 967                 } rdma;
 968         } tsas;
 969 };
 970
 971 /* Discovery log page header */
 972 struct nvmf_disc_rsp_page_hdr {
 973         __le64          genctr;
 974         __le64          numrec;
 975         __le16          recfmt;
 976         __u8            resv14[1006];
 977         struct nvmf_disc_rsp_page_entry entries[0];
 978 };
 979
 980 struct nvmf_connect_command {
 981         __u8            opcode;
 982         __u8            resv1;
 983         __u16           command_id;
 984         __u8            fctype;
 985         __u8            resv2[19];
 986         union nvme_data_ptr dptr;
 987         __le16          recfmt;
 988         __le16          qid;
 989         __le16          sqsize;
 990         __u8            cattr;
 991         __u8            resv3;
 992         __le32          kato;
 993         __u8            resv4[12];
 994 };
 995
 996 struct nvmf_connect_data {
 997         uuid_t          hostid;
 998         __le16          cntlid;
 999         char            resv4[238];
1000         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1001         char            hostnqn[NVMF_NQN_FIELD_LEN];
1002         char            resv5[256];
1003 };
1004
1005 struct nvmf_property_set_command {
1006         __u8            opcode;
1007         __u8            resv1;
1008         __u16           command_id;
1009         __u8            fctype;
1010         __u8            resv2[35];
1011         __u8            attrib;
1012         __u8            resv3[3];
1013         __le32          offset;
1014         __le64          value;
1015         __u8            resv4[8];
1016 };
1017
1018 struct nvmf_property_get_command {
1019         __u8            opcode;
1020         __u8            resv1;
1021         __u16           command_id;
1022         __u8            fctype;
1023         __u8            resv2[35];
1024         __u8            attrib;
1025         __u8            resv3[3];
1026         __le32          offset;
1027         __u8            resv4[16];
1028 };
1029
1030 struct nvme_dbbuf {
1031         __u8                    opcode;
1032         __u8                    flags;
1033         __u16                   command_id;
1034         __u32                   rsvd1[5];
1035         __le64                  prp1;
1036         __le64                  prp2;
1037         __u32                   rsvd12[6];
1038 };
1039
1040 struct streams_directive_params {
1041         __le16  msl;
1042         __le16  nssa;
1043         __le16  nsso;
1044         __u8    rsvd[10];
1045         __le32  sws;
1046         __le16  sgs;
1047         __le16  nsa;
1048         __le16  nso;
1049         __u8    rsvd2[6];
1050 };
1051
1052 struct nvme_command {
1053         union {
1054                 struct nvme_common_command common;
1055                 struct nvme_rw_command rw;
1056                 struct nvme_identify identify;
1057                 struct nvme_features features;
1058                 struct nvme_create_cq create_cq;
1059                 struct nvme_create_sq create_sq;
1060                 struct nvme_delete_queue delete_queue;
1061                 struct nvme_download_firmware dlfw;
1062                 struct nvme_format_cmd format;
1063                 struct nvme_dsm_cmd dsm;
1064                 struct nvme_write_zeroes_cmd write_zeroes;
1065                 struct nvme_abort_cmd abort;
1066                 struct nvme_get_log_page_command get_log_page;
1067                 struct nvmf_common_command fabrics;
1068                 struct nvmf_connect_command connect;
1069                 struct nvmf_property_set_command prop_set;
1070                 struct nvmf_property_get_command prop_get;
1071                 struct nvme_dbbuf dbbuf;
1072                 struct nvme_directive_cmd directive;
1073         };
1074 };
1075
1076 static inline bool nvme_is_write(struct nvme_command *cmd)
1077 {
1078         /*
1079          * What a mess...
1080          *
1081          * Why can't we simply have a Fabrics In and Fabrics out command?
1082          */
1083         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1084                 return cmd->fabrics.fctype & 1;
1085         return cmd->common.opcode & 1;
1086 }
1087
1088 enum {
1089         /*
1090          * Generic Command Status:
1091          */
1092         NVME_SC_SUCCESS                 = 0x0,
1093         NVME_SC_INVALID_OPCODE          = 0x1,
1094         NVME_SC_INVALID_FIELD           = 0x2,
1095         NVME_SC_CMDID_CONFLICT          = 0x3,
1096         NVME_SC_DATA_XFER_ERROR         = 0x4,
1097         NVME_SC_POWER_LOSS              = 0x5,
1098         NVME_SC_INTERNAL                = 0x6,
1099         NVME_SC_ABORT_REQ               = 0x7,
1100         NVME_SC_ABORT_QUEUE             = 0x8,
1101         NVME_SC_FUSED_FAIL              = 0x9,
1102         NVME_SC_FUSED_MISSING           = 0xa,
1103         NVME_SC_INVALID_NS              = 0xb,
1104         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1105         NVME_SC_SGL_INVALID_LAST        = 0xd,
1106         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1107         NVME_SC_SGL_INVALID_DATA        = 0xf,
1108         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1109         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1110
1111         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1112         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
1113
1114         NVME_SC_LBA_RANGE               = 0x80,
1115         NVME_SC_CAP_EXCEEDED            = 0x81,
1116         NVME_SC_NS_NOT_READY            = 0x82,
1117         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1118
1119         /*
1120          * Command Specific Status:
1121          */
1122         NVME_SC_CQ_INVALID              = 0x100,
1123         NVME_SC_QID_INVALID             = 0x101,
1124         NVME_SC_QUEUE_SIZE              = 0x102,
1125         NVME_SC_ABORT_LIMIT             = 0x103,
1126         NVME_SC_ABORT_MISSING           = 0x104,
1127         NVME_SC_ASYNC_LIMIT             = 0x105,
1128         NVME_SC_FIRMWARE_SLOT           = 0x106,
1129         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1130         NVME_SC_INVALID_VECTOR          = 0x108,
1131         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1132         NVME_SC_INVALID_FORMAT          = 0x10a,
1133         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1134         NVME_SC_INVALID_QUEUE           = 0x10c,
1135         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1136         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1137         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1138         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1139         NVME_SC_FW_NEEDS_RESET          = 0x111,
1140         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1141         NVME_SC_FW_ACIVATE_PROHIBITED   = 0x113,
1142         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1143         NVME_SC_NS_INSUFFICENT_CAP      = 0x115,
1144         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1145         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1146         NVME_SC_NS_IS_PRIVATE           = 0x119,
1147         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1148         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1149         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1150
1151         /*
1152          * I/O Command Set Specific - NVM commands:
1153          */
1154         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1155         NVME_SC_INVALID_PI              = 0x181,
1156         NVME_SC_READ_ONLY               = 0x182,
1157         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1158
1159         /*
1160          * I/O Command Set Specific - Fabrics commands:
1161          */
1162         NVME_SC_CONNECT_FORMAT          = 0x180,
1163         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1164         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1165         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1166         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1167
1168         NVME_SC_DISCOVERY_RESTART       = 0x190,
1169         NVME_SC_AUTH_REQUIRED           = 0x191,
1170
1171         /*
1172          * Media and Data Integrity Errors:
1173          */
1174         NVME_SC_WRITE_FAULT             = 0x280,
1175         NVME_SC_READ_ERROR              = 0x281,
1176         NVME_SC_GUARD_CHECK             = 0x282,
1177         NVME_SC_APPTAG_CHECK            = 0x283,
1178         NVME_SC_REFTAG_CHECK            = 0x284,
1179         NVME_SC_COMPARE_FAILED          = 0x285,
1180         NVME_SC_ACCESS_DENIED           = 0x286,
1181         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1182
1183         NVME_SC_DNR                     = 0x4000,
1184 };
1185
1186 struct nvme_completion {
1187         /*
1188          * Used by Admin and Fabrics commands to return data:
1189          */
1190         union nvme_result {
1191                 __le16  u16;
1192                 __le32  u32;
1193                 __le64  u64;
1194         } result;
1195         __le16  sq_head;        /* how much of this queue may be reclaimed */
1196         __le16  sq_id;          /* submission queue that generated this entry */
1197         __u16   command_id;     /* of the command which completed */
1198         __le16  status;         /* did the command fail, and if so, why? */
1199 };
1200
1201 #define NVME_VS(major, minor, tertiary) \
1202         (((major) << 16) | ((minor) << 8) | (tertiary))
1203
1204 #define NVME_MAJOR(ver)         ((ver) >> 16)
1205 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
1206 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
1207
1208 #endif /* _LINUX_NVME_H */