2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #ifndef __LINUX_MTD_SPI_NOR_H
11 #define __LINUX_MTD_SPI_NOR_H
13 #include <linux/bitops.h>
14 #include <linux/mtd/cfi.h>
15 #include <linux/mtd/mtd.h>
20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
21 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
23 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
24 #define SNOR_MFR_GIGADEVICE 0xc8
25 #define SNOR_MFR_INTEL CFI_MFR_INTEL
26 #define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
27 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
28 #define SNOR_MFR_SPANSION CFI_MFR_AMD
29 #define SNOR_MFR_SST CFI_MFR_SST
30 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
33 * Note on opcode nomenclature: some opcodes have a format like
34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
35 * of I/O lines used for the opcode, address, and data (respectively). The
36 * FUNCTION has an optional suffix of '4', to represent an opcode which
37 * requires a 4-byte (32-bit) address.
41 #define SPINOR_OP_WREN 0x06 /* Write enable */
42 #define SPINOR_OP_RDSR 0x05 /* Read status register */
43 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
44 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
45 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
46 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
47 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
52 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
53 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
54 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
55 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
56 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
57 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
58 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
59 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
60 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
61 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
62 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
63 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
64 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
65 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
66 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
69 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
70 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
72 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
73 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
74 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
75 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
76 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
77 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
78 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
79 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
80 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
82 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
83 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
84 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
85 #define SPINOR_OP_READ_1_4_4_DTR 0xed
87 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
88 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
89 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
91 /* Used for SST flashes only. */
92 #define SPINOR_OP_BP 0x02 /* Byte program */
93 #define SPINOR_OP_WRDI 0x04 /* Write disable */
94 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
96 /* Used for S3AN flashes only */
97 #define SPINOR_OP_XSE 0x50 /* Sector erase */
98 #define SPINOR_OP_XPP 0x82 /* Page program */
99 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
101 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
102 #define XSR_RDY BIT(7) /* Ready */
105 /* Used for Macronix and Winbond flashes. */
106 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
107 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
109 /* Used for Spansion flashes only. */
110 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
111 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
113 /* Used for Micron flashes only. */
114 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
115 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
117 /* Status Register bits. */
118 #define SR_WIP BIT(0) /* Write in progress */
119 #define SR_WEL BIT(1) /* Write enable latch */
120 /* meaning of other SR_* bits may differ between vendors */
121 #define SR_BP0 BIT(2) /* Block protect 0 */
122 #define SR_BP1 BIT(3) /* Block protect 1 */
123 #define SR_BP2 BIT(4) /* Block protect 2 */
124 #define SR_TB BIT(5) /* Top/Bottom protect */
125 #define SR_SRWD BIT(7) /* SR write protect */
126 /* Spansion/Cypress specific status bits */
127 #define SR_E_ERR BIT(5)
128 #define SR_P_ERR BIT(6)
130 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
132 /* Enhanced Volatile Configuration Register bits */
133 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
135 /* Flag Status Register bits */
136 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
137 #define FSR_E_ERR BIT(5) /* Erase operation status */
138 #define FSR_P_ERR BIT(4) /* Program operation status */
139 #define FSR_PT_ERR BIT(1) /* Protection error bit */
141 /* Configuration Register bits. */
142 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
144 /* Status Register 2 bits. */
145 #define SR2_QUAD_EN_BIT7 BIT(7)
147 /* Supported SPI protocols */
148 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
149 #define SNOR_PROTO_INST_SHIFT 16
150 #define SNOR_PROTO_INST(_nbits) \
151 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
152 SNOR_PROTO_INST_MASK)
154 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
155 #define SNOR_PROTO_ADDR_SHIFT 8
156 #define SNOR_PROTO_ADDR(_nbits) \
157 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
158 SNOR_PROTO_ADDR_MASK)
160 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
161 #define SNOR_PROTO_DATA_SHIFT 0
162 #define SNOR_PROTO_DATA(_nbits) \
163 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
164 SNOR_PROTO_DATA_MASK)
166 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
168 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
169 (SNOR_PROTO_INST(_inst_nbits) | \
170 SNOR_PROTO_ADDR(_addr_nbits) | \
171 SNOR_PROTO_DATA(_data_nbits))
172 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
173 (SNOR_PROTO_IS_DTR | \
174 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
176 enum spi_nor_protocol {
177 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
178 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
179 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
180 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
181 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
182 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
183 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
184 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
185 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
186 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
188 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
189 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
190 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
191 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
194 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
196 return !!(proto & SNOR_PROTO_IS_DTR);
199 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
201 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
202 SNOR_PROTO_INST_SHIFT;
205 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
207 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
208 SNOR_PROTO_ADDR_SHIFT;
211 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
213 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
214 SNOR_PROTO_DATA_SHIFT;
217 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
219 return spi_nor_get_protocol_data_nbits(proto);
222 #define SPI_NOR_MAX_CMD_SIZE 8
224 SPI_NOR_OPS_READ = 0,
231 enum spi_nor_option_flags {
232 SNOR_F_USE_FSR = BIT(0),
233 SNOR_F_HAS_SR_TB = BIT(1),
234 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
235 SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
236 SNOR_F_READY_XSR_RDY = BIT(4),
237 SNOR_F_USE_CLSR = BIT(5),
238 SNOR_F_BROKEN_RESET = BIT(6),
242 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
243 * @size: the size of the sector/block erased by the erase type.
244 * JEDEC JESD216B imposes erase sizes to be a power of 2.
245 * @size_shift: @size is a power of 2, the shift is stored in
247 * @size_mask: the size mask based on @size_shift.
248 * @opcode: the SPI command op code to erase the sector/block.
249 * @idx: Erase Type index as sorted in the Basic Flash Parameter
250 * Table. It will be used to synchronize the supported
251 * Erase Types with the ones identified in the SFDP
254 struct spi_nor_erase_type {
263 * struct spi_nor_erase_command - Used for non-uniform erases
264 * The structure is used to describe a list of erase commands to be executed
265 * once we validate that the erase can be performed. The elements in the list
266 * are run-length encoded.
267 * @list: for inclusion into the list of erase commands.
268 * @count: how many times the same erase command should be
269 * consecutively used.
270 * @size: the size of the sector/block erased by the command.
271 * @opcode: the SPI command op code to erase the sector/block.
273 struct spi_nor_erase_command {
274 struct list_head list;
281 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
282 * @offset: the offset in the data array of erase region start.
283 * LSB bits are used as a bitmask encoding flags to
284 * determine if this region is overlaid, if this region is
285 * the last in the SPI NOR flash memory and to indicate
286 * all the supported erase commands inside this region.
287 * The erase types are sorted in ascending order with the
288 * smallest Erase Type size being at BIT(0).
289 * @size: the size of the region in bytes.
291 struct spi_nor_erase_region {
296 #define SNOR_ERASE_TYPE_MAX 4
297 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
299 #define SNOR_LAST_REGION BIT(4)
300 #define SNOR_OVERLAID_REGION BIT(5)
302 #define SNOR_ERASE_FLAGS_MAX 6
303 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
306 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
307 * @regions: array of erase regions. The regions are consecutive in
308 * address space. Walking through the regions is done
310 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
311 * sector size (legacy implementation).
312 * @erase_type: an array of erase types shared by all the regions.
313 * The erase types are sorted in ascending order, with the
314 * smallest Erase Type size being the first member in the
316 * @uniform_erase_type: bitmask encoding erase types that can erase the
317 * entire memory. This member is completed at init by
318 * uniform and non-uniform SPI NOR flash memories if they
319 * support at least one erase type that can erase the
322 struct spi_nor_erase_map {
323 struct spi_nor_erase_region *regions;
324 struct spi_nor_erase_region uniform_region;
325 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
326 u8 uniform_erase_type;
330 * struct flash_info - Forward declaration of a structure used internally by
336 * struct spi_nor - Structure for defining a the SPI NOR layer
337 * @mtd: point to a mtd_info structure
338 * @lock: the lock for the read/write/erase/lock/unlock operations
339 * @dev: point to a spi device, or a spi nor controller device.
340 * @info: spi-nor part JDEC MFR id and other info
341 * @page_size: the page size of the SPI NOR
342 * @addr_width: number of address bytes
343 * @erase_opcode: the opcode for erasing a sector
344 * @read_opcode: the read opcode
345 * @read_dummy: the dummy needed by the read operation
346 * @program_opcode: the program opcode
347 * @sst_write_second: used by the SST write operation
348 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
349 * @read_proto: the SPI protocol for read operations
350 * @write_proto: the SPI protocol for write operations
351 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
352 * @cmd_buf: used by the write_reg
353 * @erase_map: the erase map of the SPI NOR
354 * @prepare: [OPTIONAL] do some preparations for the
355 * read/write/erase/lock/unlock operations
356 * @unprepare: [OPTIONAL] do some post work after the
357 * read/write/erase/lock/unlock operations
358 * @read_reg: [DRIVER-SPECIFIC] read out the register
359 * @write_reg: [DRIVER-SPECIFIC] write data to the register
360 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
361 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
362 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
363 * at the offset @offs; if not provided by the driver,
364 * spi-nor will send the erase opcode via write_reg()
365 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
366 * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
367 * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
368 * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode
370 * @priv: the private data
376 const struct flash_info *info;
383 enum spi_nor_protocol read_proto;
384 enum spi_nor_protocol write_proto;
385 enum spi_nor_protocol reg_proto;
386 bool sst_write_second;
388 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
389 struct spi_nor_erase_map erase_map;
391 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
392 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
393 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
394 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
396 ssize_t (*read)(struct spi_nor *nor, loff_t from,
397 size_t len, u_char *read_buf);
398 ssize_t (*write)(struct spi_nor *nor, loff_t to,
399 size_t len, const u_char *write_buf);
400 int (*erase)(struct spi_nor *nor, loff_t offs);
402 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
403 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
404 int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
405 int (*quad_enable)(struct spi_nor *nor);
410 static u64 __maybe_unused
411 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
413 return region->offset & SNOR_LAST_REGION;
416 static u64 __maybe_unused
417 spi_nor_region_end(const struct spi_nor_erase_region *region)
419 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
422 static void __maybe_unused
423 spi_nor_region_mark_end(struct spi_nor_erase_region *region)
425 region->offset |= SNOR_LAST_REGION;
428 static void __maybe_unused
429 spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
431 region->offset |= SNOR_OVERLAID_REGION;
434 static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
436 return !!nor->erase_map.uniform_erase_type;
439 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
440 struct device_node *np)
442 mtd_set_of_node(&nor->mtd, np);
445 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
447 return mtd_get_of_node(&nor->mtd);
451 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
452 * supported by the SPI controller (bus master).
453 * @mask: the bitmask listing all the supported hw capabilies
455 struct spi_nor_hwcaps {
460 *(Fast) Read capabilities.
461 * MUST be ordered by priority: the higher bit position, the higher priority.
462 * As a matter of performances, it is relevant to use Octo SPI protocols first,
463 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
466 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
467 #define SNOR_HWCAPS_READ BIT(0)
468 #define SNOR_HWCAPS_READ_FAST BIT(1)
469 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
471 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
472 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
473 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
474 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
475 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
477 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
478 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
479 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
480 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
481 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
483 #define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
484 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
485 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
486 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
487 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
490 * Page Program capabilities.
491 * MUST be ordered by priority: the higher bit position, the higher priority.
492 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
493 * legacy SPI 1-1-1 protocol.
494 * Note that Dual Page Programs are not supported because there is no existing
495 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
496 * implements such commands.
498 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
499 #define SNOR_HWCAPS_PP BIT(16)
501 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
502 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
503 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
504 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
506 #define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
507 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
508 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
509 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
512 * spi_nor_scan() - scan the SPI NOR
513 * @nor: the spi_nor structure
514 * @name: the chip type name
515 * @hwcaps: the hardware capabilities supported by the controller driver
517 * The drivers can use this fuction to scan the SPI NOR.
518 * In the scanning, it will try to get all the necessary information to
519 * fill the mtd_info{} and the spi_nor{}.
521 * The chip type name can be provided through the @name parameter.
523 * Return: 0 for success, others for failure.
525 int spi_nor_scan(struct spi_nor *nor, const char *name,
526 const struct spi_nor_hwcaps *hwcaps);
529 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
530 * @nor: the spi_nor structure
532 void spi_nor_restore(struct spi_nor *nor);