1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
8 * Contains standard defines and IDs for NAND flash devices
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/flashchip.h>
18 #include <linux/mtd/bbm.h>
19 #include <linux/mtd/jedec.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/onfi.h>
22 #include <linux/mutex.h>
24 #include <linux/types.h>
28 /* The maximum number of NAND chips in an array */
29 #define NAND_MAX_CHIPS 8
32 * Constants for hardware specific CLE/ALE/NCE function
34 * These are bits which can be or'ed to set/clear multiple
37 /* Select the chip by setting nCE to low */
39 /* Select the command latch by setting CLE to high */
41 /* Select the address latch by setting ALE to high */
44 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
45 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
46 #define NAND_CTRL_CHANGE 0x80
49 * Standard NAND flash commands
51 #define NAND_CMD_READ0 0
52 #define NAND_CMD_READ1 1
53 #define NAND_CMD_RNDOUT 5
54 #define NAND_CMD_PAGEPROG 0x10
55 #define NAND_CMD_READOOB 0x50
56 #define NAND_CMD_ERASE1 0x60
57 #define NAND_CMD_STATUS 0x70
58 #define NAND_CMD_SEQIN 0x80
59 #define NAND_CMD_RNDIN 0x85
60 #define NAND_CMD_READID 0x90
61 #define NAND_CMD_ERASE2 0xd0
62 #define NAND_CMD_PARAM 0xec
63 #define NAND_CMD_GET_FEATURES 0xee
64 #define NAND_CMD_SET_FEATURES 0xef
65 #define NAND_CMD_RESET 0xff
67 /* Extended commands for large page devices */
68 #define NAND_CMD_READSTART 0x30
69 #define NAND_CMD_RNDOUTSTART 0xE0
70 #define NAND_CMD_CACHEDPROG 0x15
72 #define NAND_CMD_NONE -1
75 #define NAND_STATUS_FAIL 0x01
76 #define NAND_STATUS_FAIL_N1 0x02
77 #define NAND_STATUS_TRUE_READY 0x20
78 #define NAND_STATUS_READY 0x40
79 #define NAND_STATUS_WP 0x80
81 #define NAND_DATA_IFACE_CHECK_ONLY -1
84 * Constants for ECC_MODES
103 * Constants for Hardware ECC
105 /* Reset Hardware ECC for read */
106 #define NAND_ECC_READ 0
107 /* Reset Hardware ECC for write */
108 #define NAND_ECC_WRITE 1
109 /* Enable Hardware ECC before syndrome is read back from flash */
110 #define NAND_ECC_READSYN 2
113 * Enable generic NAND 'page erased' check. This check is only done when
114 * ecc.correct() returns -EBADMSG.
115 * Set this flag if your implementation does not fix bitflips in erased
116 * pages and you want to rely on the default implementation.
118 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
119 #define NAND_ECC_MAXIMIZE BIT(1)
122 * Option constants for bizarre disfunctionality and real
126 /* Buswidth is 16 bit */
127 #define NAND_BUSWIDTH_16 BIT(1)
130 * When using software implementation of Hamming, we can specify which byte
131 * ordering should be used.
133 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
135 /* Chip has cache program function */
136 #define NAND_CACHEPRG BIT(3)
137 /* Options valid for Samsung large page devices */
138 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
141 * Chip requires ready check on read (for auto-incremented sequential read).
142 * True only for small page devices; large page devices do not support
145 #define NAND_NEED_READRDY BIT(8)
147 /* Chip does not allow subpage writes */
148 #define NAND_NO_SUBPAGE_WRITE BIT(9)
150 /* Device is one of 'new' xD cards that expose fake nand command set */
151 #define NAND_BROKEN_XD BIT(10)
153 /* Device behaves just like nand, but is readonly */
154 #define NAND_ROM BIT(11)
156 /* Device supports subpage reads */
157 #define NAND_SUBPAGE_READ BIT(12)
158 /* Macros to identify the above */
159 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
162 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
165 #define NAND_NEED_SCRAMBLING BIT(13)
167 /* Device needs 3rd row address cycle */
168 #define NAND_ROW_ADDR_3 BIT(14)
170 /* Non chip related options */
171 /* This option skips the bbt scan during initialization. */
172 #define NAND_SKIP_BBTSCAN BIT(16)
173 /* Chip may not exist, so silence any errors in scan */
174 #define NAND_SCAN_SILENT_NODEV BIT(18)
177 * Autodetect nand buswidth with readid/onfi.
178 * This suppose the driver will configure the hardware in 8 bits mode
179 * when calling nand_scan_ident, and update its configuration
180 * before calling nand_scan_tail.
182 #define NAND_BUSWIDTH_AUTO BIT(19)
185 * This option could be defined by controller drivers to protect against
186 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
188 #define NAND_USES_DMA BIT(20)
191 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
192 * on the default ->cmdfunc() implementation, you may want to let the core
193 * handle the tCCS delay which is required when a column change (RNDIN or
194 * RNDOUT) is requested.
195 * If your controller already takes care of this delay, you don't need to set
198 #define NAND_WAIT_TCCS BIT(21)
201 * Whether the NAND chip is a boot medium. Drivers might use this information
202 * to select ECC algorithms supported by the boot ROM or similar restrictions.
204 #define NAND_IS_BOOT_MEDIUM BIT(22)
207 * Do not try to tweak the timings at runtime. This is needed when the
208 * controller initializes the timings on itself or when it relies on
209 * configuration done by the bootloader.
211 #define NAND_KEEP_TIMINGS BIT(23)
214 * There are different places where the manufacturer stores the factory bad
217 * Position within the block: Each of these pages needs to be checked for a
218 * bad block marking pattern.
220 #define NAND_BBM_FIRSTPAGE BIT(24)
221 #define NAND_BBM_SECONDPAGE BIT(25)
222 #define NAND_BBM_LASTPAGE BIT(26)
225 * Some controllers with pipelined ECC engines override the BBM marker with
226 * data or ECC bytes, thus making bad block detection through bad block marker
227 * impossible. Let's flag those chips so the core knows it shouldn't check the
228 * BBM and consider all blocks good.
230 #define NAND_NO_BBM_QUIRK BIT(27)
232 /* Cell info constants */
233 #define NAND_CI_CHIPNR_MSK 0x03
234 #define NAND_CI_CELLTYPE_MSK 0x0C
235 #define NAND_CI_CELLTYPE_SHIFT 2
237 /* Position within the OOB data of the page */
238 #define NAND_BBM_POS_SMALL 5
239 #define NAND_BBM_POS_LARGE 0
242 * struct nand_parameters - NAND generic parameters from the parameter page
244 * @supports_set_get_features: The NAND chip supports setting/getting features
245 * @set_feature_list: Bitmap of features that can be set
246 * @get_feature_list: Bitmap of features that can be get
247 * @onfi: ONFI specific parameters
249 struct nand_parameters {
250 /* Generic parameters */
252 bool supports_set_get_features;
253 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
254 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
256 /* ONFI parameters */
257 struct onfi_params *onfi;
260 /* The maximum expected count of bytes in the NAND ID sequence */
261 #define NAND_MAX_ID_LEN 8
264 * struct nand_id - NAND id structure
265 * @data: buffer containing the id bytes.
269 u8 data[NAND_MAX_ID_LEN];
274 * struct nand_ecc_step_info - ECC step information of ECC engine
275 * @stepsize: data bytes per ECC step
276 * @strengths: array of supported strengths
277 * @nstrengths: number of supported strengths
279 struct nand_ecc_step_info {
281 const int *strengths;
286 * struct nand_ecc_caps - capability of ECC engine
287 * @stepinfos: array of ECC step information
288 * @nstepinfos: number of ECC step information
289 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
291 struct nand_ecc_caps {
292 const struct nand_ecc_step_info *stepinfos;
294 int (*calc_ecc_bytes)(int step_size, int strength);
297 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
298 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
299 static const int __name##_strengths[] = { __VA_ARGS__ }; \
300 static const struct nand_ecc_step_info __name##_stepinfo = { \
301 .stepsize = __step, \
302 .strengths = __name##_strengths, \
303 .nstrengths = ARRAY_SIZE(__name##_strengths), \
305 static const struct nand_ecc_caps __name = { \
306 .stepinfos = &__name##_stepinfo, \
308 .calc_ecc_bytes = __calc, \
312 * struct nand_ecc_ctrl - Control structure for ECC
314 * @algo: ECC algorithm
315 * @steps: number of ECC steps per page
316 * @size: data bytes per ECC step
317 * @bytes: ECC bytes per step
318 * @strength: max number of correctible bits per ECC step
319 * @total: total number of ECC bytes per page
320 * @prepad: padding information for syndrome based ECC generators
321 * @postpad: padding information for syndrome based ECC generators
322 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
323 * @priv: pointer to private ECC control data
324 * @calc_buf: buffer for calculated ECC, size is oobsize.
325 * @code_buf: buffer for ECC read from flash, size is oobsize.
326 * @hwctl: function to control hardware ECC generator. Must only
327 * be provided if an hardware ECC is available
328 * @calculate: function for ECC calculation or readback from ECC hardware
329 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
330 * Should return a positive number representing the number of
331 * corrected bitflips, -EBADMSG if the number of bitflips exceed
332 * ECC strength, or any other error code if the error is not
333 * directly related to correction.
334 * If -EBADMSG is returned the input buffers should be left
336 * @read_page_raw: function to read a raw page without ECC. This function
337 * should hide the specific layout used by the ECC
338 * controller and always return contiguous in-band and
339 * out-of-band data even if they're not stored
340 * contiguously on the NAND chip (e.g.
341 * NAND_ECC_HW_SYNDROME interleaves in-band and
343 * @write_page_raw: function to write a raw page without ECC. This function
344 * should hide the specific layout used by the ECC
345 * controller and consider the passed data as contiguous
346 * in-band and out-of-band data. ECC controller is
347 * responsible for doing the appropriate transformations
348 * to adapt to its specific layout (e.g.
349 * NAND_ECC_HW_SYNDROME interleaves in-band and
351 * @read_page: function to read a page according to the ECC generator
352 * requirements; returns maximum number of bitflips corrected in
353 * any single ECC step, -EIO hw error
354 * @read_subpage: function to read parts of the page covered by ECC;
355 * returns same as read_page()
356 * @write_subpage: function to write parts of the page covered by ECC.
357 * @write_page: function to write a page according to the ECC generator
359 * @write_oob_raw: function to write chip OOB data without ECC
360 * @read_oob_raw: function to read chip OOB data without ECC
361 * @read_oob: function to read chip OOB data
362 * @write_oob: function to write chip OOB data
364 struct nand_ecc_ctrl {
365 enum nand_ecc_mode mode;
366 enum nand_ecc_algo algo;
374 unsigned int options;
378 void (*hwctl)(struct nand_chip *chip, int mode);
379 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
381 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
383 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
384 int oob_required, int page);
385 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
386 int oob_required, int page);
387 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
388 int oob_required, int page);
389 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
390 uint32_t len, uint8_t *buf, int page);
391 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
392 uint32_t data_len, const uint8_t *data_buf,
393 int oob_required, int page);
394 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
395 int oob_required, int page);
396 int (*write_oob_raw)(struct nand_chip *chip, int page);
397 int (*read_oob_raw)(struct nand_chip *chip, int page);
398 int (*read_oob)(struct nand_chip *chip, int page);
399 int (*write_oob)(struct nand_chip *chip, int page);
403 * struct nand_sdr_timings - SDR NAND chip timings
405 * This struct defines the timing requirements of a SDR NAND chip.
406 * These information can be found in every NAND datasheets and the timings
407 * meaning are described in the ONFI specifications:
408 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
411 * All these timings are expressed in picoseconds.
413 * @tBERS_max: Block erase time
414 * @tCCS_min: Change column setup time
415 * @tPROG_max: Page program time
416 * @tR_max: Page read time
417 * @tALH_min: ALE hold time
418 * @tADL_min: ALE to data loading time
419 * @tALS_min: ALE setup time
420 * @tAR_min: ALE to RE# delay
421 * @tCEA_max: CE# access time
422 * @tCEH_min: CE# high hold time
423 * @tCH_min: CE# hold time
424 * @tCHZ_max: CE# high to output hi-Z
425 * @tCLH_min: CLE hold time
426 * @tCLR_min: CLE to RE# delay
427 * @tCLS_min: CLE setup time
428 * @tCOH_min: CE# high to output hold
429 * @tCS_min: CE# setup time
430 * @tDH_min: Data hold time
431 * @tDS_min: Data setup time
432 * @tFEAT_max: Busy time for Set Features and Get Features
433 * @tIR_min: Output hi-Z to RE# low
434 * @tITC_max: Interface and Timing Mode Change time
435 * @tRC_min: RE# cycle time
436 * @tREA_max: RE# access time
437 * @tREH_min: RE# high hold time
438 * @tRHOH_min: RE# high to output hold
439 * @tRHW_min: RE# high to WE# low
440 * @tRHZ_max: RE# high to output hi-Z
441 * @tRLOH_min: RE# low to output hold
442 * @tRP_min: RE# pulse width
443 * @tRR_min: Ready to RE# low (data only)
444 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
445 * rising edge of R/B#.
446 * @tWB_max: WE# high to SR[6] low
447 * @tWC_min: WE# cycle time
448 * @tWH_min: WE# high hold time
449 * @tWHR_min: WE# high to RE# low
450 * @tWP_min: WE# pulse width
451 * @tWW_min: WP# transition to WE# low
453 struct nand_sdr_timings {
495 * enum nand_data_interface_type - NAND interface timing type
496 * @NAND_SDR_IFACE: Single Data Rate interface
498 enum nand_data_interface_type {
503 * struct nand_data_interface - NAND interface timing
504 * @type: type of the timing
505 * @timings: The timing information
506 * @timings.mode: Timing mode as defined in the specification
507 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
509 struct nand_data_interface {
510 enum nand_data_interface_type type;
511 struct nand_timings {
514 struct nand_sdr_timings sdr;
520 * nand_get_sdr_timings - get SDR timing from data interface
521 * @conf: The data interface
523 static inline const struct nand_sdr_timings *
524 nand_get_sdr_timings(const struct nand_data_interface *conf)
526 if (conf->type != NAND_SDR_IFACE)
527 return ERR_PTR(-EINVAL);
529 return &conf->timings.sdr;
533 * struct nand_op_cmd_instr - Definition of a command instruction
534 * @opcode: the command to issue in one cycle
536 struct nand_op_cmd_instr {
541 * struct nand_op_addr_instr - Definition of an address instruction
542 * @naddrs: length of the @addrs array
543 * @addrs: array containing the address cycles to issue
545 struct nand_op_addr_instr {
551 * struct nand_op_data_instr - Definition of a data instruction
552 * @len: number of data bytes to move
553 * @buf: buffer to fill
554 * @buf.in: buffer to fill when reading from the NAND chip
555 * @buf.out: buffer to read from when writing to the NAND chip
556 * @force_8bit: force 8-bit access
558 * Please note that "in" and "out" are inverted from the ONFI specification
559 * and are from the controller perspective, so a "in" is a read from the NAND
560 * chip while a "out" is a write to the NAND chip.
562 struct nand_op_data_instr {
572 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
573 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
575 struct nand_op_waitrdy_instr {
576 unsigned int timeout_ms;
580 * enum nand_op_instr_type - Definition of all instruction types
581 * @NAND_OP_CMD_INSTR: command instruction
582 * @NAND_OP_ADDR_INSTR: address instruction
583 * @NAND_OP_DATA_IN_INSTR: data in instruction
584 * @NAND_OP_DATA_OUT_INSTR: data out instruction
585 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
587 enum nand_op_instr_type {
590 NAND_OP_DATA_IN_INSTR,
591 NAND_OP_DATA_OUT_INSTR,
592 NAND_OP_WAITRDY_INSTR,
596 * struct nand_op_instr - Instruction object
597 * @type: the instruction type
598 * @ctx: extra data associated to the instruction. You'll have to use the
599 * appropriate element depending on @type
600 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
601 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
602 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
603 * or %NAND_OP_DATA_OUT_INSTR
604 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
605 * @delay_ns: delay the controller should apply after the instruction has been
606 * issued on the bus. Most modern controllers have internal timings
607 * control logic, and in this case, the controller driver can ignore
610 struct nand_op_instr {
611 enum nand_op_instr_type type;
613 struct nand_op_cmd_instr cmd;
614 struct nand_op_addr_instr addr;
615 struct nand_op_data_instr data;
616 struct nand_op_waitrdy_instr waitrdy;
618 unsigned int delay_ns;
622 * Special handling must be done for the WAITRDY timeout parameter as it usually
623 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
624 * tBERS (during an erase) which all of them are u64 values that cannot be
625 * divided by usual kernel macros and must be handled with the special
626 * DIV_ROUND_UP_ULL() macro.
628 * Cast to type of dividend is needed here to guarantee that the result won't
629 * be an unsigned long long when the dividend is an unsigned long (or smaller),
630 * which is what the compiler does when it sees ternary operator with 2
631 * different return types (picks the largest type to make sure there's no
634 #define __DIVIDE(dividend, divisor) ({ \
635 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
636 DIV_ROUND_UP(dividend, divisor) : \
637 DIV_ROUND_UP_ULL(dividend, divisor)); \
639 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
640 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
642 #define NAND_OP_CMD(id, ns) \
644 .type = NAND_OP_CMD_INSTR, \
645 .ctx.cmd.opcode = id, \
649 #define NAND_OP_ADDR(ncycles, cycles, ns) \
651 .type = NAND_OP_ADDR_INSTR, \
659 #define NAND_OP_DATA_IN(l, b, ns) \
661 .type = NAND_OP_DATA_IN_INSTR, \
665 .force_8bit = false, \
670 #define NAND_OP_DATA_OUT(l, b, ns) \
672 .type = NAND_OP_DATA_OUT_INSTR, \
676 .force_8bit = false, \
681 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
683 .type = NAND_OP_DATA_IN_INSTR, \
687 .force_8bit = true, \
692 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
694 .type = NAND_OP_DATA_OUT_INSTR, \
698 .force_8bit = true, \
703 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
705 .type = NAND_OP_WAITRDY_INSTR, \
706 .ctx.waitrdy.timeout_ms = tout_ms, \
711 * struct nand_subop - a sub operation
712 * @cs: the CS line to select for this NAND sub-operation
713 * @instrs: array of instructions
714 * @ninstrs: length of the @instrs array
715 * @first_instr_start_off: offset to start from for the first instruction
716 * of the sub-operation
717 * @last_instr_end_off: offset to end at (excluded) for the last instruction
718 * of the sub-operation
720 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
721 * address instructions.
723 * When an operation cannot be handled as is by the NAND controller, it will
724 * be split by the parser into sub-operations which will be passed to the
729 const struct nand_op_instr *instrs;
730 unsigned int ninstrs;
731 unsigned int first_instr_start_off;
732 unsigned int last_instr_end_off;
735 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
737 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
739 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
741 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
745 * struct nand_op_parser_addr_constraints - Constraints for address instructions
746 * @maxcycles: maximum number of address cycles the controller can issue in a
749 struct nand_op_parser_addr_constraints {
750 unsigned int maxcycles;
754 * struct nand_op_parser_data_constraints - Constraints for data instructions
755 * @maxlen: maximum data length that the controller can handle in a single step
757 struct nand_op_parser_data_constraints {
762 * struct nand_op_parser_pattern_elem - One element of a pattern
763 * @type: the instructuction type
764 * @optional: whether this element of the pattern is optional or mandatory
765 * @ctx: address or data constraint
766 * @ctx.addr: address constraint (number of cycles)
767 * @ctx.data: data constraint (data length)
769 struct nand_op_parser_pattern_elem {
770 enum nand_op_instr_type type;
773 struct nand_op_parser_addr_constraints addr;
774 struct nand_op_parser_data_constraints data;
778 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
780 .type = NAND_OP_CMD_INSTR, \
784 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
786 .type = NAND_OP_ADDR_INSTR, \
788 .ctx.addr.maxcycles = _maxcycles, \
791 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
793 .type = NAND_OP_DATA_IN_INSTR, \
795 .ctx.data.maxlen = _maxlen, \
798 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
800 .type = NAND_OP_DATA_OUT_INSTR, \
802 .ctx.data.maxlen = _maxlen, \
805 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
807 .type = NAND_OP_WAITRDY_INSTR, \
812 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
813 * @elems: array of pattern elements
814 * @nelems: number of pattern elements in @elems array
815 * @exec: the function that will issue a sub-operation
817 * A pattern is a list of elements, each element reprensenting one instruction
818 * with its constraints. The pattern itself is used by the core to match NAND
819 * chip operation with NAND controller operations.
820 * Once a match between a NAND controller operation pattern and a NAND chip
821 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
822 * hook is called so that the controller driver can issue the operation on the
825 * Controller drivers should declare as many patterns as they support and pass
826 * this list of patterns (created with the help of the following macro) to
827 * the nand_op_parser_exec_op() helper.
829 struct nand_op_parser_pattern {
830 const struct nand_op_parser_pattern_elem *elems;
832 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
835 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
838 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
839 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
840 sizeof(struct nand_op_parser_pattern_elem), \
844 * struct nand_op_parser - NAND controller operation parser descriptor
845 * @patterns: array of supported patterns
846 * @npatterns: length of the @patterns array
848 * The parser descriptor is just an array of supported patterns which will be
849 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
850 * NAND operation (or tries to determine if a specific operation is supported).
852 * It is worth mentioning that patterns will be tested in their declaration
853 * order, and the first match will be taken, so it's important to order patterns
854 * appropriately so that simple/inefficient patterns are placed at the end of
855 * the list. Usually, this is where you put single instruction patterns.
857 struct nand_op_parser {
858 const struct nand_op_parser_pattern *patterns;
859 unsigned int npatterns;
862 #define NAND_OP_PARSER(...) \
864 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
865 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
866 sizeof(struct nand_op_parser_pattern), \
870 * struct nand_operation - NAND operation descriptor
871 * @cs: the CS line to select for this NAND operation
872 * @instrs: array of instructions to execute
873 * @ninstrs: length of the @instrs array
875 * The actual operation structure that will be passed to chip->exec_op().
877 struct nand_operation {
879 const struct nand_op_instr *instrs;
880 unsigned int ninstrs;
883 #define NAND_OPERATION(_cs, _instrs) \
887 .ninstrs = ARRAY_SIZE(_instrs), \
890 int nand_op_parser_exec_op(struct nand_chip *chip,
891 const struct nand_op_parser *parser,
892 const struct nand_operation *op, bool check_only);
894 static inline void nand_op_trace(const char *prefix,
895 const struct nand_op_instr *instr)
897 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
898 switch (instr->type) {
899 case NAND_OP_CMD_INSTR:
900 pr_debug("%sCMD [0x%02x]\n", prefix,
901 instr->ctx.cmd.opcode);
903 case NAND_OP_ADDR_INSTR:
904 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
905 instr->ctx.addr.naddrs,
906 instr->ctx.addr.naddrs < 64 ?
907 instr->ctx.addr.naddrs : 64,
908 instr->ctx.addr.addrs);
910 case NAND_OP_DATA_IN_INSTR:
911 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
913 instr->ctx.data.force_8bit ?
914 ", force 8-bit" : "");
916 case NAND_OP_DATA_OUT_INSTR:
917 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
919 instr->ctx.data.force_8bit ?
920 ", force 8-bit" : "");
922 case NAND_OP_WAITRDY_INSTR:
923 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
924 instr->ctx.waitrdy.timeout_ms);
931 * struct nand_controller_ops - Controller operations
933 * @attach_chip: this method is called after the NAND detection phase after
934 * flash ID and MTD fields such as erase size, page size and OOB
935 * size have been set up. ECC requirements are available if
936 * provided by the NAND chip or device tree. Typically used to
937 * choose the appropriate ECC configuration and allocate
938 * associated resources.
939 * This hook is optional.
940 * @detach_chip: free all resources allocated/claimed in
941 * nand_controller_ops->attach_chip().
942 * This hook is optional.
943 * @exec_op: controller specific method to execute NAND operations.
944 * This method replaces chip->legacy.cmdfunc(),
945 * chip->legacy.{read,write}_{buf,byte,word}(),
946 * chip->legacy.dev_ready() and chip->legacy.waifunc().
947 * @setup_data_interface: setup the data interface and timing. If
948 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
949 * means the configuration should not be applied but
951 * This hook is optional.
953 struct nand_controller_ops {
954 int (*attach_chip)(struct nand_chip *chip);
955 void (*detach_chip)(struct nand_chip *chip);
956 int (*exec_op)(struct nand_chip *chip,
957 const struct nand_operation *op,
959 int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
960 const struct nand_data_interface *conf);
964 * struct nand_controller - Structure used to describe a NAND controller
966 * @lock: lock used to serialize accesses to the NAND controller
967 * @ops: NAND controller operations.
969 struct nand_controller {
971 const struct nand_controller_ops *ops;
974 static inline void nand_controller_init(struct nand_controller *nfc)
976 mutex_init(&nfc->lock);
980 * struct nand_legacy - NAND chip legacy fields/hooks
981 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
982 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
983 * @select_chip: select/deselect a specific target/die
984 * @read_byte: read one byte from the chip
985 * @write_byte: write a single byte to the chip on the low 8 I/O lines
986 * @write_buf: write data from the buffer to the chip
987 * @read_buf: read data from the chip into the buffer
988 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
989 * to write command and address
990 * @cmdfunc: hardware specific function for writing commands to the chip.
991 * @dev_ready: hardware specific function for accessing device ready/busy line.
992 * If set to NULL no access to ready/busy is available and the
993 * ready/busy information is read from the chip status register.
994 * @waitfunc: hardware specific function for wait on ready.
995 * @block_bad: check if a block is bad, using OOB markers
996 * @block_markbad: mark a block bad
997 * @set_features: set the NAND chip features
998 * @get_features: get the NAND chip features
999 * @chip_delay: chip dependent delay for transferring data from array to read
1001 * @dummy_controller: dummy controller implementation for drivers that can
1002 * only control a single chip
1004 * If you look at this structure you're already wrong. These fields/hooks are
1007 struct nand_legacy {
1008 void __iomem *IO_ADDR_R;
1009 void __iomem *IO_ADDR_W;
1010 void (*select_chip)(struct nand_chip *chip, int cs);
1011 u8 (*read_byte)(struct nand_chip *chip);
1012 void (*write_byte)(struct nand_chip *chip, u8 byte);
1013 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1014 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1015 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1016 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1018 int (*dev_ready)(struct nand_chip *chip);
1019 int (*waitfunc)(struct nand_chip *chip);
1020 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1021 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1022 int (*set_features)(struct nand_chip *chip, int feature_addr,
1023 u8 *subfeature_para);
1024 int (*get_features)(struct nand_chip *chip, int feature_addr,
1025 u8 *subfeature_para);
1027 struct nand_controller dummy_controller;
1031 * struct nand_chip - NAND Private Flash Chip Data
1032 * @base: Inherit from the generic NAND device
1033 * @legacy: All legacy fields/hooks. If you develop a new driver,
1034 * don't even try to use any of these fields/hooks, and if
1035 * you're modifying an existing driver that is using those
1036 * fields/hooks, you should consider reworking the driver
1038 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
1039 * setting the read-retry mode. Mostly needed for MLC NAND.
1040 * @ecc: [BOARDSPECIFIC] ECC control structure
1041 * @buf_align: minimum buffer alignment required by a platform
1042 * @oob_poi: "poison value buffer," used for laying out OOB data
1044 * @page_shift: [INTERN] number of address bits in a page (column
1046 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
1047 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
1048 * @chip_shift: [INTERN] number of address bits in one chip
1049 * @options: [BOARDSPECIFIC] various chip options. They can partly
1050 * be set to inform nand_scan about special functionality.
1051 * See the defines for further explanation.
1052 * @bbt_options: [INTERN] bad block specific options. All options used
1053 * here must come from bbm.h. By default, these options
1054 * will be copied to the appropriate nand_bbt_descr's.
1055 * @badblockpos: [INTERN] position of the bad block marker in the oob
1057 * @badblockbits: [INTERN] minimum number of set bits in a good block's
1058 * bad block marker position; i.e., BBM == 11110111b is
1059 * not bad when badblockbits == 7
1060 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1061 * set to the actually used ONFI mode if the chip is
1062 * ONFI compliant or deduced from the datasheet if
1063 * the NAND chip is not ONFI compliant.
1064 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
1065 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
1066 * @pagecache: Structure containing page cache related fields
1067 * @pagecache.bitflips: Number of bitflips of the cached page
1068 * @pagecache.page: Page number currently in the cache. -1 means no page is
1070 * @subpagesize: [INTERN] holds the subpagesize
1071 * @id: [INTERN] holds NAND ID
1072 * @parameters: [INTERN] holds generic parameters under an easily
1074 * @data_interface: [INTERN] NAND interface timing information
1075 * @cur_cs: currently selected target. -1 means no target selected,
1076 * otherwise we should always have cur_cs >= 0 &&
1077 * cur_cs < nanddev_ntargets(). NAND Controller drivers
1078 * should not modify this value, but they're allowed to
1080 * @read_retries: [INTERN] the number of read retry modes supported
1081 * @lock: lock protecting the suspended field. Also used to
1082 * serialize accesses to the NAND device.
1083 * @suspended: set to 1 when the device is suspended, 0 when it's not.
1084 * @suspend: [REPLACEABLE] specific NAND device suspend operation
1085 * @resume: [REPLACEABLE] specific NAND device resume operation
1086 * @bbt: [INTERN] bad block table pointer
1087 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
1089 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
1090 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
1092 * @controller: [REPLACEABLE] a pointer to a hardware controller
1093 * structure which is shared among multiple independent
1095 * @priv: [OPTIONAL] pointer to private chip data
1096 * @manufacturer: [INTERN] Contains manufacturer information
1097 * @manufacturer.desc: [INTERN] Contains manufacturer's description
1098 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1099 * @lock_area: [REPLACEABLE] specific NAND chip lock operation
1100 * @unlock_area: [REPLACEABLE] specific NAND chip unlock operation
1104 struct nand_device base;
1106 struct nand_legacy legacy;
1108 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1110 unsigned int options;
1111 unsigned int bbt_options;
1114 int phys_erase_shift;
1115 int bbt_erase_shift;
1121 unsigned int bitflips;
1126 int onfi_timing_mode_default;
1127 unsigned int badblockpos;
1131 struct nand_parameters parameters;
1133 struct nand_data_interface data_interface;
1140 unsigned int suspended : 1;
1141 int (*suspend)(struct nand_chip *chip);
1142 void (*resume)(struct nand_chip *chip);
1145 struct nand_controller *controller;
1147 struct nand_ecc_ctrl ecc;
1148 unsigned long buf_align;
1151 struct nand_bbt_descr *bbt_td;
1152 struct nand_bbt_descr *bbt_md;
1154 struct nand_bbt_descr *badblock_pattern;
1159 const struct nand_manufacturer *desc;
1163 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1164 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1167 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1168 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1170 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1172 return container_of(mtd, struct nand_chip, base.mtd);
1175 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1177 return &chip->base.mtd;
1180 static inline void *nand_get_controller_data(struct nand_chip *chip)
1185 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1190 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1193 chip->manufacturer.priv = priv;
1196 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1198 return chip->manufacturer.priv;
1201 static inline void nand_set_flash_node(struct nand_chip *chip,
1202 struct device_node *np)
1204 mtd_set_of_node(nand_to_mtd(chip), np);
1207 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1209 return mtd_get_of_node(nand_to_mtd(chip));
1213 * A helper for defining older NAND chips where the second ID byte fully
1214 * defined the chip, including the geometry (chip size, eraseblock size, page
1215 * size). All these chips have 512 bytes NAND page size.
1217 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1218 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1219 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1222 * A helper for defining newer chips which report their page size and
1223 * eraseblock size via the extended ID bytes.
1225 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1226 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1227 * device ID now only represented a particular total chip size (and voltage,
1228 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1229 * using the same device ID.
1231 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1232 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1235 #define NAND_ECC_INFO(_strength, _step) \
1236 { .strength_ds = (_strength), .step_ds = (_step) }
1237 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1238 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1241 * struct nand_flash_dev - NAND Flash Device ID Structure
1242 * @name: a human-readable name of the NAND chip
1243 * @dev_id: the device ID (the second byte of the full chip ID array)
1244 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1245 * memory address as ``id[0]``)
1246 * @dev_id: device ID part of the full chip ID array (refers the same memory
1247 * address as ``id[1]``)
1248 * @id: full device ID array
1249 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1250 * well as the eraseblock size) is determined from the extended NAND
1252 * @chipsize: total chip size in MiB
1253 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1254 * @options: stores various chip bit options
1255 * @id_len: The valid length of the @id.
1256 * @oobsize: OOB size
1257 * @ecc: ECC correctability and step information from the datasheet.
1258 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1259 * @ecc_strength_ds in nand_chip{}.
1260 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1261 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1262 * For example, the "4bit ECC for each 512Byte" can be set with
1263 * NAND_ECC_INFO(4, 512).
1264 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1265 * reset. Should be deduced from timings described
1269 struct nand_flash_dev {
1276 uint8_t id[NAND_MAX_ID_LEN];
1278 unsigned int pagesize;
1279 unsigned int chipsize;
1280 unsigned int erasesize;
1281 unsigned int options;
1285 uint16_t strength_ds;
1288 int onfi_timing_mode_default;
1291 int nand_create_bbt(struct nand_chip *chip);
1294 * Check if it is a SLC nand.
1295 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1296 * We do not distinguish the MLC and TLC now.
1298 static inline bool nand_is_slc(struct nand_chip *chip)
1300 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1301 "chip->bits_per_cell is used uninitialized\n");
1302 return nanddev_bits_per_cell(&chip->base) == 1;
1306 * Check if the opcode's address should be sent only on the lower 8 bits
1307 * @command: opcode to check
1309 static inline int nand_opcode_8bits(unsigned int command)
1312 case NAND_CMD_READID:
1313 case NAND_CMD_PARAM:
1314 case NAND_CMD_GET_FEATURES:
1315 case NAND_CMD_SET_FEATURES:
1323 int nand_check_erased_ecc_chunk(void *data, int datalen,
1324 void *ecc, int ecclen,
1325 void *extraoob, int extraooblen,
1328 int nand_ecc_choose_conf(struct nand_chip *chip,
1329 const struct nand_ecc_caps *caps, int oobavail);
1331 /* Default write_oob implementation */
1332 int nand_write_oob_std(struct nand_chip *chip, int page);
1334 /* Default read_oob implementation */
1335 int nand_read_oob_std(struct nand_chip *chip, int page);
1337 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1338 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1339 u8 *subfeature_param);
1341 /* read_page_raw implementations */
1342 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1344 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1345 int oob_required, int page);
1347 /* write_page_raw implementations */
1348 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1349 int oob_required, int page);
1350 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1351 int oob_required, int page);
1353 /* Reset and initialize a NAND device */
1354 int nand_reset(struct nand_chip *chip, int chipnr);
1356 /* NAND operation helpers */
1357 int nand_reset_op(struct nand_chip *chip);
1358 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1360 int nand_status_op(struct nand_chip *chip, u8 *status);
1361 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1362 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1363 unsigned int offset_in_page, void *buf, unsigned int len);
1364 int nand_change_read_column_op(struct nand_chip *chip,
1365 unsigned int offset_in_page, void *buf,
1366 unsigned int len, bool force_8bit);
1367 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1368 unsigned int offset_in_page, void *buf, unsigned int len);
1369 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1370 unsigned int offset_in_page, const void *buf,
1372 int nand_prog_page_end_op(struct nand_chip *chip);
1373 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1374 unsigned int offset_in_page, const void *buf,
1376 int nand_change_write_column_op(struct nand_chip *chip,
1377 unsigned int offset_in_page, const void *buf,
1378 unsigned int len, bool force_8bit);
1379 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1380 bool force_8bit, bool check_only);
1381 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1382 unsigned int len, bool force_8bit);
1384 /* Scan and identify a NAND device */
1385 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1386 struct nand_flash_dev *ids);
1388 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1390 return nand_scan_with_ids(chip, max_chips, NULL);
1393 /* Internal helper for board drivers which need to override command function */
1394 void nand_wait_ready(struct nand_chip *chip);
1397 * Free resources held by the NAND device, must be called on error after a
1398 * sucessful nand_scan().
1400 void nand_cleanup(struct nand_chip *chip);
1403 * External helper for controller drivers that have to implement the WAITRDY
1404 * instruction and have no physical pin to check it.
1406 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1408 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1409 unsigned long timeout_ms);
1411 /* Select/deselect a NAND target. */
1412 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1413 void nand_deselect_target(struct nand_chip *chip);
1416 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1417 unsigned int src_off, unsigned int nbits);
1420 * nand_get_data_buf() - Get the internal page buffer
1421 * @chip: NAND chip object
1423 * Returns the pre-allocated page buffer after invalidating the cache. This
1424 * function should be used by drivers that do not want to allocate their own
1425 * bounce buffer and still need such a buffer for specific operations (most
1426 * commonly when reading OOB data only).
1428 * Be careful to never call this function in the write/write_oob path, because
1429 * the core may have placed the data to be written out in this buffer.
1431 * Return: pointer to the page cache buffer
1433 static inline void *nand_get_data_buf(struct nand_chip *chip)
1435 chip->pagecache.page = -1;
1437 return chip->data_buf;
1440 #endif /* __LINUX_MTD_RAWNAND_H */