2 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
3 * Steven J. Hill <sjhill@realitydiluted.com>
4 * Thomas Gleixner <tglx@linutronix.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_RAWNAND_H
17 #define __LINUX_MTD_RAWNAND_H
19 #include <linux/wait.h>
20 #include <linux/spinlock.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/flashchip.h>
23 #include <linux/mtd/bbm.h>
25 #include <linux/types.h>
28 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 int nand_scan_with_ids(struct nand_chip *chip, int max_chips,
32 struct nand_flash_dev *ids);
34 static inline int nand_scan(struct nand_chip *chip, int max_chips)
36 return nand_scan_with_ids(chip, max_chips, NULL);
39 /* Internal helper for board drivers which need to override command function */
40 void nand_wait_ready(struct nand_chip *chip);
42 /* The maximum number of NAND chips in an array */
43 #define NAND_MAX_CHIPS 8
46 * Constants for hardware specific CLE/ALE/NCE function
48 * These are bits which can be or'ed to set/clear multiple
51 /* Select the chip by setting nCE to low */
53 /* Select the command latch by setting CLE to high */
55 /* Select the address latch by setting ALE to high */
58 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
59 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
60 #define NAND_CTRL_CHANGE 0x80
63 * Standard NAND flash commands
65 #define NAND_CMD_READ0 0
66 #define NAND_CMD_READ1 1
67 #define NAND_CMD_RNDOUT 5
68 #define NAND_CMD_PAGEPROG 0x10
69 #define NAND_CMD_READOOB 0x50
70 #define NAND_CMD_ERASE1 0x60
71 #define NAND_CMD_STATUS 0x70
72 #define NAND_CMD_SEQIN 0x80
73 #define NAND_CMD_RNDIN 0x85
74 #define NAND_CMD_READID 0x90
75 #define NAND_CMD_ERASE2 0xd0
76 #define NAND_CMD_PARAM 0xec
77 #define NAND_CMD_GET_FEATURES 0xee
78 #define NAND_CMD_SET_FEATURES 0xef
79 #define NAND_CMD_RESET 0xff
81 /* Extended commands for large page devices */
82 #define NAND_CMD_READSTART 0x30
83 #define NAND_CMD_RNDOUTSTART 0xE0
84 #define NAND_CMD_CACHEDPROG 0x15
86 #define NAND_CMD_NONE -1
89 #define NAND_STATUS_FAIL 0x01
90 #define NAND_STATUS_FAIL_N1 0x02
91 #define NAND_STATUS_TRUE_READY 0x20
92 #define NAND_STATUS_READY 0x40
93 #define NAND_STATUS_WP 0x80
95 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * Constants for ECC_MODES
104 NAND_ECC_HW_SYNDROME,
105 NAND_ECC_HW_OOB_FIRST,
117 * Constants for Hardware ECC
119 /* Reset Hardware ECC for read */
120 #define NAND_ECC_READ 0
121 /* Reset Hardware ECC for write */
122 #define NAND_ECC_WRITE 1
123 /* Enable Hardware ECC before syndrome is read back from flash */
124 #define NAND_ECC_READSYN 2
127 * Enable generic NAND 'page erased' check. This check is only done when
128 * ecc.correct() returns -EBADMSG.
129 * Set this flag if your implementation does not fix bitflips in erased
130 * pages and you want to rely on the default implementation.
132 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
133 #define NAND_ECC_MAXIMIZE BIT(1)
135 /* Bit mask for flags passed to do_nand_read_ecc */
136 #define NAND_GET_DEVICE 0x80
140 * Option constants for bizarre disfunctionality and real
143 /* Buswidth is 16 bit */
144 #define NAND_BUSWIDTH_16 0x00000002
145 /* Chip has cache program function */
146 #define NAND_CACHEPRG 0x00000008
148 * Chip requires ready check on read (for auto-incremented sequential read).
149 * True only for small page devices; large page devices do not support
152 #define NAND_NEED_READRDY 0x00000100
154 /* Chip does not allow subpage writes */
155 #define NAND_NO_SUBPAGE_WRITE 0x00000200
157 /* Device is one of 'new' xD cards that expose fake nand command set */
158 #define NAND_BROKEN_XD 0x00000400
160 /* Device behaves just like nand, but is readonly */
161 #define NAND_ROM 0x00000800
163 /* Device supports subpage reads */
164 #define NAND_SUBPAGE_READ 0x00001000
167 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
170 #define NAND_NEED_SCRAMBLING 0x00002000
172 /* Device needs 3rd row address cycle */
173 #define NAND_ROW_ADDR_3 0x00004000
175 /* Options valid for Samsung large page devices */
176 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
178 /* Macros to identify the above */
179 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
180 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
181 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
183 /* Non chip related options */
184 /* This option skips the bbt scan during initialization. */
185 #define NAND_SKIP_BBTSCAN 0x00010000
186 /* Chip may not exist, so silence any errors in scan */
187 #define NAND_SCAN_SILENT_NODEV 0x00040000
189 * Autodetect nand buswidth with readid/onfi.
190 * This suppose the driver will configure the hardware in 8 bits mode
191 * when calling nand_scan_ident, and update its configuration
192 * before calling nand_scan_tail.
194 #define NAND_BUSWIDTH_AUTO 0x00080000
196 * This option could be defined by controller drivers to protect against
197 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
199 #define NAND_USE_BOUNCE_BUFFER 0x00100000
202 * In case your controller is implementing ->cmd_ctrl() and is relying on the
203 * default ->cmdfunc() implementation, you may want to let the core handle the
204 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
206 * If your controller already takes care of this delay, you don't need to set
209 #define NAND_WAIT_TCCS 0x00200000
212 * Whether the NAND chip is a boot medium. Drivers might use this information
213 * to select ECC algorithms supported by the boot ROM or similar restrictions.
215 #define NAND_IS_BOOT_MEDIUM 0x00400000
217 /* Options set by nand scan */
218 /* Nand scan has allocated controller struct */
219 #define NAND_CONTROLLER_ALLOC 0x80000000
221 /* Cell info constants */
222 #define NAND_CI_CHIPNR_MSK 0x03
223 #define NAND_CI_CELLTYPE_MSK 0x0C
224 #define NAND_CI_CELLTYPE_SHIFT 2
229 /* ONFI version bits */
230 #define ONFI_VERSION_1_0 BIT(1)
231 #define ONFI_VERSION_2_0 BIT(2)
232 #define ONFI_VERSION_2_1 BIT(3)
233 #define ONFI_VERSION_2_2 BIT(4)
234 #define ONFI_VERSION_2_3 BIT(5)
235 #define ONFI_VERSION_3_0 BIT(6)
236 #define ONFI_VERSION_3_1 BIT(7)
237 #define ONFI_VERSION_3_2 BIT(8)
238 #define ONFI_VERSION_4_0 BIT(9)
241 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
242 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
244 /* ONFI timing mode, used in both asynchronous and synchronous mode */
245 #define ONFI_TIMING_MODE_0 (1 << 0)
246 #define ONFI_TIMING_MODE_1 (1 << 1)
247 #define ONFI_TIMING_MODE_2 (1 << 2)
248 #define ONFI_TIMING_MODE_3 (1 << 3)
249 #define ONFI_TIMING_MODE_4 (1 << 4)
250 #define ONFI_TIMING_MODE_5 (1 << 5)
251 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
253 /* ONFI feature number/address */
254 #define ONFI_FEATURE_NUMBER 256
255 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
257 /* Vendor-specific feature address (Micron) */
258 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
259 #define ONFI_FEATURE_ON_DIE_ECC 0x90
260 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
262 /* ONFI subfeature parameters length */
263 #define ONFI_SUBFEATURE_PARAM_LEN 4
265 /* ONFI optional commands SET/GET FEATURES supported? */
266 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
268 struct nand_onfi_params {
269 /* rev info and features block */
270 /* 'O' 'N' 'F' 'I' */
276 __le16 ext_param_page_length; /* since ONFI 2.1 */
277 u8 num_of_param_pages; /* since ONFI 2.1 */
280 /* manufacturer information block */
281 char manufacturer[12];
287 /* memory organization block */
288 __le32 byte_per_page;
289 __le16 spare_bytes_per_page;
290 __le32 data_bytes_per_ppage;
291 __le16 spare_bytes_per_ppage;
292 __le32 pages_per_block;
293 __le32 blocks_per_lun;
298 __le16 block_endurance;
299 u8 guaranteed_good_blocks;
300 __le16 guaranteed_block_endurance;
301 u8 programs_per_page;
308 /* electrical parameter block */
309 u8 io_pin_capacitance_max;
310 __le16 async_timing_mode;
311 __le16 program_cache_timing_mode;
316 __le16 src_sync_timing_mode;
317 u8 src_ssync_features;
318 __le16 clk_pin_capacitance_typ;
319 __le16 io_pin_capacitance_typ;
320 __le16 input_pin_capacitance_typ;
321 u8 input_pin_capacitance_max;
322 u8 driver_strength_support;
328 __le16 vendor_revision;
334 #define ONFI_CRC_BASE 0x4F4E
336 /* Extended ECC information Block Definition (since ONFI 2.1) */
337 struct onfi_ext_ecc_info {
341 __le16 block_endurance;
345 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
346 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
347 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
348 struct onfi_ext_section {
353 #define ONFI_EXT_SECTION_MAX 8
355 /* Extended Parameter Page Definition (since ONFI 2.1) */
356 struct onfi_ext_param_page {
358 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
360 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
363 * The actual size of the Extended Parameter Page is in
364 * @ext_param_page_length of nand_onfi_params{}.
365 * The following are the variable length sections.
366 * So we do not add any fields below. Please see the ONFI spec.
370 struct jedec_ecc_info {
374 __le16 block_endurance;
379 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
381 struct nand_jedec_params {
382 /* rev info and features block */
383 /* 'J' 'E' 'S' 'D' */
389 u8 num_of_param_pages;
392 /* manufacturer information block */
393 char manufacturer[12];
398 /* memory organization block */
399 __le32 byte_per_page;
400 __le16 spare_bytes_per_page;
402 __le32 pages_per_block;
403 __le32 blocks_per_lun;
407 u8 programs_per_page;
409 u8 multi_plane_op_attr;
412 /* electrical parameter block */
413 __le16 async_sdr_speed_grade;
414 __le16 toggle_ddr_speed_grade;
415 __le16 sync_ddr_speed_grade;
416 u8 async_sdr_features;
417 u8 toggle_ddr_features;
418 u8 sync_ddr_features;
422 __le16 t_r_multi_plane;
424 __le16 io_pin_capacitance_typ;
425 __le16 input_pin_capacitance_typ;
426 __le16 clk_pin_capacitance_typ;
427 u8 driver_strength_support;
431 /* ECC and endurance block */
432 u8 guaranteed_good_blocks;
433 __le16 guaranteed_block_endurance;
434 struct jedec_ecc_info ecc_info[4];
441 __le16 vendor_rev_num;
444 /* CRC for Parameter Page */
449 * struct onfi_params - ONFI specific parameters that will be reused
450 * @version: ONFI version (BCD encoded), 0 if ONFI is not supported
451 * @tPROG: Page program time
452 * @tBERS: Block erase time
453 * @tR: Page read time
454 * @tCCS: Change column setup time
455 * @async_timing_mode: Supported asynchronous timing mode
456 * @vendor_revision: Vendor specific revision number
457 * @vendor: Vendor specific data
465 u16 async_timing_mode;
471 * struct nand_parameters - NAND generic parameters from the parameter page
473 * @supports_set_get_features: The NAND chip supports setting/getting features
474 * @set_feature_list: Bitmap of features that can be set
475 * @get_feature_list: Bitmap of features that can be get
476 * @onfi: ONFI specific parameters
478 struct nand_parameters {
479 /* Generic parameters */
481 bool supports_set_get_features;
482 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
483 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
485 /* ONFI parameters */
486 struct onfi_params *onfi;
489 /* The maximum expected count of bytes in the NAND ID sequence */
490 #define NAND_MAX_ID_LEN 8
493 * struct nand_id - NAND id structure
494 * @data: buffer containing the id bytes.
498 u8 data[NAND_MAX_ID_LEN];
503 * struct nand_controller_ops - Controller operations
505 * @attach_chip: this method is called after the NAND detection phase after
506 * flash ID and MTD fields such as erase size, page size and OOB
507 * size have been set up. ECC requirements are available if
508 * provided by the NAND chip or device tree. Typically used to
509 * choose the appropriate ECC configuration and allocate
510 * associated resources.
511 * This hook is optional.
512 * @detach_chip: free all resources allocated/claimed in
513 * nand_controller_ops->attach_chip().
514 * This hook is optional.
516 struct nand_controller_ops {
517 int (*attach_chip)(struct nand_chip *chip);
518 void (*detach_chip)(struct nand_chip *chip);
522 * struct nand_controller - Structure used to describe a NAND controller
524 * @lock: protection lock
525 * @active: the mtd device which holds the controller currently
526 * @wq: wait queue to sleep on if a NAND operation is in
527 * progress used instead of the per chip wait queue
528 * when a hw controller is available.
529 * @ops: NAND controller operations.
531 struct nand_controller {
533 struct nand_chip *active;
534 wait_queue_head_t wq;
535 const struct nand_controller_ops *ops;
538 static inline void nand_controller_init(struct nand_controller *nfc)
541 spin_lock_init(&nfc->lock);
542 init_waitqueue_head(&nfc->wq);
546 * struct nand_ecc_step_info - ECC step information of ECC engine
547 * @stepsize: data bytes per ECC step
548 * @strengths: array of supported strengths
549 * @nstrengths: number of supported strengths
551 struct nand_ecc_step_info {
553 const int *strengths;
558 * struct nand_ecc_caps - capability of ECC engine
559 * @stepinfos: array of ECC step information
560 * @nstepinfos: number of ECC step information
561 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
563 struct nand_ecc_caps {
564 const struct nand_ecc_step_info *stepinfos;
566 int (*calc_ecc_bytes)(int step_size, int strength);
569 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
570 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
571 static const int __name##_strengths[] = { __VA_ARGS__ }; \
572 static const struct nand_ecc_step_info __name##_stepinfo = { \
573 .stepsize = __step, \
574 .strengths = __name##_strengths, \
575 .nstrengths = ARRAY_SIZE(__name##_strengths), \
577 static const struct nand_ecc_caps __name = { \
578 .stepinfos = &__name##_stepinfo, \
580 .calc_ecc_bytes = __calc, \
584 * struct nand_ecc_ctrl - Control structure for ECC
586 * @algo: ECC algorithm
587 * @steps: number of ECC steps per page
588 * @size: data bytes per ECC step
589 * @bytes: ECC bytes per step
590 * @strength: max number of correctible bits per ECC step
591 * @total: total number of ECC bytes per page
592 * @prepad: padding information for syndrome based ECC generators
593 * @postpad: padding information for syndrome based ECC generators
594 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
595 * @priv: pointer to private ECC control data
596 * @calc_buf: buffer for calculated ECC, size is oobsize.
597 * @code_buf: buffer for ECC read from flash, size is oobsize.
598 * @hwctl: function to control hardware ECC generator. Must only
599 * be provided if an hardware ECC is available
600 * @calculate: function for ECC calculation or readback from ECC hardware
601 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
602 * Should return a positive number representing the number of
603 * corrected bitflips, -EBADMSG if the number of bitflips exceed
604 * ECC strength, or any other error code if the error is not
605 * directly related to correction.
606 * If -EBADMSG is returned the input buffers should be left
608 * @read_page_raw: function to read a raw page without ECC. This function
609 * should hide the specific layout used by the ECC
610 * controller and always return contiguous in-band and
611 * out-of-band data even if they're not stored
612 * contiguously on the NAND chip (e.g.
613 * NAND_ECC_HW_SYNDROME interleaves in-band and
615 * @write_page_raw: function to write a raw page without ECC. This function
616 * should hide the specific layout used by the ECC
617 * controller and consider the passed data as contiguous
618 * in-band and out-of-band data. ECC controller is
619 * responsible for doing the appropriate transformations
620 * to adapt to its specific layout (e.g.
621 * NAND_ECC_HW_SYNDROME interleaves in-band and
623 * @read_page: function to read a page according to the ECC generator
624 * requirements; returns maximum number of bitflips corrected in
625 * any single ECC step, -EIO hw error
626 * @read_subpage: function to read parts of the page covered by ECC;
627 * returns same as read_page()
628 * @write_subpage: function to write parts of the page covered by ECC.
629 * @write_page: function to write a page according to the ECC generator
631 * @write_oob_raw: function to write chip OOB data without ECC
632 * @read_oob_raw: function to read chip OOB data without ECC
633 * @read_oob: function to read chip OOB data
634 * @write_oob: function to write chip OOB data
636 struct nand_ecc_ctrl {
637 nand_ecc_modes_t mode;
638 enum nand_ecc_algo algo;
646 unsigned int options;
650 void (*hwctl)(struct nand_chip *chip, int mode);
651 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
653 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
655 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
656 int oob_required, int page);
657 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
658 int oob_required, int page);
659 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
660 int oob_required, int page);
661 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
662 uint32_t len, uint8_t *buf, int page);
663 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
664 uint32_t data_len, const uint8_t *data_buf,
665 int oob_required, int page);
666 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
667 int oob_required, int page);
668 int (*write_oob_raw)(struct nand_chip *chip, int page);
669 int (*read_oob_raw)(struct nand_chip *chip, int page);
670 int (*read_oob)(struct nand_chip *chip, int page);
671 int (*write_oob)(struct nand_chip *chip, int page);
675 * struct nand_sdr_timings - SDR NAND chip timings
677 * This struct defines the timing requirements of a SDR NAND chip.
678 * These information can be found in every NAND datasheets and the timings
679 * meaning are described in the ONFI specifications:
680 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
683 * All these timings are expressed in picoseconds.
685 * @tBERS_max: Block erase time
686 * @tCCS_min: Change column setup time
687 * @tPROG_max: Page program time
688 * @tR_max: Page read time
689 * @tALH_min: ALE hold time
690 * @tADL_min: ALE to data loading time
691 * @tALS_min: ALE setup time
692 * @tAR_min: ALE to RE# delay
693 * @tCEA_max: CE# access time
694 * @tCEH_min: CE# high hold time
695 * @tCH_min: CE# hold time
696 * @tCHZ_max: CE# high to output hi-Z
697 * @tCLH_min: CLE hold time
698 * @tCLR_min: CLE to RE# delay
699 * @tCLS_min: CLE setup time
700 * @tCOH_min: CE# high to output hold
701 * @tCS_min: CE# setup time
702 * @tDH_min: Data hold time
703 * @tDS_min: Data setup time
704 * @tFEAT_max: Busy time for Set Features and Get Features
705 * @tIR_min: Output hi-Z to RE# low
706 * @tITC_max: Interface and Timing Mode Change time
707 * @tRC_min: RE# cycle time
708 * @tREA_max: RE# access time
709 * @tREH_min: RE# high hold time
710 * @tRHOH_min: RE# high to output hold
711 * @tRHW_min: RE# high to WE# low
712 * @tRHZ_max: RE# high to output hi-Z
713 * @tRLOH_min: RE# low to output hold
714 * @tRP_min: RE# pulse width
715 * @tRR_min: Ready to RE# low (data only)
716 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
717 * rising edge of R/B#.
718 * @tWB_max: WE# high to SR[6] low
719 * @tWC_min: WE# cycle time
720 * @tWH_min: WE# high hold time
721 * @tWHR_min: WE# high to RE# low
722 * @tWP_min: WE# pulse width
723 * @tWW_min: WP# transition to WE# low
725 struct nand_sdr_timings {
767 * enum nand_data_interface_type - NAND interface timing type
768 * @NAND_SDR_IFACE: Single Data Rate interface
770 enum nand_data_interface_type {
775 * struct nand_data_interface - NAND interface timing
776 * @type: type of the timing
777 * @timings: The timing, type according to @type
778 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
780 struct nand_data_interface {
781 enum nand_data_interface_type type;
783 struct nand_sdr_timings sdr;
788 * nand_get_sdr_timings - get SDR timing from data interface
789 * @conf: The data interface
791 static inline const struct nand_sdr_timings *
792 nand_get_sdr_timings(const struct nand_data_interface *conf)
794 if (conf->type != NAND_SDR_IFACE)
795 return ERR_PTR(-EINVAL);
797 return &conf->timings.sdr;
801 * struct nand_manufacturer_ops - NAND Manufacturer operations
802 * @detect: detect the NAND memory organization and capabilities
803 * @init: initialize all vendor specific fields (like the ->read_retry()
804 * implementation) if any.
805 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
806 * is here to let vendor specific code release those resources.
807 * @fixup_onfi_param_page: apply vendor specific fixups to the ONFI parameter
808 * page. This is called after the checksum is verified.
810 struct nand_manufacturer_ops {
811 void (*detect)(struct nand_chip *chip);
812 int (*init)(struct nand_chip *chip);
813 void (*cleanup)(struct nand_chip *chip);
814 void (*fixup_onfi_param_page)(struct nand_chip *chip,
815 struct nand_onfi_params *p);
819 * struct nand_op_cmd_instr - Definition of a command instruction
820 * @opcode: the command to issue in one cycle
822 struct nand_op_cmd_instr {
827 * struct nand_op_addr_instr - Definition of an address instruction
828 * @naddrs: length of the @addrs array
829 * @addrs: array containing the address cycles to issue
831 struct nand_op_addr_instr {
837 * struct nand_op_data_instr - Definition of a data instruction
838 * @len: number of data bytes to move
839 * @buf: buffer to fill
840 * @buf.in: buffer to fill when reading from the NAND chip
841 * @buf.out: buffer to read from when writing to the NAND chip
842 * @force_8bit: force 8-bit access
844 * Please note that "in" and "out" are inverted from the ONFI specification
845 * and are from the controller perspective, so a "in" is a read from the NAND
846 * chip while a "out" is a write to the NAND chip.
848 struct nand_op_data_instr {
858 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
859 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
861 struct nand_op_waitrdy_instr {
862 unsigned int timeout_ms;
866 * enum nand_op_instr_type - Definition of all instruction types
867 * @NAND_OP_CMD_INSTR: command instruction
868 * @NAND_OP_ADDR_INSTR: address instruction
869 * @NAND_OP_DATA_IN_INSTR: data in instruction
870 * @NAND_OP_DATA_OUT_INSTR: data out instruction
871 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
873 enum nand_op_instr_type {
876 NAND_OP_DATA_IN_INSTR,
877 NAND_OP_DATA_OUT_INSTR,
878 NAND_OP_WAITRDY_INSTR,
882 * struct nand_op_instr - Instruction object
883 * @type: the instruction type
884 * @ctx: extra data associated to the instruction. You'll have to use the
885 * appropriate element depending on @type
886 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
887 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
888 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
889 * or %NAND_OP_DATA_OUT_INSTR
890 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
891 * @delay_ns: delay the controller should apply after the instruction has been
892 * issued on the bus. Most modern controllers have internal timings
893 * control logic, and in this case, the controller driver can ignore
896 struct nand_op_instr {
897 enum nand_op_instr_type type;
899 struct nand_op_cmd_instr cmd;
900 struct nand_op_addr_instr addr;
901 struct nand_op_data_instr data;
902 struct nand_op_waitrdy_instr waitrdy;
904 unsigned int delay_ns;
908 * Special handling must be done for the WAITRDY timeout parameter as it usually
909 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
910 * tBERS (during an erase) which all of them are u64 values that cannot be
911 * divided by usual kernel macros and must be handled with the special
912 * DIV_ROUND_UP_ULL() macro.
914 * Cast to type of dividend is needed here to guarantee that the result won't
915 * be an unsigned long long when the dividend is an unsigned long (or smaller),
916 * which is what the compiler does when it sees ternary operator with 2
917 * different return types (picks the largest type to make sure there's no
920 #define __DIVIDE(dividend, divisor) ({ \
921 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
922 DIV_ROUND_UP(dividend, divisor) : \
923 DIV_ROUND_UP_ULL(dividend, divisor)); \
925 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
926 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
928 #define NAND_OP_CMD(id, ns) \
930 .type = NAND_OP_CMD_INSTR, \
931 .ctx.cmd.opcode = id, \
935 #define NAND_OP_ADDR(ncycles, cycles, ns) \
937 .type = NAND_OP_ADDR_INSTR, \
945 #define NAND_OP_DATA_IN(l, b, ns) \
947 .type = NAND_OP_DATA_IN_INSTR, \
951 .force_8bit = false, \
956 #define NAND_OP_DATA_OUT(l, b, ns) \
958 .type = NAND_OP_DATA_OUT_INSTR, \
962 .force_8bit = false, \
967 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
969 .type = NAND_OP_DATA_IN_INSTR, \
973 .force_8bit = true, \
978 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
980 .type = NAND_OP_DATA_OUT_INSTR, \
984 .force_8bit = true, \
989 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
991 .type = NAND_OP_WAITRDY_INSTR, \
992 .ctx.waitrdy.timeout_ms = tout_ms, \
997 * struct nand_subop - a sub operation
998 * @instrs: array of instructions
999 * @ninstrs: length of the @instrs array
1000 * @first_instr_start_off: offset to start from for the first instruction
1001 * of the sub-operation
1002 * @last_instr_end_off: offset to end at (excluded) for the last instruction
1003 * of the sub-operation
1005 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
1006 * address instructions.
1008 * When an operation cannot be handled as is by the NAND controller, it will
1009 * be split by the parser into sub-operations which will be passed to the
1010 * controller driver.
1013 const struct nand_op_instr *instrs;
1014 unsigned int ninstrs;
1015 unsigned int first_instr_start_off;
1016 unsigned int last_instr_end_off;
1019 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
1020 unsigned int op_id);
1021 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
1022 unsigned int op_id);
1023 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
1024 unsigned int op_id);
1025 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
1026 unsigned int op_id);
1029 * struct nand_op_parser_addr_constraints - Constraints for address instructions
1030 * @maxcycles: maximum number of address cycles the controller can issue in a
1033 struct nand_op_parser_addr_constraints {
1034 unsigned int maxcycles;
1038 * struct nand_op_parser_data_constraints - Constraints for data instructions
1039 * @maxlen: maximum data length that the controller can handle in a single step
1041 struct nand_op_parser_data_constraints {
1042 unsigned int maxlen;
1046 * struct nand_op_parser_pattern_elem - One element of a pattern
1047 * @type: the instructuction type
1048 * @optional: whether this element of the pattern is optional or mandatory
1049 * @ctx: address or data constraint
1050 * @ctx.addr: address constraint (number of cycles)
1051 * @ctx.data: data constraint (data length)
1053 struct nand_op_parser_pattern_elem {
1054 enum nand_op_instr_type type;
1057 struct nand_op_parser_addr_constraints addr;
1058 struct nand_op_parser_data_constraints data;
1062 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
1064 .type = NAND_OP_CMD_INSTR, \
1068 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
1070 .type = NAND_OP_ADDR_INSTR, \
1072 .ctx.addr.maxcycles = _maxcycles, \
1075 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
1077 .type = NAND_OP_DATA_IN_INSTR, \
1079 .ctx.data.maxlen = _maxlen, \
1082 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
1084 .type = NAND_OP_DATA_OUT_INSTR, \
1086 .ctx.data.maxlen = _maxlen, \
1089 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
1091 .type = NAND_OP_WAITRDY_INSTR, \
1096 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
1097 * @elems: array of pattern elements
1098 * @nelems: number of pattern elements in @elems array
1099 * @exec: the function that will issue a sub-operation
1101 * A pattern is a list of elements, each element reprensenting one instruction
1102 * with its constraints. The pattern itself is used by the core to match NAND
1103 * chip operation with NAND controller operations.
1104 * Once a match between a NAND controller operation pattern and a NAND chip
1105 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
1106 * hook is called so that the controller driver can issue the operation on the
1109 * Controller drivers should declare as many patterns as they support and pass
1110 * this list of patterns (created with the help of the following macro) to
1111 * the nand_op_parser_exec_op() helper.
1113 struct nand_op_parser_pattern {
1114 const struct nand_op_parser_pattern_elem *elems;
1115 unsigned int nelems;
1116 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
1119 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
1122 .elems = (struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
1123 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
1124 sizeof(struct nand_op_parser_pattern_elem), \
1128 * struct nand_op_parser - NAND controller operation parser descriptor
1129 * @patterns: array of supported patterns
1130 * @npatterns: length of the @patterns array
1132 * The parser descriptor is just an array of supported patterns which will be
1133 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
1134 * NAND operation (or tries to determine if a specific operation is supported).
1136 * It is worth mentioning that patterns will be tested in their declaration
1137 * order, and the first match will be taken, so it's important to order patterns
1138 * appropriately so that simple/inefficient patterns are placed at the end of
1139 * the list. Usually, this is where you put single instruction patterns.
1141 struct nand_op_parser {
1142 const struct nand_op_parser_pattern *patterns;
1143 unsigned int npatterns;
1146 #define NAND_OP_PARSER(...) \
1148 .patterns = (struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
1149 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
1150 sizeof(struct nand_op_parser_pattern), \
1154 * struct nand_operation - NAND operation descriptor
1155 * @instrs: array of instructions to execute
1156 * @ninstrs: length of the @instrs array
1158 * The actual operation structure that will be passed to chip->exec_op().
1160 struct nand_operation {
1161 const struct nand_op_instr *instrs;
1162 unsigned int ninstrs;
1165 #define NAND_OPERATION(_instrs) \
1167 .instrs = _instrs, \
1168 .ninstrs = ARRAY_SIZE(_instrs), \
1171 int nand_op_parser_exec_op(struct nand_chip *chip,
1172 const struct nand_op_parser *parser,
1173 const struct nand_operation *op, bool check_only);
1176 * struct nand_chip - NAND Private Flash Chip Data
1177 * @mtd: MTD device registered to the MTD framework
1178 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
1180 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
1182 * @read_byte: [REPLACEABLE] read one byte from the chip
1183 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
1185 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
1186 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
1187 * @select_chip: [REPLACEABLE] select chip nr
1188 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
1189 * @block_markbad: [REPLACEABLE] mark a block bad
1190 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
1191 * ALE/CLE/nCE. Also used to write command and address
1192 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
1193 * device ready/busy line. If set to NULL no access to
1194 * ready/busy is available and the ready/busy information
1195 * is read from the chip status register.
1196 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
1197 * commands to the chip.
1198 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
1200 * @exec_op: controller specific method to execute NAND operations.
1201 * This method replaces ->cmdfunc(),
1202 * ->{read,write}_{buf,byte,word}(), ->dev_ready() and
1204 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
1205 * setting the read-retry mode. Mostly needed for MLC NAND.
1206 * @ecc: [BOARDSPECIFIC] ECC control structure
1207 * @buf_align: minimum buffer alignment required by a platform
1208 * @dummy_controller: dummy controller implementation for drivers that can
1209 * only control a single chip
1210 * @erase: [REPLACEABLE] erase function
1211 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
1212 * data from array to read regs (tR).
1213 * @state: [INTERN] the current state of the NAND device
1214 * @oob_poi: "poison value buffer," used for laying out OOB data
1216 * @page_shift: [INTERN] number of address bits in a page (column
1218 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
1219 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
1220 * @chip_shift: [INTERN] number of address bits in one chip
1221 * @options: [BOARDSPECIFIC] various chip options. They can partly
1222 * be set to inform nand_scan about special functionality.
1223 * See the defines for further explanation.
1224 * @bbt_options: [INTERN] bad block specific options. All options used
1225 * here must come from bbm.h. By default, these options
1226 * will be copied to the appropriate nand_bbt_descr's.
1227 * @badblockpos: [INTERN] position of the bad block marker in the oob
1229 * @badblockbits: [INTERN] minimum number of set bits in a good block's
1230 * bad block marker position; i.e., BBM == 11110111b is
1231 * not bad when badblockbits == 7
1232 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
1233 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
1234 * Minimum amount of bit errors per @ecc_step_ds guaranteed
1235 * to be correctable. If unknown, set to zero.
1236 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
1237 * also from the datasheet. It is the recommended ECC step
1238 * size, if known; if unknown, set to zero.
1239 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1240 * set to the actually used ONFI mode if the chip is
1241 * ONFI compliant or deduced from the datasheet if
1242 * the NAND chip is not ONFI compliant.
1243 * @numchips: [INTERN] number of physical chips
1244 * @chipsize: [INTERN] the size of one chip for multichip arrays
1245 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
1246 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
1247 * @pagebuf: [INTERN] holds the pagenumber which is currently in
1249 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
1250 * currently in data_buf.
1251 * @subpagesize: [INTERN] holds the subpagesize
1252 * @id: [INTERN] holds NAND ID
1253 * @parameters: [INTERN] holds generic parameters under an easily
1255 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
1256 * this nand device will encounter their life times.
1257 * @blocks_per_die: [INTERN] The number of PEBs in a die
1258 * @data_interface: [INTERN] NAND interface timing information
1259 * @read_retries: [INTERN] the number of read retry modes supported
1260 * @set_features: [REPLACEABLE] set the NAND chip features
1261 * @get_features: [REPLACEABLE] get the NAND chip features
1262 * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
1263 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
1264 * means the configuration should not be applied but
1266 * @bbt: [INTERN] bad block table pointer
1267 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
1269 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
1270 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
1272 * @controller: [REPLACEABLE] a pointer to a hardware controller
1273 * structure which is shared among multiple independent
1275 * @priv: [OPTIONAL] pointer to private chip data
1276 * @manufacturer: [INTERN] Contains manufacturer information
1277 * @manufacturer.desc: [INTERN] Contains manufacturer's description
1278 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1282 struct mtd_info mtd;
1283 void __iomem *IO_ADDR_R;
1284 void __iomem *IO_ADDR_W;
1286 uint8_t (*read_byte)(struct nand_chip *chip);
1287 void (*write_byte)(struct nand_chip *chip, uint8_t byte);
1288 void (*write_buf)(struct nand_chip *chip, const uint8_t *buf, int len);
1289 void (*read_buf)(struct nand_chip *chip, uint8_t *buf, int len);
1290 void (*select_chip)(struct nand_chip *chip, int cs);
1291 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1292 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1293 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1294 int (*dev_ready)(struct nand_chip *chip);
1295 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1297 int (*waitfunc)(struct nand_chip *chip);
1298 int (*exec_op)(struct nand_chip *chip,
1299 const struct nand_operation *op,
1301 int (*erase)(struct nand_chip *chip, int page);
1302 int (*set_features)(struct nand_chip *chip, int feature_addr,
1303 uint8_t *subfeature_para);
1304 int (*get_features)(struct nand_chip *chip, int feature_addr,
1305 uint8_t *subfeature_para);
1306 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1307 int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
1308 const struct nand_data_interface *conf);
1311 unsigned int options;
1312 unsigned int bbt_options;
1315 int phys_erase_shift;
1316 int bbt_erase_shift;
1323 unsigned int pagebuf_bitflips;
1325 uint8_t bits_per_cell;
1326 uint16_t ecc_strength_ds;
1327 uint16_t ecc_step_ds;
1328 int onfi_timing_mode_default;
1333 struct nand_parameters parameters;
1337 struct nand_data_interface data_interface;
1344 struct nand_controller *controller;
1346 struct nand_ecc_ctrl ecc;
1347 unsigned long buf_align;
1348 struct nand_controller dummy_controller;
1351 struct nand_bbt_descr *bbt_td;
1352 struct nand_bbt_descr *bbt_md;
1354 struct nand_bbt_descr *badblock_pattern;
1359 const struct nand_manufacturer *desc;
1364 static inline int nand_exec_op(struct nand_chip *chip,
1365 const struct nand_operation *op)
1370 return chip->exec_op(chip, op, false);
1373 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1374 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1376 static inline void nand_set_flash_node(struct nand_chip *chip,
1377 struct device_node *np)
1379 mtd_set_of_node(&chip->mtd, np);
1382 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1384 return mtd_get_of_node(&chip->mtd);
1387 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1389 return container_of(mtd, struct nand_chip, mtd);
1392 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1397 static inline void *nand_get_controller_data(struct nand_chip *chip)
1402 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1407 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1410 chip->manufacturer.priv = priv;
1413 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1415 return chip->manufacturer.priv;
1419 * NAND Flash Manufacturer ID Codes
1421 #define NAND_MFR_TOSHIBA 0x98
1422 #define NAND_MFR_ESMT 0xc8
1423 #define NAND_MFR_SAMSUNG 0xec
1424 #define NAND_MFR_FUJITSU 0x04
1425 #define NAND_MFR_NATIONAL 0x8f
1426 #define NAND_MFR_RENESAS 0x07
1427 #define NAND_MFR_STMICRO 0x20
1428 #define NAND_MFR_HYNIX 0xad
1429 #define NAND_MFR_MICRON 0x2c
1430 #define NAND_MFR_AMD 0x01
1431 #define NAND_MFR_MACRONIX 0xc2
1432 #define NAND_MFR_EON 0x92
1433 #define NAND_MFR_SANDISK 0x45
1434 #define NAND_MFR_INTEL 0x89
1435 #define NAND_MFR_ATO 0x9b
1436 #define NAND_MFR_WINBOND 0xef
1440 * A helper for defining older NAND chips where the second ID byte fully
1441 * defined the chip, including the geometry (chip size, eraseblock size, page
1442 * size). All these chips have 512 bytes NAND page size.
1444 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1445 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1446 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1449 * A helper for defining newer chips which report their page size and
1450 * eraseblock size via the extended ID bytes.
1452 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1453 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1454 * device ID now only represented a particular total chip size (and voltage,
1455 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1456 * using the same device ID.
1458 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1459 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1462 #define NAND_ECC_INFO(_strength, _step) \
1463 { .strength_ds = (_strength), .step_ds = (_step) }
1464 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1465 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1468 * struct nand_flash_dev - NAND Flash Device ID Structure
1469 * @name: a human-readable name of the NAND chip
1470 * @dev_id: the device ID (the second byte of the full chip ID array)
1471 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1472 * memory address as @id[0])
1473 * @dev_id: device ID part of the full chip ID array (refers the same memory
1474 * address as @id[1])
1475 * @id: full device ID array
1476 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1477 * well as the eraseblock size) is determined from the extended NAND
1479 * @chipsize: total chip size in MiB
1480 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1481 * @options: stores various chip bit options
1482 * @id_len: The valid length of the @id.
1483 * @oobsize: OOB size
1484 * @ecc: ECC correctability and step information from the datasheet.
1485 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1486 * @ecc_strength_ds in nand_chip{}.
1487 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1488 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1489 * For example, the "4bit ECC for each 512Byte" can be set with
1490 * NAND_ECC_INFO(4, 512).
1491 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1492 * reset. Should be deduced from timings described
1496 struct nand_flash_dev {
1503 uint8_t id[NAND_MAX_ID_LEN];
1505 unsigned int pagesize;
1506 unsigned int chipsize;
1507 unsigned int erasesize;
1508 unsigned int options;
1512 uint16_t strength_ds;
1515 int onfi_timing_mode_default;
1519 * struct nand_manufacturer - NAND Flash Manufacturer structure
1520 * @name: Manufacturer name
1521 * @id: manufacturer ID code of device.
1522 * @ops: manufacturer operations
1524 struct nand_manufacturer {
1527 const struct nand_manufacturer_ops *ops;
1530 const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1532 static inline const char *
1533 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1535 return manufacturer ? manufacturer->name : "Unknown";
1538 extern struct nand_flash_dev nand_flash_ids[];
1540 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1541 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1542 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1543 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1544 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1545 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1547 int nand_create_bbt(struct nand_chip *chip);
1548 int nand_markbad_bbt(struct nand_chip *chip, loff_t offs);
1549 int nand_isreserved_bbt(struct nand_chip *chip, loff_t offs);
1550 int nand_isbad_bbt(struct nand_chip *chip, loff_t offs, int allowbbt);
1551 int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
1555 * struct platform_nand_chip - chip level device structure
1556 * @nr_chips: max. number of chips to scan for
1557 * @chip_offset: chip number offset
1558 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1559 * @partitions: mtd partition list
1560 * @chip_delay: R/B delay value in us
1561 * @options: Option flags, e.g. 16bit buswidth
1562 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1563 * @part_probe_types: NULL-terminated array of probe types
1565 struct platform_nand_chip {
1569 struct mtd_partition *partitions;
1571 unsigned int options;
1572 unsigned int bbt_options;
1573 const char **part_probe_types;
1576 /* Keep gcc happy */
1577 struct platform_device;
1580 * struct platform_nand_ctrl - controller level device structure
1581 * @probe: platform specific function to probe/setup hardware
1582 * @remove: platform specific function to remove/teardown hardware
1583 * @dev_ready: platform specific function to read ready/busy pin
1584 * @select_chip: platform specific chip select function
1585 * @cmd_ctrl: platform specific function for controlling
1586 * ALE/CLE/nCE. Also used to write command and address
1587 * @write_buf: platform specific function for write buffer
1588 * @read_buf: platform specific function for read buffer
1589 * @priv: private data to transport driver specific settings
1591 * All fields are optional and depend on the hardware driver requirements
1593 struct platform_nand_ctrl {
1594 int (*probe)(struct platform_device *pdev);
1595 void (*remove)(struct platform_device *pdev);
1596 int (*dev_ready)(struct nand_chip *chip);
1597 void (*select_chip)(struct nand_chip *chip, int cs);
1598 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1599 void (*write_buf)(struct nand_chip *chip, const uint8_t *buf, int len);
1600 void (*read_buf)(struct nand_chip *chip, uint8_t *buf, int len);
1605 * struct platform_nand_data - container structure for platform-specific data
1606 * @chip: chip level chip structure
1607 * @ctrl: controller level device structure
1609 struct platform_nand_data {
1610 struct platform_nand_chip chip;
1611 struct platform_nand_ctrl ctrl;
1614 /* return the supported asynchronous timing mode. */
1615 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1617 if (!chip->parameters.onfi)
1618 return ONFI_TIMING_MODE_UNKNOWN;
1620 return chip->parameters.onfi->async_timing_mode;
1623 int onfi_fill_data_interface(struct nand_chip *chip,
1624 enum nand_data_interface_type type,
1628 * Check if it is a SLC nand.
1629 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1630 * We do not distinguish the MLC and TLC now.
1632 static inline bool nand_is_slc(struct nand_chip *chip)
1634 WARN(chip->bits_per_cell == 0,
1635 "chip->bits_per_cell is used uninitialized\n");
1636 return chip->bits_per_cell == 1;
1640 * Check if the opcode's address should be sent only on the lower 8 bits
1641 * @command: opcode to check
1643 static inline int nand_opcode_8bits(unsigned int command)
1646 case NAND_CMD_READID:
1647 case NAND_CMD_PARAM:
1648 case NAND_CMD_GET_FEATURES:
1649 case NAND_CMD_SET_FEATURES:
1657 /* get timing characteristics from ONFI timing mode. */
1658 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1660 int nand_check_erased_ecc_chunk(void *data, int datalen,
1661 void *ecc, int ecclen,
1662 void *extraoob, int extraooblen,
1665 int nand_ecc_choose_conf(struct nand_chip *chip,
1666 const struct nand_ecc_caps *caps, int oobavail);
1668 /* Default write_oob implementation */
1669 int nand_write_oob_std(struct nand_chip *chip, int page);
1671 /* Default write_oob syndrome implementation */
1672 int nand_write_oob_syndrome(struct nand_chip *chip, int page);
1674 /* Default read_oob implementation */
1675 int nand_read_oob_std(struct nand_chip *chip, int page);
1677 /* Default read_oob syndrome implementation */
1678 int nand_read_oob_syndrome(struct nand_chip *chip, int page);
1680 /* Wrapper to use in order for controllers/vendors to GET/SET FEATURES */
1681 int nand_get_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1682 int nand_set_features(struct nand_chip *chip, int addr, u8 *subfeature_param);
1683 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1684 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1685 u8 *subfeature_param);
1687 /* Default read_page_raw implementation */
1688 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1690 int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,
1691 int oob_required, int page);
1693 /* Default write_page_raw implementation */
1694 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1695 int oob_required, int page);
1696 int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,
1697 int oob_required, int page);
1699 /* Reset and initialize a NAND device */
1700 int nand_reset(struct nand_chip *chip, int chipnr);
1702 /* NAND operation helpers */
1703 int nand_reset_op(struct nand_chip *chip);
1704 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1706 int nand_status_op(struct nand_chip *chip, u8 *status);
1707 int nand_exit_status_op(struct nand_chip *chip);
1708 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1709 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1710 unsigned int offset_in_page, void *buf, unsigned int len);
1711 int nand_change_read_column_op(struct nand_chip *chip,
1712 unsigned int offset_in_page, void *buf,
1713 unsigned int len, bool force_8bit);
1714 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1715 unsigned int offset_in_page, void *buf, unsigned int len);
1716 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1717 unsigned int offset_in_page, const void *buf,
1719 int nand_prog_page_end_op(struct nand_chip *chip);
1720 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1721 unsigned int offset_in_page, const void *buf,
1723 int nand_change_write_column_op(struct nand_chip *chip,
1724 unsigned int offset_in_page, const void *buf,
1725 unsigned int len, bool force_8bit);
1726 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1728 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1729 unsigned int len, bool force_8bit);
1732 * Free resources held by the NAND device, must be called on error after a
1733 * sucessful nand_scan().
1735 void nand_cleanup(struct nand_chip *chip);
1736 /* Unregister the MTD device and calls nand_cleanup() */
1737 void nand_release(struct nand_chip *chip);
1739 /* Default extended ID decoding function */
1740 void nand_decode_ext_id(struct nand_chip *chip);
1743 * External helper for controller drivers that have to implement the WAITRDY
1744 * instruction and have no physical pin to check it.
1746 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1748 #endif /* __LINUX_MTD_RAWNAND_H */