1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
8 * Contains standard defines and IDs for NAND flash devices
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/flashchip.h>
18 #include <linux/mtd/bbm.h>
19 #include <linux/mtd/jedec.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/onfi.h>
22 #include <linux/mutex.h>
24 #include <linux/types.h>
28 /* The maximum number of NAND chips in an array */
29 #define NAND_MAX_CHIPS 8
32 * Constants for hardware specific CLE/ALE/NCE function
34 * These are bits which can be or'ed to set/clear multiple
37 /* Select the chip by setting nCE to low */
39 /* Select the command latch by setting CLE to high */
41 /* Select the address latch by setting ALE to high */
44 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
45 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
46 #define NAND_CTRL_CHANGE 0x80
49 * Standard NAND flash commands
51 #define NAND_CMD_READ0 0
52 #define NAND_CMD_READ1 1
53 #define NAND_CMD_RNDOUT 5
54 #define NAND_CMD_PAGEPROG 0x10
55 #define NAND_CMD_READOOB 0x50
56 #define NAND_CMD_ERASE1 0x60
57 #define NAND_CMD_STATUS 0x70
58 #define NAND_CMD_SEQIN 0x80
59 #define NAND_CMD_RNDIN 0x85
60 #define NAND_CMD_READID 0x90
61 #define NAND_CMD_ERASE2 0xd0
62 #define NAND_CMD_PARAM 0xec
63 #define NAND_CMD_GET_FEATURES 0xee
64 #define NAND_CMD_SET_FEATURES 0xef
65 #define NAND_CMD_RESET 0xff
67 /* Extended commands for large page devices */
68 #define NAND_CMD_READSTART 0x30
69 #define NAND_CMD_RNDOUTSTART 0xE0
70 #define NAND_CMD_CACHEDPROG 0x15
72 #define NAND_CMD_NONE -1
75 #define NAND_STATUS_FAIL 0x01
76 #define NAND_STATUS_FAIL_N1 0x02
77 #define NAND_STATUS_TRUE_READY 0x20
78 #define NAND_STATUS_READY 0x40
79 #define NAND_STATUS_WP 0x80
81 #define NAND_DATA_IFACE_CHECK_ONLY -1
84 * Constants for ECC_MODES
91 NAND_ECC_HW_OOB_FIRST,
103 * Constants for Hardware ECC
105 /* Reset Hardware ECC for read */
106 #define NAND_ECC_READ 0
107 /* Reset Hardware ECC for write */
108 #define NAND_ECC_WRITE 1
109 /* Enable Hardware ECC before syndrome is read back from flash */
110 #define NAND_ECC_READSYN 2
113 * Enable generic NAND 'page erased' check. This check is only done when
114 * ecc.correct() returns -EBADMSG.
115 * Set this flag if your implementation does not fix bitflips in erased
116 * pages and you want to rely on the default implementation.
118 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
119 #define NAND_ECC_MAXIMIZE BIT(1)
122 * When using software implementation of Hamming, we can specify which byte
123 * ordering should be used.
125 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
128 * Option constants for bizarre disfunctionality and real
131 /* Buswidth is 16 bit */
132 #define NAND_BUSWIDTH_16 0x00000002
133 /* Chip has cache program function */
134 #define NAND_CACHEPRG 0x00000008
136 * Chip requires ready check on read (for auto-incremented sequential read).
137 * True only for small page devices; large page devices do not support
140 #define NAND_NEED_READRDY 0x00000100
142 /* Chip does not allow subpage writes */
143 #define NAND_NO_SUBPAGE_WRITE 0x00000200
145 /* Device is one of 'new' xD cards that expose fake nand command set */
146 #define NAND_BROKEN_XD 0x00000400
148 /* Device behaves just like nand, but is readonly */
149 #define NAND_ROM 0x00000800
151 /* Device supports subpage reads */
152 #define NAND_SUBPAGE_READ 0x00001000
155 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
158 #define NAND_NEED_SCRAMBLING 0x00002000
160 /* Device needs 3rd row address cycle */
161 #define NAND_ROW_ADDR_3 0x00004000
163 /* Options valid for Samsung large page devices */
164 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
166 /* Macros to identify the above */
167 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
170 * There are different places where the manufacturer stores the factory bad
173 * Position within the block: Each of these pages needs to be checked for a
174 * bad block marking pattern.
176 #define NAND_BBM_FIRSTPAGE 0x01000000
177 #define NAND_BBM_SECONDPAGE 0x02000000
178 #define NAND_BBM_LASTPAGE 0x04000000
180 /* Position within the OOB data of the page */
181 #define NAND_BBM_POS_SMALL 5
182 #define NAND_BBM_POS_LARGE 0
184 /* Non chip related options */
185 /* This option skips the bbt scan during initialization. */
186 #define NAND_SKIP_BBTSCAN 0x00010000
187 /* Chip may not exist, so silence any errors in scan */
188 #define NAND_SCAN_SILENT_NODEV 0x00040000
190 * Autodetect nand buswidth with readid/onfi.
191 * This suppose the driver will configure the hardware in 8 bits mode
192 * when calling nand_scan_ident, and update its configuration
193 * before calling nand_scan_tail.
195 #define NAND_BUSWIDTH_AUTO 0x00080000
197 * This option could be defined by controller drivers to protect against
198 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
200 #define NAND_USE_BOUNCE_BUFFER 0x00100000
203 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
204 * on the default ->cmdfunc() implementation, you may want to let the core
205 * handle the tCCS delay which is required when a column change (RNDIN or
206 * RNDOUT) is requested.
207 * If your controller already takes care of this delay, you don't need to set
210 #define NAND_WAIT_TCCS 0x00200000
213 * Whether the NAND chip is a boot medium. Drivers might use this information
214 * to select ECC algorithms supported by the boot ROM or similar restrictions.
216 #define NAND_IS_BOOT_MEDIUM 0x00400000
219 * Do not try to tweak the timings at runtime. This is needed when the
220 * controller initializes the timings on itself or when it relies on
221 * configuration done by the bootloader.
223 #define NAND_KEEP_TIMINGS 0x00800000
225 /* Cell info constants */
226 #define NAND_CI_CHIPNR_MSK 0x03
227 #define NAND_CI_CELLTYPE_MSK 0x0C
228 #define NAND_CI_CELLTYPE_SHIFT 2
231 * struct nand_parameters - NAND generic parameters from the parameter page
233 * @supports_set_get_features: The NAND chip supports setting/getting features
234 * @set_feature_list: Bitmap of features that can be set
235 * @get_feature_list: Bitmap of features that can be get
236 * @onfi: ONFI specific parameters
238 struct nand_parameters {
239 /* Generic parameters */
241 bool supports_set_get_features;
242 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
243 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
245 /* ONFI parameters */
246 struct onfi_params *onfi;
249 /* The maximum expected count of bytes in the NAND ID sequence */
250 #define NAND_MAX_ID_LEN 8
253 * struct nand_id - NAND id structure
254 * @data: buffer containing the id bytes.
258 u8 data[NAND_MAX_ID_LEN];
263 * struct nand_ecc_step_info - ECC step information of ECC engine
264 * @stepsize: data bytes per ECC step
265 * @strengths: array of supported strengths
266 * @nstrengths: number of supported strengths
268 struct nand_ecc_step_info {
270 const int *strengths;
275 * struct nand_ecc_caps - capability of ECC engine
276 * @stepinfos: array of ECC step information
277 * @nstepinfos: number of ECC step information
278 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
280 struct nand_ecc_caps {
281 const struct nand_ecc_step_info *stepinfos;
283 int (*calc_ecc_bytes)(int step_size, int strength);
286 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
287 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
288 static const int __name##_strengths[] = { __VA_ARGS__ }; \
289 static const struct nand_ecc_step_info __name##_stepinfo = { \
290 .stepsize = __step, \
291 .strengths = __name##_strengths, \
292 .nstrengths = ARRAY_SIZE(__name##_strengths), \
294 static const struct nand_ecc_caps __name = { \
295 .stepinfos = &__name##_stepinfo, \
297 .calc_ecc_bytes = __calc, \
301 * struct nand_ecc_ctrl - Control structure for ECC
303 * @algo: ECC algorithm
304 * @steps: number of ECC steps per page
305 * @size: data bytes per ECC step
306 * @bytes: ECC bytes per step
307 * @strength: max number of correctible bits per ECC step
308 * @total: total number of ECC bytes per page
309 * @prepad: padding information for syndrome based ECC generators
310 * @postpad: padding information for syndrome based ECC generators
311 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
312 * @priv: pointer to private ECC control data
313 * @calc_buf: buffer for calculated ECC, size is oobsize.
314 * @code_buf: buffer for ECC read from flash, size is oobsize.
315 * @hwctl: function to control hardware ECC generator. Must only
316 * be provided if an hardware ECC is available
317 * @calculate: function for ECC calculation or readback from ECC hardware
318 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
319 * Should return a positive number representing the number of
320 * corrected bitflips, -EBADMSG if the number of bitflips exceed
321 * ECC strength, or any other error code if the error is not
322 * directly related to correction.
323 * If -EBADMSG is returned the input buffers should be left
325 * @read_page_raw: function to read a raw page without ECC. This function
326 * should hide the specific layout used by the ECC
327 * controller and always return contiguous in-band and
328 * out-of-band data even if they're not stored
329 * contiguously on the NAND chip (e.g.
330 * NAND_ECC_HW_SYNDROME interleaves in-band and
332 * @write_page_raw: function to write a raw page without ECC. This function
333 * should hide the specific layout used by the ECC
334 * controller and consider the passed data as contiguous
335 * in-band and out-of-band data. ECC controller is
336 * responsible for doing the appropriate transformations
337 * to adapt to its specific layout (e.g.
338 * NAND_ECC_HW_SYNDROME interleaves in-band and
340 * @read_page: function to read a page according to the ECC generator
341 * requirements; returns maximum number of bitflips corrected in
342 * any single ECC step, -EIO hw error
343 * @read_subpage: function to read parts of the page covered by ECC;
344 * returns same as read_page()
345 * @write_subpage: function to write parts of the page covered by ECC.
346 * @write_page: function to write a page according to the ECC generator
348 * @write_oob_raw: function to write chip OOB data without ECC
349 * @read_oob_raw: function to read chip OOB data without ECC
350 * @read_oob: function to read chip OOB data
351 * @write_oob: function to write chip OOB data
353 struct nand_ecc_ctrl {
354 nand_ecc_modes_t mode;
355 enum nand_ecc_algo algo;
363 unsigned int options;
367 void (*hwctl)(struct nand_chip *chip, int mode);
368 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
370 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
372 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
373 int oob_required, int page);
374 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
375 int oob_required, int page);
376 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
377 int oob_required, int page);
378 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
379 uint32_t len, uint8_t *buf, int page);
380 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
381 uint32_t data_len, const uint8_t *data_buf,
382 int oob_required, int page);
383 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
384 int oob_required, int page);
385 int (*write_oob_raw)(struct nand_chip *chip, int page);
386 int (*read_oob_raw)(struct nand_chip *chip, int page);
387 int (*read_oob)(struct nand_chip *chip, int page);
388 int (*write_oob)(struct nand_chip *chip, int page);
392 * struct nand_sdr_timings - SDR NAND chip timings
394 * This struct defines the timing requirements of a SDR NAND chip.
395 * These information can be found in every NAND datasheets and the timings
396 * meaning are described in the ONFI specifications:
397 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
400 * All these timings are expressed in picoseconds.
402 * @tBERS_max: Block erase time
403 * @tCCS_min: Change column setup time
404 * @tPROG_max: Page program time
405 * @tR_max: Page read time
406 * @tALH_min: ALE hold time
407 * @tADL_min: ALE to data loading time
408 * @tALS_min: ALE setup time
409 * @tAR_min: ALE to RE# delay
410 * @tCEA_max: CE# access time
411 * @tCEH_min: CE# high hold time
412 * @tCH_min: CE# hold time
413 * @tCHZ_max: CE# high to output hi-Z
414 * @tCLH_min: CLE hold time
415 * @tCLR_min: CLE to RE# delay
416 * @tCLS_min: CLE setup time
417 * @tCOH_min: CE# high to output hold
418 * @tCS_min: CE# setup time
419 * @tDH_min: Data hold time
420 * @tDS_min: Data setup time
421 * @tFEAT_max: Busy time for Set Features and Get Features
422 * @tIR_min: Output hi-Z to RE# low
423 * @tITC_max: Interface and Timing Mode Change time
424 * @tRC_min: RE# cycle time
425 * @tREA_max: RE# access time
426 * @tREH_min: RE# high hold time
427 * @tRHOH_min: RE# high to output hold
428 * @tRHW_min: RE# high to WE# low
429 * @tRHZ_max: RE# high to output hi-Z
430 * @tRLOH_min: RE# low to output hold
431 * @tRP_min: RE# pulse width
432 * @tRR_min: Ready to RE# low (data only)
433 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
434 * rising edge of R/B#.
435 * @tWB_max: WE# high to SR[6] low
436 * @tWC_min: WE# cycle time
437 * @tWH_min: WE# high hold time
438 * @tWHR_min: WE# high to RE# low
439 * @tWP_min: WE# pulse width
440 * @tWW_min: WP# transition to WE# low
442 struct nand_sdr_timings {
484 * enum nand_data_interface_type - NAND interface timing type
485 * @NAND_SDR_IFACE: Single Data Rate interface
487 enum nand_data_interface_type {
492 * struct nand_data_interface - NAND interface timing
493 * @type: type of the timing
494 * @timings: The timing information
495 * @timings.mode: Timing mode as defined in the specification
496 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
498 struct nand_data_interface {
499 enum nand_data_interface_type type;
500 struct nand_timings {
503 struct nand_sdr_timings sdr;
509 * nand_get_sdr_timings - get SDR timing from data interface
510 * @conf: The data interface
512 static inline const struct nand_sdr_timings *
513 nand_get_sdr_timings(const struct nand_data_interface *conf)
515 if (conf->type != NAND_SDR_IFACE)
516 return ERR_PTR(-EINVAL);
518 return &conf->timings.sdr;
522 * struct nand_op_cmd_instr - Definition of a command instruction
523 * @opcode: the command to issue in one cycle
525 struct nand_op_cmd_instr {
530 * struct nand_op_addr_instr - Definition of an address instruction
531 * @naddrs: length of the @addrs array
532 * @addrs: array containing the address cycles to issue
534 struct nand_op_addr_instr {
540 * struct nand_op_data_instr - Definition of a data instruction
541 * @len: number of data bytes to move
542 * @buf: buffer to fill
543 * @buf.in: buffer to fill when reading from the NAND chip
544 * @buf.out: buffer to read from when writing to the NAND chip
545 * @force_8bit: force 8-bit access
547 * Please note that "in" and "out" are inverted from the ONFI specification
548 * and are from the controller perspective, so a "in" is a read from the NAND
549 * chip while a "out" is a write to the NAND chip.
551 struct nand_op_data_instr {
561 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
562 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
564 struct nand_op_waitrdy_instr {
565 unsigned int timeout_ms;
569 * enum nand_op_instr_type - Definition of all instruction types
570 * @NAND_OP_CMD_INSTR: command instruction
571 * @NAND_OP_ADDR_INSTR: address instruction
572 * @NAND_OP_DATA_IN_INSTR: data in instruction
573 * @NAND_OP_DATA_OUT_INSTR: data out instruction
574 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
576 enum nand_op_instr_type {
579 NAND_OP_DATA_IN_INSTR,
580 NAND_OP_DATA_OUT_INSTR,
581 NAND_OP_WAITRDY_INSTR,
585 * struct nand_op_instr - Instruction object
586 * @type: the instruction type
587 * @ctx: extra data associated to the instruction. You'll have to use the
588 * appropriate element depending on @type
589 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
590 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
591 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
592 * or %NAND_OP_DATA_OUT_INSTR
593 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
594 * @delay_ns: delay the controller should apply after the instruction has been
595 * issued on the bus. Most modern controllers have internal timings
596 * control logic, and in this case, the controller driver can ignore
599 struct nand_op_instr {
600 enum nand_op_instr_type type;
602 struct nand_op_cmd_instr cmd;
603 struct nand_op_addr_instr addr;
604 struct nand_op_data_instr data;
605 struct nand_op_waitrdy_instr waitrdy;
607 unsigned int delay_ns;
611 * Special handling must be done for the WAITRDY timeout parameter as it usually
612 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
613 * tBERS (during an erase) which all of them are u64 values that cannot be
614 * divided by usual kernel macros and must be handled with the special
615 * DIV_ROUND_UP_ULL() macro.
617 * Cast to type of dividend is needed here to guarantee that the result won't
618 * be an unsigned long long when the dividend is an unsigned long (or smaller),
619 * which is what the compiler does when it sees ternary operator with 2
620 * different return types (picks the largest type to make sure there's no
623 #define __DIVIDE(dividend, divisor) ({ \
624 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
625 DIV_ROUND_UP(dividend, divisor) : \
626 DIV_ROUND_UP_ULL(dividend, divisor)); \
628 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
629 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
631 #define NAND_OP_CMD(id, ns) \
633 .type = NAND_OP_CMD_INSTR, \
634 .ctx.cmd.opcode = id, \
638 #define NAND_OP_ADDR(ncycles, cycles, ns) \
640 .type = NAND_OP_ADDR_INSTR, \
648 #define NAND_OP_DATA_IN(l, b, ns) \
650 .type = NAND_OP_DATA_IN_INSTR, \
654 .force_8bit = false, \
659 #define NAND_OP_DATA_OUT(l, b, ns) \
661 .type = NAND_OP_DATA_OUT_INSTR, \
665 .force_8bit = false, \
670 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
672 .type = NAND_OP_DATA_IN_INSTR, \
676 .force_8bit = true, \
681 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
683 .type = NAND_OP_DATA_OUT_INSTR, \
687 .force_8bit = true, \
692 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
694 .type = NAND_OP_WAITRDY_INSTR, \
695 .ctx.waitrdy.timeout_ms = tout_ms, \
700 * struct nand_subop - a sub operation
701 * @instrs: array of instructions
702 * @ninstrs: length of the @instrs array
703 * @first_instr_start_off: offset to start from for the first instruction
704 * of the sub-operation
705 * @last_instr_end_off: offset to end at (excluded) for the last instruction
706 * of the sub-operation
708 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
709 * address instructions.
711 * When an operation cannot be handled as is by the NAND controller, it will
712 * be split by the parser into sub-operations which will be passed to the
716 const struct nand_op_instr *instrs;
717 unsigned int ninstrs;
718 unsigned int first_instr_start_off;
719 unsigned int last_instr_end_off;
722 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
724 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
726 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
728 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
732 * struct nand_op_parser_addr_constraints - Constraints for address instructions
733 * @maxcycles: maximum number of address cycles the controller can issue in a
736 struct nand_op_parser_addr_constraints {
737 unsigned int maxcycles;
741 * struct nand_op_parser_data_constraints - Constraints for data instructions
742 * @maxlen: maximum data length that the controller can handle in a single step
744 struct nand_op_parser_data_constraints {
749 * struct nand_op_parser_pattern_elem - One element of a pattern
750 * @type: the instructuction type
751 * @optional: whether this element of the pattern is optional or mandatory
752 * @ctx: address or data constraint
753 * @ctx.addr: address constraint (number of cycles)
754 * @ctx.data: data constraint (data length)
756 struct nand_op_parser_pattern_elem {
757 enum nand_op_instr_type type;
760 struct nand_op_parser_addr_constraints addr;
761 struct nand_op_parser_data_constraints data;
765 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
767 .type = NAND_OP_CMD_INSTR, \
771 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
773 .type = NAND_OP_ADDR_INSTR, \
775 .ctx.addr.maxcycles = _maxcycles, \
778 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
780 .type = NAND_OP_DATA_IN_INSTR, \
782 .ctx.data.maxlen = _maxlen, \
785 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
787 .type = NAND_OP_DATA_OUT_INSTR, \
789 .ctx.data.maxlen = _maxlen, \
792 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
794 .type = NAND_OP_WAITRDY_INSTR, \
799 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
800 * @elems: array of pattern elements
801 * @nelems: number of pattern elements in @elems array
802 * @exec: the function that will issue a sub-operation
804 * A pattern is a list of elements, each element reprensenting one instruction
805 * with its constraints. The pattern itself is used by the core to match NAND
806 * chip operation with NAND controller operations.
807 * Once a match between a NAND controller operation pattern and a NAND chip
808 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
809 * hook is called so that the controller driver can issue the operation on the
812 * Controller drivers should declare as many patterns as they support and pass
813 * this list of patterns (created with the help of the following macro) to
814 * the nand_op_parser_exec_op() helper.
816 struct nand_op_parser_pattern {
817 const struct nand_op_parser_pattern_elem *elems;
819 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
822 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
825 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
826 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
827 sizeof(struct nand_op_parser_pattern_elem), \
831 * struct nand_op_parser - NAND controller operation parser descriptor
832 * @patterns: array of supported patterns
833 * @npatterns: length of the @patterns array
835 * The parser descriptor is just an array of supported patterns which will be
836 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
837 * NAND operation (or tries to determine if a specific operation is supported).
839 * It is worth mentioning that patterns will be tested in their declaration
840 * order, and the first match will be taken, so it's important to order patterns
841 * appropriately so that simple/inefficient patterns are placed at the end of
842 * the list. Usually, this is where you put single instruction patterns.
844 struct nand_op_parser {
845 const struct nand_op_parser_pattern *patterns;
846 unsigned int npatterns;
849 #define NAND_OP_PARSER(...) \
851 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
852 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
853 sizeof(struct nand_op_parser_pattern), \
857 * struct nand_operation - NAND operation descriptor
858 * @cs: the CS line to select for this NAND operation
859 * @instrs: array of instructions to execute
860 * @ninstrs: length of the @instrs array
862 * The actual operation structure that will be passed to chip->exec_op().
864 struct nand_operation {
866 const struct nand_op_instr *instrs;
867 unsigned int ninstrs;
870 #define NAND_OPERATION(_cs, _instrs) \
874 .ninstrs = ARRAY_SIZE(_instrs), \
877 int nand_op_parser_exec_op(struct nand_chip *chip,
878 const struct nand_op_parser *parser,
879 const struct nand_operation *op, bool check_only);
881 static inline void nand_op_trace(const char *prefix,
882 const struct nand_op_instr *instr)
884 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
885 switch (instr->type) {
886 case NAND_OP_CMD_INSTR:
887 pr_debug("%sCMD [0x%02x]\n", prefix,
888 instr->ctx.cmd.opcode);
890 case NAND_OP_ADDR_INSTR:
891 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
892 instr->ctx.addr.naddrs,
893 instr->ctx.addr.naddrs < 64 ?
894 instr->ctx.addr.naddrs : 64,
895 instr->ctx.addr.addrs);
897 case NAND_OP_DATA_IN_INSTR:
898 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
900 instr->ctx.data.force_8bit ?
901 ", force 8-bit" : "");
903 case NAND_OP_DATA_OUT_INSTR:
904 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
906 instr->ctx.data.force_8bit ?
907 ", force 8-bit" : "");
909 case NAND_OP_WAITRDY_INSTR:
910 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
911 instr->ctx.waitrdy.timeout_ms);
918 * struct nand_controller_ops - Controller operations
920 * @attach_chip: this method is called after the NAND detection phase after
921 * flash ID and MTD fields such as erase size, page size and OOB
922 * size have been set up. ECC requirements are available if
923 * provided by the NAND chip or device tree. Typically used to
924 * choose the appropriate ECC configuration and allocate
925 * associated resources.
926 * This hook is optional.
927 * @detach_chip: free all resources allocated/claimed in
928 * nand_controller_ops->attach_chip().
929 * This hook is optional.
930 * @exec_op: controller specific method to execute NAND operations.
931 * This method replaces chip->legacy.cmdfunc(),
932 * chip->legacy.{read,write}_{buf,byte,word}(),
933 * chip->legacy.dev_ready() and chip->legacy.waifunc().
934 * @setup_data_interface: setup the data interface and timing. If
935 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
936 * means the configuration should not be applied but
938 * This hook is optional.
940 struct nand_controller_ops {
941 int (*attach_chip)(struct nand_chip *chip);
942 void (*detach_chip)(struct nand_chip *chip);
943 int (*exec_op)(struct nand_chip *chip,
944 const struct nand_operation *op,
946 int (*setup_data_interface)(struct nand_chip *chip, int chipnr,
947 const struct nand_data_interface *conf);
951 * struct nand_controller - Structure used to describe a NAND controller
953 * @lock: lock used to serialize accesses to the NAND controller
954 * @ops: NAND controller operations.
956 struct nand_controller {
958 const struct nand_controller_ops *ops;
961 static inline void nand_controller_init(struct nand_controller *nfc)
963 mutex_init(&nfc->lock);
967 * struct nand_legacy - NAND chip legacy fields/hooks
968 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
969 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
970 * @select_chip: select/deselect a specific target/die
971 * @read_byte: read one byte from the chip
972 * @write_byte: write a single byte to the chip on the low 8 I/O lines
973 * @write_buf: write data from the buffer to the chip
974 * @read_buf: read data from the chip into the buffer
975 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
976 * to write command and address
977 * @cmdfunc: hardware specific function for writing commands to the chip.
978 * @dev_ready: hardware specific function for accessing device ready/busy line.
979 * If set to NULL no access to ready/busy is available and the
980 * ready/busy information is read from the chip status register.
981 * @waitfunc: hardware specific function for wait on ready.
982 * @block_bad: check if a block is bad, using OOB markers
983 * @block_markbad: mark a block bad
984 * @set_features: set the NAND chip features
985 * @get_features: get the NAND chip features
986 * @chip_delay: chip dependent delay for transferring data from array to read
988 * @dummy_controller: dummy controller implementation for drivers that can
989 * only control a single chip
991 * If you look at this structure you're already wrong. These fields/hooks are
995 void __iomem *IO_ADDR_R;
996 void __iomem *IO_ADDR_W;
997 void (*select_chip)(struct nand_chip *chip, int cs);
998 u8 (*read_byte)(struct nand_chip *chip);
999 void (*write_byte)(struct nand_chip *chip, u8 byte);
1000 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1001 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1002 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1003 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1005 int (*dev_ready)(struct nand_chip *chip);
1006 int (*waitfunc)(struct nand_chip *chip);
1007 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1008 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1009 int (*set_features)(struct nand_chip *chip, int feature_addr,
1010 u8 *subfeature_para);
1011 int (*get_features)(struct nand_chip *chip, int feature_addr,
1012 u8 *subfeature_para);
1014 struct nand_controller dummy_controller;
1018 * struct nand_chip - NAND Private Flash Chip Data
1019 * @base: Inherit from the generic NAND device
1020 * @legacy: All legacy fields/hooks. If you develop a new driver,
1021 * don't even try to use any of these fields/hooks, and if
1022 * you're modifying an existing driver that is using those
1023 * fields/hooks, you should consider reworking the driver
1025 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
1026 * setting the read-retry mode. Mostly needed for MLC NAND.
1027 * @ecc: [BOARDSPECIFIC] ECC control structure
1028 * @buf_align: minimum buffer alignment required by a platform
1029 * @oob_poi: "poison value buffer," used for laying out OOB data
1031 * @page_shift: [INTERN] number of address bits in a page (column
1033 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
1034 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
1035 * @chip_shift: [INTERN] number of address bits in one chip
1036 * @options: [BOARDSPECIFIC] various chip options. They can partly
1037 * be set to inform nand_scan about special functionality.
1038 * See the defines for further explanation.
1039 * @bbt_options: [INTERN] bad block specific options. All options used
1040 * here must come from bbm.h. By default, these options
1041 * will be copied to the appropriate nand_bbt_descr's.
1042 * @badblockpos: [INTERN] position of the bad block marker in the oob
1044 * @badblockbits: [INTERN] minimum number of set bits in a good block's
1045 * bad block marker position; i.e., BBM == 11110111b is
1046 * not bad when badblockbits == 7
1047 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
1048 * set to the actually used ONFI mode if the chip is
1049 * ONFI compliant or deduced from the datasheet if
1050 * the NAND chip is not ONFI compliant.
1051 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
1052 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize).
1053 * @pagecache: Structure containing page cache related fields
1054 * @pagecache.bitflips: Number of bitflips of the cached page
1055 * @pagecache.page: Page number currently in the cache. -1 means no page is
1057 * @subpagesize: [INTERN] holds the subpagesize
1058 * @id: [INTERN] holds NAND ID
1059 * @parameters: [INTERN] holds generic parameters under an easily
1061 * @data_interface: [INTERN] NAND interface timing information
1062 * @cur_cs: currently selected target. -1 means no target selected,
1063 * otherwise we should always have cur_cs >= 0 &&
1064 * cur_cs < nanddev_ntargets(). NAND Controller drivers
1065 * should not modify this value, but they're allowed to
1067 * @read_retries: [INTERN] the number of read retry modes supported
1068 * @lock: lock protecting the suspended field. Also used to
1069 * serialize accesses to the NAND device.
1070 * @suspended: set to 1 when the device is suspended, 0 when it's not.
1071 * @suspend: [REPLACEABLE] specific NAND device suspend operation
1072 * @resume: [REPLACEABLE] specific NAND device resume operation
1073 * @bbt: [INTERN] bad block table pointer
1074 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
1076 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
1077 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
1079 * @controller: [REPLACEABLE] a pointer to a hardware controller
1080 * structure which is shared among multiple independent
1082 * @priv: [OPTIONAL] pointer to private chip data
1083 * @manufacturer: [INTERN] Contains manufacturer information
1084 * @manufacturer.desc: [INTERN] Contains manufacturer's description
1085 * @manufacturer.priv: [INTERN] Contains manufacturer private information
1086 * @lock_area: [REPLACEABLE] specific NAND chip lock operation
1087 * @unlock_area: [REPLACEABLE] specific NAND chip unlock operation
1091 struct nand_device base;
1093 struct nand_legacy legacy;
1095 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1097 unsigned int options;
1098 unsigned int bbt_options;
1101 int phys_erase_shift;
1102 int bbt_erase_shift;
1108 unsigned int bitflips;
1113 int onfi_timing_mode_default;
1114 unsigned int badblockpos;
1118 struct nand_parameters parameters;
1120 struct nand_data_interface data_interface;
1127 unsigned int suspended : 1;
1128 int (*suspend)(struct nand_chip *chip);
1129 void (*resume)(struct nand_chip *chip);
1132 struct nand_controller *controller;
1134 struct nand_ecc_ctrl ecc;
1135 unsigned long buf_align;
1138 struct nand_bbt_descr *bbt_td;
1139 struct nand_bbt_descr *bbt_md;
1141 struct nand_bbt_descr *badblock_pattern;
1146 const struct nand_manufacturer *desc;
1150 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1151 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1154 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
1155 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
1157 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1159 return container_of(mtd, struct nand_chip, base.mtd);
1162 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1164 return &chip->base.mtd;
1167 static inline void *nand_get_controller_data(struct nand_chip *chip)
1172 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1177 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1180 chip->manufacturer.priv = priv;
1183 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1185 return chip->manufacturer.priv;
1188 static inline void nand_set_flash_node(struct nand_chip *chip,
1189 struct device_node *np)
1191 mtd_set_of_node(nand_to_mtd(chip), np);
1194 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1196 return mtd_get_of_node(nand_to_mtd(chip));
1200 * A helper for defining older NAND chips where the second ID byte fully
1201 * defined the chip, including the geometry (chip size, eraseblock size, page
1202 * size). All these chips have 512 bytes NAND page size.
1204 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1205 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1206 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1209 * A helper for defining newer chips which report their page size and
1210 * eraseblock size via the extended ID bytes.
1212 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1213 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1214 * device ID now only represented a particular total chip size (and voltage,
1215 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1216 * using the same device ID.
1218 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1219 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1222 #define NAND_ECC_INFO(_strength, _step) \
1223 { .strength_ds = (_strength), .step_ds = (_step) }
1224 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1225 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1228 * struct nand_flash_dev - NAND Flash Device ID Structure
1229 * @name: a human-readable name of the NAND chip
1230 * @dev_id: the device ID (the second byte of the full chip ID array)
1231 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1232 * memory address as ``id[0]``)
1233 * @dev_id: device ID part of the full chip ID array (refers the same memory
1234 * address as ``id[1]``)
1235 * @id: full device ID array
1236 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1237 * well as the eraseblock size) is determined from the extended NAND
1239 * @chipsize: total chip size in MiB
1240 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1241 * @options: stores various chip bit options
1242 * @id_len: The valid length of the @id.
1243 * @oobsize: OOB size
1244 * @ecc: ECC correctability and step information from the datasheet.
1245 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1246 * @ecc_strength_ds in nand_chip{}.
1247 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1248 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1249 * For example, the "4bit ECC for each 512Byte" can be set with
1250 * NAND_ECC_INFO(4, 512).
1251 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1252 * reset. Should be deduced from timings described
1256 struct nand_flash_dev {
1263 uint8_t id[NAND_MAX_ID_LEN];
1265 unsigned int pagesize;
1266 unsigned int chipsize;
1267 unsigned int erasesize;
1268 unsigned int options;
1272 uint16_t strength_ds;
1275 int onfi_timing_mode_default;
1278 int nand_create_bbt(struct nand_chip *chip);
1281 * Check if it is a SLC nand.
1282 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1283 * We do not distinguish the MLC and TLC now.
1285 static inline bool nand_is_slc(struct nand_chip *chip)
1287 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1288 "chip->bits_per_cell is used uninitialized\n");
1289 return nanddev_bits_per_cell(&chip->base) == 1;
1293 * Check if the opcode's address should be sent only on the lower 8 bits
1294 * @command: opcode to check
1296 static inline int nand_opcode_8bits(unsigned int command)
1299 case NAND_CMD_READID:
1300 case NAND_CMD_PARAM:
1301 case NAND_CMD_GET_FEATURES:
1302 case NAND_CMD_SET_FEATURES:
1310 int nand_check_erased_ecc_chunk(void *data, int datalen,
1311 void *ecc, int ecclen,
1312 void *extraoob, int extraooblen,
1315 int nand_ecc_choose_conf(struct nand_chip *chip,
1316 const struct nand_ecc_caps *caps, int oobavail);
1318 /* Default write_oob implementation */
1319 int nand_write_oob_std(struct nand_chip *chip, int page);
1321 /* Default read_oob implementation */
1322 int nand_read_oob_std(struct nand_chip *chip, int page);
1324 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1325 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1326 u8 *subfeature_param);
1328 /* Default read_page_raw implementation */
1329 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1332 /* Default write_page_raw implementation */
1333 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1334 int oob_required, int page);
1336 /* Reset and initialize a NAND device */
1337 int nand_reset(struct nand_chip *chip, int chipnr);
1339 /* NAND operation helpers */
1340 int nand_reset_op(struct nand_chip *chip);
1341 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1343 int nand_status_op(struct nand_chip *chip, u8 *status);
1344 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1345 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1346 unsigned int offset_in_page, void *buf, unsigned int len);
1347 int nand_change_read_column_op(struct nand_chip *chip,
1348 unsigned int offset_in_page, void *buf,
1349 unsigned int len, bool force_8bit);
1350 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1351 unsigned int offset_in_page, void *buf, unsigned int len);
1352 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1353 unsigned int offset_in_page, const void *buf,
1355 int nand_prog_page_end_op(struct nand_chip *chip);
1356 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1357 unsigned int offset_in_page, const void *buf,
1359 int nand_change_write_column_op(struct nand_chip *chip,
1360 unsigned int offset_in_page, const void *buf,
1361 unsigned int len, bool force_8bit);
1362 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1364 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1365 unsigned int len, bool force_8bit);
1367 /* Scan and identify a NAND device */
1368 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1369 struct nand_flash_dev *ids);
1371 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1373 return nand_scan_with_ids(chip, max_chips, NULL);
1376 /* Internal helper for board drivers which need to override command function */
1377 void nand_wait_ready(struct nand_chip *chip);
1380 * Free resources held by the NAND device, must be called on error after a
1381 * sucessful nand_scan().
1383 void nand_cleanup(struct nand_chip *chip);
1384 /* Unregister the MTD device and calls nand_cleanup() */
1385 void nand_release(struct nand_chip *chip);
1388 * External helper for controller drivers that have to implement the WAITRDY
1389 * instruction and have no physical pin to check it.
1391 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1393 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1394 unsigned long timeout_ms);
1396 /* Select/deselect a NAND target. */
1397 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1398 void nand_deselect_target(struct nand_chip *chip);
1401 * nand_get_data_buf() - Get the internal page buffer
1402 * @chip: NAND chip object
1404 * Returns the pre-allocated page buffer after invalidating the cache. This
1405 * function should be used by drivers that do not want to allocate their own
1406 * bounce buffer and still need such a buffer for specific operations (most
1407 * commonly when reading OOB data only).
1409 * Be careful to never call this function in the write/write_oob path, because
1410 * the core may have placed the data to be written out in this buffer.
1412 * Return: pointer to the page cache buffer
1414 static inline void *nand_get_data_buf(struct nand_chip *chip)
1416 chip->pagecache.page = -1;
1418 return chip->data_buf;
1421 #endif /* __LINUX_MTD_RAWNAND_H */