1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
8 * Contains standard defines and IDs for NAND flash devices
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/flashchip.h>
19 #include <linux/mtd/bbm.h>
20 #include <linux/mtd/jedec.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/mtd/onfi.h>
23 #include <linux/mutex.h>
25 #include <linux/types.h>
29 /* The maximum number of NAND chips in an array */
30 #define NAND_MAX_CHIPS 8
33 * Constants for hardware specific CLE/ALE/NCE function
35 * These are bits which can be or'ed to set/clear multiple
38 /* Select the chip by setting nCE to low */
40 /* Select the command latch by setting CLE to high */
42 /* Select the address latch by setting ALE to high */
45 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
46 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
47 #define NAND_CTRL_CHANGE 0x80
50 * Standard NAND flash commands
52 #define NAND_CMD_READ0 0
53 #define NAND_CMD_READ1 1
54 #define NAND_CMD_RNDOUT 5
55 #define NAND_CMD_PAGEPROG 0x10
56 #define NAND_CMD_READOOB 0x50
57 #define NAND_CMD_ERASE1 0x60
58 #define NAND_CMD_STATUS 0x70
59 #define NAND_CMD_SEQIN 0x80
60 #define NAND_CMD_RNDIN 0x85
61 #define NAND_CMD_READID 0x90
62 #define NAND_CMD_ERASE2 0xd0
63 #define NAND_CMD_PARAM 0xec
64 #define NAND_CMD_GET_FEATURES 0xee
65 #define NAND_CMD_SET_FEATURES 0xef
66 #define NAND_CMD_RESET 0xff
68 /* Extended commands for large page devices */
69 #define NAND_CMD_READSTART 0x30
70 #define NAND_CMD_RNDOUTSTART 0xE0
71 #define NAND_CMD_CACHEDPROG 0x15
73 #define NAND_CMD_NONE -1
76 #define NAND_STATUS_FAIL 0x01
77 #define NAND_STATUS_FAIL_N1 0x02
78 #define NAND_STATUS_TRUE_READY 0x20
79 #define NAND_STATUS_READY 0x40
80 #define NAND_STATUS_WP 0x80
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for ECC_MODES
97 * Constants for Hardware ECC
99 /* Reset Hardware ECC for read */
100 #define NAND_ECC_READ 0
101 /* Reset Hardware ECC for write */
102 #define NAND_ECC_WRITE 1
103 /* Enable Hardware ECC before syndrome is read back from flash */
104 #define NAND_ECC_READSYN 2
107 * Enable generic NAND 'page erased' check. This check is only done when
108 * ecc.correct() returns -EBADMSG.
109 * Set this flag if your implementation does not fix bitflips in erased
110 * pages and you want to rely on the default implementation.
112 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
113 #define NAND_ECC_MAXIMIZE BIT(1)
116 * Option constants for bizarre disfunctionality and real
120 /* Buswidth is 16 bit */
121 #define NAND_BUSWIDTH_16 BIT(1)
124 * When using software implementation of Hamming, we can specify which byte
125 * ordering should be used.
127 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
129 /* Chip has cache program function */
130 #define NAND_CACHEPRG BIT(3)
131 /* Options valid for Samsung large page devices */
132 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
135 * Chip requires ready check on read (for auto-incremented sequential read).
136 * True only for small page devices; large page devices do not support
139 #define NAND_NEED_READRDY BIT(8)
141 /* Chip does not allow subpage writes */
142 #define NAND_NO_SUBPAGE_WRITE BIT(9)
144 /* Device is one of 'new' xD cards that expose fake nand command set */
145 #define NAND_BROKEN_XD BIT(10)
147 /* Device behaves just like nand, but is readonly */
148 #define NAND_ROM BIT(11)
150 /* Device supports subpage reads */
151 #define NAND_SUBPAGE_READ BIT(12)
152 /* Macros to identify the above */
153 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
156 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
159 #define NAND_NEED_SCRAMBLING BIT(13)
161 /* Device needs 3rd row address cycle */
162 #define NAND_ROW_ADDR_3 BIT(14)
164 /* Non chip related options */
165 /* This option skips the bbt scan during initialization. */
166 #define NAND_SKIP_BBTSCAN BIT(16)
167 /* Chip may not exist, so silence any errors in scan */
168 #define NAND_SCAN_SILENT_NODEV BIT(18)
171 * Autodetect nand buswidth with readid/onfi.
172 * This suppose the driver will configure the hardware in 8 bits mode
173 * when calling nand_scan_ident, and update its configuration
174 * before calling nand_scan_tail.
176 #define NAND_BUSWIDTH_AUTO BIT(19)
179 * This option could be defined by controller drivers to protect against
180 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
182 #define NAND_USES_DMA BIT(20)
185 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
186 * on the default ->cmdfunc() implementation, you may want to let the core
187 * handle the tCCS delay which is required when a column change (RNDIN or
188 * RNDOUT) is requested.
189 * If your controller already takes care of this delay, you don't need to set
192 #define NAND_WAIT_TCCS BIT(21)
195 * Whether the NAND chip is a boot medium. Drivers might use this information
196 * to select ECC algorithms supported by the boot ROM or similar restrictions.
198 #define NAND_IS_BOOT_MEDIUM BIT(22)
201 * Do not try to tweak the timings at runtime. This is needed when the
202 * controller initializes the timings on itself or when it relies on
203 * configuration done by the bootloader.
205 #define NAND_KEEP_TIMINGS BIT(23)
208 * There are different places where the manufacturer stores the factory bad
211 * Position within the block: Each of these pages needs to be checked for a
212 * bad block marking pattern.
214 #define NAND_BBM_FIRSTPAGE BIT(24)
215 #define NAND_BBM_SECONDPAGE BIT(25)
216 #define NAND_BBM_LASTPAGE BIT(26)
219 * Some controllers with pipelined ECC engines override the BBM marker with
220 * data or ECC bytes, thus making bad block detection through bad block marker
221 * impossible. Let's flag those chips so the core knows it shouldn't check the
222 * BBM and consider all blocks good.
224 #define NAND_NO_BBM_QUIRK BIT(27)
226 /* Cell info constants */
227 #define NAND_CI_CHIPNR_MSK 0x03
228 #define NAND_CI_CELLTYPE_MSK 0x0C
229 #define NAND_CI_CELLTYPE_SHIFT 2
231 /* Position within the OOB data of the page */
232 #define NAND_BBM_POS_SMALL 5
233 #define NAND_BBM_POS_LARGE 0
236 * struct nand_parameters - NAND generic parameters from the parameter page
238 * @supports_set_get_features: The NAND chip supports setting/getting features
239 * @set_feature_list: Bitmap of features that can be set
240 * @get_feature_list: Bitmap of features that can be get
241 * @onfi: ONFI specific parameters
243 struct nand_parameters {
244 /* Generic parameters */
246 bool supports_set_get_features;
247 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
248 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
250 /* ONFI parameters */
251 struct onfi_params *onfi;
254 /* The maximum expected count of bytes in the NAND ID sequence */
255 #define NAND_MAX_ID_LEN 8
258 * struct nand_id - NAND id structure
259 * @data: buffer containing the id bytes.
263 u8 data[NAND_MAX_ID_LEN];
268 * struct nand_ecc_step_info - ECC step information of ECC engine
269 * @stepsize: data bytes per ECC step
270 * @strengths: array of supported strengths
271 * @nstrengths: number of supported strengths
273 struct nand_ecc_step_info {
275 const int *strengths;
280 * struct nand_ecc_caps - capability of ECC engine
281 * @stepinfos: array of ECC step information
282 * @nstepinfos: number of ECC step information
283 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
285 struct nand_ecc_caps {
286 const struct nand_ecc_step_info *stepinfos;
288 int (*calc_ecc_bytes)(int step_size, int strength);
291 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
292 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
293 static const int __name##_strengths[] = { __VA_ARGS__ }; \
294 static const struct nand_ecc_step_info __name##_stepinfo = { \
295 .stepsize = __step, \
296 .strengths = __name##_strengths, \
297 .nstrengths = ARRAY_SIZE(__name##_strengths), \
299 static const struct nand_ecc_caps __name = { \
300 .stepinfos = &__name##_stepinfo, \
302 .calc_ecc_bytes = __calc, \
306 * struct nand_ecc_ctrl - Control structure for ECC
307 * @engine_type: ECC engine type
308 * @placement: OOB bytes placement
309 * @algo: ECC algorithm
310 * @steps: number of ECC steps per page
311 * @size: data bytes per ECC step
312 * @bytes: ECC bytes per step
313 * @strength: max number of correctible bits per ECC step
314 * @total: total number of ECC bytes per page
315 * @prepad: padding information for syndrome based ECC generators
316 * @postpad: padding information for syndrome based ECC generators
317 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
318 * @priv: pointer to private ECC control data
319 * @calc_buf: buffer for calculated ECC, size is oobsize.
320 * @code_buf: buffer for ECC read from flash, size is oobsize.
321 * @hwctl: function to control hardware ECC generator. Must only
322 * be provided if an hardware ECC is available
323 * @calculate: function for ECC calculation or readback from ECC hardware
324 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
325 * Should return a positive number representing the number of
326 * corrected bitflips, -EBADMSG if the number of bitflips exceed
327 * ECC strength, or any other error code if the error is not
328 * directly related to correction.
329 * If -EBADMSG is returned the input buffers should be left
331 * @read_page_raw: function to read a raw page without ECC. This function
332 * should hide the specific layout used by the ECC
333 * controller and always return contiguous in-band and
334 * out-of-band data even if they're not stored
335 * contiguously on the NAND chip (e.g.
336 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
338 * @write_page_raw: function to write a raw page without ECC. This function
339 * should hide the specific layout used by the ECC
340 * controller and consider the passed data as contiguous
341 * in-band and out-of-band data. ECC controller is
342 * responsible for doing the appropriate transformations
343 * to adapt to its specific layout (e.g.
344 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
346 * @read_page: function to read a page according to the ECC generator
347 * requirements; returns maximum number of bitflips corrected in
348 * any single ECC step, -EIO hw error
349 * @read_subpage: function to read parts of the page covered by ECC;
350 * returns same as read_page()
351 * @write_subpage: function to write parts of the page covered by ECC.
352 * @write_page: function to write a page according to the ECC generator
354 * @write_oob_raw: function to write chip OOB data without ECC
355 * @read_oob_raw: function to read chip OOB data without ECC
356 * @read_oob: function to read chip OOB data
357 * @write_oob: function to write chip OOB data
359 struct nand_ecc_ctrl {
360 enum nand_ecc_engine_type engine_type;
361 enum nand_ecc_placement placement;
362 enum nand_ecc_algo algo;
370 unsigned int options;
374 void (*hwctl)(struct nand_chip *chip, int mode);
375 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
377 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
379 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
380 int oob_required, int page);
381 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
382 int oob_required, int page);
383 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
384 int oob_required, int page);
385 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
386 uint32_t len, uint8_t *buf, int page);
387 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
388 uint32_t data_len, const uint8_t *data_buf,
389 int oob_required, int page);
390 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
391 int oob_required, int page);
392 int (*write_oob_raw)(struct nand_chip *chip, int page);
393 int (*read_oob_raw)(struct nand_chip *chip, int page);
394 int (*read_oob)(struct nand_chip *chip, int page);
395 int (*write_oob)(struct nand_chip *chip, int page);
399 * struct nand_sdr_timings - SDR NAND chip timings
401 * This struct defines the timing requirements of a SDR NAND chip.
402 * These information can be found in every NAND datasheets and the timings
403 * meaning are described in the ONFI specifications:
404 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
407 * All these timings are expressed in picoseconds.
409 * @tBERS_max: Block erase time
410 * @tCCS_min: Change column setup time
411 * @tPROG_max: Page program time
412 * @tR_max: Page read time
413 * @tALH_min: ALE hold time
414 * @tADL_min: ALE to data loading time
415 * @tALS_min: ALE setup time
416 * @tAR_min: ALE to RE# delay
417 * @tCEA_max: CE# access time
418 * @tCEH_min: CE# high hold time
419 * @tCH_min: CE# hold time
420 * @tCHZ_max: CE# high to output hi-Z
421 * @tCLH_min: CLE hold time
422 * @tCLR_min: CLE to RE# delay
423 * @tCLS_min: CLE setup time
424 * @tCOH_min: CE# high to output hold
425 * @tCS_min: CE# setup time
426 * @tDH_min: Data hold time
427 * @tDS_min: Data setup time
428 * @tFEAT_max: Busy time for Set Features and Get Features
429 * @tIR_min: Output hi-Z to RE# low
430 * @tITC_max: Interface and Timing Mode Change time
431 * @tRC_min: RE# cycle time
432 * @tREA_max: RE# access time
433 * @tREH_min: RE# high hold time
434 * @tRHOH_min: RE# high to output hold
435 * @tRHW_min: RE# high to WE# low
436 * @tRHZ_max: RE# high to output hi-Z
437 * @tRLOH_min: RE# low to output hold
438 * @tRP_min: RE# pulse width
439 * @tRR_min: Ready to RE# low (data only)
440 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
441 * rising edge of R/B#.
442 * @tWB_max: WE# high to SR[6] low
443 * @tWC_min: WE# cycle time
444 * @tWH_min: WE# high hold time
445 * @tWHR_min: WE# high to RE# low
446 * @tWP_min: WE# pulse width
447 * @tWW_min: WP# transition to WE# low
449 struct nand_sdr_timings {
491 * enum nand_interface_type - NAND interface type
492 * @NAND_SDR_IFACE: Single Data Rate interface
494 enum nand_interface_type {
499 * struct nand_interface_config - NAND interface timing
500 * @type: type of the timing
501 * @timings: The timing information
502 * @timings.mode: Timing mode as defined in the specification
503 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
505 struct nand_interface_config {
506 enum nand_interface_type type;
507 struct nand_timings {
510 struct nand_sdr_timings sdr;
516 * nand_get_sdr_timings - get SDR timing from data interface
517 * @conf: The data interface
519 static inline const struct nand_sdr_timings *
520 nand_get_sdr_timings(const struct nand_interface_config *conf)
522 if (conf->type != NAND_SDR_IFACE)
523 return ERR_PTR(-EINVAL);
525 return &conf->timings.sdr;
529 * struct nand_op_cmd_instr - Definition of a command instruction
530 * @opcode: the command to issue in one cycle
532 struct nand_op_cmd_instr {
537 * struct nand_op_addr_instr - Definition of an address instruction
538 * @naddrs: length of the @addrs array
539 * @addrs: array containing the address cycles to issue
541 struct nand_op_addr_instr {
547 * struct nand_op_data_instr - Definition of a data instruction
548 * @len: number of data bytes to move
549 * @buf: buffer to fill
550 * @buf.in: buffer to fill when reading from the NAND chip
551 * @buf.out: buffer to read from when writing to the NAND chip
552 * @force_8bit: force 8-bit access
554 * Please note that "in" and "out" are inverted from the ONFI specification
555 * and are from the controller perspective, so a "in" is a read from the NAND
556 * chip while a "out" is a write to the NAND chip.
558 struct nand_op_data_instr {
568 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
569 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
571 struct nand_op_waitrdy_instr {
572 unsigned int timeout_ms;
576 * enum nand_op_instr_type - Definition of all instruction types
577 * @NAND_OP_CMD_INSTR: command instruction
578 * @NAND_OP_ADDR_INSTR: address instruction
579 * @NAND_OP_DATA_IN_INSTR: data in instruction
580 * @NAND_OP_DATA_OUT_INSTR: data out instruction
581 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
583 enum nand_op_instr_type {
586 NAND_OP_DATA_IN_INSTR,
587 NAND_OP_DATA_OUT_INSTR,
588 NAND_OP_WAITRDY_INSTR,
592 * struct nand_op_instr - Instruction object
593 * @type: the instruction type
594 * @ctx: extra data associated to the instruction. You'll have to use the
595 * appropriate element depending on @type
596 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
597 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
598 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
599 * or %NAND_OP_DATA_OUT_INSTR
600 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
601 * @delay_ns: delay the controller should apply after the instruction has been
602 * issued on the bus. Most modern controllers have internal timings
603 * control logic, and in this case, the controller driver can ignore
606 struct nand_op_instr {
607 enum nand_op_instr_type type;
609 struct nand_op_cmd_instr cmd;
610 struct nand_op_addr_instr addr;
611 struct nand_op_data_instr data;
612 struct nand_op_waitrdy_instr waitrdy;
614 unsigned int delay_ns;
618 * Special handling must be done for the WAITRDY timeout parameter as it usually
619 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
620 * tBERS (during an erase) which all of them are u64 values that cannot be
621 * divided by usual kernel macros and must be handled with the special
622 * DIV_ROUND_UP_ULL() macro.
624 * Cast to type of dividend is needed here to guarantee that the result won't
625 * be an unsigned long long when the dividend is an unsigned long (or smaller),
626 * which is what the compiler does when it sees ternary operator with 2
627 * different return types (picks the largest type to make sure there's no
630 #define __DIVIDE(dividend, divisor) ({ \
631 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
632 DIV_ROUND_UP(dividend, divisor) : \
633 DIV_ROUND_UP_ULL(dividend, divisor)); \
635 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
636 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
638 #define NAND_OP_CMD(id, ns) \
640 .type = NAND_OP_CMD_INSTR, \
641 .ctx.cmd.opcode = id, \
645 #define NAND_OP_ADDR(ncycles, cycles, ns) \
647 .type = NAND_OP_ADDR_INSTR, \
655 #define NAND_OP_DATA_IN(l, b, ns) \
657 .type = NAND_OP_DATA_IN_INSTR, \
661 .force_8bit = false, \
666 #define NAND_OP_DATA_OUT(l, b, ns) \
668 .type = NAND_OP_DATA_OUT_INSTR, \
672 .force_8bit = false, \
677 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
679 .type = NAND_OP_DATA_IN_INSTR, \
683 .force_8bit = true, \
688 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
690 .type = NAND_OP_DATA_OUT_INSTR, \
694 .force_8bit = true, \
699 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
701 .type = NAND_OP_WAITRDY_INSTR, \
702 .ctx.waitrdy.timeout_ms = tout_ms, \
707 * struct nand_subop - a sub operation
708 * @cs: the CS line to select for this NAND sub-operation
709 * @instrs: array of instructions
710 * @ninstrs: length of the @instrs array
711 * @first_instr_start_off: offset to start from for the first instruction
712 * of the sub-operation
713 * @last_instr_end_off: offset to end at (excluded) for the last instruction
714 * of the sub-operation
716 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
717 * address instructions.
719 * When an operation cannot be handled as is by the NAND controller, it will
720 * be split by the parser into sub-operations which will be passed to the
725 const struct nand_op_instr *instrs;
726 unsigned int ninstrs;
727 unsigned int first_instr_start_off;
728 unsigned int last_instr_end_off;
731 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
733 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
735 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
737 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
741 * struct nand_op_parser_addr_constraints - Constraints for address instructions
742 * @maxcycles: maximum number of address cycles the controller can issue in a
745 struct nand_op_parser_addr_constraints {
746 unsigned int maxcycles;
750 * struct nand_op_parser_data_constraints - Constraints for data instructions
751 * @maxlen: maximum data length that the controller can handle in a single step
753 struct nand_op_parser_data_constraints {
758 * struct nand_op_parser_pattern_elem - One element of a pattern
759 * @type: the instructuction type
760 * @optional: whether this element of the pattern is optional or mandatory
761 * @ctx: address or data constraint
762 * @ctx.addr: address constraint (number of cycles)
763 * @ctx.data: data constraint (data length)
765 struct nand_op_parser_pattern_elem {
766 enum nand_op_instr_type type;
769 struct nand_op_parser_addr_constraints addr;
770 struct nand_op_parser_data_constraints data;
774 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
776 .type = NAND_OP_CMD_INSTR, \
780 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
782 .type = NAND_OP_ADDR_INSTR, \
784 .ctx.addr.maxcycles = _maxcycles, \
787 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
789 .type = NAND_OP_DATA_IN_INSTR, \
791 .ctx.data.maxlen = _maxlen, \
794 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
796 .type = NAND_OP_DATA_OUT_INSTR, \
798 .ctx.data.maxlen = _maxlen, \
801 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
803 .type = NAND_OP_WAITRDY_INSTR, \
808 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
809 * @elems: array of pattern elements
810 * @nelems: number of pattern elements in @elems array
811 * @exec: the function that will issue a sub-operation
813 * A pattern is a list of elements, each element reprensenting one instruction
814 * with its constraints. The pattern itself is used by the core to match NAND
815 * chip operation with NAND controller operations.
816 * Once a match between a NAND controller operation pattern and a NAND chip
817 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
818 * hook is called so that the controller driver can issue the operation on the
821 * Controller drivers should declare as many patterns as they support and pass
822 * this list of patterns (created with the help of the following macro) to
823 * the nand_op_parser_exec_op() helper.
825 struct nand_op_parser_pattern {
826 const struct nand_op_parser_pattern_elem *elems;
828 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
831 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
834 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
835 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
836 sizeof(struct nand_op_parser_pattern_elem), \
840 * struct nand_op_parser - NAND controller operation parser descriptor
841 * @patterns: array of supported patterns
842 * @npatterns: length of the @patterns array
844 * The parser descriptor is just an array of supported patterns which will be
845 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
846 * NAND operation (or tries to determine if a specific operation is supported).
848 * It is worth mentioning that patterns will be tested in their declaration
849 * order, and the first match will be taken, so it's important to order patterns
850 * appropriately so that simple/inefficient patterns are placed at the end of
851 * the list. Usually, this is where you put single instruction patterns.
853 struct nand_op_parser {
854 const struct nand_op_parser_pattern *patterns;
855 unsigned int npatterns;
858 #define NAND_OP_PARSER(...) \
860 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
861 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
862 sizeof(struct nand_op_parser_pattern), \
866 * struct nand_operation - NAND operation descriptor
867 * @cs: the CS line to select for this NAND operation
868 * @instrs: array of instructions to execute
869 * @ninstrs: length of the @instrs array
871 * The actual operation structure that will be passed to chip->exec_op().
873 struct nand_operation {
875 const struct nand_op_instr *instrs;
876 unsigned int ninstrs;
879 #define NAND_OPERATION(_cs, _instrs) \
883 .ninstrs = ARRAY_SIZE(_instrs), \
886 int nand_op_parser_exec_op(struct nand_chip *chip,
887 const struct nand_op_parser *parser,
888 const struct nand_operation *op, bool check_only);
890 static inline void nand_op_trace(const char *prefix,
891 const struct nand_op_instr *instr)
893 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
894 switch (instr->type) {
895 case NAND_OP_CMD_INSTR:
896 pr_debug("%sCMD [0x%02x]\n", prefix,
897 instr->ctx.cmd.opcode);
899 case NAND_OP_ADDR_INSTR:
900 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
901 instr->ctx.addr.naddrs,
902 instr->ctx.addr.naddrs < 64 ?
903 instr->ctx.addr.naddrs : 64,
904 instr->ctx.addr.addrs);
906 case NAND_OP_DATA_IN_INSTR:
907 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
909 instr->ctx.data.force_8bit ?
910 ", force 8-bit" : "");
912 case NAND_OP_DATA_OUT_INSTR:
913 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
915 instr->ctx.data.force_8bit ?
916 ", force 8-bit" : "");
918 case NAND_OP_WAITRDY_INSTR:
919 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
920 instr->ctx.waitrdy.timeout_ms);
927 * struct nand_controller_ops - Controller operations
929 * @attach_chip: this method is called after the NAND detection phase after
930 * flash ID and MTD fields such as erase size, page size and OOB
931 * size have been set up. ECC requirements are available if
932 * provided by the NAND chip or device tree. Typically used to
933 * choose the appropriate ECC configuration and allocate
934 * associated resources.
935 * This hook is optional.
936 * @detach_chip: free all resources allocated/claimed in
937 * nand_controller_ops->attach_chip().
938 * This hook is optional.
939 * @exec_op: controller specific method to execute NAND operations.
940 * This method replaces chip->legacy.cmdfunc(),
941 * chip->legacy.{read,write}_{buf,byte,word}(),
942 * chip->legacy.dev_ready() and chip->legacy.waifunc().
943 * @setup_interface: setup the data interface and timing. If chipnr is set to
944 * %NAND_DATA_IFACE_CHECK_ONLY this means the configuration
945 * should not be applied but only checked.
946 * This hook is optional.
948 struct nand_controller_ops {
949 int (*attach_chip)(struct nand_chip *chip);
950 void (*detach_chip)(struct nand_chip *chip);
951 int (*exec_op)(struct nand_chip *chip,
952 const struct nand_operation *op,
954 int (*setup_interface)(struct nand_chip *chip, int chipnr,
955 const struct nand_interface_config *conf);
959 * struct nand_controller - Structure used to describe a NAND controller
961 * @lock: lock used to serialize accesses to the NAND controller
962 * @ops: NAND controller operations.
964 struct nand_controller {
966 const struct nand_controller_ops *ops;
969 static inline void nand_controller_init(struct nand_controller *nfc)
971 mutex_init(&nfc->lock);
975 * struct nand_legacy - NAND chip legacy fields/hooks
976 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
977 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
978 * @select_chip: select/deselect a specific target/die
979 * @read_byte: read one byte from the chip
980 * @write_byte: write a single byte to the chip on the low 8 I/O lines
981 * @write_buf: write data from the buffer to the chip
982 * @read_buf: read data from the chip into the buffer
983 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
984 * to write command and address
985 * @cmdfunc: hardware specific function for writing commands to the chip.
986 * @dev_ready: hardware specific function for accessing device ready/busy line.
987 * If set to NULL no access to ready/busy is available and the
988 * ready/busy information is read from the chip status register.
989 * @waitfunc: hardware specific function for wait on ready.
990 * @block_bad: check if a block is bad, using OOB markers
991 * @block_markbad: mark a block bad
992 * @set_features: set the NAND chip features
993 * @get_features: get the NAND chip features
994 * @chip_delay: chip dependent delay for transferring data from array to read
996 * @dummy_controller: dummy controller implementation for drivers that can
997 * only control a single chip
999 * If you look at this structure you're already wrong. These fields/hooks are
1002 struct nand_legacy {
1003 void __iomem *IO_ADDR_R;
1004 void __iomem *IO_ADDR_W;
1005 void (*select_chip)(struct nand_chip *chip, int cs);
1006 u8 (*read_byte)(struct nand_chip *chip);
1007 void (*write_byte)(struct nand_chip *chip, u8 byte);
1008 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1009 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1010 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1011 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1013 int (*dev_ready)(struct nand_chip *chip);
1014 int (*waitfunc)(struct nand_chip *chip);
1015 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1016 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1017 int (*set_features)(struct nand_chip *chip, int feature_addr,
1018 u8 *subfeature_para);
1019 int (*get_features)(struct nand_chip *chip, int feature_addr,
1020 u8 *subfeature_para);
1022 struct nand_controller dummy_controller;
1026 * struct nand_chip_ops - NAND chip operations
1027 * @suspend: Suspend operation
1028 * @resume: Resume operation
1029 * @lock_area: Lock operation
1030 * @unlock_area: Unlock operation
1031 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1032 * @choose_interface_config: Choose the best interface configuration
1034 struct nand_chip_ops {
1035 int (*suspend)(struct nand_chip *chip);
1036 void (*resume)(struct nand_chip *chip);
1037 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1038 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1039 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1040 int (*choose_interface_config)(struct nand_chip *chip,
1041 struct nand_interface_config *iface);
1045 * struct nand_manufacturer - NAND manufacturer structure
1046 * @desc: The manufacturer description
1047 * @priv: Private information for the manufacturer driver
1049 struct nand_manufacturer {
1050 const struct nand_manufacturer_desc *desc;
1055 * struct nand_chip - NAND Private Flash Chip Data
1056 * @base: Inherit from the generic NAND device
1057 * @id: Holds NAND ID
1058 * @parameters: Holds generic parameters under an easily readable form
1059 * @manufacturer: Manufacturer information
1060 * @ops: NAND chip operations
1061 * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try
1062 * to use any of these fields/hooks, and if you're modifying an
1063 * existing driver that is using those fields/hooks, you should
1064 * consider reworking the driver and avoid using them.
1065 * @options: Various chip options. They can partly be set to inform nand_scan
1066 * about special functionality. See the defines for further
1068 * @current_interface_config: The currently used NAND interface configuration
1069 * @best_interface_config: The best NAND interface configuration which fits both
1070 * the NAND chip and NAND controller constraints. If
1071 * unset, the default reset interface configuration must
1073 * @bbt_erase_shift: Number of address bits in a bbt entry
1074 * @bbt_options: Bad block table specific options. All options used here must
1075 * come from bbm.h. By default, these options will be copied to
1076 * the appropriate nand_bbt_descr's.
1077 * @badblockpos: Bad block marker position in the oob area
1078 * @badblockbits: Minimum number of set bits in a good block's bad block marker
1079 * position; i.e., BBM = 11110111b is good when badblockbits = 7
1080 * @bbt_td: Bad block table descriptor for flash lookup
1081 * @bbt_md: Bad block table mirror descriptor
1082 * @badblock_pattern: Bad block scan pattern used for initial bad block scan
1083 * @bbt: Bad block table pointer
1084 * @page_shift: Number of address bits in a page (column address bits)
1085 * @phys_erase_shift: Number of address bits in a physical eraseblock
1086 * @chip_shift: Number of address bits in one chip
1087 * @pagemask: Page number mask = number of (pages / chip) - 1
1088 * @subpagesize: Holds the subpagesize
1089 * @data_buf: Buffer for data, size is (page size + oobsize)
1090 * @oob_poi: pointer on the OOB area covered by data_buf
1091 * @pagecache: Structure containing page cache related fields
1092 * @pagecache.bitflips: Number of bitflips of the cached page
1093 * @pagecache.page: Page number currently in the cache. -1 means no page is
1095 * @buf_align: Minimum buffer alignment required by a platform
1096 * @lock: Lock protecting the suspended field. Also used to serialize accesses
1097 * to the NAND device
1098 * @suspended: Set to 1 when the device is suspended, 0 when it's not
1099 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1100 * should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
1101 * NAND Controller drivers should not modify this value, but they're
1102 * allowed to read it.
1103 * @read_retries: The number of read retry modes supported
1104 * @controller: The hardware controller structure which is shared among multiple
1105 * independent devices
1106 * @ecc: The ECC controller structure
1107 * @priv: Chip private data
1110 struct nand_device base;
1112 struct nand_parameters parameters;
1113 struct nand_manufacturer manufacturer;
1114 struct nand_chip_ops ops;
1115 struct nand_legacy legacy;
1116 unsigned int options;
1118 /* Data interface */
1119 const struct nand_interface_config *current_interface_config;
1120 struct nand_interface_config *best_interface_config;
1122 /* Bad block information */
1123 unsigned int bbt_erase_shift;
1124 unsigned int bbt_options;
1125 unsigned int badblockpos;
1126 unsigned int badblockbits;
1127 struct nand_bbt_descr *bbt_td;
1128 struct nand_bbt_descr *bbt_md;
1129 struct nand_bbt_descr *badblock_pattern;
1132 /* Device internal layout */
1133 unsigned int page_shift;
1134 unsigned int phys_erase_shift;
1135 unsigned int chip_shift;
1136 unsigned int pagemask;
1137 unsigned int subpagesize;
1143 unsigned int bitflips;
1146 unsigned long buf_align;
1150 unsigned int suspended : 1;
1155 struct nand_controller *controller;
1156 struct nand_ecc_ctrl ecc;
1160 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1162 return container_of(mtd, struct nand_chip, base.mtd);
1165 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1167 return &chip->base.mtd;
1170 static inline void *nand_get_controller_data(struct nand_chip *chip)
1175 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1180 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1183 chip->manufacturer.priv = priv;
1186 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1188 return chip->manufacturer.priv;
1191 static inline void nand_set_flash_node(struct nand_chip *chip,
1192 struct device_node *np)
1194 mtd_set_of_node(nand_to_mtd(chip), np);
1197 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1199 return mtd_get_of_node(nand_to_mtd(chip));
1203 * nand_get_interface_config - Retrieve the current interface configuration
1205 * @chip: The NAND chip
1207 static inline const struct nand_interface_config *
1208 nand_get_interface_config(struct nand_chip *chip)
1210 return chip->current_interface_config;
1214 * A helper for defining older NAND chips where the second ID byte fully
1215 * defined the chip, including the geometry (chip size, eraseblock size, page
1216 * size). All these chips have 512 bytes NAND page size.
1218 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1219 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1220 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1223 * A helper for defining newer chips which report their page size and
1224 * eraseblock size via the extended ID bytes.
1226 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1227 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1228 * device ID now only represented a particular total chip size (and voltage,
1229 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1230 * using the same device ID.
1232 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1233 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1236 #define NAND_ECC_INFO(_strength, _step) \
1237 { .strength_ds = (_strength), .step_ds = (_step) }
1238 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1239 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1242 * struct nand_flash_dev - NAND Flash Device ID Structure
1243 * @name: a human-readable name of the NAND chip
1244 * @dev_id: the device ID (the second byte of the full chip ID array)
1245 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1246 * memory address as ``id[0]``)
1247 * @dev_id: device ID part of the full chip ID array (refers the same memory
1248 * address as ``id[1]``)
1249 * @id: full device ID array
1250 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1251 * well as the eraseblock size) is determined from the extended NAND
1253 * @chipsize: total chip size in MiB
1254 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1255 * @options: stores various chip bit options
1256 * @id_len: The valid length of the @id.
1257 * @oobsize: OOB size
1258 * @ecc: ECC correctability and step information from the datasheet.
1259 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1260 * @ecc_strength_ds in nand_chip{}.
1261 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1262 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1263 * For example, the "4bit ECC for each 512Byte" can be set with
1264 * NAND_ECC_INFO(4, 512).
1266 struct nand_flash_dev {
1273 uint8_t id[NAND_MAX_ID_LEN];
1275 unsigned int pagesize;
1276 unsigned int chipsize;
1277 unsigned int erasesize;
1278 unsigned int options;
1282 uint16_t strength_ds;
1287 int nand_create_bbt(struct nand_chip *chip);
1290 * Check if it is a SLC nand.
1291 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1292 * We do not distinguish the MLC and TLC now.
1294 static inline bool nand_is_slc(struct nand_chip *chip)
1296 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1297 "chip->bits_per_cell is used uninitialized\n");
1298 return nanddev_bits_per_cell(&chip->base) == 1;
1302 * Check if the opcode's address should be sent only on the lower 8 bits
1303 * @command: opcode to check
1305 static inline int nand_opcode_8bits(unsigned int command)
1308 case NAND_CMD_READID:
1309 case NAND_CMD_PARAM:
1310 case NAND_CMD_GET_FEATURES:
1311 case NAND_CMD_SET_FEATURES:
1319 int nand_check_erased_ecc_chunk(void *data, int datalen,
1320 void *ecc, int ecclen,
1321 void *extraoob, int extraooblen,
1324 int nand_ecc_choose_conf(struct nand_chip *chip,
1325 const struct nand_ecc_caps *caps, int oobavail);
1327 /* Default write_oob implementation */
1328 int nand_write_oob_std(struct nand_chip *chip, int page);
1330 /* Default read_oob implementation */
1331 int nand_read_oob_std(struct nand_chip *chip, int page);
1333 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1334 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1335 u8 *subfeature_param);
1337 /* read_page_raw implementations */
1338 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1340 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1341 int oob_required, int page);
1343 /* write_page_raw implementations */
1344 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1345 int oob_required, int page);
1346 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1347 int oob_required, int page);
1349 /* Reset and initialize a NAND device */
1350 int nand_reset(struct nand_chip *chip, int chipnr);
1352 /* NAND operation helpers */
1353 int nand_reset_op(struct nand_chip *chip);
1354 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1356 int nand_status_op(struct nand_chip *chip, u8 *status);
1357 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1358 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1359 unsigned int offset_in_page, void *buf, unsigned int len);
1360 int nand_change_read_column_op(struct nand_chip *chip,
1361 unsigned int offset_in_page, void *buf,
1362 unsigned int len, bool force_8bit);
1363 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1364 unsigned int offset_in_page, void *buf, unsigned int len);
1365 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1366 unsigned int offset_in_page, const void *buf,
1368 int nand_prog_page_end_op(struct nand_chip *chip);
1369 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1370 unsigned int offset_in_page, const void *buf,
1372 int nand_change_write_column_op(struct nand_chip *chip,
1373 unsigned int offset_in_page, const void *buf,
1374 unsigned int len, bool force_8bit);
1375 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1376 bool force_8bit, bool check_only);
1377 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1378 unsigned int len, bool force_8bit);
1380 /* Scan and identify a NAND device */
1381 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1382 struct nand_flash_dev *ids);
1384 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1386 return nand_scan_with_ids(chip, max_chips, NULL);
1389 /* Internal helper for board drivers which need to override command function */
1390 void nand_wait_ready(struct nand_chip *chip);
1393 * Free resources held by the NAND device, must be called on error after a
1394 * sucessful nand_scan().
1396 void nand_cleanup(struct nand_chip *chip);
1399 * External helper for controller drivers that have to implement the WAITRDY
1400 * instruction and have no physical pin to check it.
1402 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1404 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1405 unsigned long timeout_ms);
1407 /* Select/deselect a NAND target. */
1408 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1409 void nand_deselect_target(struct nand_chip *chip);
1412 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1413 unsigned int src_off, unsigned int nbits);
1416 * nand_get_data_buf() - Get the internal page buffer
1417 * @chip: NAND chip object
1419 * Returns the pre-allocated page buffer after invalidating the cache. This
1420 * function should be used by drivers that do not want to allocate their own
1421 * bounce buffer and still need such a buffer for specific operations (most
1422 * commonly when reading OOB data only).
1424 * Be careful to never call this function in the write/write_oob path, because
1425 * the core may have placed the data to be written out in this buffer.
1427 * Return: pointer to the page cache buffer
1429 static inline void *nand_get_data_buf(struct nand_chip *chip)
1431 chip->pagecache.page = -1;
1433 return chip->data_buf;
1436 #endif /* __LINUX_MTD_RAWNAND_H */