2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
29 /* Scan and identify a NAND device */
30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
32 * Separate phases of nand_scan(), allowing board driver to intervene
33 * and override command or ECC setup according to flash type.
35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
36 struct nand_flash_dev *table);
37 extern int nand_scan_tail(struct mtd_info *mtd);
39 /* Free resources held by the NAND device */
40 extern void nand_release(struct mtd_info *mtd);
42 /* Internal helper for board drivers which need to override command function */
43 extern void nand_wait_ready(struct mtd_info *mtd);
45 /* locks all blocks present in the device */
46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
48 /* unlocks specified locked blocks */
49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
51 /* The maximum number of NAND chips in an array */
52 #define NAND_MAX_CHIPS 8
55 * Constants for hardware specific CLE/ALE/NCE function
57 * These are bits which can be or'ed to set/clear multiple
60 /* Select the chip by setting nCE to low */
62 /* Select the command latch by setting CLE to high */
64 /* Select the address latch by setting ALE to high */
67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69 #define NAND_CTRL_CHANGE 0x80
72 * Standard NAND flash commands
74 #define NAND_CMD_READ0 0
75 #define NAND_CMD_READ1 1
76 #define NAND_CMD_RNDOUT 5
77 #define NAND_CMD_PAGEPROG 0x10
78 #define NAND_CMD_READOOB 0x50
79 #define NAND_CMD_ERASE1 0x60
80 #define NAND_CMD_STATUS 0x70
81 #define NAND_CMD_SEQIN 0x80
82 #define NAND_CMD_RNDIN 0x85
83 #define NAND_CMD_READID 0x90
84 #define NAND_CMD_ERASE2 0xd0
85 #define NAND_CMD_PARAM 0xec
86 #define NAND_CMD_GET_FEATURES 0xee
87 #define NAND_CMD_SET_FEATURES 0xef
88 #define NAND_CMD_RESET 0xff
90 #define NAND_CMD_LOCK 0x2a
91 #define NAND_CMD_UNLOCK1 0x23
92 #define NAND_CMD_UNLOCK2 0x24
94 /* Extended commands for large page devices */
95 #define NAND_CMD_READSTART 0x30
96 #define NAND_CMD_RNDOUTSTART 0xE0
97 #define NAND_CMD_CACHEDPROG 0x15
99 #define NAND_CMD_NONE -1
102 #define NAND_STATUS_FAIL 0x01
103 #define NAND_STATUS_FAIL_N1 0x02
104 #define NAND_STATUS_TRUE_READY 0x20
105 #define NAND_STATUS_READY 0x40
106 #define NAND_STATUS_WP 0x80
109 * Constants for ECC_MODES
115 NAND_ECC_HW_SYNDROME,
116 NAND_ECC_HW_OOB_FIRST,
121 * Constants for Hardware ECC
123 /* Reset Hardware ECC for read */
124 #define NAND_ECC_READ 0
125 /* Reset Hardware ECC for write */
126 #define NAND_ECC_WRITE 1
127 /* Enable Hardware ECC before syndrome is read back from flash */
128 #define NAND_ECC_READSYN 2
130 /* Bit mask for flags passed to do_nand_read_ecc */
131 #define NAND_GET_DEVICE 0x80
135 * Option constants for bizarre disfunctionality and real
138 /* Buswidth is 16 bit */
139 #define NAND_BUSWIDTH_16 0x00000002
140 /* Chip has cache program function */
141 #define NAND_CACHEPRG 0x00000008
143 * Chip requires ready check on read (for auto-incremented sequential read).
144 * True only for small page devices; large page devices do not support
147 #define NAND_NEED_READRDY 0x00000100
149 /* Chip does not allow subpage writes */
150 #define NAND_NO_SUBPAGE_WRITE 0x00000200
152 /* Device is one of 'new' xD cards that expose fake nand command set */
153 #define NAND_BROKEN_XD 0x00000400
155 /* Device behaves just like nand, but is readonly */
156 #define NAND_ROM 0x00000800
158 /* Device supports subpage reads */
159 #define NAND_SUBPAGE_READ 0x00001000
161 /* Options valid for Samsung large page devices */
162 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
164 /* Macros to identify the above */
165 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
166 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
168 /* Non chip related options */
169 /* This option skips the bbt scan during initialization. */
170 #define NAND_SKIP_BBTSCAN 0x00010000
172 * This option is defined if the board driver allocates its own buffers
173 * (e.g. because it needs them DMA-coherent).
175 #define NAND_OWN_BUFFERS 0x00020000
176 /* Chip may not exist, so silence any errors in scan */
177 #define NAND_SCAN_SILENT_NODEV 0x00040000
179 * Autodetect nand buswidth with readid/onfi.
180 * This suppose the driver will configure the hardware in 8 bits mode
181 * when calling nand_scan_ident, and update its configuration
182 * before calling nand_scan_tail.
184 #define NAND_BUSWIDTH_AUTO 0x00080000
186 /* Options set by nand scan */
187 /* Nand scan has allocated controller struct */
188 #define NAND_CONTROLLER_ALLOC 0x80000000
190 /* Cell info constants */
191 #define NAND_CI_CHIPNR_MSK 0x03
192 #define NAND_CI_CELLTYPE_MSK 0x0C
193 #define NAND_CI_CELLTYPE_SHIFT 2
199 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
200 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
202 /* ONFI timing mode, used in both asynchronous and synchronous mode */
203 #define ONFI_TIMING_MODE_0 (1 << 0)
204 #define ONFI_TIMING_MODE_1 (1 << 1)
205 #define ONFI_TIMING_MODE_2 (1 << 2)
206 #define ONFI_TIMING_MODE_3 (1 << 3)
207 #define ONFI_TIMING_MODE_4 (1 << 4)
208 #define ONFI_TIMING_MODE_5 (1 << 5)
209 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
211 /* ONFI feature address */
212 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
214 /* Vendor-specific feature address (Micron) */
215 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
217 /* ONFI subfeature parameters length */
218 #define ONFI_SUBFEATURE_PARAM_LEN 4
220 /* ONFI optional commands SET/GET FEATURES supported? */
221 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
223 struct nand_onfi_params {
224 /* rev info and features block */
225 /* 'O' 'N' 'F' 'I' */
231 __le16 ext_param_page_length; /* since ONFI 2.1 */
232 u8 num_of_param_pages; /* since ONFI 2.1 */
235 /* manufacturer information block */
236 char manufacturer[12];
242 /* memory organization block */
243 __le32 byte_per_page;
244 __le16 spare_bytes_per_page;
245 __le32 data_bytes_per_ppage;
246 __le16 spare_bytes_per_ppage;
247 __le32 pages_per_block;
248 __le32 blocks_per_lun;
253 __le16 block_endurance;
254 u8 guaranteed_good_blocks;
255 __le16 guaranteed_block_endurance;
256 u8 programs_per_page;
263 /* electrical parameter block */
264 u8 io_pin_capacitance_max;
265 __le16 async_timing_mode;
266 __le16 program_cache_timing_mode;
271 __le16 src_sync_timing_mode;
272 __le16 src_ssync_features;
273 __le16 clk_pin_capacitance_typ;
274 __le16 io_pin_capacitance_typ;
275 __le16 input_pin_capacitance_typ;
276 u8 input_pin_capacitance_max;
277 u8 driver_strength_support;
283 __le16 vendor_revision;
289 #define ONFI_CRC_BASE 0x4F4E
291 /* Extended ECC information Block Definition (since ONFI 2.1) */
292 struct onfi_ext_ecc_info {
296 __le16 block_endurance;
300 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
301 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
302 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
303 struct onfi_ext_section {
308 #define ONFI_EXT_SECTION_MAX 8
310 /* Extended Parameter Page Definition (since ONFI 2.1) */
311 struct onfi_ext_param_page {
313 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
315 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
318 * The actual size of the Extended Parameter Page is in
319 * @ext_param_page_length of nand_onfi_params{}.
320 * The following are the variable length sections.
321 * So we do not add any fields below. Please see the ONFI spec.
325 struct nand_onfi_vendor_micron {
330 u8 dq_imped_num_settings;
331 u8 dq_imped_feat_addr;
332 u8 rb_pulldown_strength;
333 u8 rb_pulldown_strength_feat_addr;
334 u8 rb_pulldown_strength_num_settings;
337 u8 otp_data_prot_addr;
340 u8 read_retry_options;
346 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
347 * @lock: protection lock
348 * @active: the mtd device which holds the controller currently
349 * @wq: wait queue to sleep on if a NAND operation is in
350 * progress used instead of the per chip wait queue
351 * when a hw controller is available.
353 struct nand_hw_control {
355 struct nand_chip *active;
356 wait_queue_head_t wq;
360 * struct nand_ecc_ctrl - Control structure for ECC
362 * @steps: number of ECC steps per page
363 * @size: data bytes per ECC step
364 * @bytes: ECC bytes per step
365 * @strength: max number of correctible bits per ECC step
366 * @total: total number of ECC bytes per page
367 * @prepad: padding information for syndrome based ECC generators
368 * @postpad: padding information for syndrome based ECC generators
369 * @layout: ECC layout control struct pointer
370 * @priv: pointer to private ECC control data
371 * @hwctl: function to control hardware ECC generator. Must only
372 * be provided if an hardware ECC is available
373 * @calculate: function for ECC calculation or readback from ECC hardware
374 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
375 * @read_page_raw: function to read a raw page without ECC
376 * @write_page_raw: function to write a raw page without ECC
377 * @read_page: function to read a page according to the ECC generator
378 * requirements; returns maximum number of bitflips corrected in
379 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
380 * @read_subpage: function to read parts of the page covered by ECC;
381 * returns same as read_page()
382 * @write_subpage: function to write parts of the page covered by ECC.
383 * @write_page: function to write a page according to the ECC generator
385 * @write_oob_raw: function to write chip OOB data without ECC
386 * @read_oob_raw: function to read chip OOB data without ECC
387 * @read_oob: function to read chip OOB data
388 * @write_oob: function to write chip OOB data
390 struct nand_ecc_ctrl {
391 nand_ecc_modes_t mode;
399 struct nand_ecclayout *layout;
401 void (*hwctl)(struct mtd_info *mtd, int mode);
402 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
404 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
406 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
407 uint8_t *buf, int oob_required, int page);
408 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
409 const uint8_t *buf, int oob_required);
410 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
411 uint8_t *buf, int oob_required, int page);
412 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
413 uint32_t offs, uint32_t len, uint8_t *buf);
414 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
415 uint32_t offset, uint32_t data_len,
416 const uint8_t *data_buf, int oob_required);
417 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
418 const uint8_t *buf, int oob_required);
419 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
421 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
423 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
424 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
429 * struct nand_buffers - buffer structure for read/write
430 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
431 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
432 * @databuf: buffer pointer for data, size is (page size + oobsize).
434 * Do not change the order of buffers. databuf and oobrbuf must be in
437 struct nand_buffers {
444 * struct nand_chip - NAND Private Flash Chip Data
445 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
447 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
449 * @read_byte: [REPLACEABLE] read one byte from the chip
450 * @read_word: [REPLACEABLE] read one word from the chip
451 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
453 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
454 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
455 * @select_chip: [REPLACEABLE] select chip nr
456 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
457 * @block_markbad: [REPLACEABLE] mark a block bad
458 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
459 * ALE/CLE/nCE. Also used to write command and address
460 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
461 * mtd->oobsize, mtd->writesize and so on.
462 * @id_data contains the 8 bytes values of NAND_CMD_READID.
463 * Return with the bus width.
464 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
465 * device ready/busy line. If set to NULL no access to
466 * ready/busy is available and the ready/busy information
467 * is read from the chip status register.
468 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
469 * commands to the chip.
470 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
472 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
473 * setting the read-retry mode. Mostly needed for MLC NAND.
474 * @ecc: [BOARDSPECIFIC] ECC control structure
475 * @buffers: buffer structure for read/write
476 * @hwcontrol: platform-specific hardware control structure
477 * @erase_cmd: [INTERN] erase command write function, selectable due
479 * @scan_bbt: [REPLACEABLE] function to scan bad block table
480 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
481 * data from array to read regs (tR).
482 * @state: [INTERN] the current state of the NAND device
483 * @oob_poi: "poison value buffer," used for laying out OOB data
485 * @page_shift: [INTERN] number of address bits in a page (column
487 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
488 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
489 * @chip_shift: [INTERN] number of address bits in one chip
490 * @options: [BOARDSPECIFIC] various chip options. They can partly
491 * be set to inform nand_scan about special functionality.
492 * See the defines for further explanation.
493 * @bbt_options: [INTERN] bad block specific options. All options used
494 * here must come from bbm.h. By default, these options
495 * will be copied to the appropriate nand_bbt_descr's.
496 * @badblockpos: [INTERN] position of the bad block marker in the oob
498 * @badblockbits: [INTERN] minimum number of set bits in a good block's
499 * bad block marker position; i.e., BBM == 11110111b is
500 * not bad when badblockbits == 7
501 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
502 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
503 * Minimum amount of bit errors per @ecc_step_ds guaranteed
504 * to be correctable. If unknown, set to zero.
505 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
506 * also from the datasheet. It is the recommended ECC step
507 * size, if known; if unknown, set to zero.
508 * @numchips: [INTERN] number of physical chips
509 * @chipsize: [INTERN] the size of one chip for multichip arrays
510 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
511 * @pagebuf: [INTERN] holds the pagenumber which is currently in
513 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
514 * currently in data_buf.
515 * @subpagesize: [INTERN] holds the subpagesize
516 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
517 * non 0 if ONFI supported.
518 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
519 * supported, 0 otherwise.
520 * @read_retries: [INTERN] the number of read retry modes supported
521 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
522 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
523 * @bbt: [INTERN] bad block table pointer
524 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
526 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
527 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
529 * @controller: [REPLACEABLE] a pointer to a hardware controller
530 * structure which is shared among multiple independent
532 * @priv: [OPTIONAL] pointer to private chip data
533 * @errstat: [OPTIONAL] hardware specific function to perform
534 * additional error status checks (determine if errors are
536 * @write_page: [REPLACEABLE] High-level page write function
540 void __iomem *IO_ADDR_R;
541 void __iomem *IO_ADDR_W;
543 uint8_t (*read_byte)(struct mtd_info *mtd);
544 u16 (*read_word)(struct mtd_info *mtd);
545 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
546 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
547 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
548 void (*select_chip)(struct mtd_info *mtd, int chip);
549 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
550 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
551 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
552 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
554 int (*dev_ready)(struct mtd_info *mtd);
555 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
557 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
558 void (*erase_cmd)(struct mtd_info *mtd, int page);
559 int (*scan_bbt)(struct mtd_info *mtd);
560 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
561 int status, int page);
562 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
563 uint32_t offset, int data_len, const uint8_t *buf,
564 int oob_required, int page, int cached, int raw);
565 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
566 int feature_addr, uint8_t *subfeature_para);
567 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
568 int feature_addr, uint8_t *subfeature_para);
569 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
572 unsigned int options;
573 unsigned int bbt_options;
576 int phys_erase_shift;
583 unsigned int pagebuf_bitflips;
585 uint8_t bits_per_cell;
586 uint16_t ecc_strength_ds;
587 uint16_t ecc_step_ds;
592 struct nand_onfi_params onfi_params;
599 struct nand_hw_control *controller;
601 struct nand_ecc_ctrl ecc;
602 struct nand_buffers *buffers;
603 struct nand_hw_control hwcontrol;
606 struct nand_bbt_descr *bbt_td;
607 struct nand_bbt_descr *bbt_md;
609 struct nand_bbt_descr *badblock_pattern;
615 * NAND Flash Manufacturer ID Codes
617 #define NAND_MFR_TOSHIBA 0x98
618 #define NAND_MFR_SAMSUNG 0xec
619 #define NAND_MFR_FUJITSU 0x04
620 #define NAND_MFR_NATIONAL 0x8f
621 #define NAND_MFR_RENESAS 0x07
622 #define NAND_MFR_STMICRO 0x20
623 #define NAND_MFR_HYNIX 0xad
624 #define NAND_MFR_MICRON 0x2c
625 #define NAND_MFR_AMD 0x01
626 #define NAND_MFR_MACRONIX 0xc2
627 #define NAND_MFR_EON 0x92
628 #define NAND_MFR_SANDISK 0x45
629 #define NAND_MFR_INTEL 0x89
631 /* The maximum expected count of bytes in the NAND ID sequence */
632 #define NAND_MAX_ID_LEN 8
635 * A helper for defining older NAND chips where the second ID byte fully
636 * defined the chip, including the geometry (chip size, eraseblock size, page
637 * size). All these chips have 512 bytes NAND page size.
639 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
640 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
641 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
644 * A helper for defining newer chips which report their page size and
645 * eraseblock size via the extended ID bytes.
647 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
648 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
649 * device ID now only represented a particular total chip size (and voltage,
650 * buswidth), and the page size, eraseblock size, and OOB size could vary while
651 * using the same device ID.
653 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
654 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
657 #define NAND_ECC_INFO(_strength, _step) \
658 { .strength_ds = (_strength), .step_ds = (_step) }
659 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
660 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
663 * struct nand_flash_dev - NAND Flash Device ID Structure
664 * @name: a human-readable name of the NAND chip
665 * @dev_id: the device ID (the second byte of the full chip ID array)
666 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
667 * memory address as @id[0])
668 * @dev_id: device ID part of the full chip ID array (refers the same memory
670 * @id: full device ID array
671 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
672 * well as the eraseblock size) is determined from the extended NAND
674 * @chipsize: total chip size in MiB
675 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
676 * @options: stores various chip bit options
677 * @id_len: The valid length of the @id.
679 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
680 * @ecc_strength_ds in nand_chip{}.
681 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
682 * @ecc_step_ds in nand_chip{}, also from the datasheet.
683 * For example, the "4bit ECC for each 512Byte" can be set with
684 * NAND_ECC_INFO(4, 512).
686 struct nand_flash_dev {
693 uint8_t id[NAND_MAX_ID_LEN];
695 unsigned int pagesize;
696 unsigned int chipsize;
697 unsigned int erasesize;
698 unsigned int options;
702 uint16_t strength_ds;
708 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
709 * @name: Manufacturer name
710 * @id: manufacturer ID code of device.
712 struct nand_manufacturers {
717 extern struct nand_flash_dev nand_flash_ids[];
718 extern struct nand_manufacturers nand_manuf_ids[];
720 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
721 extern int nand_default_bbt(struct mtd_info *mtd);
722 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
723 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
724 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
726 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
727 size_t *retlen, uint8_t *buf);
730 * struct platform_nand_chip - chip level device structure
731 * @nr_chips: max. number of chips to scan for
732 * @chip_offset: chip number offset
733 * @nr_partitions: number of partitions pointed to by partitions (or zero)
734 * @partitions: mtd partition list
735 * @chip_delay: R/B delay value in us
736 * @options: Option flags, e.g. 16bit buswidth
737 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
738 * @ecclayout: ECC layout info structure
739 * @part_probe_types: NULL-terminated array of probe types
741 struct platform_nand_chip {
745 struct mtd_partition *partitions;
746 struct nand_ecclayout *ecclayout;
748 unsigned int options;
749 unsigned int bbt_options;
750 const char **part_probe_types;
754 struct platform_device;
757 * struct platform_nand_ctrl - controller level device structure
758 * @probe: platform specific function to probe/setup hardware
759 * @remove: platform specific function to remove/teardown hardware
760 * @hwcontrol: platform specific hardware control structure
761 * @dev_ready: platform specific function to read ready/busy pin
762 * @select_chip: platform specific chip select function
763 * @cmd_ctrl: platform specific function for controlling
764 * ALE/CLE/nCE. Also used to write command and address
765 * @write_buf: platform specific function for write buffer
766 * @read_buf: platform specific function for read buffer
767 * @read_byte: platform specific function to read one byte from chip
768 * @priv: private data to transport driver specific settings
770 * All fields are optional and depend on the hardware driver requirements
772 struct platform_nand_ctrl {
773 int (*probe)(struct platform_device *pdev);
774 void (*remove)(struct platform_device *pdev);
775 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
776 int (*dev_ready)(struct mtd_info *mtd);
777 void (*select_chip)(struct mtd_info *mtd, int chip);
778 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
779 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
780 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
781 unsigned char (*read_byte)(struct mtd_info *mtd);
786 * struct platform_nand_data - container structure for platform-specific data
787 * @chip: chip level chip structure
788 * @ctrl: controller level device structure
790 struct platform_nand_data {
791 struct platform_nand_chip chip;
792 struct platform_nand_ctrl ctrl;
795 /* Some helpers to access the data structures */
797 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
799 struct nand_chip *chip = mtd->priv;
804 /* return the supported features. */
805 static inline int onfi_feature(struct nand_chip *chip)
807 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
810 /* return the supported asynchronous timing mode. */
811 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
813 if (!chip->onfi_version)
814 return ONFI_TIMING_MODE_UNKNOWN;
815 return le16_to_cpu(chip->onfi_params.async_timing_mode);
818 /* return the supported synchronous timing mode. */
819 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
821 if (!chip->onfi_version)
822 return ONFI_TIMING_MODE_UNKNOWN;
823 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
827 * Check if it is a SLC nand.
828 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
829 * We do not distinguish the MLC and TLC now.
831 static inline bool nand_is_slc(struct nand_chip *chip)
833 return chip->bits_per_cell == 1;
837 * Check if the opcode's address should be sent only on the lower 8 bits
838 * @command: opcode to check
840 static inline int nand_opcode_8bits(unsigned int command)
842 return command == NAND_CMD_READID;
845 #endif /* __LINUX_MTD_NAND_H */