2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
233 struct mlx5_ifc_flow_table_fields_supported_bits {
236 u8 outer_ether_type[0x1];
237 u8 reserved_at_3[0x1];
238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
241 u8 reserved_at_7[0x1];
242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
245 u8 reserved_at_b[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
260 u8 reserved_at_1a[0x5];
261 u8 source_eswitch_port[0x1];
265 u8 inner_ether_type[0x1];
266 u8 reserved_at_23[0x1];
267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
270 u8 reserved_at_27[0x1];
271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
274 u8 reserved_at_2b[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
286 u8 reserved_at_37[0x9];
288 u8 reserved_at_40[0x40];
291 struct mlx5_ifc_flow_table_prop_layout_bits {
293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
295 u8 flow_modify_en[0x1];
297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
301 u8 reserved_at_9[0x17];
303 u8 reserved_at_20[0x2];
304 u8 log_max_ft_size[0x6];
305 u8 reserved_at_28[0x10];
306 u8 max_ft_level[0x8];
308 u8 reserved_at_40[0x20];
310 u8 reserved_at_60[0x18];
311 u8 log_max_ft_num[0x8];
313 u8 reserved_at_80[0x18];
314 u8 log_max_destination[0x8];
316 u8 reserved_at_a0[0x18];
317 u8 log_max_flow[0x8];
319 u8 reserved_at_c0[0x40];
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
326 struct mlx5_ifc_odp_per_transport_service_cap_bits {
331 u8 reserved_at_4[0x1];
333 u8 reserved_at_6[0x1a];
336 struct mlx5_ifc_ipv4_layout_bits {
337 u8 reserved_at_0[0x60];
342 struct mlx5_ifc_ipv6_layout_bits {
346 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
349 u8 reserved_at_0[0x80];
352 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
369 u8 reserved_at_91[0x1];
371 u8 reserved_at_93[0x4];
377 u8 reserved_at_c0[0x20];
382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
387 struct mlx5_ifc_fte_match_set_misc_bits {
388 u8 reserved_at_0[0x8];
391 u8 reserved_at_20[0x10];
392 u8 source_port[0x10];
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
401 u8 outer_second_vlan_tag[0x1];
402 u8 inner_second_vlan_tag[0x1];
403 u8 reserved_at_62[0xe];
404 u8 gre_protocol[0x10];
410 u8 reserved_at_b8[0x8];
412 u8 reserved_at_c0[0x20];
414 u8 reserved_at_e0[0xc];
415 u8 outer_ipv6_flow_label[0x14];
417 u8 reserved_at_100[0xc];
418 u8 inner_ipv6_flow_label[0x14];
420 u8 reserved_at_120[0xe0];
423 struct mlx5_ifc_cmd_pas_bits {
427 u8 reserved_at_34[0xc];
430 struct mlx5_ifc_uint64_bits {
437 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
438 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
439 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
440 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
441 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
442 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
443 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
444 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
445 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
446 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
449 struct mlx5_ifc_ads_bits {
452 u8 reserved_at_2[0xe];
455 u8 reserved_at_20[0x8];
461 u8 reserved_at_45[0x3];
462 u8 src_addr_index[0x8];
463 u8 reserved_at_50[0x4];
467 u8 reserved_at_60[0x4];
471 u8 rgid_rip[16][0x8];
473 u8 reserved_at_100[0x4];
476 u8 reserved_at_106[0x1];
491 struct mlx5_ifc_flow_table_nic_cap_bits {
492 u8 nic_rx_multi_path_tirs[0x1];
493 u8 nic_rx_multi_path_tirs_fts[0x1];
494 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
495 u8 reserved_at_3[0x1fd];
497 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
499 u8 reserved_at_400[0x200];
501 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
505 u8 reserved_at_a00[0x200];
507 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
509 u8 reserved_at_e00[0x7200];
512 struct mlx5_ifc_flow_table_eswitch_cap_bits {
513 u8 reserved_at_0[0x200];
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
521 u8 reserved_at_800[0x7800];
524 struct mlx5_ifc_e_switch_cap_bits {
525 u8 vport_svlan_strip[0x1];
526 u8 vport_cvlan_strip[0x1];
527 u8 vport_svlan_insert[0x1];
528 u8 vport_cvlan_insert_if_not_exist[0x1];
529 u8 vport_cvlan_insert_overwrite[0x1];
530 u8 reserved_at_5[0x19];
531 u8 nic_vport_node_guid_modify[0x1];
532 u8 nic_vport_port_guid_modify[0x1];
534 u8 vxlan_encap_decap[0x1];
535 u8 nvgre_encap_decap[0x1];
536 u8 reserved_at_22[0x9];
537 u8 log_max_encap_headers[0x5];
539 u8 max_encap_header_size[0xa];
541 u8 reserved_40[0x7c0];
545 struct mlx5_ifc_qos_cap_bits {
546 u8 packet_pacing[0x1];
547 u8 esw_scheduling[0x1];
548 u8 reserved_at_2[0x1e];
550 u8 reserved_at_20[0x20];
552 u8 packet_pacing_max_rate[0x20];
554 u8 packet_pacing_min_rate[0x20];
556 u8 reserved_at_80[0x10];
557 u8 packet_pacing_rate_table_size[0x10];
559 u8 esw_element_type[0x10];
560 u8 esw_tsar_type[0x10];
562 u8 reserved_at_c0[0x10];
563 u8 max_qos_para_vport[0x10];
565 u8 max_tsar_bw_share[0x20];
567 u8 reserved_at_100[0x700];
570 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
574 u8 lro_psh_flag[0x1];
575 u8 lro_time_stamp[0x1];
576 u8 reserved_at_5[0x3];
577 u8 self_lb_en_modifiable[0x1];
578 u8 reserved_at_9[0x2];
580 u8 reserved_at_10[0x2];
581 u8 wqe_inline_mode[0x2];
582 u8 rss_ind_tbl_cap[0x4];
585 u8 reserved_at_1a[0x1];
586 u8 tunnel_lso_const_out_ip_id[0x1];
587 u8 reserved_at_1c[0x2];
588 u8 tunnel_statless_gre[0x1];
589 u8 tunnel_stateless_vxlan[0x1];
591 u8 reserved_at_20[0x20];
593 u8 reserved_at_40[0x10];
594 u8 lro_min_mss_size[0x10];
596 u8 reserved_at_60[0x120];
598 u8 lro_timer_supported_periods[4][0x20];
600 u8 reserved_at_200[0x600];
603 struct mlx5_ifc_roce_cap_bits {
605 u8 reserved_at_1[0x1f];
607 u8 reserved_at_20[0x60];
609 u8 reserved_at_80[0xc];
611 u8 reserved_at_90[0x8];
612 u8 roce_version[0x8];
614 u8 reserved_at_a0[0x10];
615 u8 r_roce_dest_udp_port[0x10];
617 u8 r_roce_max_src_udp_port[0x10];
618 u8 r_roce_min_src_udp_port[0x10];
620 u8 reserved_at_e0[0x10];
621 u8 roce_address_table_size[0x10];
623 u8 reserved_at_100[0x700];
627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
650 struct mlx5_ifc_atomic_caps_bits {
651 u8 reserved_at_0[0x40];
653 u8 atomic_req_8B_endianess_mode[0x2];
654 u8 reserved_at_42[0x4];
655 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
657 u8 reserved_at_47[0x19];
659 u8 reserved_at_60[0x20];
661 u8 reserved_at_80[0x10];
662 u8 atomic_operations[0x10];
664 u8 reserved_at_a0[0x10];
665 u8 atomic_size_qp[0x10];
667 u8 reserved_at_c0[0x10];
668 u8 atomic_size_dc[0x10];
670 u8 reserved_at_e0[0x720];
673 struct mlx5_ifc_odp_cap_bits {
674 u8 reserved_at_0[0x40];
677 u8 reserved_at_41[0x1f];
679 u8 reserved_at_60[0x20];
681 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
683 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
685 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
687 u8 reserved_at_e0[0x720];
690 struct mlx5_ifc_calc_op {
691 u8 reserved_at_0[0x10];
692 u8 reserved_at_10[0x9];
693 u8 op_swap_endianness[0x1];
702 struct mlx5_ifc_vector_calc_cap_bits {
704 u8 reserved_at_1[0x1f];
705 u8 reserved_at_20[0x8];
706 u8 max_vec_count[0x8];
707 u8 reserved_at_30[0xd];
708 u8 max_chunk_size[0x3];
709 struct mlx5_ifc_calc_op calc0;
710 struct mlx5_ifc_calc_op calc1;
711 struct mlx5_ifc_calc_op calc2;
712 struct mlx5_ifc_calc_op calc3;
714 u8 reserved_at_e0[0x720];
718 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
719 MLX5_WQ_TYPE_CYCLIC = 0x1,
720 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
724 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
725 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
746 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
747 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
757 MLX5_CAP_PORT_TYPE_IB = 0x0,
758 MLX5_CAP_PORT_TYPE_ETH = 0x1,
761 struct mlx5_ifc_cmd_hca_cap_bits {
762 u8 reserved_at_0[0x80];
764 u8 log_max_srq_sz[0x8];
765 u8 log_max_qp_sz[0x8];
766 u8 reserved_at_90[0xb];
769 u8 reserved_at_a0[0xb];
771 u8 reserved_at_b0[0x10];
773 u8 reserved_at_c0[0x8];
774 u8 log_max_cq_sz[0x8];
775 u8 reserved_at_d0[0xb];
778 u8 log_max_eq_sz[0x8];
779 u8 reserved_at_e8[0x2];
780 u8 log_max_mkey[0x6];
781 u8 reserved_at_f0[0xc];
784 u8 max_indirection[0x8];
785 u8 reserved_at_108[0x1];
786 u8 log_max_mrw_sz[0x7];
787 u8 reserved_at_110[0x2];
788 u8 log_max_bsf_list_size[0x6];
789 u8 reserved_at_118[0x2];
790 u8 log_max_klm_list_size[0x6];
792 u8 reserved_at_120[0xa];
793 u8 log_max_ra_req_dc[0x6];
794 u8 reserved_at_130[0xa];
795 u8 log_max_ra_res_dc[0x6];
797 u8 reserved_at_140[0xa];
798 u8 log_max_ra_req_qp[0x6];
799 u8 reserved_at_150[0xa];
800 u8 log_max_ra_res_qp[0x6];
803 u8 cc_query_allowed[0x1];
804 u8 cc_modify_allowed[0x1];
805 u8 reserved_at_163[0xd];
806 u8 gid_table_size[0x10];
808 u8 out_of_seq_cnt[0x1];
809 u8 vport_counters[0x1];
810 u8 retransmission_q_counters[0x1];
811 u8 reserved_at_183[0x1];
812 u8 modify_rq_counter_set_id[0x1];
813 u8 reserved_at_185[0x1];
815 u8 pkey_table_size[0x10];
817 u8 vport_group_manager[0x1];
818 u8 vhca_group_manager[0x1];
821 u8 reserved_at_1a4[0x1];
823 u8 nic_flow_table[0x1];
824 u8 eswitch_flow_table[0x1];
825 u8 early_vf_enable[0x1];
826 u8 reserved_at_1a9[0x2];
827 u8 local_ca_ack_delay[0x5];
828 u8 port_module_event[0x1];
829 u8 reserved_at_1b0[0x1];
831 u8 reserved_at_1b2[0x1];
832 u8 disable_link_up[0x1];
837 u8 reserved_at_1c0[0x3];
839 u8 reserved_at_1c8[0x4];
841 u8 reserved_at_1d0[0x1];
843 u8 reserved_at_1d2[0x4];
846 u8 reserved_at_1d8[0x1];
855 u8 stat_rate_support[0x10];
856 u8 reserved_at_1f0[0xc];
859 u8 compact_address_vector[0x1];
861 u8 reserved_at_201[0x2];
862 u8 ipoib_basic_offloads[0x1];
863 u8 reserved_at_205[0xa];
864 u8 drain_sigerr[0x1];
865 u8 cmdif_checksum[0x2];
867 u8 reserved_at_213[0x1];
868 u8 wq_signature[0x1];
869 u8 sctr_data_cqe[0x1];
870 u8 reserved_at_216[0x1];
876 u8 eth_net_offloads[0x1];
879 u8 reserved_at_21f[0x1];
883 u8 cq_moderation[0x1];
884 u8 reserved_at_223[0x3];
888 u8 reserved_at_229[0x1];
889 u8 scqe_break_moderation[0x1];
890 u8 cq_period_start_from_cqe[0x1];
892 u8 reserved_at_22d[0x1];
895 u8 umr_ptr_rlky[0x1];
897 u8 reserved_at_232[0x4];
900 u8 set_deth_sqpn[0x1];
901 u8 reserved_at_239[0x3];
907 u8 reserved_at_240[0xa];
909 u8 reserved_at_250[0x8];
913 u8 driver_version[0x1];
914 u8 pad_tx_eth_packet[0x1];
915 u8 reserved_at_263[0x8];
916 u8 log_bf_reg_size[0x5];
918 u8 reserved_at_270[0xb];
920 u8 num_lag_ports[0x4];
922 u8 reserved_at_280[0x10];
923 u8 max_wqe_sz_sq[0x10];
925 u8 reserved_at_2a0[0x10];
926 u8 max_wqe_sz_rq[0x10];
928 u8 reserved_at_2c0[0x10];
929 u8 max_wqe_sz_sq_dc[0x10];
931 u8 reserved_at_2e0[0x7];
934 u8 reserved_at_300[0x18];
937 u8 reserved_at_320[0x3];
938 u8 log_max_transport_domain[0x5];
939 u8 reserved_at_328[0x3];
941 u8 reserved_at_330[0xb];
942 u8 log_max_xrcd[0x5];
944 u8 reserved_at_340[0x8];
945 u8 log_max_flow_counter_bulk[0x8];
946 u8 max_flow_counter[0x10];
949 u8 reserved_at_360[0x3];
951 u8 reserved_at_368[0x3];
953 u8 reserved_at_370[0x3];
955 u8 reserved_at_378[0x3];
958 u8 basic_cyclic_rcv_wqe[0x1];
959 u8 reserved_at_381[0x2];
961 u8 reserved_at_388[0x3];
963 u8 reserved_at_390[0x3];
964 u8 log_max_rqt_size[0x5];
965 u8 reserved_at_398[0x3];
966 u8 log_max_tis_per_sq[0x5];
968 u8 reserved_at_3a0[0x3];
969 u8 log_max_stride_sz_rq[0x5];
970 u8 reserved_at_3a8[0x3];
971 u8 log_min_stride_sz_rq[0x5];
972 u8 reserved_at_3b0[0x3];
973 u8 log_max_stride_sz_sq[0x5];
974 u8 reserved_at_3b8[0x3];
975 u8 log_min_stride_sz_sq[0x5];
977 u8 reserved_at_3c0[0x1b];
978 u8 log_max_wq_sz[0x5];
980 u8 nic_vport_change_event[0x1];
981 u8 reserved_at_3e1[0xa];
982 u8 log_max_vlan_list[0x5];
983 u8 reserved_at_3f0[0x3];
984 u8 log_max_current_mc_list[0x5];
985 u8 reserved_at_3f8[0x3];
986 u8 log_max_current_uc_list[0x5];
988 u8 reserved_at_400[0x80];
990 u8 reserved_at_480[0x3];
991 u8 log_max_l2_table[0x5];
992 u8 reserved_at_488[0x8];
993 u8 log_uar_page_sz[0x10];
995 u8 reserved_at_4a0[0x20];
996 u8 device_frequency_mhz[0x20];
997 u8 device_frequency_khz[0x20];
999 u8 reserved_at_500[0x80];
1001 u8 reserved_at_580[0x3f];
1002 u8 cqe_compression[0x1];
1004 u8 cqe_compression_timeout[0x10];
1005 u8 cqe_compression_max_num[0x10];
1007 u8 reserved_at_5e0[0x10];
1008 u8 tag_matching[0x1];
1009 u8 rndv_offload_rc[0x1];
1010 u8 rndv_offload_dc[0x1];
1011 u8 log_tag_matching_list_sz[0x5];
1012 u8 reserved_at_5e8[0x3];
1013 u8 log_max_xrq[0x5];
1015 u8 reserved_at_5f0[0x200];
1018 enum mlx5_flow_destination_type {
1019 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1020 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1021 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1023 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1026 struct mlx5_ifc_dest_format_struct_bits {
1027 u8 destination_type[0x8];
1028 u8 destination_id[0x18];
1030 u8 reserved_at_20[0x20];
1033 struct mlx5_ifc_flow_counter_list_bits {
1035 u8 num_of_counters[0xf];
1036 u8 flow_counter_id[0x10];
1038 u8 reserved_at_20[0x20];
1041 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1042 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1043 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1044 u8 reserved_at_0[0x40];
1047 struct mlx5_ifc_fte_match_param_bits {
1048 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1050 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1052 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1054 u8 reserved_at_600[0xa00];
1058 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1065 struct mlx5_ifc_rx_hash_field_select_bits {
1066 u8 l3_prot_type[0x1];
1067 u8 l4_prot_type[0x1];
1068 u8 selected_fields[0x1e];
1072 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1073 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1077 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1078 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1081 struct mlx5_ifc_wq_bits {
1083 u8 wq_signature[0x1];
1084 u8 end_padding_mode[0x2];
1086 u8 reserved_at_8[0x18];
1088 u8 hds_skip_first_sge[0x1];
1089 u8 log2_hds_buf_size[0x3];
1090 u8 reserved_at_24[0x7];
1091 u8 page_offset[0x5];
1094 u8 reserved_at_40[0x8];
1097 u8 reserved_at_60[0x8];
1102 u8 hw_counter[0x20];
1104 u8 sw_counter[0x20];
1106 u8 reserved_at_100[0xc];
1107 u8 log_wq_stride[0x4];
1108 u8 reserved_at_110[0x3];
1109 u8 log_wq_pg_sz[0x5];
1110 u8 reserved_at_118[0x3];
1113 u8 reserved_at_120[0x15];
1114 u8 log_wqe_num_of_strides[0x3];
1115 u8 two_byte_shift_en[0x1];
1116 u8 reserved_at_139[0x4];
1117 u8 log_wqe_stride_size[0x3];
1119 u8 reserved_at_140[0x4c0];
1121 struct mlx5_ifc_cmd_pas_bits pas[0];
1124 struct mlx5_ifc_rq_num_bits {
1125 u8 reserved_at_0[0x8];
1129 struct mlx5_ifc_mac_address_layout_bits {
1130 u8 reserved_at_0[0x10];
1131 u8 mac_addr_47_32[0x10];
1133 u8 mac_addr_31_0[0x20];
1136 struct mlx5_ifc_vlan_layout_bits {
1137 u8 reserved_at_0[0x14];
1140 u8 reserved_at_20[0x20];
1143 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1144 u8 reserved_at_0[0xa0];
1146 u8 min_time_between_cnps[0x20];
1148 u8 reserved_at_c0[0x12];
1150 u8 reserved_at_d8[0x5];
1151 u8 cnp_802p_prio[0x3];
1153 u8 reserved_at_e0[0x720];
1156 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1157 u8 reserved_at_0[0x60];
1159 u8 reserved_at_60[0x4];
1160 u8 clamp_tgt_rate[0x1];
1161 u8 reserved_at_65[0x3];
1162 u8 clamp_tgt_rate_after_time_inc[0x1];
1163 u8 reserved_at_69[0x17];
1165 u8 reserved_at_80[0x20];
1167 u8 rpg_time_reset[0x20];
1169 u8 rpg_byte_reset[0x20];
1171 u8 rpg_threshold[0x20];
1173 u8 rpg_max_rate[0x20];
1175 u8 rpg_ai_rate[0x20];
1177 u8 rpg_hai_rate[0x20];
1181 u8 rpg_min_dec_fac[0x20];
1183 u8 rpg_min_rate[0x20];
1185 u8 reserved_at_1c0[0xe0];
1187 u8 rate_to_set_on_first_cnp[0x20];
1191 u8 dce_tcp_rtt[0x20];
1193 u8 rate_reduce_monitor_period[0x20];
1195 u8 reserved_at_320[0x20];
1197 u8 initial_alpha_value[0x20];
1199 u8 reserved_at_360[0x4a0];
1202 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1203 u8 reserved_at_0[0x80];
1205 u8 rppp_max_rps[0x20];
1207 u8 rpg_time_reset[0x20];
1209 u8 rpg_byte_reset[0x20];
1211 u8 rpg_threshold[0x20];
1213 u8 rpg_max_rate[0x20];
1215 u8 rpg_ai_rate[0x20];
1217 u8 rpg_hai_rate[0x20];
1221 u8 rpg_min_dec_fac[0x20];
1223 u8 rpg_min_rate[0x20];
1225 u8 reserved_at_1c0[0x640];
1229 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1230 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1231 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1234 struct mlx5_ifc_resize_field_select_bits {
1235 u8 resize_field_select[0x20];
1239 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1241 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1242 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1245 struct mlx5_ifc_modify_field_select_bits {
1246 u8 modify_field_select[0x20];
1249 struct mlx5_ifc_field_select_r_roce_np_bits {
1250 u8 field_select_r_roce_np[0x20];
1253 struct mlx5_ifc_field_select_r_roce_rp_bits {
1254 u8 field_select_r_roce_rp[0x20];
1258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1270 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1271 u8 field_select_8021qaurp[0x20];
1274 struct mlx5_ifc_phys_layer_cntrs_bits {
1275 u8 time_since_last_clear_high[0x20];
1277 u8 time_since_last_clear_low[0x20];
1279 u8 symbol_errors_high[0x20];
1281 u8 symbol_errors_low[0x20];
1283 u8 sync_headers_errors_high[0x20];
1285 u8 sync_headers_errors_low[0x20];
1287 u8 edpl_bip_errors_lane0_high[0x20];
1289 u8 edpl_bip_errors_lane0_low[0x20];
1291 u8 edpl_bip_errors_lane1_high[0x20];
1293 u8 edpl_bip_errors_lane1_low[0x20];
1295 u8 edpl_bip_errors_lane2_high[0x20];
1297 u8 edpl_bip_errors_lane2_low[0x20];
1299 u8 edpl_bip_errors_lane3_high[0x20];
1301 u8 edpl_bip_errors_lane3_low[0x20];
1303 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1305 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1307 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1309 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1311 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1313 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1315 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1317 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1319 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1321 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1323 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1325 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1327 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1329 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1331 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1333 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1335 u8 rs_fec_corrected_blocks_high[0x20];
1337 u8 rs_fec_corrected_blocks_low[0x20];
1339 u8 rs_fec_uncorrectable_blocks_high[0x20];
1341 u8 rs_fec_uncorrectable_blocks_low[0x20];
1343 u8 rs_fec_no_errors_blocks_high[0x20];
1345 u8 rs_fec_no_errors_blocks_low[0x20];
1347 u8 rs_fec_single_error_blocks_high[0x20];
1349 u8 rs_fec_single_error_blocks_low[0x20];
1351 u8 rs_fec_corrected_symbols_total_high[0x20];
1353 u8 rs_fec_corrected_symbols_total_low[0x20];
1355 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1357 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1359 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1361 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1363 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1365 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1367 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1369 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1371 u8 link_down_events[0x20];
1373 u8 successful_recovery_events[0x20];
1375 u8 reserved_at_640[0x180];
1378 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1379 u8 symbol_error_counter[0x10];
1381 u8 link_error_recovery_counter[0x8];
1383 u8 link_downed_counter[0x8];
1385 u8 port_rcv_errors[0x10];
1387 u8 port_rcv_remote_physical_errors[0x10];
1389 u8 port_rcv_switch_relay_errors[0x10];
1391 u8 port_xmit_discards[0x10];
1393 u8 port_xmit_constraint_errors[0x8];
1395 u8 port_rcv_constraint_errors[0x8];
1397 u8 reserved_at_70[0x8];
1399 u8 link_overrun_errors[0x8];
1401 u8 reserved_at_80[0x10];
1403 u8 vl_15_dropped[0x10];
1405 u8 reserved_at_a0[0xa0];
1408 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1409 u8 transmit_queue_high[0x20];
1411 u8 transmit_queue_low[0x20];
1413 u8 reserved_at_40[0x780];
1416 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1417 u8 rx_octets_high[0x20];
1419 u8 rx_octets_low[0x20];
1421 u8 reserved_at_40[0xc0];
1423 u8 rx_frames_high[0x20];
1425 u8 rx_frames_low[0x20];
1427 u8 tx_octets_high[0x20];
1429 u8 tx_octets_low[0x20];
1431 u8 reserved_at_180[0xc0];
1433 u8 tx_frames_high[0x20];
1435 u8 tx_frames_low[0x20];
1437 u8 rx_pause_high[0x20];
1439 u8 rx_pause_low[0x20];
1441 u8 rx_pause_duration_high[0x20];
1443 u8 rx_pause_duration_low[0x20];
1445 u8 tx_pause_high[0x20];
1447 u8 tx_pause_low[0x20];
1449 u8 tx_pause_duration_high[0x20];
1451 u8 tx_pause_duration_low[0x20];
1453 u8 rx_pause_transition_high[0x20];
1455 u8 rx_pause_transition_low[0x20];
1457 u8 reserved_at_3c0[0x400];
1460 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1461 u8 port_transmit_wait_high[0x20];
1463 u8 port_transmit_wait_low[0x20];
1465 u8 reserved_at_40[0x780];
1468 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1469 u8 dot3stats_alignment_errors_high[0x20];
1471 u8 dot3stats_alignment_errors_low[0x20];
1473 u8 dot3stats_fcs_errors_high[0x20];
1475 u8 dot3stats_fcs_errors_low[0x20];
1477 u8 dot3stats_single_collision_frames_high[0x20];
1479 u8 dot3stats_single_collision_frames_low[0x20];
1481 u8 dot3stats_multiple_collision_frames_high[0x20];
1483 u8 dot3stats_multiple_collision_frames_low[0x20];
1485 u8 dot3stats_sqe_test_errors_high[0x20];
1487 u8 dot3stats_sqe_test_errors_low[0x20];
1489 u8 dot3stats_deferred_transmissions_high[0x20];
1491 u8 dot3stats_deferred_transmissions_low[0x20];
1493 u8 dot3stats_late_collisions_high[0x20];
1495 u8 dot3stats_late_collisions_low[0x20];
1497 u8 dot3stats_excessive_collisions_high[0x20];
1499 u8 dot3stats_excessive_collisions_low[0x20];
1501 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1503 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1505 u8 dot3stats_carrier_sense_errors_high[0x20];
1507 u8 dot3stats_carrier_sense_errors_low[0x20];
1509 u8 dot3stats_frame_too_longs_high[0x20];
1511 u8 dot3stats_frame_too_longs_low[0x20];
1513 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1515 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1517 u8 dot3stats_symbol_errors_high[0x20];
1519 u8 dot3stats_symbol_errors_low[0x20];
1521 u8 dot3control_in_unknown_opcodes_high[0x20];
1523 u8 dot3control_in_unknown_opcodes_low[0x20];
1525 u8 dot3in_pause_frames_high[0x20];
1527 u8 dot3in_pause_frames_low[0x20];
1529 u8 dot3out_pause_frames_high[0x20];
1531 u8 dot3out_pause_frames_low[0x20];
1533 u8 reserved_at_400[0x3c0];
1536 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1537 u8 ether_stats_drop_events_high[0x20];
1539 u8 ether_stats_drop_events_low[0x20];
1541 u8 ether_stats_octets_high[0x20];
1543 u8 ether_stats_octets_low[0x20];
1545 u8 ether_stats_pkts_high[0x20];
1547 u8 ether_stats_pkts_low[0x20];
1549 u8 ether_stats_broadcast_pkts_high[0x20];
1551 u8 ether_stats_broadcast_pkts_low[0x20];
1553 u8 ether_stats_multicast_pkts_high[0x20];
1555 u8 ether_stats_multicast_pkts_low[0x20];
1557 u8 ether_stats_crc_align_errors_high[0x20];
1559 u8 ether_stats_crc_align_errors_low[0x20];
1561 u8 ether_stats_undersize_pkts_high[0x20];
1563 u8 ether_stats_undersize_pkts_low[0x20];
1565 u8 ether_stats_oversize_pkts_high[0x20];
1567 u8 ether_stats_oversize_pkts_low[0x20];
1569 u8 ether_stats_fragments_high[0x20];
1571 u8 ether_stats_fragments_low[0x20];
1573 u8 ether_stats_jabbers_high[0x20];
1575 u8 ether_stats_jabbers_low[0x20];
1577 u8 ether_stats_collisions_high[0x20];
1579 u8 ether_stats_collisions_low[0x20];
1581 u8 ether_stats_pkts64octets_high[0x20];
1583 u8 ether_stats_pkts64octets_low[0x20];
1585 u8 ether_stats_pkts65to127octets_high[0x20];
1587 u8 ether_stats_pkts65to127octets_low[0x20];
1589 u8 ether_stats_pkts128to255octets_high[0x20];
1591 u8 ether_stats_pkts128to255octets_low[0x20];
1593 u8 ether_stats_pkts256to511octets_high[0x20];
1595 u8 ether_stats_pkts256to511octets_low[0x20];
1597 u8 ether_stats_pkts512to1023octets_high[0x20];
1599 u8 ether_stats_pkts512to1023octets_low[0x20];
1601 u8 ether_stats_pkts1024to1518octets_high[0x20];
1603 u8 ether_stats_pkts1024to1518octets_low[0x20];
1605 u8 ether_stats_pkts1519to2047octets_high[0x20];
1607 u8 ether_stats_pkts1519to2047octets_low[0x20];
1609 u8 ether_stats_pkts2048to4095octets_high[0x20];
1611 u8 ether_stats_pkts2048to4095octets_low[0x20];
1613 u8 ether_stats_pkts4096to8191octets_high[0x20];
1615 u8 ether_stats_pkts4096to8191octets_low[0x20];
1617 u8 ether_stats_pkts8192to10239octets_high[0x20];
1619 u8 ether_stats_pkts8192to10239octets_low[0x20];
1621 u8 reserved_at_540[0x280];
1624 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1625 u8 if_in_octets_high[0x20];
1627 u8 if_in_octets_low[0x20];
1629 u8 if_in_ucast_pkts_high[0x20];
1631 u8 if_in_ucast_pkts_low[0x20];
1633 u8 if_in_discards_high[0x20];
1635 u8 if_in_discards_low[0x20];
1637 u8 if_in_errors_high[0x20];
1639 u8 if_in_errors_low[0x20];
1641 u8 if_in_unknown_protos_high[0x20];
1643 u8 if_in_unknown_protos_low[0x20];
1645 u8 if_out_octets_high[0x20];
1647 u8 if_out_octets_low[0x20];
1649 u8 if_out_ucast_pkts_high[0x20];
1651 u8 if_out_ucast_pkts_low[0x20];
1653 u8 if_out_discards_high[0x20];
1655 u8 if_out_discards_low[0x20];
1657 u8 if_out_errors_high[0x20];
1659 u8 if_out_errors_low[0x20];
1661 u8 if_in_multicast_pkts_high[0x20];
1663 u8 if_in_multicast_pkts_low[0x20];
1665 u8 if_in_broadcast_pkts_high[0x20];
1667 u8 if_in_broadcast_pkts_low[0x20];
1669 u8 if_out_multicast_pkts_high[0x20];
1671 u8 if_out_multicast_pkts_low[0x20];
1673 u8 if_out_broadcast_pkts_high[0x20];
1675 u8 if_out_broadcast_pkts_low[0x20];
1677 u8 reserved_at_340[0x480];
1680 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1681 u8 a_frames_transmitted_ok_high[0x20];
1683 u8 a_frames_transmitted_ok_low[0x20];
1685 u8 a_frames_received_ok_high[0x20];
1687 u8 a_frames_received_ok_low[0x20];
1689 u8 a_frame_check_sequence_errors_high[0x20];
1691 u8 a_frame_check_sequence_errors_low[0x20];
1693 u8 a_alignment_errors_high[0x20];
1695 u8 a_alignment_errors_low[0x20];
1697 u8 a_octets_transmitted_ok_high[0x20];
1699 u8 a_octets_transmitted_ok_low[0x20];
1701 u8 a_octets_received_ok_high[0x20];
1703 u8 a_octets_received_ok_low[0x20];
1705 u8 a_multicast_frames_xmitted_ok_high[0x20];
1707 u8 a_multicast_frames_xmitted_ok_low[0x20];
1709 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1711 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1713 u8 a_multicast_frames_received_ok_high[0x20];
1715 u8 a_multicast_frames_received_ok_low[0x20];
1717 u8 a_broadcast_frames_received_ok_high[0x20];
1719 u8 a_broadcast_frames_received_ok_low[0x20];
1721 u8 a_in_range_length_errors_high[0x20];
1723 u8 a_in_range_length_errors_low[0x20];
1725 u8 a_out_of_range_length_field_high[0x20];
1727 u8 a_out_of_range_length_field_low[0x20];
1729 u8 a_frame_too_long_errors_high[0x20];
1731 u8 a_frame_too_long_errors_low[0x20];
1733 u8 a_symbol_error_during_carrier_high[0x20];
1735 u8 a_symbol_error_during_carrier_low[0x20];
1737 u8 a_mac_control_frames_transmitted_high[0x20];
1739 u8 a_mac_control_frames_transmitted_low[0x20];
1741 u8 a_mac_control_frames_received_high[0x20];
1743 u8 a_mac_control_frames_received_low[0x20];
1745 u8 a_unsupported_opcodes_received_high[0x20];
1747 u8 a_unsupported_opcodes_received_low[0x20];
1749 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1751 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1753 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1755 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1757 u8 reserved_at_4c0[0x300];
1760 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1761 u8 life_time_counter_high[0x20];
1763 u8 life_time_counter_low[0x20];
1769 u8 l0_to_recovery_eieos[0x20];
1771 u8 l0_to_recovery_ts[0x20];
1773 u8 l0_to_recovery_framing[0x20];
1775 u8 l0_to_recovery_retrain[0x20];
1777 u8 crc_error_dllp[0x20];
1779 u8 crc_error_tlp[0x20];
1781 u8 reserved_at_140[0x680];
1784 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
1785 u8 life_time_counter_high[0x20];
1787 u8 life_time_counter_low[0x20];
1789 u8 time_to_boot_image_start[0x20];
1791 u8 time_to_link_image[0x20];
1793 u8 calibration_time[0x20];
1795 u8 time_to_first_perst[0x20];
1797 u8 time_to_detect_state[0x20];
1799 u8 time_to_l0[0x20];
1801 u8 time_to_crs_en[0x20];
1803 u8 time_to_plastic_image_start[0x20];
1805 u8 time_to_iron_image_start[0x20];
1807 u8 perst_handler[0x20];
1809 u8 times_in_l1[0x20];
1811 u8 times_in_l23[0x20];
1815 u8 config_cycle1usec[0x20];
1817 u8 config_cycle2to7usec[0x20];
1819 u8 config_cycle_8to15usec[0x20];
1821 u8 config_cycle_16_to_63usec[0x20];
1823 u8 config_cycle_64usec[0x20];
1825 u8 correctable_err_msg_sent[0x20];
1827 u8 non_fatal_err_msg_sent[0x20];
1829 u8 fatal_err_msg_sent[0x20];
1831 u8 reserved_at_2e0[0x4e0];
1834 struct mlx5_ifc_cmd_inter_comp_event_bits {
1835 u8 command_completion_vector[0x20];
1837 u8 reserved_at_20[0xc0];
1840 struct mlx5_ifc_stall_vl_event_bits {
1841 u8 reserved_at_0[0x18];
1843 u8 reserved_at_19[0x3];
1846 u8 reserved_at_20[0xa0];
1849 struct mlx5_ifc_db_bf_congestion_event_bits {
1850 u8 event_subtype[0x8];
1851 u8 reserved_at_8[0x8];
1852 u8 congestion_level[0x8];
1853 u8 reserved_at_18[0x8];
1855 u8 reserved_at_20[0xa0];
1858 struct mlx5_ifc_gpio_event_bits {
1859 u8 reserved_at_0[0x60];
1861 u8 gpio_event_hi[0x20];
1863 u8 gpio_event_lo[0x20];
1865 u8 reserved_at_a0[0x40];
1868 struct mlx5_ifc_port_state_change_event_bits {
1869 u8 reserved_at_0[0x40];
1872 u8 reserved_at_44[0x1c];
1874 u8 reserved_at_60[0x80];
1877 struct mlx5_ifc_dropped_packet_logged_bits {
1878 u8 reserved_at_0[0xe0];
1882 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1883 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1886 struct mlx5_ifc_cq_error_bits {
1887 u8 reserved_at_0[0x8];
1890 u8 reserved_at_20[0x20];
1892 u8 reserved_at_40[0x18];
1895 u8 reserved_at_60[0x80];
1898 struct mlx5_ifc_rdma_page_fault_event_bits {
1899 u8 bytes_committed[0x20];
1903 u8 reserved_at_40[0x10];
1904 u8 packet_len[0x10];
1906 u8 rdma_op_len[0x20];
1910 u8 reserved_at_c0[0x5];
1917 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1918 u8 bytes_committed[0x20];
1920 u8 reserved_at_20[0x10];
1923 u8 reserved_at_40[0x10];
1926 u8 reserved_at_60[0x60];
1928 u8 reserved_at_c0[0x5];
1935 struct mlx5_ifc_qp_events_bits {
1936 u8 reserved_at_0[0xa0];
1939 u8 reserved_at_a8[0x18];
1941 u8 reserved_at_c0[0x8];
1942 u8 qpn_rqn_sqn[0x18];
1945 struct mlx5_ifc_dct_events_bits {
1946 u8 reserved_at_0[0xc0];
1948 u8 reserved_at_c0[0x8];
1949 u8 dct_number[0x18];
1952 struct mlx5_ifc_comp_event_bits {
1953 u8 reserved_at_0[0xc0];
1955 u8 reserved_at_c0[0x8];
1960 MLX5_QPC_STATE_RST = 0x0,
1961 MLX5_QPC_STATE_INIT = 0x1,
1962 MLX5_QPC_STATE_RTR = 0x2,
1963 MLX5_QPC_STATE_RTS = 0x3,
1964 MLX5_QPC_STATE_SQER = 0x4,
1965 MLX5_QPC_STATE_ERR = 0x6,
1966 MLX5_QPC_STATE_SQD = 0x7,
1967 MLX5_QPC_STATE_SUSPENDED = 0x9,
1971 MLX5_QPC_ST_RC = 0x0,
1972 MLX5_QPC_ST_UC = 0x1,
1973 MLX5_QPC_ST_UD = 0x2,
1974 MLX5_QPC_ST_XRC = 0x3,
1975 MLX5_QPC_ST_DCI = 0x5,
1976 MLX5_QPC_ST_QP0 = 0x7,
1977 MLX5_QPC_ST_QP1 = 0x8,
1978 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1979 MLX5_QPC_ST_REG_UMR = 0xc,
1983 MLX5_QPC_PM_STATE_ARMED = 0x0,
1984 MLX5_QPC_PM_STATE_REARM = 0x1,
1985 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1986 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1990 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1991 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1995 MLX5_QPC_MTU_256_BYTES = 0x1,
1996 MLX5_QPC_MTU_512_BYTES = 0x2,
1997 MLX5_QPC_MTU_1K_BYTES = 0x3,
1998 MLX5_QPC_MTU_2K_BYTES = 0x4,
1999 MLX5_QPC_MTU_4K_BYTES = 0x5,
2000 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2004 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2005 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2006 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2007 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2008 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2009 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2010 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2011 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2015 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2016 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2017 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2021 MLX5_QPC_CS_RES_DISABLE = 0x0,
2022 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2023 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2026 struct mlx5_ifc_qpc_bits {
2028 u8 lag_tx_port_affinity[0x4];
2030 u8 reserved_at_10[0x3];
2032 u8 reserved_at_15[0x7];
2033 u8 end_padding_mode[0x2];
2034 u8 reserved_at_1e[0x2];
2036 u8 wq_signature[0x1];
2037 u8 block_lb_mc[0x1];
2038 u8 atomic_like_write_en[0x1];
2039 u8 latency_sensitive[0x1];
2040 u8 reserved_at_24[0x1];
2041 u8 drain_sigerr[0x1];
2042 u8 reserved_at_26[0x2];
2046 u8 log_msg_max[0x5];
2047 u8 reserved_at_48[0x1];
2048 u8 log_rq_size[0x4];
2049 u8 log_rq_stride[0x3];
2051 u8 log_sq_size[0x4];
2052 u8 reserved_at_55[0x6];
2054 u8 ulp_stateless_offload_mode[0x4];
2056 u8 counter_set_id[0x8];
2059 u8 reserved_at_80[0x8];
2060 u8 user_index[0x18];
2062 u8 reserved_at_a0[0x3];
2063 u8 log_page_size[0x5];
2064 u8 remote_qpn[0x18];
2066 struct mlx5_ifc_ads_bits primary_address_path;
2068 struct mlx5_ifc_ads_bits secondary_address_path;
2070 u8 log_ack_req_freq[0x4];
2071 u8 reserved_at_384[0x4];
2072 u8 log_sra_max[0x3];
2073 u8 reserved_at_38b[0x2];
2074 u8 retry_count[0x3];
2076 u8 reserved_at_393[0x1];
2078 u8 cur_rnr_retry[0x3];
2079 u8 cur_retry_count[0x3];
2080 u8 reserved_at_39b[0x5];
2082 u8 reserved_at_3a0[0x20];
2084 u8 reserved_at_3c0[0x8];
2085 u8 next_send_psn[0x18];
2087 u8 reserved_at_3e0[0x8];
2090 u8 reserved_at_400[0x8];
2093 u8 reserved_at_420[0x20];
2095 u8 reserved_at_440[0x8];
2096 u8 last_acked_psn[0x18];
2098 u8 reserved_at_460[0x8];
2101 u8 reserved_at_480[0x8];
2102 u8 log_rra_max[0x3];
2103 u8 reserved_at_48b[0x1];
2104 u8 atomic_mode[0x4];
2108 u8 reserved_at_493[0x1];
2109 u8 page_offset[0x6];
2110 u8 reserved_at_49a[0x3];
2111 u8 cd_slave_receive[0x1];
2112 u8 cd_slave_send[0x1];
2115 u8 reserved_at_4a0[0x3];
2116 u8 min_rnr_nak[0x5];
2117 u8 next_rcv_psn[0x18];
2119 u8 reserved_at_4c0[0x8];
2122 u8 reserved_at_4e0[0x8];
2129 u8 reserved_at_560[0x5];
2131 u8 srqn_rmpn_xrqn[0x18];
2133 u8 reserved_at_580[0x8];
2136 u8 hw_sq_wqebb_counter[0x10];
2137 u8 sw_sq_wqebb_counter[0x10];
2139 u8 hw_rq_counter[0x20];
2141 u8 sw_rq_counter[0x20];
2143 u8 reserved_at_600[0x20];
2145 u8 reserved_at_620[0xf];
2150 u8 dc_access_key[0x40];
2152 u8 reserved_at_680[0xc0];
2155 struct mlx5_ifc_roce_addr_layout_bits {
2156 u8 source_l3_address[16][0x8];
2158 u8 reserved_at_80[0x3];
2161 u8 source_mac_47_32[0x10];
2163 u8 source_mac_31_0[0x20];
2165 u8 reserved_at_c0[0x14];
2166 u8 roce_l3_type[0x4];
2167 u8 roce_version[0x8];
2169 u8 reserved_at_e0[0x20];
2172 union mlx5_ifc_hca_cap_union_bits {
2173 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2174 struct mlx5_ifc_odp_cap_bits odp_cap;
2175 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2176 struct mlx5_ifc_roce_cap_bits roce_cap;
2177 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2178 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2179 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2180 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2181 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2182 struct mlx5_ifc_qos_cap_bits qos_cap;
2183 u8 reserved_at_0[0x8000];
2187 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2188 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2189 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2190 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2191 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2192 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2195 struct mlx5_ifc_flow_context_bits {
2196 u8 reserved_at_0[0x20];
2200 u8 reserved_at_40[0x8];
2203 u8 reserved_at_60[0x10];
2206 u8 reserved_at_80[0x8];
2207 u8 destination_list_size[0x18];
2209 u8 reserved_at_a0[0x8];
2210 u8 flow_counter_list_size[0x18];
2214 u8 reserved_at_e0[0x120];
2216 struct mlx5_ifc_fte_match_param_bits match_value;
2218 u8 reserved_at_1200[0x600];
2220 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2224 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2225 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2228 struct mlx5_ifc_xrc_srqc_bits {
2230 u8 log_xrc_srq_size[0x4];
2231 u8 reserved_at_8[0x18];
2233 u8 wq_signature[0x1];
2235 u8 reserved_at_22[0x1];
2237 u8 basic_cyclic_rcv_wqe[0x1];
2238 u8 log_rq_stride[0x3];
2241 u8 page_offset[0x6];
2242 u8 reserved_at_46[0x2];
2245 u8 reserved_at_60[0x20];
2247 u8 user_index_equal_xrc_srqn[0x1];
2248 u8 reserved_at_81[0x1];
2249 u8 log_page_size[0x6];
2250 u8 user_index[0x18];
2252 u8 reserved_at_a0[0x20];
2254 u8 reserved_at_c0[0x8];
2260 u8 reserved_at_100[0x40];
2262 u8 db_record_addr_h[0x20];
2264 u8 db_record_addr_l[0x1e];
2265 u8 reserved_at_17e[0x2];
2267 u8 reserved_at_180[0x80];
2270 struct mlx5_ifc_traffic_counter_bits {
2276 struct mlx5_ifc_tisc_bits {
2277 u8 strict_lag_tx_port_affinity[0x1];
2278 u8 reserved_at_1[0x3];
2279 u8 lag_tx_port_affinity[0x04];
2281 u8 reserved_at_8[0x4];
2283 u8 reserved_at_10[0x10];
2285 u8 reserved_at_20[0x100];
2287 u8 reserved_at_120[0x8];
2288 u8 transport_domain[0x18];
2290 u8 reserved_at_140[0x3c0];
2294 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2295 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2299 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2300 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2304 MLX5_RX_HASH_FN_NONE = 0x0,
2305 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2306 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2310 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2311 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2314 struct mlx5_ifc_tirc_bits {
2315 u8 reserved_at_0[0x20];
2318 u8 reserved_at_24[0x1c];
2320 u8 reserved_at_40[0x40];
2322 u8 reserved_at_80[0x4];
2323 u8 lro_timeout_period_usecs[0x10];
2324 u8 lro_enable_mask[0x4];
2325 u8 lro_max_ip_payload_size[0x8];
2327 u8 reserved_at_a0[0x40];
2329 u8 reserved_at_e0[0x8];
2330 u8 inline_rqn[0x18];
2332 u8 rx_hash_symmetric[0x1];
2333 u8 reserved_at_101[0x1];
2334 u8 tunneled_offload_en[0x1];
2335 u8 reserved_at_103[0x5];
2336 u8 indirect_table[0x18];
2339 u8 reserved_at_124[0x2];
2340 u8 self_lb_block[0x2];
2341 u8 transport_domain[0x18];
2343 u8 rx_hash_toeplitz_key[10][0x20];
2345 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2347 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2349 u8 reserved_at_2c0[0x4c0];
2353 MLX5_SRQC_STATE_GOOD = 0x0,
2354 MLX5_SRQC_STATE_ERROR = 0x1,
2357 struct mlx5_ifc_srqc_bits {
2359 u8 log_srq_size[0x4];
2360 u8 reserved_at_8[0x18];
2362 u8 wq_signature[0x1];
2364 u8 reserved_at_22[0x1];
2366 u8 reserved_at_24[0x1];
2367 u8 log_rq_stride[0x3];
2370 u8 page_offset[0x6];
2371 u8 reserved_at_46[0x2];
2374 u8 reserved_at_60[0x20];
2376 u8 reserved_at_80[0x2];
2377 u8 log_page_size[0x6];
2378 u8 reserved_at_88[0x18];
2380 u8 reserved_at_a0[0x20];
2382 u8 reserved_at_c0[0x8];
2388 u8 reserved_at_100[0x40];
2392 u8 reserved_at_180[0x80];
2396 MLX5_SQC_STATE_RST = 0x0,
2397 MLX5_SQC_STATE_RDY = 0x1,
2398 MLX5_SQC_STATE_ERR = 0x3,
2401 struct mlx5_ifc_sqc_bits {
2405 u8 flush_in_error_en[0x1];
2406 u8 reserved_at_4[0x1];
2407 u8 min_wqe_inline_mode[0x3];
2410 u8 reserved_at_d[0x13];
2412 u8 reserved_at_20[0x8];
2413 u8 user_index[0x18];
2415 u8 reserved_at_40[0x8];
2418 u8 reserved_at_60[0x90];
2420 u8 packet_pacing_rate_limit_index[0x10];
2421 u8 tis_lst_sz[0x10];
2422 u8 reserved_at_110[0x10];
2424 u8 reserved_at_120[0x40];
2426 u8 reserved_at_160[0x8];
2429 struct mlx5_ifc_wq_bits wq;
2433 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2434 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2435 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2436 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2439 struct mlx5_ifc_scheduling_context_bits {
2440 u8 element_type[0x8];
2441 u8 reserved_at_8[0x18];
2443 u8 element_attributes[0x20];
2445 u8 parent_element_id[0x20];
2447 u8 reserved_at_60[0x40];
2451 u8 max_average_bw[0x20];
2453 u8 reserved_at_e0[0x120];
2456 struct mlx5_ifc_rqtc_bits {
2457 u8 reserved_at_0[0xa0];
2459 u8 reserved_at_a0[0x10];
2460 u8 rqt_max_size[0x10];
2462 u8 reserved_at_c0[0x10];
2463 u8 rqt_actual_size[0x10];
2465 u8 reserved_at_e0[0x6a0];
2467 struct mlx5_ifc_rq_num_bits rq_num[0];
2471 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2472 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2476 MLX5_RQC_STATE_RST = 0x0,
2477 MLX5_RQC_STATE_RDY = 0x1,
2478 MLX5_RQC_STATE_ERR = 0x3,
2481 struct mlx5_ifc_rqc_bits {
2483 u8 reserved_at_1[0x1];
2484 u8 scatter_fcs[0x1];
2486 u8 mem_rq_type[0x4];
2488 u8 reserved_at_c[0x1];
2489 u8 flush_in_error_en[0x1];
2490 u8 reserved_at_e[0x12];
2492 u8 reserved_at_20[0x8];
2493 u8 user_index[0x18];
2495 u8 reserved_at_40[0x8];
2498 u8 counter_set_id[0x8];
2499 u8 reserved_at_68[0x18];
2501 u8 reserved_at_80[0x8];
2504 u8 reserved_at_a0[0xe0];
2506 struct mlx5_ifc_wq_bits wq;
2510 MLX5_RMPC_STATE_RDY = 0x1,
2511 MLX5_RMPC_STATE_ERR = 0x3,
2514 struct mlx5_ifc_rmpc_bits {
2515 u8 reserved_at_0[0x8];
2517 u8 reserved_at_c[0x14];
2519 u8 basic_cyclic_rcv_wqe[0x1];
2520 u8 reserved_at_21[0x1f];
2522 u8 reserved_at_40[0x140];
2524 struct mlx5_ifc_wq_bits wq;
2527 struct mlx5_ifc_nic_vport_context_bits {
2528 u8 reserved_at_0[0x5];
2529 u8 min_wqe_inline_mode[0x3];
2530 u8 reserved_at_8[0x17];
2533 u8 arm_change_event[0x1];
2534 u8 reserved_at_21[0x1a];
2535 u8 event_on_mtu[0x1];
2536 u8 event_on_promisc_change[0x1];
2537 u8 event_on_vlan_change[0x1];
2538 u8 event_on_mc_address_change[0x1];
2539 u8 event_on_uc_address_change[0x1];
2541 u8 reserved_at_40[0xf0];
2545 u8 system_image_guid[0x40];
2549 u8 reserved_at_200[0x140];
2550 u8 qkey_violation_counter[0x10];
2551 u8 reserved_at_350[0x430];
2555 u8 promisc_all[0x1];
2556 u8 reserved_at_783[0x2];
2557 u8 allowed_list_type[0x3];
2558 u8 reserved_at_788[0xc];
2559 u8 allowed_list_size[0xc];
2561 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2563 u8 reserved_at_7e0[0x20];
2565 u8 current_uc_mac_address[0][0x40];
2569 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2570 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2571 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2574 struct mlx5_ifc_mkc_bits {
2575 u8 reserved_at_0[0x1];
2577 u8 reserved_at_2[0xd];
2578 u8 small_fence_on_rdma_read_response[0x1];
2585 u8 access_mode[0x2];
2586 u8 reserved_at_18[0x8];
2591 u8 reserved_at_40[0x20];
2596 u8 reserved_at_63[0x2];
2597 u8 expected_sigerr_count[0x1];
2598 u8 reserved_at_66[0x1];
2602 u8 start_addr[0x40];
2606 u8 bsf_octword_size[0x20];
2608 u8 reserved_at_120[0x80];
2610 u8 translations_octword_size[0x20];
2612 u8 reserved_at_1c0[0x1b];
2613 u8 log_page_size[0x5];
2615 u8 reserved_at_1e0[0x20];
2618 struct mlx5_ifc_pkey_bits {
2619 u8 reserved_at_0[0x10];
2623 struct mlx5_ifc_array128_auto_bits {
2624 u8 array128_auto[16][0x8];
2627 struct mlx5_ifc_hca_vport_context_bits {
2628 u8 field_select[0x20];
2630 u8 reserved_at_20[0xe0];
2632 u8 sm_virt_aware[0x1];
2635 u8 grh_required[0x1];
2636 u8 reserved_at_104[0xc];
2637 u8 port_physical_state[0x4];
2638 u8 vport_state_policy[0x4];
2640 u8 vport_state[0x4];
2642 u8 reserved_at_120[0x20];
2644 u8 system_image_guid[0x40];
2652 u8 cap_mask1_field_select[0x20];
2656 u8 cap_mask2_field_select[0x20];
2658 u8 reserved_at_280[0x80];
2661 u8 reserved_at_310[0x4];
2662 u8 init_type_reply[0x4];
2664 u8 subnet_timeout[0x5];
2668 u8 reserved_at_334[0xc];
2670 u8 qkey_violation_counter[0x10];
2671 u8 pkey_violation_counter[0x10];
2673 u8 reserved_at_360[0xca0];
2676 struct mlx5_ifc_esw_vport_context_bits {
2677 u8 reserved_at_0[0x3];
2678 u8 vport_svlan_strip[0x1];
2679 u8 vport_cvlan_strip[0x1];
2680 u8 vport_svlan_insert[0x1];
2681 u8 vport_cvlan_insert[0x2];
2682 u8 reserved_at_8[0x18];
2684 u8 reserved_at_20[0x20];
2693 u8 reserved_at_60[0x7a0];
2697 MLX5_EQC_STATUS_OK = 0x0,
2698 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2702 MLX5_EQC_ST_ARMED = 0x9,
2703 MLX5_EQC_ST_FIRED = 0xa,
2706 struct mlx5_ifc_eqc_bits {
2708 u8 reserved_at_4[0x9];
2711 u8 reserved_at_f[0x5];
2713 u8 reserved_at_18[0x8];
2715 u8 reserved_at_20[0x20];
2717 u8 reserved_at_40[0x14];
2718 u8 page_offset[0x6];
2719 u8 reserved_at_5a[0x6];
2721 u8 reserved_at_60[0x3];
2722 u8 log_eq_size[0x5];
2725 u8 reserved_at_80[0x20];
2727 u8 reserved_at_a0[0x18];
2730 u8 reserved_at_c0[0x3];
2731 u8 log_page_size[0x5];
2732 u8 reserved_at_c8[0x18];
2734 u8 reserved_at_e0[0x60];
2736 u8 reserved_at_140[0x8];
2737 u8 consumer_counter[0x18];
2739 u8 reserved_at_160[0x8];
2740 u8 producer_counter[0x18];
2742 u8 reserved_at_180[0x80];
2746 MLX5_DCTC_STATE_ACTIVE = 0x0,
2747 MLX5_DCTC_STATE_DRAINING = 0x1,
2748 MLX5_DCTC_STATE_DRAINED = 0x2,
2752 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2753 MLX5_DCTC_CS_RES_NA = 0x1,
2754 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2758 MLX5_DCTC_MTU_256_BYTES = 0x1,
2759 MLX5_DCTC_MTU_512_BYTES = 0x2,
2760 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2761 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2762 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2765 struct mlx5_ifc_dctc_bits {
2766 u8 reserved_at_0[0x4];
2768 u8 reserved_at_8[0x18];
2770 u8 reserved_at_20[0x8];
2771 u8 user_index[0x18];
2773 u8 reserved_at_40[0x8];
2776 u8 counter_set_id[0x8];
2777 u8 atomic_mode[0x4];
2781 u8 atomic_like_write_en[0x1];
2782 u8 latency_sensitive[0x1];
2785 u8 reserved_at_73[0xd];
2787 u8 reserved_at_80[0x8];
2789 u8 reserved_at_90[0x3];
2790 u8 min_rnr_nak[0x5];
2791 u8 reserved_at_98[0x8];
2793 u8 reserved_at_a0[0x8];
2796 u8 reserved_at_c0[0x8];
2800 u8 reserved_at_e8[0x4];
2801 u8 flow_label[0x14];
2803 u8 dc_access_key[0x40];
2805 u8 reserved_at_140[0x5];
2808 u8 pkey_index[0x10];
2810 u8 reserved_at_160[0x8];
2811 u8 my_addr_index[0x8];
2812 u8 reserved_at_170[0x8];
2815 u8 dc_access_key_violation_count[0x20];
2817 u8 reserved_at_1a0[0x14];
2823 u8 reserved_at_1c0[0x40];
2827 MLX5_CQC_STATUS_OK = 0x0,
2828 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2829 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2833 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2834 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2838 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2839 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2840 MLX5_CQC_ST_FIRED = 0xa,
2844 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2845 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2846 MLX5_CQ_PERIOD_NUM_MODES
2849 struct mlx5_ifc_cqc_bits {
2851 u8 reserved_at_4[0x4];
2854 u8 reserved_at_c[0x1];
2855 u8 scqe_break_moderation_en[0x1];
2857 u8 cq_period_mode[0x2];
2858 u8 cqe_comp_en[0x1];
2859 u8 mini_cqe_res_format[0x2];
2861 u8 reserved_at_18[0x8];
2863 u8 reserved_at_20[0x20];
2865 u8 reserved_at_40[0x14];
2866 u8 page_offset[0x6];
2867 u8 reserved_at_5a[0x6];
2869 u8 reserved_at_60[0x3];
2870 u8 log_cq_size[0x5];
2873 u8 reserved_at_80[0x4];
2875 u8 cq_max_count[0x10];
2877 u8 reserved_at_a0[0x18];
2880 u8 reserved_at_c0[0x3];
2881 u8 log_page_size[0x5];
2882 u8 reserved_at_c8[0x18];
2884 u8 reserved_at_e0[0x20];
2886 u8 reserved_at_100[0x8];
2887 u8 last_notified_index[0x18];
2889 u8 reserved_at_120[0x8];
2890 u8 last_solicit_index[0x18];
2892 u8 reserved_at_140[0x8];
2893 u8 consumer_counter[0x18];
2895 u8 reserved_at_160[0x8];
2896 u8 producer_counter[0x18];
2898 u8 reserved_at_180[0x40];
2903 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2904 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2905 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2906 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2907 u8 reserved_at_0[0x800];
2910 struct mlx5_ifc_query_adapter_param_block_bits {
2911 u8 reserved_at_0[0xc0];
2913 u8 reserved_at_c0[0x8];
2914 u8 ieee_vendor_id[0x18];
2916 u8 reserved_at_e0[0x10];
2917 u8 vsd_vendor_id[0x10];
2921 u8 vsd_contd_psid[16][0x8];
2925 MLX5_XRQC_STATE_GOOD = 0x0,
2926 MLX5_XRQC_STATE_ERROR = 0x1,
2930 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2931 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2935 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2938 struct mlx5_ifc_tag_matching_topology_context_bits {
2939 u8 log_matching_list_sz[0x4];
2940 u8 reserved_at_4[0xc];
2941 u8 append_next_index[0x10];
2943 u8 sw_phase_cnt[0x10];
2944 u8 hw_phase_cnt[0x10];
2946 u8 reserved_at_40[0x40];
2949 struct mlx5_ifc_xrqc_bits {
2952 u8 reserved_at_5[0xf];
2954 u8 reserved_at_18[0x4];
2957 u8 reserved_at_20[0x8];
2958 u8 user_index[0x18];
2960 u8 reserved_at_40[0x8];
2963 u8 reserved_at_60[0xa0];
2965 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2967 u8 reserved_at_180[0x880];
2969 struct mlx5_ifc_wq_bits wq;
2972 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2973 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2974 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2975 u8 reserved_at_0[0x20];
2978 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2979 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2980 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2981 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2982 u8 reserved_at_0[0x20];
2985 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2986 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2987 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2988 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2989 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2990 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2991 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2992 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2993 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2994 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2995 u8 reserved_at_0[0x7c0];
2998 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2999 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3000 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
3001 u8 reserved_at_0[0x7c0];
3004 union mlx5_ifc_event_auto_bits {
3005 struct mlx5_ifc_comp_event_bits comp_event;
3006 struct mlx5_ifc_dct_events_bits dct_events;
3007 struct mlx5_ifc_qp_events_bits qp_events;
3008 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3009 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3010 struct mlx5_ifc_cq_error_bits cq_error;
3011 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3012 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3013 struct mlx5_ifc_gpio_event_bits gpio_event;
3014 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3015 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3016 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3017 u8 reserved_at_0[0xe0];
3020 struct mlx5_ifc_health_buffer_bits {
3021 u8 reserved_at_0[0x100];
3023 u8 assert_existptr[0x20];
3025 u8 assert_callra[0x20];
3027 u8 reserved_at_140[0x40];
3029 u8 fw_version[0x20];
3033 u8 reserved_at_1c0[0x20];
3035 u8 irisc_index[0x8];
3040 struct mlx5_ifc_register_loopback_control_bits {
3042 u8 reserved_at_1[0x7];
3044 u8 reserved_at_10[0x10];
3046 u8 reserved_at_20[0x60];
3049 struct mlx5_ifc_vport_tc_element_bits {
3050 u8 traffic_class[0x4];
3051 u8 reserved_at_4[0xc];
3052 u8 vport_number[0x10];
3055 struct mlx5_ifc_vport_element_bits {
3056 u8 reserved_at_0[0x10];
3057 u8 vport_number[0x10];
3061 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3062 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3063 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3066 struct mlx5_ifc_tsar_element_bits {
3067 u8 reserved_at_0[0x8];
3069 u8 reserved_at_10[0x10];
3072 struct mlx5_ifc_teardown_hca_out_bits {
3074 u8 reserved_at_8[0x18];
3078 u8 reserved_at_40[0x40];
3082 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3083 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3086 struct mlx5_ifc_teardown_hca_in_bits {
3088 u8 reserved_at_10[0x10];
3090 u8 reserved_at_20[0x10];
3093 u8 reserved_at_40[0x10];
3096 u8 reserved_at_60[0x20];
3099 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3101 u8 reserved_at_8[0x18];
3105 u8 reserved_at_40[0x40];
3108 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3110 u8 reserved_at_10[0x10];
3112 u8 reserved_at_20[0x10];
3115 u8 reserved_at_40[0x8];
3118 u8 reserved_at_60[0x20];
3120 u8 opt_param_mask[0x20];
3122 u8 reserved_at_a0[0x20];
3124 struct mlx5_ifc_qpc_bits qpc;
3126 u8 reserved_at_800[0x80];
3129 struct mlx5_ifc_sqd2rts_qp_out_bits {
3131 u8 reserved_at_8[0x18];
3135 u8 reserved_at_40[0x40];
3138 struct mlx5_ifc_sqd2rts_qp_in_bits {
3140 u8 reserved_at_10[0x10];
3142 u8 reserved_at_20[0x10];
3145 u8 reserved_at_40[0x8];
3148 u8 reserved_at_60[0x20];
3150 u8 opt_param_mask[0x20];
3152 u8 reserved_at_a0[0x20];
3154 struct mlx5_ifc_qpc_bits qpc;
3156 u8 reserved_at_800[0x80];
3159 struct mlx5_ifc_set_roce_address_out_bits {
3161 u8 reserved_at_8[0x18];
3165 u8 reserved_at_40[0x40];
3168 struct mlx5_ifc_set_roce_address_in_bits {
3170 u8 reserved_at_10[0x10];
3172 u8 reserved_at_20[0x10];
3175 u8 roce_address_index[0x10];
3176 u8 reserved_at_50[0x10];
3178 u8 reserved_at_60[0x20];
3180 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3183 struct mlx5_ifc_set_mad_demux_out_bits {
3185 u8 reserved_at_8[0x18];
3189 u8 reserved_at_40[0x40];
3193 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3194 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3197 struct mlx5_ifc_set_mad_demux_in_bits {
3199 u8 reserved_at_10[0x10];
3201 u8 reserved_at_20[0x10];
3204 u8 reserved_at_40[0x20];
3206 u8 reserved_at_60[0x6];
3208 u8 reserved_at_68[0x18];
3211 struct mlx5_ifc_set_l2_table_entry_out_bits {
3213 u8 reserved_at_8[0x18];
3217 u8 reserved_at_40[0x40];
3220 struct mlx5_ifc_set_l2_table_entry_in_bits {
3222 u8 reserved_at_10[0x10];
3224 u8 reserved_at_20[0x10];
3227 u8 reserved_at_40[0x60];
3229 u8 reserved_at_a0[0x8];
3230 u8 table_index[0x18];
3232 u8 reserved_at_c0[0x20];
3234 u8 reserved_at_e0[0x13];
3238 struct mlx5_ifc_mac_address_layout_bits mac_address;
3240 u8 reserved_at_140[0xc0];
3243 struct mlx5_ifc_set_issi_out_bits {
3245 u8 reserved_at_8[0x18];
3249 u8 reserved_at_40[0x40];
3252 struct mlx5_ifc_set_issi_in_bits {
3254 u8 reserved_at_10[0x10];
3256 u8 reserved_at_20[0x10];
3259 u8 reserved_at_40[0x10];
3260 u8 current_issi[0x10];
3262 u8 reserved_at_60[0x20];
3265 struct mlx5_ifc_set_hca_cap_out_bits {
3267 u8 reserved_at_8[0x18];
3271 u8 reserved_at_40[0x40];
3274 struct mlx5_ifc_set_hca_cap_in_bits {
3276 u8 reserved_at_10[0x10];
3278 u8 reserved_at_20[0x10];
3281 u8 reserved_at_40[0x40];
3283 union mlx5_ifc_hca_cap_union_bits capability;
3287 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3288 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3289 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3290 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3293 struct mlx5_ifc_set_fte_out_bits {
3295 u8 reserved_at_8[0x18];
3299 u8 reserved_at_40[0x40];
3302 struct mlx5_ifc_set_fte_in_bits {
3304 u8 reserved_at_10[0x10];
3306 u8 reserved_at_20[0x10];
3309 u8 other_vport[0x1];
3310 u8 reserved_at_41[0xf];
3311 u8 vport_number[0x10];
3313 u8 reserved_at_60[0x20];
3316 u8 reserved_at_88[0x18];
3318 u8 reserved_at_a0[0x8];
3321 u8 reserved_at_c0[0x18];
3322 u8 modify_enable_mask[0x8];
3324 u8 reserved_at_e0[0x20];
3326 u8 flow_index[0x20];
3328 u8 reserved_at_120[0xe0];
3330 struct mlx5_ifc_flow_context_bits flow_context;
3333 struct mlx5_ifc_rts2rts_qp_out_bits {
3335 u8 reserved_at_8[0x18];
3339 u8 reserved_at_40[0x40];
3342 struct mlx5_ifc_rts2rts_qp_in_bits {
3344 u8 reserved_at_10[0x10];
3346 u8 reserved_at_20[0x10];
3349 u8 reserved_at_40[0x8];
3352 u8 reserved_at_60[0x20];
3354 u8 opt_param_mask[0x20];
3356 u8 reserved_at_a0[0x20];
3358 struct mlx5_ifc_qpc_bits qpc;
3360 u8 reserved_at_800[0x80];
3363 struct mlx5_ifc_rtr2rts_qp_out_bits {
3365 u8 reserved_at_8[0x18];
3369 u8 reserved_at_40[0x40];
3372 struct mlx5_ifc_rtr2rts_qp_in_bits {
3374 u8 reserved_at_10[0x10];
3376 u8 reserved_at_20[0x10];
3379 u8 reserved_at_40[0x8];
3382 u8 reserved_at_60[0x20];
3384 u8 opt_param_mask[0x20];
3386 u8 reserved_at_a0[0x20];
3388 struct mlx5_ifc_qpc_bits qpc;
3390 u8 reserved_at_800[0x80];
3393 struct mlx5_ifc_rst2init_qp_out_bits {
3395 u8 reserved_at_8[0x18];
3399 u8 reserved_at_40[0x40];
3402 struct mlx5_ifc_rst2init_qp_in_bits {
3404 u8 reserved_at_10[0x10];
3406 u8 reserved_at_20[0x10];
3409 u8 reserved_at_40[0x8];
3412 u8 reserved_at_60[0x20];
3414 u8 opt_param_mask[0x20];
3416 u8 reserved_at_a0[0x20];
3418 struct mlx5_ifc_qpc_bits qpc;
3420 u8 reserved_at_800[0x80];
3423 struct mlx5_ifc_query_xrq_out_bits {
3425 u8 reserved_at_8[0x18];
3429 u8 reserved_at_40[0x40];
3431 struct mlx5_ifc_xrqc_bits xrq_context;
3434 struct mlx5_ifc_query_xrq_in_bits {
3436 u8 reserved_at_10[0x10];
3438 u8 reserved_at_20[0x10];
3441 u8 reserved_at_40[0x8];
3444 u8 reserved_at_60[0x20];
3447 struct mlx5_ifc_query_xrc_srq_out_bits {
3449 u8 reserved_at_8[0x18];
3453 u8 reserved_at_40[0x40];
3455 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3457 u8 reserved_at_280[0x600];
3462 struct mlx5_ifc_query_xrc_srq_in_bits {
3464 u8 reserved_at_10[0x10];
3466 u8 reserved_at_20[0x10];
3469 u8 reserved_at_40[0x8];
3472 u8 reserved_at_60[0x20];
3476 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3477 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3480 struct mlx5_ifc_query_vport_state_out_bits {
3482 u8 reserved_at_8[0x18];
3486 u8 reserved_at_40[0x20];
3488 u8 reserved_at_60[0x18];
3489 u8 admin_state[0x4];
3494 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3495 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3498 struct mlx5_ifc_query_vport_state_in_bits {
3500 u8 reserved_at_10[0x10];
3502 u8 reserved_at_20[0x10];
3505 u8 other_vport[0x1];
3506 u8 reserved_at_41[0xf];
3507 u8 vport_number[0x10];
3509 u8 reserved_at_60[0x20];
3512 struct mlx5_ifc_query_vport_counter_out_bits {
3514 u8 reserved_at_8[0x18];
3518 u8 reserved_at_40[0x40];
3520 struct mlx5_ifc_traffic_counter_bits received_errors;
3522 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3524 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3526 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3528 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3530 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3532 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3534 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3536 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3538 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3540 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3542 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3544 u8 reserved_at_680[0xa00];
3548 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3551 struct mlx5_ifc_query_vport_counter_in_bits {
3553 u8 reserved_at_10[0x10];
3555 u8 reserved_at_20[0x10];
3558 u8 other_vport[0x1];
3559 u8 reserved_at_41[0xb];
3561 u8 vport_number[0x10];
3563 u8 reserved_at_60[0x60];
3566 u8 reserved_at_c1[0x1f];
3568 u8 reserved_at_e0[0x20];
3571 struct mlx5_ifc_query_tis_out_bits {
3573 u8 reserved_at_8[0x18];
3577 u8 reserved_at_40[0x40];
3579 struct mlx5_ifc_tisc_bits tis_context;
3582 struct mlx5_ifc_query_tis_in_bits {
3584 u8 reserved_at_10[0x10];
3586 u8 reserved_at_20[0x10];
3589 u8 reserved_at_40[0x8];
3592 u8 reserved_at_60[0x20];
3595 struct mlx5_ifc_query_tir_out_bits {
3597 u8 reserved_at_8[0x18];
3601 u8 reserved_at_40[0xc0];
3603 struct mlx5_ifc_tirc_bits tir_context;
3606 struct mlx5_ifc_query_tir_in_bits {
3608 u8 reserved_at_10[0x10];
3610 u8 reserved_at_20[0x10];
3613 u8 reserved_at_40[0x8];
3616 u8 reserved_at_60[0x20];
3619 struct mlx5_ifc_query_srq_out_bits {
3621 u8 reserved_at_8[0x18];
3625 u8 reserved_at_40[0x40];
3627 struct mlx5_ifc_srqc_bits srq_context_entry;
3629 u8 reserved_at_280[0x600];
3634 struct mlx5_ifc_query_srq_in_bits {
3636 u8 reserved_at_10[0x10];
3638 u8 reserved_at_20[0x10];
3641 u8 reserved_at_40[0x8];
3644 u8 reserved_at_60[0x20];
3647 struct mlx5_ifc_query_sq_out_bits {
3649 u8 reserved_at_8[0x18];
3653 u8 reserved_at_40[0xc0];
3655 struct mlx5_ifc_sqc_bits sq_context;
3658 struct mlx5_ifc_query_sq_in_bits {
3660 u8 reserved_at_10[0x10];
3662 u8 reserved_at_20[0x10];
3665 u8 reserved_at_40[0x8];
3668 u8 reserved_at_60[0x20];
3671 struct mlx5_ifc_query_special_contexts_out_bits {
3673 u8 reserved_at_8[0x18];
3677 u8 dump_fill_mkey[0x20];
3682 struct mlx5_ifc_query_special_contexts_in_bits {
3684 u8 reserved_at_10[0x10];
3686 u8 reserved_at_20[0x10];
3689 u8 reserved_at_40[0x40];
3692 struct mlx5_ifc_query_scheduling_element_out_bits {
3694 u8 reserved_at_10[0x10];
3696 u8 reserved_at_20[0x10];
3699 u8 reserved_at_40[0xc0];
3701 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3703 u8 reserved_at_300[0x100];
3707 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3710 struct mlx5_ifc_query_scheduling_element_in_bits {
3712 u8 reserved_at_10[0x10];
3714 u8 reserved_at_20[0x10];
3717 u8 scheduling_hierarchy[0x8];
3718 u8 reserved_at_48[0x18];
3720 u8 scheduling_element_id[0x20];
3722 u8 reserved_at_80[0x180];
3725 struct mlx5_ifc_query_rqt_out_bits {
3727 u8 reserved_at_8[0x18];
3731 u8 reserved_at_40[0xc0];
3733 struct mlx5_ifc_rqtc_bits rqt_context;
3736 struct mlx5_ifc_query_rqt_in_bits {
3738 u8 reserved_at_10[0x10];
3740 u8 reserved_at_20[0x10];
3743 u8 reserved_at_40[0x8];
3746 u8 reserved_at_60[0x20];
3749 struct mlx5_ifc_query_rq_out_bits {
3751 u8 reserved_at_8[0x18];
3755 u8 reserved_at_40[0xc0];
3757 struct mlx5_ifc_rqc_bits rq_context;
3760 struct mlx5_ifc_query_rq_in_bits {
3762 u8 reserved_at_10[0x10];
3764 u8 reserved_at_20[0x10];
3767 u8 reserved_at_40[0x8];
3770 u8 reserved_at_60[0x20];
3773 struct mlx5_ifc_query_roce_address_out_bits {
3775 u8 reserved_at_8[0x18];
3779 u8 reserved_at_40[0x40];
3781 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3784 struct mlx5_ifc_query_roce_address_in_bits {
3786 u8 reserved_at_10[0x10];
3788 u8 reserved_at_20[0x10];
3791 u8 roce_address_index[0x10];
3792 u8 reserved_at_50[0x10];
3794 u8 reserved_at_60[0x20];
3797 struct mlx5_ifc_query_rmp_out_bits {
3799 u8 reserved_at_8[0x18];
3803 u8 reserved_at_40[0xc0];
3805 struct mlx5_ifc_rmpc_bits rmp_context;
3808 struct mlx5_ifc_query_rmp_in_bits {
3810 u8 reserved_at_10[0x10];
3812 u8 reserved_at_20[0x10];
3815 u8 reserved_at_40[0x8];
3818 u8 reserved_at_60[0x20];
3821 struct mlx5_ifc_query_qp_out_bits {
3823 u8 reserved_at_8[0x18];
3827 u8 reserved_at_40[0x40];
3829 u8 opt_param_mask[0x20];
3831 u8 reserved_at_a0[0x20];
3833 struct mlx5_ifc_qpc_bits qpc;
3835 u8 reserved_at_800[0x80];
3840 struct mlx5_ifc_query_qp_in_bits {
3842 u8 reserved_at_10[0x10];
3844 u8 reserved_at_20[0x10];
3847 u8 reserved_at_40[0x8];
3850 u8 reserved_at_60[0x20];
3853 struct mlx5_ifc_query_q_counter_out_bits {
3855 u8 reserved_at_8[0x18];
3859 u8 reserved_at_40[0x40];
3861 u8 rx_write_requests[0x20];
3863 u8 reserved_at_a0[0x20];
3865 u8 rx_read_requests[0x20];
3867 u8 reserved_at_e0[0x20];
3869 u8 rx_atomic_requests[0x20];
3871 u8 reserved_at_120[0x20];
3873 u8 rx_dct_connect[0x20];
3875 u8 reserved_at_160[0x20];
3877 u8 out_of_buffer[0x20];
3879 u8 reserved_at_1a0[0x20];
3881 u8 out_of_sequence[0x20];
3883 u8 reserved_at_1e0[0x20];
3885 u8 duplicate_request[0x20];
3887 u8 reserved_at_220[0x20];
3889 u8 rnr_nak_retry_err[0x20];
3891 u8 reserved_at_260[0x20];
3893 u8 packet_seq_err[0x20];
3895 u8 reserved_at_2a0[0x20];
3897 u8 implied_nak_seq_err[0x20];
3899 u8 reserved_at_2e0[0x20];
3901 u8 local_ack_timeout_err[0x20];
3903 u8 reserved_at_320[0x4e0];
3906 struct mlx5_ifc_query_q_counter_in_bits {
3908 u8 reserved_at_10[0x10];
3910 u8 reserved_at_20[0x10];
3913 u8 reserved_at_40[0x80];
3916 u8 reserved_at_c1[0x1f];
3918 u8 reserved_at_e0[0x18];
3919 u8 counter_set_id[0x8];
3922 struct mlx5_ifc_query_pages_out_bits {
3924 u8 reserved_at_8[0x18];
3928 u8 reserved_at_40[0x10];
3929 u8 function_id[0x10];
3935 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3936 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3937 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3940 struct mlx5_ifc_query_pages_in_bits {
3942 u8 reserved_at_10[0x10];
3944 u8 reserved_at_20[0x10];
3947 u8 reserved_at_40[0x10];
3948 u8 function_id[0x10];
3950 u8 reserved_at_60[0x20];
3953 struct mlx5_ifc_query_nic_vport_context_out_bits {
3955 u8 reserved_at_8[0x18];
3959 u8 reserved_at_40[0x40];
3961 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3964 struct mlx5_ifc_query_nic_vport_context_in_bits {
3966 u8 reserved_at_10[0x10];
3968 u8 reserved_at_20[0x10];
3971 u8 other_vport[0x1];
3972 u8 reserved_at_41[0xf];
3973 u8 vport_number[0x10];
3975 u8 reserved_at_60[0x5];
3976 u8 allowed_list_type[0x3];
3977 u8 reserved_at_68[0x18];
3980 struct mlx5_ifc_query_mkey_out_bits {
3982 u8 reserved_at_8[0x18];
3986 u8 reserved_at_40[0x40];
3988 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3990 u8 reserved_at_280[0x600];
3992 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3994 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3997 struct mlx5_ifc_query_mkey_in_bits {
3999 u8 reserved_at_10[0x10];
4001 u8 reserved_at_20[0x10];
4004 u8 reserved_at_40[0x8];
4005 u8 mkey_index[0x18];
4008 u8 reserved_at_61[0x1f];
4011 struct mlx5_ifc_query_mad_demux_out_bits {
4013 u8 reserved_at_8[0x18];
4017 u8 reserved_at_40[0x40];
4019 u8 mad_dumux_parameters_block[0x20];
4022 struct mlx5_ifc_query_mad_demux_in_bits {
4024 u8 reserved_at_10[0x10];
4026 u8 reserved_at_20[0x10];
4029 u8 reserved_at_40[0x40];
4032 struct mlx5_ifc_query_l2_table_entry_out_bits {
4034 u8 reserved_at_8[0x18];
4038 u8 reserved_at_40[0xa0];
4040 u8 reserved_at_e0[0x13];
4044 struct mlx5_ifc_mac_address_layout_bits mac_address;
4046 u8 reserved_at_140[0xc0];
4049 struct mlx5_ifc_query_l2_table_entry_in_bits {
4051 u8 reserved_at_10[0x10];
4053 u8 reserved_at_20[0x10];
4056 u8 reserved_at_40[0x60];
4058 u8 reserved_at_a0[0x8];
4059 u8 table_index[0x18];
4061 u8 reserved_at_c0[0x140];
4064 struct mlx5_ifc_query_issi_out_bits {
4066 u8 reserved_at_8[0x18];
4070 u8 reserved_at_40[0x10];
4071 u8 current_issi[0x10];
4073 u8 reserved_at_60[0xa0];
4075 u8 reserved_at_100[76][0x8];
4076 u8 supported_issi_dw0[0x20];
4079 struct mlx5_ifc_query_issi_in_bits {
4081 u8 reserved_at_10[0x10];
4083 u8 reserved_at_20[0x10];
4086 u8 reserved_at_40[0x40];
4089 struct mlx5_ifc_set_driver_version_out_bits {
4091 u8 reserved_0[0x18];
4094 u8 reserved_1[0x40];
4097 struct mlx5_ifc_set_driver_version_in_bits {
4099 u8 reserved_0[0x10];
4101 u8 reserved_1[0x10];
4104 u8 reserved_2[0x40];
4105 u8 driver_version[64][0x8];
4108 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4110 u8 reserved_at_8[0x18];
4114 u8 reserved_at_40[0x40];
4116 struct mlx5_ifc_pkey_bits pkey[0];
4119 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4121 u8 reserved_at_10[0x10];
4123 u8 reserved_at_20[0x10];
4126 u8 other_vport[0x1];
4127 u8 reserved_at_41[0xb];
4129 u8 vport_number[0x10];
4131 u8 reserved_at_60[0x10];
4132 u8 pkey_index[0x10];
4136 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4137 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4138 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4141 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4143 u8 reserved_at_8[0x18];
4147 u8 reserved_at_40[0x20];
4150 u8 reserved_at_70[0x10];
4152 struct mlx5_ifc_array128_auto_bits gid[0];
4155 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4157 u8 reserved_at_10[0x10];
4159 u8 reserved_at_20[0x10];
4162 u8 other_vport[0x1];
4163 u8 reserved_at_41[0xb];
4165 u8 vport_number[0x10];
4167 u8 reserved_at_60[0x10];
4171 struct mlx5_ifc_query_hca_vport_context_out_bits {
4173 u8 reserved_at_8[0x18];
4177 u8 reserved_at_40[0x40];
4179 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4182 struct mlx5_ifc_query_hca_vport_context_in_bits {
4184 u8 reserved_at_10[0x10];
4186 u8 reserved_at_20[0x10];
4189 u8 other_vport[0x1];
4190 u8 reserved_at_41[0xb];
4192 u8 vport_number[0x10];
4194 u8 reserved_at_60[0x20];
4197 struct mlx5_ifc_query_hca_cap_out_bits {
4199 u8 reserved_at_8[0x18];
4203 u8 reserved_at_40[0x40];
4205 union mlx5_ifc_hca_cap_union_bits capability;
4208 struct mlx5_ifc_query_hca_cap_in_bits {
4210 u8 reserved_at_10[0x10];
4212 u8 reserved_at_20[0x10];
4215 u8 reserved_at_40[0x40];
4218 struct mlx5_ifc_query_flow_table_out_bits {
4220 u8 reserved_at_8[0x18];
4224 u8 reserved_at_40[0x80];
4226 u8 reserved_at_c0[0x8];
4228 u8 reserved_at_d0[0x8];
4231 u8 reserved_at_e0[0x120];
4234 struct mlx5_ifc_query_flow_table_in_bits {
4236 u8 reserved_at_10[0x10];
4238 u8 reserved_at_20[0x10];
4241 u8 reserved_at_40[0x40];
4244 u8 reserved_at_88[0x18];
4246 u8 reserved_at_a0[0x8];
4249 u8 reserved_at_c0[0x140];
4252 struct mlx5_ifc_query_fte_out_bits {
4254 u8 reserved_at_8[0x18];
4258 u8 reserved_at_40[0x1c0];
4260 struct mlx5_ifc_flow_context_bits flow_context;
4263 struct mlx5_ifc_query_fte_in_bits {
4265 u8 reserved_at_10[0x10];
4267 u8 reserved_at_20[0x10];
4270 u8 reserved_at_40[0x40];
4273 u8 reserved_at_88[0x18];
4275 u8 reserved_at_a0[0x8];
4278 u8 reserved_at_c0[0x40];
4280 u8 flow_index[0x20];
4282 u8 reserved_at_120[0xe0];
4286 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4287 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4288 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4291 struct mlx5_ifc_query_flow_group_out_bits {
4293 u8 reserved_at_8[0x18];
4297 u8 reserved_at_40[0xa0];
4299 u8 start_flow_index[0x20];
4301 u8 reserved_at_100[0x20];
4303 u8 end_flow_index[0x20];
4305 u8 reserved_at_140[0xa0];
4307 u8 reserved_at_1e0[0x18];
4308 u8 match_criteria_enable[0x8];
4310 struct mlx5_ifc_fte_match_param_bits match_criteria;
4312 u8 reserved_at_1200[0xe00];
4315 struct mlx5_ifc_query_flow_group_in_bits {
4317 u8 reserved_at_10[0x10];
4319 u8 reserved_at_20[0x10];
4322 u8 reserved_at_40[0x40];
4325 u8 reserved_at_88[0x18];
4327 u8 reserved_at_a0[0x8];
4332 u8 reserved_at_e0[0x120];
4335 struct mlx5_ifc_query_flow_counter_out_bits {
4337 u8 reserved_at_8[0x18];
4341 u8 reserved_at_40[0x40];
4343 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4346 struct mlx5_ifc_query_flow_counter_in_bits {
4348 u8 reserved_at_10[0x10];
4350 u8 reserved_at_20[0x10];
4353 u8 reserved_at_40[0x80];
4356 u8 reserved_at_c1[0xf];
4357 u8 num_of_counters[0x10];
4359 u8 reserved_at_e0[0x10];
4360 u8 flow_counter_id[0x10];
4363 struct mlx5_ifc_query_esw_vport_context_out_bits {
4365 u8 reserved_at_8[0x18];
4369 u8 reserved_at_40[0x40];
4371 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4374 struct mlx5_ifc_query_esw_vport_context_in_bits {
4376 u8 reserved_at_10[0x10];
4378 u8 reserved_at_20[0x10];
4381 u8 other_vport[0x1];
4382 u8 reserved_at_41[0xf];
4383 u8 vport_number[0x10];
4385 u8 reserved_at_60[0x20];
4388 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4390 u8 reserved_at_8[0x18];
4394 u8 reserved_at_40[0x40];
4397 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4398 u8 reserved_at_0[0x1c];
4399 u8 vport_cvlan_insert[0x1];
4400 u8 vport_svlan_insert[0x1];
4401 u8 vport_cvlan_strip[0x1];
4402 u8 vport_svlan_strip[0x1];
4405 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4407 u8 reserved_at_10[0x10];
4409 u8 reserved_at_20[0x10];
4412 u8 other_vport[0x1];
4413 u8 reserved_at_41[0xf];
4414 u8 vport_number[0x10];
4416 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4418 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4421 struct mlx5_ifc_query_eq_out_bits {
4423 u8 reserved_at_8[0x18];
4427 u8 reserved_at_40[0x40];
4429 struct mlx5_ifc_eqc_bits eq_context_entry;
4431 u8 reserved_at_280[0x40];
4433 u8 event_bitmask[0x40];
4435 u8 reserved_at_300[0x580];
4440 struct mlx5_ifc_query_eq_in_bits {
4442 u8 reserved_at_10[0x10];
4444 u8 reserved_at_20[0x10];
4447 u8 reserved_at_40[0x18];
4450 u8 reserved_at_60[0x20];
4453 struct mlx5_ifc_encap_header_in_bits {
4454 u8 reserved_at_0[0x5];
4455 u8 header_type[0x3];
4456 u8 reserved_at_8[0xe];
4457 u8 encap_header_size[0xa];
4459 u8 reserved_at_20[0x10];
4460 u8 encap_header[2][0x8];
4462 u8 more_encap_header[0][0x8];
4465 struct mlx5_ifc_query_encap_header_out_bits {
4467 u8 reserved_at_8[0x18];
4471 u8 reserved_at_40[0xa0];
4473 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4476 struct mlx5_ifc_query_encap_header_in_bits {
4478 u8 reserved_at_10[0x10];
4480 u8 reserved_at_20[0x10];
4485 u8 reserved_at_60[0xa0];
4488 struct mlx5_ifc_alloc_encap_header_out_bits {
4490 u8 reserved_at_8[0x18];
4496 u8 reserved_at_60[0x20];
4499 struct mlx5_ifc_alloc_encap_header_in_bits {
4501 u8 reserved_at_10[0x10];
4503 u8 reserved_at_20[0x10];
4506 u8 reserved_at_40[0xa0];
4508 struct mlx5_ifc_encap_header_in_bits encap_header;
4511 struct mlx5_ifc_dealloc_encap_header_out_bits {
4513 u8 reserved_at_8[0x18];
4517 u8 reserved_at_40[0x40];
4520 struct mlx5_ifc_dealloc_encap_header_in_bits {
4522 u8 reserved_at_10[0x10];
4524 u8 reserved_20[0x10];
4529 u8 reserved_60[0x20];
4532 struct mlx5_ifc_query_dct_out_bits {
4534 u8 reserved_at_8[0x18];
4538 u8 reserved_at_40[0x40];
4540 struct mlx5_ifc_dctc_bits dct_context_entry;
4542 u8 reserved_at_280[0x180];
4545 struct mlx5_ifc_query_dct_in_bits {
4547 u8 reserved_at_10[0x10];
4549 u8 reserved_at_20[0x10];
4552 u8 reserved_at_40[0x8];
4555 u8 reserved_at_60[0x20];
4558 struct mlx5_ifc_query_cq_out_bits {
4560 u8 reserved_at_8[0x18];
4564 u8 reserved_at_40[0x40];
4566 struct mlx5_ifc_cqc_bits cq_context;
4568 u8 reserved_at_280[0x600];
4573 struct mlx5_ifc_query_cq_in_bits {
4575 u8 reserved_at_10[0x10];
4577 u8 reserved_at_20[0x10];
4580 u8 reserved_at_40[0x8];
4583 u8 reserved_at_60[0x20];
4586 struct mlx5_ifc_query_cong_status_out_bits {
4588 u8 reserved_at_8[0x18];
4592 u8 reserved_at_40[0x20];
4596 u8 reserved_at_62[0x1e];
4599 struct mlx5_ifc_query_cong_status_in_bits {
4601 u8 reserved_at_10[0x10];
4603 u8 reserved_at_20[0x10];
4606 u8 reserved_at_40[0x18];
4608 u8 cong_protocol[0x4];
4610 u8 reserved_at_60[0x20];
4613 struct mlx5_ifc_query_cong_statistics_out_bits {
4615 u8 reserved_at_8[0x18];
4619 u8 reserved_at_40[0x40];
4625 u8 cnp_ignored_high[0x20];
4627 u8 cnp_ignored_low[0x20];
4629 u8 cnp_handled_high[0x20];
4631 u8 cnp_handled_low[0x20];
4633 u8 reserved_at_140[0x100];
4635 u8 time_stamp_high[0x20];
4637 u8 time_stamp_low[0x20];
4639 u8 accumulators_period[0x20];
4641 u8 ecn_marked_roce_packets_high[0x20];
4643 u8 ecn_marked_roce_packets_low[0x20];
4645 u8 cnps_sent_high[0x20];
4647 u8 cnps_sent_low[0x20];
4649 u8 reserved_at_320[0x560];
4652 struct mlx5_ifc_query_cong_statistics_in_bits {
4654 u8 reserved_at_10[0x10];
4656 u8 reserved_at_20[0x10];
4660 u8 reserved_at_41[0x1f];
4662 u8 reserved_at_60[0x20];
4665 struct mlx5_ifc_query_cong_params_out_bits {
4667 u8 reserved_at_8[0x18];
4671 u8 reserved_at_40[0x40];
4673 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4676 struct mlx5_ifc_query_cong_params_in_bits {
4678 u8 reserved_at_10[0x10];
4680 u8 reserved_at_20[0x10];
4683 u8 reserved_at_40[0x1c];
4684 u8 cong_protocol[0x4];
4686 u8 reserved_at_60[0x20];
4689 struct mlx5_ifc_query_adapter_out_bits {
4691 u8 reserved_at_8[0x18];
4695 u8 reserved_at_40[0x40];
4697 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4700 struct mlx5_ifc_query_adapter_in_bits {
4702 u8 reserved_at_10[0x10];
4704 u8 reserved_at_20[0x10];
4707 u8 reserved_at_40[0x40];
4710 struct mlx5_ifc_qp_2rst_out_bits {
4712 u8 reserved_at_8[0x18];
4716 u8 reserved_at_40[0x40];
4719 struct mlx5_ifc_qp_2rst_in_bits {
4721 u8 reserved_at_10[0x10];
4723 u8 reserved_at_20[0x10];
4726 u8 reserved_at_40[0x8];
4729 u8 reserved_at_60[0x20];
4732 struct mlx5_ifc_qp_2err_out_bits {
4734 u8 reserved_at_8[0x18];
4738 u8 reserved_at_40[0x40];
4741 struct mlx5_ifc_qp_2err_in_bits {
4743 u8 reserved_at_10[0x10];
4745 u8 reserved_at_20[0x10];
4748 u8 reserved_at_40[0x8];
4751 u8 reserved_at_60[0x20];
4754 struct mlx5_ifc_page_fault_resume_out_bits {
4756 u8 reserved_at_8[0x18];
4760 u8 reserved_at_40[0x40];
4763 struct mlx5_ifc_page_fault_resume_in_bits {
4765 u8 reserved_at_10[0x10];
4767 u8 reserved_at_20[0x10];
4771 u8 reserved_at_41[0x4];
4777 u8 reserved_at_60[0x20];
4780 struct mlx5_ifc_nop_out_bits {
4782 u8 reserved_at_8[0x18];
4786 u8 reserved_at_40[0x40];
4789 struct mlx5_ifc_nop_in_bits {
4791 u8 reserved_at_10[0x10];
4793 u8 reserved_at_20[0x10];
4796 u8 reserved_at_40[0x40];
4799 struct mlx5_ifc_modify_vport_state_out_bits {
4801 u8 reserved_at_8[0x18];
4805 u8 reserved_at_40[0x40];
4808 struct mlx5_ifc_modify_vport_state_in_bits {
4810 u8 reserved_at_10[0x10];
4812 u8 reserved_at_20[0x10];
4815 u8 other_vport[0x1];
4816 u8 reserved_at_41[0xf];
4817 u8 vport_number[0x10];
4819 u8 reserved_at_60[0x18];
4820 u8 admin_state[0x4];
4821 u8 reserved_at_7c[0x4];
4824 struct mlx5_ifc_modify_tis_out_bits {
4826 u8 reserved_at_8[0x18];
4830 u8 reserved_at_40[0x40];
4833 struct mlx5_ifc_modify_tis_bitmask_bits {
4834 u8 reserved_at_0[0x20];
4836 u8 reserved_at_20[0x1d];
4837 u8 lag_tx_port_affinity[0x1];
4838 u8 strict_lag_tx_port_affinity[0x1];
4842 struct mlx5_ifc_modify_tis_in_bits {
4844 u8 reserved_at_10[0x10];
4846 u8 reserved_at_20[0x10];
4849 u8 reserved_at_40[0x8];
4852 u8 reserved_at_60[0x20];
4854 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4856 u8 reserved_at_c0[0x40];
4858 struct mlx5_ifc_tisc_bits ctx;
4861 struct mlx5_ifc_modify_tir_bitmask_bits {
4862 u8 reserved_at_0[0x20];
4864 u8 reserved_at_20[0x1b];
4866 u8 reserved_at_3c[0x1];
4868 u8 reserved_at_3e[0x1];
4872 struct mlx5_ifc_modify_tir_out_bits {
4874 u8 reserved_at_8[0x18];
4878 u8 reserved_at_40[0x40];
4881 struct mlx5_ifc_modify_tir_in_bits {
4883 u8 reserved_at_10[0x10];
4885 u8 reserved_at_20[0x10];
4888 u8 reserved_at_40[0x8];
4891 u8 reserved_at_60[0x20];
4893 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4895 u8 reserved_at_c0[0x40];
4897 struct mlx5_ifc_tirc_bits ctx;
4900 struct mlx5_ifc_modify_sq_out_bits {
4902 u8 reserved_at_8[0x18];
4906 u8 reserved_at_40[0x40];
4909 struct mlx5_ifc_modify_sq_in_bits {
4911 u8 reserved_at_10[0x10];
4913 u8 reserved_at_20[0x10];
4917 u8 reserved_at_44[0x4];
4920 u8 reserved_at_60[0x20];
4922 u8 modify_bitmask[0x40];
4924 u8 reserved_at_c0[0x40];
4926 struct mlx5_ifc_sqc_bits ctx;
4929 struct mlx5_ifc_modify_scheduling_element_out_bits {
4931 u8 reserved_at_8[0x18];
4935 u8 reserved_at_40[0x1c0];
4939 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4940 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4943 struct mlx5_ifc_modify_scheduling_element_in_bits {
4945 u8 reserved_at_10[0x10];
4947 u8 reserved_at_20[0x10];
4950 u8 scheduling_hierarchy[0x8];
4951 u8 reserved_at_48[0x18];
4953 u8 scheduling_element_id[0x20];
4955 u8 reserved_at_80[0x20];
4957 u8 modify_bitmask[0x20];
4959 u8 reserved_at_c0[0x40];
4961 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4963 u8 reserved_at_300[0x100];
4966 struct mlx5_ifc_modify_rqt_out_bits {
4968 u8 reserved_at_8[0x18];
4972 u8 reserved_at_40[0x40];
4975 struct mlx5_ifc_rqt_bitmask_bits {
4976 u8 reserved_at_0[0x20];
4978 u8 reserved_at_20[0x1f];
4982 struct mlx5_ifc_modify_rqt_in_bits {
4984 u8 reserved_at_10[0x10];
4986 u8 reserved_at_20[0x10];
4989 u8 reserved_at_40[0x8];
4992 u8 reserved_at_60[0x20];
4994 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4996 u8 reserved_at_c0[0x40];
4998 struct mlx5_ifc_rqtc_bits ctx;
5001 struct mlx5_ifc_modify_rq_out_bits {
5003 u8 reserved_at_8[0x18];
5007 u8 reserved_at_40[0x40];
5011 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5012 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5015 struct mlx5_ifc_modify_rq_in_bits {
5017 u8 reserved_at_10[0x10];
5019 u8 reserved_at_20[0x10];
5023 u8 reserved_at_44[0x4];
5026 u8 reserved_at_60[0x20];
5028 u8 modify_bitmask[0x40];
5030 u8 reserved_at_c0[0x40];
5032 struct mlx5_ifc_rqc_bits ctx;
5035 struct mlx5_ifc_modify_rmp_out_bits {
5037 u8 reserved_at_8[0x18];
5041 u8 reserved_at_40[0x40];
5044 struct mlx5_ifc_rmp_bitmask_bits {
5045 u8 reserved_at_0[0x20];
5047 u8 reserved_at_20[0x1f];
5051 struct mlx5_ifc_modify_rmp_in_bits {
5053 u8 reserved_at_10[0x10];
5055 u8 reserved_at_20[0x10];
5059 u8 reserved_at_44[0x4];
5062 u8 reserved_at_60[0x20];
5064 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5066 u8 reserved_at_c0[0x40];
5068 struct mlx5_ifc_rmpc_bits ctx;
5071 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5073 u8 reserved_at_8[0x18];
5077 u8 reserved_at_40[0x40];
5080 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5081 u8 reserved_at_0[0x16];
5086 u8 change_event[0x1];
5088 u8 permanent_address[0x1];
5089 u8 addresses_list[0x1];
5091 u8 reserved_at_1f[0x1];
5094 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5096 u8 reserved_at_10[0x10];
5098 u8 reserved_at_20[0x10];
5101 u8 other_vport[0x1];
5102 u8 reserved_at_41[0xf];
5103 u8 vport_number[0x10];
5105 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5107 u8 reserved_at_80[0x780];
5109 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5112 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5114 u8 reserved_at_8[0x18];
5118 u8 reserved_at_40[0x40];
5121 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5123 u8 reserved_at_10[0x10];
5125 u8 reserved_at_20[0x10];
5128 u8 other_vport[0x1];
5129 u8 reserved_at_41[0xb];
5131 u8 vport_number[0x10];
5133 u8 reserved_at_60[0x20];
5135 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5138 struct mlx5_ifc_modify_cq_out_bits {
5140 u8 reserved_at_8[0x18];
5144 u8 reserved_at_40[0x40];
5148 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5149 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5152 struct mlx5_ifc_modify_cq_in_bits {
5154 u8 reserved_at_10[0x10];
5156 u8 reserved_at_20[0x10];
5159 u8 reserved_at_40[0x8];
5162 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5164 struct mlx5_ifc_cqc_bits cq_context;
5166 u8 reserved_at_280[0x600];
5171 struct mlx5_ifc_modify_cong_status_out_bits {
5173 u8 reserved_at_8[0x18];
5177 u8 reserved_at_40[0x40];
5180 struct mlx5_ifc_modify_cong_status_in_bits {
5182 u8 reserved_at_10[0x10];
5184 u8 reserved_at_20[0x10];
5187 u8 reserved_at_40[0x18];
5189 u8 cong_protocol[0x4];
5193 u8 reserved_at_62[0x1e];
5196 struct mlx5_ifc_modify_cong_params_out_bits {
5198 u8 reserved_at_8[0x18];
5202 u8 reserved_at_40[0x40];
5205 struct mlx5_ifc_modify_cong_params_in_bits {
5207 u8 reserved_at_10[0x10];
5209 u8 reserved_at_20[0x10];
5212 u8 reserved_at_40[0x1c];
5213 u8 cong_protocol[0x4];
5215 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5217 u8 reserved_at_80[0x80];
5219 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5222 struct mlx5_ifc_manage_pages_out_bits {
5224 u8 reserved_at_8[0x18];
5228 u8 output_num_entries[0x20];
5230 u8 reserved_at_60[0x20];
5236 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5237 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5238 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5241 struct mlx5_ifc_manage_pages_in_bits {
5243 u8 reserved_at_10[0x10];
5245 u8 reserved_at_20[0x10];
5248 u8 reserved_at_40[0x10];
5249 u8 function_id[0x10];
5251 u8 input_num_entries[0x20];
5256 struct mlx5_ifc_mad_ifc_out_bits {
5258 u8 reserved_at_8[0x18];
5262 u8 reserved_at_40[0x40];
5264 u8 response_mad_packet[256][0x8];
5267 struct mlx5_ifc_mad_ifc_in_bits {
5269 u8 reserved_at_10[0x10];
5271 u8 reserved_at_20[0x10];
5274 u8 remote_lid[0x10];
5275 u8 reserved_at_50[0x8];
5278 u8 reserved_at_60[0x20];
5283 struct mlx5_ifc_init_hca_out_bits {
5285 u8 reserved_at_8[0x18];
5289 u8 reserved_at_40[0x40];
5292 struct mlx5_ifc_init_hca_in_bits {
5294 u8 reserved_at_10[0x10];
5296 u8 reserved_at_20[0x10];
5299 u8 reserved_at_40[0x40];
5302 struct mlx5_ifc_init2rtr_qp_out_bits {
5304 u8 reserved_at_8[0x18];
5308 u8 reserved_at_40[0x40];
5311 struct mlx5_ifc_init2rtr_qp_in_bits {
5313 u8 reserved_at_10[0x10];
5315 u8 reserved_at_20[0x10];
5318 u8 reserved_at_40[0x8];
5321 u8 reserved_at_60[0x20];
5323 u8 opt_param_mask[0x20];
5325 u8 reserved_at_a0[0x20];
5327 struct mlx5_ifc_qpc_bits qpc;
5329 u8 reserved_at_800[0x80];
5332 struct mlx5_ifc_init2init_qp_out_bits {
5334 u8 reserved_at_8[0x18];
5338 u8 reserved_at_40[0x40];
5341 struct mlx5_ifc_init2init_qp_in_bits {
5343 u8 reserved_at_10[0x10];
5345 u8 reserved_at_20[0x10];
5348 u8 reserved_at_40[0x8];
5351 u8 reserved_at_60[0x20];
5353 u8 opt_param_mask[0x20];
5355 u8 reserved_at_a0[0x20];
5357 struct mlx5_ifc_qpc_bits qpc;
5359 u8 reserved_at_800[0x80];
5362 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5364 u8 reserved_at_8[0x18];
5368 u8 reserved_at_40[0x40];
5370 u8 packet_headers_log[128][0x8];
5372 u8 packet_syndrome[64][0x8];
5375 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5377 u8 reserved_at_10[0x10];
5379 u8 reserved_at_20[0x10];
5382 u8 reserved_at_40[0x40];
5385 struct mlx5_ifc_gen_eqe_in_bits {
5387 u8 reserved_at_10[0x10];
5389 u8 reserved_at_20[0x10];
5392 u8 reserved_at_40[0x18];
5395 u8 reserved_at_60[0x20];
5400 struct mlx5_ifc_gen_eq_out_bits {
5402 u8 reserved_at_8[0x18];
5406 u8 reserved_at_40[0x40];
5409 struct mlx5_ifc_enable_hca_out_bits {
5411 u8 reserved_at_8[0x18];
5415 u8 reserved_at_40[0x20];
5418 struct mlx5_ifc_enable_hca_in_bits {
5420 u8 reserved_at_10[0x10];
5422 u8 reserved_at_20[0x10];
5425 u8 reserved_at_40[0x10];
5426 u8 function_id[0x10];
5428 u8 reserved_at_60[0x20];
5431 struct mlx5_ifc_drain_dct_out_bits {
5433 u8 reserved_at_8[0x18];
5437 u8 reserved_at_40[0x40];
5440 struct mlx5_ifc_drain_dct_in_bits {
5442 u8 reserved_at_10[0x10];
5444 u8 reserved_at_20[0x10];
5447 u8 reserved_at_40[0x8];
5450 u8 reserved_at_60[0x20];
5453 struct mlx5_ifc_disable_hca_out_bits {
5455 u8 reserved_at_8[0x18];
5459 u8 reserved_at_40[0x20];
5462 struct mlx5_ifc_disable_hca_in_bits {
5464 u8 reserved_at_10[0x10];
5466 u8 reserved_at_20[0x10];
5469 u8 reserved_at_40[0x10];
5470 u8 function_id[0x10];
5472 u8 reserved_at_60[0x20];
5475 struct mlx5_ifc_detach_from_mcg_out_bits {
5477 u8 reserved_at_8[0x18];
5481 u8 reserved_at_40[0x40];
5484 struct mlx5_ifc_detach_from_mcg_in_bits {
5486 u8 reserved_at_10[0x10];
5488 u8 reserved_at_20[0x10];
5491 u8 reserved_at_40[0x8];
5494 u8 reserved_at_60[0x20];
5496 u8 multicast_gid[16][0x8];
5499 struct mlx5_ifc_destroy_xrq_out_bits {
5501 u8 reserved_at_8[0x18];
5505 u8 reserved_at_40[0x40];
5508 struct mlx5_ifc_destroy_xrq_in_bits {
5510 u8 reserved_at_10[0x10];
5512 u8 reserved_at_20[0x10];
5515 u8 reserved_at_40[0x8];
5518 u8 reserved_at_60[0x20];
5521 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5523 u8 reserved_at_8[0x18];
5527 u8 reserved_at_40[0x40];
5530 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5532 u8 reserved_at_10[0x10];
5534 u8 reserved_at_20[0x10];
5537 u8 reserved_at_40[0x8];
5540 u8 reserved_at_60[0x20];
5543 struct mlx5_ifc_destroy_tis_out_bits {
5545 u8 reserved_at_8[0x18];
5549 u8 reserved_at_40[0x40];
5552 struct mlx5_ifc_destroy_tis_in_bits {
5554 u8 reserved_at_10[0x10];
5556 u8 reserved_at_20[0x10];
5559 u8 reserved_at_40[0x8];
5562 u8 reserved_at_60[0x20];
5565 struct mlx5_ifc_destroy_tir_out_bits {
5567 u8 reserved_at_8[0x18];
5571 u8 reserved_at_40[0x40];
5574 struct mlx5_ifc_destroy_tir_in_bits {
5576 u8 reserved_at_10[0x10];
5578 u8 reserved_at_20[0x10];
5581 u8 reserved_at_40[0x8];
5584 u8 reserved_at_60[0x20];
5587 struct mlx5_ifc_destroy_srq_out_bits {
5589 u8 reserved_at_8[0x18];
5593 u8 reserved_at_40[0x40];
5596 struct mlx5_ifc_destroy_srq_in_bits {
5598 u8 reserved_at_10[0x10];
5600 u8 reserved_at_20[0x10];
5603 u8 reserved_at_40[0x8];
5606 u8 reserved_at_60[0x20];
5609 struct mlx5_ifc_destroy_sq_out_bits {
5611 u8 reserved_at_8[0x18];
5615 u8 reserved_at_40[0x40];
5618 struct mlx5_ifc_destroy_sq_in_bits {
5620 u8 reserved_at_10[0x10];
5622 u8 reserved_at_20[0x10];
5625 u8 reserved_at_40[0x8];
5628 u8 reserved_at_60[0x20];
5631 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5633 u8 reserved_at_8[0x18];
5637 u8 reserved_at_40[0x1c0];
5640 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5642 u8 reserved_at_10[0x10];
5644 u8 reserved_at_20[0x10];
5647 u8 scheduling_hierarchy[0x8];
5648 u8 reserved_at_48[0x18];
5650 u8 scheduling_element_id[0x20];
5652 u8 reserved_at_80[0x180];
5655 struct mlx5_ifc_destroy_rqt_out_bits {
5657 u8 reserved_at_8[0x18];
5661 u8 reserved_at_40[0x40];
5664 struct mlx5_ifc_destroy_rqt_in_bits {
5666 u8 reserved_at_10[0x10];
5668 u8 reserved_at_20[0x10];
5671 u8 reserved_at_40[0x8];
5674 u8 reserved_at_60[0x20];
5677 struct mlx5_ifc_destroy_rq_out_bits {
5679 u8 reserved_at_8[0x18];
5683 u8 reserved_at_40[0x40];
5686 struct mlx5_ifc_destroy_rq_in_bits {
5688 u8 reserved_at_10[0x10];
5690 u8 reserved_at_20[0x10];
5693 u8 reserved_at_40[0x8];
5696 u8 reserved_at_60[0x20];
5699 struct mlx5_ifc_destroy_rmp_out_bits {
5701 u8 reserved_at_8[0x18];
5705 u8 reserved_at_40[0x40];
5708 struct mlx5_ifc_destroy_rmp_in_bits {
5710 u8 reserved_at_10[0x10];
5712 u8 reserved_at_20[0x10];
5715 u8 reserved_at_40[0x8];
5718 u8 reserved_at_60[0x20];
5721 struct mlx5_ifc_destroy_qp_out_bits {
5723 u8 reserved_at_8[0x18];
5727 u8 reserved_at_40[0x40];
5730 struct mlx5_ifc_destroy_qp_in_bits {
5732 u8 reserved_at_10[0x10];
5734 u8 reserved_at_20[0x10];
5737 u8 reserved_at_40[0x8];
5740 u8 reserved_at_60[0x20];
5743 struct mlx5_ifc_destroy_psv_out_bits {
5745 u8 reserved_at_8[0x18];
5749 u8 reserved_at_40[0x40];
5752 struct mlx5_ifc_destroy_psv_in_bits {
5754 u8 reserved_at_10[0x10];
5756 u8 reserved_at_20[0x10];
5759 u8 reserved_at_40[0x8];
5762 u8 reserved_at_60[0x20];
5765 struct mlx5_ifc_destroy_mkey_out_bits {
5767 u8 reserved_at_8[0x18];
5771 u8 reserved_at_40[0x40];
5774 struct mlx5_ifc_destroy_mkey_in_bits {
5776 u8 reserved_at_10[0x10];
5778 u8 reserved_at_20[0x10];
5781 u8 reserved_at_40[0x8];
5782 u8 mkey_index[0x18];
5784 u8 reserved_at_60[0x20];
5787 struct mlx5_ifc_destroy_flow_table_out_bits {
5789 u8 reserved_at_8[0x18];
5793 u8 reserved_at_40[0x40];
5796 struct mlx5_ifc_destroy_flow_table_in_bits {
5798 u8 reserved_at_10[0x10];
5800 u8 reserved_at_20[0x10];
5803 u8 other_vport[0x1];
5804 u8 reserved_at_41[0xf];
5805 u8 vport_number[0x10];
5807 u8 reserved_at_60[0x20];
5810 u8 reserved_at_88[0x18];
5812 u8 reserved_at_a0[0x8];
5815 u8 reserved_at_c0[0x140];
5818 struct mlx5_ifc_destroy_flow_group_out_bits {
5820 u8 reserved_at_8[0x18];
5824 u8 reserved_at_40[0x40];
5827 struct mlx5_ifc_destroy_flow_group_in_bits {
5829 u8 reserved_at_10[0x10];
5831 u8 reserved_at_20[0x10];
5834 u8 other_vport[0x1];
5835 u8 reserved_at_41[0xf];
5836 u8 vport_number[0x10];
5838 u8 reserved_at_60[0x20];
5841 u8 reserved_at_88[0x18];
5843 u8 reserved_at_a0[0x8];
5848 u8 reserved_at_e0[0x120];
5851 struct mlx5_ifc_destroy_eq_out_bits {
5853 u8 reserved_at_8[0x18];
5857 u8 reserved_at_40[0x40];
5860 struct mlx5_ifc_destroy_eq_in_bits {
5862 u8 reserved_at_10[0x10];
5864 u8 reserved_at_20[0x10];
5867 u8 reserved_at_40[0x18];
5870 u8 reserved_at_60[0x20];
5873 struct mlx5_ifc_destroy_dct_out_bits {
5875 u8 reserved_at_8[0x18];
5879 u8 reserved_at_40[0x40];
5882 struct mlx5_ifc_destroy_dct_in_bits {
5884 u8 reserved_at_10[0x10];
5886 u8 reserved_at_20[0x10];
5889 u8 reserved_at_40[0x8];
5892 u8 reserved_at_60[0x20];
5895 struct mlx5_ifc_destroy_cq_out_bits {
5897 u8 reserved_at_8[0x18];
5901 u8 reserved_at_40[0x40];
5904 struct mlx5_ifc_destroy_cq_in_bits {
5906 u8 reserved_at_10[0x10];
5908 u8 reserved_at_20[0x10];
5911 u8 reserved_at_40[0x8];
5914 u8 reserved_at_60[0x20];
5917 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5919 u8 reserved_at_8[0x18];
5923 u8 reserved_at_40[0x40];
5926 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5928 u8 reserved_at_10[0x10];
5930 u8 reserved_at_20[0x10];
5933 u8 reserved_at_40[0x20];
5935 u8 reserved_at_60[0x10];
5936 u8 vxlan_udp_port[0x10];
5939 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5941 u8 reserved_at_8[0x18];
5945 u8 reserved_at_40[0x40];
5948 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5950 u8 reserved_at_10[0x10];
5952 u8 reserved_at_20[0x10];
5955 u8 reserved_at_40[0x60];
5957 u8 reserved_at_a0[0x8];
5958 u8 table_index[0x18];
5960 u8 reserved_at_c0[0x140];
5963 struct mlx5_ifc_delete_fte_out_bits {
5965 u8 reserved_at_8[0x18];
5969 u8 reserved_at_40[0x40];
5972 struct mlx5_ifc_delete_fte_in_bits {
5974 u8 reserved_at_10[0x10];
5976 u8 reserved_at_20[0x10];
5979 u8 other_vport[0x1];
5980 u8 reserved_at_41[0xf];
5981 u8 vport_number[0x10];
5983 u8 reserved_at_60[0x20];
5986 u8 reserved_at_88[0x18];
5988 u8 reserved_at_a0[0x8];
5991 u8 reserved_at_c0[0x40];
5993 u8 flow_index[0x20];
5995 u8 reserved_at_120[0xe0];
5998 struct mlx5_ifc_dealloc_xrcd_out_bits {
6000 u8 reserved_at_8[0x18];
6004 u8 reserved_at_40[0x40];
6007 struct mlx5_ifc_dealloc_xrcd_in_bits {
6009 u8 reserved_at_10[0x10];
6011 u8 reserved_at_20[0x10];
6014 u8 reserved_at_40[0x8];
6017 u8 reserved_at_60[0x20];
6020 struct mlx5_ifc_dealloc_uar_out_bits {
6022 u8 reserved_at_8[0x18];
6026 u8 reserved_at_40[0x40];
6029 struct mlx5_ifc_dealloc_uar_in_bits {
6031 u8 reserved_at_10[0x10];
6033 u8 reserved_at_20[0x10];
6036 u8 reserved_at_40[0x8];
6039 u8 reserved_at_60[0x20];
6042 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6044 u8 reserved_at_8[0x18];
6048 u8 reserved_at_40[0x40];
6051 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6053 u8 reserved_at_10[0x10];
6055 u8 reserved_at_20[0x10];
6058 u8 reserved_at_40[0x8];
6059 u8 transport_domain[0x18];
6061 u8 reserved_at_60[0x20];
6064 struct mlx5_ifc_dealloc_q_counter_out_bits {
6066 u8 reserved_at_8[0x18];
6070 u8 reserved_at_40[0x40];
6073 struct mlx5_ifc_dealloc_q_counter_in_bits {
6075 u8 reserved_at_10[0x10];
6077 u8 reserved_at_20[0x10];
6080 u8 reserved_at_40[0x18];
6081 u8 counter_set_id[0x8];
6083 u8 reserved_at_60[0x20];
6086 struct mlx5_ifc_dealloc_pd_out_bits {
6088 u8 reserved_at_8[0x18];
6092 u8 reserved_at_40[0x40];
6095 struct mlx5_ifc_dealloc_pd_in_bits {
6097 u8 reserved_at_10[0x10];
6099 u8 reserved_at_20[0x10];
6102 u8 reserved_at_40[0x8];
6105 u8 reserved_at_60[0x20];
6108 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6110 u8 reserved_at_8[0x18];
6114 u8 reserved_at_40[0x40];
6117 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6119 u8 reserved_at_10[0x10];
6121 u8 reserved_at_20[0x10];
6124 u8 reserved_at_40[0x10];
6125 u8 flow_counter_id[0x10];
6127 u8 reserved_at_60[0x20];
6130 struct mlx5_ifc_create_xrq_out_bits {
6132 u8 reserved_at_8[0x18];
6136 u8 reserved_at_40[0x8];
6139 u8 reserved_at_60[0x20];
6142 struct mlx5_ifc_create_xrq_in_bits {
6144 u8 reserved_at_10[0x10];
6146 u8 reserved_at_20[0x10];
6149 u8 reserved_at_40[0x40];
6151 struct mlx5_ifc_xrqc_bits xrq_context;
6154 struct mlx5_ifc_create_xrc_srq_out_bits {
6156 u8 reserved_at_8[0x18];
6160 u8 reserved_at_40[0x8];
6163 u8 reserved_at_60[0x20];
6166 struct mlx5_ifc_create_xrc_srq_in_bits {
6168 u8 reserved_at_10[0x10];
6170 u8 reserved_at_20[0x10];
6173 u8 reserved_at_40[0x40];
6175 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6177 u8 reserved_at_280[0x600];
6182 struct mlx5_ifc_create_tis_out_bits {
6184 u8 reserved_at_8[0x18];
6188 u8 reserved_at_40[0x8];
6191 u8 reserved_at_60[0x20];
6194 struct mlx5_ifc_create_tis_in_bits {
6196 u8 reserved_at_10[0x10];
6198 u8 reserved_at_20[0x10];
6201 u8 reserved_at_40[0xc0];
6203 struct mlx5_ifc_tisc_bits ctx;
6206 struct mlx5_ifc_create_tir_out_bits {
6208 u8 reserved_at_8[0x18];
6212 u8 reserved_at_40[0x8];
6215 u8 reserved_at_60[0x20];
6218 struct mlx5_ifc_create_tir_in_bits {
6220 u8 reserved_at_10[0x10];
6222 u8 reserved_at_20[0x10];
6225 u8 reserved_at_40[0xc0];
6227 struct mlx5_ifc_tirc_bits ctx;
6230 struct mlx5_ifc_create_srq_out_bits {
6232 u8 reserved_at_8[0x18];
6236 u8 reserved_at_40[0x8];
6239 u8 reserved_at_60[0x20];
6242 struct mlx5_ifc_create_srq_in_bits {
6244 u8 reserved_at_10[0x10];
6246 u8 reserved_at_20[0x10];
6249 u8 reserved_at_40[0x40];
6251 struct mlx5_ifc_srqc_bits srq_context_entry;
6253 u8 reserved_at_280[0x600];
6258 struct mlx5_ifc_create_sq_out_bits {
6260 u8 reserved_at_8[0x18];
6264 u8 reserved_at_40[0x8];
6267 u8 reserved_at_60[0x20];
6270 struct mlx5_ifc_create_sq_in_bits {
6272 u8 reserved_at_10[0x10];
6274 u8 reserved_at_20[0x10];
6277 u8 reserved_at_40[0xc0];
6279 struct mlx5_ifc_sqc_bits ctx;
6282 struct mlx5_ifc_create_scheduling_element_out_bits {
6284 u8 reserved_at_8[0x18];
6288 u8 reserved_at_40[0x40];
6290 u8 scheduling_element_id[0x20];
6292 u8 reserved_at_a0[0x160];
6295 struct mlx5_ifc_create_scheduling_element_in_bits {
6297 u8 reserved_at_10[0x10];
6299 u8 reserved_at_20[0x10];
6302 u8 scheduling_hierarchy[0x8];
6303 u8 reserved_at_48[0x18];
6305 u8 reserved_at_60[0xa0];
6307 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6309 u8 reserved_at_300[0x100];
6312 struct mlx5_ifc_create_rqt_out_bits {
6314 u8 reserved_at_8[0x18];
6318 u8 reserved_at_40[0x8];
6321 u8 reserved_at_60[0x20];
6324 struct mlx5_ifc_create_rqt_in_bits {
6326 u8 reserved_at_10[0x10];
6328 u8 reserved_at_20[0x10];
6331 u8 reserved_at_40[0xc0];
6333 struct mlx5_ifc_rqtc_bits rqt_context;
6336 struct mlx5_ifc_create_rq_out_bits {
6338 u8 reserved_at_8[0x18];
6342 u8 reserved_at_40[0x8];
6345 u8 reserved_at_60[0x20];
6348 struct mlx5_ifc_create_rq_in_bits {
6350 u8 reserved_at_10[0x10];
6352 u8 reserved_at_20[0x10];
6355 u8 reserved_at_40[0xc0];
6357 struct mlx5_ifc_rqc_bits ctx;
6360 struct mlx5_ifc_create_rmp_out_bits {
6362 u8 reserved_at_8[0x18];
6366 u8 reserved_at_40[0x8];
6369 u8 reserved_at_60[0x20];
6372 struct mlx5_ifc_create_rmp_in_bits {
6374 u8 reserved_at_10[0x10];
6376 u8 reserved_at_20[0x10];
6379 u8 reserved_at_40[0xc0];
6381 struct mlx5_ifc_rmpc_bits ctx;
6384 struct mlx5_ifc_create_qp_out_bits {
6386 u8 reserved_at_8[0x18];
6390 u8 reserved_at_40[0x8];
6393 u8 reserved_at_60[0x20];
6396 struct mlx5_ifc_create_qp_in_bits {
6398 u8 reserved_at_10[0x10];
6400 u8 reserved_at_20[0x10];
6403 u8 reserved_at_40[0x40];
6405 u8 opt_param_mask[0x20];
6407 u8 reserved_at_a0[0x20];
6409 struct mlx5_ifc_qpc_bits qpc;
6411 u8 reserved_at_800[0x80];
6416 struct mlx5_ifc_create_psv_out_bits {
6418 u8 reserved_at_8[0x18];
6422 u8 reserved_at_40[0x40];
6424 u8 reserved_at_80[0x8];
6425 u8 psv0_index[0x18];
6427 u8 reserved_at_a0[0x8];
6428 u8 psv1_index[0x18];
6430 u8 reserved_at_c0[0x8];
6431 u8 psv2_index[0x18];
6433 u8 reserved_at_e0[0x8];
6434 u8 psv3_index[0x18];
6437 struct mlx5_ifc_create_psv_in_bits {
6439 u8 reserved_at_10[0x10];
6441 u8 reserved_at_20[0x10];
6445 u8 reserved_at_44[0x4];
6448 u8 reserved_at_60[0x20];
6451 struct mlx5_ifc_create_mkey_out_bits {
6453 u8 reserved_at_8[0x18];
6457 u8 reserved_at_40[0x8];
6458 u8 mkey_index[0x18];
6460 u8 reserved_at_60[0x20];
6463 struct mlx5_ifc_create_mkey_in_bits {
6465 u8 reserved_at_10[0x10];
6467 u8 reserved_at_20[0x10];
6470 u8 reserved_at_40[0x20];
6473 u8 reserved_at_61[0x1f];
6475 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6477 u8 reserved_at_280[0x80];
6479 u8 translations_octword_actual_size[0x20];
6481 u8 reserved_at_320[0x560];
6483 u8 klm_pas_mtt[0][0x20];
6486 struct mlx5_ifc_create_flow_table_out_bits {
6488 u8 reserved_at_8[0x18];
6492 u8 reserved_at_40[0x8];
6495 u8 reserved_at_60[0x20];
6498 struct mlx5_ifc_create_flow_table_in_bits {
6500 u8 reserved_at_10[0x10];
6502 u8 reserved_at_20[0x10];
6505 u8 other_vport[0x1];
6506 u8 reserved_at_41[0xf];
6507 u8 vport_number[0x10];
6509 u8 reserved_at_60[0x20];
6512 u8 reserved_at_88[0x18];
6514 u8 reserved_at_a0[0x20];
6518 u8 reserved_at_c2[0x2];
6519 u8 table_miss_mode[0x4];
6521 u8 reserved_at_d0[0x8];
6524 u8 reserved_at_e0[0x8];
6525 u8 table_miss_id[0x18];
6527 u8 reserved_at_100[0x8];
6528 u8 lag_master_next_table_id[0x18];
6530 u8 reserved_at_120[0x80];
6533 struct mlx5_ifc_create_flow_group_out_bits {
6535 u8 reserved_at_8[0x18];
6539 u8 reserved_at_40[0x8];
6542 u8 reserved_at_60[0x20];
6546 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6547 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6548 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6551 struct mlx5_ifc_create_flow_group_in_bits {
6553 u8 reserved_at_10[0x10];
6555 u8 reserved_at_20[0x10];
6558 u8 other_vport[0x1];
6559 u8 reserved_at_41[0xf];
6560 u8 vport_number[0x10];
6562 u8 reserved_at_60[0x20];
6565 u8 reserved_at_88[0x18];
6567 u8 reserved_at_a0[0x8];
6570 u8 reserved_at_c0[0x20];
6572 u8 start_flow_index[0x20];
6574 u8 reserved_at_100[0x20];
6576 u8 end_flow_index[0x20];
6578 u8 reserved_at_140[0xa0];
6580 u8 reserved_at_1e0[0x18];
6581 u8 match_criteria_enable[0x8];
6583 struct mlx5_ifc_fte_match_param_bits match_criteria;
6585 u8 reserved_at_1200[0xe00];
6588 struct mlx5_ifc_create_eq_out_bits {
6590 u8 reserved_at_8[0x18];
6594 u8 reserved_at_40[0x18];
6597 u8 reserved_at_60[0x20];
6600 struct mlx5_ifc_create_eq_in_bits {
6602 u8 reserved_at_10[0x10];
6604 u8 reserved_at_20[0x10];
6607 u8 reserved_at_40[0x40];
6609 struct mlx5_ifc_eqc_bits eq_context_entry;
6611 u8 reserved_at_280[0x40];
6613 u8 event_bitmask[0x40];
6615 u8 reserved_at_300[0x580];
6620 struct mlx5_ifc_create_dct_out_bits {
6622 u8 reserved_at_8[0x18];
6626 u8 reserved_at_40[0x8];
6629 u8 reserved_at_60[0x20];
6632 struct mlx5_ifc_create_dct_in_bits {
6634 u8 reserved_at_10[0x10];
6636 u8 reserved_at_20[0x10];
6639 u8 reserved_at_40[0x40];
6641 struct mlx5_ifc_dctc_bits dct_context_entry;
6643 u8 reserved_at_280[0x180];
6646 struct mlx5_ifc_create_cq_out_bits {
6648 u8 reserved_at_8[0x18];
6652 u8 reserved_at_40[0x8];
6655 u8 reserved_at_60[0x20];
6658 struct mlx5_ifc_create_cq_in_bits {
6660 u8 reserved_at_10[0x10];
6662 u8 reserved_at_20[0x10];
6665 u8 reserved_at_40[0x40];
6667 struct mlx5_ifc_cqc_bits cq_context;
6669 u8 reserved_at_280[0x600];
6674 struct mlx5_ifc_config_int_moderation_out_bits {
6676 u8 reserved_at_8[0x18];
6680 u8 reserved_at_40[0x4];
6682 u8 int_vector[0x10];
6684 u8 reserved_at_60[0x20];
6688 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6689 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6692 struct mlx5_ifc_config_int_moderation_in_bits {
6694 u8 reserved_at_10[0x10];
6696 u8 reserved_at_20[0x10];
6699 u8 reserved_at_40[0x4];
6701 u8 int_vector[0x10];
6703 u8 reserved_at_60[0x20];
6706 struct mlx5_ifc_attach_to_mcg_out_bits {
6708 u8 reserved_at_8[0x18];
6712 u8 reserved_at_40[0x40];
6715 struct mlx5_ifc_attach_to_mcg_in_bits {
6717 u8 reserved_at_10[0x10];
6719 u8 reserved_at_20[0x10];
6722 u8 reserved_at_40[0x8];
6725 u8 reserved_at_60[0x20];
6727 u8 multicast_gid[16][0x8];
6730 struct mlx5_ifc_arm_xrq_out_bits {
6732 u8 reserved_at_8[0x18];
6736 u8 reserved_at_40[0x40];
6739 struct mlx5_ifc_arm_xrq_in_bits {
6741 u8 reserved_at_10[0x10];
6743 u8 reserved_at_20[0x10];
6746 u8 reserved_at_40[0x8];
6749 u8 reserved_at_60[0x10];
6753 struct mlx5_ifc_arm_xrc_srq_out_bits {
6755 u8 reserved_at_8[0x18];
6759 u8 reserved_at_40[0x40];
6763 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6766 struct mlx5_ifc_arm_xrc_srq_in_bits {
6768 u8 reserved_at_10[0x10];
6770 u8 reserved_at_20[0x10];
6773 u8 reserved_at_40[0x8];
6776 u8 reserved_at_60[0x10];
6780 struct mlx5_ifc_arm_rq_out_bits {
6782 u8 reserved_at_8[0x18];
6786 u8 reserved_at_40[0x40];
6790 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6791 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6794 struct mlx5_ifc_arm_rq_in_bits {
6796 u8 reserved_at_10[0x10];
6798 u8 reserved_at_20[0x10];
6801 u8 reserved_at_40[0x8];
6802 u8 srq_number[0x18];
6804 u8 reserved_at_60[0x10];
6808 struct mlx5_ifc_arm_dct_out_bits {
6810 u8 reserved_at_8[0x18];
6814 u8 reserved_at_40[0x40];
6817 struct mlx5_ifc_arm_dct_in_bits {
6819 u8 reserved_at_10[0x10];
6821 u8 reserved_at_20[0x10];
6824 u8 reserved_at_40[0x8];
6825 u8 dct_number[0x18];
6827 u8 reserved_at_60[0x20];
6830 struct mlx5_ifc_alloc_xrcd_out_bits {
6832 u8 reserved_at_8[0x18];
6836 u8 reserved_at_40[0x8];
6839 u8 reserved_at_60[0x20];
6842 struct mlx5_ifc_alloc_xrcd_in_bits {
6844 u8 reserved_at_10[0x10];
6846 u8 reserved_at_20[0x10];
6849 u8 reserved_at_40[0x40];
6852 struct mlx5_ifc_alloc_uar_out_bits {
6854 u8 reserved_at_8[0x18];
6858 u8 reserved_at_40[0x8];
6861 u8 reserved_at_60[0x20];
6864 struct mlx5_ifc_alloc_uar_in_bits {
6866 u8 reserved_at_10[0x10];
6868 u8 reserved_at_20[0x10];
6871 u8 reserved_at_40[0x40];
6874 struct mlx5_ifc_alloc_transport_domain_out_bits {
6876 u8 reserved_at_8[0x18];
6880 u8 reserved_at_40[0x8];
6881 u8 transport_domain[0x18];
6883 u8 reserved_at_60[0x20];
6886 struct mlx5_ifc_alloc_transport_domain_in_bits {
6888 u8 reserved_at_10[0x10];
6890 u8 reserved_at_20[0x10];
6893 u8 reserved_at_40[0x40];
6896 struct mlx5_ifc_alloc_q_counter_out_bits {
6898 u8 reserved_at_8[0x18];
6902 u8 reserved_at_40[0x18];
6903 u8 counter_set_id[0x8];
6905 u8 reserved_at_60[0x20];
6908 struct mlx5_ifc_alloc_q_counter_in_bits {
6910 u8 reserved_at_10[0x10];
6912 u8 reserved_at_20[0x10];
6915 u8 reserved_at_40[0x40];
6918 struct mlx5_ifc_alloc_pd_out_bits {
6920 u8 reserved_at_8[0x18];
6924 u8 reserved_at_40[0x8];
6927 u8 reserved_at_60[0x20];
6930 struct mlx5_ifc_alloc_pd_in_bits {
6932 u8 reserved_at_10[0x10];
6934 u8 reserved_at_20[0x10];
6937 u8 reserved_at_40[0x40];
6940 struct mlx5_ifc_alloc_flow_counter_out_bits {
6942 u8 reserved_at_8[0x18];
6946 u8 reserved_at_40[0x10];
6947 u8 flow_counter_id[0x10];
6949 u8 reserved_at_60[0x20];
6952 struct mlx5_ifc_alloc_flow_counter_in_bits {
6954 u8 reserved_at_10[0x10];
6956 u8 reserved_at_20[0x10];
6959 u8 reserved_at_40[0x40];
6962 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6964 u8 reserved_at_8[0x18];
6968 u8 reserved_at_40[0x40];
6971 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6973 u8 reserved_at_10[0x10];
6975 u8 reserved_at_20[0x10];
6978 u8 reserved_at_40[0x20];
6980 u8 reserved_at_60[0x10];
6981 u8 vxlan_udp_port[0x10];
6984 struct mlx5_ifc_set_rate_limit_out_bits {
6986 u8 reserved_at_8[0x18];
6990 u8 reserved_at_40[0x40];
6993 struct mlx5_ifc_set_rate_limit_in_bits {
6995 u8 reserved_at_10[0x10];
6997 u8 reserved_at_20[0x10];
7000 u8 reserved_at_40[0x10];
7001 u8 rate_limit_index[0x10];
7003 u8 reserved_at_60[0x20];
7005 u8 rate_limit[0x20];
7008 struct mlx5_ifc_access_register_out_bits {
7010 u8 reserved_at_8[0x18];
7014 u8 reserved_at_40[0x40];
7016 u8 register_data[0][0x20];
7020 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7021 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7024 struct mlx5_ifc_access_register_in_bits {
7026 u8 reserved_at_10[0x10];
7028 u8 reserved_at_20[0x10];
7031 u8 reserved_at_40[0x10];
7032 u8 register_id[0x10];
7036 u8 register_data[0][0x20];
7039 struct mlx5_ifc_sltp_reg_bits {
7044 u8 reserved_at_12[0x2];
7046 u8 reserved_at_18[0x8];
7048 u8 reserved_at_20[0x20];
7050 u8 reserved_at_40[0x7];
7056 u8 reserved_at_60[0xc];
7057 u8 ob_preemp_mode[0x4];
7061 u8 reserved_at_80[0x20];
7064 struct mlx5_ifc_slrg_reg_bits {
7069 u8 reserved_at_12[0x2];
7071 u8 reserved_at_18[0x8];
7073 u8 time_to_link_up[0x10];
7074 u8 reserved_at_30[0xc];
7075 u8 grade_lane_speed[0x4];
7077 u8 grade_version[0x8];
7080 u8 reserved_at_60[0x4];
7081 u8 height_grade_type[0x4];
7082 u8 height_grade[0x18];
7087 u8 reserved_at_a0[0x10];
7088 u8 height_sigma[0x10];
7090 u8 reserved_at_c0[0x20];
7092 u8 reserved_at_e0[0x4];
7093 u8 phase_grade_type[0x4];
7094 u8 phase_grade[0x18];
7096 u8 reserved_at_100[0x8];
7097 u8 phase_eo_pos[0x8];
7098 u8 reserved_at_110[0x8];
7099 u8 phase_eo_neg[0x8];
7101 u8 ffe_set_tested[0x10];
7102 u8 test_errors_per_lane[0x10];
7105 struct mlx5_ifc_pvlc_reg_bits {
7106 u8 reserved_at_0[0x8];
7108 u8 reserved_at_10[0x10];
7110 u8 reserved_at_20[0x1c];
7113 u8 reserved_at_40[0x1c];
7116 u8 reserved_at_60[0x1c];
7117 u8 vl_operational[0x4];
7120 struct mlx5_ifc_pude_reg_bits {
7123 u8 reserved_at_10[0x4];
7124 u8 admin_status[0x4];
7125 u8 reserved_at_18[0x4];
7126 u8 oper_status[0x4];
7128 u8 reserved_at_20[0x60];
7131 struct mlx5_ifc_ptys_reg_bits {
7132 u8 reserved_at_0[0x1];
7133 u8 an_disable_admin[0x1];
7134 u8 an_disable_cap[0x1];
7135 u8 reserved_at_3[0x5];
7137 u8 reserved_at_10[0xd];
7141 u8 reserved_at_24[0x3c];
7143 u8 eth_proto_capability[0x20];
7145 u8 ib_link_width_capability[0x10];
7146 u8 ib_proto_capability[0x10];
7148 u8 reserved_at_a0[0x20];
7150 u8 eth_proto_admin[0x20];
7152 u8 ib_link_width_admin[0x10];
7153 u8 ib_proto_admin[0x10];
7155 u8 reserved_at_100[0x20];
7157 u8 eth_proto_oper[0x20];
7159 u8 ib_link_width_oper[0x10];
7160 u8 ib_proto_oper[0x10];
7162 u8 reserved_at_160[0x20];
7164 u8 eth_proto_lp_advertise[0x20];
7166 u8 reserved_at_1a0[0x60];
7169 struct mlx5_ifc_mlcr_reg_bits {
7170 u8 reserved_at_0[0x8];
7172 u8 reserved_at_10[0x20];
7174 u8 beacon_duration[0x10];
7175 u8 reserved_at_40[0x10];
7177 u8 beacon_remain[0x10];
7180 struct mlx5_ifc_ptas_reg_bits {
7181 u8 reserved_at_0[0x20];
7183 u8 algorithm_options[0x10];
7184 u8 reserved_at_30[0x4];
7185 u8 repetitions_mode[0x4];
7186 u8 num_of_repetitions[0x8];
7188 u8 grade_version[0x8];
7189 u8 height_grade_type[0x4];
7190 u8 phase_grade_type[0x4];
7191 u8 height_grade_weight[0x8];
7192 u8 phase_grade_weight[0x8];
7194 u8 gisim_measure_bits[0x10];
7195 u8 adaptive_tap_measure_bits[0x10];
7197 u8 ber_bath_high_error_threshold[0x10];
7198 u8 ber_bath_mid_error_threshold[0x10];
7200 u8 ber_bath_low_error_threshold[0x10];
7201 u8 one_ratio_high_threshold[0x10];
7203 u8 one_ratio_high_mid_threshold[0x10];
7204 u8 one_ratio_low_mid_threshold[0x10];
7206 u8 one_ratio_low_threshold[0x10];
7207 u8 ndeo_error_threshold[0x10];
7209 u8 mixer_offset_step_size[0x10];
7210 u8 reserved_at_110[0x8];
7211 u8 mix90_phase_for_voltage_bath[0x8];
7213 u8 mixer_offset_start[0x10];
7214 u8 mixer_offset_end[0x10];
7216 u8 reserved_at_140[0x15];
7217 u8 ber_test_time[0xb];
7220 struct mlx5_ifc_pspa_reg_bits {
7224 u8 reserved_at_18[0x8];
7226 u8 reserved_at_20[0x20];
7229 struct mlx5_ifc_pqdr_reg_bits {
7230 u8 reserved_at_0[0x8];
7232 u8 reserved_at_10[0x5];
7234 u8 reserved_at_18[0x6];
7237 u8 reserved_at_20[0x20];
7239 u8 reserved_at_40[0x10];
7240 u8 min_threshold[0x10];
7242 u8 reserved_at_60[0x10];
7243 u8 max_threshold[0x10];
7245 u8 reserved_at_80[0x10];
7246 u8 mark_probability_denominator[0x10];
7248 u8 reserved_at_a0[0x60];
7251 struct mlx5_ifc_ppsc_reg_bits {
7252 u8 reserved_at_0[0x8];
7254 u8 reserved_at_10[0x10];
7256 u8 reserved_at_20[0x60];
7258 u8 reserved_at_80[0x1c];
7261 u8 reserved_at_a0[0x1c];
7262 u8 wrps_status[0x4];
7264 u8 reserved_at_c0[0x8];
7265 u8 up_threshold[0x8];
7266 u8 reserved_at_d0[0x8];
7267 u8 down_threshold[0x8];
7269 u8 reserved_at_e0[0x20];
7271 u8 reserved_at_100[0x1c];
7274 u8 reserved_at_120[0x1c];
7275 u8 srps_status[0x4];
7277 u8 reserved_at_140[0x40];
7280 struct mlx5_ifc_pplr_reg_bits {
7281 u8 reserved_at_0[0x8];
7283 u8 reserved_at_10[0x10];
7285 u8 reserved_at_20[0x8];
7287 u8 reserved_at_30[0x8];
7291 struct mlx5_ifc_pplm_reg_bits {
7292 u8 reserved_at_0[0x8];
7294 u8 reserved_at_10[0x10];
7296 u8 reserved_at_20[0x20];
7298 u8 port_profile_mode[0x8];
7299 u8 static_port_profile[0x8];
7300 u8 active_port_profile[0x8];
7301 u8 reserved_at_58[0x8];
7303 u8 retransmission_active[0x8];
7304 u8 fec_mode_active[0x18];
7306 u8 reserved_at_80[0x20];
7309 struct mlx5_ifc_ppcnt_reg_bits {
7313 u8 reserved_at_12[0x8];
7317 u8 reserved_at_21[0x1c];
7320 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7323 struct mlx5_ifc_mpcnt_reg_bits {
7324 u8 reserved_at_0[0x8];
7326 u8 reserved_at_10[0xa];
7330 u8 reserved_at_21[0x1f];
7332 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7335 struct mlx5_ifc_ppad_reg_bits {
7336 u8 reserved_at_0[0x3];
7338 u8 reserved_at_4[0x4];
7344 u8 reserved_at_40[0x40];
7347 struct mlx5_ifc_pmtu_reg_bits {
7348 u8 reserved_at_0[0x8];
7350 u8 reserved_at_10[0x10];
7353 u8 reserved_at_30[0x10];
7356 u8 reserved_at_50[0x10];
7359 u8 reserved_at_70[0x10];
7362 struct mlx5_ifc_pmpr_reg_bits {
7363 u8 reserved_at_0[0x8];
7365 u8 reserved_at_10[0x10];
7367 u8 reserved_at_20[0x18];
7368 u8 attenuation_5g[0x8];
7370 u8 reserved_at_40[0x18];
7371 u8 attenuation_7g[0x8];
7373 u8 reserved_at_60[0x18];
7374 u8 attenuation_12g[0x8];
7377 struct mlx5_ifc_pmpe_reg_bits {
7378 u8 reserved_at_0[0x8];
7380 u8 reserved_at_10[0xc];
7381 u8 module_status[0x4];
7383 u8 reserved_at_20[0x60];
7386 struct mlx5_ifc_pmpc_reg_bits {
7387 u8 module_state_updated[32][0x8];
7390 struct mlx5_ifc_pmlpn_reg_bits {
7391 u8 reserved_at_0[0x4];
7392 u8 mlpn_status[0x4];
7394 u8 reserved_at_10[0x10];
7397 u8 reserved_at_21[0x1f];
7400 struct mlx5_ifc_pmlp_reg_bits {
7402 u8 reserved_at_1[0x7];
7404 u8 reserved_at_10[0x8];
7407 u8 lane0_module_mapping[0x20];
7409 u8 lane1_module_mapping[0x20];
7411 u8 lane2_module_mapping[0x20];
7413 u8 lane3_module_mapping[0x20];
7415 u8 reserved_at_a0[0x160];
7418 struct mlx5_ifc_pmaos_reg_bits {
7419 u8 reserved_at_0[0x8];
7421 u8 reserved_at_10[0x4];
7422 u8 admin_status[0x4];
7423 u8 reserved_at_18[0x4];
7424 u8 oper_status[0x4];
7428 u8 reserved_at_22[0x1c];
7431 u8 reserved_at_40[0x40];
7434 struct mlx5_ifc_plpc_reg_bits {
7435 u8 reserved_at_0[0x4];
7437 u8 reserved_at_10[0x4];
7439 u8 reserved_at_18[0x8];
7441 u8 reserved_at_20[0x10];
7442 u8 lane_speed[0x10];
7444 u8 reserved_at_40[0x17];
7446 u8 fec_mode_policy[0x8];
7448 u8 retransmission_capability[0x8];
7449 u8 fec_mode_capability[0x18];
7451 u8 retransmission_support_admin[0x8];
7452 u8 fec_mode_support_admin[0x18];
7454 u8 retransmission_request_admin[0x8];
7455 u8 fec_mode_request_admin[0x18];
7457 u8 reserved_at_c0[0x80];
7460 struct mlx5_ifc_plib_reg_bits {
7461 u8 reserved_at_0[0x8];
7463 u8 reserved_at_10[0x8];
7466 u8 reserved_at_20[0x60];
7469 struct mlx5_ifc_plbf_reg_bits {
7470 u8 reserved_at_0[0x8];
7472 u8 reserved_at_10[0xd];
7475 u8 reserved_at_20[0x20];
7478 struct mlx5_ifc_pipg_reg_bits {
7479 u8 reserved_at_0[0x8];
7481 u8 reserved_at_10[0x10];
7484 u8 reserved_at_21[0x19];
7486 u8 reserved_at_3e[0x2];
7489 struct mlx5_ifc_pifr_reg_bits {
7490 u8 reserved_at_0[0x8];
7492 u8 reserved_at_10[0x10];
7494 u8 reserved_at_20[0xe0];
7496 u8 port_filter[8][0x20];
7498 u8 port_filter_update_en[8][0x20];
7501 struct mlx5_ifc_pfcc_reg_bits {
7502 u8 reserved_at_0[0x8];
7504 u8 reserved_at_10[0x10];
7507 u8 reserved_at_24[0x4];
7508 u8 prio_mask_tx[0x8];
7509 u8 reserved_at_30[0x8];
7510 u8 prio_mask_rx[0x8];
7514 u8 reserved_at_42[0x6];
7516 u8 reserved_at_50[0x10];
7520 u8 reserved_at_62[0x6];
7522 u8 reserved_at_70[0x10];
7524 u8 reserved_at_80[0x80];
7527 struct mlx5_ifc_pelc_reg_bits {
7529 u8 reserved_at_4[0x4];
7531 u8 reserved_at_10[0x10];
7534 u8 op_capability[0x8];
7540 u8 capability[0x40];
7546 u8 reserved_at_140[0x80];
7549 struct mlx5_ifc_peir_reg_bits {
7550 u8 reserved_at_0[0x8];
7552 u8 reserved_at_10[0x10];
7554 u8 reserved_at_20[0xc];
7555 u8 error_count[0x4];
7556 u8 reserved_at_30[0x10];
7558 u8 reserved_at_40[0xc];
7560 u8 reserved_at_50[0x8];
7564 struct mlx5_ifc_pcap_reg_bits {
7565 u8 reserved_at_0[0x8];
7567 u8 reserved_at_10[0x10];
7569 u8 port_capability_mask[4][0x20];
7572 struct mlx5_ifc_paos_reg_bits {
7575 u8 reserved_at_10[0x4];
7576 u8 admin_status[0x4];
7577 u8 reserved_at_18[0x4];
7578 u8 oper_status[0x4];
7582 u8 reserved_at_22[0x1c];
7585 u8 reserved_at_40[0x40];
7588 struct mlx5_ifc_pamp_reg_bits {
7589 u8 reserved_at_0[0x8];
7590 u8 opamp_group[0x8];
7591 u8 reserved_at_10[0xc];
7592 u8 opamp_group_type[0x4];
7594 u8 start_index[0x10];
7595 u8 reserved_at_30[0x4];
7596 u8 num_of_indices[0xc];
7598 u8 index_data[18][0x10];
7601 struct mlx5_ifc_pcmr_reg_bits {
7602 u8 reserved_at_0[0x8];
7604 u8 reserved_at_10[0x2e];
7606 u8 reserved_at_3f[0x1f];
7608 u8 reserved_at_5f[0x1];
7611 struct mlx5_ifc_lane_2_module_mapping_bits {
7612 u8 reserved_at_0[0x6];
7614 u8 reserved_at_8[0x6];
7616 u8 reserved_at_10[0x8];
7620 struct mlx5_ifc_bufferx_reg_bits {
7621 u8 reserved_at_0[0x6];
7624 u8 reserved_at_8[0xc];
7627 u8 xoff_threshold[0x10];
7628 u8 xon_threshold[0x10];
7631 struct mlx5_ifc_set_node_in_bits {
7632 u8 node_description[64][0x8];
7635 struct mlx5_ifc_register_power_settings_bits {
7636 u8 reserved_at_0[0x18];
7637 u8 power_settings_level[0x8];
7639 u8 reserved_at_20[0x60];
7642 struct mlx5_ifc_register_host_endianness_bits {
7644 u8 reserved_at_1[0x1f];
7646 u8 reserved_at_20[0x60];
7649 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7650 u8 reserved_at_0[0x20];
7654 u8 addressh_63_32[0x20];
7656 u8 addressl_31_0[0x20];
7659 struct mlx5_ifc_ud_adrs_vector_bits {
7663 u8 reserved_at_41[0x7];
7664 u8 destination_qp_dct[0x18];
7666 u8 static_rate[0x4];
7667 u8 sl_eth_prio[0x4];
7670 u8 rlid_udp_sport[0x10];
7672 u8 reserved_at_80[0x20];
7674 u8 rmac_47_16[0x20];
7680 u8 reserved_at_e0[0x1];
7682 u8 reserved_at_e2[0x2];
7683 u8 src_addr_index[0x8];
7684 u8 flow_label[0x14];
7686 u8 rgid_rip[16][0x8];
7689 struct mlx5_ifc_pages_req_event_bits {
7690 u8 reserved_at_0[0x10];
7691 u8 function_id[0x10];
7695 u8 reserved_at_40[0xa0];
7698 struct mlx5_ifc_eqe_bits {
7699 u8 reserved_at_0[0x8];
7701 u8 reserved_at_10[0x8];
7702 u8 event_sub_type[0x8];
7704 u8 reserved_at_20[0xe0];
7706 union mlx5_ifc_event_auto_bits event_data;
7708 u8 reserved_at_1e0[0x10];
7710 u8 reserved_at_1f8[0x7];
7715 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7718 struct mlx5_ifc_cmd_queue_entry_bits {
7720 u8 reserved_at_8[0x18];
7722 u8 input_length[0x20];
7724 u8 input_mailbox_pointer_63_32[0x20];
7726 u8 input_mailbox_pointer_31_9[0x17];
7727 u8 reserved_at_77[0x9];
7729 u8 command_input_inline_data[16][0x8];
7731 u8 command_output_inline_data[16][0x8];
7733 u8 output_mailbox_pointer_63_32[0x20];
7735 u8 output_mailbox_pointer_31_9[0x17];
7736 u8 reserved_at_1b7[0x9];
7738 u8 output_length[0x20];
7742 u8 reserved_at_1f0[0x8];
7747 struct mlx5_ifc_cmd_out_bits {
7749 u8 reserved_at_8[0x18];
7753 u8 command_output[0x20];
7756 struct mlx5_ifc_cmd_in_bits {
7758 u8 reserved_at_10[0x10];
7760 u8 reserved_at_20[0x10];
7763 u8 command[0][0x20];
7766 struct mlx5_ifc_cmd_if_box_bits {
7767 u8 mailbox_data[512][0x8];
7769 u8 reserved_at_1000[0x180];
7771 u8 next_pointer_63_32[0x20];
7773 u8 next_pointer_31_10[0x16];
7774 u8 reserved_at_11b6[0xa];
7776 u8 block_number[0x20];
7778 u8 reserved_at_11e0[0x8];
7780 u8 ctrl_signature[0x8];
7784 struct mlx5_ifc_mtt_bits {
7785 u8 ptag_63_32[0x20];
7788 u8 reserved_at_38[0x6];
7793 struct mlx5_ifc_query_wol_rol_out_bits {
7795 u8 reserved_at_8[0x18];
7799 u8 reserved_at_40[0x10];
7803 u8 reserved_at_60[0x20];
7806 struct mlx5_ifc_query_wol_rol_in_bits {
7808 u8 reserved_at_10[0x10];
7810 u8 reserved_at_20[0x10];
7813 u8 reserved_at_40[0x40];
7816 struct mlx5_ifc_set_wol_rol_out_bits {
7818 u8 reserved_at_8[0x18];
7822 u8 reserved_at_40[0x40];
7825 struct mlx5_ifc_set_wol_rol_in_bits {
7827 u8 reserved_at_10[0x10];
7829 u8 reserved_at_20[0x10];
7832 u8 rol_mode_valid[0x1];
7833 u8 wol_mode_valid[0x1];
7834 u8 reserved_at_42[0xe];
7838 u8 reserved_at_60[0x20];
7842 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7843 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7844 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7848 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7849 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7850 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7854 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7855 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7856 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7857 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7858 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7859 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7860 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7861 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7862 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7863 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7864 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7867 struct mlx5_ifc_initial_seg_bits {
7868 u8 fw_rev_minor[0x10];
7869 u8 fw_rev_major[0x10];
7871 u8 cmd_interface_rev[0x10];
7872 u8 fw_rev_subminor[0x10];
7874 u8 reserved_at_40[0x40];
7876 u8 cmdq_phy_addr_63_32[0x20];
7878 u8 cmdq_phy_addr_31_12[0x14];
7879 u8 reserved_at_b4[0x2];
7880 u8 nic_interface[0x2];
7881 u8 log_cmdq_size[0x4];
7882 u8 log_cmdq_stride[0x4];
7884 u8 command_doorbell_vector[0x20];
7886 u8 reserved_at_e0[0xf00];
7888 u8 initializing[0x1];
7889 u8 reserved_at_fe1[0x4];
7890 u8 nic_interface_supported[0x3];
7891 u8 reserved_at_fe8[0x18];
7893 struct mlx5_ifc_health_buffer_bits health_buffer;
7895 u8 no_dram_nic_offset[0x20];
7897 u8 reserved_at_1220[0x6e40];
7899 u8 reserved_at_8060[0x1f];
7902 u8 health_syndrome[0x8];
7903 u8 health_counter[0x18];
7905 u8 reserved_at_80a0[0x17fc0];
7908 union mlx5_ifc_ports_control_registers_document_bits {
7909 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7910 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7911 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7912 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7913 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7914 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7915 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7916 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7917 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7918 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7919 struct mlx5_ifc_paos_reg_bits paos_reg;
7920 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7921 struct mlx5_ifc_peir_reg_bits peir_reg;
7922 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7923 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7924 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7925 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7926 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7927 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7928 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7929 struct mlx5_ifc_plib_reg_bits plib_reg;
7930 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7931 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7932 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7933 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7934 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7935 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7936 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7937 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7938 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7939 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7940 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
7941 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7942 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7943 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7944 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7945 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7946 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7947 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7948 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7949 struct mlx5_ifc_pude_reg_bits pude_reg;
7950 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7951 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7952 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7953 u8 reserved_at_0[0x60e0];
7956 union mlx5_ifc_debug_enhancements_document_bits {
7957 struct mlx5_ifc_health_buffer_bits health_buffer;
7958 u8 reserved_at_0[0x200];
7961 union mlx5_ifc_uplink_pci_interface_document_bits {
7962 struct mlx5_ifc_initial_seg_bits initial_seg;
7963 u8 reserved_at_0[0x20060];
7966 struct mlx5_ifc_set_flow_table_root_out_bits {
7968 u8 reserved_at_8[0x18];
7972 u8 reserved_at_40[0x40];
7975 struct mlx5_ifc_set_flow_table_root_in_bits {
7977 u8 reserved_at_10[0x10];
7979 u8 reserved_at_20[0x10];
7982 u8 other_vport[0x1];
7983 u8 reserved_at_41[0xf];
7984 u8 vport_number[0x10];
7986 u8 reserved_at_60[0x20];
7989 u8 reserved_at_88[0x18];
7991 u8 reserved_at_a0[0x8];
7994 u8 reserved_at_c0[0x140];
7998 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7999 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8002 struct mlx5_ifc_modify_flow_table_out_bits {
8004 u8 reserved_at_8[0x18];
8008 u8 reserved_at_40[0x40];
8011 struct mlx5_ifc_modify_flow_table_in_bits {
8013 u8 reserved_at_10[0x10];
8015 u8 reserved_at_20[0x10];
8018 u8 other_vport[0x1];
8019 u8 reserved_at_41[0xf];
8020 u8 vport_number[0x10];
8022 u8 reserved_at_60[0x10];
8023 u8 modify_field_select[0x10];
8026 u8 reserved_at_88[0x18];
8028 u8 reserved_at_a0[0x8];
8031 u8 reserved_at_c0[0x4];
8032 u8 table_miss_mode[0x4];
8033 u8 reserved_at_c8[0x18];
8035 u8 reserved_at_e0[0x8];
8036 u8 table_miss_id[0x18];
8038 u8 reserved_at_100[0x8];
8039 u8 lag_master_next_table_id[0x18];
8041 u8 reserved_at_120[0x80];
8044 struct mlx5_ifc_ets_tcn_config_reg_bits {
8048 u8 reserved_at_3[0x9];
8050 u8 reserved_at_10[0x9];
8051 u8 bw_allocation[0x7];
8053 u8 reserved_at_20[0xc];
8054 u8 max_bw_units[0x4];
8055 u8 reserved_at_30[0x8];
8056 u8 max_bw_value[0x8];
8059 struct mlx5_ifc_ets_global_config_reg_bits {
8060 u8 reserved_at_0[0x2];
8062 u8 reserved_at_3[0x1d];
8064 u8 reserved_at_20[0xc];
8065 u8 max_bw_units[0x4];
8066 u8 reserved_at_30[0x8];
8067 u8 max_bw_value[0x8];
8070 struct mlx5_ifc_qetc_reg_bits {
8071 u8 reserved_at_0[0x8];
8072 u8 port_number[0x8];
8073 u8 reserved_at_10[0x30];
8075 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8076 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8079 struct mlx5_ifc_qtct_reg_bits {
8080 u8 reserved_at_0[0x8];
8081 u8 port_number[0x8];
8082 u8 reserved_at_10[0xd];
8085 u8 reserved_at_20[0x1d];
8089 struct mlx5_ifc_mcia_reg_bits {
8091 u8 reserved_at_1[0x7];
8093 u8 reserved_at_10[0x8];
8096 u8 i2c_device_address[0x8];
8097 u8 page_number[0x8];
8098 u8 device_address[0x10];
8100 u8 reserved_at_40[0x10];
8103 u8 reserved_at_60[0x20];
8119 struct mlx5_ifc_dcbx_param_bits {
8120 u8 dcbx_cee_cap[0x1];
8121 u8 dcbx_ieee_cap[0x1];
8122 u8 dcbx_standby_cap[0x1];
8123 u8 reserved_at_0[0x5];
8124 u8 port_number[0x8];
8125 u8 reserved_at_10[0xa];
8126 u8 max_application_table_size[6];
8127 u8 reserved_at_20[0x15];
8128 u8 version_oper[0x3];
8129 u8 reserved_at_38[5];
8130 u8 version_admin[0x3];
8131 u8 willing_admin[0x1];
8132 u8 reserved_at_41[0x3];
8133 u8 pfc_cap_oper[0x4];
8134 u8 reserved_at_48[0x4];
8135 u8 pfc_cap_admin[0x4];
8136 u8 reserved_at_50[0x4];
8137 u8 num_of_tc_oper[0x4];
8138 u8 reserved_at_58[0x4];
8139 u8 num_of_tc_admin[0x4];
8140 u8 remote_willing[0x1];
8141 u8 reserved_at_61[3];
8142 u8 remote_pfc_cap[4];
8143 u8 reserved_at_68[0x14];
8144 u8 remote_num_of_tc[0x4];
8145 u8 reserved_at_80[0x18];
8147 u8 reserved_at_a0[0x160];
8150 struct mlx5_ifc_lagc_bits {
8151 u8 reserved_at_0[0x1d];
8154 u8 reserved_at_20[0x14];
8155 u8 tx_remap_affinity_2[0x4];
8156 u8 reserved_at_38[0x4];
8157 u8 tx_remap_affinity_1[0x4];
8160 struct mlx5_ifc_create_lag_out_bits {
8162 u8 reserved_at_8[0x18];
8166 u8 reserved_at_40[0x40];
8169 struct mlx5_ifc_create_lag_in_bits {
8171 u8 reserved_at_10[0x10];
8173 u8 reserved_at_20[0x10];
8176 struct mlx5_ifc_lagc_bits ctx;
8179 struct mlx5_ifc_modify_lag_out_bits {
8181 u8 reserved_at_8[0x18];
8185 u8 reserved_at_40[0x40];
8188 struct mlx5_ifc_modify_lag_in_bits {
8190 u8 reserved_at_10[0x10];
8192 u8 reserved_at_20[0x10];
8195 u8 reserved_at_40[0x20];
8196 u8 field_select[0x20];
8198 struct mlx5_ifc_lagc_bits ctx;
8201 struct mlx5_ifc_query_lag_out_bits {
8203 u8 reserved_at_8[0x18];
8207 u8 reserved_at_40[0x40];
8209 struct mlx5_ifc_lagc_bits ctx;
8212 struct mlx5_ifc_query_lag_in_bits {
8214 u8 reserved_at_10[0x10];
8216 u8 reserved_at_20[0x10];
8219 u8 reserved_at_40[0x40];
8222 struct mlx5_ifc_destroy_lag_out_bits {
8224 u8 reserved_at_8[0x18];
8228 u8 reserved_at_40[0x40];
8231 struct mlx5_ifc_destroy_lag_in_bits {
8233 u8 reserved_at_10[0x10];
8235 u8 reserved_at_20[0x10];
8238 u8 reserved_at_40[0x40];
8241 struct mlx5_ifc_create_vport_lag_out_bits {
8243 u8 reserved_at_8[0x18];
8247 u8 reserved_at_40[0x40];
8250 struct mlx5_ifc_create_vport_lag_in_bits {
8252 u8 reserved_at_10[0x10];
8254 u8 reserved_at_20[0x10];
8257 u8 reserved_at_40[0x40];
8260 struct mlx5_ifc_destroy_vport_lag_out_bits {
8262 u8 reserved_at_8[0x18];
8266 u8 reserved_at_40[0x40];
8269 struct mlx5_ifc_destroy_vport_lag_in_bits {
8271 u8 reserved_at_10[0x10];
8273 u8 reserved_at_20[0x10];
8276 u8 reserved_at_40[0x40];
8279 #endif /* MLX5_IFC_H */