include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  91 };
  92
  93 enum {
  94         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  95         MLX5_OBJ_TYPE_MKEY = 0xff01,
  96         MLX5_OBJ_TYPE_QP = 0xff02,
  97         MLX5_OBJ_TYPE_PSV = 0xff03,
  98         MLX5_OBJ_TYPE_RMP = 0xff04,
  99         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 100         MLX5_OBJ_TYPE_RQ = 0xff06,
 101         MLX5_OBJ_TYPE_SQ = 0xff07,
 102         MLX5_OBJ_TYPE_TIR = 0xff08,
 103         MLX5_OBJ_TYPE_TIS = 0xff09,
 104         MLX5_OBJ_TYPE_DCT = 0xff0a,
 105         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 106         MLX5_OBJ_TYPE_RQT = 0xff0e,
 107         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 108         MLX5_OBJ_TYPE_CQ = 0xff10,
 109 };
 110
 111 enum {
 112         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 113         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 114         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 115         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 116         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 117         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 118         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 119         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 120         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 121         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 122         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 123         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 124         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 125         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 126         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 127         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 128         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 129         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 130         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 131         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 132         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 133         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 134         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 135         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 136         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 137         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 138         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 139         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 140         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 141         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 142         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 143         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 144         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 145         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 146         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 147         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 148         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 149         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 150         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 151         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 152         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 153         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 154         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 155         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 156         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 157         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 158         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 159         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 160         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 161         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 162         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 163         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 164         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 165         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 166         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 167         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 168         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 169         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 170         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 171         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 172         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 173         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 174         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 175         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 176         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 177         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 178         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 179         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 180         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 181         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 182         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 183         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 184         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 185         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 186         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 188         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 191         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 192         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 193         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 194         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 195         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 196         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 197         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 198         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 199         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 200         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 201         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 202         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 203         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 204         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 205         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 206         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 207         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 208         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 209         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 210         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 211         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 212         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 213         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 214         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 215         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 216         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 217         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 218         MLX5_CMD_OP_NOP                           = 0x80d,
 219         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 220         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 221         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 222         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 223         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 224         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 225         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 226         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 227         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 228         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 229         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 230         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 231         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 232         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 233         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 234         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 235         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 236         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 237         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 238         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 239         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 240         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 241         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 242         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 243         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 244         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 245         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 246         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 247         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 248         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 249         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 250         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 251         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 252         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 253         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 254         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 255         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 256         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 257         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 258         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 259         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 260         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 261         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 262         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 263         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 264         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 265         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 266         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 267         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 268         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 269         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 270         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 271         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 272         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 273         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 274         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 275         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 276         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 277         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 278         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 279         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 280         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 281         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 282         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 283         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 284         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 285         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 286         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 287         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 288         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 289         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 290         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 291         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 292         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 293         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 294         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 295         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 296         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 297         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 298         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 299         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 300         MLX5_CMD_OP_MAX
 301 };
 302
 303 /* Valid range for general commands that don't work over an object */
 304 enum {
 305         MLX5_CMD_OP_GENERAL_START = 0xb00,
 306         MLX5_CMD_OP_GENERAL_END = 0xd00,
 307 };
 308
 309 struct mlx5_ifc_flow_table_fields_supported_bits {
 310         u8         outer_dmac[0x1];
 311         u8         outer_smac[0x1];
 312         u8         outer_ether_type[0x1];
 313         u8         outer_ip_version[0x1];
 314         u8         outer_first_prio[0x1];
 315         u8         outer_first_cfi[0x1];
 316         u8         outer_first_vid[0x1];
 317         u8         outer_ipv4_ttl[0x1];
 318         u8         outer_second_prio[0x1];
 319         u8         outer_second_cfi[0x1];
 320         u8         outer_second_vid[0x1];
 321         u8         reserved_at_b[0x1];
 322         u8         outer_sip[0x1];
 323         u8         outer_dip[0x1];
 324         u8         outer_frag[0x1];
 325         u8         outer_ip_protocol[0x1];
 326         u8         outer_ip_ecn[0x1];
 327         u8         outer_ip_dscp[0x1];
 328         u8         outer_udp_sport[0x1];
 329         u8         outer_udp_dport[0x1];
 330         u8         outer_tcp_sport[0x1];
 331         u8         outer_tcp_dport[0x1];
 332         u8         outer_tcp_flags[0x1];
 333         u8         outer_gre_protocol[0x1];
 334         u8         outer_gre_key[0x1];
 335         u8         outer_vxlan_vni[0x1];
 336         u8         outer_geneve_vni[0x1];
 337         u8         outer_geneve_oam[0x1];
 338         u8         outer_geneve_protocol_type[0x1];
 339         u8         outer_geneve_opt_len[0x1];
 340         u8         reserved_at_1e[0x1];
 341         u8         source_eswitch_port[0x1];
 342
 343         u8         inner_dmac[0x1];
 344         u8         inner_smac[0x1];
 345         u8         inner_ether_type[0x1];
 346         u8         inner_ip_version[0x1];
 347         u8         inner_first_prio[0x1];
 348         u8         inner_first_cfi[0x1];
 349         u8         inner_first_vid[0x1];
 350         u8         reserved_at_27[0x1];
 351         u8         inner_second_prio[0x1];
 352         u8         inner_second_cfi[0x1];
 353         u8         inner_second_vid[0x1];
 354         u8         reserved_at_2b[0x1];
 355         u8         inner_sip[0x1];
 356         u8         inner_dip[0x1];
 357         u8         inner_frag[0x1];
 358         u8         inner_ip_protocol[0x1];
 359         u8         inner_ip_ecn[0x1];
 360         u8         inner_ip_dscp[0x1];
 361         u8         inner_udp_sport[0x1];
 362         u8         inner_udp_dport[0x1];
 363         u8         inner_tcp_sport[0x1];
 364         u8         inner_tcp_dport[0x1];
 365         u8         inner_tcp_flags[0x1];
 366         u8         reserved_at_37[0x9];
 367
 368         u8         geneve_tlv_option_0_data[0x1];
 369         u8         reserved_at_41[0x4];
 370         u8         outer_first_mpls_over_udp[0x4];
 371         u8         outer_first_mpls_over_gre[0x4];
 372         u8         inner_first_mpls[0x4];
 373         u8         outer_first_mpls[0x4];
 374         u8         reserved_at_55[0x2];
 375         u8         outer_esp_spi[0x1];
 376         u8         reserved_at_58[0x2];
 377         u8         bth_dst_qp[0x1];
 378         u8         reserved_at_5b[0x5];
 379
 380         u8         reserved_at_60[0x18];
 381         u8         metadata_reg_c_7[0x1];
 382         u8         metadata_reg_c_6[0x1];
 383         u8         metadata_reg_c_5[0x1];
 384         u8         metadata_reg_c_4[0x1];
 385         u8         metadata_reg_c_3[0x1];
 386         u8         metadata_reg_c_2[0x1];
 387         u8         metadata_reg_c_1[0x1];
 388         u8         metadata_reg_c_0[0x1];
 389 };
 390
 391 struct mlx5_ifc_flow_table_prop_layout_bits {
 392         u8         ft_support[0x1];
 393         u8         reserved_at_1[0x1];
 394         u8         flow_counter[0x1];
 395         u8         flow_modify_en[0x1];
 396         u8         modify_root[0x1];
 397         u8         identified_miss_table_mode[0x1];
 398         u8         flow_table_modify[0x1];
 399         u8         reformat[0x1];
 400         u8         decap[0x1];
 401         u8         reserved_at_9[0x1];
 402         u8         pop_vlan[0x1];
 403         u8         push_vlan[0x1];
 404         u8         reserved_at_c[0x1];
 405         u8         pop_vlan_2[0x1];
 406         u8         push_vlan_2[0x1];
 407         u8         reformat_and_vlan_action[0x1];
 408         u8         reserved_at_10[0x1];
 409         u8         sw_owner[0x1];
 410         u8         reformat_l3_tunnel_to_l2[0x1];
 411         u8         reformat_l2_to_l3_tunnel[0x1];
 412         u8         reformat_and_modify_action[0x1];
 413         u8         ignore_flow_level[0x1];
 414         u8         reserved_at_16[0x1];
 415         u8         table_miss_action_domain[0x1];
 416         u8         termination_table[0x1];
 417         u8         reformat_and_fwd_to_table[0x1];
 418         u8         reserved_at_1a[0x6];
 419         u8         termination_table_raw_traffic[0x1];
 420         u8         reserved_at_21[0x1];
 421         u8         log_max_ft_size[0x6];
 422         u8         log_max_modify_header_context[0x8];
 423         u8         max_modify_header_actions[0x8];
 424         u8         max_ft_level[0x8];
 425
 426         u8         reserved_at_40[0x20];
 427
 428         u8         reserved_at_60[0x18];
 429         u8         log_max_ft_num[0x8];
 430
 431         u8         reserved_at_80[0x18];
 432         u8         log_max_destination[0x8];
 433
 434         u8         log_max_flow_counter[0x8];
 435         u8         reserved_at_a8[0x10];
 436         u8         log_max_flow[0x8];
 437
 438         u8         reserved_at_c0[0x40];
 439
 440         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 441
 442         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 443 };
 444
 445 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 446         u8         send[0x1];
 447         u8         receive[0x1];
 448         u8         write[0x1];
 449         u8         read[0x1];
 450         u8         atomic[0x1];
 451         u8         srq_receive[0x1];
 452         u8         reserved_at_6[0x1a];
 453 };
 454
 455 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 456         u8         smac_47_16[0x20];
 457
 458         u8         smac_15_0[0x10];
 459         u8         ethertype[0x10];
 460
 461         u8         dmac_47_16[0x20];
 462
 463         u8         dmac_15_0[0x10];
 464         u8         first_prio[0x3];
 465         u8         first_cfi[0x1];
 466         u8         first_vid[0xc];
 467
 468         u8         ip_protocol[0x8];
 469         u8         ip_dscp[0x6];
 470         u8         ip_ecn[0x2];
 471         u8         cvlan_tag[0x1];
 472         u8         svlan_tag[0x1];
 473         u8         frag[0x1];
 474         u8         ip_version[0x4];
 475         u8         tcp_flags[0x9];
 476
 477         u8         tcp_sport[0x10];
 478         u8         tcp_dport[0x10];
 479
 480         u8         reserved_at_c0[0x18];
 481         u8         ttl_hoplimit[0x8];
 482
 483         u8         udp_sport[0x10];
 484         u8         udp_dport[0x10];
 485
 486         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 487
 488         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 489 };
 490
 491 struct mlx5_ifc_nvgre_key_bits {
 492         u8 hi[0x18];
 493         u8 lo[0x8];
 494 };
 495
 496 union mlx5_ifc_gre_key_bits {
 497         struct mlx5_ifc_nvgre_key_bits nvgre;
 498         u8 key[0x20];
 499 };
 500
 501 struct mlx5_ifc_fte_match_set_misc_bits {
 502         u8         gre_c_present[0x1];
 503         u8         reserved_at_1[0x1];
 504         u8         gre_k_present[0x1];
 505         u8         gre_s_present[0x1];
 506         u8         source_vhca_port[0x4];
 507         u8         source_sqn[0x18];
 508
 509         u8         source_eswitch_owner_vhca_id[0x10];
 510         u8         source_port[0x10];
 511
 512         u8         outer_second_prio[0x3];
 513         u8         outer_second_cfi[0x1];
 514         u8         outer_second_vid[0xc];
 515         u8         inner_second_prio[0x3];
 516         u8         inner_second_cfi[0x1];
 517         u8         inner_second_vid[0xc];
 518
 519         u8         outer_second_cvlan_tag[0x1];
 520         u8         inner_second_cvlan_tag[0x1];
 521         u8         outer_second_svlan_tag[0x1];
 522         u8         inner_second_svlan_tag[0x1];
 523         u8         reserved_at_64[0xc];
 524         u8         gre_protocol[0x10];
 525
 526         union mlx5_ifc_gre_key_bits gre_key;
 527
 528         u8         vxlan_vni[0x18];
 529         u8         reserved_at_b8[0x8];
 530
 531         u8         geneve_vni[0x18];
 532         u8         reserved_at_d8[0x7];
 533         u8         geneve_oam[0x1];
 534
 535         u8         reserved_at_e0[0xc];
 536         u8         outer_ipv6_flow_label[0x14];
 537
 538         u8         reserved_at_100[0xc];
 539         u8         inner_ipv6_flow_label[0x14];
 540
 541         u8         reserved_at_120[0xa];
 542         u8         geneve_opt_len[0x6];
 543         u8         geneve_protocol_type[0x10];
 544
 545         u8         reserved_at_140[0x8];
 546         u8         bth_dst_qp[0x18];
 547         u8         reserved_at_160[0x20];
 548         u8         outer_esp_spi[0x20];
 549         u8         reserved_at_1a0[0x60];
 550 };
 551
 552 struct mlx5_ifc_fte_match_mpls_bits {
 553         u8         mpls_label[0x14];
 554         u8         mpls_exp[0x3];
 555         u8         mpls_s_bos[0x1];
 556         u8         mpls_ttl[0x8];
 557 };
 558
 559 struct mlx5_ifc_fte_match_set_misc2_bits {
 560         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 561
 562         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 563
 564         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 565
 566         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 567
 568         u8         metadata_reg_c_7[0x20];
 569
 570         u8         metadata_reg_c_6[0x20];
 571
 572         u8         metadata_reg_c_5[0x20];
 573
 574         u8         metadata_reg_c_4[0x20];
 575
 576         u8         metadata_reg_c_3[0x20];
 577
 578         u8         metadata_reg_c_2[0x20];
 579
 580         u8         metadata_reg_c_1[0x20];
 581
 582         u8         metadata_reg_c_0[0x20];
 583
 584         u8         metadata_reg_a[0x20];
 585
 586         u8         metadata_reg_b[0x20];
 587
 588         u8         reserved_at_1c0[0x40];
 589 };
 590
 591 struct mlx5_ifc_fte_match_set_misc3_bits {
 592         u8         inner_tcp_seq_num[0x20];
 593
 594         u8         outer_tcp_seq_num[0x20];
 595
 596         u8         inner_tcp_ack_num[0x20];
 597
 598         u8         outer_tcp_ack_num[0x20];
 599
 600         u8         reserved_at_80[0x8];
 601         u8         outer_vxlan_gpe_vni[0x18];
 602
 603         u8         outer_vxlan_gpe_next_protocol[0x8];
 604         u8         outer_vxlan_gpe_flags[0x8];
 605         u8         reserved_at_b0[0x10];
 606
 607         u8         icmp_header_data[0x20];
 608
 609         u8         icmpv6_header_data[0x20];
 610
 611         u8         icmp_type[0x8];
 612         u8         icmp_code[0x8];
 613         u8         icmpv6_type[0x8];
 614         u8         icmpv6_code[0x8];
 615
 616         u8         geneve_tlv_option_0_data[0x20];
 617
 618         u8         reserved_at_140[0xc0];
 619 };
 620
 621 struct mlx5_ifc_cmd_pas_bits {
 622         u8         pa_h[0x20];
 623
 624         u8         pa_l[0x14];
 625         u8         reserved_at_34[0xc];
 626 };
 627
 628 struct mlx5_ifc_uint64_bits {
 629         u8         hi[0x20];
 630
 631         u8         lo[0x20];
 632 };
 633
 634 enum {
 635         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 636         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 637         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 638         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 639         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 640         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 641         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 642         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 643         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 644         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 645 };
 646
 647 struct mlx5_ifc_ads_bits {
 648         u8         fl[0x1];
 649         u8         free_ar[0x1];
 650         u8         reserved_at_2[0xe];
 651         u8         pkey_index[0x10];
 652
 653         u8         reserved_at_20[0x8];
 654         u8         grh[0x1];
 655         u8         mlid[0x7];
 656         u8         rlid[0x10];
 657
 658         u8         ack_timeout[0x5];
 659         u8         reserved_at_45[0x3];
 660         u8         src_addr_index[0x8];
 661         u8         reserved_at_50[0x4];
 662         u8         stat_rate[0x4];
 663         u8         hop_limit[0x8];
 664
 665         u8         reserved_at_60[0x4];
 666         u8         tclass[0x8];
 667         u8         flow_label[0x14];
 668
 669         u8         rgid_rip[16][0x8];
 670
 671         u8         reserved_at_100[0x4];
 672         u8         f_dscp[0x1];
 673         u8         f_ecn[0x1];
 674         u8         reserved_at_106[0x1];
 675         u8         f_eth_prio[0x1];
 676         u8         ecn[0x2];
 677         u8         dscp[0x6];
 678         u8         udp_sport[0x10];
 679
 680         u8         dei_cfi[0x1];
 681         u8         eth_prio[0x3];
 682         u8         sl[0x4];
 683         u8         vhca_port_num[0x8];
 684         u8         rmac_47_32[0x10];
 685
 686         u8         rmac_31_0[0x20];
 687 };
 688
 689 struct mlx5_ifc_flow_table_nic_cap_bits {
 690         u8         nic_rx_multi_path_tirs[0x1];
 691         u8         nic_rx_multi_path_tirs_fts[0x1];
 692         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 693         u8         reserved_at_3[0x4];
 694         u8         sw_owner_reformat_supported[0x1];
 695         u8         reserved_at_8[0x18];
 696
 697         u8         encap_general_header[0x1];
 698         u8         reserved_at_21[0xa];
 699         u8         log_max_packet_reformat_context[0x5];
 700         u8         reserved_at_30[0x6];
 701         u8         max_encap_header_size[0xa];
 702         u8         reserved_at_40[0x1c0];
 703
 704         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 705
 706         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 707
 708         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 709
 710         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 711
 712         u8         reserved_at_a00[0x200];
 713
 714         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 715
 716         u8         reserved_at_e00[0x1200];
 717
 718         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 719
 720         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 721
 722         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 723
 724         u8         reserved_at_20c0[0x5f40];
 725 };
 726
 727 enum {
 728         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 729         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 730         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 731         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 732         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 733         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 734         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 735         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 736 };
 737
 738 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 739         u8      fdb_to_vport_reg_c_id[0x8];
 740         u8      reserved_at_8[0xd];
 741         u8      fdb_modify_header_fwd_to_table[0x1];
 742         u8      reserved_at_16[0x1];
 743         u8      flow_source[0x1];
 744         u8      reserved_at_18[0x2];
 745         u8      multi_fdb_encap[0x1];
 746         u8      egress_acl_forward_to_vport[0x1];
 747         u8      fdb_multi_path_to_table[0x1];
 748         u8      reserved_at_1d[0x3];
 749
 750         u8      reserved_at_20[0x1e0];
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 757
 758         u8      reserved_at_800[0x1000];
 759
 760         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 761
 762         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 763
 764         u8      sw_steering_uplink_icm_address_rx[0x40];
 765
 766         u8      sw_steering_uplink_icm_address_tx[0x40];
 767
 768         u8      reserved_at_1900[0x6700];
 769 };
 770
 771 enum {
 772         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 773         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 774 };
 775
 776 struct mlx5_ifc_e_switch_cap_bits {
 777         u8         vport_svlan_strip[0x1];
 778         u8         vport_cvlan_strip[0x1];
 779         u8         vport_svlan_insert[0x1];
 780         u8         vport_cvlan_insert_if_not_exist[0x1];
 781         u8         vport_cvlan_insert_overwrite[0x1];
 782         u8         reserved_at_5[0x3];
 783         u8         esw_uplink_ingress_acl[0x1];
 784         u8         reserved_at_9[0x10];
 785         u8         esw_functions_changed[0x1];
 786         u8         reserved_at_1a[0x1];
 787         u8         ecpf_vport_exists[0x1];
 788         u8         counter_eswitch_affinity[0x1];
 789         u8         merged_eswitch[0x1];
 790         u8         nic_vport_node_guid_modify[0x1];
 791         u8         nic_vport_port_guid_modify[0x1];
 792
 793         u8         vxlan_encap_decap[0x1];
 794         u8         nvgre_encap_decap[0x1];
 795         u8         reserved_at_22[0x1];
 796         u8         log_max_fdb_encap_uplink[0x5];
 797         u8         reserved_at_21[0x3];
 798         u8         log_max_packet_reformat_context[0x5];
 799         u8         reserved_2b[0x6];
 800         u8         max_encap_header_size[0xa];
 801
 802         u8         reserved_at_40[0xb];
 803         u8         log_max_esw_sf[0x5];
 804         u8         esw_sf_base_id[0x10];
 805
 806         u8         reserved_at_60[0x7a0];
 807
 808 };
 809
 810 struct mlx5_ifc_qos_cap_bits {
 811         u8         packet_pacing[0x1];
 812         u8         esw_scheduling[0x1];
 813         u8         esw_bw_share[0x1];
 814         u8         esw_rate_limit[0x1];
 815         u8         reserved_at_4[0x1];
 816         u8         packet_pacing_burst_bound[0x1];
 817         u8         packet_pacing_typical_size[0x1];
 818         u8         reserved_at_7[0x4];
 819         u8         packet_pacing_uid[0x1];
 820         u8         reserved_at_c[0x14];
 821
 822         u8         reserved_at_20[0x20];
 823
 824         u8         packet_pacing_max_rate[0x20];
 825
 826         u8         packet_pacing_min_rate[0x20];
 827
 828         u8         reserved_at_80[0x10];
 829         u8         packet_pacing_rate_table_size[0x10];
 830
 831         u8         esw_element_type[0x10];
 832         u8         esw_tsar_type[0x10];
 833
 834         u8         reserved_at_c0[0x10];
 835         u8         max_qos_para_vport[0x10];
 836
 837         u8         max_tsar_bw_share[0x20];
 838
 839         u8         reserved_at_100[0x700];
 840 };
 841
 842 struct mlx5_ifc_debug_cap_bits {
 843         u8         core_dump_general[0x1];
 844         u8         core_dump_qp[0x1];
 845         u8         reserved_at_2[0x7];
 846         u8         resource_dump[0x1];
 847         u8         reserved_at_a[0x16];
 848
 849         u8         reserved_at_20[0x2];
 850         u8         stall_detect[0x1];
 851         u8         reserved_at_23[0x1d];
 852
 853         u8         reserved_at_40[0x7c0];
 854 };
 855
 856 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 857         u8         csum_cap[0x1];
 858         u8         vlan_cap[0x1];
 859         u8         lro_cap[0x1];
 860         u8         lro_psh_flag[0x1];
 861         u8         lro_time_stamp[0x1];
 862         u8         reserved_at_5[0x2];
 863         u8         wqe_vlan_insert[0x1];
 864         u8         self_lb_en_modifiable[0x1];
 865         u8         reserved_at_9[0x2];
 866         u8         max_lso_cap[0x5];
 867         u8         multi_pkt_send_wqe[0x2];
 868         u8         wqe_inline_mode[0x2];
 869         u8         rss_ind_tbl_cap[0x4];
 870         u8         reg_umr_sq[0x1];
 871         u8         scatter_fcs[0x1];
 872         u8         enhanced_multi_pkt_send_wqe[0x1];
 873         u8         tunnel_lso_const_out_ip_id[0x1];
 874         u8         reserved_at_1c[0x2];
 875         u8         tunnel_stateless_gre[0x1];
 876         u8         tunnel_stateless_vxlan[0x1];
 877
 878         u8         swp[0x1];
 879         u8         swp_csum[0x1];
 880         u8         swp_lso[0x1];
 881         u8         cqe_checksum_full[0x1];
 882         u8         reserved_at_24[0x5];
 883         u8         tunnel_stateless_ip_over_ip[0x1];
 884         u8         reserved_at_2a[0x6];
 885         u8         max_vxlan_udp_ports[0x8];
 886         u8         reserved_at_38[0x6];
 887         u8         max_geneve_opt_len[0x1];
 888         u8         tunnel_stateless_geneve_rx[0x1];
 889
 890         u8         reserved_at_40[0x10];
 891         u8         lro_min_mss_size[0x10];
 892
 893         u8         reserved_at_60[0x120];
 894
 895         u8         lro_timer_supported_periods[4][0x20];
 896
 897         u8         reserved_at_200[0x600];
 898 };
 899
 900 struct mlx5_ifc_roce_cap_bits {
 901         u8         roce_apm[0x1];
 902         u8         reserved_at_1[0x1f];
 903
 904         u8         reserved_at_20[0x60];
 905
 906         u8         reserved_at_80[0xc];
 907         u8         l3_type[0x4];
 908         u8         reserved_at_90[0x8];
 909         u8         roce_version[0x8];
 910
 911         u8         reserved_at_a0[0x10];
 912         u8         r_roce_dest_udp_port[0x10];
 913
 914         u8         r_roce_max_src_udp_port[0x10];
 915         u8         r_roce_min_src_udp_port[0x10];
 916
 917         u8         reserved_at_e0[0x10];
 918         u8         roce_address_table_size[0x10];
 919
 920         u8         reserved_at_100[0x700];
 921 };
 922
 923 struct mlx5_ifc_sync_steering_in_bits {
 924         u8         opcode[0x10];
 925         u8         uid[0x10];
 926
 927         u8         reserved_at_20[0x10];
 928         u8         op_mod[0x10];
 929
 930         u8         reserved_at_40[0xc0];
 931 };
 932
 933 struct mlx5_ifc_sync_steering_out_bits {
 934         u8         status[0x8];
 935         u8         reserved_at_8[0x18];
 936
 937         u8         syndrome[0x20];
 938
 939         u8         reserved_at_40[0x40];
 940 };
 941
 942 struct mlx5_ifc_device_mem_cap_bits {
 943         u8         memic[0x1];
 944         u8         reserved_at_1[0x1f];
 945
 946         u8         reserved_at_20[0xb];
 947         u8         log_min_memic_alloc_size[0x5];
 948         u8         reserved_at_30[0x8];
 949         u8         log_max_memic_addr_alignment[0x8];
 950
 951         u8         memic_bar_start_addr[0x40];
 952
 953         u8         memic_bar_size[0x20];
 954
 955         u8         max_memic_size[0x20];
 956
 957         u8         steering_sw_icm_start_address[0x40];
 958
 959         u8         reserved_at_100[0x8];
 960         u8         log_header_modify_sw_icm_size[0x8];
 961         u8         reserved_at_110[0x2];
 962         u8         log_sw_icm_alloc_granularity[0x6];
 963         u8         log_steering_sw_icm_size[0x8];
 964
 965         u8         reserved_at_120[0x20];
 966
 967         u8         header_modify_sw_icm_start_address[0x40];
 968
 969         u8         reserved_at_180[0x680];
 970 };
 971
 972 struct mlx5_ifc_device_event_cap_bits {
 973         u8         user_affiliated_events[4][0x40];
 974
 975         u8         user_unaffiliated_events[4][0x40];
 976 };
 977
 978 struct mlx5_ifc_device_virtio_emulation_cap_bits {
 979         u8         reserved_at_0[0x20];
 980
 981         u8         reserved_at_20[0x13];
 982         u8         log_doorbell_stride[0x5];
 983         u8         reserved_at_38[0x3];
 984         u8         log_doorbell_bar_size[0x5];
 985
 986         u8         doorbell_bar_offset[0x40];
 987
 988         u8         reserved_at_80[0x780];
 989 };
 990
 991 enum {
 992         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 993         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 994         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 995         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 996         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 997         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 998         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 999         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1000         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1001 };
1002
1003 enum {
1004         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1005         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1006         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1007         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1008         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1009         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1010         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1011         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1012         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1013 };
1014
1015 struct mlx5_ifc_atomic_caps_bits {
1016         u8         reserved_at_0[0x40];
1017
1018         u8         atomic_req_8B_endianness_mode[0x2];
1019         u8         reserved_at_42[0x4];
1020         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1021
1022         u8         reserved_at_47[0x19];
1023
1024         u8         reserved_at_60[0x20];
1025
1026         u8         reserved_at_80[0x10];
1027         u8         atomic_operations[0x10];
1028
1029         u8         reserved_at_a0[0x10];
1030         u8         atomic_size_qp[0x10];
1031
1032         u8         reserved_at_c0[0x10];
1033         u8         atomic_size_dc[0x10];
1034
1035         u8         reserved_at_e0[0x720];
1036 };
1037
1038 struct mlx5_ifc_odp_cap_bits {
1039         u8         reserved_at_0[0x40];
1040
1041         u8         sig[0x1];
1042         u8         reserved_at_41[0x1f];
1043
1044         u8         reserved_at_60[0x20];
1045
1046         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1047
1048         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1049
1050         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1051
1052         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1053
1054         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1055
1056         u8         reserved_at_120[0x6E0];
1057 };
1058
1059 struct mlx5_ifc_calc_op {
1060         u8        reserved_at_0[0x10];
1061         u8        reserved_at_10[0x9];
1062         u8        op_swap_endianness[0x1];
1063         u8        op_min[0x1];
1064         u8        op_xor[0x1];
1065         u8        op_or[0x1];
1066         u8        op_and[0x1];
1067         u8        op_max[0x1];
1068         u8        op_add[0x1];
1069 };
1070
1071 struct mlx5_ifc_vector_calc_cap_bits {
1072         u8         calc_matrix[0x1];
1073         u8         reserved_at_1[0x1f];
1074         u8         reserved_at_20[0x8];
1075         u8         max_vec_count[0x8];
1076         u8         reserved_at_30[0xd];
1077         u8         max_chunk_size[0x3];
1078         struct mlx5_ifc_calc_op calc0;
1079         struct mlx5_ifc_calc_op calc1;
1080         struct mlx5_ifc_calc_op calc2;
1081         struct mlx5_ifc_calc_op calc3;
1082
1083         u8         reserved_at_c0[0x720];
1084 };
1085
1086 struct mlx5_ifc_tls_cap_bits {
1087         u8         tls_1_2_aes_gcm_128[0x1];
1088         u8         tls_1_3_aes_gcm_128[0x1];
1089         u8         tls_1_2_aes_gcm_256[0x1];
1090         u8         tls_1_3_aes_gcm_256[0x1];
1091         u8         reserved_at_4[0x1c];
1092
1093         u8         reserved_at_20[0x7e0];
1094 };
1095
1096 enum {
1097         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1098         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1099         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1100         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1101 };
1102
1103 enum {
1104         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1105         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1106 };
1107
1108 enum {
1109         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1110         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1111         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1112         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1113         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1114 };
1115
1116 enum {
1117         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1118         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1119         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1120         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1121         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1122         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1123 };
1124
1125 enum {
1126         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1127         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1128 };
1129
1130 enum {
1131         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1132         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1133         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1134 };
1135
1136 enum {
1137         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1138         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1139 };
1140
1141 enum {
1142         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1143         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1144         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1145 };
1146
1147 enum {
1148         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1149         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1150         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1151         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1152 };
1153
1154 enum {
1155         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1156         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1157 };
1158
1159 #define MLX5_FC_BULK_SIZE_FACTOR 128
1160
1161 enum mlx5_fc_bulk_alloc_bitmask {
1162         MLX5_FC_BULK_128   = (1 << 0),
1163         MLX5_FC_BULK_256   = (1 << 1),
1164         MLX5_FC_BULK_512   = (1 << 2),
1165         MLX5_FC_BULK_1024  = (1 << 3),
1166         MLX5_FC_BULK_2048  = (1 << 4),
1167         MLX5_FC_BULK_4096  = (1 << 5),
1168         MLX5_FC_BULK_8192  = (1 << 6),
1169         MLX5_FC_BULK_16384 = (1 << 7),
1170 };
1171
1172 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1173
1174 struct mlx5_ifc_cmd_hca_cap_bits {
1175         u8         reserved_at_0[0x30];
1176         u8         vhca_id[0x10];
1177
1178         u8         reserved_at_40[0x40];
1179
1180         u8         log_max_srq_sz[0x8];
1181         u8         log_max_qp_sz[0x8];
1182         u8         event_cap[0x1];
1183         u8         reserved_at_91[0x7];
1184         u8         prio_tag_required[0x1];
1185         u8         reserved_at_99[0x2];
1186         u8         log_max_qp[0x5];
1187
1188         u8         reserved_at_a0[0xb];
1189         u8         log_max_srq[0x5];
1190         u8         reserved_at_b0[0x10];
1191
1192         u8         max_sgl_for_optimized_performance[0x8];
1193         u8         log_max_cq_sz[0x8];
1194         u8         reserved_at_d0[0xb];
1195         u8         log_max_cq[0x5];
1196
1197         u8         log_max_eq_sz[0x8];
1198         u8         relaxed_ordering_write[0x1];
1199         u8         relaxed_ordering_read[0x1];
1200         u8         log_max_mkey[0x6];
1201         u8         reserved_at_f0[0x8];
1202         u8         dump_fill_mkey[0x1];
1203         u8         reserved_at_f9[0x2];
1204         u8         fast_teardown[0x1];
1205         u8         log_max_eq[0x4];
1206
1207         u8         max_indirection[0x8];
1208         u8         fixed_buffer_size[0x1];
1209         u8         log_max_mrw_sz[0x7];
1210         u8         force_teardown[0x1];
1211         u8         reserved_at_111[0x1];
1212         u8         log_max_bsf_list_size[0x6];
1213         u8         umr_extended_translation_offset[0x1];
1214         u8         null_mkey[0x1];
1215         u8         log_max_klm_list_size[0x6];
1216
1217         u8         reserved_at_120[0xa];
1218         u8         log_max_ra_req_dc[0x6];
1219         u8         reserved_at_130[0xa];
1220         u8         log_max_ra_res_dc[0x6];
1221
1222         u8         reserved_at_140[0x9];
1223         u8         roce_accl[0x1];
1224         u8         log_max_ra_req_qp[0x6];
1225         u8         reserved_at_150[0xa];
1226         u8         log_max_ra_res_qp[0x6];
1227
1228         u8         end_pad[0x1];
1229         u8         cc_query_allowed[0x1];
1230         u8         cc_modify_allowed[0x1];
1231         u8         start_pad[0x1];
1232         u8         cache_line_128byte[0x1];
1233         u8         reserved_at_165[0x4];
1234         u8         rts2rts_qp_counters_set_id[0x1];
1235         u8         reserved_at_16a[0x2];
1236         u8         vnic_env_int_rq_oob[0x1];
1237         u8         sbcam_reg[0x1];
1238         u8         reserved_at_16e[0x1];
1239         u8         qcam_reg[0x1];
1240         u8         gid_table_size[0x10];
1241
1242         u8         out_of_seq_cnt[0x1];
1243         u8         vport_counters[0x1];
1244         u8         retransmission_q_counters[0x1];
1245         u8         debug[0x1];
1246         u8         modify_rq_counter_set_id[0x1];
1247         u8         rq_delay_drop[0x1];
1248         u8         max_qp_cnt[0xa];
1249         u8         pkey_table_size[0x10];
1250
1251         u8         vport_group_manager[0x1];
1252         u8         vhca_group_manager[0x1];
1253         u8         ib_virt[0x1];
1254         u8         eth_virt[0x1];
1255         u8         vnic_env_queue_counters[0x1];
1256         u8         ets[0x1];
1257         u8         nic_flow_table[0x1];
1258         u8         eswitch_manager[0x1];
1259         u8         device_memory[0x1];
1260         u8         mcam_reg[0x1];
1261         u8         pcam_reg[0x1];
1262         u8         local_ca_ack_delay[0x5];
1263         u8         port_module_event[0x1];
1264         u8         enhanced_error_q_counters[0x1];
1265         u8         ports_check[0x1];
1266         u8         reserved_at_1b3[0x1];
1267         u8         disable_link_up[0x1];
1268         u8         beacon_led[0x1];
1269         u8         port_type[0x2];
1270         u8         num_ports[0x8];
1271
1272         u8         reserved_at_1c0[0x1];
1273         u8         pps[0x1];
1274         u8         pps_modify[0x1];
1275         u8         log_max_msg[0x5];
1276         u8         reserved_at_1c8[0x4];
1277         u8         max_tc[0x4];
1278         u8         temp_warn_event[0x1];
1279         u8         dcbx[0x1];
1280         u8         general_notification_event[0x1];
1281         u8         reserved_at_1d3[0x2];
1282         u8         fpga[0x1];
1283         u8         rol_s[0x1];
1284         u8         rol_g[0x1];
1285         u8         reserved_at_1d8[0x1];
1286         u8         wol_s[0x1];
1287         u8         wol_g[0x1];
1288         u8         wol_a[0x1];
1289         u8         wol_b[0x1];
1290         u8         wol_m[0x1];
1291         u8         wol_u[0x1];
1292         u8         wol_p[0x1];
1293
1294         u8         stat_rate_support[0x10];
1295         u8         reserved_at_1f0[0xc];
1296         u8         cqe_version[0x4];
1297
1298         u8         compact_address_vector[0x1];
1299         u8         striding_rq[0x1];
1300         u8         reserved_at_202[0x1];
1301         u8         ipoib_enhanced_offloads[0x1];
1302         u8         ipoib_basic_offloads[0x1];
1303         u8         reserved_at_205[0x1];
1304         u8         repeated_block_disabled[0x1];
1305         u8         umr_modify_entity_size_disabled[0x1];
1306         u8         umr_modify_atomic_disabled[0x1];
1307         u8         umr_indirect_mkey_disabled[0x1];
1308         u8         umr_fence[0x2];
1309         u8         dc_req_scat_data_cqe[0x1];
1310         u8         reserved_at_20d[0x2];
1311         u8         drain_sigerr[0x1];
1312         u8         cmdif_checksum[0x2];
1313         u8         sigerr_cqe[0x1];
1314         u8         reserved_at_213[0x1];
1315         u8         wq_signature[0x1];
1316         u8         sctr_data_cqe[0x1];
1317         u8         reserved_at_216[0x1];
1318         u8         sho[0x1];
1319         u8         tph[0x1];
1320         u8         rf[0x1];
1321         u8         dct[0x1];
1322         u8         qos[0x1];
1323         u8         eth_net_offloads[0x1];
1324         u8         roce[0x1];
1325         u8         atomic[0x1];
1326         u8         reserved_at_21f[0x1];
1327
1328         u8         cq_oi[0x1];
1329         u8         cq_resize[0x1];
1330         u8         cq_moderation[0x1];
1331         u8         reserved_at_223[0x3];
1332         u8         cq_eq_remap[0x1];
1333         u8         pg[0x1];
1334         u8         block_lb_mc[0x1];
1335         u8         reserved_at_229[0x1];
1336         u8         scqe_break_moderation[0x1];
1337         u8         cq_period_start_from_cqe[0x1];
1338         u8         cd[0x1];
1339         u8         reserved_at_22d[0x1];
1340         u8         apm[0x1];
1341         u8         vector_calc[0x1];
1342         u8         umr_ptr_rlky[0x1];
1343         u8         imaicl[0x1];
1344         u8         qp_packet_based[0x1];
1345         u8         reserved_at_233[0x3];
1346         u8         qkv[0x1];
1347         u8         pkv[0x1];
1348         u8         set_deth_sqpn[0x1];
1349         u8         reserved_at_239[0x3];
1350         u8         xrc[0x1];
1351         u8         ud[0x1];
1352         u8         uc[0x1];
1353         u8         rc[0x1];
1354
1355         u8         uar_4k[0x1];
1356         u8         reserved_at_241[0x9];
1357         u8         uar_sz[0x6];
1358         u8         reserved_at_250[0x8];
1359         u8         log_pg_sz[0x8];
1360
1361         u8         bf[0x1];
1362         u8         driver_version[0x1];
1363         u8         pad_tx_eth_packet[0x1];
1364         u8         reserved_at_263[0x8];
1365         u8         log_bf_reg_size[0x5];
1366
1367         u8         reserved_at_270[0x8];
1368         u8         lag_tx_port_affinity[0x1];
1369         u8         reserved_at_279[0x2];
1370         u8         lag_master[0x1];
1371         u8         num_lag_ports[0x4];
1372
1373         u8         reserved_at_280[0x10];
1374         u8         max_wqe_sz_sq[0x10];
1375
1376         u8         reserved_at_2a0[0x10];
1377         u8         max_wqe_sz_rq[0x10];
1378
1379         u8         max_flow_counter_31_16[0x10];
1380         u8         max_wqe_sz_sq_dc[0x10];
1381
1382         u8         reserved_at_2e0[0x7];
1383         u8         max_qp_mcg[0x19];
1384
1385         u8         reserved_at_300[0x10];
1386         u8         flow_counter_bulk_alloc[0x8];
1387         u8         log_max_mcg[0x8];
1388
1389         u8         reserved_at_320[0x3];
1390         u8         log_max_transport_domain[0x5];
1391         u8         reserved_at_328[0x3];
1392         u8         log_max_pd[0x5];
1393         u8         reserved_at_330[0xb];
1394         u8         log_max_xrcd[0x5];
1395
1396         u8         nic_receive_steering_discard[0x1];
1397         u8         receive_discard_vport_down[0x1];
1398         u8         transmit_discard_vport_down[0x1];
1399         u8         reserved_at_343[0x5];
1400         u8         log_max_flow_counter_bulk[0x8];
1401         u8         max_flow_counter_15_0[0x10];
1402
1403
1404         u8         reserved_at_360[0x3];
1405         u8         log_max_rq[0x5];
1406         u8         reserved_at_368[0x3];
1407         u8         log_max_sq[0x5];
1408         u8         reserved_at_370[0x3];
1409         u8         log_max_tir[0x5];
1410         u8         reserved_at_378[0x3];
1411         u8         log_max_tis[0x5];
1412
1413         u8         basic_cyclic_rcv_wqe[0x1];
1414         u8         reserved_at_381[0x2];
1415         u8         log_max_rmp[0x5];
1416         u8         reserved_at_388[0x3];
1417         u8         log_max_rqt[0x5];
1418         u8         reserved_at_390[0x3];
1419         u8         log_max_rqt_size[0x5];
1420         u8         reserved_at_398[0x3];
1421         u8         log_max_tis_per_sq[0x5];
1422
1423         u8         ext_stride_num_range[0x1];
1424         u8         reserved_at_3a1[0x2];
1425         u8         log_max_stride_sz_rq[0x5];
1426         u8         reserved_at_3a8[0x3];
1427         u8         log_min_stride_sz_rq[0x5];
1428         u8         reserved_at_3b0[0x3];
1429         u8         log_max_stride_sz_sq[0x5];
1430         u8         reserved_at_3b8[0x3];
1431         u8         log_min_stride_sz_sq[0x5];
1432
1433         u8         hairpin[0x1];
1434         u8         reserved_at_3c1[0x2];
1435         u8         log_max_hairpin_queues[0x5];
1436         u8         reserved_at_3c8[0x3];
1437         u8         log_max_hairpin_wq_data_sz[0x5];
1438         u8         reserved_at_3d0[0x3];
1439         u8         log_max_hairpin_num_packets[0x5];
1440         u8         reserved_at_3d8[0x3];
1441         u8         log_max_wq_sz[0x5];
1442
1443         u8         nic_vport_change_event[0x1];
1444         u8         disable_local_lb_uc[0x1];
1445         u8         disable_local_lb_mc[0x1];
1446         u8         log_min_hairpin_wq_data_sz[0x5];
1447         u8         reserved_at_3e8[0x3];
1448         u8         log_max_vlan_list[0x5];
1449         u8         reserved_at_3f0[0x3];
1450         u8         log_max_current_mc_list[0x5];
1451         u8         reserved_at_3f8[0x3];
1452         u8         log_max_current_uc_list[0x5];
1453
1454         u8         general_obj_types[0x40];
1455
1456         u8         reserved_at_440[0x20];
1457
1458         u8         reserved_at_460[0x3];
1459         u8         log_max_uctx[0x5];
1460         u8         reserved_at_468[0x3];
1461         u8         log_max_umem[0x5];
1462         u8         max_num_eqs[0x10];
1463
1464         u8         reserved_at_480[0x1];
1465         u8         tls_tx[0x1];
1466         u8         reserved_at_482[0x1];
1467         u8         log_max_l2_table[0x5];
1468         u8         reserved_at_488[0x8];
1469         u8         log_uar_page_sz[0x10];
1470
1471         u8         reserved_at_4a0[0x20];
1472         u8         device_frequency_mhz[0x20];
1473         u8         device_frequency_khz[0x20];
1474
1475         u8         reserved_at_500[0x20];
1476         u8         num_of_uars_per_page[0x20];
1477
1478         u8         flex_parser_protocols[0x20];
1479
1480         u8         max_geneve_tlv_options[0x8];
1481         u8         reserved_at_568[0x3];
1482         u8         max_geneve_tlv_option_data_len[0x5];
1483         u8         reserved_at_570[0x10];
1484
1485         u8         reserved_at_580[0x33];
1486         u8         log_max_dek[0x5];
1487         u8         reserved_at_5b8[0x4];
1488         u8         mini_cqe_resp_stride_index[0x1];
1489         u8         cqe_128_always[0x1];
1490         u8         cqe_compression_128[0x1];
1491         u8         cqe_compression[0x1];
1492
1493         u8         cqe_compression_timeout[0x10];
1494         u8         cqe_compression_max_num[0x10];
1495
1496         u8         reserved_at_5e0[0x10];
1497         u8         tag_matching[0x1];
1498         u8         rndv_offload_rc[0x1];
1499         u8         rndv_offload_dc[0x1];
1500         u8         log_tag_matching_list_sz[0x5];
1501         u8         reserved_at_5f8[0x3];
1502         u8         log_max_xrq[0x5];
1503
1504         u8         affiliate_nic_vport_criteria[0x8];
1505         u8         native_port_num[0x8];
1506         u8         num_vhca_ports[0x8];
1507         u8         reserved_at_618[0x6];
1508         u8         sw_owner_id[0x1];
1509         u8         reserved_at_61f[0x1];
1510
1511         u8         max_num_of_monitor_counters[0x10];
1512         u8         num_ppcnt_monitor_counters[0x10];
1513
1514         u8         reserved_at_640[0x10];
1515         u8         num_q_monitor_counters[0x10];
1516
1517         u8         reserved_at_660[0x20];
1518
1519         u8         sf[0x1];
1520         u8         sf_set_partition[0x1];
1521         u8         reserved_at_682[0x1];
1522         u8         log_max_sf[0x5];
1523         u8         reserved_at_688[0x8];
1524         u8         log_min_sf_size[0x8];
1525         u8         max_num_sf_partitions[0x8];
1526
1527         u8         uctx_cap[0x20];
1528
1529         u8         reserved_at_6c0[0x4];
1530         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1531         u8         flex_parser_id_icmp_dw1[0x4];
1532         u8         flex_parser_id_icmp_dw0[0x4];
1533         u8         flex_parser_id_icmpv6_dw1[0x4];
1534         u8         flex_parser_id_icmpv6_dw0[0x4];
1535         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1536         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1537
1538         u8         reserved_at_6e0[0x10];
1539         u8         sf_base_id[0x10];
1540
1541         u8         reserved_at_700[0x80];
1542         u8         vhca_tunnel_commands[0x40];
1543         u8         reserved_at_7c0[0x40];
1544 };
1545
1546 enum mlx5_flow_destination_type {
1547         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1548         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1549         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1550
1551         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1552         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1553         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1554 };
1555
1556 enum mlx5_flow_table_miss_action {
1557         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1558         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1559         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1560 };
1561
1562 struct mlx5_ifc_dest_format_struct_bits {
1563         u8         destination_type[0x8];
1564         u8         destination_id[0x18];
1565
1566         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1567         u8         packet_reformat[0x1];
1568         u8         reserved_at_22[0xe];
1569         u8         destination_eswitch_owner_vhca_id[0x10];
1570 };
1571
1572 struct mlx5_ifc_flow_counter_list_bits {
1573         u8         flow_counter_id[0x20];
1574
1575         u8         reserved_at_20[0x20];
1576 };
1577
1578 struct mlx5_ifc_extended_dest_format_bits {
1579         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1580
1581         u8         packet_reformat_id[0x20];
1582
1583         u8         reserved_at_60[0x20];
1584 };
1585
1586 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1587         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1588         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1589 };
1590
1591 struct mlx5_ifc_fte_match_param_bits {
1592         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1593
1594         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1595
1596         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1597
1598         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1599
1600         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1601
1602         u8         reserved_at_a00[0x600];
1603 };
1604
1605 enum {
1606         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1607         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1608         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1609         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1610         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1611 };
1612
1613 struct mlx5_ifc_rx_hash_field_select_bits {
1614         u8         l3_prot_type[0x1];
1615         u8         l4_prot_type[0x1];
1616         u8         selected_fields[0x1e];
1617 };
1618
1619 enum {
1620         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1621         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1622 };
1623
1624 enum {
1625         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1626         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1627 };
1628
1629 struct mlx5_ifc_wq_bits {
1630         u8         wq_type[0x4];
1631         u8         wq_signature[0x1];
1632         u8         end_padding_mode[0x2];
1633         u8         cd_slave[0x1];
1634         u8         reserved_at_8[0x18];
1635
1636         u8         hds_skip_first_sge[0x1];
1637         u8         log2_hds_buf_size[0x3];
1638         u8         reserved_at_24[0x7];
1639         u8         page_offset[0x5];
1640         u8         lwm[0x10];
1641
1642         u8         reserved_at_40[0x8];
1643         u8         pd[0x18];
1644
1645         u8         reserved_at_60[0x8];
1646         u8         uar_page[0x18];
1647
1648         u8         dbr_addr[0x40];
1649
1650         u8         hw_counter[0x20];
1651
1652         u8         sw_counter[0x20];
1653
1654         u8         reserved_at_100[0xc];
1655         u8         log_wq_stride[0x4];
1656         u8         reserved_at_110[0x3];
1657         u8         log_wq_pg_sz[0x5];
1658         u8         reserved_at_118[0x3];
1659         u8         log_wq_sz[0x5];
1660
1661         u8         dbr_umem_valid[0x1];
1662         u8         wq_umem_valid[0x1];
1663         u8         reserved_at_122[0x1];
1664         u8         log_hairpin_num_packets[0x5];
1665         u8         reserved_at_128[0x3];
1666         u8         log_hairpin_data_sz[0x5];
1667
1668         u8         reserved_at_130[0x4];
1669         u8         log_wqe_num_of_strides[0x4];
1670         u8         two_byte_shift_en[0x1];
1671         u8         reserved_at_139[0x4];
1672         u8         log_wqe_stride_size[0x3];
1673
1674         u8         reserved_at_140[0x4c0];
1675
1676         struct mlx5_ifc_cmd_pas_bits pas[0];
1677 };
1678
1679 struct mlx5_ifc_rq_num_bits {
1680         u8         reserved_at_0[0x8];
1681         u8         rq_num[0x18];
1682 };
1683
1684 struct mlx5_ifc_mac_address_layout_bits {
1685         u8         reserved_at_0[0x10];
1686         u8         mac_addr_47_32[0x10];
1687
1688         u8         mac_addr_31_0[0x20];
1689 };
1690
1691 struct mlx5_ifc_vlan_layout_bits {
1692         u8         reserved_at_0[0x14];
1693         u8         vlan[0x0c];
1694
1695         u8         reserved_at_20[0x20];
1696 };
1697
1698 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1699         u8         reserved_at_0[0xa0];
1700
1701         u8         min_time_between_cnps[0x20];
1702
1703         u8         reserved_at_c0[0x12];
1704         u8         cnp_dscp[0x6];
1705         u8         reserved_at_d8[0x4];
1706         u8         cnp_prio_mode[0x1];
1707         u8         cnp_802p_prio[0x3];
1708
1709         u8         reserved_at_e0[0x720];
1710 };
1711
1712 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1713         u8         reserved_at_0[0x60];
1714
1715         u8         reserved_at_60[0x4];
1716         u8         clamp_tgt_rate[0x1];
1717         u8         reserved_at_65[0x3];
1718         u8         clamp_tgt_rate_after_time_inc[0x1];
1719         u8         reserved_at_69[0x17];
1720
1721         u8         reserved_at_80[0x20];
1722
1723         u8         rpg_time_reset[0x20];
1724
1725         u8         rpg_byte_reset[0x20];
1726
1727         u8         rpg_threshold[0x20];
1728
1729         u8         rpg_max_rate[0x20];
1730
1731         u8         rpg_ai_rate[0x20];
1732
1733         u8         rpg_hai_rate[0x20];
1734
1735         u8         rpg_gd[0x20];
1736
1737         u8         rpg_min_dec_fac[0x20];
1738
1739         u8         rpg_min_rate[0x20];
1740
1741         u8         reserved_at_1c0[0xe0];
1742
1743         u8         rate_to_set_on_first_cnp[0x20];
1744
1745         u8         dce_tcp_g[0x20];
1746
1747         u8         dce_tcp_rtt[0x20];
1748
1749         u8         rate_reduce_monitor_period[0x20];
1750
1751         u8         reserved_at_320[0x20];
1752
1753         u8         initial_alpha_value[0x20];
1754
1755         u8         reserved_at_360[0x4a0];
1756 };
1757
1758 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1759         u8         reserved_at_0[0x80];
1760
1761         u8         rppp_max_rps[0x20];
1762
1763         u8         rpg_time_reset[0x20];
1764
1765         u8         rpg_byte_reset[0x20];
1766
1767         u8         rpg_threshold[0x20];
1768
1769         u8         rpg_max_rate[0x20];
1770
1771         u8         rpg_ai_rate[0x20];
1772
1773         u8         rpg_hai_rate[0x20];
1774
1775         u8         rpg_gd[0x20];
1776
1777         u8         rpg_min_dec_fac[0x20];
1778
1779         u8         rpg_min_rate[0x20];
1780
1781         u8         reserved_at_1c0[0x640];
1782 };
1783
1784 enum {
1785         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1786         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1787         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1788 };
1789
1790 struct mlx5_ifc_resize_field_select_bits {
1791         u8         resize_field_select[0x20];
1792 };
1793
1794 struct mlx5_ifc_resource_dump_bits {
1795         u8         more_dump[0x1];
1796         u8         inline_dump[0x1];
1797         u8         reserved_at_2[0xa];
1798         u8         seq_num[0x4];
1799         u8         segment_type[0x10];
1800
1801         u8         reserved_at_20[0x10];
1802         u8         vhca_id[0x10];
1803
1804         u8         index1[0x20];
1805
1806         u8         index2[0x20];
1807
1808         u8         num_of_obj1[0x10];
1809         u8         num_of_obj2[0x10];
1810
1811         u8         reserved_at_a0[0x20];
1812
1813         u8         device_opaque[0x40];
1814
1815         u8         mkey[0x20];
1816
1817         u8         size[0x20];
1818
1819         u8         address[0x40];
1820
1821         u8         inline_data[52][0x20];
1822 };
1823
1824 struct mlx5_ifc_resource_dump_menu_record_bits {
1825         u8         reserved_at_0[0x4];
1826         u8         num_of_obj2_supports_active[0x1];
1827         u8         num_of_obj2_supports_all[0x1];
1828         u8         must_have_num_of_obj2[0x1];
1829         u8         support_num_of_obj2[0x1];
1830         u8         num_of_obj1_supports_active[0x1];
1831         u8         num_of_obj1_supports_all[0x1];
1832         u8         must_have_num_of_obj1[0x1];
1833         u8         support_num_of_obj1[0x1];
1834         u8         must_have_index2[0x1];
1835         u8         support_index2[0x1];
1836         u8         must_have_index1[0x1];
1837         u8         support_index1[0x1];
1838         u8         segment_type[0x10];
1839
1840         u8         segment_name[4][0x20];
1841
1842         u8         index1_name[4][0x20];
1843
1844         u8         index2_name[4][0x20];
1845 };
1846
1847 struct mlx5_ifc_resource_dump_segment_header_bits {
1848         u8         length_dw[0x10];
1849         u8         segment_type[0x10];
1850 };
1851
1852 struct mlx5_ifc_resource_dump_command_segment_bits {
1853         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1854
1855         u8         segment_called[0x10];
1856         u8         vhca_id[0x10];
1857
1858         u8         index1[0x20];
1859
1860         u8         index2[0x20];
1861
1862         u8         num_of_obj1[0x10];
1863         u8         num_of_obj2[0x10];
1864 };
1865
1866 struct mlx5_ifc_resource_dump_error_segment_bits {
1867         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1868
1869         u8         reserved_at_20[0x10];
1870         u8         syndrome_id[0x10];
1871
1872         u8         reserved_at_40[0x40];
1873
1874         u8         error[8][0x20];
1875 };
1876
1877 struct mlx5_ifc_resource_dump_info_segment_bits {
1878         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1879
1880         u8         reserved_at_20[0x18];
1881         u8         dump_version[0x8];
1882
1883         u8         hw_version[0x20];
1884
1885         u8         fw_version[0x20];
1886 };
1887
1888 struct mlx5_ifc_resource_dump_menu_segment_bits {
1889         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1890
1891         u8         reserved_at_20[0x10];
1892         u8         num_of_records[0x10];
1893
1894         struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1895 };
1896
1897 struct mlx5_ifc_resource_dump_resource_segment_bits {
1898         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1899
1900         u8         reserved_at_20[0x20];
1901
1902         u8         index1[0x20];
1903
1904         u8         index2[0x20];
1905
1906         u8         payload[0][0x20];
1907 };
1908
1909 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1910         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1911 };
1912
1913 struct mlx5_ifc_menu_resource_dump_response_bits {
1914         struct mlx5_ifc_resource_dump_info_segment_bits info;
1915         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1916         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1917         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1918 };
1919
1920 enum {
1921         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1922         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1923         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1924         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1925 };
1926
1927 struct mlx5_ifc_modify_field_select_bits {
1928         u8         modify_field_select[0x20];
1929 };
1930
1931 struct mlx5_ifc_field_select_r_roce_np_bits {
1932         u8         field_select_r_roce_np[0x20];
1933 };
1934
1935 struct mlx5_ifc_field_select_r_roce_rp_bits {
1936         u8         field_select_r_roce_rp[0x20];
1937 };
1938
1939 enum {
1940         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1941         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1942         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1943         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1944         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1945         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1946         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1947         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1948         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1949         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1950 };
1951
1952 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1953         u8         field_select_8021qaurp[0x20];
1954 };
1955
1956 struct mlx5_ifc_phys_layer_cntrs_bits {
1957         u8         time_since_last_clear_high[0x20];
1958
1959         u8         time_since_last_clear_low[0x20];
1960
1961         u8         symbol_errors_high[0x20];
1962
1963         u8         symbol_errors_low[0x20];
1964
1965         u8         sync_headers_errors_high[0x20];
1966
1967         u8         sync_headers_errors_low[0x20];
1968
1969         u8         edpl_bip_errors_lane0_high[0x20];
1970
1971         u8         edpl_bip_errors_lane0_low[0x20];
1972
1973         u8         edpl_bip_errors_lane1_high[0x20];
1974
1975         u8         edpl_bip_errors_lane1_low[0x20];
1976
1977         u8         edpl_bip_errors_lane2_high[0x20];
1978
1979         u8         edpl_bip_errors_lane2_low[0x20];
1980
1981         u8         edpl_bip_errors_lane3_high[0x20];
1982
1983         u8         edpl_bip_errors_lane3_low[0x20];
1984
1985         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1986
1987         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1988
1989         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1990
1991         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1992
1993         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1994
1995         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1996
1997         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1998
1999         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2000
2001         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2002
2003         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2004
2005         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2006
2007         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2008
2009         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2010
2011         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2012
2013         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2014
2015         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2016
2017         u8         rs_fec_corrected_blocks_high[0x20];
2018
2019         u8         rs_fec_corrected_blocks_low[0x20];
2020
2021         u8         rs_fec_uncorrectable_blocks_high[0x20];
2022
2023         u8         rs_fec_uncorrectable_blocks_low[0x20];
2024
2025         u8         rs_fec_no_errors_blocks_high[0x20];
2026
2027         u8         rs_fec_no_errors_blocks_low[0x20];
2028
2029         u8         rs_fec_single_error_blocks_high[0x20];
2030
2031         u8         rs_fec_single_error_blocks_low[0x20];
2032
2033         u8         rs_fec_corrected_symbols_total_high[0x20];
2034
2035         u8         rs_fec_corrected_symbols_total_low[0x20];
2036
2037         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2038
2039         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2040
2041         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2042
2043         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2044
2045         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2046
2047         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2048
2049         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2050
2051         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2052
2053         u8         link_down_events[0x20];
2054
2055         u8         successful_recovery_events[0x20];
2056
2057         u8         reserved_at_640[0x180];
2058 };
2059
2060 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2061         u8         time_since_last_clear_high[0x20];
2062
2063         u8         time_since_last_clear_low[0x20];
2064
2065         u8         phy_received_bits_high[0x20];
2066
2067         u8         phy_received_bits_low[0x20];
2068
2069         u8         phy_symbol_errors_high[0x20];
2070
2071         u8         phy_symbol_errors_low[0x20];
2072
2073         u8         phy_corrected_bits_high[0x20];
2074
2075         u8         phy_corrected_bits_low[0x20];
2076
2077         u8         phy_corrected_bits_lane0_high[0x20];
2078
2079         u8         phy_corrected_bits_lane0_low[0x20];
2080
2081         u8         phy_corrected_bits_lane1_high[0x20];
2082
2083         u8         phy_corrected_bits_lane1_low[0x20];
2084
2085         u8         phy_corrected_bits_lane2_high[0x20];
2086
2087         u8         phy_corrected_bits_lane2_low[0x20];
2088
2089         u8         phy_corrected_bits_lane3_high[0x20];
2090
2091         u8         phy_corrected_bits_lane3_low[0x20];
2092
2093         u8         reserved_at_200[0x5c0];
2094 };
2095
2096 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2097         u8         symbol_error_counter[0x10];
2098
2099         u8         link_error_recovery_counter[0x8];
2100
2101         u8         link_downed_counter[0x8];
2102
2103         u8         port_rcv_errors[0x10];
2104
2105         u8         port_rcv_remote_physical_errors[0x10];
2106
2107         u8         port_rcv_switch_relay_errors[0x10];
2108
2109         u8         port_xmit_discards[0x10];
2110
2111         u8         port_xmit_constraint_errors[0x8];
2112
2113         u8         port_rcv_constraint_errors[0x8];
2114
2115         u8         reserved_at_70[0x8];
2116
2117         u8         link_overrun_errors[0x8];
2118
2119         u8         reserved_at_80[0x10];
2120
2121         u8         vl_15_dropped[0x10];
2122
2123         u8         reserved_at_a0[0x80];
2124
2125         u8         port_xmit_wait[0x20];
2126 };
2127
2128 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2129         u8         transmit_queue_high[0x20];
2130
2131         u8         transmit_queue_low[0x20];
2132
2133         u8         no_buffer_discard_uc_high[0x20];
2134
2135         u8         no_buffer_discard_uc_low[0x20];
2136
2137         u8         reserved_at_80[0x740];
2138 };
2139
2140 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2141         u8         wred_discard_high[0x20];
2142
2143         u8         wred_discard_low[0x20];
2144
2145         u8         ecn_marked_tc_high[0x20];
2146
2147         u8         ecn_marked_tc_low[0x20];
2148
2149         u8         reserved_at_80[0x740];
2150 };
2151
2152 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2153         u8         rx_octets_high[0x20];
2154
2155         u8         rx_octets_low[0x20];
2156
2157         u8         reserved_at_40[0xc0];
2158
2159         u8         rx_frames_high[0x20];
2160
2161         u8         rx_frames_low[0x20];
2162
2163         u8         tx_octets_high[0x20];
2164
2165         u8         tx_octets_low[0x20];
2166
2167         u8         reserved_at_180[0xc0];
2168
2169         u8         tx_frames_high[0x20];
2170
2171         u8         tx_frames_low[0x20];
2172
2173         u8         rx_pause_high[0x20];
2174
2175         u8         rx_pause_low[0x20];
2176
2177         u8         rx_pause_duration_high[0x20];
2178
2179         u8         rx_pause_duration_low[0x20];
2180
2181         u8         tx_pause_high[0x20];
2182
2183         u8         tx_pause_low[0x20];
2184
2185         u8         tx_pause_duration_high[0x20];
2186
2187         u8         tx_pause_duration_low[0x20];
2188
2189         u8         rx_pause_transition_high[0x20];
2190
2191         u8         rx_pause_transition_low[0x20];
2192
2193         u8         rx_discards_high[0x20];
2194
2195         u8         rx_discards_low[0x20];
2196
2197         u8         device_stall_minor_watermark_cnt_high[0x20];
2198
2199         u8         device_stall_minor_watermark_cnt_low[0x20];
2200
2201         u8         device_stall_critical_watermark_cnt_high[0x20];
2202
2203         u8         device_stall_critical_watermark_cnt_low[0x20];
2204
2205         u8         reserved_at_480[0x340];
2206 };
2207
2208 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2209         u8         port_transmit_wait_high[0x20];
2210
2211         u8         port_transmit_wait_low[0x20];
2212
2213         u8         reserved_at_40[0x100];
2214
2215         u8         rx_buffer_almost_full_high[0x20];
2216
2217         u8         rx_buffer_almost_full_low[0x20];
2218
2219         u8         rx_buffer_full_high[0x20];
2220
2221         u8         rx_buffer_full_low[0x20];
2222
2223         u8         rx_icrc_encapsulated_high[0x20];
2224
2225         u8         rx_icrc_encapsulated_low[0x20];
2226
2227         u8         reserved_at_200[0x5c0];
2228 };
2229
2230 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2231         u8         dot3stats_alignment_errors_high[0x20];
2232
2233         u8         dot3stats_alignment_errors_low[0x20];
2234
2235         u8         dot3stats_fcs_errors_high[0x20];
2236
2237         u8         dot3stats_fcs_errors_low[0x20];
2238
2239         u8         dot3stats_single_collision_frames_high[0x20];
2240
2241         u8         dot3stats_single_collision_frames_low[0x20];
2242
2243         u8         dot3stats_multiple_collision_frames_high[0x20];
2244
2245         u8         dot3stats_multiple_collision_frames_low[0x20];
2246
2247         u8         dot3stats_sqe_test_errors_high[0x20];
2248
2249         u8         dot3stats_sqe_test_errors_low[0x20];
2250
2251         u8         dot3stats_deferred_transmissions_high[0x20];
2252
2253         u8         dot3stats_deferred_transmissions_low[0x20];
2254
2255         u8         dot3stats_late_collisions_high[0x20];
2256
2257         u8         dot3stats_late_collisions_low[0x20];
2258
2259         u8         dot3stats_excessive_collisions_high[0x20];
2260
2261         u8         dot3stats_excessive_collisions_low[0x20];
2262
2263         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2264
2265         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2266
2267         u8         dot3stats_carrier_sense_errors_high[0x20];
2268
2269         u8         dot3stats_carrier_sense_errors_low[0x20];
2270
2271         u8         dot3stats_frame_too_longs_high[0x20];
2272
2273         u8         dot3stats_frame_too_longs_low[0x20];
2274
2275         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2276
2277         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2278
2279         u8         dot3stats_symbol_errors_high[0x20];
2280
2281         u8         dot3stats_symbol_errors_low[0x20];
2282
2283         u8         dot3control_in_unknown_opcodes_high[0x20];
2284
2285         u8         dot3control_in_unknown_opcodes_low[0x20];
2286
2287         u8         dot3in_pause_frames_high[0x20];
2288
2289         u8         dot3in_pause_frames_low[0x20];
2290
2291         u8         dot3out_pause_frames_high[0x20];
2292
2293         u8         dot3out_pause_frames_low[0x20];
2294
2295         u8         reserved_at_400[0x3c0];
2296 };
2297
2298 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2299         u8         ether_stats_drop_events_high[0x20];
2300
2301         u8         ether_stats_drop_events_low[0x20];
2302
2303         u8         ether_stats_octets_high[0x20];
2304
2305         u8         ether_stats_octets_low[0x20];
2306
2307         u8         ether_stats_pkts_high[0x20];
2308
2309         u8         ether_stats_pkts_low[0x20];
2310
2311         u8         ether_stats_broadcast_pkts_high[0x20];
2312
2313         u8         ether_stats_broadcast_pkts_low[0x20];
2314
2315         u8         ether_stats_multicast_pkts_high[0x20];
2316
2317         u8         ether_stats_multicast_pkts_low[0x20];
2318
2319         u8         ether_stats_crc_align_errors_high[0x20];
2320
2321         u8         ether_stats_crc_align_errors_low[0x20];
2322
2323         u8         ether_stats_undersize_pkts_high[0x20];
2324
2325         u8         ether_stats_undersize_pkts_low[0x20];
2326
2327         u8         ether_stats_oversize_pkts_high[0x20];
2328
2329         u8         ether_stats_oversize_pkts_low[0x20];
2330
2331         u8         ether_stats_fragments_high[0x20];
2332
2333         u8         ether_stats_fragments_low[0x20];
2334
2335         u8         ether_stats_jabbers_high[0x20];
2336
2337         u8         ether_stats_jabbers_low[0x20];
2338
2339         u8         ether_stats_collisions_high[0x20];
2340
2341         u8         ether_stats_collisions_low[0x20];
2342
2343         u8         ether_stats_pkts64octets_high[0x20];
2344
2345         u8         ether_stats_pkts64octets_low[0x20];
2346
2347         u8         ether_stats_pkts65to127octets_high[0x20];
2348
2349         u8         ether_stats_pkts65to127octets_low[0x20];
2350
2351         u8         ether_stats_pkts128to255octets_high[0x20];
2352
2353         u8         ether_stats_pkts128to255octets_low[0x20];
2354
2355         u8         ether_stats_pkts256to511octets_high[0x20];
2356
2357         u8         ether_stats_pkts256to511octets_low[0x20];
2358
2359         u8         ether_stats_pkts512to1023octets_high[0x20];
2360
2361         u8         ether_stats_pkts512to1023octets_low[0x20];
2362
2363         u8         ether_stats_pkts1024to1518octets_high[0x20];
2364
2365         u8         ether_stats_pkts1024to1518octets_low[0x20];
2366
2367         u8         ether_stats_pkts1519to2047octets_high[0x20];
2368
2369         u8         ether_stats_pkts1519to2047octets_low[0x20];
2370
2371         u8         ether_stats_pkts2048to4095octets_high[0x20];
2372
2373         u8         ether_stats_pkts2048to4095octets_low[0x20];
2374
2375         u8         ether_stats_pkts4096to8191octets_high[0x20];
2376
2377         u8         ether_stats_pkts4096to8191octets_low[0x20];
2378
2379         u8         ether_stats_pkts8192to10239octets_high[0x20];
2380
2381         u8         ether_stats_pkts8192to10239octets_low[0x20];
2382
2383         u8         reserved_at_540[0x280];
2384 };
2385
2386 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2387         u8         if_in_octets_high[0x20];
2388
2389         u8         if_in_octets_low[0x20];
2390
2391         u8         if_in_ucast_pkts_high[0x20];
2392
2393         u8         if_in_ucast_pkts_low[0x20];
2394
2395         u8         if_in_discards_high[0x20];
2396
2397         u8         if_in_discards_low[0x20];
2398
2399         u8         if_in_errors_high[0x20];
2400
2401         u8         if_in_errors_low[0x20];
2402
2403         u8         if_in_unknown_protos_high[0x20];
2404
2405         u8         if_in_unknown_protos_low[0x20];
2406
2407         u8         if_out_octets_high[0x20];
2408
2409         u8         if_out_octets_low[0x20];
2410
2411         u8         if_out_ucast_pkts_high[0x20];
2412
2413         u8         if_out_ucast_pkts_low[0x20];
2414
2415         u8         if_out_discards_high[0x20];
2416
2417         u8         if_out_discards_low[0x20];
2418
2419         u8         if_out_errors_high[0x20];
2420
2421         u8         if_out_errors_low[0x20];
2422
2423         u8         if_in_multicast_pkts_high[0x20];
2424
2425         u8         if_in_multicast_pkts_low[0x20];
2426
2427         u8         if_in_broadcast_pkts_high[0x20];
2428
2429         u8         if_in_broadcast_pkts_low[0x20];
2430
2431         u8         if_out_multicast_pkts_high[0x20];
2432
2433         u8         if_out_multicast_pkts_low[0x20];
2434
2435         u8         if_out_broadcast_pkts_high[0x20];
2436
2437         u8         if_out_broadcast_pkts_low[0x20];
2438
2439         u8         reserved_at_340[0x480];
2440 };
2441
2442 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2443         u8         a_frames_transmitted_ok_high[0x20];
2444
2445         u8         a_frames_transmitted_ok_low[0x20];
2446
2447         u8         a_frames_received_ok_high[0x20];
2448
2449         u8         a_frames_received_ok_low[0x20];
2450
2451         u8         a_frame_check_sequence_errors_high[0x20];
2452
2453         u8         a_frame_check_sequence_errors_low[0x20];
2454
2455         u8         a_alignment_errors_high[0x20];
2456
2457         u8         a_alignment_errors_low[0x20];
2458
2459         u8         a_octets_transmitted_ok_high[0x20];
2460
2461         u8         a_octets_transmitted_ok_low[0x20];
2462
2463         u8         a_octets_received_ok_high[0x20];
2464
2465         u8         a_octets_received_ok_low[0x20];
2466
2467         u8         a_multicast_frames_xmitted_ok_high[0x20];
2468
2469         u8         a_multicast_frames_xmitted_ok_low[0x20];
2470
2471         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2472
2473         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2474
2475         u8         a_multicast_frames_received_ok_high[0x20];
2476
2477         u8         a_multicast_frames_received_ok_low[0x20];
2478
2479         u8         a_broadcast_frames_received_ok_high[0x20];
2480
2481         u8         a_broadcast_frames_received_ok_low[0x20];
2482
2483         u8         a_in_range_length_errors_high[0x20];
2484
2485         u8         a_in_range_length_errors_low[0x20];
2486
2487         u8         a_out_of_range_length_field_high[0x20];
2488
2489         u8         a_out_of_range_length_field_low[0x20];
2490
2491         u8         a_frame_too_long_errors_high[0x20];
2492
2493         u8         a_frame_too_long_errors_low[0x20];
2494
2495         u8         a_symbol_error_during_carrier_high[0x20];
2496
2497         u8         a_symbol_error_during_carrier_low[0x20];
2498
2499         u8         a_mac_control_frames_transmitted_high[0x20];
2500
2501         u8         a_mac_control_frames_transmitted_low[0x20];
2502
2503         u8         a_mac_control_frames_received_high[0x20];
2504
2505         u8         a_mac_control_frames_received_low[0x20];
2506
2507         u8         a_unsupported_opcodes_received_high[0x20];
2508
2509         u8         a_unsupported_opcodes_received_low[0x20];
2510
2511         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2512
2513         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2514
2515         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2516
2517         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2518
2519         u8         reserved_at_4c0[0x300];
2520 };
2521
2522 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2523         u8         life_time_counter_high[0x20];
2524
2525         u8         life_time_counter_low[0x20];
2526
2527         u8         rx_errors[0x20];
2528
2529         u8         tx_errors[0x20];
2530
2531         u8         l0_to_recovery_eieos[0x20];
2532
2533         u8         l0_to_recovery_ts[0x20];
2534
2535         u8         l0_to_recovery_framing[0x20];
2536
2537         u8         l0_to_recovery_retrain[0x20];
2538
2539         u8         crc_error_dllp[0x20];
2540
2541         u8         crc_error_tlp[0x20];
2542
2543         u8         tx_overflow_buffer_pkt_high[0x20];
2544
2545         u8         tx_overflow_buffer_pkt_low[0x20];
2546
2547         u8         outbound_stalled_reads[0x20];
2548
2549         u8         outbound_stalled_writes[0x20];
2550
2551         u8         outbound_stalled_reads_events[0x20];
2552
2553         u8         outbound_stalled_writes_events[0x20];
2554
2555         u8         reserved_at_200[0x5c0];
2556 };
2557
2558 struct mlx5_ifc_cmd_inter_comp_event_bits {
2559         u8         command_completion_vector[0x20];
2560
2561         u8         reserved_at_20[0xc0];
2562 };
2563
2564 struct mlx5_ifc_stall_vl_event_bits {
2565         u8         reserved_at_0[0x18];
2566         u8         port_num[0x1];
2567         u8         reserved_at_19[0x3];
2568         u8         vl[0x4];
2569
2570         u8         reserved_at_20[0xa0];
2571 };
2572
2573 struct mlx5_ifc_db_bf_congestion_event_bits {
2574         u8         event_subtype[0x8];
2575         u8         reserved_at_8[0x8];
2576         u8         congestion_level[0x8];
2577         u8         reserved_at_18[0x8];
2578
2579         u8         reserved_at_20[0xa0];
2580 };
2581
2582 struct mlx5_ifc_gpio_event_bits {
2583         u8         reserved_at_0[0x60];
2584
2585         u8         gpio_event_hi[0x20];
2586
2587         u8         gpio_event_lo[0x20];
2588
2589         u8         reserved_at_a0[0x40];
2590 };
2591
2592 struct mlx5_ifc_port_state_change_event_bits {
2593         u8         reserved_at_0[0x40];
2594
2595         u8         port_num[0x4];
2596         u8         reserved_at_44[0x1c];
2597
2598         u8         reserved_at_60[0x80];
2599 };
2600
2601 struct mlx5_ifc_dropped_packet_logged_bits {
2602         u8         reserved_at_0[0xe0];
2603 };
2604
2605 enum {
2606         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2607         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2608 };
2609
2610 struct mlx5_ifc_cq_error_bits {
2611         u8         reserved_at_0[0x8];
2612         u8         cqn[0x18];
2613
2614         u8         reserved_at_20[0x20];
2615
2616         u8         reserved_at_40[0x18];
2617         u8         syndrome[0x8];
2618
2619         u8         reserved_at_60[0x80];
2620 };
2621
2622 struct mlx5_ifc_rdma_page_fault_event_bits {
2623         u8         bytes_committed[0x20];
2624
2625         u8         r_key[0x20];
2626
2627         u8         reserved_at_40[0x10];
2628         u8         packet_len[0x10];
2629
2630         u8         rdma_op_len[0x20];
2631
2632         u8         rdma_va[0x40];
2633
2634         u8         reserved_at_c0[0x5];
2635         u8         rdma[0x1];
2636         u8         write[0x1];
2637         u8         requestor[0x1];
2638         u8         qp_number[0x18];
2639 };
2640
2641 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2642         u8         bytes_committed[0x20];
2643
2644         u8         reserved_at_20[0x10];
2645         u8         wqe_index[0x10];
2646
2647         u8         reserved_at_40[0x10];
2648         u8         len[0x10];
2649
2650         u8         reserved_at_60[0x60];
2651
2652         u8         reserved_at_c0[0x5];
2653         u8         rdma[0x1];
2654         u8         write_read[0x1];
2655         u8         requestor[0x1];
2656         u8         qpn[0x18];
2657 };
2658
2659 struct mlx5_ifc_qp_events_bits {
2660         u8         reserved_at_0[0xa0];
2661
2662         u8         type[0x8];
2663         u8         reserved_at_a8[0x18];
2664
2665         u8         reserved_at_c0[0x8];
2666         u8         qpn_rqn_sqn[0x18];
2667 };
2668
2669 struct mlx5_ifc_dct_events_bits {
2670         u8         reserved_at_0[0xc0];
2671
2672         u8         reserved_at_c0[0x8];
2673         u8         dct_number[0x18];
2674 };
2675
2676 struct mlx5_ifc_comp_event_bits {
2677         u8         reserved_at_0[0xc0];
2678
2679         u8         reserved_at_c0[0x8];
2680         u8         cq_number[0x18];
2681 };
2682
2683 enum {
2684         MLX5_QPC_STATE_RST        = 0x0,
2685         MLX5_QPC_STATE_INIT       = 0x1,
2686         MLX5_QPC_STATE_RTR        = 0x2,
2687         MLX5_QPC_STATE_RTS        = 0x3,
2688         MLX5_QPC_STATE_SQER       = 0x4,
2689         MLX5_QPC_STATE_ERR        = 0x6,
2690         MLX5_QPC_STATE_SQD        = 0x7,
2691         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2692 };
2693
2694 enum {
2695         MLX5_QPC_ST_RC            = 0x0,
2696         MLX5_QPC_ST_UC            = 0x1,
2697         MLX5_QPC_ST_UD            = 0x2,
2698         MLX5_QPC_ST_XRC           = 0x3,
2699         MLX5_QPC_ST_DCI           = 0x5,
2700         MLX5_QPC_ST_QP0           = 0x7,
2701         MLX5_QPC_ST_QP1           = 0x8,
2702         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2703         MLX5_QPC_ST_REG_UMR       = 0xc,
2704 };
2705
2706 enum {
2707         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2708         MLX5_QPC_PM_STATE_REARM     = 0x1,
2709         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2710         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2711 };
2712
2713 enum {
2714         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2715 };
2716
2717 enum {
2718         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2719         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2720 };
2721
2722 enum {
2723         MLX5_QPC_MTU_256_BYTES        = 0x1,
2724         MLX5_QPC_MTU_512_BYTES        = 0x2,
2725         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2726         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2727         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2728         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2729 };
2730
2731 enum {
2732         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2733         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2734         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2735         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2736         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2737         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2738         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2739         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2740 };
2741
2742 enum {
2743         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2744         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2745         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2746 };
2747
2748 enum {
2749         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2750         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2751         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2752 };
2753
2754 struct mlx5_ifc_qpc_bits {
2755         u8         state[0x4];
2756         u8         lag_tx_port_affinity[0x4];
2757         u8         st[0x8];
2758         u8         reserved_at_10[0x3];
2759         u8         pm_state[0x2];
2760         u8         reserved_at_15[0x1];
2761         u8         req_e2e_credit_mode[0x2];
2762         u8         offload_type[0x4];
2763         u8         end_padding_mode[0x2];
2764         u8         reserved_at_1e[0x2];
2765
2766         u8         wq_signature[0x1];
2767         u8         block_lb_mc[0x1];
2768         u8         atomic_like_write_en[0x1];
2769         u8         latency_sensitive[0x1];
2770         u8         reserved_at_24[0x1];
2771         u8         drain_sigerr[0x1];
2772         u8         reserved_at_26[0x2];
2773         u8         pd[0x18];
2774
2775         u8         mtu[0x3];
2776         u8         log_msg_max[0x5];
2777         u8         reserved_at_48[0x1];
2778         u8         log_rq_size[0x4];
2779         u8         log_rq_stride[0x3];
2780         u8         no_sq[0x1];
2781         u8         log_sq_size[0x4];
2782         u8         reserved_at_55[0x6];
2783         u8         rlky[0x1];
2784         u8         ulp_stateless_offload_mode[0x4];
2785
2786         u8         counter_set_id[0x8];
2787         u8         uar_page[0x18];
2788
2789         u8         reserved_at_80[0x8];
2790         u8         user_index[0x18];
2791
2792         u8         reserved_at_a0[0x3];
2793         u8         log_page_size[0x5];
2794         u8         remote_qpn[0x18];
2795
2796         struct mlx5_ifc_ads_bits primary_address_path;
2797
2798         struct mlx5_ifc_ads_bits secondary_address_path;
2799
2800         u8         log_ack_req_freq[0x4];
2801         u8         reserved_at_384[0x4];
2802         u8         log_sra_max[0x3];
2803         u8         reserved_at_38b[0x2];
2804         u8         retry_count[0x3];
2805         u8         rnr_retry[0x3];
2806         u8         reserved_at_393[0x1];
2807         u8         fre[0x1];
2808         u8         cur_rnr_retry[0x3];
2809         u8         cur_retry_count[0x3];
2810         u8         reserved_at_39b[0x5];
2811
2812         u8         reserved_at_3a0[0x20];
2813
2814         u8         reserved_at_3c0[0x8];
2815         u8         next_send_psn[0x18];
2816
2817         u8         reserved_at_3e0[0x8];
2818         u8         cqn_snd[0x18];
2819
2820         u8         reserved_at_400[0x8];
2821         u8         deth_sqpn[0x18];
2822
2823         u8         reserved_at_420[0x20];
2824
2825         u8         reserved_at_440[0x8];
2826         u8         last_acked_psn[0x18];
2827
2828         u8         reserved_at_460[0x8];
2829         u8         ssn[0x18];
2830
2831         u8         reserved_at_480[0x8];
2832         u8         log_rra_max[0x3];
2833         u8         reserved_at_48b[0x1];
2834         u8         atomic_mode[0x4];
2835         u8         rre[0x1];
2836         u8         rwe[0x1];
2837         u8         rae[0x1];
2838         u8         reserved_at_493[0x1];
2839         u8         page_offset[0x6];
2840         u8         reserved_at_49a[0x3];
2841         u8         cd_slave_receive[0x1];
2842         u8         cd_slave_send[0x1];
2843         u8         cd_master[0x1];
2844
2845         u8         reserved_at_4a0[0x3];
2846         u8         min_rnr_nak[0x5];
2847         u8         next_rcv_psn[0x18];
2848
2849         u8         reserved_at_4c0[0x8];
2850         u8         xrcd[0x18];
2851
2852         u8         reserved_at_4e0[0x8];
2853         u8         cqn_rcv[0x18];
2854
2855         u8         dbr_addr[0x40];
2856
2857         u8         q_key[0x20];
2858
2859         u8         reserved_at_560[0x5];
2860         u8         rq_type[0x3];
2861         u8         srqn_rmpn_xrqn[0x18];
2862
2863         u8         reserved_at_580[0x8];
2864         u8         rmsn[0x18];
2865
2866         u8         hw_sq_wqebb_counter[0x10];
2867         u8         sw_sq_wqebb_counter[0x10];
2868
2869         u8         hw_rq_counter[0x20];
2870
2871         u8         sw_rq_counter[0x20];
2872
2873         u8         reserved_at_600[0x20];
2874
2875         u8         reserved_at_620[0xf];
2876         u8         cgs[0x1];
2877         u8         cs_req[0x8];
2878         u8         cs_res[0x8];
2879
2880         u8         dc_access_key[0x40];
2881
2882         u8         reserved_at_680[0x3];
2883         u8         dbr_umem_valid[0x1];
2884
2885         u8         reserved_at_684[0xbc];
2886 };
2887
2888 struct mlx5_ifc_roce_addr_layout_bits {
2889         u8         source_l3_address[16][0x8];
2890
2891         u8         reserved_at_80[0x3];
2892         u8         vlan_valid[0x1];
2893         u8         vlan_id[0xc];
2894         u8         source_mac_47_32[0x10];
2895
2896         u8         source_mac_31_0[0x20];
2897
2898         u8         reserved_at_c0[0x14];
2899         u8         roce_l3_type[0x4];
2900         u8         roce_version[0x8];
2901
2902         u8         reserved_at_e0[0x20];
2903 };
2904
2905 union mlx5_ifc_hca_cap_union_bits {
2906         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2907         struct mlx5_ifc_odp_cap_bits odp_cap;
2908         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2909         struct mlx5_ifc_roce_cap_bits roce_cap;
2910         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2911         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2912         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2913         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2914         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2915         struct mlx5_ifc_qos_cap_bits qos_cap;
2916         struct mlx5_ifc_debug_cap_bits debug_cap;
2917         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2918         struct mlx5_ifc_tls_cap_bits tls_cap;
2919         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2920         struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2921         u8         reserved_at_0[0x8000];
2922 };
2923
2924 enum {
2925         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2926         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2927         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2928         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2929         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2930         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2931         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2932         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2933         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2934         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2935         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2936 };
2937
2938 enum {
2939         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2940         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2941         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2942 };
2943
2944 struct mlx5_ifc_vlan_bits {
2945         u8         ethtype[0x10];
2946         u8         prio[0x3];
2947         u8         cfi[0x1];
2948         u8         vid[0xc];
2949 };
2950
2951 struct mlx5_ifc_flow_context_bits {
2952         struct mlx5_ifc_vlan_bits push_vlan;
2953
2954         u8         group_id[0x20];
2955
2956         u8         reserved_at_40[0x8];
2957         u8         flow_tag[0x18];
2958
2959         u8         reserved_at_60[0x10];
2960         u8         action[0x10];
2961
2962         u8         extended_destination[0x1];
2963         u8         reserved_at_81[0x1];
2964         u8         flow_source[0x2];
2965         u8         reserved_at_84[0x4];
2966         u8         destination_list_size[0x18];
2967
2968         u8         reserved_at_a0[0x8];
2969         u8         flow_counter_list_size[0x18];
2970
2971         u8         packet_reformat_id[0x20];
2972
2973         u8         modify_header_id[0x20];
2974
2975         struct mlx5_ifc_vlan_bits push_vlan_2;
2976
2977         u8         reserved_at_120[0xe0];
2978
2979         struct mlx5_ifc_fte_match_param_bits match_value;
2980
2981         u8         reserved_at_1200[0x600];
2982
2983         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2984 };
2985
2986 enum {
2987         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2988         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2989 };
2990
2991 struct mlx5_ifc_xrc_srqc_bits {
2992         u8         state[0x4];
2993         u8         log_xrc_srq_size[0x4];
2994         u8         reserved_at_8[0x18];
2995
2996         u8         wq_signature[0x1];
2997         u8         cont_srq[0x1];
2998         u8         reserved_at_22[0x1];
2999         u8         rlky[0x1];
3000         u8         basic_cyclic_rcv_wqe[0x1];
3001         u8         log_rq_stride[0x3];
3002         u8         xrcd[0x18];
3003
3004         u8         page_offset[0x6];
3005         u8         reserved_at_46[0x1];
3006         u8         dbr_umem_valid[0x1];
3007         u8         cqn[0x18];
3008
3009         u8         reserved_at_60[0x20];
3010
3011         u8         user_index_equal_xrc_srqn[0x1];
3012         u8         reserved_at_81[0x1];
3013         u8         log_page_size[0x6];
3014         u8         user_index[0x18];
3015
3016         u8         reserved_at_a0[0x20];
3017
3018         u8         reserved_at_c0[0x8];
3019         u8         pd[0x18];
3020
3021         u8         lwm[0x10];
3022         u8         wqe_cnt[0x10];
3023
3024         u8         reserved_at_100[0x40];
3025
3026         u8         db_record_addr_h[0x20];
3027
3028         u8         db_record_addr_l[0x1e];
3029         u8         reserved_at_17e[0x2];
3030
3031         u8         reserved_at_180[0x80];
3032 };
3033
3034 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3035         u8         counter_error_queues[0x20];
3036
3037         u8         total_error_queues[0x20];
3038
3039         u8         send_queue_priority_update_flow[0x20];
3040
3041         u8         reserved_at_60[0x20];
3042
3043         u8         nic_receive_steering_discard[0x40];
3044
3045         u8         receive_discard_vport_down[0x40];
3046
3047         u8         transmit_discard_vport_down[0x40];
3048
3049         u8         reserved_at_140[0xa0];
3050
3051         u8         internal_rq_out_of_buffer[0x20];
3052
3053         u8         reserved_at_200[0xe00];
3054 };
3055
3056 struct mlx5_ifc_traffic_counter_bits {
3057         u8         packets[0x40];
3058
3059         u8         octets[0x40];
3060 };
3061
3062 struct mlx5_ifc_tisc_bits {
3063         u8         strict_lag_tx_port_affinity[0x1];
3064         u8         tls_en[0x1];
3065         u8         reserved_at_2[0x2];
3066         u8         lag_tx_port_affinity[0x04];
3067
3068         u8         reserved_at_8[0x4];
3069         u8         prio[0x4];
3070         u8         reserved_at_10[0x10];
3071
3072         u8         reserved_at_20[0x100];
3073
3074         u8         reserved_at_120[0x8];
3075         u8         transport_domain[0x18];
3076
3077         u8         reserved_at_140[0x8];
3078         u8         underlay_qpn[0x18];
3079
3080         u8         reserved_at_160[0x8];
3081         u8         pd[0x18];
3082
3083         u8         reserved_at_180[0x380];
3084 };
3085
3086 enum {
3087         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3088         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3089 };
3090
3091 enum {
3092         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3093         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3094 };
3095
3096 enum {
3097         MLX5_RX_HASH_FN_NONE           = 0x0,
3098         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3099         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3100 };
3101
3102 enum {
3103         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3104         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3105 };
3106
3107 struct mlx5_ifc_tirc_bits {
3108         u8         reserved_at_0[0x20];
3109
3110         u8         disp_type[0x4];
3111         u8         reserved_at_24[0x1c];
3112
3113         u8         reserved_at_40[0x40];
3114
3115         u8         reserved_at_80[0x4];
3116         u8         lro_timeout_period_usecs[0x10];
3117         u8         lro_enable_mask[0x4];
3118         u8         lro_max_ip_payload_size[0x8];
3119
3120         u8         reserved_at_a0[0x40];
3121
3122         u8         reserved_at_e0[0x8];
3123         u8         inline_rqn[0x18];
3124
3125         u8         rx_hash_symmetric[0x1];
3126         u8         reserved_at_101[0x1];
3127         u8         tunneled_offload_en[0x1];
3128         u8         reserved_at_103[0x5];
3129         u8         indirect_table[0x18];
3130
3131         u8         rx_hash_fn[0x4];
3132         u8         reserved_at_124[0x2];
3133         u8         self_lb_block[0x2];
3134         u8         transport_domain[0x18];
3135
3136         u8         rx_hash_toeplitz_key[10][0x20];
3137
3138         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3139
3140         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3141
3142         u8         reserved_at_2c0[0x4c0];
3143 };
3144
3145 enum {
3146         MLX5_SRQC_STATE_GOOD   = 0x0,
3147         MLX5_SRQC_STATE_ERROR  = 0x1,
3148 };
3149
3150 struct mlx5_ifc_srqc_bits {
3151         u8         state[0x4];
3152         u8         log_srq_size[0x4];
3153         u8         reserved_at_8[0x18];
3154
3155         u8         wq_signature[0x1];
3156         u8         cont_srq[0x1];
3157         u8         reserved_at_22[0x1];
3158         u8         rlky[0x1];
3159         u8         reserved_at_24[0x1];
3160         u8         log_rq_stride[0x3];
3161         u8         xrcd[0x18];
3162
3163         u8         page_offset[0x6];
3164         u8         reserved_at_46[0x2];
3165         u8         cqn[0x18];
3166
3167         u8         reserved_at_60[0x20];
3168
3169         u8         reserved_at_80[0x2];
3170         u8         log_page_size[0x6];
3171         u8         reserved_at_88[0x18];
3172
3173         u8         reserved_at_a0[0x20];
3174
3175         u8         reserved_at_c0[0x8];
3176         u8         pd[0x18];
3177
3178         u8         lwm[0x10];
3179         u8         wqe_cnt[0x10];
3180
3181         u8         reserved_at_100[0x40];
3182
3183         u8         dbr_addr[0x40];
3184
3185         u8         reserved_at_180[0x80];
3186 };
3187
3188 enum {
3189         MLX5_SQC_STATE_RST  = 0x0,
3190         MLX5_SQC_STATE_RDY  = 0x1,
3191         MLX5_SQC_STATE_ERR  = 0x3,
3192 };
3193
3194 struct mlx5_ifc_sqc_bits {
3195         u8         rlky[0x1];
3196         u8         cd_master[0x1];
3197         u8         fre[0x1];
3198         u8         flush_in_error_en[0x1];
3199         u8         allow_multi_pkt_send_wqe[0x1];
3200         u8         min_wqe_inline_mode[0x3];
3201         u8         state[0x4];
3202         u8         reg_umr[0x1];
3203         u8         allow_swp[0x1];
3204         u8         hairpin[0x1];
3205         u8         reserved_at_f[0x11];
3206
3207         u8         reserved_at_20[0x8];
3208         u8         user_index[0x18];
3209
3210         u8         reserved_at_40[0x8];
3211         u8         cqn[0x18];
3212
3213         u8         reserved_at_60[0x8];
3214         u8         hairpin_peer_rq[0x18];
3215
3216         u8         reserved_at_80[0x10];
3217         u8         hairpin_peer_vhca[0x10];
3218
3219         u8         reserved_at_a0[0x50];
3220
3221         u8         packet_pacing_rate_limit_index[0x10];
3222         u8         tis_lst_sz[0x10];
3223         u8         reserved_at_110[0x10];
3224
3225         u8         reserved_at_120[0x40];
3226
3227         u8         reserved_at_160[0x8];
3228         u8         tis_num_0[0x18];
3229
3230         struct mlx5_ifc_wq_bits wq;
3231 };
3232
3233 enum {
3234         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3235         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3236         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3237         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3238 };
3239
3240 enum {
3241         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3242         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3243         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3244         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3245 };
3246
3247 struct mlx5_ifc_scheduling_context_bits {
3248         u8         element_type[0x8];
3249         u8         reserved_at_8[0x18];
3250
3251         u8         element_attributes[0x20];
3252
3253         u8         parent_element_id[0x20];
3254
3255         u8         reserved_at_60[0x40];
3256
3257         u8         bw_share[0x20];
3258
3259         u8         max_average_bw[0x20];
3260
3261         u8         reserved_at_e0[0x120];
3262 };
3263
3264 struct mlx5_ifc_rqtc_bits {
3265         u8         reserved_at_0[0xa0];
3266
3267         u8         reserved_at_a0[0x10];
3268         u8         rqt_max_size[0x10];
3269
3270         u8         reserved_at_c0[0x10];
3271         u8         rqt_actual_size[0x10];
3272
3273         u8         reserved_at_e0[0x6a0];
3274
3275         struct mlx5_ifc_rq_num_bits rq_num[0];
3276 };
3277
3278 enum {
3279         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3280         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3281 };
3282
3283 enum {
3284         MLX5_RQC_STATE_RST  = 0x0,
3285         MLX5_RQC_STATE_RDY  = 0x1,
3286         MLX5_RQC_STATE_ERR  = 0x3,
3287 };
3288
3289 struct mlx5_ifc_rqc_bits {
3290         u8         rlky[0x1];
3291         u8         delay_drop_en[0x1];
3292         u8         scatter_fcs[0x1];
3293         u8         vsd[0x1];
3294         u8         mem_rq_type[0x4];
3295         u8         state[0x4];
3296         u8         reserved_at_c[0x1];
3297         u8         flush_in_error_en[0x1];
3298         u8         hairpin[0x1];
3299         u8         reserved_at_f[0x11];
3300
3301         u8         reserved_at_20[0x8];
3302         u8         user_index[0x18];
3303
3304         u8         reserved_at_40[0x8];
3305         u8         cqn[0x18];
3306
3307         u8         counter_set_id[0x8];
3308         u8         reserved_at_68[0x18];
3309
3310         u8         reserved_at_80[0x8];
3311         u8         rmpn[0x18];
3312
3313         u8         reserved_at_a0[0x8];
3314         u8         hairpin_peer_sq[0x18];
3315
3316         u8         reserved_at_c0[0x10];
3317         u8         hairpin_peer_vhca[0x10];
3318
3319         u8         reserved_at_e0[0xa0];
3320
3321         struct mlx5_ifc_wq_bits wq;
3322 };
3323
3324 enum {
3325         MLX5_RMPC_STATE_RDY  = 0x1,
3326         MLX5_RMPC_STATE_ERR  = 0x3,
3327 };
3328
3329 struct mlx5_ifc_rmpc_bits {
3330         u8         reserved_at_0[0x8];
3331         u8         state[0x4];
3332         u8         reserved_at_c[0x14];
3333
3334         u8         basic_cyclic_rcv_wqe[0x1];
3335         u8         reserved_at_21[0x1f];
3336
3337         u8         reserved_at_40[0x140];
3338
3339         struct mlx5_ifc_wq_bits wq;
3340 };
3341
3342 struct mlx5_ifc_nic_vport_context_bits {
3343         u8         reserved_at_0[0x5];
3344         u8         min_wqe_inline_mode[0x3];
3345         u8         reserved_at_8[0x15];
3346         u8         disable_mc_local_lb[0x1];
3347         u8         disable_uc_local_lb[0x1];
3348         u8         roce_en[0x1];
3349
3350         u8         arm_change_event[0x1];
3351         u8         reserved_at_21[0x1a];
3352         u8         event_on_mtu[0x1];
3353         u8         event_on_promisc_change[0x1];
3354         u8         event_on_vlan_change[0x1];
3355         u8         event_on_mc_address_change[0x1];
3356         u8         event_on_uc_address_change[0x1];
3357
3358         u8         reserved_at_40[0xc];
3359
3360         u8         affiliation_criteria[0x4];
3361         u8         affiliated_vhca_id[0x10];
3362
3363         u8         reserved_at_60[0xd0];
3364
3365         u8         mtu[0x10];
3366
3367         u8         system_image_guid[0x40];
3368         u8         port_guid[0x40];
3369         u8         node_guid[0x40];
3370
3371         u8         reserved_at_200[0x140];
3372         u8         qkey_violation_counter[0x10];
3373         u8         reserved_at_350[0x430];
3374
3375         u8         promisc_uc[0x1];
3376         u8         promisc_mc[0x1];
3377         u8         promisc_all[0x1];
3378         u8         reserved_at_783[0x2];
3379         u8         allowed_list_type[0x3];
3380         u8         reserved_at_788[0xc];
3381         u8         allowed_list_size[0xc];
3382
3383         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3384
3385         u8         reserved_at_7e0[0x20];
3386
3387         u8         current_uc_mac_address[0][0x40];
3388 };
3389
3390 enum {
3391         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3392         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3393         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3394         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3395         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3396         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3397 };
3398
3399 struct mlx5_ifc_mkc_bits {
3400         u8         reserved_at_0[0x1];
3401         u8         free[0x1];
3402         u8         reserved_at_2[0x1];
3403         u8         access_mode_4_2[0x3];
3404         u8         reserved_at_6[0x7];
3405         u8         relaxed_ordering_write[0x1];
3406         u8         reserved_at_e[0x1];
3407         u8         small_fence_on_rdma_read_response[0x1];
3408         u8         umr_en[0x1];
3409         u8         a[0x1];
3410         u8         rw[0x1];
3411         u8         rr[0x1];
3412         u8         lw[0x1];
3413         u8         lr[0x1];
3414         u8         access_mode_1_0[0x2];
3415         u8         reserved_at_18[0x8];
3416
3417         u8         qpn[0x18];
3418         u8         mkey_7_0[0x8];
3419
3420         u8         reserved_at_40[0x20];
3421
3422         u8         length64[0x1];
3423         u8         bsf_en[0x1];
3424         u8         sync_umr[0x1];
3425         u8         reserved_at_63[0x2];
3426         u8         expected_sigerr_count[0x1];
3427         u8         reserved_at_66[0x1];
3428         u8         en_rinval[0x1];
3429         u8         pd[0x18];
3430
3431         u8         start_addr[0x40];
3432
3433         u8         len[0x40];
3434
3435         u8         bsf_octword_size[0x20];
3436
3437         u8         reserved_at_120[0x80];
3438
3439         u8         translations_octword_size[0x20];
3440
3441         u8         reserved_at_1c0[0x19];
3442         u8         relaxed_ordering_read[0x1];
3443         u8         reserved_at_1d9[0x1];
3444         u8         log_page_size[0x5];
3445
3446         u8         reserved_at_1e0[0x20];
3447 };
3448
3449 struct mlx5_ifc_pkey_bits {
3450         u8         reserved_at_0[0x10];
3451         u8         pkey[0x10];
3452 };
3453
3454 struct mlx5_ifc_array128_auto_bits {
3455         u8         array128_auto[16][0x8];
3456 };
3457
3458 struct mlx5_ifc_hca_vport_context_bits {
3459         u8         field_select[0x20];
3460
3461         u8         reserved_at_20[0xe0];
3462
3463         u8         sm_virt_aware[0x1];
3464         u8         has_smi[0x1];
3465         u8         has_raw[0x1];
3466         u8         grh_required[0x1];
3467         u8         reserved_at_104[0xc];
3468         u8         port_physical_state[0x4];
3469         u8         vport_state_policy[0x4];
3470         u8         port_state[0x4];
3471         u8         vport_state[0x4];
3472
3473         u8         reserved_at_120[0x20];
3474
3475         u8         system_image_guid[0x40];
3476
3477         u8         port_guid[0x40];
3478
3479         u8         node_guid[0x40];
3480
3481         u8         cap_mask1[0x20];
3482
3483         u8         cap_mask1_field_select[0x20];
3484
3485         u8         cap_mask2[0x20];
3486
3487         u8         cap_mask2_field_select[0x20];
3488
3489         u8         reserved_at_280[0x80];
3490
3491         u8         lid[0x10];
3492         u8         reserved_at_310[0x4];
3493         u8         init_type_reply[0x4];
3494         u8         lmc[0x3];
3495         u8         subnet_timeout[0x5];
3496
3497         u8         sm_lid[0x10];
3498         u8         sm_sl[0x4];
3499         u8         reserved_at_334[0xc];
3500
3501         u8         qkey_violation_counter[0x10];
3502         u8         pkey_violation_counter[0x10];
3503
3504         u8         reserved_at_360[0xca0];
3505 };
3506
3507 struct mlx5_ifc_esw_vport_context_bits {
3508         u8         fdb_to_vport_reg_c[0x1];
3509         u8         reserved_at_1[0x2];
3510         u8         vport_svlan_strip[0x1];
3511         u8         vport_cvlan_strip[0x1];
3512         u8         vport_svlan_insert[0x1];
3513         u8         vport_cvlan_insert[0x2];
3514         u8         fdb_to_vport_reg_c_id[0x8];
3515         u8         reserved_at_10[0x10];
3516
3517         u8         reserved_at_20[0x20];
3518
3519         u8         svlan_cfi[0x1];
3520         u8         svlan_pcp[0x3];
3521         u8         svlan_id[0xc];
3522         u8         cvlan_cfi[0x1];
3523         u8         cvlan_pcp[0x3];
3524         u8         cvlan_id[0xc];
3525
3526         u8         reserved_at_60[0x720];
3527
3528         u8         sw_steering_vport_icm_address_rx[0x40];
3529
3530         u8         sw_steering_vport_icm_address_tx[0x40];
3531 };
3532
3533 enum {
3534         MLX5_EQC_STATUS_OK                = 0x0,
3535         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3536 };
3537
3538 enum {
3539         MLX5_EQC_ST_ARMED  = 0x9,
3540         MLX5_EQC_ST_FIRED  = 0xa,
3541 };
3542
3543 struct mlx5_ifc_eqc_bits {
3544         u8         status[0x4];
3545         u8         reserved_at_4[0x9];
3546         u8         ec[0x1];
3547         u8         oi[0x1];
3548         u8         reserved_at_f[0x5];
3549         u8         st[0x4];
3550         u8         reserved_at_18[0x8];
3551
3552         u8         reserved_at_20[0x20];
3553
3554         u8         reserved_at_40[0x14];
3555         u8         page_offset[0x6];
3556         u8         reserved_at_5a[0x6];
3557
3558         u8         reserved_at_60[0x3];
3559         u8         log_eq_size[0x5];
3560         u8         uar_page[0x18];
3561
3562         u8         reserved_at_80[0x20];
3563
3564         u8         reserved_at_a0[0x18];
3565         u8         intr[0x8];
3566
3567         u8         reserved_at_c0[0x3];
3568         u8         log_page_size[0x5];
3569         u8         reserved_at_c8[0x18];
3570
3571         u8         reserved_at_e0[0x60];
3572
3573         u8         reserved_at_140[0x8];
3574         u8         consumer_counter[0x18];
3575
3576         u8         reserved_at_160[0x8];
3577         u8         producer_counter[0x18];
3578
3579         u8         reserved_at_180[0x80];
3580 };
3581
3582 enum {
3583         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3584         MLX5_DCTC_STATE_DRAINING  = 0x1,
3585         MLX5_DCTC_STATE_DRAINED   = 0x2,
3586 };
3587
3588 enum {
3589         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3590         MLX5_DCTC_CS_RES_NA         = 0x1,
3591         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3592 };
3593
3594 enum {
3595         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3596         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3597         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3598         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3599         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3600 };
3601
3602 struct mlx5_ifc_dctc_bits {
3603         u8         reserved_at_0[0x4];
3604         u8         state[0x4];
3605         u8         reserved_at_8[0x18];
3606
3607         u8         reserved_at_20[0x8];
3608         u8         user_index[0x18];
3609
3610         u8         reserved_at_40[0x8];
3611         u8         cqn[0x18];
3612
3613         u8         counter_set_id[0x8];
3614         u8         atomic_mode[0x4];
3615         u8         rre[0x1];
3616         u8         rwe[0x1];
3617         u8         rae[0x1];
3618         u8         atomic_like_write_en[0x1];
3619         u8         latency_sensitive[0x1];
3620         u8         rlky[0x1];
3621         u8         free_ar[0x1];
3622         u8         reserved_at_73[0xd];
3623
3624         u8         reserved_at_80[0x8];
3625         u8         cs_res[0x8];
3626         u8         reserved_at_90[0x3];
3627         u8         min_rnr_nak[0x5];
3628         u8         reserved_at_98[0x8];
3629
3630         u8         reserved_at_a0[0x8];
3631         u8         srqn_xrqn[0x18];
3632
3633         u8         reserved_at_c0[0x8];
3634         u8         pd[0x18];
3635
3636         u8         tclass[0x8];
3637         u8         reserved_at_e8[0x4];
3638         u8         flow_label[0x14];
3639
3640         u8         dc_access_key[0x40];
3641
3642         u8         reserved_at_140[0x5];
3643         u8         mtu[0x3];
3644         u8         port[0x8];
3645         u8         pkey_index[0x10];
3646
3647         u8         reserved_at_160[0x8];
3648         u8         my_addr_index[0x8];
3649         u8         reserved_at_170[0x8];
3650         u8         hop_limit[0x8];
3651
3652         u8         dc_access_key_violation_count[0x20];
3653
3654         u8         reserved_at_1a0[0x14];
3655         u8         dei_cfi[0x1];
3656         u8         eth_prio[0x3];
3657         u8         ecn[0x2];
3658         u8         dscp[0x6];
3659
3660         u8         reserved_at_1c0[0x40];
3661 };
3662
3663 enum {
3664         MLX5_CQC_STATUS_OK             = 0x0,
3665         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3666         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3667 };
3668
3669 enum {
3670         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3671         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3672 };
3673
3674 enum {
3675         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3676         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3677         MLX5_CQC_ST_FIRED                                 = 0xa,
3678 };
3679
3680 enum {
3681         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3682         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3683         MLX5_CQ_PERIOD_NUM_MODES
3684 };
3685
3686 struct mlx5_ifc_cqc_bits {
3687         u8         status[0x4];
3688         u8         reserved_at_4[0x2];
3689         u8         dbr_umem_valid[0x1];
3690         u8         reserved_at_7[0x1];
3691         u8         cqe_sz[0x3];
3692         u8         cc[0x1];
3693         u8         reserved_at_c[0x1];
3694         u8         scqe_break_moderation_en[0x1];
3695         u8         oi[0x1];
3696         u8         cq_period_mode[0x2];
3697         u8         cqe_comp_en[0x1];
3698         u8         mini_cqe_res_format[0x2];
3699         u8         st[0x4];
3700         u8         reserved_at_18[0x8];
3701
3702         u8         reserved_at_20[0x20];
3703
3704         u8         reserved_at_40[0x14];
3705         u8         page_offset[0x6];
3706         u8         reserved_at_5a[0x6];
3707
3708         u8         reserved_at_60[0x3];
3709         u8         log_cq_size[0x5];
3710         u8         uar_page[0x18];
3711
3712         u8         reserved_at_80[0x4];
3713         u8         cq_period[0xc];
3714         u8         cq_max_count[0x10];
3715
3716         u8         reserved_at_a0[0x18];
3717         u8         c_eqn[0x8];
3718
3719         u8         reserved_at_c0[0x3];
3720         u8         log_page_size[0x5];
3721         u8         reserved_at_c8[0x18];
3722
3723         u8         reserved_at_e0[0x20];
3724
3725         u8         reserved_at_100[0x8];
3726         u8         last_notified_index[0x18];
3727
3728         u8         reserved_at_120[0x8];
3729         u8         last_solicit_index[0x18];
3730
3731         u8         reserved_at_140[0x8];
3732         u8         consumer_counter[0x18];
3733
3734         u8         reserved_at_160[0x8];
3735         u8         producer_counter[0x18];
3736
3737         u8         reserved_at_180[0x40];
3738
3739         u8         dbr_addr[0x40];
3740 };
3741
3742 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3743         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3744         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3745         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3746         u8         reserved_at_0[0x800];
3747 };
3748
3749 struct mlx5_ifc_query_adapter_param_block_bits {
3750         u8         reserved_at_0[0xc0];
3751
3752         u8         reserved_at_c0[0x8];
3753         u8         ieee_vendor_id[0x18];
3754
3755         u8         reserved_at_e0[0x10];
3756         u8         vsd_vendor_id[0x10];
3757
3758         u8         vsd[208][0x8];
3759
3760         u8         vsd_contd_psid[16][0x8];
3761 };
3762
3763 enum {
3764         MLX5_XRQC_STATE_GOOD   = 0x0,
3765         MLX5_XRQC_STATE_ERROR  = 0x1,
3766 };
3767
3768 enum {
3769         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3770         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3771 };
3772
3773 enum {
3774         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3775 };
3776
3777 struct mlx5_ifc_tag_matching_topology_context_bits {
3778         u8         log_matching_list_sz[0x4];
3779         u8         reserved_at_4[0xc];
3780         u8         append_next_index[0x10];
3781
3782         u8         sw_phase_cnt[0x10];
3783         u8         hw_phase_cnt[0x10];
3784
3785         u8         reserved_at_40[0x40];
3786 };
3787
3788 struct mlx5_ifc_xrqc_bits {
3789         u8         state[0x4];
3790         u8         rlkey[0x1];
3791         u8         reserved_at_5[0xf];
3792         u8         topology[0x4];
3793         u8         reserved_at_18[0x4];
3794         u8         offload[0x4];
3795
3796         u8         reserved_at_20[0x8];
3797         u8         user_index[0x18];
3798
3799         u8         reserved_at_40[0x8];
3800         u8         cqn[0x18];
3801
3802         u8         reserved_at_60[0xa0];
3803
3804         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3805
3806         u8         reserved_at_180[0x280];
3807
3808         struct mlx5_ifc_wq_bits wq;
3809 };
3810
3811 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3812         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3813         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3814         u8         reserved_at_0[0x20];
3815 };
3816
3817 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3818         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3819         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3820         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3821         u8         reserved_at_0[0x20];
3822 };
3823
3824 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3825         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3826         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3827         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3828         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3829         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3830         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3831         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3832         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3833         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3834         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3835         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3836         u8         reserved_at_0[0x7c0];
3837 };
3838
3839 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3840         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3841         u8         reserved_at_0[0x7c0];
3842 };
3843
3844 union mlx5_ifc_event_auto_bits {
3845         struct mlx5_ifc_comp_event_bits comp_event;
3846         struct mlx5_ifc_dct_events_bits dct_events;
3847         struct mlx5_ifc_qp_events_bits qp_events;
3848         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3849         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3850         struct mlx5_ifc_cq_error_bits cq_error;
3851         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3852         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3853         struct mlx5_ifc_gpio_event_bits gpio_event;
3854         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3855         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3856         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3857         u8         reserved_at_0[0xe0];
3858 };
3859
3860 struct mlx5_ifc_health_buffer_bits {
3861         u8         reserved_at_0[0x100];
3862
3863         u8         assert_existptr[0x20];
3864
3865         u8         assert_callra[0x20];
3866
3867         u8         reserved_at_140[0x40];
3868
3869         u8         fw_version[0x20];
3870
3871         u8         hw_id[0x20];
3872
3873         u8         reserved_at_1c0[0x20];
3874
3875         u8         irisc_index[0x8];
3876         u8         synd[0x8];
3877         u8         ext_synd[0x10];
3878 };
3879
3880 struct mlx5_ifc_register_loopback_control_bits {
3881         u8         no_lb[0x1];
3882         u8         reserved_at_1[0x7];
3883         u8         port[0x8];
3884         u8         reserved_at_10[0x10];
3885
3886         u8         reserved_at_20[0x60];
3887 };
3888
3889 struct mlx5_ifc_vport_tc_element_bits {
3890         u8         traffic_class[0x4];
3891         u8         reserved_at_4[0xc];
3892         u8         vport_number[0x10];
3893 };
3894
3895 struct mlx5_ifc_vport_element_bits {
3896         u8         reserved_at_0[0x10];
3897         u8         vport_number[0x10];
3898 };
3899
3900 enum {
3901         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3902         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3903         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3904 };
3905
3906 struct mlx5_ifc_tsar_element_bits {
3907         u8         reserved_at_0[0x8];
3908         u8         tsar_type[0x8];
3909         u8         reserved_at_10[0x10];
3910 };
3911
3912 enum {
3913         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3914         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3915 };
3916
3917 struct mlx5_ifc_teardown_hca_out_bits {
3918         u8         status[0x8];
3919         u8         reserved_at_8[0x18];
3920
3921         u8         syndrome[0x20];
3922
3923         u8         reserved_at_40[0x3f];
3924
3925         u8         state[0x1];
3926 };
3927
3928 enum {
3929         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3930         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3931         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3932 };
3933
3934 struct mlx5_ifc_teardown_hca_in_bits {
3935         u8         opcode[0x10];
3936         u8         reserved_at_10[0x10];
3937
3938         u8         reserved_at_20[0x10];
3939         u8         op_mod[0x10];
3940
3941         u8         reserved_at_40[0x10];
3942         u8         profile[0x10];
3943
3944         u8         reserved_at_60[0x20];
3945 };
3946
3947 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3948         u8         status[0x8];
3949         u8         reserved_at_8[0x18];
3950
3951         u8         syndrome[0x20];
3952
3953         u8         reserved_at_40[0x40];
3954 };
3955
3956 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3957         u8         opcode[0x10];
3958         u8         uid[0x10];
3959
3960         u8         reserved_at_20[0x10];
3961         u8         op_mod[0x10];
3962
3963         u8         reserved_at_40[0x8];
3964         u8         qpn[0x18];
3965
3966         u8         reserved_at_60[0x20];
3967
3968         u8         opt_param_mask[0x20];
3969
3970         u8         reserved_at_a0[0x20];
3971
3972         struct mlx5_ifc_qpc_bits qpc;
3973
3974         u8         reserved_at_800[0x80];
3975 };
3976
3977 struct mlx5_ifc_sqd2rts_qp_out_bits {
3978         u8         status[0x8];
3979         u8         reserved_at_8[0x18];
3980
3981         u8         syndrome[0x20];
3982
3983         u8         reserved_at_40[0x40];
3984 };
3985
3986 struct mlx5_ifc_sqd2rts_qp_in_bits {
3987         u8         opcode[0x10];
3988         u8         uid[0x10];
3989
3990         u8         reserved_at_20[0x10];
3991         u8         op_mod[0x10];
3992
3993         u8         reserved_at_40[0x8];
3994         u8         qpn[0x18];
3995
3996         u8         reserved_at_60[0x20];
3997
3998         u8         opt_param_mask[0x20];
3999
4000         u8         reserved_at_a0[0x20];
4001
4002         struct mlx5_ifc_qpc_bits qpc;
4003
4004         u8         reserved_at_800[0x80];
4005 };
4006
4007 struct mlx5_ifc_set_roce_address_out_bits {
4008         u8         status[0x8];
4009         u8         reserved_at_8[0x18];
4010
4011         u8         syndrome[0x20];
4012
4013         u8         reserved_at_40[0x40];
4014 };
4015
4016 struct mlx5_ifc_set_roce_address_in_bits {
4017         u8         opcode[0x10];
4018         u8         reserved_at_10[0x10];
4019
4020         u8         reserved_at_20[0x10];
4021         u8         op_mod[0x10];
4022
4023         u8         roce_address_index[0x10];
4024         u8         reserved_at_50[0xc];
4025         u8         vhca_port_num[0x4];
4026
4027         u8         reserved_at_60[0x20];
4028
4029         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4030 };
4031
4032 struct mlx5_ifc_set_mad_demux_out_bits {
4033         u8         status[0x8];
4034         u8         reserved_at_8[0x18];
4035
4036         u8         syndrome[0x20];
4037
4038         u8         reserved_at_40[0x40];
4039 };
4040
4041 enum {
4042         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4043         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4044 };
4045
4046 struct mlx5_ifc_set_mad_demux_in_bits {
4047         u8         opcode[0x10];
4048         u8         reserved_at_10[0x10];
4049
4050         u8         reserved_at_20[0x10];
4051         u8         op_mod[0x10];
4052
4053         u8         reserved_at_40[0x20];
4054
4055         u8         reserved_at_60[0x6];
4056         u8         demux_mode[0x2];
4057         u8         reserved_at_68[0x18];
4058 };
4059
4060 struct mlx5_ifc_set_l2_table_entry_out_bits {
4061         u8         status[0x8];
4062         u8         reserved_at_8[0x18];
4063
4064         u8         syndrome[0x20];
4065
4066         u8         reserved_at_40[0x40];
4067 };
4068
4069 struct mlx5_ifc_set_l2_table_entry_in_bits {
4070         u8         opcode[0x10];
4071         u8         reserved_at_10[0x10];
4072
4073         u8         reserved_at_20[0x10];
4074         u8         op_mod[0x10];
4075
4076         u8         reserved_at_40[0x60];
4077
4078         u8         reserved_at_a0[0x8];
4079         u8         table_index[0x18];
4080
4081         u8         reserved_at_c0[0x20];
4082
4083         u8         reserved_at_e0[0x13];
4084         u8         vlan_valid[0x1];
4085         u8         vlan[0xc];
4086
4087         struct mlx5_ifc_mac_address_layout_bits mac_address;
4088
4089         u8         reserved_at_140[0xc0];
4090 };
4091
4092 struct mlx5_ifc_set_issi_out_bits {
4093         u8         status[0x8];
4094         u8         reserved_at_8[0x18];
4095
4096         u8         syndrome[0x20];
4097
4098         u8         reserved_at_40[0x40];
4099 };
4100
4101 struct mlx5_ifc_set_issi_in_bits {
4102         u8         opcode[0x10];
4103         u8         reserved_at_10[0x10];
4104
4105         u8         reserved_at_20[0x10];
4106         u8         op_mod[0x10];
4107
4108         u8         reserved_at_40[0x10];
4109         u8         current_issi[0x10];
4110
4111         u8         reserved_at_60[0x20];
4112 };
4113
4114 struct mlx5_ifc_set_hca_cap_out_bits {
4115         u8         status[0x8];
4116         u8         reserved_at_8[0x18];
4117
4118         u8         syndrome[0x20];
4119
4120         u8         reserved_at_40[0x40];
4121 };
4122
4123 struct mlx5_ifc_set_hca_cap_in_bits {
4124         u8         opcode[0x10];
4125         u8         reserved_at_10[0x10];
4126
4127         u8         reserved_at_20[0x10];
4128         u8         op_mod[0x10];
4129
4130         u8         reserved_at_40[0x40];
4131
4132         union mlx5_ifc_hca_cap_union_bits capability;
4133 };
4134
4135 enum {
4136         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4137         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4138         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4139         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
4140 };
4141
4142 struct mlx5_ifc_set_fte_out_bits {
4143         u8         status[0x8];
4144         u8         reserved_at_8[0x18];
4145
4146         u8         syndrome[0x20];
4147
4148         u8         reserved_at_40[0x40];
4149 };
4150
4151 struct mlx5_ifc_set_fte_in_bits {
4152         u8         opcode[0x10];
4153         u8         reserved_at_10[0x10];
4154
4155         u8         reserved_at_20[0x10];
4156         u8         op_mod[0x10];
4157
4158         u8         other_vport[0x1];
4159         u8         reserved_at_41[0xf];
4160         u8         vport_number[0x10];
4161
4162         u8         reserved_at_60[0x20];
4163
4164         u8         table_type[0x8];
4165         u8         reserved_at_88[0x18];
4166
4167         u8         reserved_at_a0[0x8];
4168         u8         table_id[0x18];
4169
4170         u8         ignore_flow_level[0x1];
4171         u8         reserved_at_c1[0x17];
4172         u8         modify_enable_mask[0x8];
4173
4174         u8         reserved_at_e0[0x20];
4175
4176         u8         flow_index[0x20];
4177
4178         u8         reserved_at_120[0xe0];
4179
4180         struct mlx5_ifc_flow_context_bits flow_context;
4181 };
4182
4183 struct mlx5_ifc_rts2rts_qp_out_bits {
4184         u8         status[0x8];
4185         u8         reserved_at_8[0x18];
4186
4187         u8         syndrome[0x20];
4188
4189         u8         reserved_at_40[0x40];
4190 };
4191
4192 struct mlx5_ifc_rts2rts_qp_in_bits {
4193         u8         opcode[0x10];
4194         u8         uid[0x10];
4195
4196         u8         reserved_at_20[0x10];
4197         u8         op_mod[0x10];
4198
4199         u8         reserved_at_40[0x8];
4200         u8         qpn[0x18];
4201
4202         u8         reserved_at_60[0x20];
4203
4204         u8         opt_param_mask[0x20];
4205
4206         u8         reserved_at_a0[0x20];
4207
4208         struct mlx5_ifc_qpc_bits qpc;
4209
4210         u8         reserved_at_800[0x80];
4211 };
4212
4213 struct mlx5_ifc_rtr2rts_qp_out_bits {
4214         u8         status[0x8];
4215         u8         reserved_at_8[0x18];
4216
4217         u8         syndrome[0x20];
4218
4219         u8         reserved_at_40[0x40];
4220 };
4221
4222 struct mlx5_ifc_rtr2rts_qp_in_bits {
4223         u8         opcode[0x10];
4224         u8         uid[0x10];
4225
4226         u8         reserved_at_20[0x10];
4227         u8         op_mod[0x10];
4228
4229         u8         reserved_at_40[0x8];
4230         u8         qpn[0x18];
4231
4232         u8         reserved_at_60[0x20];
4233
4234         u8         opt_param_mask[0x20];
4235
4236         u8         reserved_at_a0[0x20];
4237
4238         struct mlx5_ifc_qpc_bits qpc;
4239
4240         u8         reserved_at_800[0x80];
4241 };
4242
4243 struct mlx5_ifc_rst2init_qp_out_bits {
4244         u8         status[0x8];
4245         u8         reserved_at_8[0x18];
4246
4247         u8         syndrome[0x20];
4248
4249         u8         reserved_at_40[0x40];
4250 };
4251
4252 struct mlx5_ifc_rst2init_qp_in_bits {
4253         u8         opcode[0x10];
4254         u8         uid[0x10];
4255
4256         u8         reserved_at_20[0x10];
4257         u8         op_mod[0x10];
4258
4259         u8         reserved_at_40[0x8];
4260         u8         qpn[0x18];
4261
4262         u8         reserved_at_60[0x20];
4263
4264         u8         opt_param_mask[0x20];
4265
4266         u8         reserved_at_a0[0x20];
4267
4268         struct mlx5_ifc_qpc_bits qpc;
4269
4270         u8         reserved_at_800[0x80];
4271 };
4272
4273 struct mlx5_ifc_query_xrq_out_bits {
4274         u8         status[0x8];
4275         u8         reserved_at_8[0x18];
4276
4277         u8         syndrome[0x20];
4278
4279         u8         reserved_at_40[0x40];
4280
4281         struct mlx5_ifc_xrqc_bits xrq_context;
4282 };
4283
4284 struct mlx5_ifc_query_xrq_in_bits {
4285         u8         opcode[0x10];
4286         u8         reserved_at_10[0x10];
4287
4288         u8         reserved_at_20[0x10];
4289         u8         op_mod[0x10];
4290
4291         u8         reserved_at_40[0x8];
4292         u8         xrqn[0x18];
4293
4294         u8         reserved_at_60[0x20];
4295 };
4296
4297 struct mlx5_ifc_query_xrc_srq_out_bits {
4298         u8         status[0x8];
4299         u8         reserved_at_8[0x18];
4300
4301         u8         syndrome[0x20];
4302
4303         u8         reserved_at_40[0x40];
4304
4305         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4306
4307         u8         reserved_at_280[0x600];
4308
4309         u8         pas[0][0x40];
4310 };
4311
4312 struct mlx5_ifc_query_xrc_srq_in_bits {
4313         u8         opcode[0x10];
4314         u8         reserved_at_10[0x10];
4315
4316         u8         reserved_at_20[0x10];
4317         u8         op_mod[0x10];
4318
4319         u8         reserved_at_40[0x8];
4320         u8         xrc_srqn[0x18];
4321
4322         u8         reserved_at_60[0x20];
4323 };
4324
4325 enum {
4326         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4327         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4328 };
4329
4330 struct mlx5_ifc_query_vport_state_out_bits {
4331         u8         status[0x8];
4332         u8         reserved_at_8[0x18];
4333
4334         u8         syndrome[0x20];
4335
4336         u8         reserved_at_40[0x20];
4337
4338         u8         reserved_at_60[0x18];
4339         u8         admin_state[0x4];
4340         u8         state[0x4];
4341 };
4342
4343 enum {
4344         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4345         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4346 };
4347
4348 struct mlx5_ifc_arm_monitor_counter_in_bits {
4349         u8         opcode[0x10];
4350         u8         uid[0x10];
4351
4352         u8         reserved_at_20[0x10];
4353         u8         op_mod[0x10];
4354
4355         u8         reserved_at_40[0x20];
4356
4357         u8         reserved_at_60[0x20];
4358 };
4359
4360 struct mlx5_ifc_arm_monitor_counter_out_bits {
4361         u8         status[0x8];
4362         u8         reserved_at_8[0x18];
4363
4364         u8         syndrome[0x20];
4365
4366         u8         reserved_at_40[0x40];
4367 };
4368
4369 enum {
4370         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4371         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4372 };
4373
4374 enum mlx5_monitor_counter_ppcnt {
4375         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4376         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4377         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4378         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4379         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4380         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4381 };
4382
4383 enum {
4384         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4385 };
4386
4387 struct mlx5_ifc_monitor_counter_output_bits {
4388         u8         reserved_at_0[0x4];
4389         u8         type[0x4];
4390         u8         reserved_at_8[0x8];
4391         u8         counter[0x10];
4392
4393         u8         counter_group_id[0x20];
4394 };
4395
4396 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4397 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4398 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4399                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4400
4401 struct mlx5_ifc_set_monitor_counter_in_bits {
4402         u8         opcode[0x10];
4403         u8         uid[0x10];
4404
4405         u8         reserved_at_20[0x10];
4406         u8         op_mod[0x10];
4407
4408         u8         reserved_at_40[0x10];
4409         u8         num_of_counters[0x10];
4410
4411         u8         reserved_at_60[0x20];
4412
4413         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4414 };
4415
4416 struct mlx5_ifc_set_monitor_counter_out_bits {
4417         u8         status[0x8];
4418         u8         reserved_at_8[0x18];
4419
4420         u8         syndrome[0x20];
4421
4422         u8         reserved_at_40[0x40];
4423 };
4424
4425 struct mlx5_ifc_query_vport_state_in_bits {
4426         u8         opcode[0x10];
4427         u8         reserved_at_10[0x10];
4428
4429         u8         reserved_at_20[0x10];
4430         u8         op_mod[0x10];
4431
4432         u8         other_vport[0x1];
4433         u8         reserved_at_41[0xf];
4434         u8         vport_number[0x10];
4435
4436         u8         reserved_at_60[0x20];
4437 };
4438
4439 struct mlx5_ifc_query_vnic_env_out_bits {
4440         u8         status[0x8];
4441         u8         reserved_at_8[0x18];
4442
4443         u8         syndrome[0x20];
4444
4445         u8         reserved_at_40[0x40];
4446
4447         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4448 };
4449
4450 enum {
4451         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4452 };
4453
4454 struct mlx5_ifc_query_vnic_env_in_bits {
4455         u8         opcode[0x10];
4456         u8         reserved_at_10[0x10];
4457
4458         u8         reserved_at_20[0x10];
4459         u8         op_mod[0x10];
4460
4461         u8         other_vport[0x1];
4462         u8         reserved_at_41[0xf];
4463         u8         vport_number[0x10];
4464
4465         u8         reserved_at_60[0x20];
4466 };
4467
4468 struct mlx5_ifc_query_vport_counter_out_bits {
4469         u8         status[0x8];
4470         u8         reserved_at_8[0x18];
4471
4472         u8         syndrome[0x20];
4473
4474         u8         reserved_at_40[0x40];
4475
4476         struct mlx5_ifc_traffic_counter_bits received_errors;
4477
4478         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4479
4480         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4481
4482         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4483
4484         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4485
4486         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4487
4488         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4489
4490         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4491
4492         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4493
4494         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4495
4496         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4497
4498         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4499
4500         u8         reserved_at_680[0xa00];
4501 };
4502
4503 enum {
4504         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4505 };
4506
4507 struct mlx5_ifc_query_vport_counter_in_bits {
4508         u8         opcode[0x10];
4509         u8         reserved_at_10[0x10];
4510
4511         u8         reserved_at_20[0x10];
4512         u8         op_mod[0x10];
4513
4514         u8         other_vport[0x1];
4515         u8         reserved_at_41[0xb];
4516         u8         port_num[0x4];
4517         u8         vport_number[0x10];
4518
4519         u8         reserved_at_60[0x60];
4520
4521         u8         clear[0x1];
4522         u8         reserved_at_c1[0x1f];
4523
4524         u8         reserved_at_e0[0x20];
4525 };
4526
4527 struct mlx5_ifc_query_tis_out_bits {
4528         u8         status[0x8];
4529         u8         reserved_at_8[0x18];
4530
4531         u8         syndrome[0x20];
4532
4533         u8         reserved_at_40[0x40];
4534
4535         struct mlx5_ifc_tisc_bits tis_context;
4536 };
4537
4538 struct mlx5_ifc_query_tis_in_bits {
4539         u8         opcode[0x10];
4540         u8         reserved_at_10[0x10];
4541
4542         u8         reserved_at_20[0x10];
4543         u8         op_mod[0x10];
4544
4545         u8         reserved_at_40[0x8];
4546         u8         tisn[0x18];
4547
4548         u8         reserved_at_60[0x20];
4549 };
4550
4551 struct mlx5_ifc_query_tir_out_bits {
4552         u8         status[0x8];
4553         u8         reserved_at_8[0x18];
4554
4555         u8         syndrome[0x20];
4556
4557         u8         reserved_at_40[0xc0];
4558
4559         struct mlx5_ifc_tirc_bits tir_context;
4560 };
4561
4562 struct mlx5_ifc_query_tir_in_bits {
4563         u8         opcode[0x10];
4564         u8         reserved_at_10[0x10];
4565
4566         u8         reserved_at_20[0x10];
4567         u8         op_mod[0x10];
4568
4569         u8         reserved_at_40[0x8];
4570         u8         tirn[0x18];
4571
4572         u8         reserved_at_60[0x20];
4573 };
4574
4575 struct mlx5_ifc_query_srq_out_bits {
4576         u8         status[0x8];
4577         u8         reserved_at_8[0x18];
4578
4579         u8         syndrome[0x20];
4580
4581         u8         reserved_at_40[0x40];
4582
4583         struct mlx5_ifc_srqc_bits srq_context_entry;
4584
4585         u8         reserved_at_280[0x600];
4586
4587         u8         pas[0][0x40];
4588 };
4589
4590 struct mlx5_ifc_query_srq_in_bits {
4591         u8         opcode[0x10];
4592         u8         reserved_at_10[0x10];
4593
4594         u8         reserved_at_20[0x10];
4595         u8         op_mod[0x10];
4596
4597         u8         reserved_at_40[0x8];
4598         u8         srqn[0x18];
4599
4600         u8         reserved_at_60[0x20];
4601 };
4602
4603 struct mlx5_ifc_query_sq_out_bits {
4604         u8         status[0x8];
4605         u8         reserved_at_8[0x18];
4606
4607         u8         syndrome[0x20];
4608
4609         u8         reserved_at_40[0xc0];
4610
4611         struct mlx5_ifc_sqc_bits sq_context;
4612 };
4613
4614 struct mlx5_ifc_query_sq_in_bits {
4615         u8         opcode[0x10];
4616         u8         reserved_at_10[0x10];
4617
4618         u8         reserved_at_20[0x10];
4619         u8         op_mod[0x10];
4620
4621         u8         reserved_at_40[0x8];
4622         u8         sqn[0x18];
4623
4624         u8         reserved_at_60[0x20];
4625 };
4626
4627 struct mlx5_ifc_query_special_contexts_out_bits {
4628         u8         status[0x8];
4629         u8         reserved_at_8[0x18];
4630
4631         u8         syndrome[0x20];
4632
4633         u8         dump_fill_mkey[0x20];
4634
4635         u8         resd_lkey[0x20];
4636
4637         u8         null_mkey[0x20];
4638
4639         u8         reserved_at_a0[0x60];
4640 };
4641
4642 struct mlx5_ifc_query_special_contexts_in_bits {
4643         u8         opcode[0x10];
4644         u8         reserved_at_10[0x10];
4645
4646         u8         reserved_at_20[0x10];
4647         u8         op_mod[0x10];
4648
4649         u8         reserved_at_40[0x40];
4650 };
4651
4652 struct mlx5_ifc_query_scheduling_element_out_bits {
4653         u8         opcode[0x10];
4654         u8         reserved_at_10[0x10];
4655
4656         u8         reserved_at_20[0x10];
4657         u8         op_mod[0x10];
4658
4659         u8         reserved_at_40[0xc0];
4660
4661         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4662
4663         u8         reserved_at_300[0x100];
4664 };
4665
4666 enum {
4667         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4668 };
4669
4670 struct mlx5_ifc_query_scheduling_element_in_bits {
4671         u8         opcode[0x10];
4672         u8         reserved_at_10[0x10];
4673
4674         u8         reserved_at_20[0x10];
4675         u8         op_mod[0x10];
4676
4677         u8         scheduling_hierarchy[0x8];
4678         u8         reserved_at_48[0x18];
4679
4680         u8         scheduling_element_id[0x20];
4681
4682         u8         reserved_at_80[0x180];
4683 };
4684
4685 struct mlx5_ifc_query_rqt_out_bits {
4686         u8         status[0x8];
4687         u8         reserved_at_8[0x18];
4688
4689         u8         syndrome[0x20];
4690
4691         u8         reserved_at_40[0xc0];
4692
4693         struct mlx5_ifc_rqtc_bits rqt_context;
4694 };
4695
4696 struct mlx5_ifc_query_rqt_in_bits {
4697         u8         opcode[0x10];
4698         u8         reserved_at_10[0x10];
4699
4700         u8         reserved_at_20[0x10];
4701         u8         op_mod[0x10];
4702
4703         u8         reserved_at_40[0x8];
4704         u8         rqtn[0x18];
4705
4706         u8         reserved_at_60[0x20];
4707 };
4708
4709 struct mlx5_ifc_query_rq_out_bits {
4710         u8         status[0x8];
4711         u8         reserved_at_8[0x18];
4712
4713         u8         syndrome[0x20];
4714
4715         u8         reserved_at_40[0xc0];
4716
4717         struct mlx5_ifc_rqc_bits rq_context;
4718 };
4719
4720 struct mlx5_ifc_query_rq_in_bits {
4721         u8         opcode[0x10];
4722         u8         reserved_at_10[0x10];
4723
4724         u8         reserved_at_20[0x10];
4725         u8         op_mod[0x10];
4726
4727         u8         reserved_at_40[0x8];
4728         u8         rqn[0x18];
4729
4730         u8         reserved_at_60[0x20];
4731 };
4732
4733 struct mlx5_ifc_query_roce_address_out_bits {
4734         u8         status[0x8];
4735         u8         reserved_at_8[0x18];
4736
4737         u8         syndrome[0x20];
4738
4739         u8         reserved_at_40[0x40];
4740
4741         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4742 };
4743
4744 struct mlx5_ifc_query_roce_address_in_bits {
4745         u8         opcode[0x10];
4746         u8         reserved_at_10[0x10];
4747
4748         u8         reserved_at_20[0x10];
4749         u8         op_mod[0x10];
4750
4751         u8         roce_address_index[0x10];
4752         u8         reserved_at_50[0xc];
4753         u8         vhca_port_num[0x4];
4754
4755         u8         reserved_at_60[0x20];
4756 };
4757
4758 struct mlx5_ifc_query_rmp_out_bits {
4759         u8         status[0x8];
4760         u8         reserved_at_8[0x18];
4761
4762         u8         syndrome[0x20];
4763
4764         u8         reserved_at_40[0xc0];
4765
4766         struct mlx5_ifc_rmpc_bits rmp_context;
4767 };
4768
4769 struct mlx5_ifc_query_rmp_in_bits {
4770         u8         opcode[0x10];
4771         u8         reserved_at_10[0x10];
4772
4773         u8         reserved_at_20[0x10];
4774         u8         op_mod[0x10];
4775
4776         u8         reserved_at_40[0x8];
4777         u8         rmpn[0x18];
4778
4779         u8         reserved_at_60[0x20];
4780 };
4781
4782 struct mlx5_ifc_query_qp_out_bits {
4783         u8         status[0x8];
4784         u8         reserved_at_8[0x18];
4785
4786         u8         syndrome[0x20];
4787
4788         u8         reserved_at_40[0x40];
4789
4790         u8         opt_param_mask[0x20];
4791
4792         u8         reserved_at_a0[0x20];
4793
4794         struct mlx5_ifc_qpc_bits qpc;
4795
4796         u8         reserved_at_800[0x80];
4797
4798         u8         pas[0][0x40];
4799 };
4800
4801 struct mlx5_ifc_query_qp_in_bits {
4802         u8         opcode[0x10];
4803         u8         reserved_at_10[0x10];
4804
4805         u8         reserved_at_20[0x10];
4806         u8         op_mod[0x10];
4807
4808         u8         reserved_at_40[0x8];
4809         u8         qpn[0x18];
4810
4811         u8         reserved_at_60[0x20];
4812 };
4813
4814 struct mlx5_ifc_query_q_counter_out_bits {
4815         u8         status[0x8];
4816         u8         reserved_at_8[0x18];
4817
4818         u8         syndrome[0x20];
4819
4820         u8         reserved_at_40[0x40];
4821
4822         u8         rx_write_requests[0x20];
4823
4824         u8         reserved_at_a0[0x20];
4825
4826         u8         rx_read_requests[0x20];
4827
4828         u8         reserved_at_e0[0x20];
4829
4830         u8         rx_atomic_requests[0x20];
4831
4832         u8         reserved_at_120[0x20];
4833
4834         u8         rx_dct_connect[0x20];
4835
4836         u8         reserved_at_160[0x20];
4837
4838         u8         out_of_buffer[0x20];
4839
4840         u8         reserved_at_1a0[0x20];
4841
4842         u8         out_of_sequence[0x20];
4843
4844         u8         reserved_at_1e0[0x20];
4845
4846         u8         duplicate_request[0x20];
4847
4848         u8         reserved_at_220[0x20];
4849
4850         u8         rnr_nak_retry_err[0x20];
4851
4852         u8         reserved_at_260[0x20];
4853
4854         u8         packet_seq_err[0x20];
4855
4856         u8         reserved_at_2a0[0x20];
4857
4858         u8         implied_nak_seq_err[0x20];
4859
4860         u8         reserved_at_2e0[0x20];
4861
4862         u8         local_ack_timeout_err[0x20];
4863
4864         u8         reserved_at_320[0xa0];
4865
4866         u8         resp_local_length_error[0x20];
4867
4868         u8         req_local_length_error[0x20];
4869
4870         u8         resp_local_qp_error[0x20];
4871
4872         u8         local_operation_error[0x20];
4873
4874         u8         resp_local_protection[0x20];
4875
4876         u8         req_local_protection[0x20];
4877
4878         u8         resp_cqe_error[0x20];
4879
4880         u8         req_cqe_error[0x20];
4881
4882         u8         req_mw_binding[0x20];
4883
4884         u8         req_bad_response[0x20];
4885
4886         u8         req_remote_invalid_request[0x20];
4887
4888         u8         resp_remote_invalid_request[0x20];
4889
4890         u8         req_remote_access_errors[0x20];
4891
4892         u8         resp_remote_access_errors[0x20];
4893
4894         u8         req_remote_operation_errors[0x20];
4895
4896         u8         req_transport_retries_exceeded[0x20];
4897
4898         u8         cq_overflow[0x20];
4899
4900         u8         resp_cqe_flush_error[0x20];
4901
4902         u8         req_cqe_flush_error[0x20];
4903
4904         u8         reserved_at_620[0x20];
4905
4906         u8         roce_adp_retrans[0x20];
4907
4908         u8         roce_adp_retrans_to[0x20];
4909
4910         u8         roce_slow_restart[0x20];
4911
4912         u8         roce_slow_restart_cnps[0x20];
4913
4914         u8         roce_slow_restart_trans[0x20];
4915
4916         u8         reserved_at_6e0[0x120];
4917 };
4918
4919 struct mlx5_ifc_query_q_counter_in_bits {
4920         u8         opcode[0x10];
4921         u8         reserved_at_10[0x10];
4922
4923         u8         reserved_at_20[0x10];
4924         u8         op_mod[0x10];
4925
4926         u8         reserved_at_40[0x80];
4927
4928         u8         clear[0x1];
4929         u8         reserved_at_c1[0x1f];
4930
4931         u8         reserved_at_e0[0x18];
4932         u8         counter_set_id[0x8];
4933 };
4934
4935 struct mlx5_ifc_query_pages_out_bits {
4936         u8         status[0x8];
4937         u8         reserved_at_8[0x18];
4938
4939         u8         syndrome[0x20];
4940
4941         u8         embedded_cpu_function[0x1];
4942         u8         reserved_at_41[0xf];
4943         u8         function_id[0x10];
4944
4945         u8         num_pages[0x20];
4946 };
4947
4948 enum {
4949         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4950         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4951         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4952 };
4953
4954 struct mlx5_ifc_query_pages_in_bits {
4955         u8         opcode[0x10];
4956         u8         reserved_at_10[0x10];
4957
4958         u8         reserved_at_20[0x10];
4959         u8         op_mod[0x10];
4960
4961         u8         embedded_cpu_function[0x1];
4962         u8         reserved_at_41[0xf];
4963         u8         function_id[0x10];
4964
4965         u8         reserved_at_60[0x20];
4966 };
4967
4968 struct mlx5_ifc_query_nic_vport_context_out_bits {
4969         u8         status[0x8];
4970         u8         reserved_at_8[0x18];
4971
4972         u8         syndrome[0x20];
4973
4974         u8         reserved_at_40[0x40];
4975
4976         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4977 };
4978
4979 struct mlx5_ifc_query_nic_vport_context_in_bits {
4980         u8         opcode[0x10];
4981         u8         reserved_at_10[0x10];
4982
4983         u8         reserved_at_20[0x10];
4984         u8         op_mod[0x10];
4985
4986         u8         other_vport[0x1];
4987         u8         reserved_at_41[0xf];
4988         u8         vport_number[0x10];
4989
4990         u8         reserved_at_60[0x5];
4991         u8         allowed_list_type[0x3];
4992         u8         reserved_at_68[0x18];
4993 };
4994
4995 struct mlx5_ifc_query_mkey_out_bits {
4996         u8         status[0x8];
4997         u8         reserved_at_8[0x18];
4998
4999         u8         syndrome[0x20];
5000
5001         u8         reserved_at_40[0x40];
5002
5003         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5004
5005         u8         reserved_at_280[0x600];
5006
5007         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5008
5009         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5010 };
5011
5012 struct mlx5_ifc_query_mkey_in_bits {
5013         u8         opcode[0x10];
5014         u8         reserved_at_10[0x10];
5015
5016         u8         reserved_at_20[0x10];
5017         u8         op_mod[0x10];
5018
5019         u8         reserved_at_40[0x8];
5020         u8         mkey_index[0x18];
5021
5022         u8         pg_access[0x1];
5023         u8         reserved_at_61[0x1f];
5024 };
5025
5026 struct mlx5_ifc_query_mad_demux_out_bits {
5027         u8         status[0x8];
5028         u8         reserved_at_8[0x18];
5029
5030         u8         syndrome[0x20];
5031
5032         u8         reserved_at_40[0x40];
5033
5034         u8         mad_dumux_parameters_block[0x20];
5035 };
5036
5037 struct mlx5_ifc_query_mad_demux_in_bits {
5038         u8         opcode[0x10];
5039         u8         reserved_at_10[0x10];
5040
5041         u8         reserved_at_20[0x10];
5042         u8         op_mod[0x10];
5043
5044         u8         reserved_at_40[0x40];
5045 };
5046
5047 struct mlx5_ifc_query_l2_table_entry_out_bits {
5048         u8         status[0x8];
5049         u8         reserved_at_8[0x18];
5050
5051         u8         syndrome[0x20];
5052
5053         u8         reserved_at_40[0xa0];
5054
5055         u8         reserved_at_e0[0x13];
5056         u8         vlan_valid[0x1];
5057         u8         vlan[0xc];
5058
5059         struct mlx5_ifc_mac_address_layout_bits mac_address;
5060
5061         u8         reserved_at_140[0xc0];
5062 };
5063
5064 struct mlx5_ifc_query_l2_table_entry_in_bits {
5065         u8         opcode[0x10];
5066         u8         reserved_at_10[0x10];
5067
5068         u8         reserved_at_20[0x10];
5069         u8         op_mod[0x10];
5070
5071         u8         reserved_at_40[0x60];
5072
5073         u8         reserved_at_a0[0x8];
5074         u8         table_index[0x18];
5075
5076         u8         reserved_at_c0[0x140];
5077 };
5078
5079 struct mlx5_ifc_query_issi_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x10];
5086         u8         current_issi[0x10];
5087
5088         u8         reserved_at_60[0xa0];
5089
5090         u8         reserved_at_100[76][0x8];
5091         u8         supported_issi_dw0[0x20];
5092 };
5093
5094 struct mlx5_ifc_query_issi_in_bits {
5095         u8         opcode[0x10];
5096         u8         reserved_at_10[0x10];
5097
5098         u8         reserved_at_20[0x10];
5099         u8         op_mod[0x10];
5100
5101         u8         reserved_at_40[0x40];
5102 };
5103
5104 struct mlx5_ifc_set_driver_version_out_bits {
5105         u8         status[0x8];
5106         u8         reserved_0[0x18];
5107
5108         u8         syndrome[0x20];
5109         u8         reserved_1[0x40];
5110 };
5111
5112 struct mlx5_ifc_set_driver_version_in_bits {
5113         u8         opcode[0x10];
5114         u8         reserved_0[0x10];
5115
5116         u8         reserved_1[0x10];
5117         u8         op_mod[0x10];
5118
5119         u8         reserved_2[0x40];
5120         u8         driver_version[64][0x8];
5121 };
5122
5123 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5124         u8         status[0x8];
5125         u8         reserved_at_8[0x18];
5126
5127         u8         syndrome[0x20];
5128
5129         u8         reserved_at_40[0x40];
5130
5131         struct mlx5_ifc_pkey_bits pkey[0];
5132 };
5133
5134 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5135         u8         opcode[0x10];
5136         u8         reserved_at_10[0x10];
5137
5138         u8         reserved_at_20[0x10];
5139         u8         op_mod[0x10];
5140
5141         u8         other_vport[0x1];
5142         u8         reserved_at_41[0xb];
5143         u8         port_num[0x4];
5144         u8         vport_number[0x10];
5145
5146         u8         reserved_at_60[0x10];
5147         u8         pkey_index[0x10];
5148 };
5149
5150 enum {
5151         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5152         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5153         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5154 };
5155
5156 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5157         u8         status[0x8];
5158         u8         reserved_at_8[0x18];
5159
5160         u8         syndrome[0x20];
5161
5162         u8         reserved_at_40[0x20];
5163
5164         u8         gids_num[0x10];
5165         u8         reserved_at_70[0x10];
5166
5167         struct mlx5_ifc_array128_auto_bits gid[0];
5168 };
5169
5170 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5171         u8         opcode[0x10];
5172         u8         reserved_at_10[0x10];
5173
5174         u8         reserved_at_20[0x10];
5175         u8         op_mod[0x10];
5176
5177         u8         other_vport[0x1];
5178         u8         reserved_at_41[0xb];
5179         u8         port_num[0x4];
5180         u8         vport_number[0x10];
5181
5182         u8         reserved_at_60[0x10];
5183         u8         gid_index[0x10];
5184 };
5185
5186 struct mlx5_ifc_query_hca_vport_context_out_bits {
5187         u8         status[0x8];
5188         u8         reserved_at_8[0x18];
5189
5190         u8         syndrome[0x20];
5191
5192         u8         reserved_at_40[0x40];
5193
5194         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5195 };
5196
5197 struct mlx5_ifc_query_hca_vport_context_in_bits {
5198         u8         opcode[0x10];
5199         u8         reserved_at_10[0x10];
5200
5201         u8         reserved_at_20[0x10];
5202         u8         op_mod[0x10];
5203
5204         u8         other_vport[0x1];
5205         u8         reserved_at_41[0xb];
5206         u8         port_num[0x4];
5207         u8         vport_number[0x10];
5208
5209         u8         reserved_at_60[0x20];
5210 };
5211
5212 struct mlx5_ifc_query_hca_cap_out_bits {
5213         u8         status[0x8];
5214         u8         reserved_at_8[0x18];
5215
5216         u8         syndrome[0x20];
5217
5218         u8         reserved_at_40[0x40];
5219
5220         union mlx5_ifc_hca_cap_union_bits capability;
5221 };
5222
5223 struct mlx5_ifc_query_hca_cap_in_bits {
5224         u8         opcode[0x10];
5225         u8         reserved_at_10[0x10];
5226
5227         u8         reserved_at_20[0x10];
5228         u8         op_mod[0x10];
5229
5230         u8         other_function[0x1];
5231         u8         reserved_at_41[0xf];
5232         u8         function_id[0x10];
5233
5234         u8         reserved_at_60[0x20];
5235 };
5236
5237 struct mlx5_ifc_other_hca_cap_bits {
5238         u8         roce[0x1];
5239         u8         reserved_at_1[0x27f];
5240 };
5241
5242 struct mlx5_ifc_query_other_hca_cap_out_bits {
5243         u8         status[0x8];
5244         u8         reserved_at_8[0x18];
5245
5246         u8         syndrome[0x20];
5247
5248         u8         reserved_at_40[0x40];
5249
5250         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5251 };
5252
5253 struct mlx5_ifc_query_other_hca_cap_in_bits {
5254         u8         opcode[0x10];
5255         u8         reserved_at_10[0x10];
5256
5257         u8         reserved_at_20[0x10];
5258         u8         op_mod[0x10];
5259
5260         u8         reserved_at_40[0x10];
5261         u8         function_id[0x10];
5262
5263         u8         reserved_at_60[0x20];
5264 };
5265
5266 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5267         u8         status[0x8];
5268         u8         reserved_at_8[0x18];
5269
5270         u8         syndrome[0x20];
5271
5272         u8         reserved_at_40[0x40];
5273 };
5274
5275 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5276         u8         opcode[0x10];
5277         u8         reserved_at_10[0x10];
5278
5279         u8         reserved_at_20[0x10];
5280         u8         op_mod[0x10];
5281
5282         u8         reserved_at_40[0x10];
5283         u8         function_id[0x10];
5284         u8         field_select[0x20];
5285
5286         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5287 };
5288
5289 struct mlx5_ifc_flow_table_context_bits {
5290         u8         reformat_en[0x1];
5291         u8         decap_en[0x1];
5292         u8         sw_owner[0x1];
5293         u8         termination_table[0x1];
5294         u8         table_miss_action[0x4];
5295         u8         level[0x8];
5296         u8         reserved_at_10[0x8];
5297         u8         log_size[0x8];
5298
5299         u8         reserved_at_20[0x8];
5300         u8         table_miss_id[0x18];
5301
5302         u8         reserved_at_40[0x8];
5303         u8         lag_master_next_table_id[0x18];
5304
5305         u8         reserved_at_60[0x60];
5306
5307         u8         sw_owner_icm_root_1[0x40];
5308
5309         u8         sw_owner_icm_root_0[0x40];
5310
5311 };
5312
5313 struct mlx5_ifc_query_flow_table_out_bits {
5314         u8         status[0x8];
5315         u8         reserved_at_8[0x18];
5316
5317         u8         syndrome[0x20];
5318
5319         u8         reserved_at_40[0x80];
5320
5321         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5322 };
5323
5324 struct mlx5_ifc_query_flow_table_in_bits {
5325         u8         opcode[0x10];
5326         u8         reserved_at_10[0x10];
5327
5328         u8         reserved_at_20[0x10];
5329         u8         op_mod[0x10];
5330
5331         u8         reserved_at_40[0x40];
5332
5333         u8         table_type[0x8];
5334         u8         reserved_at_88[0x18];
5335
5336         u8         reserved_at_a0[0x8];
5337         u8         table_id[0x18];
5338
5339         u8         reserved_at_c0[0x140];
5340 };
5341
5342 struct mlx5_ifc_query_fte_out_bits {
5343         u8         status[0x8];
5344         u8         reserved_at_8[0x18];
5345
5346         u8         syndrome[0x20];
5347
5348         u8         reserved_at_40[0x1c0];
5349
5350         struct mlx5_ifc_flow_context_bits flow_context;
5351 };
5352
5353 struct mlx5_ifc_query_fte_in_bits {
5354         u8         opcode[0x10];
5355         u8         reserved_at_10[0x10];
5356
5357         u8         reserved_at_20[0x10];
5358         u8         op_mod[0x10];
5359
5360         u8         reserved_at_40[0x40];
5361
5362         u8         table_type[0x8];
5363         u8         reserved_at_88[0x18];
5364
5365         u8         reserved_at_a0[0x8];
5366         u8         table_id[0x18];
5367
5368         u8         reserved_at_c0[0x40];
5369
5370         u8         flow_index[0x20];
5371
5372         u8         reserved_at_120[0xe0];
5373 };
5374
5375 enum {
5376         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5377         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5378         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5379         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5380         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5381 };
5382
5383 struct mlx5_ifc_query_flow_group_out_bits {
5384         u8         status[0x8];
5385         u8         reserved_at_8[0x18];
5386
5387         u8         syndrome[0x20];
5388
5389         u8         reserved_at_40[0xa0];
5390
5391         u8         start_flow_index[0x20];
5392
5393         u8         reserved_at_100[0x20];
5394
5395         u8         end_flow_index[0x20];
5396
5397         u8         reserved_at_140[0xa0];
5398
5399         u8         reserved_at_1e0[0x18];
5400         u8         match_criteria_enable[0x8];
5401
5402         struct mlx5_ifc_fte_match_param_bits match_criteria;
5403
5404         u8         reserved_at_1200[0xe00];
5405 };
5406
5407 struct mlx5_ifc_query_flow_group_in_bits {
5408         u8         opcode[0x10];
5409         u8         reserved_at_10[0x10];
5410
5411         u8         reserved_at_20[0x10];
5412         u8         op_mod[0x10];
5413
5414         u8         reserved_at_40[0x40];
5415
5416         u8         table_type[0x8];
5417         u8         reserved_at_88[0x18];
5418
5419         u8         reserved_at_a0[0x8];
5420         u8         table_id[0x18];
5421
5422         u8         group_id[0x20];
5423
5424         u8         reserved_at_e0[0x120];
5425 };
5426
5427 struct mlx5_ifc_query_flow_counter_out_bits {
5428         u8         status[0x8];
5429         u8         reserved_at_8[0x18];
5430
5431         u8         syndrome[0x20];
5432
5433         u8         reserved_at_40[0x40];
5434
5435         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5436 };
5437
5438 struct mlx5_ifc_query_flow_counter_in_bits {
5439         u8         opcode[0x10];
5440         u8         reserved_at_10[0x10];
5441
5442         u8         reserved_at_20[0x10];
5443         u8         op_mod[0x10];
5444
5445         u8         reserved_at_40[0x80];
5446
5447         u8         clear[0x1];
5448         u8         reserved_at_c1[0xf];
5449         u8         num_of_counters[0x10];
5450
5451         u8         flow_counter_id[0x20];
5452 };
5453
5454 struct mlx5_ifc_query_esw_vport_context_out_bits {
5455         u8         status[0x8];
5456         u8         reserved_at_8[0x18];
5457
5458         u8         syndrome[0x20];
5459
5460         u8         reserved_at_40[0x40];
5461
5462         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5463 };
5464
5465 struct mlx5_ifc_query_esw_vport_context_in_bits {
5466         u8         opcode[0x10];
5467         u8         reserved_at_10[0x10];
5468
5469         u8         reserved_at_20[0x10];
5470         u8         op_mod[0x10];
5471
5472         u8         other_vport[0x1];
5473         u8         reserved_at_41[0xf];
5474         u8         vport_number[0x10];
5475
5476         u8         reserved_at_60[0x20];
5477 };
5478
5479 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5480         u8         status[0x8];
5481         u8         reserved_at_8[0x18];
5482
5483         u8         syndrome[0x20];
5484
5485         u8         reserved_at_40[0x40];
5486 };
5487
5488 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5489         u8         reserved_at_0[0x1b];
5490         u8         fdb_to_vport_reg_c_id[0x1];
5491         u8         vport_cvlan_insert[0x1];
5492         u8         vport_svlan_insert[0x1];
5493         u8         vport_cvlan_strip[0x1];
5494         u8         vport_svlan_strip[0x1];
5495 };
5496
5497 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5498         u8         opcode[0x10];
5499         u8         reserved_at_10[0x10];
5500
5501         u8         reserved_at_20[0x10];
5502         u8         op_mod[0x10];
5503
5504         u8         other_vport[0x1];
5505         u8         reserved_at_41[0xf];
5506         u8         vport_number[0x10];
5507
5508         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5509
5510         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5511 };
5512
5513 struct mlx5_ifc_query_eq_out_bits {
5514         u8         status[0x8];
5515         u8         reserved_at_8[0x18];
5516
5517         u8         syndrome[0x20];
5518
5519         u8         reserved_at_40[0x40];
5520
5521         struct mlx5_ifc_eqc_bits eq_context_entry;
5522
5523         u8         reserved_at_280[0x40];
5524
5525         u8         event_bitmask[0x40];
5526
5527         u8         reserved_at_300[0x580];
5528
5529         u8         pas[0][0x40];
5530 };
5531
5532 struct mlx5_ifc_query_eq_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_at_10[0x10];
5535
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         reserved_at_40[0x18];
5540         u8         eq_number[0x8];
5541
5542         u8         reserved_at_60[0x20];
5543 };
5544
5545 struct mlx5_ifc_packet_reformat_context_in_bits {
5546         u8         reserved_at_0[0x5];
5547         u8         reformat_type[0x3];
5548         u8         reserved_at_8[0xe];
5549         u8         reformat_data_size[0xa];
5550
5551         u8         reserved_at_20[0x10];
5552         u8         reformat_data[2][0x8];
5553
5554         u8         more_reformat_data[0][0x8];
5555 };
5556
5557 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5558         u8         status[0x8];
5559         u8         reserved_at_8[0x18];
5560
5561         u8         syndrome[0x20];
5562
5563         u8         reserved_at_40[0xa0];
5564
5565         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5566 };
5567
5568 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5569         u8         opcode[0x10];
5570         u8         reserved_at_10[0x10];
5571
5572         u8         reserved_at_20[0x10];
5573         u8         op_mod[0x10];
5574
5575         u8         packet_reformat_id[0x20];
5576
5577         u8         reserved_at_60[0xa0];
5578 };
5579
5580 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5581         u8         status[0x8];
5582         u8         reserved_at_8[0x18];
5583
5584         u8         syndrome[0x20];
5585
5586         u8         packet_reformat_id[0x20];
5587
5588         u8         reserved_at_60[0x20];
5589 };
5590
5591 enum mlx5_reformat_ctx_type {
5592         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5593         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5594         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5595         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5596         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5597 };
5598
5599 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5600         u8         opcode[0x10];
5601         u8         reserved_at_10[0x10];
5602
5603         u8         reserved_at_20[0x10];
5604         u8         op_mod[0x10];
5605
5606         u8         reserved_at_40[0xa0];
5607
5608         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5609 };
5610
5611 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5612         u8         status[0x8];
5613         u8         reserved_at_8[0x18];
5614
5615         u8         syndrome[0x20];
5616
5617         u8         reserved_at_40[0x40];
5618 };
5619
5620 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5621         u8         opcode[0x10];
5622         u8         reserved_at_10[0x10];
5623
5624         u8         reserved_20[0x10];
5625         u8         op_mod[0x10];
5626
5627         u8         packet_reformat_id[0x20];
5628
5629         u8         reserved_60[0x20];
5630 };
5631
5632 struct mlx5_ifc_set_action_in_bits {
5633         u8         action_type[0x4];
5634         u8         field[0xc];
5635         u8         reserved_at_10[0x3];
5636         u8         offset[0x5];
5637         u8         reserved_at_18[0x3];
5638         u8         length[0x5];
5639
5640         u8         data[0x20];
5641 };
5642
5643 struct mlx5_ifc_add_action_in_bits {
5644         u8         action_type[0x4];
5645         u8         field[0xc];
5646         u8         reserved_at_10[0x10];
5647
5648         u8         data[0x20];
5649 };
5650
5651 struct mlx5_ifc_copy_action_in_bits {
5652         u8         action_type[0x4];
5653         u8         src_field[0xc];
5654         u8         reserved_at_10[0x3];
5655         u8         src_offset[0x5];
5656         u8         reserved_at_18[0x3];
5657         u8         length[0x5];
5658
5659         u8         reserved_at_20[0x4];
5660         u8         dst_field[0xc];
5661         u8         reserved_at_30[0x3];
5662         u8         dst_offset[0x5];
5663         u8         reserved_at_38[0x8];
5664 };
5665
5666 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5667         struct mlx5_ifc_set_action_in_bits set_action_in;
5668         struct mlx5_ifc_add_action_in_bits add_action_in;
5669         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5670         u8         reserved_at_0[0x40];
5671 };
5672
5673 enum {
5674         MLX5_ACTION_TYPE_SET   = 0x1,
5675         MLX5_ACTION_TYPE_ADD   = 0x2,
5676         MLX5_ACTION_TYPE_COPY  = 0x3,
5677 };
5678
5679 enum {
5680         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5681         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5682         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5683         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5684         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5685         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5686         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5687         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5688         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5689         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5690         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5691         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5692         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5693         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5694         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5695         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5696         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5697         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5698         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5699         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5700         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5701         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5702         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5703         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5704         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5705         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5706         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5707         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5708         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5709         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5710         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5711         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5712         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5713         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5714         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5715         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5716 };
5717
5718 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5719         u8         status[0x8];
5720         u8         reserved_at_8[0x18];
5721
5722         u8         syndrome[0x20];
5723
5724         u8         modify_header_id[0x20];
5725
5726         u8         reserved_at_60[0x20];
5727 };
5728
5729 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5730         u8         opcode[0x10];
5731         u8         reserved_at_10[0x10];
5732
5733         u8         reserved_at_20[0x10];
5734         u8         op_mod[0x10];
5735
5736         u8         reserved_at_40[0x20];
5737
5738         u8         table_type[0x8];
5739         u8         reserved_at_68[0x10];
5740         u8         num_of_actions[0x8];
5741
5742         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5743 };
5744
5745 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5746         u8         status[0x8];
5747         u8         reserved_at_8[0x18];
5748
5749         u8         syndrome[0x20];
5750
5751         u8         reserved_at_40[0x40];
5752 };
5753
5754 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5755         u8         opcode[0x10];
5756         u8         reserved_at_10[0x10];
5757
5758         u8         reserved_at_20[0x10];
5759         u8         op_mod[0x10];
5760
5761         u8         modify_header_id[0x20];
5762
5763         u8         reserved_at_60[0x20];
5764 };
5765
5766 struct mlx5_ifc_query_dct_out_bits {
5767         u8         status[0x8];
5768         u8         reserved_at_8[0x18];
5769
5770         u8         syndrome[0x20];
5771
5772         u8         reserved_at_40[0x40];
5773
5774         struct mlx5_ifc_dctc_bits dct_context_entry;
5775
5776         u8         reserved_at_280[0x180];
5777 };
5778
5779 struct mlx5_ifc_query_dct_in_bits {
5780         u8         opcode[0x10];
5781         u8         reserved_at_10[0x10];
5782
5783         u8         reserved_at_20[0x10];
5784         u8         op_mod[0x10];
5785
5786         u8         reserved_at_40[0x8];
5787         u8         dctn[0x18];
5788
5789         u8         reserved_at_60[0x20];
5790 };
5791
5792 struct mlx5_ifc_query_cq_out_bits {
5793         u8         status[0x8];
5794         u8         reserved_at_8[0x18];
5795
5796         u8         syndrome[0x20];
5797
5798         u8         reserved_at_40[0x40];
5799
5800         struct mlx5_ifc_cqc_bits cq_context;
5801
5802         u8         reserved_at_280[0x600];
5803
5804         u8         pas[0][0x40];
5805 };
5806
5807 struct mlx5_ifc_query_cq_in_bits {
5808         u8         opcode[0x10];
5809         u8         reserved_at_10[0x10];
5810
5811         u8         reserved_at_20[0x10];
5812         u8         op_mod[0x10];
5813
5814         u8         reserved_at_40[0x8];
5815         u8         cqn[0x18];
5816
5817         u8         reserved_at_60[0x20];
5818 };
5819
5820 struct mlx5_ifc_query_cong_status_out_bits {
5821         u8         status[0x8];
5822         u8         reserved_at_8[0x18];
5823
5824         u8         syndrome[0x20];
5825
5826         u8         reserved_at_40[0x20];
5827
5828         u8         enable[0x1];
5829         u8         tag_enable[0x1];
5830         u8         reserved_at_62[0x1e];
5831 };
5832
5833 struct mlx5_ifc_query_cong_status_in_bits {
5834         u8         opcode[0x10];
5835         u8         reserved_at_10[0x10];
5836
5837         u8         reserved_at_20[0x10];
5838         u8         op_mod[0x10];
5839
5840         u8         reserved_at_40[0x18];
5841         u8         priority[0x4];
5842         u8         cong_protocol[0x4];
5843
5844         u8         reserved_at_60[0x20];
5845 };
5846
5847 struct mlx5_ifc_query_cong_statistics_out_bits {
5848         u8         status[0x8];
5849         u8         reserved_at_8[0x18];
5850
5851         u8         syndrome[0x20];
5852
5853         u8         reserved_at_40[0x40];
5854
5855         u8         rp_cur_flows[0x20];
5856
5857         u8         sum_flows[0x20];
5858
5859         u8         rp_cnp_ignored_high[0x20];
5860
5861         u8         rp_cnp_ignored_low[0x20];
5862
5863         u8         rp_cnp_handled_high[0x20];
5864
5865         u8         rp_cnp_handled_low[0x20];
5866
5867         u8         reserved_at_140[0x100];
5868
5869         u8         time_stamp_high[0x20];
5870
5871         u8         time_stamp_low[0x20];
5872
5873         u8         accumulators_period[0x20];
5874
5875         u8         np_ecn_marked_roce_packets_high[0x20];
5876
5877         u8         np_ecn_marked_roce_packets_low[0x20];
5878
5879         u8         np_cnp_sent_high[0x20];
5880
5881         u8         np_cnp_sent_low[0x20];
5882
5883         u8         reserved_at_320[0x560];
5884 };
5885
5886 struct mlx5_ifc_query_cong_statistics_in_bits {
5887         u8         opcode[0x10];
5888         u8         reserved_at_10[0x10];
5889
5890         u8         reserved_at_20[0x10];
5891         u8         op_mod[0x10];
5892
5893         u8         clear[0x1];
5894         u8         reserved_at_41[0x1f];
5895
5896         u8         reserved_at_60[0x20];
5897 };
5898
5899 struct mlx5_ifc_query_cong_params_out_bits {
5900         u8         status[0x8];
5901         u8         reserved_at_8[0x18];
5902
5903         u8         syndrome[0x20];
5904
5905         u8         reserved_at_40[0x40];
5906
5907         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5908 };
5909
5910 struct mlx5_ifc_query_cong_params_in_bits {
5911         u8         opcode[0x10];
5912         u8         reserved_at_10[0x10];
5913
5914         u8         reserved_at_20[0x10];
5915         u8         op_mod[0x10];
5916
5917         u8         reserved_at_40[0x1c];
5918         u8         cong_protocol[0x4];
5919
5920         u8         reserved_at_60[0x20];
5921 };
5922
5923 struct mlx5_ifc_query_adapter_out_bits {
5924         u8         status[0x8];
5925         u8         reserved_at_8[0x18];
5926
5927         u8         syndrome[0x20];
5928
5929         u8         reserved_at_40[0x40];
5930
5931         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5932 };
5933
5934 struct mlx5_ifc_query_adapter_in_bits {
5935         u8         opcode[0x10];
5936         u8         reserved_at_10[0x10];
5937
5938         u8         reserved_at_20[0x10];
5939         u8         op_mod[0x10];
5940
5941         u8         reserved_at_40[0x40];
5942 };
5943
5944 struct mlx5_ifc_qp_2rst_out_bits {
5945         u8         status[0x8];
5946         u8         reserved_at_8[0x18];
5947
5948         u8         syndrome[0x20];
5949
5950         u8         reserved_at_40[0x40];
5951 };
5952
5953 struct mlx5_ifc_qp_2rst_in_bits {
5954         u8         opcode[0x10];
5955         u8         uid[0x10];
5956
5957         u8         reserved_at_20[0x10];
5958         u8         op_mod[0x10];
5959
5960         u8         reserved_at_40[0x8];
5961         u8         qpn[0x18];
5962
5963         u8         reserved_at_60[0x20];
5964 };
5965
5966 struct mlx5_ifc_qp_2err_out_bits {
5967         u8         status[0x8];
5968         u8         reserved_at_8[0x18];
5969
5970         u8         syndrome[0x20];
5971
5972         u8         reserved_at_40[0x40];
5973 };
5974
5975 struct mlx5_ifc_qp_2err_in_bits {
5976         u8         opcode[0x10];
5977         u8         uid[0x10];
5978
5979         u8         reserved_at_20[0x10];
5980         u8         op_mod[0x10];
5981
5982         u8         reserved_at_40[0x8];
5983         u8         qpn[0x18];
5984
5985         u8         reserved_at_60[0x20];
5986 };
5987
5988 struct mlx5_ifc_page_fault_resume_out_bits {
5989         u8         status[0x8];
5990         u8         reserved_at_8[0x18];
5991
5992         u8         syndrome[0x20];
5993
5994         u8         reserved_at_40[0x40];
5995 };
5996
5997 struct mlx5_ifc_page_fault_resume_in_bits {
5998         u8         opcode[0x10];
5999         u8         reserved_at_10[0x10];
6000
6001         u8         reserved_at_20[0x10];
6002         u8         op_mod[0x10];
6003
6004         u8         error[0x1];
6005         u8         reserved_at_41[0x4];
6006         u8         page_fault_type[0x3];
6007         u8         wq_number[0x18];
6008
6009         u8         reserved_at_60[0x8];
6010         u8         token[0x18];
6011 };
6012
6013 struct mlx5_ifc_nop_out_bits {
6014         u8         status[0x8];
6015         u8         reserved_at_8[0x18];
6016
6017         u8         syndrome[0x20];
6018
6019         u8         reserved_at_40[0x40];
6020 };
6021
6022 struct mlx5_ifc_nop_in_bits {
6023         u8         opcode[0x10];
6024         u8         reserved_at_10[0x10];
6025
6026         u8         reserved_at_20[0x10];
6027         u8         op_mod[0x10];
6028
6029         u8         reserved_at_40[0x40];
6030 };
6031
6032 struct mlx5_ifc_modify_vport_state_out_bits {
6033         u8         status[0x8];
6034         u8         reserved_at_8[0x18];
6035
6036         u8         syndrome[0x20];
6037
6038         u8         reserved_at_40[0x40];
6039 };
6040
6041 struct mlx5_ifc_modify_vport_state_in_bits {
6042         u8         opcode[0x10];
6043         u8         reserved_at_10[0x10];
6044
6045         u8         reserved_at_20[0x10];
6046         u8         op_mod[0x10];
6047
6048         u8         other_vport[0x1];
6049         u8         reserved_at_41[0xf];
6050         u8         vport_number[0x10];
6051
6052         u8         reserved_at_60[0x18];
6053         u8         admin_state[0x4];
6054         u8         reserved_at_7c[0x4];
6055 };
6056
6057 struct mlx5_ifc_modify_tis_out_bits {
6058         u8         status[0x8];
6059         u8         reserved_at_8[0x18];
6060
6061         u8         syndrome[0x20];
6062
6063         u8         reserved_at_40[0x40];
6064 };
6065
6066 struct mlx5_ifc_modify_tis_bitmask_bits {
6067         u8         reserved_at_0[0x20];
6068
6069         u8         reserved_at_20[0x1d];
6070         u8         lag_tx_port_affinity[0x1];
6071         u8         strict_lag_tx_port_affinity[0x1];
6072         u8         prio[0x1];
6073 };
6074
6075 struct mlx5_ifc_modify_tis_in_bits {
6076         u8         opcode[0x10];
6077         u8         uid[0x10];
6078
6079         u8         reserved_at_20[0x10];
6080         u8         op_mod[0x10];
6081
6082         u8         reserved_at_40[0x8];
6083         u8         tisn[0x18];
6084
6085         u8         reserved_at_60[0x20];
6086
6087         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6088
6089         u8         reserved_at_c0[0x40];
6090
6091         struct mlx5_ifc_tisc_bits ctx;
6092 };
6093
6094 struct mlx5_ifc_modify_tir_bitmask_bits {
6095         u8         reserved_at_0[0x20];
6096
6097         u8         reserved_at_20[0x1b];
6098         u8         self_lb_en[0x1];
6099         u8         reserved_at_3c[0x1];
6100         u8         hash[0x1];
6101         u8         reserved_at_3e[0x1];
6102         u8         lro[0x1];
6103 };
6104
6105 struct mlx5_ifc_modify_tir_out_bits {
6106         u8         status[0x8];
6107         u8         reserved_at_8[0x18];
6108
6109         u8         syndrome[0x20];
6110
6111         u8         reserved_at_40[0x40];
6112 };
6113
6114 struct mlx5_ifc_modify_tir_in_bits {
6115         u8         opcode[0x10];
6116         u8         uid[0x10];
6117
6118         u8         reserved_at_20[0x10];
6119         u8         op_mod[0x10];
6120
6121         u8         reserved_at_40[0x8];
6122         u8         tirn[0x18];
6123
6124         u8         reserved_at_60[0x20];
6125
6126         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6127
6128         u8         reserved_at_c0[0x40];
6129
6130         struct mlx5_ifc_tirc_bits ctx;
6131 };
6132
6133 struct mlx5_ifc_modify_sq_out_bits {
6134         u8         status[0x8];
6135         u8         reserved_at_8[0x18];
6136
6137         u8         syndrome[0x20];
6138
6139         u8         reserved_at_40[0x40];
6140 };
6141
6142 struct mlx5_ifc_modify_sq_in_bits {
6143         u8         opcode[0x10];
6144         u8         uid[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         sq_state[0x4];
6150         u8         reserved_at_44[0x4];
6151         u8         sqn[0x18];
6152
6153         u8         reserved_at_60[0x20];
6154
6155         u8         modify_bitmask[0x40];
6156
6157         u8         reserved_at_c0[0x40];
6158
6159         struct mlx5_ifc_sqc_bits ctx;
6160 };
6161
6162 struct mlx5_ifc_modify_scheduling_element_out_bits {
6163         u8         status[0x8];
6164         u8         reserved_at_8[0x18];
6165
6166         u8         syndrome[0x20];
6167
6168         u8         reserved_at_40[0x1c0];
6169 };
6170
6171 enum {
6172         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6173         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6174 };
6175
6176 struct mlx5_ifc_modify_scheduling_element_in_bits {
6177         u8         opcode[0x10];
6178         u8         reserved_at_10[0x10];
6179
6180         u8         reserved_at_20[0x10];
6181         u8         op_mod[0x10];
6182
6183         u8         scheduling_hierarchy[0x8];
6184         u8         reserved_at_48[0x18];
6185
6186         u8         scheduling_element_id[0x20];
6187
6188         u8         reserved_at_80[0x20];
6189
6190         u8         modify_bitmask[0x20];
6191
6192         u8         reserved_at_c0[0x40];
6193
6194         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6195
6196         u8         reserved_at_300[0x100];
6197 };
6198
6199 struct mlx5_ifc_modify_rqt_out_bits {
6200         u8         status[0x8];
6201         u8         reserved_at_8[0x18];
6202
6203         u8         syndrome[0x20];
6204
6205         u8         reserved_at_40[0x40];
6206 };
6207
6208 struct mlx5_ifc_rqt_bitmask_bits {
6209         u8         reserved_at_0[0x20];
6210
6211         u8         reserved_at_20[0x1f];
6212         u8         rqn_list[0x1];
6213 };
6214
6215 struct mlx5_ifc_modify_rqt_in_bits {
6216         u8         opcode[0x10];
6217         u8         uid[0x10];
6218
6219         u8         reserved_at_20[0x10];
6220         u8         op_mod[0x10];
6221
6222         u8         reserved_at_40[0x8];
6223         u8         rqtn[0x18];
6224
6225         u8         reserved_at_60[0x20];
6226
6227         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6228
6229         u8         reserved_at_c0[0x40];
6230
6231         struct mlx5_ifc_rqtc_bits ctx;
6232 };
6233
6234 struct mlx5_ifc_modify_rq_out_bits {
6235         u8         status[0x8];
6236         u8         reserved_at_8[0x18];
6237
6238         u8         syndrome[0x20];
6239
6240         u8         reserved_at_40[0x40];
6241 };
6242
6243 enum {
6244         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6245         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6246         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6247 };
6248
6249 struct mlx5_ifc_modify_rq_in_bits {
6250         u8         opcode[0x10];
6251         u8         uid[0x10];
6252
6253         u8         reserved_at_20[0x10];
6254         u8         op_mod[0x10];
6255
6256         u8         rq_state[0x4];
6257         u8         reserved_at_44[0x4];
6258         u8         rqn[0x18];
6259
6260         u8         reserved_at_60[0x20];
6261
6262         u8         modify_bitmask[0x40];
6263
6264         u8         reserved_at_c0[0x40];
6265
6266         struct mlx5_ifc_rqc_bits ctx;
6267 };
6268
6269 struct mlx5_ifc_modify_rmp_out_bits {
6270         u8         status[0x8];
6271         u8         reserved_at_8[0x18];
6272
6273         u8         syndrome[0x20];
6274
6275         u8         reserved_at_40[0x40];
6276 };
6277
6278 struct mlx5_ifc_rmp_bitmask_bits {
6279         u8         reserved_at_0[0x20];
6280
6281         u8         reserved_at_20[0x1f];
6282         u8         lwm[0x1];
6283 };
6284
6285 struct mlx5_ifc_modify_rmp_in_bits {
6286         u8         opcode[0x10];
6287         u8         uid[0x10];
6288
6289         u8         reserved_at_20[0x10];
6290         u8         op_mod[0x10];
6291
6292         u8         rmp_state[0x4];
6293         u8         reserved_at_44[0x4];
6294         u8         rmpn[0x18];
6295
6296         u8         reserved_at_60[0x20];
6297
6298         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6299
6300         u8         reserved_at_c0[0x40];
6301
6302         struct mlx5_ifc_rmpc_bits ctx;
6303 };
6304
6305 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6306         u8         status[0x8];
6307         u8         reserved_at_8[0x18];
6308
6309         u8         syndrome[0x20];
6310
6311         u8         reserved_at_40[0x40];
6312 };
6313
6314 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6315         u8         reserved_at_0[0x12];
6316         u8         affiliation[0x1];
6317         u8         reserved_at_13[0x1];
6318         u8         disable_uc_local_lb[0x1];
6319         u8         disable_mc_local_lb[0x1];
6320         u8         node_guid[0x1];
6321         u8         port_guid[0x1];
6322         u8         min_inline[0x1];
6323         u8         mtu[0x1];
6324         u8         change_event[0x1];
6325         u8         promisc[0x1];
6326         u8         permanent_address[0x1];
6327         u8         addresses_list[0x1];
6328         u8         roce_en[0x1];
6329         u8         reserved_at_1f[0x1];
6330 };
6331
6332 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6333         u8         opcode[0x10];
6334         u8         reserved_at_10[0x10];
6335
6336         u8         reserved_at_20[0x10];
6337         u8         op_mod[0x10];
6338
6339         u8         other_vport[0x1];
6340         u8         reserved_at_41[0xf];
6341         u8         vport_number[0x10];
6342
6343         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6344
6345         u8         reserved_at_80[0x780];
6346
6347         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6348 };
6349
6350 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6351         u8         status[0x8];
6352         u8         reserved_at_8[0x18];
6353
6354         u8         syndrome[0x20];
6355
6356         u8         reserved_at_40[0x40];
6357 };
6358
6359 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6360         u8         opcode[0x10];
6361         u8         reserved_at_10[0x10];
6362
6363         u8         reserved_at_20[0x10];
6364         u8         op_mod[0x10];
6365
6366         u8         other_vport[0x1];
6367         u8         reserved_at_41[0xb];
6368         u8         port_num[0x4];
6369         u8         vport_number[0x10];
6370
6371         u8         reserved_at_60[0x20];
6372
6373         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6374 };
6375
6376 struct mlx5_ifc_modify_cq_out_bits {
6377         u8         status[0x8];
6378         u8         reserved_at_8[0x18];
6379
6380         u8         syndrome[0x20];
6381
6382         u8         reserved_at_40[0x40];
6383 };
6384
6385 enum {
6386         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6387         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6388 };
6389
6390 struct mlx5_ifc_modify_cq_in_bits {
6391         u8         opcode[0x10];
6392         u8         uid[0x10];
6393
6394         u8         reserved_at_20[0x10];
6395         u8         op_mod[0x10];
6396
6397         u8         reserved_at_40[0x8];
6398         u8         cqn[0x18];
6399
6400         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6401
6402         struct mlx5_ifc_cqc_bits cq_context;
6403
6404         u8         reserved_at_280[0x60];
6405
6406         u8         cq_umem_valid[0x1];
6407         u8         reserved_at_2e1[0x1f];
6408
6409         u8         reserved_at_300[0x580];
6410
6411         u8         pas[0][0x40];
6412 };
6413
6414 struct mlx5_ifc_modify_cong_status_out_bits {
6415         u8         status[0x8];
6416         u8         reserved_at_8[0x18];
6417
6418         u8         syndrome[0x20];
6419
6420         u8         reserved_at_40[0x40];
6421 };
6422
6423 struct mlx5_ifc_modify_cong_status_in_bits {
6424         u8         opcode[0x10];
6425         u8         reserved_at_10[0x10];
6426
6427         u8         reserved_at_20[0x10];
6428         u8         op_mod[0x10];
6429
6430         u8         reserved_at_40[0x18];
6431         u8         priority[0x4];
6432         u8         cong_protocol[0x4];
6433
6434         u8         enable[0x1];
6435         u8         tag_enable[0x1];
6436         u8         reserved_at_62[0x1e];
6437 };
6438
6439 struct mlx5_ifc_modify_cong_params_out_bits {
6440         u8         status[0x8];
6441         u8         reserved_at_8[0x18];
6442
6443         u8         syndrome[0x20];
6444
6445         u8         reserved_at_40[0x40];
6446 };
6447
6448 struct mlx5_ifc_modify_cong_params_in_bits {
6449         u8         opcode[0x10];
6450         u8         reserved_at_10[0x10];
6451
6452         u8         reserved_at_20[0x10];
6453         u8         op_mod[0x10];
6454
6455         u8         reserved_at_40[0x1c];
6456         u8         cong_protocol[0x4];
6457
6458         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6459
6460         u8         reserved_at_80[0x80];
6461
6462         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6463 };
6464
6465 struct mlx5_ifc_manage_pages_out_bits {
6466         u8         status[0x8];
6467         u8         reserved_at_8[0x18];
6468
6469         u8         syndrome[0x20];
6470
6471         u8         output_num_entries[0x20];
6472
6473         u8         reserved_at_60[0x20];
6474
6475         u8         pas[0][0x40];
6476 };
6477
6478 enum {
6479         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6480         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6481         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6482 };
6483
6484 struct mlx5_ifc_manage_pages_in_bits {
6485         u8         opcode[0x10];
6486         u8         reserved_at_10[0x10];
6487
6488         u8         reserved_at_20[0x10];
6489         u8         op_mod[0x10];
6490
6491         u8         embedded_cpu_function[0x1];
6492         u8         reserved_at_41[0xf];
6493         u8         function_id[0x10];
6494
6495         u8         input_num_entries[0x20];
6496
6497         u8         pas[0][0x40];
6498 };
6499
6500 struct mlx5_ifc_mad_ifc_out_bits {
6501         u8         status[0x8];
6502         u8         reserved_at_8[0x18];
6503
6504         u8         syndrome[0x20];
6505
6506         u8         reserved_at_40[0x40];
6507
6508         u8         response_mad_packet[256][0x8];
6509 };
6510
6511 struct mlx5_ifc_mad_ifc_in_bits {
6512         u8         opcode[0x10];
6513         u8         reserved_at_10[0x10];
6514
6515         u8         reserved_at_20[0x10];
6516         u8         op_mod[0x10];
6517
6518         u8         remote_lid[0x10];
6519         u8         reserved_at_50[0x8];
6520         u8         port[0x8];
6521
6522         u8         reserved_at_60[0x20];
6523
6524         u8         mad[256][0x8];
6525 };
6526
6527 struct mlx5_ifc_init_hca_out_bits {
6528         u8         status[0x8];
6529         u8         reserved_at_8[0x18];
6530
6531         u8         syndrome[0x20];
6532
6533         u8         reserved_at_40[0x40];
6534 };
6535
6536 struct mlx5_ifc_init_hca_in_bits {
6537         u8         opcode[0x10];
6538         u8         reserved_at_10[0x10];
6539
6540         u8         reserved_at_20[0x10];
6541         u8         op_mod[0x10];
6542
6543         u8         reserved_at_40[0x40];
6544         u8         sw_owner_id[4][0x20];
6545 };
6546
6547 struct mlx5_ifc_init2rtr_qp_out_bits {
6548         u8         status[0x8];
6549         u8         reserved_at_8[0x18];
6550
6551         u8         syndrome[0x20];
6552
6553         u8         reserved_at_40[0x40];
6554 };
6555
6556 struct mlx5_ifc_init2rtr_qp_in_bits {
6557         u8         opcode[0x10];
6558         u8         uid[0x10];
6559
6560         u8         reserved_at_20[0x10];
6561         u8         op_mod[0x10];
6562
6563         u8         reserved_at_40[0x8];
6564         u8         qpn[0x18];
6565
6566         u8         reserved_at_60[0x20];
6567
6568         u8         opt_param_mask[0x20];
6569
6570         u8         reserved_at_a0[0x20];
6571
6572         struct mlx5_ifc_qpc_bits qpc;
6573
6574         u8         reserved_at_800[0x80];
6575 };
6576
6577 struct mlx5_ifc_init2init_qp_out_bits {
6578         u8         status[0x8];
6579         u8         reserved_at_8[0x18];
6580
6581         u8         syndrome[0x20];
6582
6583         u8         reserved_at_40[0x40];
6584 };
6585
6586 struct mlx5_ifc_init2init_qp_in_bits {
6587         u8         opcode[0x10];
6588         u8         uid[0x10];
6589
6590         u8         reserved_at_20[0x10];
6591         u8         op_mod[0x10];
6592
6593         u8         reserved_at_40[0x8];
6594         u8         qpn[0x18];
6595
6596         u8         reserved_at_60[0x20];
6597
6598         u8         opt_param_mask[0x20];
6599
6600         u8         reserved_at_a0[0x20];
6601
6602         struct mlx5_ifc_qpc_bits qpc;
6603
6604         u8         reserved_at_800[0x80];
6605 };
6606
6607 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6608         u8         status[0x8];
6609         u8         reserved_at_8[0x18];
6610
6611         u8         syndrome[0x20];
6612
6613         u8         reserved_at_40[0x40];
6614
6615         u8         packet_headers_log[128][0x8];
6616
6617         u8         packet_syndrome[64][0x8];
6618 };
6619
6620 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6621         u8         opcode[0x10];
6622         u8         reserved_at_10[0x10];
6623
6624         u8         reserved_at_20[0x10];
6625         u8         op_mod[0x10];
6626
6627         u8         reserved_at_40[0x40];
6628 };
6629
6630 struct mlx5_ifc_gen_eqe_in_bits {
6631         u8         opcode[0x10];
6632         u8         reserved_at_10[0x10];
6633
6634         u8         reserved_at_20[0x10];
6635         u8         op_mod[0x10];
6636
6637         u8         reserved_at_40[0x18];
6638         u8         eq_number[0x8];
6639
6640         u8         reserved_at_60[0x20];
6641
6642         u8         eqe[64][0x8];
6643 };
6644
6645 struct mlx5_ifc_gen_eq_out_bits {
6646         u8         status[0x8];
6647         u8         reserved_at_8[0x18];
6648
6649         u8         syndrome[0x20];
6650
6651         u8         reserved_at_40[0x40];
6652 };
6653
6654 struct mlx5_ifc_enable_hca_out_bits {
6655         u8         status[0x8];
6656         u8         reserved_at_8[0x18];
6657
6658         u8         syndrome[0x20];
6659
6660         u8         reserved_at_40[0x20];
6661 };
6662
6663 struct mlx5_ifc_enable_hca_in_bits {
6664         u8         opcode[0x10];
6665         u8         reserved_at_10[0x10];
6666
6667         u8         reserved_at_20[0x10];
6668         u8         op_mod[0x10];
6669
6670         u8         embedded_cpu_function[0x1];
6671         u8         reserved_at_41[0xf];
6672         u8         function_id[0x10];
6673
6674         u8         reserved_at_60[0x20];
6675 };
6676
6677 struct mlx5_ifc_drain_dct_out_bits {
6678         u8         status[0x8];
6679         u8         reserved_at_8[0x18];
6680
6681         u8         syndrome[0x20];
6682
6683         u8         reserved_at_40[0x40];
6684 };
6685
6686 struct mlx5_ifc_drain_dct_in_bits {
6687         u8         opcode[0x10];
6688         u8         uid[0x10];
6689
6690         u8         reserved_at_20[0x10];
6691         u8         op_mod[0x10];
6692
6693         u8         reserved_at_40[0x8];
6694         u8         dctn[0x18];
6695
6696         u8         reserved_at_60[0x20];
6697 };
6698
6699 struct mlx5_ifc_disable_hca_out_bits {
6700         u8         status[0x8];
6701         u8         reserved_at_8[0x18];
6702
6703         u8         syndrome[0x20];
6704
6705         u8         reserved_at_40[0x20];
6706 };
6707
6708 struct mlx5_ifc_disable_hca_in_bits {
6709         u8         opcode[0x10];
6710         u8         reserved_at_10[0x10];
6711
6712         u8         reserved_at_20[0x10];
6713         u8         op_mod[0x10];
6714
6715         u8         embedded_cpu_function[0x1];
6716         u8         reserved_at_41[0xf];
6717         u8         function_id[0x10];
6718
6719         u8         reserved_at_60[0x20];
6720 };
6721
6722 struct mlx5_ifc_detach_from_mcg_out_bits {
6723         u8         status[0x8];
6724         u8         reserved_at_8[0x18];
6725
6726         u8         syndrome[0x20];
6727
6728         u8         reserved_at_40[0x40];
6729 };
6730
6731 struct mlx5_ifc_detach_from_mcg_in_bits {
6732         u8         opcode[0x10];
6733         u8         uid[0x10];
6734
6735         u8         reserved_at_20[0x10];
6736         u8         op_mod[0x10];
6737
6738         u8         reserved_at_40[0x8];
6739         u8         qpn[0x18];
6740
6741         u8         reserved_at_60[0x20];
6742
6743         u8         multicast_gid[16][0x8];
6744 };
6745
6746 struct mlx5_ifc_destroy_xrq_out_bits {
6747         u8         status[0x8];
6748         u8         reserved_at_8[0x18];
6749
6750         u8         syndrome[0x20];
6751
6752         u8         reserved_at_40[0x40];
6753 };
6754
6755 struct mlx5_ifc_destroy_xrq_in_bits {
6756         u8         opcode[0x10];
6757         u8         uid[0x10];
6758
6759         u8         reserved_at_20[0x10];
6760         u8         op_mod[0x10];
6761
6762         u8         reserved_at_40[0x8];
6763         u8         xrqn[0x18];
6764
6765         u8         reserved_at_60[0x20];
6766 };
6767
6768 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6769         u8         status[0x8];
6770         u8         reserved_at_8[0x18];
6771
6772         u8         syndrome[0x20];
6773
6774         u8         reserved_at_40[0x40];
6775 };
6776
6777 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6778         u8         opcode[0x10];
6779         u8         uid[0x10];
6780
6781         u8         reserved_at_20[0x10];
6782         u8         op_mod[0x10];
6783
6784         u8         reserved_at_40[0x8];
6785         u8         xrc_srqn[0x18];
6786
6787         u8         reserved_at_60[0x20];
6788 };
6789
6790 struct mlx5_ifc_destroy_tis_out_bits {
6791         u8         status[0x8];
6792         u8         reserved_at_8[0x18];
6793
6794         u8         syndrome[0x20];
6795
6796         u8         reserved_at_40[0x40];
6797 };
6798
6799 struct mlx5_ifc_destroy_tis_in_bits {
6800         u8         opcode[0x10];
6801         u8         uid[0x10];
6802
6803         u8         reserved_at_20[0x10];
6804         u8         op_mod[0x10];
6805
6806         u8         reserved_at_40[0x8];
6807         u8         tisn[0x18];
6808
6809         u8         reserved_at_60[0x20];
6810 };
6811
6812 struct mlx5_ifc_destroy_tir_out_bits {
6813         u8         status[0x8];
6814         u8         reserved_at_8[0x18];
6815
6816         u8         syndrome[0x20];
6817
6818         u8         reserved_at_40[0x40];
6819 };
6820
6821 struct mlx5_ifc_destroy_tir_in_bits {
6822         u8         opcode[0x10];
6823         u8         uid[0x10];
6824
6825         u8         reserved_at_20[0x10];
6826         u8         op_mod[0x10];
6827
6828         u8         reserved_at_40[0x8];
6829         u8         tirn[0x18];
6830
6831         u8         reserved_at_60[0x20];
6832 };
6833
6834 struct mlx5_ifc_destroy_srq_out_bits {
6835         u8         status[0x8];
6836         u8         reserved_at_8[0x18];
6837
6838         u8         syndrome[0x20];
6839
6840         u8         reserved_at_40[0x40];
6841 };
6842
6843 struct mlx5_ifc_destroy_srq_in_bits {
6844         u8         opcode[0x10];
6845         u8         uid[0x10];
6846
6847         u8         reserved_at_20[0x10];
6848         u8         op_mod[0x10];
6849
6850         u8         reserved_at_40[0x8];
6851         u8         srqn[0x18];
6852
6853         u8         reserved_at_60[0x20];
6854 };
6855
6856 struct mlx5_ifc_destroy_sq_out_bits {
6857         u8         status[0x8];
6858         u8         reserved_at_8[0x18];
6859
6860         u8         syndrome[0x20];
6861
6862         u8         reserved_at_40[0x40];
6863 };
6864
6865 struct mlx5_ifc_destroy_sq_in_bits {
6866         u8         opcode[0x10];
6867         u8         uid[0x10];
6868
6869         u8         reserved_at_20[0x10];
6870         u8         op_mod[0x10];
6871
6872         u8         reserved_at_40[0x8];
6873         u8         sqn[0x18];
6874
6875         u8         reserved_at_60[0x20];
6876 };
6877
6878 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6879         u8         status[0x8];
6880         u8         reserved_at_8[0x18];
6881
6882         u8         syndrome[0x20];
6883
6884         u8         reserved_at_40[0x1c0];
6885 };
6886
6887 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6888         u8         opcode[0x10];
6889         u8         reserved_at_10[0x10];
6890
6891         u8         reserved_at_20[0x10];
6892         u8         op_mod[0x10];
6893
6894         u8         scheduling_hierarchy[0x8];
6895         u8         reserved_at_48[0x18];
6896
6897         u8         scheduling_element_id[0x20];
6898
6899         u8         reserved_at_80[0x180];
6900 };
6901
6902 struct mlx5_ifc_destroy_rqt_out_bits {
6903         u8         status[0x8];
6904         u8         reserved_at_8[0x18];
6905
6906         u8         syndrome[0x20];
6907
6908         u8         reserved_at_40[0x40];
6909 };
6910
6911 struct mlx5_ifc_destroy_rqt_in_bits {
6912         u8         opcode[0x10];
6913         u8         uid[0x10];
6914
6915         u8         reserved_at_20[0x10];
6916         u8         op_mod[0x10];
6917
6918         u8         reserved_at_40[0x8];
6919         u8         rqtn[0x18];
6920
6921         u8         reserved_at_60[0x20];
6922 };
6923
6924 struct mlx5_ifc_destroy_rq_out_bits {
6925         u8         status[0x8];
6926         u8         reserved_at_8[0x18];
6927
6928         u8         syndrome[0x20];
6929
6930         u8         reserved_at_40[0x40];
6931 };
6932
6933 struct mlx5_ifc_destroy_rq_in_bits {
6934         u8         opcode[0x10];
6935         u8         uid[0x10];
6936
6937         u8         reserved_at_20[0x10];
6938         u8         op_mod[0x10];
6939
6940         u8         reserved_at_40[0x8];
6941         u8         rqn[0x18];
6942
6943         u8         reserved_at_60[0x20];
6944 };
6945
6946 struct mlx5_ifc_set_delay_drop_params_in_bits {
6947         u8         opcode[0x10];
6948         u8         reserved_at_10[0x10];
6949
6950         u8         reserved_at_20[0x10];
6951         u8         op_mod[0x10];
6952
6953         u8         reserved_at_40[0x20];
6954
6955         u8         reserved_at_60[0x10];
6956         u8         delay_drop_timeout[0x10];
6957 };
6958
6959 struct mlx5_ifc_set_delay_drop_params_out_bits {
6960         u8         status[0x8];
6961         u8         reserved_at_8[0x18];
6962
6963         u8         syndrome[0x20];
6964
6965         u8         reserved_at_40[0x40];
6966 };
6967
6968 struct mlx5_ifc_destroy_rmp_out_bits {
6969         u8         status[0x8];
6970         u8         reserved_at_8[0x18];
6971
6972         u8         syndrome[0x20];
6973
6974         u8         reserved_at_40[0x40];
6975 };
6976
6977 struct mlx5_ifc_destroy_rmp_in_bits {
6978         u8         opcode[0x10];
6979         u8         uid[0x10];
6980
6981         u8         reserved_at_20[0x10];
6982         u8         op_mod[0x10];
6983
6984         u8         reserved_at_40[0x8];
6985         u8         rmpn[0x18];
6986
6987         u8         reserved_at_60[0x20];
6988 };
6989
6990 struct mlx5_ifc_destroy_qp_out_bits {
6991         u8         status[0x8];
6992         u8         reserved_at_8[0x18];
6993
6994         u8         syndrome[0x20];
6995
6996         u8         reserved_at_40[0x40];
6997 };
6998
6999 struct mlx5_ifc_destroy_qp_in_bits {
7000         u8         opcode[0x10];
7001         u8         uid[0x10];
7002
7003         u8         reserved_at_20[0x10];
7004         u8         op_mod[0x10];
7005
7006         u8         reserved_at_40[0x8];
7007         u8         qpn[0x18];
7008
7009         u8         reserved_at_60[0x20];
7010 };
7011
7012 struct mlx5_ifc_destroy_psv_out_bits {
7013         u8         status[0x8];
7014         u8         reserved_at_8[0x18];
7015
7016         u8         syndrome[0x20];
7017
7018         u8         reserved_at_40[0x40];
7019 };
7020
7021 struct mlx5_ifc_destroy_psv_in_bits {
7022         u8         opcode[0x10];
7023         u8         reserved_at_10[0x10];
7024
7025         u8         reserved_at_20[0x10];
7026         u8         op_mod[0x10];
7027
7028         u8         reserved_at_40[0x8];
7029         u8         psvn[0x18];
7030
7031         u8         reserved_at_60[0x20];
7032 };
7033
7034 struct mlx5_ifc_destroy_mkey_out_bits {
7035         u8         status[0x8];
7036         u8         reserved_at_8[0x18];
7037
7038         u8         syndrome[0x20];
7039
7040         u8         reserved_at_40[0x40];
7041 };
7042
7043 struct mlx5_ifc_destroy_mkey_in_bits {
7044         u8         opcode[0x10];
7045         u8         reserved_at_10[0x10];
7046
7047         u8         reserved_at_20[0x10];
7048         u8         op_mod[0x10];
7049
7050         u8         reserved_at_40[0x8];
7051         u8         mkey_index[0x18];
7052
7053         u8         reserved_at_60[0x20];
7054 };
7055
7056 struct mlx5_ifc_destroy_flow_table_out_bits {
7057         u8         status[0x8];
7058         u8         reserved_at_8[0x18];
7059
7060         u8         syndrome[0x20];
7061
7062         u8         reserved_at_40[0x40];
7063 };
7064
7065 struct mlx5_ifc_destroy_flow_table_in_bits {
7066         u8         opcode[0x10];
7067         u8         reserved_at_10[0x10];
7068
7069         u8         reserved_at_20[0x10];
7070         u8         op_mod[0x10];
7071
7072         u8         other_vport[0x1];
7073         u8         reserved_at_41[0xf];
7074         u8         vport_number[0x10];
7075
7076         u8         reserved_at_60[0x20];
7077
7078         u8         table_type[0x8];
7079         u8         reserved_at_88[0x18];
7080
7081         u8         reserved_at_a0[0x8];
7082         u8         table_id[0x18];
7083
7084         u8         reserved_at_c0[0x140];
7085 };
7086
7087 struct mlx5_ifc_destroy_flow_group_out_bits {
7088         u8         status[0x8];
7089         u8         reserved_at_8[0x18];
7090
7091         u8         syndrome[0x20];
7092
7093         u8         reserved_at_40[0x40];
7094 };
7095
7096 struct mlx5_ifc_destroy_flow_group_in_bits {
7097         u8         opcode[0x10];
7098         u8         reserved_at_10[0x10];
7099
7100         u8         reserved_at_20[0x10];
7101         u8         op_mod[0x10];
7102
7103         u8         other_vport[0x1];
7104         u8         reserved_at_41[0xf];
7105         u8         vport_number[0x10];
7106
7107         u8         reserved_at_60[0x20];
7108
7109         u8         table_type[0x8];
7110         u8         reserved_at_88[0x18];
7111
7112         u8         reserved_at_a0[0x8];
7113         u8         table_id[0x18];
7114
7115         u8         group_id[0x20];
7116
7117         u8         reserved_at_e0[0x120];
7118 };
7119
7120 struct mlx5_ifc_destroy_eq_out_bits {
7121         u8         status[0x8];
7122         u8         reserved_at_8[0x18];
7123
7124         u8         syndrome[0x20];
7125
7126         u8         reserved_at_40[0x40];
7127 };
7128
7129 struct mlx5_ifc_destroy_eq_in_bits {
7130         u8         opcode[0x10];
7131         u8         reserved_at_10[0x10];
7132
7133         u8         reserved_at_20[0x10];
7134         u8         op_mod[0x10];
7135
7136         u8         reserved_at_40[0x18];
7137         u8         eq_number[0x8];
7138
7139         u8         reserved_at_60[0x20];
7140 };
7141
7142 struct mlx5_ifc_destroy_dct_out_bits {
7143         u8         status[0x8];
7144         u8         reserved_at_8[0x18];
7145
7146         u8         syndrome[0x20];
7147
7148         u8         reserved_at_40[0x40];
7149 };
7150
7151 struct mlx5_ifc_destroy_dct_in_bits {
7152         u8         opcode[0x10];
7153         u8         uid[0x10];
7154
7155         u8         reserved_at_20[0x10];
7156         u8         op_mod[0x10];
7157
7158         u8         reserved_at_40[0x8];
7159         u8         dctn[0x18];
7160
7161         u8         reserved_at_60[0x20];
7162 };
7163
7164 struct mlx5_ifc_destroy_cq_out_bits {
7165         u8         status[0x8];
7166         u8         reserved_at_8[0x18];
7167
7168         u8         syndrome[0x20];
7169
7170         u8         reserved_at_40[0x40];
7171 };
7172
7173 struct mlx5_ifc_destroy_cq_in_bits {
7174         u8         opcode[0x10];
7175         u8         uid[0x10];
7176
7177         u8         reserved_at_20[0x10];
7178         u8         op_mod[0x10];
7179
7180         u8         reserved_at_40[0x8];
7181         u8         cqn[0x18];
7182
7183         u8         reserved_at_60[0x20];
7184 };
7185
7186 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7187         u8         status[0x8];
7188         u8         reserved_at_8[0x18];
7189
7190         u8         syndrome[0x20];
7191
7192         u8         reserved_at_40[0x40];
7193 };
7194
7195 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7196         u8         opcode[0x10];
7197         u8         reserved_at_10[0x10];
7198
7199         u8         reserved_at_20[0x10];
7200         u8         op_mod[0x10];
7201
7202         u8         reserved_at_40[0x20];
7203
7204         u8         reserved_at_60[0x10];
7205         u8         vxlan_udp_port[0x10];
7206 };
7207
7208 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7209         u8         status[0x8];
7210         u8         reserved_at_8[0x18];
7211
7212         u8         syndrome[0x20];
7213
7214         u8         reserved_at_40[0x40];
7215 };
7216
7217 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7218         u8         opcode[0x10];
7219         u8         reserved_at_10[0x10];
7220
7221         u8         reserved_at_20[0x10];
7222         u8         op_mod[0x10];
7223
7224         u8         reserved_at_40[0x60];
7225
7226         u8         reserved_at_a0[0x8];
7227         u8         table_index[0x18];
7228
7229         u8         reserved_at_c0[0x140];
7230 };
7231
7232 struct mlx5_ifc_delete_fte_out_bits {
7233         u8         status[0x8];
7234         u8         reserved_at_8[0x18];
7235
7236         u8         syndrome[0x20];
7237
7238         u8         reserved_at_40[0x40];
7239 };
7240
7241 struct mlx5_ifc_delete_fte_in_bits {
7242         u8         opcode[0x10];
7243         u8         reserved_at_10[0x10];
7244
7245         u8         reserved_at_20[0x10];
7246         u8         op_mod[0x10];
7247
7248         u8         other_vport[0x1];
7249         u8         reserved_at_41[0xf];
7250         u8         vport_number[0x10];
7251
7252         u8         reserved_at_60[0x20];
7253
7254         u8         table_type[0x8];
7255         u8         reserved_at_88[0x18];
7256
7257         u8         reserved_at_a0[0x8];
7258         u8         table_id[0x18];
7259
7260         u8         reserved_at_c0[0x40];
7261
7262         u8         flow_index[0x20];
7263
7264         u8         reserved_at_120[0xe0];
7265 };
7266
7267 struct mlx5_ifc_dealloc_xrcd_out_bits {
7268         u8         status[0x8];
7269         u8         reserved_at_8[0x18];
7270
7271         u8         syndrome[0x20];
7272
7273         u8         reserved_at_40[0x40];
7274 };
7275
7276 struct mlx5_ifc_dealloc_xrcd_in_bits {
7277         u8         opcode[0x10];
7278         u8         uid[0x10];
7279
7280         u8         reserved_at_20[0x10];
7281         u8         op_mod[0x10];
7282
7283         u8         reserved_at_40[0x8];
7284         u8         xrcd[0x18];
7285
7286         u8         reserved_at_60[0x20];
7287 };
7288
7289 struct mlx5_ifc_dealloc_uar_out_bits {
7290         u8         status[0x8];
7291         u8         reserved_at_8[0x18];
7292
7293         u8         syndrome[0x20];
7294
7295         u8         reserved_at_40[0x40];
7296 };
7297
7298 struct mlx5_ifc_dealloc_uar_in_bits {
7299         u8         opcode[0x10];
7300         u8         reserved_at_10[0x10];
7301
7302         u8         reserved_at_20[0x10];
7303         u8         op_mod[0x10];
7304
7305         u8         reserved_at_40[0x8];
7306         u8         uar[0x18];
7307
7308         u8         reserved_at_60[0x20];
7309 };
7310
7311 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7312         u8         status[0x8];
7313         u8         reserved_at_8[0x18];
7314
7315         u8         syndrome[0x20];
7316
7317         u8         reserved_at_40[0x40];
7318 };
7319
7320 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7321         u8         opcode[0x10];
7322         u8         uid[0x10];
7323
7324         u8         reserved_at_20[0x10];
7325         u8         op_mod[0x10];
7326
7327         u8         reserved_at_40[0x8];
7328         u8         transport_domain[0x18];
7329
7330         u8         reserved_at_60[0x20];
7331 };
7332
7333 struct mlx5_ifc_dealloc_q_counter_out_bits {
7334         u8         status[0x8];
7335         u8         reserved_at_8[0x18];
7336
7337         u8         syndrome[0x20];
7338
7339         u8         reserved_at_40[0x40];
7340 };
7341
7342 struct mlx5_ifc_dealloc_q_counter_in_bits {
7343         u8         opcode[0x10];
7344         u8         reserved_at_10[0x10];
7345
7346         u8         reserved_at_20[0x10];
7347         u8         op_mod[0x10];
7348
7349         u8         reserved_at_40[0x18];
7350         u8         counter_set_id[0x8];
7351
7352         u8         reserved_at_60[0x20];
7353 };
7354
7355 struct mlx5_ifc_dealloc_pd_out_bits {
7356         u8         status[0x8];
7357         u8         reserved_at_8[0x18];
7358
7359         u8         syndrome[0x20];
7360
7361         u8         reserved_at_40[0x40];
7362 };
7363
7364 struct mlx5_ifc_dealloc_pd_in_bits {
7365         u8         opcode[0x10];
7366         u8         uid[0x10];
7367
7368         u8         reserved_at_20[0x10];
7369         u8         op_mod[0x10];
7370
7371         u8         reserved_at_40[0x8];
7372         u8         pd[0x18];
7373
7374         u8         reserved_at_60[0x20];
7375 };
7376
7377 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7378         u8         status[0x8];
7379         u8         reserved_at_8[0x18];
7380
7381         u8         syndrome[0x20];
7382
7383         u8         reserved_at_40[0x40];
7384 };
7385
7386 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7387         u8         opcode[0x10];
7388         u8         reserved_at_10[0x10];
7389
7390         u8         reserved_at_20[0x10];
7391         u8         op_mod[0x10];
7392
7393         u8         flow_counter_id[0x20];
7394
7395         u8         reserved_at_60[0x20];
7396 };
7397
7398 struct mlx5_ifc_create_xrq_out_bits {
7399         u8         status[0x8];
7400         u8         reserved_at_8[0x18];
7401
7402         u8         syndrome[0x20];
7403
7404         u8         reserved_at_40[0x8];
7405         u8         xrqn[0x18];
7406
7407         u8         reserved_at_60[0x20];
7408 };
7409
7410 struct mlx5_ifc_create_xrq_in_bits {
7411         u8         opcode[0x10];
7412         u8         uid[0x10];
7413
7414         u8         reserved_at_20[0x10];
7415         u8         op_mod[0x10];
7416
7417         u8         reserved_at_40[0x40];
7418
7419         struct mlx5_ifc_xrqc_bits xrq_context;
7420 };
7421
7422 struct mlx5_ifc_create_xrc_srq_out_bits {
7423         u8         status[0x8];
7424         u8         reserved_at_8[0x18];
7425
7426         u8         syndrome[0x20];
7427
7428         u8         reserved_at_40[0x8];
7429         u8         xrc_srqn[0x18];
7430
7431         u8         reserved_at_60[0x20];
7432 };
7433
7434 struct mlx5_ifc_create_xrc_srq_in_bits {
7435         u8         opcode[0x10];
7436         u8         uid[0x10];
7437
7438         u8         reserved_at_20[0x10];
7439         u8         op_mod[0x10];
7440
7441         u8         reserved_at_40[0x40];
7442
7443         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7444
7445         u8         reserved_at_280[0x60];
7446
7447         u8         xrc_srq_umem_valid[0x1];
7448         u8         reserved_at_2e1[0x1f];
7449
7450         u8         reserved_at_300[0x580];
7451
7452         u8         pas[0][0x40];
7453 };
7454
7455 struct mlx5_ifc_create_tis_out_bits {
7456         u8         status[0x8];
7457         u8         reserved_at_8[0x18];
7458
7459         u8         syndrome[0x20];
7460
7461         u8         reserved_at_40[0x8];
7462         u8         tisn[0x18];
7463
7464         u8         reserved_at_60[0x20];
7465 };
7466
7467 struct mlx5_ifc_create_tis_in_bits {
7468         u8         opcode[0x10];
7469         u8         uid[0x10];
7470
7471         u8         reserved_at_20[0x10];
7472         u8         op_mod[0x10];
7473
7474         u8         reserved_at_40[0xc0];
7475
7476         struct mlx5_ifc_tisc_bits ctx;
7477 };
7478
7479 struct mlx5_ifc_create_tir_out_bits {
7480         u8         status[0x8];
7481         u8         icm_address_63_40[0x18];
7482
7483         u8         syndrome[0x20];
7484
7485         u8         icm_address_39_32[0x8];
7486         u8         tirn[0x18];
7487
7488         u8         icm_address_31_0[0x20];
7489 };
7490
7491 struct mlx5_ifc_create_tir_in_bits {
7492         u8         opcode[0x10];
7493         u8         uid[0x10];
7494
7495         u8         reserved_at_20[0x10];
7496         u8         op_mod[0x10];
7497
7498         u8         reserved_at_40[0xc0];
7499
7500         struct mlx5_ifc_tirc_bits ctx;
7501 };
7502
7503 struct mlx5_ifc_create_srq_out_bits {
7504         u8         status[0x8];
7505         u8         reserved_at_8[0x18];
7506
7507         u8         syndrome[0x20];
7508
7509         u8         reserved_at_40[0x8];
7510         u8         srqn[0x18];
7511
7512         u8         reserved_at_60[0x20];
7513 };
7514
7515 struct mlx5_ifc_create_srq_in_bits {
7516         u8         opcode[0x10];
7517         u8         uid[0x10];
7518
7519         u8         reserved_at_20[0x10];
7520         u8         op_mod[0x10];
7521
7522         u8         reserved_at_40[0x40];
7523
7524         struct mlx5_ifc_srqc_bits srq_context_entry;
7525
7526         u8         reserved_at_280[0x600];
7527
7528         u8         pas[0][0x40];
7529 };
7530
7531 struct mlx5_ifc_create_sq_out_bits {
7532         u8         status[0x8];
7533         u8         reserved_at_8[0x18];
7534
7535         u8         syndrome[0x20];
7536
7537         u8         reserved_at_40[0x8];
7538         u8         sqn[0x18];
7539
7540         u8         reserved_at_60[0x20];
7541 };
7542
7543 struct mlx5_ifc_create_sq_in_bits {
7544         u8         opcode[0x10];
7545         u8         uid[0x10];
7546
7547         u8         reserved_at_20[0x10];
7548         u8         op_mod[0x10];
7549
7550         u8         reserved_at_40[0xc0];
7551
7552         struct mlx5_ifc_sqc_bits ctx;
7553 };
7554
7555 struct mlx5_ifc_create_scheduling_element_out_bits {
7556         u8         status[0x8];
7557         u8         reserved_at_8[0x18];
7558
7559         u8         syndrome[0x20];
7560
7561         u8         reserved_at_40[0x40];
7562
7563         u8         scheduling_element_id[0x20];
7564
7565         u8         reserved_at_a0[0x160];
7566 };
7567
7568 struct mlx5_ifc_create_scheduling_element_in_bits {
7569         u8         opcode[0x10];
7570         u8         reserved_at_10[0x10];
7571
7572         u8         reserved_at_20[0x10];
7573         u8         op_mod[0x10];
7574
7575         u8         scheduling_hierarchy[0x8];
7576         u8         reserved_at_48[0x18];
7577
7578         u8         reserved_at_60[0xa0];
7579
7580         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7581
7582         u8         reserved_at_300[0x100];
7583 };
7584
7585 struct mlx5_ifc_create_rqt_out_bits {
7586         u8         status[0x8];
7587         u8         reserved_at_8[0x18];
7588
7589         u8         syndrome[0x20];
7590
7591         u8         reserved_at_40[0x8];
7592         u8         rqtn[0x18];
7593
7594         u8         reserved_at_60[0x20];
7595 };
7596
7597 struct mlx5_ifc_create_rqt_in_bits {
7598         u8         opcode[0x10];
7599         u8         uid[0x10];
7600
7601         u8         reserved_at_20[0x10];
7602         u8         op_mod[0x10];
7603
7604         u8         reserved_at_40[0xc0];
7605
7606         struct mlx5_ifc_rqtc_bits rqt_context;
7607 };
7608
7609 struct mlx5_ifc_create_rq_out_bits {
7610         u8         status[0x8];
7611         u8         reserved_at_8[0x18];
7612
7613         u8         syndrome[0x20];
7614
7615         u8         reserved_at_40[0x8];
7616         u8         rqn[0x18];
7617
7618         u8         reserved_at_60[0x20];
7619 };
7620
7621 struct mlx5_ifc_create_rq_in_bits {
7622         u8         opcode[0x10];
7623         u8         uid[0x10];
7624
7625         u8         reserved_at_20[0x10];
7626         u8         op_mod[0x10];
7627
7628         u8         reserved_at_40[0xc0];
7629
7630         struct mlx5_ifc_rqc_bits ctx;
7631 };
7632
7633 struct mlx5_ifc_create_rmp_out_bits {
7634         u8         status[0x8];
7635         u8         reserved_at_8[0x18];
7636
7637         u8         syndrome[0x20];
7638
7639         u8         reserved_at_40[0x8];
7640         u8         rmpn[0x18];
7641
7642         u8         reserved_at_60[0x20];
7643 };
7644
7645 struct mlx5_ifc_create_rmp_in_bits {
7646         u8         opcode[0x10];
7647         u8         uid[0x10];
7648
7649         u8         reserved_at_20[0x10];
7650         u8         op_mod[0x10];
7651
7652         u8         reserved_at_40[0xc0];
7653
7654         struct mlx5_ifc_rmpc_bits ctx;
7655 };
7656
7657 struct mlx5_ifc_create_qp_out_bits {
7658         u8         status[0x8];
7659         u8         reserved_at_8[0x18];
7660
7661         u8         syndrome[0x20];
7662
7663         u8         reserved_at_40[0x8];
7664         u8         qpn[0x18];
7665
7666         u8         reserved_at_60[0x20];
7667 };
7668
7669 struct mlx5_ifc_create_qp_in_bits {
7670         u8         opcode[0x10];
7671         u8         uid[0x10];
7672
7673         u8         reserved_at_20[0x10];
7674         u8         op_mod[0x10];
7675
7676         u8         reserved_at_40[0x40];
7677
7678         u8         opt_param_mask[0x20];
7679
7680         u8         reserved_at_a0[0x20];
7681
7682         struct mlx5_ifc_qpc_bits qpc;
7683
7684         u8         reserved_at_800[0x60];
7685
7686         u8         wq_umem_valid[0x1];
7687         u8         reserved_at_861[0x1f];
7688
7689         u8         pas[0][0x40];
7690 };
7691
7692 struct mlx5_ifc_create_psv_out_bits {
7693         u8         status[0x8];
7694         u8         reserved_at_8[0x18];
7695
7696         u8         syndrome[0x20];
7697
7698         u8         reserved_at_40[0x40];
7699
7700         u8         reserved_at_80[0x8];
7701         u8         psv0_index[0x18];
7702
7703         u8         reserved_at_a0[0x8];
7704         u8         psv1_index[0x18];
7705
7706         u8         reserved_at_c0[0x8];
7707         u8         psv2_index[0x18];
7708
7709         u8         reserved_at_e0[0x8];
7710         u8         psv3_index[0x18];
7711 };
7712
7713 struct mlx5_ifc_create_psv_in_bits {
7714         u8         opcode[0x10];
7715         u8         reserved_at_10[0x10];
7716
7717         u8         reserved_at_20[0x10];
7718         u8         op_mod[0x10];
7719
7720         u8         num_psv[0x4];
7721         u8         reserved_at_44[0x4];
7722         u8         pd[0x18];
7723
7724         u8         reserved_at_60[0x20];
7725 };
7726
7727 struct mlx5_ifc_create_mkey_out_bits {
7728         u8         status[0x8];
7729         u8         reserved_at_8[0x18];
7730
7731         u8         syndrome[0x20];
7732
7733         u8         reserved_at_40[0x8];
7734         u8         mkey_index[0x18];
7735
7736         u8         reserved_at_60[0x20];
7737 };
7738
7739 struct mlx5_ifc_create_mkey_in_bits {
7740         u8         opcode[0x10];
7741         u8         reserved_at_10[0x10];
7742
7743         u8         reserved_at_20[0x10];
7744         u8         op_mod[0x10];
7745
7746         u8         reserved_at_40[0x20];
7747
7748         u8         pg_access[0x1];
7749         u8         mkey_umem_valid[0x1];
7750         u8         reserved_at_62[0x1e];
7751
7752         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7753
7754         u8         reserved_at_280[0x80];
7755
7756         u8         translations_octword_actual_size[0x20];
7757
7758         u8         reserved_at_320[0x560];
7759
7760         u8         klm_pas_mtt[0][0x20];
7761 };
7762
7763 enum {
7764         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7765         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7766         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7767         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7768         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7769         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7770         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7771 };
7772
7773 struct mlx5_ifc_create_flow_table_out_bits {
7774         u8         status[0x8];
7775         u8         icm_address_63_40[0x18];
7776
7777         u8         syndrome[0x20];
7778
7779         u8         icm_address_39_32[0x8];
7780         u8         table_id[0x18];
7781
7782         u8         icm_address_31_0[0x20];
7783 };
7784
7785 struct mlx5_ifc_create_flow_table_in_bits {
7786         u8         opcode[0x10];
7787         u8         reserved_at_10[0x10];
7788
7789         u8         reserved_at_20[0x10];
7790         u8         op_mod[0x10];
7791
7792         u8         other_vport[0x1];
7793         u8         reserved_at_41[0xf];
7794         u8         vport_number[0x10];
7795
7796         u8         reserved_at_60[0x20];
7797
7798         u8         table_type[0x8];
7799         u8         reserved_at_88[0x18];
7800
7801         u8         reserved_at_a0[0x20];
7802
7803         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7804 };
7805
7806 struct mlx5_ifc_create_flow_group_out_bits {
7807         u8         status[0x8];
7808         u8         reserved_at_8[0x18];
7809
7810         u8         syndrome[0x20];
7811
7812         u8         reserved_at_40[0x8];
7813         u8         group_id[0x18];
7814
7815         u8         reserved_at_60[0x20];
7816 };
7817
7818 enum {
7819         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7820         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7821         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7822         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7823 };
7824
7825 struct mlx5_ifc_create_flow_group_in_bits {
7826         u8         opcode[0x10];
7827         u8         reserved_at_10[0x10];
7828
7829         u8         reserved_at_20[0x10];
7830         u8         op_mod[0x10];
7831
7832         u8         other_vport[0x1];
7833         u8         reserved_at_41[0xf];
7834         u8         vport_number[0x10];
7835
7836         u8         reserved_at_60[0x20];
7837
7838         u8         table_type[0x8];
7839         u8         reserved_at_88[0x18];
7840
7841         u8         reserved_at_a0[0x8];
7842         u8         table_id[0x18];
7843
7844         u8         source_eswitch_owner_vhca_id_valid[0x1];
7845
7846         u8         reserved_at_c1[0x1f];
7847
7848         u8         start_flow_index[0x20];
7849
7850         u8         reserved_at_100[0x20];
7851
7852         u8         end_flow_index[0x20];
7853
7854         u8         reserved_at_140[0xa0];
7855
7856         u8         reserved_at_1e0[0x18];
7857         u8         match_criteria_enable[0x8];
7858
7859         struct mlx5_ifc_fte_match_param_bits match_criteria;
7860
7861         u8         reserved_at_1200[0xe00];
7862 };
7863
7864 struct mlx5_ifc_create_eq_out_bits {
7865         u8         status[0x8];
7866         u8         reserved_at_8[0x18];
7867
7868         u8         syndrome[0x20];
7869
7870         u8         reserved_at_40[0x18];
7871         u8         eq_number[0x8];
7872
7873         u8         reserved_at_60[0x20];
7874 };
7875
7876 struct mlx5_ifc_create_eq_in_bits {
7877         u8         opcode[0x10];
7878         u8         uid[0x10];
7879
7880         u8         reserved_at_20[0x10];
7881         u8         op_mod[0x10];
7882
7883         u8         reserved_at_40[0x40];
7884
7885         struct mlx5_ifc_eqc_bits eq_context_entry;
7886
7887         u8         reserved_at_280[0x40];
7888
7889         u8         event_bitmask[4][0x40];
7890
7891         u8         reserved_at_3c0[0x4c0];
7892
7893         u8         pas[0][0x40];
7894 };
7895
7896 struct mlx5_ifc_create_dct_out_bits {
7897         u8         status[0x8];
7898         u8         reserved_at_8[0x18];
7899
7900         u8         syndrome[0x20];
7901
7902         u8         reserved_at_40[0x8];
7903         u8         dctn[0x18];
7904
7905         u8         reserved_at_60[0x20];
7906 };
7907
7908 struct mlx5_ifc_create_dct_in_bits {
7909         u8         opcode[0x10];
7910         u8         uid[0x10];
7911
7912         u8         reserved_at_20[0x10];
7913         u8         op_mod[0x10];
7914
7915         u8         reserved_at_40[0x40];
7916
7917         struct mlx5_ifc_dctc_bits dct_context_entry;
7918
7919         u8         reserved_at_280[0x180];
7920 };
7921
7922 struct mlx5_ifc_create_cq_out_bits {
7923         u8         status[0x8];
7924         u8         reserved_at_8[0x18];
7925
7926         u8         syndrome[0x20];
7927
7928         u8         reserved_at_40[0x8];
7929         u8         cqn[0x18];
7930
7931         u8         reserved_at_60[0x20];
7932 };
7933
7934 struct mlx5_ifc_create_cq_in_bits {
7935         u8         opcode[0x10];
7936         u8         uid[0x10];
7937
7938         u8         reserved_at_20[0x10];
7939         u8         op_mod[0x10];
7940
7941         u8         reserved_at_40[0x40];
7942
7943         struct mlx5_ifc_cqc_bits cq_context;
7944
7945         u8         reserved_at_280[0x60];
7946
7947         u8         cq_umem_valid[0x1];
7948         u8         reserved_at_2e1[0x59f];
7949
7950         u8         pas[0][0x40];
7951 };
7952
7953 struct mlx5_ifc_config_int_moderation_out_bits {
7954         u8         status[0x8];
7955         u8         reserved_at_8[0x18];
7956
7957         u8         syndrome[0x20];
7958
7959         u8         reserved_at_40[0x4];
7960         u8         min_delay[0xc];
7961         u8         int_vector[0x10];
7962
7963         u8         reserved_at_60[0x20];
7964 };
7965
7966 enum {
7967         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7968         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7969 };
7970
7971 struct mlx5_ifc_config_int_moderation_in_bits {
7972         u8         opcode[0x10];
7973         u8         reserved_at_10[0x10];
7974
7975         u8         reserved_at_20[0x10];
7976         u8         op_mod[0x10];
7977
7978         u8         reserved_at_40[0x4];
7979         u8         min_delay[0xc];
7980         u8         int_vector[0x10];
7981
7982         u8         reserved_at_60[0x20];
7983 };
7984
7985 struct mlx5_ifc_attach_to_mcg_out_bits {
7986         u8         status[0x8];
7987         u8         reserved_at_8[0x18];
7988
7989         u8         syndrome[0x20];
7990
7991         u8         reserved_at_40[0x40];
7992 };
7993
7994 struct mlx5_ifc_attach_to_mcg_in_bits {
7995         u8         opcode[0x10];
7996         u8         uid[0x10];
7997
7998         u8         reserved_at_20[0x10];
7999         u8         op_mod[0x10];
8000
8001         u8         reserved_at_40[0x8];
8002         u8         qpn[0x18];
8003
8004         u8         reserved_at_60[0x20];
8005
8006         u8         multicast_gid[16][0x8];
8007 };
8008
8009 struct mlx5_ifc_arm_xrq_out_bits {
8010         u8         status[0x8];
8011         u8         reserved_at_8[0x18];
8012
8013         u8         syndrome[0x20];
8014
8015         u8         reserved_at_40[0x40];
8016 };
8017
8018 struct mlx5_ifc_arm_xrq_in_bits {
8019         u8         opcode[0x10];
8020         u8         reserved_at_10[0x10];
8021
8022         u8         reserved_at_20[0x10];
8023         u8         op_mod[0x10];
8024
8025         u8         reserved_at_40[0x8];
8026         u8         xrqn[0x18];
8027
8028         u8         reserved_at_60[0x10];
8029         u8         lwm[0x10];
8030 };
8031
8032 struct mlx5_ifc_arm_xrc_srq_out_bits {
8033         u8         status[0x8];
8034         u8         reserved_at_8[0x18];
8035
8036         u8         syndrome[0x20];
8037
8038         u8         reserved_at_40[0x40];
8039 };
8040
8041 enum {
8042         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8043 };
8044
8045 struct mlx5_ifc_arm_xrc_srq_in_bits {
8046         u8         opcode[0x10];
8047         u8         uid[0x10];
8048
8049         u8         reserved_at_20[0x10];
8050         u8         op_mod[0x10];
8051
8052         u8         reserved_at_40[0x8];
8053         u8         xrc_srqn[0x18];
8054
8055         u8         reserved_at_60[0x10];
8056         u8         lwm[0x10];
8057 };
8058
8059 struct mlx5_ifc_arm_rq_out_bits {
8060         u8         status[0x8];
8061         u8         reserved_at_8[0x18];
8062
8063         u8         syndrome[0x20];
8064
8065         u8         reserved_at_40[0x40];
8066 };
8067
8068 enum {
8069         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8070         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8071 };
8072
8073 struct mlx5_ifc_arm_rq_in_bits {
8074         u8         opcode[0x10];
8075         u8         uid[0x10];
8076
8077         u8         reserved_at_20[0x10];
8078         u8         op_mod[0x10];
8079
8080         u8         reserved_at_40[0x8];
8081         u8         srq_number[0x18];
8082
8083         u8         reserved_at_60[0x10];
8084         u8         lwm[0x10];
8085 };
8086
8087 struct mlx5_ifc_arm_dct_out_bits {
8088         u8         status[0x8];
8089         u8         reserved_at_8[0x18];
8090
8091         u8         syndrome[0x20];
8092
8093         u8         reserved_at_40[0x40];
8094 };
8095
8096 struct mlx5_ifc_arm_dct_in_bits {
8097         u8         opcode[0x10];
8098         u8         reserved_at_10[0x10];
8099
8100         u8         reserved_at_20[0x10];
8101         u8         op_mod[0x10];
8102
8103         u8         reserved_at_40[0x8];
8104         u8         dct_number[0x18];
8105
8106         u8         reserved_at_60[0x20];
8107 };
8108
8109 struct mlx5_ifc_alloc_xrcd_out_bits {
8110         u8         status[0x8];
8111         u8         reserved_at_8[0x18];
8112
8113         u8         syndrome[0x20];
8114
8115         u8         reserved_at_40[0x8];
8116         u8         xrcd[0x18];
8117
8118         u8         reserved_at_60[0x20];
8119 };
8120
8121 struct mlx5_ifc_alloc_xrcd_in_bits {
8122         u8         opcode[0x10];
8123         u8         uid[0x10];
8124
8125         u8         reserved_at_20[0x10];
8126         u8         op_mod[0x10];
8127
8128         u8         reserved_at_40[0x40];
8129 };
8130
8131 struct mlx5_ifc_alloc_uar_out_bits {
8132         u8         status[0x8];
8133         u8         reserved_at_8[0x18];
8134
8135         u8         syndrome[0x20];
8136
8137         u8         reserved_at_40[0x8];
8138         u8         uar[0x18];
8139
8140         u8         reserved_at_60[0x20];
8141 };
8142
8143 struct mlx5_ifc_alloc_uar_in_bits {
8144         u8         opcode[0x10];
8145         u8         reserved_at_10[0x10];
8146
8147         u8         reserved_at_20[0x10];
8148         u8         op_mod[0x10];
8149
8150         u8         reserved_at_40[0x40];
8151 };
8152
8153 struct mlx5_ifc_alloc_transport_domain_out_bits {
8154         u8         status[0x8];
8155         u8         reserved_at_8[0x18];
8156
8157         u8         syndrome[0x20];
8158
8159         u8         reserved_at_40[0x8];
8160         u8         transport_domain[0x18];
8161
8162         u8         reserved_at_60[0x20];
8163 };
8164
8165 struct mlx5_ifc_alloc_transport_domain_in_bits {
8166         u8         opcode[0x10];
8167         u8         uid[0x10];
8168
8169         u8         reserved_at_20[0x10];
8170         u8         op_mod[0x10];
8171
8172         u8         reserved_at_40[0x40];
8173 };
8174
8175 struct mlx5_ifc_alloc_q_counter_out_bits {
8176         u8         status[0x8];
8177         u8         reserved_at_8[0x18];
8178
8179         u8         syndrome[0x20];
8180
8181         u8         reserved_at_40[0x18];
8182         u8         counter_set_id[0x8];
8183
8184         u8         reserved_at_60[0x20];
8185 };
8186
8187 struct mlx5_ifc_alloc_q_counter_in_bits {
8188         u8         opcode[0x10];
8189         u8         uid[0x10];
8190
8191         u8         reserved_at_20[0x10];
8192         u8         op_mod[0x10];
8193
8194         u8         reserved_at_40[0x40];
8195 };
8196
8197 struct mlx5_ifc_alloc_pd_out_bits {
8198         u8         status[0x8];
8199         u8         reserved_at_8[0x18];
8200
8201         u8         syndrome[0x20];
8202
8203         u8         reserved_at_40[0x8];
8204         u8         pd[0x18];
8205
8206         u8         reserved_at_60[0x20];
8207 };
8208
8209 struct mlx5_ifc_alloc_pd_in_bits {
8210         u8         opcode[0x10];
8211         u8         uid[0x10];
8212
8213         u8         reserved_at_20[0x10];
8214         u8         op_mod[0x10];
8215
8216         u8         reserved_at_40[0x40];
8217 };
8218
8219 struct mlx5_ifc_alloc_flow_counter_out_bits {
8220         u8         status[0x8];
8221         u8         reserved_at_8[0x18];
8222
8223         u8         syndrome[0x20];
8224
8225         u8         flow_counter_id[0x20];
8226
8227         u8         reserved_at_60[0x20];
8228 };
8229
8230 struct mlx5_ifc_alloc_flow_counter_in_bits {
8231         u8         opcode[0x10];
8232         u8         reserved_at_10[0x10];
8233
8234         u8         reserved_at_20[0x10];
8235         u8         op_mod[0x10];
8236
8237         u8         reserved_at_40[0x38];
8238         u8         flow_counter_bulk[0x8];
8239 };
8240
8241 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8242         u8         status[0x8];
8243         u8         reserved_at_8[0x18];
8244
8245         u8         syndrome[0x20];
8246
8247         u8         reserved_at_40[0x40];
8248 };
8249
8250 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8251         u8         opcode[0x10];
8252         u8         reserved_at_10[0x10];
8253
8254         u8         reserved_at_20[0x10];
8255         u8         op_mod[0x10];
8256
8257         u8         reserved_at_40[0x20];
8258
8259         u8         reserved_at_60[0x10];
8260         u8         vxlan_udp_port[0x10];
8261 };
8262
8263 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8264         u8         status[0x8];
8265         u8         reserved_at_8[0x18];
8266
8267         u8         syndrome[0x20];
8268
8269         u8         reserved_at_40[0x40];
8270 };
8271
8272 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8273         u8         rate_limit[0x20];
8274
8275         u8         burst_upper_bound[0x20];
8276
8277         u8         reserved_at_40[0x10];
8278         u8         typical_packet_size[0x10];
8279
8280         u8         reserved_at_60[0x120];
8281 };
8282
8283 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8284         u8         opcode[0x10];
8285         u8         uid[0x10];
8286
8287         u8         reserved_at_20[0x10];
8288         u8         op_mod[0x10];
8289
8290         u8         reserved_at_40[0x10];
8291         u8         rate_limit_index[0x10];
8292
8293         u8         reserved_at_60[0x20];
8294
8295         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8296 };
8297
8298 struct mlx5_ifc_access_register_out_bits {
8299         u8         status[0x8];
8300         u8         reserved_at_8[0x18];
8301
8302         u8         syndrome[0x20];
8303
8304         u8         reserved_at_40[0x40];
8305
8306         u8         register_data[0][0x20];
8307 };
8308
8309 enum {
8310         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8311         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8312 };
8313
8314 struct mlx5_ifc_access_register_in_bits {
8315         u8         opcode[0x10];
8316         u8         reserved_at_10[0x10];
8317
8318         u8         reserved_at_20[0x10];
8319         u8         op_mod[0x10];
8320
8321         u8         reserved_at_40[0x10];
8322         u8         register_id[0x10];
8323
8324         u8         argument[0x20];
8325
8326         u8         register_data[0][0x20];
8327 };
8328
8329 struct mlx5_ifc_sltp_reg_bits {
8330         u8         status[0x4];
8331         u8         version[0x4];
8332         u8         local_port[0x8];
8333         u8         pnat[0x2];
8334         u8         reserved_at_12[0x2];
8335         u8         lane[0x4];
8336         u8         reserved_at_18[0x8];
8337
8338         u8         reserved_at_20[0x20];
8339
8340         u8         reserved_at_40[0x7];
8341         u8         polarity[0x1];
8342         u8         ob_tap0[0x8];
8343         u8         ob_tap1[0x8];
8344         u8         ob_tap2[0x8];
8345
8346         u8         reserved_at_60[0xc];
8347         u8         ob_preemp_mode[0x4];
8348         u8         ob_reg[0x8];
8349         u8         ob_bias[0x8];
8350
8351         u8         reserved_at_80[0x20];
8352 };
8353
8354 struct mlx5_ifc_slrg_reg_bits {
8355         u8         status[0x4];
8356         u8         version[0x4];
8357         u8         local_port[0x8];
8358         u8         pnat[0x2];
8359         u8         reserved_at_12[0x2];
8360         u8         lane[0x4];
8361         u8         reserved_at_18[0x8];
8362
8363         u8         time_to_link_up[0x10];
8364         u8         reserved_at_30[0xc];
8365         u8         grade_lane_speed[0x4];
8366
8367         u8         grade_version[0x8];
8368         u8         grade[0x18];
8369
8370         u8         reserved_at_60[0x4];
8371         u8         height_grade_type[0x4];
8372         u8         height_grade[0x18];
8373
8374         u8         height_dz[0x10];
8375         u8         height_dv[0x10];
8376
8377         u8         reserved_at_a0[0x10];
8378         u8         height_sigma[0x10];
8379
8380         u8         reserved_at_c0[0x20];
8381
8382         u8         reserved_at_e0[0x4];
8383         u8         phase_grade_type[0x4];
8384         u8         phase_grade[0x18];
8385
8386         u8         reserved_at_100[0x8];
8387         u8         phase_eo_pos[0x8];
8388         u8         reserved_at_110[0x8];
8389         u8         phase_eo_neg[0x8];
8390
8391         u8         ffe_set_tested[0x10];
8392         u8         test_errors_per_lane[0x10];
8393 };
8394
8395 struct mlx5_ifc_pvlc_reg_bits {
8396         u8         reserved_at_0[0x8];
8397         u8         local_port[0x8];
8398         u8         reserved_at_10[0x10];
8399
8400         u8         reserved_at_20[0x1c];
8401         u8         vl_hw_cap[0x4];
8402
8403         u8         reserved_at_40[0x1c];
8404         u8         vl_admin[0x4];
8405
8406         u8         reserved_at_60[0x1c];
8407         u8         vl_operational[0x4];
8408 };
8409
8410 struct mlx5_ifc_pude_reg_bits {
8411         u8         swid[0x8];
8412         u8         local_port[0x8];
8413         u8         reserved_at_10[0x4];
8414         u8         admin_status[0x4];
8415         u8         reserved_at_18[0x4];
8416         u8         oper_status[0x4];
8417
8418         u8         reserved_at_20[0x60];
8419 };
8420
8421 struct mlx5_ifc_ptys_reg_bits {
8422         u8         reserved_at_0[0x1];
8423         u8         an_disable_admin[0x1];
8424         u8         an_disable_cap[0x1];
8425         u8         reserved_at_3[0x5];
8426         u8         local_port[0x8];
8427         u8         reserved_at_10[0xd];
8428         u8         proto_mask[0x3];
8429
8430         u8         an_status[0x4];
8431         u8         reserved_at_24[0xc];
8432         u8         data_rate_oper[0x10];
8433
8434         u8         ext_eth_proto_capability[0x20];
8435
8436         u8         eth_proto_capability[0x20];
8437
8438         u8         ib_link_width_capability[0x10];
8439         u8         ib_proto_capability[0x10];
8440
8441         u8         ext_eth_proto_admin[0x20];
8442
8443         u8         eth_proto_admin[0x20];
8444
8445         u8         ib_link_width_admin[0x10];
8446         u8         ib_proto_admin[0x10];
8447
8448         u8         ext_eth_proto_oper[0x20];
8449
8450         u8         eth_proto_oper[0x20];
8451
8452         u8         ib_link_width_oper[0x10];
8453         u8         ib_proto_oper[0x10];
8454
8455         u8         reserved_at_160[0x1c];
8456         u8         connector_type[0x4];
8457
8458         u8         eth_proto_lp_advertise[0x20];
8459
8460         u8         reserved_at_1a0[0x60];
8461 };
8462
8463 struct mlx5_ifc_mlcr_reg_bits {
8464         u8         reserved_at_0[0x8];
8465         u8         local_port[0x8];
8466         u8         reserved_at_10[0x20];
8467
8468         u8         beacon_duration[0x10];
8469         u8         reserved_at_40[0x10];
8470
8471         u8         beacon_remain[0x10];
8472 };
8473
8474 struct mlx5_ifc_ptas_reg_bits {
8475         u8         reserved_at_0[0x20];
8476
8477         u8         algorithm_options[0x10];
8478         u8         reserved_at_30[0x4];
8479         u8         repetitions_mode[0x4];
8480         u8         num_of_repetitions[0x8];
8481
8482         u8         grade_version[0x8];
8483         u8         height_grade_type[0x4];
8484         u8         phase_grade_type[0x4];
8485         u8         height_grade_weight[0x8];
8486         u8         phase_grade_weight[0x8];
8487
8488         u8         gisim_measure_bits[0x10];
8489         u8         adaptive_tap_measure_bits[0x10];
8490
8491         u8         ber_bath_high_error_threshold[0x10];
8492         u8         ber_bath_mid_error_threshold[0x10];
8493
8494         u8         ber_bath_low_error_threshold[0x10];
8495         u8         one_ratio_high_threshold[0x10];
8496
8497         u8         one_ratio_high_mid_threshold[0x10];
8498         u8         one_ratio_low_mid_threshold[0x10];
8499
8500         u8         one_ratio_low_threshold[0x10];
8501         u8         ndeo_error_threshold[0x10];
8502
8503         u8         mixer_offset_step_size[0x10];
8504         u8         reserved_at_110[0x8];
8505         u8         mix90_phase_for_voltage_bath[0x8];
8506
8507         u8         mixer_offset_start[0x10];
8508         u8         mixer_offset_end[0x10];
8509
8510         u8         reserved_at_140[0x15];
8511         u8         ber_test_time[0xb];
8512 };
8513
8514 struct mlx5_ifc_pspa_reg_bits {
8515         u8         swid[0x8];
8516         u8         local_port[0x8];
8517         u8         sub_port[0x8];
8518         u8         reserved_at_18[0x8];
8519
8520         u8         reserved_at_20[0x20];
8521 };
8522
8523 struct mlx5_ifc_pqdr_reg_bits {
8524         u8         reserved_at_0[0x8];
8525         u8         local_port[0x8];
8526         u8         reserved_at_10[0x5];
8527         u8         prio[0x3];
8528         u8         reserved_at_18[0x6];
8529         u8         mode[0x2];
8530
8531         u8         reserved_at_20[0x20];
8532
8533         u8         reserved_at_40[0x10];
8534         u8         min_threshold[0x10];
8535
8536         u8         reserved_at_60[0x10];
8537         u8         max_threshold[0x10];
8538
8539         u8         reserved_at_80[0x10];
8540         u8         mark_probability_denominator[0x10];
8541
8542         u8         reserved_at_a0[0x60];
8543 };
8544
8545 struct mlx5_ifc_ppsc_reg_bits {
8546         u8         reserved_at_0[0x8];
8547         u8         local_port[0x8];
8548         u8         reserved_at_10[0x10];
8549
8550         u8         reserved_at_20[0x60];
8551
8552         u8         reserved_at_80[0x1c];
8553         u8         wrps_admin[0x4];
8554
8555         u8         reserved_at_a0[0x1c];
8556         u8         wrps_status[0x4];
8557
8558         u8         reserved_at_c0[0x8];
8559         u8         up_threshold[0x8];
8560         u8         reserved_at_d0[0x8];
8561         u8         down_threshold[0x8];
8562
8563         u8         reserved_at_e0[0x20];
8564
8565         u8         reserved_at_100[0x1c];
8566         u8         srps_admin[0x4];
8567
8568         u8         reserved_at_120[0x1c];
8569         u8         srps_status[0x4];
8570
8571         u8         reserved_at_140[0x40];
8572 };
8573
8574 struct mlx5_ifc_pplr_reg_bits {
8575         u8         reserved_at_0[0x8];
8576         u8         local_port[0x8];
8577         u8         reserved_at_10[0x10];
8578
8579         u8         reserved_at_20[0x8];
8580         u8         lb_cap[0x8];
8581         u8         reserved_at_30[0x8];
8582         u8         lb_en[0x8];
8583 };
8584
8585 struct mlx5_ifc_pplm_reg_bits {
8586         u8         reserved_at_0[0x8];
8587         u8         local_port[0x8];
8588         u8         reserved_at_10[0x10];
8589
8590         u8         reserved_at_20[0x20];
8591
8592         u8         port_profile_mode[0x8];
8593         u8         static_port_profile[0x8];
8594         u8         active_port_profile[0x8];
8595         u8         reserved_at_58[0x8];
8596
8597         u8         retransmission_active[0x8];
8598         u8         fec_mode_active[0x18];
8599
8600         u8         rs_fec_correction_bypass_cap[0x4];
8601         u8         reserved_at_84[0x8];
8602         u8         fec_override_cap_56g[0x4];
8603         u8         fec_override_cap_100g[0x4];
8604         u8         fec_override_cap_50g[0x4];
8605         u8         fec_override_cap_25g[0x4];
8606         u8         fec_override_cap_10g_40g[0x4];
8607
8608         u8         rs_fec_correction_bypass_admin[0x4];
8609         u8         reserved_at_a4[0x8];
8610         u8         fec_override_admin_56g[0x4];
8611         u8         fec_override_admin_100g[0x4];
8612         u8         fec_override_admin_50g[0x4];
8613         u8         fec_override_admin_25g[0x4];
8614         u8         fec_override_admin_10g_40g[0x4];
8615
8616         u8         fec_override_cap_400g_8x[0x10];
8617         u8         fec_override_cap_200g_4x[0x10];
8618
8619         u8         fec_override_cap_100g_2x[0x10];
8620         u8         fec_override_cap_50g_1x[0x10];
8621
8622         u8         fec_override_admin_400g_8x[0x10];
8623         u8         fec_override_admin_200g_4x[0x10];
8624
8625         u8         fec_override_admin_100g_2x[0x10];
8626         u8         fec_override_admin_50g_1x[0x10];
8627 };
8628
8629 struct mlx5_ifc_ppcnt_reg_bits {
8630         u8         swid[0x8];
8631         u8         local_port[0x8];
8632         u8         pnat[0x2];
8633         u8         reserved_at_12[0x8];
8634         u8         grp[0x6];
8635
8636         u8         clr[0x1];
8637         u8         reserved_at_21[0x1c];
8638         u8         prio_tc[0x3];
8639
8640         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8641 };
8642
8643 struct mlx5_ifc_mpein_reg_bits {
8644         u8         reserved_at_0[0x2];
8645         u8         depth[0x6];
8646         u8         pcie_index[0x8];
8647         u8         node[0x8];
8648         u8         reserved_at_18[0x8];
8649
8650         u8         capability_mask[0x20];
8651
8652         u8         reserved_at_40[0x8];
8653         u8         link_width_enabled[0x8];
8654         u8         link_speed_enabled[0x10];
8655
8656         u8         lane0_physical_position[0x8];
8657         u8         link_width_active[0x8];
8658         u8         link_speed_active[0x10];
8659
8660         u8         num_of_pfs[0x10];
8661         u8         num_of_vfs[0x10];
8662
8663         u8         bdf0[0x10];
8664         u8         reserved_at_b0[0x10];
8665
8666         u8         max_read_request_size[0x4];
8667         u8         max_payload_size[0x4];
8668         u8         reserved_at_c8[0x5];
8669         u8         pwr_status[0x3];
8670         u8         port_type[0x4];
8671         u8         reserved_at_d4[0xb];
8672         u8         lane_reversal[0x1];
8673
8674         u8         reserved_at_e0[0x14];
8675         u8         pci_power[0xc];
8676
8677         u8         reserved_at_100[0x20];
8678
8679         u8         device_status[0x10];
8680         u8         port_state[0x8];
8681         u8         reserved_at_138[0x8];
8682
8683         u8         reserved_at_140[0x10];
8684         u8         receiver_detect_result[0x10];
8685
8686         u8         reserved_at_160[0x20];
8687 };
8688
8689 struct mlx5_ifc_mpcnt_reg_bits {
8690         u8         reserved_at_0[0x8];
8691         u8         pcie_index[0x8];
8692         u8         reserved_at_10[0xa];
8693         u8         grp[0x6];
8694
8695         u8         clr[0x1];
8696         u8         reserved_at_21[0x1f];
8697
8698         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8699 };
8700
8701 struct mlx5_ifc_ppad_reg_bits {
8702         u8         reserved_at_0[0x3];
8703         u8         single_mac[0x1];
8704         u8         reserved_at_4[0x4];
8705         u8         local_port[0x8];
8706         u8         mac_47_32[0x10];
8707
8708         u8         mac_31_0[0x20];
8709
8710         u8         reserved_at_40[0x40];
8711 };
8712
8713 struct mlx5_ifc_pmtu_reg_bits {
8714         u8         reserved_at_0[0x8];
8715         u8         local_port[0x8];
8716         u8         reserved_at_10[0x10];
8717
8718         u8         max_mtu[0x10];
8719         u8         reserved_at_30[0x10];
8720
8721         u8         admin_mtu[0x10];
8722         u8         reserved_at_50[0x10];
8723
8724         u8         oper_mtu[0x10];
8725         u8         reserved_at_70[0x10];
8726 };
8727
8728 struct mlx5_ifc_pmpr_reg_bits {
8729         u8         reserved_at_0[0x8];
8730         u8         module[0x8];
8731         u8         reserved_at_10[0x10];
8732
8733         u8         reserved_at_20[0x18];
8734         u8         attenuation_5g[0x8];
8735
8736         u8         reserved_at_40[0x18];
8737         u8         attenuation_7g[0x8];
8738
8739         u8         reserved_at_60[0x18];
8740         u8         attenuation_12g[0x8];
8741 };
8742
8743 struct mlx5_ifc_pmpe_reg_bits {
8744         u8         reserved_at_0[0x8];
8745         u8         module[0x8];
8746         u8         reserved_at_10[0xc];
8747         u8         module_status[0x4];
8748
8749         u8         reserved_at_20[0x60];
8750 };
8751
8752 struct mlx5_ifc_pmpc_reg_bits {
8753         u8         module_state_updated[32][0x8];
8754 };
8755
8756 struct mlx5_ifc_pmlpn_reg_bits {
8757         u8         reserved_at_0[0x4];
8758         u8         mlpn_status[0x4];
8759         u8         local_port[0x8];
8760         u8         reserved_at_10[0x10];
8761
8762         u8         e[0x1];
8763         u8         reserved_at_21[0x1f];
8764 };
8765
8766 struct mlx5_ifc_pmlp_reg_bits {
8767         u8         rxtx[0x1];
8768         u8         reserved_at_1[0x7];
8769         u8         local_port[0x8];
8770         u8         reserved_at_10[0x8];
8771         u8         width[0x8];
8772
8773         u8         lane0_module_mapping[0x20];
8774
8775         u8         lane1_module_mapping[0x20];
8776
8777         u8         lane2_module_mapping[0x20];
8778
8779         u8         lane3_module_mapping[0x20];
8780
8781         u8         reserved_at_a0[0x160];
8782 };
8783
8784 struct mlx5_ifc_pmaos_reg_bits {
8785         u8         reserved_at_0[0x8];
8786         u8         module[0x8];
8787         u8         reserved_at_10[0x4];
8788         u8         admin_status[0x4];
8789         u8         reserved_at_18[0x4];
8790         u8         oper_status[0x4];
8791
8792         u8         ase[0x1];
8793         u8         ee[0x1];
8794         u8         reserved_at_22[0x1c];
8795         u8         e[0x2];
8796
8797         u8         reserved_at_40[0x40];
8798 };
8799
8800 struct mlx5_ifc_plpc_reg_bits {
8801         u8         reserved_at_0[0x4];
8802         u8         profile_id[0xc];
8803         u8         reserved_at_10[0x4];
8804         u8         proto_mask[0x4];
8805         u8         reserved_at_18[0x8];
8806
8807         u8         reserved_at_20[0x10];
8808         u8         lane_speed[0x10];
8809
8810         u8         reserved_at_40[0x17];
8811         u8         lpbf[0x1];
8812         u8         fec_mode_policy[0x8];
8813
8814         u8         retransmission_capability[0x8];
8815         u8         fec_mode_capability[0x18];
8816
8817         u8         retransmission_support_admin[0x8];
8818         u8         fec_mode_support_admin[0x18];
8819
8820         u8         retransmission_request_admin[0x8];
8821         u8         fec_mode_request_admin[0x18];
8822
8823         u8         reserved_at_c0[0x80];
8824 };
8825
8826 struct mlx5_ifc_plib_reg_bits {
8827         u8         reserved_at_0[0x8];
8828         u8         local_port[0x8];
8829         u8         reserved_at_10[0x8];
8830         u8         ib_port[0x8];
8831
8832         u8         reserved_at_20[0x60];
8833 };
8834
8835 struct mlx5_ifc_plbf_reg_bits {
8836         u8         reserved_at_0[0x8];
8837         u8         local_port[0x8];
8838         u8         reserved_at_10[0xd];
8839         u8         lbf_mode[0x3];
8840
8841         u8         reserved_at_20[0x20];
8842 };
8843
8844 struct mlx5_ifc_pipg_reg_bits {
8845         u8         reserved_at_0[0x8];
8846         u8         local_port[0x8];
8847         u8         reserved_at_10[0x10];
8848
8849         u8         dic[0x1];
8850         u8         reserved_at_21[0x19];
8851         u8         ipg[0x4];
8852         u8         reserved_at_3e[0x2];
8853 };
8854
8855 struct mlx5_ifc_pifr_reg_bits {
8856         u8         reserved_at_0[0x8];
8857         u8         local_port[0x8];
8858         u8         reserved_at_10[0x10];
8859
8860         u8         reserved_at_20[0xe0];
8861
8862         u8         port_filter[8][0x20];
8863
8864         u8         port_filter_update_en[8][0x20];
8865 };
8866
8867 struct mlx5_ifc_pfcc_reg_bits {
8868         u8         reserved_at_0[0x8];
8869         u8         local_port[0x8];
8870         u8         reserved_at_10[0xb];
8871         u8         ppan_mask_n[0x1];
8872         u8         minor_stall_mask[0x1];
8873         u8         critical_stall_mask[0x1];
8874         u8         reserved_at_1e[0x2];
8875
8876         u8         ppan[0x4];
8877         u8         reserved_at_24[0x4];
8878         u8         prio_mask_tx[0x8];
8879         u8         reserved_at_30[0x8];
8880         u8         prio_mask_rx[0x8];
8881
8882         u8         pptx[0x1];
8883         u8         aptx[0x1];
8884         u8         pptx_mask_n[0x1];
8885         u8         reserved_at_43[0x5];
8886         u8         pfctx[0x8];
8887         u8         reserved_at_50[0x10];
8888
8889         u8         pprx[0x1];
8890         u8         aprx[0x1];
8891         u8         pprx_mask_n[0x1];
8892         u8         reserved_at_63[0x5];
8893         u8         pfcrx[0x8];
8894         u8         reserved_at_70[0x10];
8895
8896         u8         device_stall_minor_watermark[0x10];
8897         u8         device_stall_critical_watermark[0x10];
8898
8899         u8         reserved_at_a0[0x60];
8900 };
8901
8902 struct mlx5_ifc_pelc_reg_bits {
8903         u8         op[0x4];
8904         u8         reserved_at_4[0x4];
8905         u8         local_port[0x8];
8906         u8         reserved_at_10[0x10];
8907
8908         u8         op_admin[0x8];
8909         u8         op_capability[0x8];
8910         u8         op_request[0x8];
8911         u8         op_active[0x8];
8912
8913         u8         admin[0x40];
8914
8915         u8         capability[0x40];
8916
8917         u8         request[0x40];
8918
8919         u8         active[0x40];
8920
8921         u8         reserved_at_140[0x80];
8922 };
8923
8924 struct mlx5_ifc_peir_reg_bits {
8925         u8         reserved_at_0[0x8];
8926         u8         local_port[0x8];
8927         u8         reserved_at_10[0x10];
8928
8929         u8         reserved_at_20[0xc];
8930         u8         error_count[0x4];
8931         u8         reserved_at_30[0x10];
8932
8933         u8         reserved_at_40[0xc];
8934         u8         lane[0x4];
8935         u8         reserved_at_50[0x8];
8936         u8         error_type[0x8];
8937 };
8938
8939 struct mlx5_ifc_mpegc_reg_bits {
8940         u8         reserved_at_0[0x30];
8941         u8         field_select[0x10];
8942
8943         u8         tx_overflow_sense[0x1];
8944         u8         mark_cqe[0x1];
8945         u8         mark_cnp[0x1];
8946         u8         reserved_at_43[0x1b];
8947         u8         tx_lossy_overflow_oper[0x2];
8948
8949         u8         reserved_at_60[0x100];
8950 };
8951
8952 struct mlx5_ifc_pcam_enhanced_features_bits {
8953         u8         reserved_at_0[0x68];
8954         u8         fec_50G_per_lane_in_pplm[0x1];
8955         u8         reserved_at_69[0x4];
8956         u8         rx_icrc_encapsulated_counter[0x1];
8957         u8         reserved_at_6e[0x4];
8958         u8         ptys_extended_ethernet[0x1];
8959         u8         reserved_at_73[0x3];
8960         u8         pfcc_mask[0x1];
8961         u8         reserved_at_77[0x3];
8962         u8         per_lane_error_counters[0x1];
8963         u8         rx_buffer_fullness_counters[0x1];
8964         u8         ptys_connector_type[0x1];
8965         u8         reserved_at_7d[0x1];
8966         u8         ppcnt_discard_group[0x1];
8967         u8         ppcnt_statistical_group[0x1];
8968 };
8969
8970 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8971         u8         port_access_reg_cap_mask_127_to_96[0x20];
8972         u8         port_access_reg_cap_mask_95_to_64[0x20];
8973
8974         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8975         u8         pplm[0x1];
8976         u8         port_access_reg_cap_mask_34_to_32[0x3];
8977
8978         u8         port_access_reg_cap_mask_31_to_13[0x13];
8979         u8         pbmc[0x1];
8980         u8         pptb[0x1];
8981         u8         port_access_reg_cap_mask_10_to_09[0x2];
8982         u8         ppcnt[0x1];
8983         u8         port_access_reg_cap_mask_07_to_00[0x8];
8984 };
8985
8986 struct mlx5_ifc_pcam_reg_bits {
8987         u8         reserved_at_0[0x8];
8988         u8         feature_group[0x8];
8989         u8         reserved_at_10[0x8];
8990         u8         access_reg_group[0x8];
8991
8992         u8         reserved_at_20[0x20];
8993
8994         union {
8995                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8996                 u8         reserved_at_0[0x80];
8997         } port_access_reg_cap_mask;
8998
8999         u8         reserved_at_c0[0x80];
9000
9001         union {
9002                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9003                 u8         reserved_at_0[0x80];
9004         } feature_cap_mask;
9005
9006         u8         reserved_at_1c0[0xc0];
9007 };
9008
9009 struct mlx5_ifc_mcam_enhanced_features_bits {
9010         u8         reserved_at_0[0x6e];
9011         u8         pci_status_and_power[0x1];
9012         u8         reserved_at_6f[0x5];
9013         u8         mark_tx_action_cnp[0x1];
9014         u8         mark_tx_action_cqe[0x1];
9015         u8         dynamic_tx_overflow[0x1];
9016         u8         reserved_at_77[0x4];
9017         u8         pcie_outbound_stalled[0x1];
9018         u8         tx_overflow_buffer_pkt[0x1];
9019         u8         mtpps_enh_out_per_adj[0x1];
9020         u8         mtpps_fs[0x1];
9021         u8         pcie_performance_group[0x1];
9022 };
9023
9024 struct mlx5_ifc_mcam_access_reg_bits {
9025         u8         reserved_at_0[0x1c];
9026         u8         mcda[0x1];
9027         u8         mcc[0x1];
9028         u8         mcqi[0x1];
9029         u8         mcqs[0x1];
9030
9031         u8         regs_95_to_87[0x9];
9032         u8         mpegc[0x1];
9033         u8         regs_85_to_68[0x12];
9034         u8         tracer_registers[0x4];
9035
9036         u8         regs_63_to_32[0x20];
9037         u8         regs_31_to_0[0x20];
9038 };
9039
9040 struct mlx5_ifc_mcam_access_reg_bits1 {
9041         u8         regs_127_to_96[0x20];
9042
9043         u8         regs_95_to_64[0x20];
9044
9045         u8         regs_63_to_32[0x20];
9046
9047         u8         regs_31_to_0[0x20];
9048 };
9049
9050 struct mlx5_ifc_mcam_access_reg_bits2 {
9051         u8         regs_127_to_99[0x1d];
9052         u8         mirc[0x1];
9053         u8         regs_97_to_96[0x2];
9054
9055         u8         regs_95_to_64[0x20];
9056
9057         u8         regs_63_to_32[0x20];
9058
9059         u8         regs_31_to_0[0x20];
9060 };
9061
9062 struct mlx5_ifc_mcam_reg_bits {
9063         u8         reserved_at_0[0x8];
9064         u8         feature_group[0x8];
9065         u8         reserved_at_10[0x8];
9066         u8         access_reg_group[0x8];
9067
9068         u8         reserved_at_20[0x20];
9069
9070         union {
9071                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9072                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9073                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9074                 u8         reserved_at_0[0x80];
9075         } mng_access_reg_cap_mask;
9076
9077         u8         reserved_at_c0[0x80];
9078
9079         union {
9080                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9081                 u8         reserved_at_0[0x80];
9082         } mng_feature_cap_mask;
9083
9084         u8         reserved_at_1c0[0x80];
9085 };
9086
9087 struct mlx5_ifc_qcam_access_reg_cap_mask {
9088         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9089         u8         qpdpm[0x1];
9090         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9091         u8         qdpm[0x1];
9092         u8         qpts[0x1];
9093         u8         qcap[0x1];
9094         u8         qcam_access_reg_cap_mask_0[0x1];
9095 };
9096
9097 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9098         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9099         u8         qpts_trust_both[0x1];
9100 };
9101
9102 struct mlx5_ifc_qcam_reg_bits {
9103         u8         reserved_at_0[0x8];
9104         u8         feature_group[0x8];
9105         u8         reserved_at_10[0x8];
9106         u8         access_reg_group[0x8];
9107         u8         reserved_at_20[0x20];
9108
9109         union {
9110                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9111                 u8  reserved_at_0[0x80];
9112         } qos_access_reg_cap_mask;
9113
9114         u8         reserved_at_c0[0x80];
9115
9116         union {
9117                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9118                 u8  reserved_at_0[0x80];
9119         } qos_feature_cap_mask;
9120
9121         u8         reserved_at_1c0[0x80];
9122 };
9123
9124 struct mlx5_ifc_core_dump_reg_bits {
9125         u8         reserved_at_0[0x18];
9126         u8         core_dump_type[0x8];
9127
9128         u8         reserved_at_20[0x30];
9129         u8         vhca_id[0x10];
9130
9131         u8         reserved_at_60[0x8];
9132         u8         qpn[0x18];
9133         u8         reserved_at_80[0x180];
9134 };
9135
9136 struct mlx5_ifc_pcap_reg_bits {
9137         u8         reserved_at_0[0x8];
9138         u8         local_port[0x8];
9139         u8         reserved_at_10[0x10];
9140
9141         u8         port_capability_mask[4][0x20];
9142 };
9143
9144 struct mlx5_ifc_paos_reg_bits {
9145         u8         swid[0x8];
9146         u8         local_port[0x8];
9147         u8         reserved_at_10[0x4];
9148         u8         admin_status[0x4];
9149         u8         reserved_at_18[0x4];
9150         u8         oper_status[0x4];
9151
9152         u8         ase[0x1];
9153         u8         ee[0x1];
9154         u8         reserved_at_22[0x1c];
9155         u8         e[0x2];
9156
9157         u8         reserved_at_40[0x40];
9158 };
9159
9160 struct mlx5_ifc_pamp_reg_bits {
9161         u8         reserved_at_0[0x8];
9162         u8         opamp_group[0x8];
9163         u8         reserved_at_10[0xc];
9164         u8         opamp_group_type[0x4];
9165
9166         u8         start_index[0x10];
9167         u8         reserved_at_30[0x4];
9168         u8         num_of_indices[0xc];
9169
9170         u8         index_data[18][0x10];
9171 };
9172
9173 struct mlx5_ifc_pcmr_reg_bits {
9174         u8         reserved_at_0[0x8];
9175         u8         local_port[0x8];
9176         u8         reserved_at_10[0x10];
9177         u8         entropy_force_cap[0x1];
9178         u8         entropy_calc_cap[0x1];
9179         u8         entropy_gre_calc_cap[0x1];
9180         u8         reserved_at_23[0x1b];
9181         u8         fcs_cap[0x1];
9182         u8         reserved_at_3f[0x1];
9183         u8         entropy_force[0x1];
9184         u8         entropy_calc[0x1];
9185         u8         entropy_gre_calc[0x1];
9186         u8         reserved_at_43[0x1b];
9187         u8         fcs_chk[0x1];
9188         u8         reserved_at_5f[0x1];
9189 };
9190
9191 struct mlx5_ifc_lane_2_module_mapping_bits {
9192         u8         reserved_at_0[0x6];
9193         u8         rx_lane[0x2];
9194         u8         reserved_at_8[0x6];
9195         u8         tx_lane[0x2];
9196         u8         reserved_at_10[0x8];
9197         u8         module[0x8];
9198 };
9199
9200 struct mlx5_ifc_bufferx_reg_bits {
9201         u8         reserved_at_0[0x6];
9202         u8         lossy[0x1];
9203         u8         epsb[0x1];
9204         u8         reserved_at_8[0xc];
9205         u8         size[0xc];
9206
9207         u8         xoff_threshold[0x10];
9208         u8         xon_threshold[0x10];
9209 };
9210
9211 struct mlx5_ifc_set_node_in_bits {
9212         u8         node_description[64][0x8];
9213 };
9214
9215 struct mlx5_ifc_register_power_settings_bits {
9216         u8         reserved_at_0[0x18];
9217         u8         power_settings_level[0x8];
9218
9219         u8         reserved_at_20[0x60];
9220 };
9221
9222 struct mlx5_ifc_register_host_endianness_bits {
9223         u8         he[0x1];
9224         u8         reserved_at_1[0x1f];
9225
9226         u8         reserved_at_20[0x60];
9227 };
9228
9229 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9230         u8         reserved_at_0[0x20];
9231
9232         u8         mkey[0x20];
9233
9234         u8         addressh_63_32[0x20];
9235
9236         u8         addressl_31_0[0x20];
9237 };
9238
9239 struct mlx5_ifc_ud_adrs_vector_bits {
9240         u8         dc_key[0x40];
9241
9242         u8         ext[0x1];
9243         u8         reserved_at_41[0x7];
9244         u8         destination_qp_dct[0x18];
9245
9246         u8         static_rate[0x4];
9247         u8         sl_eth_prio[0x4];
9248         u8         fl[0x1];
9249         u8         mlid[0x7];
9250         u8         rlid_udp_sport[0x10];
9251
9252         u8         reserved_at_80[0x20];
9253
9254         u8         rmac_47_16[0x20];
9255
9256         u8         rmac_15_0[0x10];
9257         u8         tclass[0x8];
9258         u8         hop_limit[0x8];
9259
9260         u8         reserved_at_e0[0x1];
9261         u8         grh[0x1];
9262         u8         reserved_at_e2[0x2];
9263         u8         src_addr_index[0x8];
9264         u8         flow_label[0x14];
9265
9266         u8         rgid_rip[16][0x8];
9267 };
9268
9269 struct mlx5_ifc_pages_req_event_bits {
9270         u8         reserved_at_0[0x10];
9271         u8         function_id[0x10];
9272
9273         u8         num_pages[0x20];
9274
9275         u8         reserved_at_40[0xa0];
9276 };
9277
9278 struct mlx5_ifc_eqe_bits {
9279         u8         reserved_at_0[0x8];
9280         u8         event_type[0x8];
9281         u8         reserved_at_10[0x8];
9282         u8         event_sub_type[0x8];
9283
9284         u8         reserved_at_20[0xe0];
9285
9286         union mlx5_ifc_event_auto_bits event_data;
9287
9288         u8         reserved_at_1e0[0x10];
9289         u8         signature[0x8];
9290         u8         reserved_at_1f8[0x7];
9291         u8         owner[0x1];
9292 };
9293
9294 enum {
9295         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9296 };
9297
9298 struct mlx5_ifc_cmd_queue_entry_bits {
9299         u8         type[0x8];
9300         u8         reserved_at_8[0x18];
9301
9302         u8         input_length[0x20];
9303
9304         u8         input_mailbox_pointer_63_32[0x20];
9305
9306         u8         input_mailbox_pointer_31_9[0x17];
9307         u8         reserved_at_77[0x9];
9308
9309         u8         command_input_inline_data[16][0x8];
9310
9311         u8         command_output_inline_data[16][0x8];
9312
9313         u8         output_mailbox_pointer_63_32[0x20];
9314
9315         u8         output_mailbox_pointer_31_9[0x17];
9316         u8         reserved_at_1b7[0x9];
9317
9318         u8         output_length[0x20];
9319
9320         u8         token[0x8];
9321         u8         signature[0x8];
9322         u8         reserved_at_1f0[0x8];
9323         u8         status[0x7];
9324         u8         ownership[0x1];
9325 };
9326
9327 struct mlx5_ifc_cmd_out_bits {
9328         u8         status[0x8];
9329         u8         reserved_at_8[0x18];
9330
9331         u8         syndrome[0x20];
9332
9333         u8         command_output[0x20];
9334 };
9335
9336 struct mlx5_ifc_cmd_in_bits {
9337         u8         opcode[0x10];
9338         u8         reserved_at_10[0x10];
9339
9340         u8         reserved_at_20[0x10];
9341         u8         op_mod[0x10];
9342
9343         u8         command[0][0x20];
9344 };
9345
9346 struct mlx5_ifc_cmd_if_box_bits {
9347         u8         mailbox_data[512][0x8];
9348
9349         u8         reserved_at_1000[0x180];
9350
9351         u8         next_pointer_63_32[0x20];
9352
9353         u8         next_pointer_31_10[0x16];
9354         u8         reserved_at_11b6[0xa];
9355
9356         u8         block_number[0x20];
9357
9358         u8         reserved_at_11e0[0x8];
9359         u8         token[0x8];
9360         u8         ctrl_signature[0x8];
9361         u8         signature[0x8];
9362 };
9363
9364 struct mlx5_ifc_mtt_bits {
9365         u8         ptag_63_32[0x20];
9366
9367         u8         ptag_31_8[0x18];
9368         u8         reserved_at_38[0x6];
9369         u8         wr_en[0x1];
9370         u8         rd_en[0x1];
9371 };
9372
9373 struct mlx5_ifc_query_wol_rol_out_bits {
9374         u8         status[0x8];
9375         u8         reserved_at_8[0x18];
9376
9377         u8         syndrome[0x20];
9378
9379         u8         reserved_at_40[0x10];
9380         u8         rol_mode[0x8];
9381         u8         wol_mode[0x8];
9382
9383         u8         reserved_at_60[0x20];
9384 };
9385
9386 struct mlx5_ifc_query_wol_rol_in_bits {
9387         u8         opcode[0x10];
9388         u8         reserved_at_10[0x10];
9389
9390         u8         reserved_at_20[0x10];
9391         u8         op_mod[0x10];
9392
9393         u8         reserved_at_40[0x40];
9394 };
9395
9396 struct mlx5_ifc_set_wol_rol_out_bits {
9397         u8         status[0x8];
9398         u8         reserved_at_8[0x18];
9399
9400         u8         syndrome[0x20];
9401
9402         u8         reserved_at_40[0x40];
9403 };
9404
9405 struct mlx5_ifc_set_wol_rol_in_bits {
9406         u8         opcode[0x10];
9407         u8         reserved_at_10[0x10];
9408
9409         u8         reserved_at_20[0x10];
9410         u8         op_mod[0x10];
9411
9412         u8         rol_mode_valid[0x1];
9413         u8         wol_mode_valid[0x1];
9414         u8         reserved_at_42[0xe];
9415         u8         rol_mode[0x8];
9416         u8         wol_mode[0x8];
9417
9418         u8         reserved_at_60[0x20];
9419 };
9420
9421 enum {
9422         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9423         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9424         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9425 };
9426
9427 enum {
9428         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9429         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9430         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9431 };
9432
9433 enum {
9434         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9435         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9436         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9437         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9438         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9439         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9440         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9441         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9442         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9443         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9444         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9445 };
9446
9447 struct mlx5_ifc_initial_seg_bits {
9448         u8         fw_rev_minor[0x10];
9449         u8         fw_rev_major[0x10];
9450
9451         u8         cmd_interface_rev[0x10];
9452         u8         fw_rev_subminor[0x10];
9453
9454         u8         reserved_at_40[0x40];
9455
9456         u8         cmdq_phy_addr_63_32[0x20];
9457
9458         u8         cmdq_phy_addr_31_12[0x14];
9459         u8         reserved_at_b4[0x2];
9460         u8         nic_interface[0x2];
9461         u8         log_cmdq_size[0x4];
9462         u8         log_cmdq_stride[0x4];
9463
9464         u8         command_doorbell_vector[0x20];
9465
9466         u8         reserved_at_e0[0xf00];
9467
9468         u8         initializing[0x1];
9469         u8         reserved_at_fe1[0x4];
9470         u8         nic_interface_supported[0x3];
9471         u8         embedded_cpu[0x1];
9472         u8         reserved_at_fe9[0x17];
9473
9474         struct mlx5_ifc_health_buffer_bits health_buffer;
9475
9476         u8         no_dram_nic_offset[0x20];
9477
9478         u8         reserved_at_1220[0x6e40];
9479
9480         u8         reserved_at_8060[0x1f];
9481         u8         clear_int[0x1];
9482
9483         u8         health_syndrome[0x8];
9484         u8         health_counter[0x18];
9485
9486         u8         reserved_at_80a0[0x17fc0];
9487 };
9488
9489 struct mlx5_ifc_mtpps_reg_bits {
9490         u8         reserved_at_0[0xc];
9491         u8         cap_number_of_pps_pins[0x4];
9492         u8         reserved_at_10[0x4];
9493         u8         cap_max_num_of_pps_in_pins[0x4];
9494         u8         reserved_at_18[0x4];
9495         u8         cap_max_num_of_pps_out_pins[0x4];
9496
9497         u8         reserved_at_20[0x24];
9498         u8         cap_pin_3_mode[0x4];
9499         u8         reserved_at_48[0x4];
9500         u8         cap_pin_2_mode[0x4];
9501         u8         reserved_at_50[0x4];
9502         u8         cap_pin_1_mode[0x4];
9503         u8         reserved_at_58[0x4];
9504         u8         cap_pin_0_mode[0x4];
9505
9506         u8         reserved_at_60[0x4];
9507         u8         cap_pin_7_mode[0x4];
9508         u8         reserved_at_68[0x4];
9509         u8         cap_pin_6_mode[0x4];
9510         u8         reserved_at_70[0x4];
9511         u8         cap_pin_5_mode[0x4];
9512         u8         reserved_at_78[0x4];
9513         u8         cap_pin_4_mode[0x4];
9514
9515         u8         field_select[0x20];
9516         u8         reserved_at_a0[0x60];
9517
9518         u8         enable[0x1];
9519         u8         reserved_at_101[0xb];
9520         u8         pattern[0x4];
9521         u8         reserved_at_110[0x4];
9522         u8         pin_mode[0x4];
9523         u8         pin[0x8];
9524
9525         u8         reserved_at_120[0x20];
9526
9527         u8         time_stamp[0x40];
9528
9529         u8         out_pulse_duration[0x10];
9530         u8         out_periodic_adjustment[0x10];
9531         u8         enhanced_out_periodic_adjustment[0x20];
9532
9533         u8         reserved_at_1c0[0x20];
9534 };
9535
9536 struct mlx5_ifc_mtppse_reg_bits {
9537         u8         reserved_at_0[0x18];
9538         u8         pin[0x8];
9539         u8         event_arm[0x1];
9540         u8         reserved_at_21[0x1b];
9541         u8         event_generation_mode[0x4];
9542         u8         reserved_at_40[0x40];
9543 };
9544
9545 struct mlx5_ifc_mcqs_reg_bits {
9546         u8         last_index_flag[0x1];
9547         u8         reserved_at_1[0x7];
9548         u8         fw_device[0x8];
9549         u8         component_index[0x10];
9550
9551         u8         reserved_at_20[0x10];
9552         u8         identifier[0x10];
9553
9554         u8         reserved_at_40[0x17];
9555         u8         component_status[0x5];
9556         u8         component_update_state[0x4];
9557
9558         u8         last_update_state_changer_type[0x4];
9559         u8         last_update_state_changer_host_id[0x4];
9560         u8         reserved_at_68[0x18];
9561 };
9562
9563 struct mlx5_ifc_mcqi_cap_bits {
9564         u8         supported_info_bitmask[0x20];
9565
9566         u8         component_size[0x20];
9567
9568         u8         max_component_size[0x20];
9569
9570         u8         log_mcda_word_size[0x4];
9571         u8         reserved_at_64[0xc];
9572         u8         mcda_max_write_size[0x10];
9573
9574         u8         rd_en[0x1];
9575         u8         reserved_at_81[0x1];
9576         u8         match_chip_id[0x1];
9577         u8         match_psid[0x1];
9578         u8         check_user_timestamp[0x1];
9579         u8         match_base_guid_mac[0x1];
9580         u8         reserved_at_86[0x1a];
9581 };
9582
9583 struct mlx5_ifc_mcqi_version_bits {
9584         u8         reserved_at_0[0x2];
9585         u8         build_time_valid[0x1];
9586         u8         user_defined_time_valid[0x1];
9587         u8         reserved_at_4[0x14];
9588         u8         version_string_length[0x8];
9589
9590         u8         version[0x20];
9591
9592         u8         build_time[0x40];
9593
9594         u8         user_defined_time[0x40];
9595
9596         u8         build_tool_version[0x20];
9597
9598         u8         reserved_at_e0[0x20];
9599
9600         u8         version_string[92][0x8];
9601 };
9602
9603 struct mlx5_ifc_mcqi_activation_method_bits {
9604         u8         pending_server_ac_power_cycle[0x1];
9605         u8         pending_server_dc_power_cycle[0x1];
9606         u8         pending_server_reboot[0x1];
9607         u8         pending_fw_reset[0x1];
9608         u8         auto_activate[0x1];
9609         u8         all_hosts_sync[0x1];
9610         u8         device_hw_reset[0x1];
9611         u8         reserved_at_7[0x19];
9612 };
9613
9614 union mlx5_ifc_mcqi_reg_data_bits {
9615         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9616         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9617         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9618 };
9619
9620 struct mlx5_ifc_mcqi_reg_bits {
9621         u8         read_pending_component[0x1];
9622         u8         reserved_at_1[0xf];
9623         u8         component_index[0x10];
9624
9625         u8         reserved_at_20[0x20];
9626
9627         u8         reserved_at_40[0x1b];
9628         u8         info_type[0x5];
9629
9630         u8         info_size[0x20];
9631
9632         u8         offset[0x20];
9633
9634         u8         reserved_at_a0[0x10];
9635         u8         data_size[0x10];
9636
9637         union mlx5_ifc_mcqi_reg_data_bits data[0];
9638 };
9639
9640 struct mlx5_ifc_mcc_reg_bits {
9641         u8         reserved_at_0[0x4];
9642         u8         time_elapsed_since_last_cmd[0xc];
9643         u8         reserved_at_10[0x8];
9644         u8         instruction[0x8];
9645
9646         u8         reserved_at_20[0x10];
9647         u8         component_index[0x10];
9648
9649         u8         reserved_at_40[0x8];
9650         u8         update_handle[0x18];
9651
9652         u8         handle_owner_type[0x4];
9653         u8         handle_owner_host_id[0x4];
9654         u8         reserved_at_68[0x1];
9655         u8         control_progress[0x7];
9656         u8         error_code[0x8];
9657         u8         reserved_at_78[0x4];
9658         u8         control_state[0x4];
9659
9660         u8         component_size[0x20];
9661
9662         u8         reserved_at_a0[0x60];
9663 };
9664
9665 struct mlx5_ifc_mcda_reg_bits {
9666         u8         reserved_at_0[0x8];
9667         u8         update_handle[0x18];
9668
9669         u8         offset[0x20];
9670
9671         u8         reserved_at_40[0x10];
9672         u8         size[0x10];
9673
9674         u8         reserved_at_60[0x20];
9675
9676         u8         data[0][0x20];
9677 };
9678
9679 struct mlx5_ifc_mirc_reg_bits {
9680         u8         reserved_at_0[0x18];
9681         u8         status_code[0x8];
9682
9683         u8         reserved_at_20[0x20];
9684 };
9685
9686 union mlx5_ifc_ports_control_registers_document_bits {
9687         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9688         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9689         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9690         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9691         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9692         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9693         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9694         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9695         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9696         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9697         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9698         struct mlx5_ifc_paos_reg_bits paos_reg;
9699         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9700         struct mlx5_ifc_peir_reg_bits peir_reg;
9701         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9702         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9703         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9704         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9705         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9706         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9707         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9708         struct mlx5_ifc_plib_reg_bits plib_reg;
9709         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9710         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9711         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9712         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9713         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9714         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9715         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9716         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9717         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9718         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9719         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9720         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9721         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9722         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9723         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9724         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9725         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9726         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9727         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9728         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9729         struct mlx5_ifc_pude_reg_bits pude_reg;
9730         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9731         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9732         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9733         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9734         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9735         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9736         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9737         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9738         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9739         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9740         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9741         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9742         u8         reserved_at_0[0x60e0];
9743 };
9744
9745 union mlx5_ifc_debug_enhancements_document_bits {
9746         struct mlx5_ifc_health_buffer_bits health_buffer;
9747         u8         reserved_at_0[0x200];
9748 };
9749
9750 union mlx5_ifc_uplink_pci_interface_document_bits {
9751         struct mlx5_ifc_initial_seg_bits initial_seg;
9752         u8         reserved_at_0[0x20060];
9753 };
9754
9755 struct mlx5_ifc_set_flow_table_root_out_bits {
9756         u8         status[0x8];
9757         u8         reserved_at_8[0x18];
9758
9759         u8         syndrome[0x20];
9760
9761         u8         reserved_at_40[0x40];
9762 };
9763
9764 struct mlx5_ifc_set_flow_table_root_in_bits {
9765         u8         opcode[0x10];
9766         u8         reserved_at_10[0x10];
9767
9768         u8         reserved_at_20[0x10];
9769         u8         op_mod[0x10];
9770
9771         u8         other_vport[0x1];
9772         u8         reserved_at_41[0xf];
9773         u8         vport_number[0x10];
9774
9775         u8         reserved_at_60[0x20];
9776
9777         u8         table_type[0x8];
9778         u8         reserved_at_88[0x18];
9779
9780         u8         reserved_at_a0[0x8];
9781         u8         table_id[0x18];
9782
9783         u8         reserved_at_c0[0x8];
9784         u8         underlay_qpn[0x18];
9785         u8         reserved_at_e0[0x120];
9786 };
9787
9788 enum {
9789         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9790         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9791 };
9792
9793 struct mlx5_ifc_modify_flow_table_out_bits {
9794         u8         status[0x8];
9795         u8         reserved_at_8[0x18];
9796
9797         u8         syndrome[0x20];
9798
9799         u8         reserved_at_40[0x40];
9800 };
9801
9802 struct mlx5_ifc_modify_flow_table_in_bits {
9803         u8         opcode[0x10];
9804         u8         reserved_at_10[0x10];
9805
9806         u8         reserved_at_20[0x10];
9807         u8         op_mod[0x10];
9808
9809         u8         other_vport[0x1];
9810         u8         reserved_at_41[0xf];
9811         u8         vport_number[0x10];
9812
9813         u8         reserved_at_60[0x10];
9814         u8         modify_field_select[0x10];
9815
9816         u8         table_type[0x8];
9817         u8         reserved_at_88[0x18];
9818
9819         u8         reserved_at_a0[0x8];
9820         u8         table_id[0x18];
9821
9822         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9823 };
9824
9825 struct mlx5_ifc_ets_tcn_config_reg_bits {
9826         u8         g[0x1];
9827         u8         b[0x1];
9828         u8         r[0x1];
9829         u8         reserved_at_3[0x9];
9830         u8         group[0x4];
9831         u8         reserved_at_10[0x9];
9832         u8         bw_allocation[0x7];
9833
9834         u8         reserved_at_20[0xc];
9835         u8         max_bw_units[0x4];
9836         u8         reserved_at_30[0x8];
9837         u8         max_bw_value[0x8];
9838 };
9839
9840 struct mlx5_ifc_ets_global_config_reg_bits {
9841         u8         reserved_at_0[0x2];
9842         u8         r[0x1];
9843         u8         reserved_at_3[0x1d];
9844
9845         u8         reserved_at_20[0xc];
9846         u8         max_bw_units[0x4];
9847         u8         reserved_at_30[0x8];
9848         u8         max_bw_value[0x8];
9849 };
9850
9851 struct mlx5_ifc_qetc_reg_bits {
9852         u8                                         reserved_at_0[0x8];
9853         u8                                         port_number[0x8];
9854         u8                                         reserved_at_10[0x30];
9855
9856         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9857         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9858 };
9859
9860 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9861         u8         e[0x1];
9862         u8         reserved_at_01[0x0b];
9863         u8         prio[0x04];
9864 };
9865
9866 struct mlx5_ifc_qpdpm_reg_bits {
9867         u8                                     reserved_at_0[0x8];
9868         u8                                     local_port[0x8];
9869         u8                                     reserved_at_10[0x10];
9870         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9871 };
9872
9873 struct mlx5_ifc_qpts_reg_bits {
9874         u8         reserved_at_0[0x8];
9875         u8         local_port[0x8];
9876         u8         reserved_at_10[0x2d];
9877         u8         trust_state[0x3];
9878 };
9879
9880 struct mlx5_ifc_pptb_reg_bits {
9881         u8         reserved_at_0[0x2];
9882         u8         mm[0x2];
9883         u8         reserved_at_4[0x4];
9884         u8         local_port[0x8];
9885         u8         reserved_at_10[0x6];
9886         u8         cm[0x1];
9887         u8         um[0x1];
9888         u8         pm[0x8];
9889
9890         u8         prio_x_buff[0x20];
9891
9892         u8         pm_msb[0x8];
9893         u8         reserved_at_48[0x10];
9894         u8         ctrl_buff[0x4];
9895         u8         untagged_buff[0x4];
9896 };
9897
9898 struct mlx5_ifc_pbmc_reg_bits {
9899         u8         reserved_at_0[0x8];
9900         u8         local_port[0x8];
9901         u8         reserved_at_10[0x10];
9902
9903         u8         xoff_timer_value[0x10];
9904         u8         xoff_refresh[0x10];
9905
9906         u8         reserved_at_40[0x9];
9907         u8         fullness_threshold[0x7];
9908         u8         port_buffer_size[0x10];
9909
9910         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9911
9912         u8         reserved_at_2e0[0x40];
9913 };
9914
9915 struct mlx5_ifc_qtct_reg_bits {
9916         u8         reserved_at_0[0x8];
9917         u8         port_number[0x8];
9918         u8         reserved_at_10[0xd];
9919         u8         prio[0x3];
9920
9921         u8         reserved_at_20[0x1d];
9922         u8         tclass[0x3];
9923 };
9924
9925 struct mlx5_ifc_mcia_reg_bits {
9926         u8         l[0x1];
9927         u8         reserved_at_1[0x7];
9928         u8         module[0x8];
9929         u8         reserved_at_10[0x8];
9930         u8         status[0x8];
9931
9932         u8         i2c_device_address[0x8];
9933         u8         page_number[0x8];
9934         u8         device_address[0x10];
9935
9936         u8         reserved_at_40[0x10];
9937         u8         size[0x10];
9938
9939         u8         reserved_at_60[0x20];
9940
9941         u8         dword_0[0x20];
9942         u8         dword_1[0x20];
9943         u8         dword_2[0x20];
9944         u8         dword_3[0x20];
9945         u8         dword_4[0x20];
9946         u8         dword_5[0x20];
9947         u8         dword_6[0x20];
9948         u8         dword_7[0x20];
9949         u8         dword_8[0x20];
9950         u8         dword_9[0x20];
9951         u8         dword_10[0x20];
9952         u8         dword_11[0x20];
9953 };
9954
9955 struct mlx5_ifc_dcbx_param_bits {
9956         u8         dcbx_cee_cap[0x1];
9957         u8         dcbx_ieee_cap[0x1];
9958         u8         dcbx_standby_cap[0x1];
9959         u8         reserved_at_3[0x5];
9960         u8         port_number[0x8];
9961         u8         reserved_at_10[0xa];
9962         u8         max_application_table_size[6];
9963         u8         reserved_at_20[0x15];
9964         u8         version_oper[0x3];
9965         u8         reserved_at_38[5];
9966         u8         version_admin[0x3];
9967         u8         willing_admin[0x1];
9968         u8         reserved_at_41[0x3];
9969         u8         pfc_cap_oper[0x4];
9970         u8         reserved_at_48[0x4];
9971         u8         pfc_cap_admin[0x4];
9972         u8         reserved_at_50[0x4];
9973         u8         num_of_tc_oper[0x4];
9974         u8         reserved_at_58[0x4];
9975         u8         num_of_tc_admin[0x4];
9976         u8         remote_willing[0x1];
9977         u8         reserved_at_61[3];
9978         u8         remote_pfc_cap[4];
9979         u8         reserved_at_68[0x14];
9980         u8         remote_num_of_tc[0x4];
9981         u8         reserved_at_80[0x18];
9982         u8         error[0x8];
9983         u8         reserved_at_a0[0x160];
9984 };
9985
9986 struct mlx5_ifc_lagc_bits {
9987         u8         reserved_at_0[0x1d];
9988         u8         lag_state[0x3];
9989
9990         u8         reserved_at_20[0x14];
9991         u8         tx_remap_affinity_2[0x4];
9992         u8         reserved_at_38[0x4];
9993         u8         tx_remap_affinity_1[0x4];
9994 };
9995
9996 struct mlx5_ifc_create_lag_out_bits {
9997         u8         status[0x8];
9998         u8         reserved_at_8[0x18];
9999
10000         u8         syndrome[0x20];
10001
10002         u8         reserved_at_40[0x40];
10003 };
10004
10005 struct mlx5_ifc_create_lag_in_bits {
10006         u8         opcode[0x10];
10007         u8         reserved_at_10[0x10];
10008
10009         u8         reserved_at_20[0x10];
10010         u8         op_mod[0x10];
10011
10012         struct mlx5_ifc_lagc_bits ctx;
10013 };
10014
10015 struct mlx5_ifc_modify_lag_out_bits {
10016         u8         status[0x8];
10017         u8         reserved_at_8[0x18];
10018
10019         u8         syndrome[0x20];
10020
10021         u8         reserved_at_40[0x40];
10022 };
10023
10024 struct mlx5_ifc_modify_lag_in_bits {
10025         u8         opcode[0x10];
10026         u8         reserved_at_10[0x10];
10027
10028         u8         reserved_at_20[0x10];
10029         u8         op_mod[0x10];
10030
10031         u8         reserved_at_40[0x20];
10032         u8         field_select[0x20];
10033
10034         struct mlx5_ifc_lagc_bits ctx;
10035 };
10036
10037 struct mlx5_ifc_query_lag_out_bits {
10038         u8         status[0x8];
10039         u8         reserved_at_8[0x18];
10040
10041         u8         syndrome[0x20];
10042
10043         struct mlx5_ifc_lagc_bits ctx;
10044 };
10045
10046 struct mlx5_ifc_query_lag_in_bits {
10047         u8         opcode[0x10];
10048         u8         reserved_at_10[0x10];
10049
10050         u8         reserved_at_20[0x10];
10051         u8         op_mod[0x10];
10052
10053         u8         reserved_at_40[0x40];
10054 };
10055
10056 struct mlx5_ifc_destroy_lag_out_bits {
10057         u8         status[0x8];
10058         u8         reserved_at_8[0x18];
10059
10060         u8         syndrome[0x20];
10061
10062         u8         reserved_at_40[0x40];
10063 };
10064
10065 struct mlx5_ifc_destroy_lag_in_bits {
10066         u8         opcode[0x10];
10067         u8         reserved_at_10[0x10];
10068
10069         u8         reserved_at_20[0x10];
10070         u8         op_mod[0x10];
10071
10072         u8         reserved_at_40[0x40];
10073 };
10074
10075 struct mlx5_ifc_create_vport_lag_out_bits {
10076         u8         status[0x8];
10077         u8         reserved_at_8[0x18];
10078
10079         u8         syndrome[0x20];
10080
10081         u8         reserved_at_40[0x40];
10082 };
10083
10084 struct mlx5_ifc_create_vport_lag_in_bits {
10085         u8         opcode[0x10];
10086         u8         reserved_at_10[0x10];
10087
10088         u8         reserved_at_20[0x10];
10089         u8         op_mod[0x10];
10090
10091         u8         reserved_at_40[0x40];
10092 };
10093
10094 struct mlx5_ifc_destroy_vport_lag_out_bits {
10095         u8         status[0x8];
10096         u8         reserved_at_8[0x18];
10097
10098         u8         syndrome[0x20];
10099
10100         u8         reserved_at_40[0x40];
10101 };
10102
10103 struct mlx5_ifc_destroy_vport_lag_in_bits {
10104         u8         opcode[0x10];
10105         u8         reserved_at_10[0x10];
10106
10107         u8         reserved_at_20[0x10];
10108         u8         op_mod[0x10];
10109
10110         u8         reserved_at_40[0x40];
10111 };
10112
10113 struct mlx5_ifc_alloc_memic_in_bits {
10114         u8         opcode[0x10];
10115         u8         reserved_at_10[0x10];
10116
10117         u8         reserved_at_20[0x10];
10118         u8         op_mod[0x10];
10119
10120         u8         reserved_at_30[0x20];
10121
10122         u8         reserved_at_40[0x18];
10123         u8         log_memic_addr_alignment[0x8];
10124
10125         u8         range_start_addr[0x40];
10126
10127         u8         range_size[0x20];
10128
10129         u8         memic_size[0x20];
10130 };
10131
10132 struct mlx5_ifc_alloc_memic_out_bits {
10133         u8         status[0x8];
10134         u8         reserved_at_8[0x18];
10135
10136         u8         syndrome[0x20];
10137
10138         u8         memic_start_addr[0x40];
10139 };
10140
10141 struct mlx5_ifc_dealloc_memic_in_bits {
10142         u8         opcode[0x10];
10143         u8         reserved_at_10[0x10];
10144
10145         u8         reserved_at_20[0x10];
10146         u8         op_mod[0x10];
10147
10148         u8         reserved_at_40[0x40];
10149
10150         u8         memic_start_addr[0x40];
10151
10152         u8         memic_size[0x20];
10153
10154         u8         reserved_at_e0[0x20];
10155 };
10156
10157 struct mlx5_ifc_dealloc_memic_out_bits {
10158         u8         status[0x8];
10159         u8         reserved_at_8[0x18];
10160
10161         u8         syndrome[0x20];
10162
10163         u8         reserved_at_40[0x40];
10164 };
10165
10166 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10167         u8         opcode[0x10];
10168         u8         uid[0x10];
10169
10170         u8         vhca_tunnel_id[0x10];
10171         u8         obj_type[0x10];
10172
10173         u8         obj_id[0x20];
10174
10175         u8         reserved_at_60[0x20];
10176 };
10177
10178 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10179         u8         status[0x8];
10180         u8         reserved_at_8[0x18];
10181
10182         u8         syndrome[0x20];
10183
10184         u8         obj_id[0x20];
10185
10186         u8         reserved_at_60[0x20];
10187 };
10188
10189 struct mlx5_ifc_umem_bits {
10190         u8         reserved_at_0[0x80];
10191
10192         u8         reserved_at_80[0x1b];
10193         u8         log_page_size[0x5];
10194
10195         u8         page_offset[0x20];
10196
10197         u8         num_of_mtt[0x40];
10198
10199         struct mlx5_ifc_mtt_bits  mtt[0];
10200 };
10201
10202 struct mlx5_ifc_uctx_bits {
10203         u8         cap[0x20];
10204
10205         u8         reserved_at_20[0x160];
10206 };
10207
10208 struct mlx5_ifc_sw_icm_bits {
10209         u8         modify_field_select[0x40];
10210
10211         u8         reserved_at_40[0x18];
10212         u8         log_sw_icm_size[0x8];
10213
10214         u8         reserved_at_60[0x20];
10215
10216         u8         sw_icm_start_addr[0x40];
10217
10218         u8         reserved_at_c0[0x140];
10219 };
10220
10221 struct mlx5_ifc_geneve_tlv_option_bits {
10222         u8         modify_field_select[0x40];
10223
10224         u8         reserved_at_40[0x18];
10225         u8         geneve_option_fte_index[0x8];
10226
10227         u8         option_class[0x10];
10228         u8         option_type[0x8];
10229         u8         reserved_at_78[0x3];
10230         u8         option_data_length[0x5];
10231
10232         u8         reserved_at_80[0x180];
10233 };
10234
10235 struct mlx5_ifc_create_umem_in_bits {
10236         u8         opcode[0x10];
10237         u8         uid[0x10];
10238
10239         u8         reserved_at_20[0x10];
10240         u8         op_mod[0x10];
10241
10242         u8         reserved_at_40[0x40];
10243
10244         struct mlx5_ifc_umem_bits  umem;
10245 };
10246
10247 struct mlx5_ifc_create_uctx_in_bits {
10248         u8         opcode[0x10];
10249         u8         reserved_at_10[0x10];
10250
10251         u8         reserved_at_20[0x10];
10252         u8         op_mod[0x10];
10253
10254         u8         reserved_at_40[0x40];
10255
10256         struct mlx5_ifc_uctx_bits  uctx;
10257 };
10258
10259 struct mlx5_ifc_destroy_uctx_in_bits {
10260         u8         opcode[0x10];
10261         u8         reserved_at_10[0x10];
10262
10263         u8         reserved_at_20[0x10];
10264         u8         op_mod[0x10];
10265
10266         u8         reserved_at_40[0x10];
10267         u8         uid[0x10];
10268
10269         u8         reserved_at_60[0x20];
10270 };
10271
10272 struct mlx5_ifc_create_sw_icm_in_bits {
10273         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10274         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10275 };
10276
10277 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10278         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10279         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10280 };
10281
10282 struct mlx5_ifc_mtrc_string_db_param_bits {
10283         u8         string_db_base_address[0x20];
10284
10285         u8         reserved_at_20[0x8];
10286         u8         string_db_size[0x18];
10287 };
10288
10289 struct mlx5_ifc_mtrc_cap_bits {
10290         u8         trace_owner[0x1];
10291         u8         trace_to_memory[0x1];
10292         u8         reserved_at_2[0x4];
10293         u8         trc_ver[0x2];
10294         u8         reserved_at_8[0x14];
10295         u8         num_string_db[0x4];
10296
10297         u8         first_string_trace[0x8];
10298         u8         num_string_trace[0x8];
10299         u8         reserved_at_30[0x28];
10300
10301         u8         log_max_trace_buffer_size[0x8];
10302
10303         u8         reserved_at_60[0x20];
10304
10305         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10306
10307         u8         reserved_at_280[0x180];
10308 };
10309
10310 struct mlx5_ifc_mtrc_conf_bits {
10311         u8         reserved_at_0[0x1c];
10312         u8         trace_mode[0x4];
10313         u8         reserved_at_20[0x18];
10314         u8         log_trace_buffer_size[0x8];
10315         u8         trace_mkey[0x20];
10316         u8         reserved_at_60[0x3a0];
10317 };
10318
10319 struct mlx5_ifc_mtrc_stdb_bits {
10320         u8         string_db_index[0x4];
10321         u8         reserved_at_4[0x4];
10322         u8         read_size[0x18];
10323         u8         start_offset[0x20];
10324         u8         string_db_data[0];
10325 };
10326
10327 struct mlx5_ifc_mtrc_ctrl_bits {
10328         u8         trace_status[0x2];
10329         u8         reserved_at_2[0x2];
10330         u8         arm_event[0x1];
10331         u8         reserved_at_5[0xb];
10332         u8         modify_field_select[0x10];
10333         u8         reserved_at_20[0x2b];
10334         u8         current_timestamp52_32[0x15];
10335         u8         current_timestamp31_0[0x20];
10336         u8         reserved_at_80[0x180];
10337 };
10338
10339 struct mlx5_ifc_host_params_context_bits {
10340         u8         host_number[0x8];
10341         u8         reserved_at_8[0x7];
10342         u8         host_pf_disabled[0x1];
10343         u8         host_num_of_vfs[0x10];
10344
10345         u8         host_total_vfs[0x10];
10346         u8         host_pci_bus[0x10];
10347
10348         u8         reserved_at_40[0x10];
10349         u8         host_pci_device[0x10];
10350
10351         u8         reserved_at_60[0x10];
10352         u8         host_pci_function[0x10];
10353
10354         u8         reserved_at_80[0x180];
10355 };
10356
10357 struct mlx5_ifc_query_esw_functions_in_bits {
10358         u8         opcode[0x10];
10359         u8         reserved_at_10[0x10];
10360
10361         u8         reserved_at_20[0x10];
10362         u8         op_mod[0x10];
10363
10364         u8         reserved_at_40[0x40];
10365 };
10366
10367 struct mlx5_ifc_query_esw_functions_out_bits {
10368         u8         status[0x8];
10369         u8         reserved_at_8[0x18];
10370
10371         u8         syndrome[0x20];
10372
10373         u8         reserved_at_40[0x40];
10374
10375         struct mlx5_ifc_host_params_context_bits host_params_context;
10376
10377         u8         reserved_at_280[0x180];
10378         u8         host_sf_enable[0][0x40];
10379 };
10380
10381 struct mlx5_ifc_sf_partition_bits {
10382         u8         reserved_at_0[0x10];
10383         u8         log_num_sf[0x8];
10384         u8         log_sf_bar_size[0x8];
10385 };
10386
10387 struct mlx5_ifc_query_sf_partitions_out_bits {
10388         u8         status[0x8];
10389         u8         reserved_at_8[0x18];
10390
10391         u8         syndrome[0x20];
10392
10393         u8         reserved_at_40[0x18];
10394         u8         num_sf_partitions[0x8];
10395
10396         u8         reserved_at_60[0x20];
10397
10398         struct mlx5_ifc_sf_partition_bits sf_partition[0];
10399 };
10400
10401 struct mlx5_ifc_query_sf_partitions_in_bits {
10402         u8         opcode[0x10];
10403         u8         reserved_at_10[0x10];
10404
10405         u8         reserved_at_20[0x10];
10406         u8         op_mod[0x10];
10407
10408         u8         reserved_at_40[0x40];
10409 };
10410
10411 struct mlx5_ifc_dealloc_sf_out_bits {
10412         u8         status[0x8];
10413         u8         reserved_at_8[0x18];
10414
10415         u8         syndrome[0x20];
10416
10417         u8         reserved_at_40[0x40];
10418 };
10419
10420 struct mlx5_ifc_dealloc_sf_in_bits {
10421         u8         opcode[0x10];
10422         u8         reserved_at_10[0x10];
10423
10424         u8         reserved_at_20[0x10];
10425         u8         op_mod[0x10];
10426
10427         u8         reserved_at_40[0x10];
10428         u8         function_id[0x10];
10429
10430         u8         reserved_at_60[0x20];
10431 };
10432
10433 struct mlx5_ifc_alloc_sf_out_bits {
10434         u8         status[0x8];
10435         u8         reserved_at_8[0x18];
10436
10437         u8         syndrome[0x20];
10438
10439         u8         reserved_at_40[0x40];
10440 };
10441
10442 struct mlx5_ifc_alloc_sf_in_bits {
10443         u8         opcode[0x10];
10444         u8         reserved_at_10[0x10];
10445
10446         u8         reserved_at_20[0x10];
10447         u8         op_mod[0x10];
10448
10449         u8         reserved_at_40[0x10];
10450         u8         function_id[0x10];
10451
10452         u8         reserved_at_60[0x20];
10453 };
10454
10455 struct mlx5_ifc_affiliated_event_header_bits {
10456         u8         reserved_at_0[0x10];
10457         u8         obj_type[0x10];
10458
10459         u8         obj_id[0x20];
10460 };
10461
10462 enum {
10463         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10464 };
10465
10466 enum {
10467         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10468 };
10469
10470 struct mlx5_ifc_encryption_key_obj_bits {
10471         u8         modify_field_select[0x40];
10472
10473         u8         reserved_at_40[0x14];
10474         u8         key_size[0x4];
10475         u8         reserved_at_58[0x4];
10476         u8         key_type[0x4];
10477
10478         u8         reserved_at_60[0x8];
10479         u8         pd[0x18];
10480
10481         u8         reserved_at_80[0x180];
10482         u8         key[8][0x20];
10483
10484         u8         reserved_at_300[0x500];
10485 };
10486
10487 struct mlx5_ifc_create_encryption_key_in_bits {
10488         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10489         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10490 };
10491
10492 enum {
10493         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10494         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10495 };
10496
10497 enum {
10498         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10499         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10500 };
10501
10502 struct mlx5_ifc_tls_static_params_bits {
10503         u8         const_2[0x2];
10504         u8         tls_version[0x4];
10505         u8         const_1[0x2];
10506         u8         reserved_at_8[0x14];
10507         u8         encryption_standard[0x4];
10508
10509         u8         reserved_at_20[0x20];
10510
10511         u8         initial_record_number[0x40];
10512
10513         u8         resync_tcp_sn[0x20];
10514
10515         u8         gcm_iv[0x20];
10516
10517         u8         implicit_iv[0x40];
10518
10519         u8         reserved_at_100[0x8];
10520         u8         dek_index[0x18];
10521
10522         u8         reserved_at_120[0xe0];
10523 };
10524
10525 struct mlx5_ifc_tls_progress_params_bits {
10526         u8         reserved_at_0[0x8];
10527         u8         tisn[0x18];
10528
10529         u8         next_record_tcp_sn[0x20];
10530
10531         u8         hw_resync_tcp_sn[0x20];
10532
10533         u8         record_tracker_state[0x2];
10534         u8         auth_state[0x2];
10535         u8         reserved_at_64[0x4];
10536         u8         hw_offset_record_number[0x18];
10537 };
10538
10539 #endif /* MLX5_IFC_H */