2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
96 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
97 MLX5_CMD_OP_CREATE_EQ = 0x301,
98 MLX5_CMD_OP_DESTROY_EQ = 0x302,
99 MLX5_CMD_OP_QUERY_EQ = 0x303,
100 MLX5_CMD_OP_GEN_EQE = 0x304,
101 MLX5_CMD_OP_CREATE_CQ = 0x400,
102 MLX5_CMD_OP_DESTROY_CQ = 0x401,
103 MLX5_CMD_OP_QUERY_CQ = 0x402,
104 MLX5_CMD_OP_MODIFY_CQ = 0x403,
105 MLX5_CMD_OP_CREATE_QP = 0x500,
106 MLX5_CMD_OP_DESTROY_QP = 0x501,
107 MLX5_CMD_OP_RST2INIT_QP = 0x502,
108 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
109 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
110 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
111 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
112 MLX5_CMD_OP_2ERR_QP = 0x507,
113 MLX5_CMD_OP_2RST_QP = 0x50a,
114 MLX5_CMD_OP_QUERY_QP = 0x50b,
115 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
116 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
117 MLX5_CMD_OP_CREATE_PSV = 0x600,
118 MLX5_CMD_OP_DESTROY_PSV = 0x601,
119 MLX5_CMD_OP_CREATE_SRQ = 0x700,
120 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
121 MLX5_CMD_OP_QUERY_SRQ = 0x702,
122 MLX5_CMD_OP_ARM_RQ = 0x703,
123 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
124 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
125 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
126 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
127 MLX5_CMD_OP_CREATE_DCT = 0x710,
128 MLX5_CMD_OP_DESTROY_DCT = 0x711,
129 MLX5_CMD_OP_DRAIN_DCT = 0x712,
130 MLX5_CMD_OP_QUERY_DCT = 0x713,
131 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
132 MLX5_CMD_OP_CREATE_XRQ = 0x717,
133 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
134 MLX5_CMD_OP_QUERY_XRQ = 0x719,
135 MLX5_CMD_OP_ARM_XRQ = 0x71a,
136 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
137 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
138 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
139 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
140 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
141 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
142 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
143 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
145 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
146 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
148 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
149 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
150 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
151 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
152 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
153 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
154 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
155 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
156 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
157 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
158 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
159 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
160 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
161 MLX5_CMD_OP_ALLOC_PD = 0x800,
162 MLX5_CMD_OP_DEALLOC_PD = 0x801,
163 MLX5_CMD_OP_ALLOC_UAR = 0x802,
164 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
166 MLX5_CMD_OP_ACCESS_REG = 0x805,
167 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
168 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
169 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
170 MLX5_CMD_OP_MAD_IFC = 0x50d,
171 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
172 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
173 MLX5_CMD_OP_NOP = 0x80d,
174 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
175 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
176 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
177 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
178 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
179 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
180 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
181 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
182 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
183 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
184 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
185 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
186 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
187 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
188 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
189 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
190 MLX5_CMD_OP_CREATE_LAG = 0x840,
191 MLX5_CMD_OP_MODIFY_LAG = 0x841,
192 MLX5_CMD_OP_QUERY_LAG = 0x842,
193 MLX5_CMD_OP_DESTROY_LAG = 0x843,
194 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
195 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
196 MLX5_CMD_OP_CREATE_TIR = 0x900,
197 MLX5_CMD_OP_MODIFY_TIR = 0x901,
198 MLX5_CMD_OP_DESTROY_TIR = 0x902,
199 MLX5_CMD_OP_QUERY_TIR = 0x903,
200 MLX5_CMD_OP_CREATE_SQ = 0x904,
201 MLX5_CMD_OP_MODIFY_SQ = 0x905,
202 MLX5_CMD_OP_DESTROY_SQ = 0x906,
203 MLX5_CMD_OP_QUERY_SQ = 0x907,
204 MLX5_CMD_OP_CREATE_RQ = 0x908,
205 MLX5_CMD_OP_MODIFY_RQ = 0x909,
206 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
207 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
208 MLX5_CMD_OP_QUERY_RQ = 0x90b,
209 MLX5_CMD_OP_CREATE_RMP = 0x90c,
210 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
211 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
212 MLX5_CMD_OP_QUERY_RMP = 0x90f,
213 MLX5_CMD_OP_CREATE_TIS = 0x912,
214 MLX5_CMD_OP_MODIFY_TIS = 0x913,
215 MLX5_CMD_OP_DESTROY_TIS = 0x914,
216 MLX5_CMD_OP_QUERY_TIS = 0x915,
217 MLX5_CMD_OP_CREATE_RQT = 0x916,
218 MLX5_CMD_OP_MODIFY_RQT = 0x917,
219 MLX5_CMD_OP_DESTROY_RQT = 0x918,
220 MLX5_CMD_OP_QUERY_RQT = 0x919,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
222 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
223 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
224 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
225 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
226 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
227 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
228 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
229 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
230 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
231 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
232 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
233 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
234 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
235 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
236 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
237 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
238 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
239 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
240 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
241 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
242 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
243 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
247 struct mlx5_ifc_flow_table_fields_supported_bits {
250 u8 outer_ether_type[0x1];
251 u8 outer_ip_version[0x1];
252 u8 outer_first_prio[0x1];
253 u8 outer_first_cfi[0x1];
254 u8 outer_first_vid[0x1];
255 u8 outer_ipv4_ttl[0x1];
256 u8 outer_second_prio[0x1];
257 u8 outer_second_cfi[0x1];
258 u8 outer_second_vid[0x1];
259 u8 reserved_at_b[0x1];
263 u8 outer_ip_protocol[0x1];
264 u8 outer_ip_ecn[0x1];
265 u8 outer_ip_dscp[0x1];
266 u8 outer_udp_sport[0x1];
267 u8 outer_udp_dport[0x1];
268 u8 outer_tcp_sport[0x1];
269 u8 outer_tcp_dport[0x1];
270 u8 outer_tcp_flags[0x1];
271 u8 outer_gre_protocol[0x1];
272 u8 outer_gre_key[0x1];
273 u8 outer_vxlan_vni[0x1];
274 u8 reserved_at_1a[0x5];
275 u8 source_eswitch_port[0x1];
279 u8 inner_ether_type[0x1];
280 u8 inner_ip_version[0x1];
281 u8 inner_first_prio[0x1];
282 u8 inner_first_cfi[0x1];
283 u8 inner_first_vid[0x1];
284 u8 reserved_at_27[0x1];
285 u8 inner_second_prio[0x1];
286 u8 inner_second_cfi[0x1];
287 u8 inner_second_vid[0x1];
288 u8 reserved_at_2b[0x1];
292 u8 inner_ip_protocol[0x1];
293 u8 inner_ip_ecn[0x1];
294 u8 inner_ip_dscp[0x1];
295 u8 inner_udp_sport[0x1];
296 u8 inner_udp_dport[0x1];
297 u8 inner_tcp_sport[0x1];
298 u8 inner_tcp_dport[0x1];
299 u8 inner_tcp_flags[0x1];
300 u8 reserved_at_37[0x9];
301 u8 reserved_at_40[0x17];
302 u8 outer_esp_spi[0x1];
303 u8 reserved_at_58[0x2];
306 u8 reserved_at_5b[0x25];
309 struct mlx5_ifc_flow_table_prop_layout_bits {
311 u8 reserved_at_1[0x1];
312 u8 flow_counter[0x1];
313 u8 flow_modify_en[0x1];
315 u8 identified_miss_table_mode[0x1];
316 u8 flow_table_modify[0x1];
319 u8 reserved_at_9[0x1];
322 u8 reserved_at_c[0x14];
324 u8 reserved_at_20[0x2];
325 u8 log_max_ft_size[0x6];
326 u8 log_max_modify_header_context[0x8];
327 u8 max_modify_header_actions[0x8];
328 u8 max_ft_level[0x8];
330 u8 reserved_at_40[0x20];
332 u8 reserved_at_60[0x18];
333 u8 log_max_ft_num[0x8];
335 u8 reserved_at_80[0x18];
336 u8 log_max_destination[0x8];
338 u8 log_max_flow_counter[0x8];
339 u8 reserved_at_a8[0x10];
340 u8 log_max_flow[0x8];
342 u8 reserved_at_c0[0x40];
344 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
346 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
349 struct mlx5_ifc_odp_per_transport_service_cap_bits {
356 u8 reserved_at_6[0x1a];
359 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
384 u8 reserved_at_c0[0x18];
385 u8 ttl_hoplimit[0x8];
390 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
392 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
395 struct mlx5_ifc_fte_match_set_misc_bits {
396 u8 reserved_at_0[0x8];
399 u8 source_eswitch_owner_vhca_id[0x10];
400 u8 source_port[0x10];
402 u8 outer_second_prio[0x3];
403 u8 outer_second_cfi[0x1];
404 u8 outer_second_vid[0xc];
405 u8 inner_second_prio[0x3];
406 u8 inner_second_cfi[0x1];
407 u8 inner_second_vid[0xc];
409 u8 outer_second_cvlan_tag[0x1];
410 u8 inner_second_cvlan_tag[0x1];
411 u8 outer_second_svlan_tag[0x1];
412 u8 inner_second_svlan_tag[0x1];
413 u8 reserved_at_64[0xc];
414 u8 gre_protocol[0x10];
420 u8 reserved_at_b8[0x8];
422 u8 reserved_at_c0[0x20];
424 u8 reserved_at_e0[0xc];
425 u8 outer_ipv6_flow_label[0x14];
427 u8 reserved_at_100[0xc];
428 u8 inner_ipv6_flow_label[0x14];
430 u8 reserved_at_120[0x28];
432 u8 reserved_at_160[0x20];
433 u8 outer_esp_spi[0x20];
434 u8 reserved_at_1a0[0x60];
437 struct mlx5_ifc_cmd_pas_bits {
441 u8 reserved_at_34[0xc];
444 struct mlx5_ifc_uint64_bits {
451 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
452 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
453 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
454 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
455 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
456 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
457 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
458 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
459 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
460 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
463 struct mlx5_ifc_ads_bits {
466 u8 reserved_at_2[0xe];
469 u8 reserved_at_20[0x8];
475 u8 reserved_at_45[0x3];
476 u8 src_addr_index[0x8];
477 u8 reserved_at_50[0x4];
481 u8 reserved_at_60[0x4];
485 u8 rgid_rip[16][0x8];
487 u8 reserved_at_100[0x4];
490 u8 reserved_at_106[0x1];
499 u8 vhca_port_num[0x8];
505 struct mlx5_ifc_flow_table_nic_cap_bits {
506 u8 nic_rx_multi_path_tirs[0x1];
507 u8 nic_rx_multi_path_tirs_fts[0x1];
508 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
509 u8 reserved_at_3[0x1fd];
511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
513 u8 reserved_at_400[0x200];
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
519 u8 reserved_at_a00[0x200];
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
523 u8 reserved_at_e00[0x7200];
526 struct mlx5_ifc_flow_table_eswitch_cap_bits {
527 u8 reserved_at_0[0x200];
529 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
531 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
535 u8 reserved_at_800[0x7800];
538 struct mlx5_ifc_e_switch_cap_bits {
539 u8 vport_svlan_strip[0x1];
540 u8 vport_cvlan_strip[0x1];
541 u8 vport_svlan_insert[0x1];
542 u8 vport_cvlan_insert_if_not_exist[0x1];
543 u8 vport_cvlan_insert_overwrite[0x1];
544 u8 reserved_at_5[0x18];
545 u8 merged_eswitch[0x1];
546 u8 nic_vport_node_guid_modify[0x1];
547 u8 nic_vport_port_guid_modify[0x1];
549 u8 vxlan_encap_decap[0x1];
550 u8 nvgre_encap_decap[0x1];
551 u8 reserved_at_22[0x9];
552 u8 log_max_encap_headers[0x5];
554 u8 max_encap_header_size[0xa];
556 u8 reserved_40[0x7c0];
560 struct mlx5_ifc_qos_cap_bits {
561 u8 packet_pacing[0x1];
562 u8 esw_scheduling[0x1];
563 u8 esw_bw_share[0x1];
564 u8 esw_rate_limit[0x1];
565 u8 reserved_at_4[0x1];
566 u8 packet_pacing_burst_bound[0x1];
567 u8 packet_pacing_typical_size[0x1];
568 u8 reserved_at_7[0x19];
570 u8 reserved_at_20[0x20];
572 u8 packet_pacing_max_rate[0x20];
574 u8 packet_pacing_min_rate[0x20];
576 u8 reserved_at_80[0x10];
577 u8 packet_pacing_rate_table_size[0x10];
579 u8 esw_element_type[0x10];
580 u8 esw_tsar_type[0x10];
582 u8 reserved_at_c0[0x10];
583 u8 max_qos_para_vport[0x10];
585 u8 max_tsar_bw_share[0x20];
587 u8 reserved_at_100[0x700];
590 struct mlx5_ifc_debug_cap_bits {
591 u8 reserved_at_0[0x20];
593 u8 reserved_at_20[0x2];
594 u8 stall_detect[0x1];
595 u8 reserved_at_23[0x1d];
597 u8 reserved_at_40[0x7c0];
600 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
604 u8 lro_psh_flag[0x1];
605 u8 lro_time_stamp[0x1];
606 u8 reserved_at_5[0x2];
607 u8 wqe_vlan_insert[0x1];
608 u8 self_lb_en_modifiable[0x1];
609 u8 reserved_at_9[0x2];
611 u8 multi_pkt_send_wqe[0x2];
612 u8 wqe_inline_mode[0x2];
613 u8 rss_ind_tbl_cap[0x4];
616 u8 enhanced_multi_pkt_send_wqe[0x1];
617 u8 tunnel_lso_const_out_ip_id[0x1];
618 u8 reserved_at_1c[0x2];
619 u8 tunnel_stateless_gre[0x1];
620 u8 tunnel_stateless_vxlan[0x1];
625 u8 reserved_at_23[0x1b];
626 u8 max_geneve_opt_len[0x1];
627 u8 tunnel_stateless_geneve_rx[0x1];
629 u8 reserved_at_40[0x10];
630 u8 lro_min_mss_size[0x10];
632 u8 reserved_at_60[0x120];
634 u8 lro_timer_supported_periods[4][0x20];
636 u8 reserved_at_200[0x600];
639 struct mlx5_ifc_roce_cap_bits {
641 u8 reserved_at_1[0x1f];
643 u8 reserved_at_20[0x60];
645 u8 reserved_at_80[0xc];
647 u8 reserved_at_90[0x8];
648 u8 roce_version[0x8];
650 u8 reserved_at_a0[0x10];
651 u8 r_roce_dest_udp_port[0x10];
653 u8 r_roce_max_src_udp_port[0x10];
654 u8 r_roce_min_src_udp_port[0x10];
656 u8 reserved_at_e0[0x10];
657 u8 roce_address_table_size[0x10];
659 u8 reserved_at_100[0x700];
662 struct mlx5_ifc_device_mem_cap_bits {
664 u8 reserved_at_1[0x1f];
666 u8 reserved_at_20[0xb];
667 u8 log_min_memic_alloc_size[0x5];
668 u8 reserved_at_30[0x8];
669 u8 log_max_memic_addr_alignment[0x8];
671 u8 memic_bar_start_addr[0x40];
673 u8 memic_bar_size[0x20];
675 u8 max_memic_size[0x20];
677 u8 reserved_at_c0[0x740];
681 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
682 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
683 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
693 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
694 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
695 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
704 struct mlx5_ifc_atomic_caps_bits {
705 u8 reserved_at_0[0x40];
707 u8 atomic_req_8B_endianness_mode[0x2];
708 u8 reserved_at_42[0x4];
709 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
711 u8 reserved_at_47[0x19];
713 u8 reserved_at_60[0x20];
715 u8 reserved_at_80[0x10];
716 u8 atomic_operations[0x10];
718 u8 reserved_at_a0[0x10];
719 u8 atomic_size_qp[0x10];
721 u8 reserved_at_c0[0x10];
722 u8 atomic_size_dc[0x10];
724 u8 reserved_at_e0[0x720];
727 struct mlx5_ifc_odp_cap_bits {
728 u8 reserved_at_0[0x40];
731 u8 reserved_at_41[0x1f];
733 u8 reserved_at_60[0x20];
735 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
737 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
739 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
741 u8 reserved_at_e0[0x720];
744 struct mlx5_ifc_calc_op {
745 u8 reserved_at_0[0x10];
746 u8 reserved_at_10[0x9];
747 u8 op_swap_endianness[0x1];
756 struct mlx5_ifc_vector_calc_cap_bits {
758 u8 reserved_at_1[0x1f];
759 u8 reserved_at_20[0x8];
760 u8 max_vec_count[0x8];
761 u8 reserved_at_30[0xd];
762 u8 max_chunk_size[0x3];
763 struct mlx5_ifc_calc_op calc0;
764 struct mlx5_ifc_calc_op calc1;
765 struct mlx5_ifc_calc_op calc2;
766 struct mlx5_ifc_calc_op calc3;
768 u8 reserved_at_e0[0x720];
772 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
773 MLX5_WQ_TYPE_CYCLIC = 0x1,
774 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
775 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
779 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
780 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
784 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
785 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
786 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
792 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
793 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
794 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
801 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
802 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
806 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
807 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
808 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
812 MLX5_CAP_PORT_TYPE_IB = 0x0,
813 MLX5_CAP_PORT_TYPE_ETH = 0x1,
817 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
818 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
819 MLX5_CAP_UMR_FENCE_NONE = 0x2,
822 struct mlx5_ifc_cmd_hca_cap_bits {
823 u8 reserved_at_0[0x30];
826 u8 reserved_at_40[0x40];
828 u8 log_max_srq_sz[0x8];
829 u8 log_max_qp_sz[0x8];
830 u8 reserved_at_90[0xb];
833 u8 reserved_at_a0[0xb];
835 u8 reserved_at_b0[0x10];
837 u8 reserved_at_c0[0x8];
838 u8 log_max_cq_sz[0x8];
839 u8 reserved_at_d0[0xb];
842 u8 log_max_eq_sz[0x8];
843 u8 reserved_at_e8[0x2];
844 u8 log_max_mkey[0x6];
845 u8 reserved_at_f0[0xc];
848 u8 max_indirection[0x8];
849 u8 fixed_buffer_size[0x1];
850 u8 log_max_mrw_sz[0x7];
851 u8 force_teardown[0x1];
852 u8 reserved_at_111[0x1];
853 u8 log_max_bsf_list_size[0x6];
854 u8 umr_extended_translation_offset[0x1];
856 u8 log_max_klm_list_size[0x6];
858 u8 reserved_at_120[0xa];
859 u8 log_max_ra_req_dc[0x6];
860 u8 reserved_at_130[0xa];
861 u8 log_max_ra_res_dc[0x6];
863 u8 reserved_at_140[0xa];
864 u8 log_max_ra_req_qp[0x6];
865 u8 reserved_at_150[0xa];
866 u8 log_max_ra_res_qp[0x6];
869 u8 cc_query_allowed[0x1];
870 u8 cc_modify_allowed[0x1];
872 u8 cache_line_128byte[0x1];
873 u8 reserved_at_165[0xa];
875 u8 gid_table_size[0x10];
877 u8 out_of_seq_cnt[0x1];
878 u8 vport_counters[0x1];
879 u8 retransmission_q_counters[0x1];
881 u8 modify_rq_counter_set_id[0x1];
882 u8 rq_delay_drop[0x1];
884 u8 pkey_table_size[0x10];
886 u8 vport_group_manager[0x1];
887 u8 vhca_group_manager[0x1];
890 u8 vnic_env_queue_counters[0x1];
892 u8 nic_flow_table[0x1];
893 u8 eswitch_flow_table[0x1];
894 u8 device_memory[0x1];
897 u8 local_ca_ack_delay[0x5];
898 u8 port_module_event[0x1];
899 u8 enhanced_error_q_counters[0x1];
901 u8 reserved_at_1b3[0x1];
902 u8 disable_link_up[0x1];
907 u8 reserved_at_1c0[0x1];
911 u8 reserved_at_1c8[0x4];
913 u8 reserved_at_1d0[0x1];
915 u8 general_notification_event[0x1];
916 u8 reserved_at_1d3[0x2];
920 u8 reserved_at_1d8[0x1];
929 u8 stat_rate_support[0x10];
930 u8 reserved_at_1f0[0xc];
933 u8 compact_address_vector[0x1];
935 u8 reserved_at_202[0x1];
936 u8 ipoib_enhanced_offloads[0x1];
937 u8 ipoib_basic_offloads[0x1];
938 u8 reserved_at_205[0x1];
939 u8 repeated_block_disabled[0x1];
940 u8 umr_modify_entity_size_disabled[0x1];
941 u8 umr_modify_atomic_disabled[0x1];
942 u8 umr_indirect_mkey_disabled[0x1];
944 u8 reserved_at_20c[0x3];
945 u8 drain_sigerr[0x1];
946 u8 cmdif_checksum[0x2];
948 u8 reserved_at_213[0x1];
949 u8 wq_signature[0x1];
950 u8 sctr_data_cqe[0x1];
951 u8 reserved_at_216[0x1];
957 u8 eth_net_offloads[0x1];
960 u8 reserved_at_21f[0x1];
964 u8 cq_moderation[0x1];
965 u8 reserved_at_223[0x3];
969 u8 reserved_at_229[0x1];
970 u8 scqe_break_moderation[0x1];
971 u8 cq_period_start_from_cqe[0x1];
973 u8 reserved_at_22d[0x1];
976 u8 umr_ptr_rlky[0x1];
978 u8 reserved_at_232[0x4];
981 u8 set_deth_sqpn[0x1];
982 u8 reserved_at_239[0x3];
989 u8 reserved_at_241[0x9];
991 u8 reserved_at_250[0x8];
995 u8 driver_version[0x1];
996 u8 pad_tx_eth_packet[0x1];
997 u8 reserved_at_263[0x8];
998 u8 log_bf_reg_size[0x5];
1000 u8 reserved_at_270[0xb];
1002 u8 num_lag_ports[0x4];
1004 u8 reserved_at_280[0x10];
1005 u8 max_wqe_sz_sq[0x10];
1007 u8 reserved_at_2a0[0x10];
1008 u8 max_wqe_sz_rq[0x10];
1010 u8 max_flow_counter_31_16[0x10];
1011 u8 max_wqe_sz_sq_dc[0x10];
1013 u8 reserved_at_2e0[0x7];
1014 u8 max_qp_mcg[0x19];
1016 u8 reserved_at_300[0x18];
1017 u8 log_max_mcg[0x8];
1019 u8 reserved_at_320[0x3];
1020 u8 log_max_transport_domain[0x5];
1021 u8 reserved_at_328[0x3];
1023 u8 reserved_at_330[0xb];
1024 u8 log_max_xrcd[0x5];
1026 u8 nic_receive_steering_discard[0x1];
1027 u8 receive_discard_vport_down[0x1];
1028 u8 transmit_discard_vport_down[0x1];
1029 u8 reserved_at_343[0x5];
1030 u8 log_max_flow_counter_bulk[0x8];
1031 u8 max_flow_counter_15_0[0x10];
1034 u8 reserved_at_360[0x3];
1036 u8 reserved_at_368[0x3];
1038 u8 reserved_at_370[0x3];
1039 u8 log_max_tir[0x5];
1040 u8 reserved_at_378[0x3];
1041 u8 log_max_tis[0x5];
1043 u8 basic_cyclic_rcv_wqe[0x1];
1044 u8 reserved_at_381[0x2];
1045 u8 log_max_rmp[0x5];
1046 u8 reserved_at_388[0x3];
1047 u8 log_max_rqt[0x5];
1048 u8 reserved_at_390[0x3];
1049 u8 log_max_rqt_size[0x5];
1050 u8 reserved_at_398[0x3];
1051 u8 log_max_tis_per_sq[0x5];
1053 u8 ext_stride_num_range[0x1];
1054 u8 reserved_at_3a1[0x2];
1055 u8 log_max_stride_sz_rq[0x5];
1056 u8 reserved_at_3a8[0x3];
1057 u8 log_min_stride_sz_rq[0x5];
1058 u8 reserved_at_3b0[0x3];
1059 u8 log_max_stride_sz_sq[0x5];
1060 u8 reserved_at_3b8[0x3];
1061 u8 log_min_stride_sz_sq[0x5];
1064 u8 reserved_at_3c1[0x2];
1065 u8 log_max_hairpin_queues[0x5];
1066 u8 reserved_at_3c8[0x3];
1067 u8 log_max_hairpin_wq_data_sz[0x5];
1068 u8 reserved_at_3d0[0x3];
1069 u8 log_max_hairpin_num_packets[0x5];
1070 u8 reserved_at_3d8[0x3];
1071 u8 log_max_wq_sz[0x5];
1073 u8 nic_vport_change_event[0x1];
1074 u8 disable_local_lb_uc[0x1];
1075 u8 disable_local_lb_mc[0x1];
1076 u8 log_min_hairpin_wq_data_sz[0x5];
1077 u8 reserved_at_3e8[0x3];
1078 u8 log_max_vlan_list[0x5];
1079 u8 reserved_at_3f0[0x3];
1080 u8 log_max_current_mc_list[0x5];
1081 u8 reserved_at_3f8[0x3];
1082 u8 log_max_current_uc_list[0x5];
1084 u8 reserved_at_400[0x80];
1086 u8 reserved_at_480[0x3];
1087 u8 log_max_l2_table[0x5];
1088 u8 reserved_at_488[0x8];
1089 u8 log_uar_page_sz[0x10];
1091 u8 reserved_at_4a0[0x20];
1092 u8 device_frequency_mhz[0x20];
1093 u8 device_frequency_khz[0x20];
1095 u8 reserved_at_500[0x20];
1096 u8 num_of_uars_per_page[0x20];
1097 u8 reserved_at_540[0x40];
1099 u8 reserved_at_580[0x3d];
1100 u8 cqe_128_always[0x1];
1101 u8 cqe_compression_128[0x1];
1102 u8 cqe_compression[0x1];
1104 u8 cqe_compression_timeout[0x10];
1105 u8 cqe_compression_max_num[0x10];
1107 u8 reserved_at_5e0[0x10];
1108 u8 tag_matching[0x1];
1109 u8 rndv_offload_rc[0x1];
1110 u8 rndv_offload_dc[0x1];
1111 u8 log_tag_matching_list_sz[0x5];
1112 u8 reserved_at_5f8[0x3];
1113 u8 log_max_xrq[0x5];
1115 u8 affiliate_nic_vport_criteria[0x8];
1116 u8 native_port_num[0x8];
1117 u8 num_vhca_ports[0x8];
1118 u8 reserved_at_618[0x6];
1119 u8 sw_owner_id[0x1];
1120 u8 reserved_at_61f[0x1e1];
1123 enum mlx5_flow_destination_type {
1124 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1125 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1126 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1128 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1129 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1132 struct mlx5_ifc_dest_format_struct_bits {
1133 u8 destination_type[0x8];
1134 u8 destination_id[0x18];
1135 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1136 u8 reserved_at_21[0xf];
1137 u8 destination_eswitch_owner_vhca_id[0x10];
1140 struct mlx5_ifc_flow_counter_list_bits {
1141 u8 flow_counter_id[0x20];
1143 u8 reserved_at_20[0x20];
1146 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1147 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1148 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1149 u8 reserved_at_0[0x40];
1152 struct mlx5_ifc_fte_match_param_bits {
1153 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1155 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1157 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1159 u8 reserved_at_600[0xa00];
1163 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1164 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1165 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1166 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1167 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1170 struct mlx5_ifc_rx_hash_field_select_bits {
1171 u8 l3_prot_type[0x1];
1172 u8 l4_prot_type[0x1];
1173 u8 selected_fields[0x1e];
1177 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1178 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1182 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1183 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1186 struct mlx5_ifc_wq_bits {
1188 u8 wq_signature[0x1];
1189 u8 end_padding_mode[0x2];
1191 u8 reserved_at_8[0x18];
1193 u8 hds_skip_first_sge[0x1];
1194 u8 log2_hds_buf_size[0x3];
1195 u8 reserved_at_24[0x7];
1196 u8 page_offset[0x5];
1199 u8 reserved_at_40[0x8];
1202 u8 reserved_at_60[0x8];
1207 u8 hw_counter[0x20];
1209 u8 sw_counter[0x20];
1211 u8 reserved_at_100[0xc];
1212 u8 log_wq_stride[0x4];
1213 u8 reserved_at_110[0x3];
1214 u8 log_wq_pg_sz[0x5];
1215 u8 reserved_at_118[0x3];
1218 u8 reserved_at_120[0x3];
1219 u8 log_hairpin_num_packets[0x5];
1220 u8 reserved_at_128[0x3];
1221 u8 log_hairpin_data_sz[0x5];
1223 u8 reserved_at_130[0x4];
1224 u8 log_wqe_num_of_strides[0x4];
1225 u8 two_byte_shift_en[0x1];
1226 u8 reserved_at_139[0x4];
1227 u8 log_wqe_stride_size[0x3];
1229 u8 reserved_at_140[0x4c0];
1231 struct mlx5_ifc_cmd_pas_bits pas[0];
1234 struct mlx5_ifc_rq_num_bits {
1235 u8 reserved_at_0[0x8];
1239 struct mlx5_ifc_mac_address_layout_bits {
1240 u8 reserved_at_0[0x10];
1241 u8 mac_addr_47_32[0x10];
1243 u8 mac_addr_31_0[0x20];
1246 struct mlx5_ifc_vlan_layout_bits {
1247 u8 reserved_at_0[0x14];
1250 u8 reserved_at_20[0x20];
1253 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1254 u8 reserved_at_0[0xa0];
1256 u8 min_time_between_cnps[0x20];
1258 u8 reserved_at_c0[0x12];
1260 u8 reserved_at_d8[0x4];
1261 u8 cnp_prio_mode[0x1];
1262 u8 cnp_802p_prio[0x3];
1264 u8 reserved_at_e0[0x720];
1267 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1268 u8 reserved_at_0[0x60];
1270 u8 reserved_at_60[0x4];
1271 u8 clamp_tgt_rate[0x1];
1272 u8 reserved_at_65[0x3];
1273 u8 clamp_tgt_rate_after_time_inc[0x1];
1274 u8 reserved_at_69[0x17];
1276 u8 reserved_at_80[0x20];
1278 u8 rpg_time_reset[0x20];
1280 u8 rpg_byte_reset[0x20];
1282 u8 rpg_threshold[0x20];
1284 u8 rpg_max_rate[0x20];
1286 u8 rpg_ai_rate[0x20];
1288 u8 rpg_hai_rate[0x20];
1292 u8 rpg_min_dec_fac[0x20];
1294 u8 rpg_min_rate[0x20];
1296 u8 reserved_at_1c0[0xe0];
1298 u8 rate_to_set_on_first_cnp[0x20];
1302 u8 dce_tcp_rtt[0x20];
1304 u8 rate_reduce_monitor_period[0x20];
1306 u8 reserved_at_320[0x20];
1308 u8 initial_alpha_value[0x20];
1310 u8 reserved_at_360[0x4a0];
1313 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1314 u8 reserved_at_0[0x80];
1316 u8 rppp_max_rps[0x20];
1318 u8 rpg_time_reset[0x20];
1320 u8 rpg_byte_reset[0x20];
1322 u8 rpg_threshold[0x20];
1324 u8 rpg_max_rate[0x20];
1326 u8 rpg_ai_rate[0x20];
1328 u8 rpg_hai_rate[0x20];
1332 u8 rpg_min_dec_fac[0x20];
1334 u8 rpg_min_rate[0x20];
1336 u8 reserved_at_1c0[0x640];
1340 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1341 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1342 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1345 struct mlx5_ifc_resize_field_select_bits {
1346 u8 resize_field_select[0x20];
1350 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1351 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1352 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1353 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1356 struct mlx5_ifc_modify_field_select_bits {
1357 u8 modify_field_select[0x20];
1360 struct mlx5_ifc_field_select_r_roce_np_bits {
1361 u8 field_select_r_roce_np[0x20];
1364 struct mlx5_ifc_field_select_r_roce_rp_bits {
1365 u8 field_select_r_roce_rp[0x20];
1369 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1370 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1371 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1377 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1378 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1381 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1382 u8 field_select_8021qaurp[0x20];
1385 struct mlx5_ifc_phys_layer_cntrs_bits {
1386 u8 time_since_last_clear_high[0x20];
1388 u8 time_since_last_clear_low[0x20];
1390 u8 symbol_errors_high[0x20];
1392 u8 symbol_errors_low[0x20];
1394 u8 sync_headers_errors_high[0x20];
1396 u8 sync_headers_errors_low[0x20];
1398 u8 edpl_bip_errors_lane0_high[0x20];
1400 u8 edpl_bip_errors_lane0_low[0x20];
1402 u8 edpl_bip_errors_lane1_high[0x20];
1404 u8 edpl_bip_errors_lane1_low[0x20];
1406 u8 edpl_bip_errors_lane2_high[0x20];
1408 u8 edpl_bip_errors_lane2_low[0x20];
1410 u8 edpl_bip_errors_lane3_high[0x20];
1412 u8 edpl_bip_errors_lane3_low[0x20];
1414 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1416 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1418 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1420 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1422 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1424 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1426 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1428 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1430 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1432 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1434 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1436 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1438 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1440 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1442 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1444 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1446 u8 rs_fec_corrected_blocks_high[0x20];
1448 u8 rs_fec_corrected_blocks_low[0x20];
1450 u8 rs_fec_uncorrectable_blocks_high[0x20];
1452 u8 rs_fec_uncorrectable_blocks_low[0x20];
1454 u8 rs_fec_no_errors_blocks_high[0x20];
1456 u8 rs_fec_no_errors_blocks_low[0x20];
1458 u8 rs_fec_single_error_blocks_high[0x20];
1460 u8 rs_fec_single_error_blocks_low[0x20];
1462 u8 rs_fec_corrected_symbols_total_high[0x20];
1464 u8 rs_fec_corrected_symbols_total_low[0x20];
1466 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1468 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1470 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1472 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1474 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1476 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1478 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1480 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1482 u8 link_down_events[0x20];
1484 u8 successful_recovery_events[0x20];
1486 u8 reserved_at_640[0x180];
1489 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1490 u8 time_since_last_clear_high[0x20];
1492 u8 time_since_last_clear_low[0x20];
1494 u8 phy_received_bits_high[0x20];
1496 u8 phy_received_bits_low[0x20];
1498 u8 phy_symbol_errors_high[0x20];
1500 u8 phy_symbol_errors_low[0x20];
1502 u8 phy_corrected_bits_high[0x20];
1504 u8 phy_corrected_bits_low[0x20];
1506 u8 phy_corrected_bits_lane0_high[0x20];
1508 u8 phy_corrected_bits_lane0_low[0x20];
1510 u8 phy_corrected_bits_lane1_high[0x20];
1512 u8 phy_corrected_bits_lane1_low[0x20];
1514 u8 phy_corrected_bits_lane2_high[0x20];
1516 u8 phy_corrected_bits_lane2_low[0x20];
1518 u8 phy_corrected_bits_lane3_high[0x20];
1520 u8 phy_corrected_bits_lane3_low[0x20];
1522 u8 reserved_at_200[0x5c0];
1525 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1526 u8 symbol_error_counter[0x10];
1528 u8 link_error_recovery_counter[0x8];
1530 u8 link_downed_counter[0x8];
1532 u8 port_rcv_errors[0x10];
1534 u8 port_rcv_remote_physical_errors[0x10];
1536 u8 port_rcv_switch_relay_errors[0x10];
1538 u8 port_xmit_discards[0x10];
1540 u8 port_xmit_constraint_errors[0x8];
1542 u8 port_rcv_constraint_errors[0x8];
1544 u8 reserved_at_70[0x8];
1546 u8 link_overrun_errors[0x8];
1548 u8 reserved_at_80[0x10];
1550 u8 vl_15_dropped[0x10];
1552 u8 reserved_at_a0[0x80];
1554 u8 port_xmit_wait[0x20];
1557 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1558 u8 transmit_queue_high[0x20];
1560 u8 transmit_queue_low[0x20];
1562 u8 reserved_at_40[0x780];
1565 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1566 u8 rx_octets_high[0x20];
1568 u8 rx_octets_low[0x20];
1570 u8 reserved_at_40[0xc0];
1572 u8 rx_frames_high[0x20];
1574 u8 rx_frames_low[0x20];
1576 u8 tx_octets_high[0x20];
1578 u8 tx_octets_low[0x20];
1580 u8 reserved_at_180[0xc0];
1582 u8 tx_frames_high[0x20];
1584 u8 tx_frames_low[0x20];
1586 u8 rx_pause_high[0x20];
1588 u8 rx_pause_low[0x20];
1590 u8 rx_pause_duration_high[0x20];
1592 u8 rx_pause_duration_low[0x20];
1594 u8 tx_pause_high[0x20];
1596 u8 tx_pause_low[0x20];
1598 u8 tx_pause_duration_high[0x20];
1600 u8 tx_pause_duration_low[0x20];
1602 u8 rx_pause_transition_high[0x20];
1604 u8 rx_pause_transition_low[0x20];
1606 u8 reserved_at_3c0[0x40];
1608 u8 device_stall_minor_watermark_cnt_high[0x20];
1610 u8 device_stall_minor_watermark_cnt_low[0x20];
1612 u8 device_stall_critical_watermark_cnt_high[0x20];
1614 u8 device_stall_critical_watermark_cnt_low[0x20];
1616 u8 reserved_at_480[0x340];
1619 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1620 u8 port_transmit_wait_high[0x20];
1622 u8 port_transmit_wait_low[0x20];
1624 u8 reserved_at_40[0x100];
1626 u8 rx_buffer_almost_full_high[0x20];
1628 u8 rx_buffer_almost_full_low[0x20];
1630 u8 rx_buffer_full_high[0x20];
1632 u8 rx_buffer_full_low[0x20];
1634 u8 reserved_at_1c0[0x600];
1637 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1638 u8 dot3stats_alignment_errors_high[0x20];
1640 u8 dot3stats_alignment_errors_low[0x20];
1642 u8 dot3stats_fcs_errors_high[0x20];
1644 u8 dot3stats_fcs_errors_low[0x20];
1646 u8 dot3stats_single_collision_frames_high[0x20];
1648 u8 dot3stats_single_collision_frames_low[0x20];
1650 u8 dot3stats_multiple_collision_frames_high[0x20];
1652 u8 dot3stats_multiple_collision_frames_low[0x20];
1654 u8 dot3stats_sqe_test_errors_high[0x20];
1656 u8 dot3stats_sqe_test_errors_low[0x20];
1658 u8 dot3stats_deferred_transmissions_high[0x20];
1660 u8 dot3stats_deferred_transmissions_low[0x20];
1662 u8 dot3stats_late_collisions_high[0x20];
1664 u8 dot3stats_late_collisions_low[0x20];
1666 u8 dot3stats_excessive_collisions_high[0x20];
1668 u8 dot3stats_excessive_collisions_low[0x20];
1670 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1672 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1674 u8 dot3stats_carrier_sense_errors_high[0x20];
1676 u8 dot3stats_carrier_sense_errors_low[0x20];
1678 u8 dot3stats_frame_too_longs_high[0x20];
1680 u8 dot3stats_frame_too_longs_low[0x20];
1682 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1684 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1686 u8 dot3stats_symbol_errors_high[0x20];
1688 u8 dot3stats_symbol_errors_low[0x20];
1690 u8 dot3control_in_unknown_opcodes_high[0x20];
1692 u8 dot3control_in_unknown_opcodes_low[0x20];
1694 u8 dot3in_pause_frames_high[0x20];
1696 u8 dot3in_pause_frames_low[0x20];
1698 u8 dot3out_pause_frames_high[0x20];
1700 u8 dot3out_pause_frames_low[0x20];
1702 u8 reserved_at_400[0x3c0];
1705 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1706 u8 ether_stats_drop_events_high[0x20];
1708 u8 ether_stats_drop_events_low[0x20];
1710 u8 ether_stats_octets_high[0x20];
1712 u8 ether_stats_octets_low[0x20];
1714 u8 ether_stats_pkts_high[0x20];
1716 u8 ether_stats_pkts_low[0x20];
1718 u8 ether_stats_broadcast_pkts_high[0x20];
1720 u8 ether_stats_broadcast_pkts_low[0x20];
1722 u8 ether_stats_multicast_pkts_high[0x20];
1724 u8 ether_stats_multicast_pkts_low[0x20];
1726 u8 ether_stats_crc_align_errors_high[0x20];
1728 u8 ether_stats_crc_align_errors_low[0x20];
1730 u8 ether_stats_undersize_pkts_high[0x20];
1732 u8 ether_stats_undersize_pkts_low[0x20];
1734 u8 ether_stats_oversize_pkts_high[0x20];
1736 u8 ether_stats_oversize_pkts_low[0x20];
1738 u8 ether_stats_fragments_high[0x20];
1740 u8 ether_stats_fragments_low[0x20];
1742 u8 ether_stats_jabbers_high[0x20];
1744 u8 ether_stats_jabbers_low[0x20];
1746 u8 ether_stats_collisions_high[0x20];
1748 u8 ether_stats_collisions_low[0x20];
1750 u8 ether_stats_pkts64octets_high[0x20];
1752 u8 ether_stats_pkts64octets_low[0x20];
1754 u8 ether_stats_pkts65to127octets_high[0x20];
1756 u8 ether_stats_pkts65to127octets_low[0x20];
1758 u8 ether_stats_pkts128to255octets_high[0x20];
1760 u8 ether_stats_pkts128to255octets_low[0x20];
1762 u8 ether_stats_pkts256to511octets_high[0x20];
1764 u8 ether_stats_pkts256to511octets_low[0x20];
1766 u8 ether_stats_pkts512to1023octets_high[0x20];
1768 u8 ether_stats_pkts512to1023octets_low[0x20];
1770 u8 ether_stats_pkts1024to1518octets_high[0x20];
1772 u8 ether_stats_pkts1024to1518octets_low[0x20];
1774 u8 ether_stats_pkts1519to2047octets_high[0x20];
1776 u8 ether_stats_pkts1519to2047octets_low[0x20];
1778 u8 ether_stats_pkts2048to4095octets_high[0x20];
1780 u8 ether_stats_pkts2048to4095octets_low[0x20];
1782 u8 ether_stats_pkts4096to8191octets_high[0x20];
1784 u8 ether_stats_pkts4096to8191octets_low[0x20];
1786 u8 ether_stats_pkts8192to10239octets_high[0x20];
1788 u8 ether_stats_pkts8192to10239octets_low[0x20];
1790 u8 reserved_at_540[0x280];
1793 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1794 u8 if_in_octets_high[0x20];
1796 u8 if_in_octets_low[0x20];
1798 u8 if_in_ucast_pkts_high[0x20];
1800 u8 if_in_ucast_pkts_low[0x20];
1802 u8 if_in_discards_high[0x20];
1804 u8 if_in_discards_low[0x20];
1806 u8 if_in_errors_high[0x20];
1808 u8 if_in_errors_low[0x20];
1810 u8 if_in_unknown_protos_high[0x20];
1812 u8 if_in_unknown_protos_low[0x20];
1814 u8 if_out_octets_high[0x20];
1816 u8 if_out_octets_low[0x20];
1818 u8 if_out_ucast_pkts_high[0x20];
1820 u8 if_out_ucast_pkts_low[0x20];
1822 u8 if_out_discards_high[0x20];
1824 u8 if_out_discards_low[0x20];
1826 u8 if_out_errors_high[0x20];
1828 u8 if_out_errors_low[0x20];
1830 u8 if_in_multicast_pkts_high[0x20];
1832 u8 if_in_multicast_pkts_low[0x20];
1834 u8 if_in_broadcast_pkts_high[0x20];
1836 u8 if_in_broadcast_pkts_low[0x20];
1838 u8 if_out_multicast_pkts_high[0x20];
1840 u8 if_out_multicast_pkts_low[0x20];
1842 u8 if_out_broadcast_pkts_high[0x20];
1844 u8 if_out_broadcast_pkts_low[0x20];
1846 u8 reserved_at_340[0x480];
1849 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1850 u8 a_frames_transmitted_ok_high[0x20];
1852 u8 a_frames_transmitted_ok_low[0x20];
1854 u8 a_frames_received_ok_high[0x20];
1856 u8 a_frames_received_ok_low[0x20];
1858 u8 a_frame_check_sequence_errors_high[0x20];
1860 u8 a_frame_check_sequence_errors_low[0x20];
1862 u8 a_alignment_errors_high[0x20];
1864 u8 a_alignment_errors_low[0x20];
1866 u8 a_octets_transmitted_ok_high[0x20];
1868 u8 a_octets_transmitted_ok_low[0x20];
1870 u8 a_octets_received_ok_high[0x20];
1872 u8 a_octets_received_ok_low[0x20];
1874 u8 a_multicast_frames_xmitted_ok_high[0x20];
1876 u8 a_multicast_frames_xmitted_ok_low[0x20];
1878 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1880 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1882 u8 a_multicast_frames_received_ok_high[0x20];
1884 u8 a_multicast_frames_received_ok_low[0x20];
1886 u8 a_broadcast_frames_received_ok_high[0x20];
1888 u8 a_broadcast_frames_received_ok_low[0x20];
1890 u8 a_in_range_length_errors_high[0x20];
1892 u8 a_in_range_length_errors_low[0x20];
1894 u8 a_out_of_range_length_field_high[0x20];
1896 u8 a_out_of_range_length_field_low[0x20];
1898 u8 a_frame_too_long_errors_high[0x20];
1900 u8 a_frame_too_long_errors_low[0x20];
1902 u8 a_symbol_error_during_carrier_high[0x20];
1904 u8 a_symbol_error_during_carrier_low[0x20];
1906 u8 a_mac_control_frames_transmitted_high[0x20];
1908 u8 a_mac_control_frames_transmitted_low[0x20];
1910 u8 a_mac_control_frames_received_high[0x20];
1912 u8 a_mac_control_frames_received_low[0x20];
1914 u8 a_unsupported_opcodes_received_high[0x20];
1916 u8 a_unsupported_opcodes_received_low[0x20];
1918 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1920 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1922 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1924 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1926 u8 reserved_at_4c0[0x300];
1929 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1930 u8 life_time_counter_high[0x20];
1932 u8 life_time_counter_low[0x20];
1938 u8 l0_to_recovery_eieos[0x20];
1940 u8 l0_to_recovery_ts[0x20];
1942 u8 l0_to_recovery_framing[0x20];
1944 u8 l0_to_recovery_retrain[0x20];
1946 u8 crc_error_dllp[0x20];
1948 u8 crc_error_tlp[0x20];
1950 u8 tx_overflow_buffer_pkt_high[0x20];
1952 u8 tx_overflow_buffer_pkt_low[0x20];
1954 u8 outbound_stalled_reads[0x20];
1956 u8 outbound_stalled_writes[0x20];
1958 u8 outbound_stalled_reads_events[0x20];
1960 u8 outbound_stalled_writes_events[0x20];
1962 u8 reserved_at_200[0x5c0];
1965 struct mlx5_ifc_cmd_inter_comp_event_bits {
1966 u8 command_completion_vector[0x20];
1968 u8 reserved_at_20[0xc0];
1971 struct mlx5_ifc_stall_vl_event_bits {
1972 u8 reserved_at_0[0x18];
1974 u8 reserved_at_19[0x3];
1977 u8 reserved_at_20[0xa0];
1980 struct mlx5_ifc_db_bf_congestion_event_bits {
1981 u8 event_subtype[0x8];
1982 u8 reserved_at_8[0x8];
1983 u8 congestion_level[0x8];
1984 u8 reserved_at_18[0x8];
1986 u8 reserved_at_20[0xa0];
1989 struct mlx5_ifc_gpio_event_bits {
1990 u8 reserved_at_0[0x60];
1992 u8 gpio_event_hi[0x20];
1994 u8 gpio_event_lo[0x20];
1996 u8 reserved_at_a0[0x40];
1999 struct mlx5_ifc_port_state_change_event_bits {
2000 u8 reserved_at_0[0x40];
2003 u8 reserved_at_44[0x1c];
2005 u8 reserved_at_60[0x80];
2008 struct mlx5_ifc_dropped_packet_logged_bits {
2009 u8 reserved_at_0[0xe0];
2013 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2014 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2017 struct mlx5_ifc_cq_error_bits {
2018 u8 reserved_at_0[0x8];
2021 u8 reserved_at_20[0x20];
2023 u8 reserved_at_40[0x18];
2026 u8 reserved_at_60[0x80];
2029 struct mlx5_ifc_rdma_page_fault_event_bits {
2030 u8 bytes_committed[0x20];
2034 u8 reserved_at_40[0x10];
2035 u8 packet_len[0x10];
2037 u8 rdma_op_len[0x20];
2041 u8 reserved_at_c0[0x5];
2048 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2049 u8 bytes_committed[0x20];
2051 u8 reserved_at_20[0x10];
2054 u8 reserved_at_40[0x10];
2057 u8 reserved_at_60[0x60];
2059 u8 reserved_at_c0[0x5];
2066 struct mlx5_ifc_qp_events_bits {
2067 u8 reserved_at_0[0xa0];
2070 u8 reserved_at_a8[0x18];
2072 u8 reserved_at_c0[0x8];
2073 u8 qpn_rqn_sqn[0x18];
2076 struct mlx5_ifc_dct_events_bits {
2077 u8 reserved_at_0[0xc0];
2079 u8 reserved_at_c0[0x8];
2080 u8 dct_number[0x18];
2083 struct mlx5_ifc_comp_event_bits {
2084 u8 reserved_at_0[0xc0];
2086 u8 reserved_at_c0[0x8];
2091 MLX5_QPC_STATE_RST = 0x0,
2092 MLX5_QPC_STATE_INIT = 0x1,
2093 MLX5_QPC_STATE_RTR = 0x2,
2094 MLX5_QPC_STATE_RTS = 0x3,
2095 MLX5_QPC_STATE_SQER = 0x4,
2096 MLX5_QPC_STATE_ERR = 0x6,
2097 MLX5_QPC_STATE_SQD = 0x7,
2098 MLX5_QPC_STATE_SUSPENDED = 0x9,
2102 MLX5_QPC_ST_RC = 0x0,
2103 MLX5_QPC_ST_UC = 0x1,
2104 MLX5_QPC_ST_UD = 0x2,
2105 MLX5_QPC_ST_XRC = 0x3,
2106 MLX5_QPC_ST_DCI = 0x5,
2107 MLX5_QPC_ST_QP0 = 0x7,
2108 MLX5_QPC_ST_QP1 = 0x8,
2109 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2110 MLX5_QPC_ST_REG_UMR = 0xc,
2114 MLX5_QPC_PM_STATE_ARMED = 0x0,
2115 MLX5_QPC_PM_STATE_REARM = 0x1,
2116 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2117 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2121 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2125 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2126 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2130 MLX5_QPC_MTU_256_BYTES = 0x1,
2131 MLX5_QPC_MTU_512_BYTES = 0x2,
2132 MLX5_QPC_MTU_1K_BYTES = 0x3,
2133 MLX5_QPC_MTU_2K_BYTES = 0x4,
2134 MLX5_QPC_MTU_4K_BYTES = 0x5,
2135 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2139 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2140 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2141 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2142 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2143 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2144 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2145 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2146 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2150 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2151 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2152 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2156 MLX5_QPC_CS_RES_DISABLE = 0x0,
2157 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2158 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2161 struct mlx5_ifc_qpc_bits {
2163 u8 lag_tx_port_affinity[0x4];
2165 u8 reserved_at_10[0x3];
2167 u8 reserved_at_15[0x3];
2168 u8 offload_type[0x4];
2169 u8 end_padding_mode[0x2];
2170 u8 reserved_at_1e[0x2];
2172 u8 wq_signature[0x1];
2173 u8 block_lb_mc[0x1];
2174 u8 atomic_like_write_en[0x1];
2175 u8 latency_sensitive[0x1];
2176 u8 reserved_at_24[0x1];
2177 u8 drain_sigerr[0x1];
2178 u8 reserved_at_26[0x2];
2182 u8 log_msg_max[0x5];
2183 u8 reserved_at_48[0x1];
2184 u8 log_rq_size[0x4];
2185 u8 log_rq_stride[0x3];
2187 u8 log_sq_size[0x4];
2188 u8 reserved_at_55[0x6];
2190 u8 ulp_stateless_offload_mode[0x4];
2192 u8 counter_set_id[0x8];
2195 u8 reserved_at_80[0x8];
2196 u8 user_index[0x18];
2198 u8 reserved_at_a0[0x3];
2199 u8 log_page_size[0x5];
2200 u8 remote_qpn[0x18];
2202 struct mlx5_ifc_ads_bits primary_address_path;
2204 struct mlx5_ifc_ads_bits secondary_address_path;
2206 u8 log_ack_req_freq[0x4];
2207 u8 reserved_at_384[0x4];
2208 u8 log_sra_max[0x3];
2209 u8 reserved_at_38b[0x2];
2210 u8 retry_count[0x3];
2212 u8 reserved_at_393[0x1];
2214 u8 cur_rnr_retry[0x3];
2215 u8 cur_retry_count[0x3];
2216 u8 reserved_at_39b[0x5];
2218 u8 reserved_at_3a0[0x20];
2220 u8 reserved_at_3c0[0x8];
2221 u8 next_send_psn[0x18];
2223 u8 reserved_at_3e0[0x8];
2226 u8 reserved_at_400[0x8];
2229 u8 reserved_at_420[0x20];
2231 u8 reserved_at_440[0x8];
2232 u8 last_acked_psn[0x18];
2234 u8 reserved_at_460[0x8];
2237 u8 reserved_at_480[0x8];
2238 u8 log_rra_max[0x3];
2239 u8 reserved_at_48b[0x1];
2240 u8 atomic_mode[0x4];
2244 u8 reserved_at_493[0x1];
2245 u8 page_offset[0x6];
2246 u8 reserved_at_49a[0x3];
2247 u8 cd_slave_receive[0x1];
2248 u8 cd_slave_send[0x1];
2251 u8 reserved_at_4a0[0x3];
2252 u8 min_rnr_nak[0x5];
2253 u8 next_rcv_psn[0x18];
2255 u8 reserved_at_4c0[0x8];
2258 u8 reserved_at_4e0[0x8];
2265 u8 reserved_at_560[0x5];
2267 u8 srqn_rmpn_xrqn[0x18];
2269 u8 reserved_at_580[0x8];
2272 u8 hw_sq_wqebb_counter[0x10];
2273 u8 sw_sq_wqebb_counter[0x10];
2275 u8 hw_rq_counter[0x20];
2277 u8 sw_rq_counter[0x20];
2279 u8 reserved_at_600[0x20];
2281 u8 reserved_at_620[0xf];
2286 u8 dc_access_key[0x40];
2288 u8 reserved_at_680[0xc0];
2291 struct mlx5_ifc_roce_addr_layout_bits {
2292 u8 source_l3_address[16][0x8];
2294 u8 reserved_at_80[0x3];
2297 u8 source_mac_47_32[0x10];
2299 u8 source_mac_31_0[0x20];
2301 u8 reserved_at_c0[0x14];
2302 u8 roce_l3_type[0x4];
2303 u8 roce_version[0x8];
2305 u8 reserved_at_e0[0x20];
2308 union mlx5_ifc_hca_cap_union_bits {
2309 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2310 struct mlx5_ifc_odp_cap_bits odp_cap;
2311 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2312 struct mlx5_ifc_roce_cap_bits roce_cap;
2313 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2314 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2315 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2316 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2317 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2318 struct mlx5_ifc_qos_cap_bits qos_cap;
2319 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2320 u8 reserved_at_0[0x8000];
2324 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2325 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2326 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2327 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2328 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2329 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2330 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2331 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2332 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2335 struct mlx5_ifc_vlan_bits {
2342 struct mlx5_ifc_flow_context_bits {
2343 struct mlx5_ifc_vlan_bits push_vlan;
2347 u8 reserved_at_40[0x8];
2350 u8 reserved_at_60[0x10];
2353 u8 reserved_at_80[0x8];
2354 u8 destination_list_size[0x18];
2356 u8 reserved_at_a0[0x8];
2357 u8 flow_counter_list_size[0x18];
2361 u8 modify_header_id[0x20];
2363 u8 reserved_at_100[0x100];
2365 struct mlx5_ifc_fte_match_param_bits match_value;
2367 u8 reserved_at_1200[0x600];
2369 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2373 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2374 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2377 struct mlx5_ifc_xrc_srqc_bits {
2379 u8 log_xrc_srq_size[0x4];
2380 u8 reserved_at_8[0x18];
2382 u8 wq_signature[0x1];
2384 u8 reserved_at_22[0x1];
2386 u8 basic_cyclic_rcv_wqe[0x1];
2387 u8 log_rq_stride[0x3];
2390 u8 page_offset[0x6];
2391 u8 reserved_at_46[0x2];
2394 u8 reserved_at_60[0x20];
2396 u8 user_index_equal_xrc_srqn[0x1];
2397 u8 reserved_at_81[0x1];
2398 u8 log_page_size[0x6];
2399 u8 user_index[0x18];
2401 u8 reserved_at_a0[0x20];
2403 u8 reserved_at_c0[0x8];
2409 u8 reserved_at_100[0x40];
2411 u8 db_record_addr_h[0x20];
2413 u8 db_record_addr_l[0x1e];
2414 u8 reserved_at_17e[0x2];
2416 u8 reserved_at_180[0x80];
2419 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2420 u8 counter_error_queues[0x20];
2422 u8 total_error_queues[0x20];
2424 u8 send_queue_priority_update_flow[0x20];
2426 u8 reserved_at_60[0x20];
2428 u8 nic_receive_steering_discard[0x40];
2430 u8 receive_discard_vport_down[0x40];
2432 u8 transmit_discard_vport_down[0x40];
2434 u8 reserved_at_140[0xec0];
2437 struct mlx5_ifc_traffic_counter_bits {
2443 struct mlx5_ifc_tisc_bits {
2444 u8 strict_lag_tx_port_affinity[0x1];
2445 u8 reserved_at_1[0x3];
2446 u8 lag_tx_port_affinity[0x04];
2448 u8 reserved_at_8[0x4];
2450 u8 reserved_at_10[0x10];
2452 u8 reserved_at_20[0x100];
2454 u8 reserved_at_120[0x8];
2455 u8 transport_domain[0x18];
2457 u8 reserved_at_140[0x8];
2458 u8 underlay_qpn[0x18];
2459 u8 reserved_at_160[0x3a0];
2463 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2464 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2468 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2469 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2473 MLX5_RX_HASH_FN_NONE = 0x0,
2474 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2475 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2479 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2480 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2483 struct mlx5_ifc_tirc_bits {
2484 u8 reserved_at_0[0x20];
2487 u8 reserved_at_24[0x1c];
2489 u8 reserved_at_40[0x40];
2491 u8 reserved_at_80[0x4];
2492 u8 lro_timeout_period_usecs[0x10];
2493 u8 lro_enable_mask[0x4];
2494 u8 lro_max_ip_payload_size[0x8];
2496 u8 reserved_at_a0[0x40];
2498 u8 reserved_at_e0[0x8];
2499 u8 inline_rqn[0x18];
2501 u8 rx_hash_symmetric[0x1];
2502 u8 reserved_at_101[0x1];
2503 u8 tunneled_offload_en[0x1];
2504 u8 reserved_at_103[0x5];
2505 u8 indirect_table[0x18];
2508 u8 reserved_at_124[0x2];
2509 u8 self_lb_block[0x2];
2510 u8 transport_domain[0x18];
2512 u8 rx_hash_toeplitz_key[10][0x20];
2514 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2516 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2518 u8 reserved_at_2c0[0x4c0];
2522 MLX5_SRQC_STATE_GOOD = 0x0,
2523 MLX5_SRQC_STATE_ERROR = 0x1,
2526 struct mlx5_ifc_srqc_bits {
2528 u8 log_srq_size[0x4];
2529 u8 reserved_at_8[0x18];
2531 u8 wq_signature[0x1];
2533 u8 reserved_at_22[0x1];
2535 u8 reserved_at_24[0x1];
2536 u8 log_rq_stride[0x3];
2539 u8 page_offset[0x6];
2540 u8 reserved_at_46[0x2];
2543 u8 reserved_at_60[0x20];
2545 u8 reserved_at_80[0x2];
2546 u8 log_page_size[0x6];
2547 u8 reserved_at_88[0x18];
2549 u8 reserved_at_a0[0x20];
2551 u8 reserved_at_c0[0x8];
2557 u8 reserved_at_100[0x40];
2561 u8 reserved_at_180[0x80];
2565 MLX5_SQC_STATE_RST = 0x0,
2566 MLX5_SQC_STATE_RDY = 0x1,
2567 MLX5_SQC_STATE_ERR = 0x3,
2570 struct mlx5_ifc_sqc_bits {
2574 u8 flush_in_error_en[0x1];
2575 u8 allow_multi_pkt_send_wqe[0x1];
2576 u8 min_wqe_inline_mode[0x3];
2581 u8 reserved_at_f[0x11];
2583 u8 reserved_at_20[0x8];
2584 u8 user_index[0x18];
2586 u8 reserved_at_40[0x8];
2589 u8 reserved_at_60[0x8];
2590 u8 hairpin_peer_rq[0x18];
2592 u8 reserved_at_80[0x10];
2593 u8 hairpin_peer_vhca[0x10];
2595 u8 reserved_at_a0[0x50];
2597 u8 packet_pacing_rate_limit_index[0x10];
2598 u8 tis_lst_sz[0x10];
2599 u8 reserved_at_110[0x10];
2601 u8 reserved_at_120[0x40];
2603 u8 reserved_at_160[0x8];
2606 struct mlx5_ifc_wq_bits wq;
2610 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2611 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2612 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2613 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2616 struct mlx5_ifc_scheduling_context_bits {
2617 u8 element_type[0x8];
2618 u8 reserved_at_8[0x18];
2620 u8 element_attributes[0x20];
2622 u8 parent_element_id[0x20];
2624 u8 reserved_at_60[0x40];
2628 u8 max_average_bw[0x20];
2630 u8 reserved_at_e0[0x120];
2633 struct mlx5_ifc_rqtc_bits {
2634 u8 reserved_at_0[0xa0];
2636 u8 reserved_at_a0[0x10];
2637 u8 rqt_max_size[0x10];
2639 u8 reserved_at_c0[0x10];
2640 u8 rqt_actual_size[0x10];
2642 u8 reserved_at_e0[0x6a0];
2644 struct mlx5_ifc_rq_num_bits rq_num[0];
2648 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2649 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2653 MLX5_RQC_STATE_RST = 0x0,
2654 MLX5_RQC_STATE_RDY = 0x1,
2655 MLX5_RQC_STATE_ERR = 0x3,
2658 struct mlx5_ifc_rqc_bits {
2660 u8 delay_drop_en[0x1];
2661 u8 scatter_fcs[0x1];
2663 u8 mem_rq_type[0x4];
2665 u8 reserved_at_c[0x1];
2666 u8 flush_in_error_en[0x1];
2668 u8 reserved_at_f[0x11];
2670 u8 reserved_at_20[0x8];
2671 u8 user_index[0x18];
2673 u8 reserved_at_40[0x8];
2676 u8 counter_set_id[0x8];
2677 u8 reserved_at_68[0x18];
2679 u8 reserved_at_80[0x8];
2682 u8 reserved_at_a0[0x8];
2683 u8 hairpin_peer_sq[0x18];
2685 u8 reserved_at_c0[0x10];
2686 u8 hairpin_peer_vhca[0x10];
2688 u8 reserved_at_e0[0xa0];
2690 struct mlx5_ifc_wq_bits wq;
2694 MLX5_RMPC_STATE_RDY = 0x1,
2695 MLX5_RMPC_STATE_ERR = 0x3,
2698 struct mlx5_ifc_rmpc_bits {
2699 u8 reserved_at_0[0x8];
2701 u8 reserved_at_c[0x14];
2703 u8 basic_cyclic_rcv_wqe[0x1];
2704 u8 reserved_at_21[0x1f];
2706 u8 reserved_at_40[0x140];
2708 struct mlx5_ifc_wq_bits wq;
2711 struct mlx5_ifc_nic_vport_context_bits {
2712 u8 reserved_at_0[0x5];
2713 u8 min_wqe_inline_mode[0x3];
2714 u8 reserved_at_8[0x15];
2715 u8 disable_mc_local_lb[0x1];
2716 u8 disable_uc_local_lb[0x1];
2719 u8 arm_change_event[0x1];
2720 u8 reserved_at_21[0x1a];
2721 u8 event_on_mtu[0x1];
2722 u8 event_on_promisc_change[0x1];
2723 u8 event_on_vlan_change[0x1];
2724 u8 event_on_mc_address_change[0x1];
2725 u8 event_on_uc_address_change[0x1];
2727 u8 reserved_at_40[0xc];
2729 u8 affiliation_criteria[0x4];
2730 u8 affiliated_vhca_id[0x10];
2732 u8 reserved_at_60[0xd0];
2736 u8 system_image_guid[0x40];
2740 u8 reserved_at_200[0x140];
2741 u8 qkey_violation_counter[0x10];
2742 u8 reserved_at_350[0x430];
2746 u8 promisc_all[0x1];
2747 u8 reserved_at_783[0x2];
2748 u8 allowed_list_type[0x3];
2749 u8 reserved_at_788[0xc];
2750 u8 allowed_list_size[0xc];
2752 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2754 u8 reserved_at_7e0[0x20];
2756 u8 current_uc_mac_address[0][0x40];
2760 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2761 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2762 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2763 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2764 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2767 struct mlx5_ifc_mkc_bits {
2768 u8 reserved_at_0[0x1];
2770 u8 reserved_at_2[0x1];
2771 u8 access_mode_4_2[0x3];
2772 u8 reserved_at_6[0x7];
2773 u8 relaxed_ordering_write[0x1];
2774 u8 reserved_at_e[0x1];
2775 u8 small_fence_on_rdma_read_response[0x1];
2782 u8 access_mode_1_0[0x2];
2783 u8 reserved_at_18[0x8];
2788 u8 reserved_at_40[0x20];
2793 u8 reserved_at_63[0x2];
2794 u8 expected_sigerr_count[0x1];
2795 u8 reserved_at_66[0x1];
2799 u8 start_addr[0x40];
2803 u8 bsf_octword_size[0x20];
2805 u8 reserved_at_120[0x80];
2807 u8 translations_octword_size[0x20];
2809 u8 reserved_at_1c0[0x1b];
2810 u8 log_page_size[0x5];
2812 u8 reserved_at_1e0[0x20];
2815 struct mlx5_ifc_pkey_bits {
2816 u8 reserved_at_0[0x10];
2820 struct mlx5_ifc_array128_auto_bits {
2821 u8 array128_auto[16][0x8];
2824 struct mlx5_ifc_hca_vport_context_bits {
2825 u8 field_select[0x20];
2827 u8 reserved_at_20[0xe0];
2829 u8 sm_virt_aware[0x1];
2832 u8 grh_required[0x1];
2833 u8 reserved_at_104[0xc];
2834 u8 port_physical_state[0x4];
2835 u8 vport_state_policy[0x4];
2837 u8 vport_state[0x4];
2839 u8 reserved_at_120[0x20];
2841 u8 system_image_guid[0x40];
2849 u8 cap_mask1_field_select[0x20];
2853 u8 cap_mask2_field_select[0x20];
2855 u8 reserved_at_280[0x80];
2858 u8 reserved_at_310[0x4];
2859 u8 init_type_reply[0x4];
2861 u8 subnet_timeout[0x5];
2865 u8 reserved_at_334[0xc];
2867 u8 qkey_violation_counter[0x10];
2868 u8 pkey_violation_counter[0x10];
2870 u8 reserved_at_360[0xca0];
2873 struct mlx5_ifc_esw_vport_context_bits {
2874 u8 reserved_at_0[0x3];
2875 u8 vport_svlan_strip[0x1];
2876 u8 vport_cvlan_strip[0x1];
2877 u8 vport_svlan_insert[0x1];
2878 u8 vport_cvlan_insert[0x2];
2879 u8 reserved_at_8[0x18];
2881 u8 reserved_at_20[0x20];
2890 u8 reserved_at_60[0x7a0];
2894 MLX5_EQC_STATUS_OK = 0x0,
2895 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2899 MLX5_EQC_ST_ARMED = 0x9,
2900 MLX5_EQC_ST_FIRED = 0xa,
2903 struct mlx5_ifc_eqc_bits {
2905 u8 reserved_at_4[0x9];
2908 u8 reserved_at_f[0x5];
2910 u8 reserved_at_18[0x8];
2912 u8 reserved_at_20[0x20];
2914 u8 reserved_at_40[0x14];
2915 u8 page_offset[0x6];
2916 u8 reserved_at_5a[0x6];
2918 u8 reserved_at_60[0x3];
2919 u8 log_eq_size[0x5];
2922 u8 reserved_at_80[0x20];
2924 u8 reserved_at_a0[0x18];
2927 u8 reserved_at_c0[0x3];
2928 u8 log_page_size[0x5];
2929 u8 reserved_at_c8[0x18];
2931 u8 reserved_at_e0[0x60];
2933 u8 reserved_at_140[0x8];
2934 u8 consumer_counter[0x18];
2936 u8 reserved_at_160[0x8];
2937 u8 producer_counter[0x18];
2939 u8 reserved_at_180[0x80];
2943 MLX5_DCTC_STATE_ACTIVE = 0x0,
2944 MLX5_DCTC_STATE_DRAINING = 0x1,
2945 MLX5_DCTC_STATE_DRAINED = 0x2,
2949 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2950 MLX5_DCTC_CS_RES_NA = 0x1,
2951 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2955 MLX5_DCTC_MTU_256_BYTES = 0x1,
2956 MLX5_DCTC_MTU_512_BYTES = 0x2,
2957 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2958 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2959 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2962 struct mlx5_ifc_dctc_bits {
2963 u8 reserved_at_0[0x4];
2965 u8 reserved_at_8[0x18];
2967 u8 reserved_at_20[0x8];
2968 u8 user_index[0x18];
2970 u8 reserved_at_40[0x8];
2973 u8 counter_set_id[0x8];
2974 u8 atomic_mode[0x4];
2978 u8 atomic_like_write_en[0x1];
2979 u8 latency_sensitive[0x1];
2982 u8 reserved_at_73[0xd];
2984 u8 reserved_at_80[0x8];
2986 u8 reserved_at_90[0x3];
2987 u8 min_rnr_nak[0x5];
2988 u8 reserved_at_98[0x8];
2990 u8 reserved_at_a0[0x8];
2993 u8 reserved_at_c0[0x8];
2997 u8 reserved_at_e8[0x4];
2998 u8 flow_label[0x14];
3000 u8 dc_access_key[0x40];
3002 u8 reserved_at_140[0x5];
3005 u8 pkey_index[0x10];
3007 u8 reserved_at_160[0x8];
3008 u8 my_addr_index[0x8];
3009 u8 reserved_at_170[0x8];
3012 u8 dc_access_key_violation_count[0x20];
3014 u8 reserved_at_1a0[0x14];
3020 u8 reserved_at_1c0[0x40];
3024 MLX5_CQC_STATUS_OK = 0x0,
3025 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3026 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3030 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3031 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3035 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3036 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3037 MLX5_CQC_ST_FIRED = 0xa,
3041 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3042 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3043 MLX5_CQ_PERIOD_NUM_MODES
3046 struct mlx5_ifc_cqc_bits {
3048 u8 reserved_at_4[0x4];
3051 u8 reserved_at_c[0x1];
3052 u8 scqe_break_moderation_en[0x1];
3054 u8 cq_period_mode[0x2];
3055 u8 cqe_comp_en[0x1];
3056 u8 mini_cqe_res_format[0x2];
3058 u8 reserved_at_18[0x8];
3060 u8 reserved_at_20[0x20];
3062 u8 reserved_at_40[0x14];
3063 u8 page_offset[0x6];
3064 u8 reserved_at_5a[0x6];
3066 u8 reserved_at_60[0x3];
3067 u8 log_cq_size[0x5];
3070 u8 reserved_at_80[0x4];
3072 u8 cq_max_count[0x10];
3074 u8 reserved_at_a0[0x18];
3077 u8 reserved_at_c0[0x3];
3078 u8 log_page_size[0x5];
3079 u8 reserved_at_c8[0x18];
3081 u8 reserved_at_e0[0x20];
3083 u8 reserved_at_100[0x8];
3084 u8 last_notified_index[0x18];
3086 u8 reserved_at_120[0x8];
3087 u8 last_solicit_index[0x18];
3089 u8 reserved_at_140[0x8];
3090 u8 consumer_counter[0x18];
3092 u8 reserved_at_160[0x8];
3093 u8 producer_counter[0x18];
3095 u8 reserved_at_180[0x40];
3100 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3101 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3102 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3103 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3104 u8 reserved_at_0[0x800];
3107 struct mlx5_ifc_query_adapter_param_block_bits {
3108 u8 reserved_at_0[0xc0];
3110 u8 reserved_at_c0[0x8];
3111 u8 ieee_vendor_id[0x18];
3113 u8 reserved_at_e0[0x10];
3114 u8 vsd_vendor_id[0x10];
3118 u8 vsd_contd_psid[16][0x8];
3122 MLX5_XRQC_STATE_GOOD = 0x0,
3123 MLX5_XRQC_STATE_ERROR = 0x1,
3127 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3128 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3132 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3135 struct mlx5_ifc_tag_matching_topology_context_bits {
3136 u8 log_matching_list_sz[0x4];
3137 u8 reserved_at_4[0xc];
3138 u8 append_next_index[0x10];
3140 u8 sw_phase_cnt[0x10];
3141 u8 hw_phase_cnt[0x10];
3143 u8 reserved_at_40[0x40];
3146 struct mlx5_ifc_xrqc_bits {
3149 u8 reserved_at_5[0xf];
3151 u8 reserved_at_18[0x4];
3154 u8 reserved_at_20[0x8];
3155 u8 user_index[0x18];
3157 u8 reserved_at_40[0x8];
3160 u8 reserved_at_60[0xa0];
3162 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3164 u8 reserved_at_180[0x280];
3166 struct mlx5_ifc_wq_bits wq;
3169 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3170 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3171 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3172 u8 reserved_at_0[0x20];
3175 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3176 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3177 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3178 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3179 u8 reserved_at_0[0x20];
3182 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3183 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3184 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3185 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3186 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3187 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3188 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3189 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3190 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3191 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3192 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3193 u8 reserved_at_0[0x7c0];
3196 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3197 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3198 u8 reserved_at_0[0x7c0];
3201 union mlx5_ifc_event_auto_bits {
3202 struct mlx5_ifc_comp_event_bits comp_event;
3203 struct mlx5_ifc_dct_events_bits dct_events;
3204 struct mlx5_ifc_qp_events_bits qp_events;
3205 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3206 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3207 struct mlx5_ifc_cq_error_bits cq_error;
3208 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3209 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3210 struct mlx5_ifc_gpio_event_bits gpio_event;
3211 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3212 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3213 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3214 u8 reserved_at_0[0xe0];
3217 struct mlx5_ifc_health_buffer_bits {
3218 u8 reserved_at_0[0x100];
3220 u8 assert_existptr[0x20];
3222 u8 assert_callra[0x20];
3224 u8 reserved_at_140[0x40];
3226 u8 fw_version[0x20];
3230 u8 reserved_at_1c0[0x20];
3232 u8 irisc_index[0x8];
3237 struct mlx5_ifc_register_loopback_control_bits {
3239 u8 reserved_at_1[0x7];
3241 u8 reserved_at_10[0x10];
3243 u8 reserved_at_20[0x60];
3246 struct mlx5_ifc_vport_tc_element_bits {
3247 u8 traffic_class[0x4];
3248 u8 reserved_at_4[0xc];
3249 u8 vport_number[0x10];
3252 struct mlx5_ifc_vport_element_bits {
3253 u8 reserved_at_0[0x10];
3254 u8 vport_number[0x10];
3258 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3259 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3260 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3263 struct mlx5_ifc_tsar_element_bits {
3264 u8 reserved_at_0[0x8];
3266 u8 reserved_at_10[0x10];
3270 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3271 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3274 struct mlx5_ifc_teardown_hca_out_bits {
3276 u8 reserved_at_8[0x18];
3280 u8 reserved_at_40[0x3f];
3282 u8 force_state[0x1];
3286 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3287 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3290 struct mlx5_ifc_teardown_hca_in_bits {
3292 u8 reserved_at_10[0x10];
3294 u8 reserved_at_20[0x10];
3297 u8 reserved_at_40[0x10];
3300 u8 reserved_at_60[0x20];
3303 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3305 u8 reserved_at_8[0x18];
3309 u8 reserved_at_40[0x40];
3312 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3314 u8 reserved_at_10[0x10];
3316 u8 reserved_at_20[0x10];
3319 u8 reserved_at_40[0x8];
3322 u8 reserved_at_60[0x20];
3324 u8 opt_param_mask[0x20];
3326 u8 reserved_at_a0[0x20];
3328 struct mlx5_ifc_qpc_bits qpc;
3330 u8 reserved_at_800[0x80];
3333 struct mlx5_ifc_sqd2rts_qp_out_bits {
3335 u8 reserved_at_8[0x18];
3339 u8 reserved_at_40[0x40];
3342 struct mlx5_ifc_sqd2rts_qp_in_bits {
3344 u8 reserved_at_10[0x10];
3346 u8 reserved_at_20[0x10];
3349 u8 reserved_at_40[0x8];
3352 u8 reserved_at_60[0x20];
3354 u8 opt_param_mask[0x20];
3356 u8 reserved_at_a0[0x20];
3358 struct mlx5_ifc_qpc_bits qpc;
3360 u8 reserved_at_800[0x80];
3363 struct mlx5_ifc_set_roce_address_out_bits {
3365 u8 reserved_at_8[0x18];
3369 u8 reserved_at_40[0x40];
3372 struct mlx5_ifc_set_roce_address_in_bits {
3374 u8 reserved_at_10[0x10];
3376 u8 reserved_at_20[0x10];
3379 u8 roce_address_index[0x10];
3380 u8 reserved_at_50[0xc];
3381 u8 vhca_port_num[0x4];
3383 u8 reserved_at_60[0x20];
3385 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3388 struct mlx5_ifc_set_mad_demux_out_bits {
3390 u8 reserved_at_8[0x18];
3394 u8 reserved_at_40[0x40];
3398 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3399 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3402 struct mlx5_ifc_set_mad_demux_in_bits {
3404 u8 reserved_at_10[0x10];
3406 u8 reserved_at_20[0x10];
3409 u8 reserved_at_40[0x20];
3411 u8 reserved_at_60[0x6];
3413 u8 reserved_at_68[0x18];
3416 struct mlx5_ifc_set_l2_table_entry_out_bits {
3418 u8 reserved_at_8[0x18];
3422 u8 reserved_at_40[0x40];
3425 struct mlx5_ifc_set_l2_table_entry_in_bits {
3427 u8 reserved_at_10[0x10];
3429 u8 reserved_at_20[0x10];
3432 u8 reserved_at_40[0x60];
3434 u8 reserved_at_a0[0x8];
3435 u8 table_index[0x18];
3437 u8 reserved_at_c0[0x20];
3439 u8 reserved_at_e0[0x13];
3443 struct mlx5_ifc_mac_address_layout_bits mac_address;
3445 u8 reserved_at_140[0xc0];
3448 struct mlx5_ifc_set_issi_out_bits {
3450 u8 reserved_at_8[0x18];
3454 u8 reserved_at_40[0x40];
3457 struct mlx5_ifc_set_issi_in_bits {
3459 u8 reserved_at_10[0x10];
3461 u8 reserved_at_20[0x10];
3464 u8 reserved_at_40[0x10];
3465 u8 current_issi[0x10];
3467 u8 reserved_at_60[0x20];
3470 struct mlx5_ifc_set_hca_cap_out_bits {
3472 u8 reserved_at_8[0x18];
3476 u8 reserved_at_40[0x40];
3479 struct mlx5_ifc_set_hca_cap_in_bits {
3481 u8 reserved_at_10[0x10];
3483 u8 reserved_at_20[0x10];
3486 u8 reserved_at_40[0x40];
3488 union mlx5_ifc_hca_cap_union_bits capability;
3492 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3493 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3494 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3495 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3498 struct mlx5_ifc_set_fte_out_bits {
3500 u8 reserved_at_8[0x18];
3504 u8 reserved_at_40[0x40];
3507 struct mlx5_ifc_set_fte_in_bits {
3509 u8 reserved_at_10[0x10];
3511 u8 reserved_at_20[0x10];
3514 u8 other_vport[0x1];
3515 u8 reserved_at_41[0xf];
3516 u8 vport_number[0x10];
3518 u8 reserved_at_60[0x20];
3521 u8 reserved_at_88[0x18];
3523 u8 reserved_at_a0[0x8];
3526 u8 reserved_at_c0[0x18];
3527 u8 modify_enable_mask[0x8];
3529 u8 reserved_at_e0[0x20];
3531 u8 flow_index[0x20];
3533 u8 reserved_at_120[0xe0];
3535 struct mlx5_ifc_flow_context_bits flow_context;
3538 struct mlx5_ifc_rts2rts_qp_out_bits {
3540 u8 reserved_at_8[0x18];
3544 u8 reserved_at_40[0x40];
3547 struct mlx5_ifc_rts2rts_qp_in_bits {
3549 u8 reserved_at_10[0x10];
3551 u8 reserved_at_20[0x10];
3554 u8 reserved_at_40[0x8];
3557 u8 reserved_at_60[0x20];
3559 u8 opt_param_mask[0x20];
3561 u8 reserved_at_a0[0x20];
3563 struct mlx5_ifc_qpc_bits qpc;
3565 u8 reserved_at_800[0x80];
3568 struct mlx5_ifc_rtr2rts_qp_out_bits {
3570 u8 reserved_at_8[0x18];
3574 u8 reserved_at_40[0x40];
3577 struct mlx5_ifc_rtr2rts_qp_in_bits {
3579 u8 reserved_at_10[0x10];
3581 u8 reserved_at_20[0x10];
3584 u8 reserved_at_40[0x8];
3587 u8 reserved_at_60[0x20];
3589 u8 opt_param_mask[0x20];
3591 u8 reserved_at_a0[0x20];
3593 struct mlx5_ifc_qpc_bits qpc;
3595 u8 reserved_at_800[0x80];
3598 struct mlx5_ifc_rst2init_qp_out_bits {
3600 u8 reserved_at_8[0x18];
3604 u8 reserved_at_40[0x40];
3607 struct mlx5_ifc_rst2init_qp_in_bits {
3609 u8 reserved_at_10[0x10];
3611 u8 reserved_at_20[0x10];
3614 u8 reserved_at_40[0x8];
3617 u8 reserved_at_60[0x20];
3619 u8 opt_param_mask[0x20];
3621 u8 reserved_at_a0[0x20];
3623 struct mlx5_ifc_qpc_bits qpc;
3625 u8 reserved_at_800[0x80];
3628 struct mlx5_ifc_query_xrq_out_bits {
3630 u8 reserved_at_8[0x18];
3634 u8 reserved_at_40[0x40];
3636 struct mlx5_ifc_xrqc_bits xrq_context;
3639 struct mlx5_ifc_query_xrq_in_bits {
3641 u8 reserved_at_10[0x10];
3643 u8 reserved_at_20[0x10];
3646 u8 reserved_at_40[0x8];
3649 u8 reserved_at_60[0x20];
3652 struct mlx5_ifc_query_xrc_srq_out_bits {
3654 u8 reserved_at_8[0x18];
3658 u8 reserved_at_40[0x40];
3660 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3662 u8 reserved_at_280[0x600];
3667 struct mlx5_ifc_query_xrc_srq_in_bits {
3669 u8 reserved_at_10[0x10];
3671 u8 reserved_at_20[0x10];
3674 u8 reserved_at_40[0x8];
3677 u8 reserved_at_60[0x20];
3681 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3682 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3685 struct mlx5_ifc_query_vport_state_out_bits {
3687 u8 reserved_at_8[0x18];
3691 u8 reserved_at_40[0x20];
3693 u8 reserved_at_60[0x18];
3694 u8 admin_state[0x4];
3699 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3700 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3703 struct mlx5_ifc_query_vport_state_in_bits {
3705 u8 reserved_at_10[0x10];
3707 u8 reserved_at_20[0x10];
3710 u8 other_vport[0x1];
3711 u8 reserved_at_41[0xf];
3712 u8 vport_number[0x10];
3714 u8 reserved_at_60[0x20];
3717 struct mlx5_ifc_query_vnic_env_out_bits {
3719 u8 reserved_at_8[0x18];
3723 u8 reserved_at_40[0x40];
3725 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3729 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3732 struct mlx5_ifc_query_vnic_env_in_bits {
3734 u8 reserved_at_10[0x10];
3736 u8 reserved_at_20[0x10];
3739 u8 other_vport[0x1];
3740 u8 reserved_at_41[0xf];
3741 u8 vport_number[0x10];
3743 u8 reserved_at_60[0x20];
3746 struct mlx5_ifc_query_vport_counter_out_bits {
3748 u8 reserved_at_8[0x18];
3752 u8 reserved_at_40[0x40];
3754 struct mlx5_ifc_traffic_counter_bits received_errors;
3756 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3758 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3760 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3762 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3764 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3766 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3768 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3770 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3772 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3774 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3776 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3778 u8 reserved_at_680[0xa00];
3782 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3785 struct mlx5_ifc_query_vport_counter_in_bits {
3787 u8 reserved_at_10[0x10];
3789 u8 reserved_at_20[0x10];
3792 u8 other_vport[0x1];
3793 u8 reserved_at_41[0xb];
3795 u8 vport_number[0x10];
3797 u8 reserved_at_60[0x60];
3800 u8 reserved_at_c1[0x1f];
3802 u8 reserved_at_e0[0x20];
3805 struct mlx5_ifc_query_tis_out_bits {
3807 u8 reserved_at_8[0x18];
3811 u8 reserved_at_40[0x40];
3813 struct mlx5_ifc_tisc_bits tis_context;
3816 struct mlx5_ifc_query_tis_in_bits {
3818 u8 reserved_at_10[0x10];
3820 u8 reserved_at_20[0x10];
3823 u8 reserved_at_40[0x8];
3826 u8 reserved_at_60[0x20];
3829 struct mlx5_ifc_query_tir_out_bits {
3831 u8 reserved_at_8[0x18];
3835 u8 reserved_at_40[0xc0];
3837 struct mlx5_ifc_tirc_bits tir_context;
3840 struct mlx5_ifc_query_tir_in_bits {
3842 u8 reserved_at_10[0x10];
3844 u8 reserved_at_20[0x10];
3847 u8 reserved_at_40[0x8];
3850 u8 reserved_at_60[0x20];
3853 struct mlx5_ifc_query_srq_out_bits {
3855 u8 reserved_at_8[0x18];
3859 u8 reserved_at_40[0x40];
3861 struct mlx5_ifc_srqc_bits srq_context_entry;
3863 u8 reserved_at_280[0x600];
3868 struct mlx5_ifc_query_srq_in_bits {
3870 u8 reserved_at_10[0x10];
3872 u8 reserved_at_20[0x10];
3875 u8 reserved_at_40[0x8];
3878 u8 reserved_at_60[0x20];
3881 struct mlx5_ifc_query_sq_out_bits {
3883 u8 reserved_at_8[0x18];
3887 u8 reserved_at_40[0xc0];
3889 struct mlx5_ifc_sqc_bits sq_context;
3892 struct mlx5_ifc_query_sq_in_bits {
3894 u8 reserved_at_10[0x10];
3896 u8 reserved_at_20[0x10];
3899 u8 reserved_at_40[0x8];
3902 u8 reserved_at_60[0x20];
3905 struct mlx5_ifc_query_special_contexts_out_bits {
3907 u8 reserved_at_8[0x18];
3911 u8 dump_fill_mkey[0x20];
3917 u8 reserved_at_a0[0x60];
3920 struct mlx5_ifc_query_special_contexts_in_bits {
3922 u8 reserved_at_10[0x10];
3924 u8 reserved_at_20[0x10];
3927 u8 reserved_at_40[0x40];
3930 struct mlx5_ifc_query_scheduling_element_out_bits {
3932 u8 reserved_at_10[0x10];
3934 u8 reserved_at_20[0x10];
3937 u8 reserved_at_40[0xc0];
3939 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3941 u8 reserved_at_300[0x100];
3945 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3948 struct mlx5_ifc_query_scheduling_element_in_bits {
3950 u8 reserved_at_10[0x10];
3952 u8 reserved_at_20[0x10];
3955 u8 scheduling_hierarchy[0x8];
3956 u8 reserved_at_48[0x18];
3958 u8 scheduling_element_id[0x20];
3960 u8 reserved_at_80[0x180];
3963 struct mlx5_ifc_query_rqt_out_bits {
3965 u8 reserved_at_8[0x18];
3969 u8 reserved_at_40[0xc0];
3971 struct mlx5_ifc_rqtc_bits rqt_context;
3974 struct mlx5_ifc_query_rqt_in_bits {
3976 u8 reserved_at_10[0x10];
3978 u8 reserved_at_20[0x10];
3981 u8 reserved_at_40[0x8];
3984 u8 reserved_at_60[0x20];
3987 struct mlx5_ifc_query_rq_out_bits {
3989 u8 reserved_at_8[0x18];
3993 u8 reserved_at_40[0xc0];
3995 struct mlx5_ifc_rqc_bits rq_context;
3998 struct mlx5_ifc_query_rq_in_bits {
4000 u8 reserved_at_10[0x10];
4002 u8 reserved_at_20[0x10];
4005 u8 reserved_at_40[0x8];
4008 u8 reserved_at_60[0x20];
4011 struct mlx5_ifc_query_roce_address_out_bits {
4013 u8 reserved_at_8[0x18];
4017 u8 reserved_at_40[0x40];
4019 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4022 struct mlx5_ifc_query_roce_address_in_bits {
4024 u8 reserved_at_10[0x10];
4026 u8 reserved_at_20[0x10];
4029 u8 roce_address_index[0x10];
4030 u8 reserved_at_50[0xc];
4031 u8 vhca_port_num[0x4];
4033 u8 reserved_at_60[0x20];
4036 struct mlx5_ifc_query_rmp_out_bits {
4038 u8 reserved_at_8[0x18];
4042 u8 reserved_at_40[0xc0];
4044 struct mlx5_ifc_rmpc_bits rmp_context;
4047 struct mlx5_ifc_query_rmp_in_bits {
4049 u8 reserved_at_10[0x10];
4051 u8 reserved_at_20[0x10];
4054 u8 reserved_at_40[0x8];
4057 u8 reserved_at_60[0x20];
4060 struct mlx5_ifc_query_qp_out_bits {
4062 u8 reserved_at_8[0x18];
4066 u8 reserved_at_40[0x40];
4068 u8 opt_param_mask[0x20];
4070 u8 reserved_at_a0[0x20];
4072 struct mlx5_ifc_qpc_bits qpc;
4074 u8 reserved_at_800[0x80];
4079 struct mlx5_ifc_query_qp_in_bits {
4081 u8 reserved_at_10[0x10];
4083 u8 reserved_at_20[0x10];
4086 u8 reserved_at_40[0x8];
4089 u8 reserved_at_60[0x20];
4092 struct mlx5_ifc_query_q_counter_out_bits {
4094 u8 reserved_at_8[0x18];
4098 u8 reserved_at_40[0x40];
4100 u8 rx_write_requests[0x20];
4102 u8 reserved_at_a0[0x20];
4104 u8 rx_read_requests[0x20];
4106 u8 reserved_at_e0[0x20];
4108 u8 rx_atomic_requests[0x20];
4110 u8 reserved_at_120[0x20];
4112 u8 rx_dct_connect[0x20];
4114 u8 reserved_at_160[0x20];
4116 u8 out_of_buffer[0x20];
4118 u8 reserved_at_1a0[0x20];
4120 u8 out_of_sequence[0x20];
4122 u8 reserved_at_1e0[0x20];
4124 u8 duplicate_request[0x20];
4126 u8 reserved_at_220[0x20];
4128 u8 rnr_nak_retry_err[0x20];
4130 u8 reserved_at_260[0x20];
4132 u8 packet_seq_err[0x20];
4134 u8 reserved_at_2a0[0x20];
4136 u8 implied_nak_seq_err[0x20];
4138 u8 reserved_at_2e0[0x20];
4140 u8 local_ack_timeout_err[0x20];
4142 u8 reserved_at_320[0xa0];
4144 u8 resp_local_length_error[0x20];
4146 u8 req_local_length_error[0x20];
4148 u8 resp_local_qp_error[0x20];
4150 u8 local_operation_error[0x20];
4152 u8 resp_local_protection[0x20];
4154 u8 req_local_protection[0x20];
4156 u8 resp_cqe_error[0x20];
4158 u8 req_cqe_error[0x20];
4160 u8 req_mw_binding[0x20];
4162 u8 req_bad_response[0x20];
4164 u8 req_remote_invalid_request[0x20];
4166 u8 resp_remote_invalid_request[0x20];
4168 u8 req_remote_access_errors[0x20];
4170 u8 resp_remote_access_errors[0x20];
4172 u8 req_remote_operation_errors[0x20];
4174 u8 req_transport_retries_exceeded[0x20];
4176 u8 cq_overflow[0x20];
4178 u8 resp_cqe_flush_error[0x20];
4180 u8 req_cqe_flush_error[0x20];
4182 u8 reserved_at_620[0x1e0];
4185 struct mlx5_ifc_query_q_counter_in_bits {
4187 u8 reserved_at_10[0x10];
4189 u8 reserved_at_20[0x10];
4192 u8 reserved_at_40[0x80];
4195 u8 reserved_at_c1[0x1f];
4197 u8 reserved_at_e0[0x18];
4198 u8 counter_set_id[0x8];
4201 struct mlx5_ifc_query_pages_out_bits {
4203 u8 reserved_at_8[0x18];
4207 u8 reserved_at_40[0x10];
4208 u8 function_id[0x10];
4214 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4215 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4216 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4219 struct mlx5_ifc_query_pages_in_bits {
4221 u8 reserved_at_10[0x10];
4223 u8 reserved_at_20[0x10];
4226 u8 reserved_at_40[0x10];
4227 u8 function_id[0x10];
4229 u8 reserved_at_60[0x20];
4232 struct mlx5_ifc_query_nic_vport_context_out_bits {
4234 u8 reserved_at_8[0x18];
4238 u8 reserved_at_40[0x40];
4240 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4243 struct mlx5_ifc_query_nic_vport_context_in_bits {
4245 u8 reserved_at_10[0x10];
4247 u8 reserved_at_20[0x10];
4250 u8 other_vport[0x1];
4251 u8 reserved_at_41[0xf];
4252 u8 vport_number[0x10];
4254 u8 reserved_at_60[0x5];
4255 u8 allowed_list_type[0x3];
4256 u8 reserved_at_68[0x18];
4259 struct mlx5_ifc_query_mkey_out_bits {
4261 u8 reserved_at_8[0x18];
4265 u8 reserved_at_40[0x40];
4267 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4269 u8 reserved_at_280[0x600];
4271 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4273 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4276 struct mlx5_ifc_query_mkey_in_bits {
4278 u8 reserved_at_10[0x10];
4280 u8 reserved_at_20[0x10];
4283 u8 reserved_at_40[0x8];
4284 u8 mkey_index[0x18];
4287 u8 reserved_at_61[0x1f];
4290 struct mlx5_ifc_query_mad_demux_out_bits {
4292 u8 reserved_at_8[0x18];
4296 u8 reserved_at_40[0x40];
4298 u8 mad_dumux_parameters_block[0x20];
4301 struct mlx5_ifc_query_mad_demux_in_bits {
4303 u8 reserved_at_10[0x10];
4305 u8 reserved_at_20[0x10];
4308 u8 reserved_at_40[0x40];
4311 struct mlx5_ifc_query_l2_table_entry_out_bits {
4313 u8 reserved_at_8[0x18];
4317 u8 reserved_at_40[0xa0];
4319 u8 reserved_at_e0[0x13];
4323 struct mlx5_ifc_mac_address_layout_bits mac_address;
4325 u8 reserved_at_140[0xc0];
4328 struct mlx5_ifc_query_l2_table_entry_in_bits {
4330 u8 reserved_at_10[0x10];
4332 u8 reserved_at_20[0x10];
4335 u8 reserved_at_40[0x60];
4337 u8 reserved_at_a0[0x8];
4338 u8 table_index[0x18];
4340 u8 reserved_at_c0[0x140];
4343 struct mlx5_ifc_query_issi_out_bits {
4345 u8 reserved_at_8[0x18];
4349 u8 reserved_at_40[0x10];
4350 u8 current_issi[0x10];
4352 u8 reserved_at_60[0xa0];
4354 u8 reserved_at_100[76][0x8];
4355 u8 supported_issi_dw0[0x20];
4358 struct mlx5_ifc_query_issi_in_bits {
4360 u8 reserved_at_10[0x10];
4362 u8 reserved_at_20[0x10];
4365 u8 reserved_at_40[0x40];
4368 struct mlx5_ifc_set_driver_version_out_bits {
4370 u8 reserved_0[0x18];
4373 u8 reserved_1[0x40];
4376 struct mlx5_ifc_set_driver_version_in_bits {
4378 u8 reserved_0[0x10];
4380 u8 reserved_1[0x10];
4383 u8 reserved_2[0x40];
4384 u8 driver_version[64][0x8];
4387 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4389 u8 reserved_at_8[0x18];
4393 u8 reserved_at_40[0x40];
4395 struct mlx5_ifc_pkey_bits pkey[0];
4398 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4400 u8 reserved_at_10[0x10];
4402 u8 reserved_at_20[0x10];
4405 u8 other_vport[0x1];
4406 u8 reserved_at_41[0xb];
4408 u8 vport_number[0x10];
4410 u8 reserved_at_60[0x10];
4411 u8 pkey_index[0x10];
4415 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4416 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4417 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4420 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4422 u8 reserved_at_8[0x18];
4426 u8 reserved_at_40[0x20];
4429 u8 reserved_at_70[0x10];
4431 struct mlx5_ifc_array128_auto_bits gid[0];
4434 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4436 u8 reserved_at_10[0x10];
4438 u8 reserved_at_20[0x10];
4441 u8 other_vport[0x1];
4442 u8 reserved_at_41[0xb];
4444 u8 vport_number[0x10];
4446 u8 reserved_at_60[0x10];
4450 struct mlx5_ifc_query_hca_vport_context_out_bits {
4452 u8 reserved_at_8[0x18];
4456 u8 reserved_at_40[0x40];
4458 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4461 struct mlx5_ifc_query_hca_vport_context_in_bits {
4463 u8 reserved_at_10[0x10];
4465 u8 reserved_at_20[0x10];
4468 u8 other_vport[0x1];
4469 u8 reserved_at_41[0xb];
4471 u8 vport_number[0x10];
4473 u8 reserved_at_60[0x20];
4476 struct mlx5_ifc_query_hca_cap_out_bits {
4478 u8 reserved_at_8[0x18];
4482 u8 reserved_at_40[0x40];
4484 union mlx5_ifc_hca_cap_union_bits capability;
4487 struct mlx5_ifc_query_hca_cap_in_bits {
4489 u8 reserved_at_10[0x10];
4491 u8 reserved_at_20[0x10];
4494 u8 reserved_at_40[0x40];
4497 struct mlx5_ifc_query_flow_table_out_bits {
4499 u8 reserved_at_8[0x18];
4503 u8 reserved_at_40[0x80];
4505 u8 reserved_at_c0[0x8];
4507 u8 reserved_at_d0[0x8];
4510 u8 reserved_at_e0[0x120];
4513 struct mlx5_ifc_query_flow_table_in_bits {
4515 u8 reserved_at_10[0x10];
4517 u8 reserved_at_20[0x10];
4520 u8 reserved_at_40[0x40];
4523 u8 reserved_at_88[0x18];
4525 u8 reserved_at_a0[0x8];
4528 u8 reserved_at_c0[0x140];
4531 struct mlx5_ifc_query_fte_out_bits {
4533 u8 reserved_at_8[0x18];
4537 u8 reserved_at_40[0x1c0];
4539 struct mlx5_ifc_flow_context_bits flow_context;
4542 struct mlx5_ifc_query_fte_in_bits {
4544 u8 reserved_at_10[0x10];
4546 u8 reserved_at_20[0x10];
4549 u8 reserved_at_40[0x40];
4552 u8 reserved_at_88[0x18];
4554 u8 reserved_at_a0[0x8];
4557 u8 reserved_at_c0[0x40];
4559 u8 flow_index[0x20];
4561 u8 reserved_at_120[0xe0];
4565 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4566 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4567 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4570 struct mlx5_ifc_query_flow_group_out_bits {
4572 u8 reserved_at_8[0x18];
4576 u8 reserved_at_40[0xa0];
4578 u8 start_flow_index[0x20];
4580 u8 reserved_at_100[0x20];
4582 u8 end_flow_index[0x20];
4584 u8 reserved_at_140[0xa0];
4586 u8 reserved_at_1e0[0x18];
4587 u8 match_criteria_enable[0x8];
4589 struct mlx5_ifc_fte_match_param_bits match_criteria;
4591 u8 reserved_at_1200[0xe00];
4594 struct mlx5_ifc_query_flow_group_in_bits {
4596 u8 reserved_at_10[0x10];
4598 u8 reserved_at_20[0x10];
4601 u8 reserved_at_40[0x40];
4604 u8 reserved_at_88[0x18];
4606 u8 reserved_at_a0[0x8];
4611 u8 reserved_at_e0[0x120];
4614 struct mlx5_ifc_query_flow_counter_out_bits {
4616 u8 reserved_at_8[0x18];
4620 u8 reserved_at_40[0x40];
4622 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4625 struct mlx5_ifc_query_flow_counter_in_bits {
4627 u8 reserved_at_10[0x10];
4629 u8 reserved_at_20[0x10];
4632 u8 reserved_at_40[0x80];
4635 u8 reserved_at_c1[0xf];
4636 u8 num_of_counters[0x10];
4638 u8 flow_counter_id[0x20];
4641 struct mlx5_ifc_query_esw_vport_context_out_bits {
4643 u8 reserved_at_8[0x18];
4647 u8 reserved_at_40[0x40];
4649 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4652 struct mlx5_ifc_query_esw_vport_context_in_bits {
4654 u8 reserved_at_10[0x10];
4656 u8 reserved_at_20[0x10];
4659 u8 other_vport[0x1];
4660 u8 reserved_at_41[0xf];
4661 u8 vport_number[0x10];
4663 u8 reserved_at_60[0x20];
4666 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4668 u8 reserved_at_8[0x18];
4672 u8 reserved_at_40[0x40];
4675 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4676 u8 reserved_at_0[0x1c];
4677 u8 vport_cvlan_insert[0x1];
4678 u8 vport_svlan_insert[0x1];
4679 u8 vport_cvlan_strip[0x1];
4680 u8 vport_svlan_strip[0x1];
4683 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4685 u8 reserved_at_10[0x10];
4687 u8 reserved_at_20[0x10];
4690 u8 other_vport[0x1];
4691 u8 reserved_at_41[0xf];
4692 u8 vport_number[0x10];
4694 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4696 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4699 struct mlx5_ifc_query_eq_out_bits {
4701 u8 reserved_at_8[0x18];
4705 u8 reserved_at_40[0x40];
4707 struct mlx5_ifc_eqc_bits eq_context_entry;
4709 u8 reserved_at_280[0x40];
4711 u8 event_bitmask[0x40];
4713 u8 reserved_at_300[0x580];
4718 struct mlx5_ifc_query_eq_in_bits {
4720 u8 reserved_at_10[0x10];
4722 u8 reserved_at_20[0x10];
4725 u8 reserved_at_40[0x18];
4728 u8 reserved_at_60[0x20];
4731 struct mlx5_ifc_encap_header_in_bits {
4732 u8 reserved_at_0[0x5];
4733 u8 header_type[0x3];
4734 u8 reserved_at_8[0xe];
4735 u8 encap_header_size[0xa];
4737 u8 reserved_at_20[0x10];
4738 u8 encap_header[2][0x8];
4740 u8 more_encap_header[0][0x8];
4743 struct mlx5_ifc_query_encap_header_out_bits {
4745 u8 reserved_at_8[0x18];
4749 u8 reserved_at_40[0xa0];
4751 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4754 struct mlx5_ifc_query_encap_header_in_bits {
4756 u8 reserved_at_10[0x10];
4758 u8 reserved_at_20[0x10];
4763 u8 reserved_at_60[0xa0];
4766 struct mlx5_ifc_alloc_encap_header_out_bits {
4768 u8 reserved_at_8[0x18];
4774 u8 reserved_at_60[0x20];
4777 struct mlx5_ifc_alloc_encap_header_in_bits {
4779 u8 reserved_at_10[0x10];
4781 u8 reserved_at_20[0x10];
4784 u8 reserved_at_40[0xa0];
4786 struct mlx5_ifc_encap_header_in_bits encap_header;
4789 struct mlx5_ifc_dealloc_encap_header_out_bits {
4791 u8 reserved_at_8[0x18];
4795 u8 reserved_at_40[0x40];
4798 struct mlx5_ifc_dealloc_encap_header_in_bits {
4800 u8 reserved_at_10[0x10];
4802 u8 reserved_20[0x10];
4807 u8 reserved_60[0x20];
4810 struct mlx5_ifc_set_action_in_bits {
4811 u8 action_type[0x4];
4813 u8 reserved_at_10[0x3];
4815 u8 reserved_at_18[0x3];
4821 struct mlx5_ifc_add_action_in_bits {
4822 u8 action_type[0x4];
4824 u8 reserved_at_10[0x10];
4829 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4830 struct mlx5_ifc_set_action_in_bits set_action_in;
4831 struct mlx5_ifc_add_action_in_bits add_action_in;
4832 u8 reserved_at_0[0x40];
4836 MLX5_ACTION_TYPE_SET = 0x1,
4837 MLX5_ACTION_TYPE_ADD = 0x2,
4841 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4842 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4843 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4844 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4845 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4846 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4847 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4848 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4849 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4850 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4851 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4852 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4853 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4854 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4855 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4857 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4858 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4859 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4861 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4862 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4863 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4866 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4868 u8 reserved_at_8[0x18];
4872 u8 modify_header_id[0x20];
4874 u8 reserved_at_60[0x20];
4877 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4879 u8 reserved_at_10[0x10];
4881 u8 reserved_at_20[0x10];
4884 u8 reserved_at_40[0x20];
4887 u8 reserved_at_68[0x10];
4888 u8 num_of_actions[0x8];
4890 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4893 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4895 u8 reserved_at_8[0x18];
4899 u8 reserved_at_40[0x40];
4902 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4904 u8 reserved_at_10[0x10];
4906 u8 reserved_at_20[0x10];
4909 u8 modify_header_id[0x20];
4911 u8 reserved_at_60[0x20];
4914 struct mlx5_ifc_query_dct_out_bits {
4916 u8 reserved_at_8[0x18];
4920 u8 reserved_at_40[0x40];
4922 struct mlx5_ifc_dctc_bits dct_context_entry;
4924 u8 reserved_at_280[0x180];
4927 struct mlx5_ifc_query_dct_in_bits {
4929 u8 reserved_at_10[0x10];
4931 u8 reserved_at_20[0x10];
4934 u8 reserved_at_40[0x8];
4937 u8 reserved_at_60[0x20];
4940 struct mlx5_ifc_query_cq_out_bits {
4942 u8 reserved_at_8[0x18];
4946 u8 reserved_at_40[0x40];
4948 struct mlx5_ifc_cqc_bits cq_context;
4950 u8 reserved_at_280[0x600];
4955 struct mlx5_ifc_query_cq_in_bits {
4957 u8 reserved_at_10[0x10];
4959 u8 reserved_at_20[0x10];
4962 u8 reserved_at_40[0x8];
4965 u8 reserved_at_60[0x20];
4968 struct mlx5_ifc_query_cong_status_out_bits {
4970 u8 reserved_at_8[0x18];
4974 u8 reserved_at_40[0x20];
4978 u8 reserved_at_62[0x1e];
4981 struct mlx5_ifc_query_cong_status_in_bits {
4983 u8 reserved_at_10[0x10];
4985 u8 reserved_at_20[0x10];
4988 u8 reserved_at_40[0x18];
4990 u8 cong_protocol[0x4];
4992 u8 reserved_at_60[0x20];
4995 struct mlx5_ifc_query_cong_statistics_out_bits {
4997 u8 reserved_at_8[0x18];
5001 u8 reserved_at_40[0x40];
5003 u8 rp_cur_flows[0x20];
5007 u8 rp_cnp_ignored_high[0x20];
5009 u8 rp_cnp_ignored_low[0x20];
5011 u8 rp_cnp_handled_high[0x20];
5013 u8 rp_cnp_handled_low[0x20];
5015 u8 reserved_at_140[0x100];
5017 u8 time_stamp_high[0x20];
5019 u8 time_stamp_low[0x20];
5021 u8 accumulators_period[0x20];
5023 u8 np_ecn_marked_roce_packets_high[0x20];
5025 u8 np_ecn_marked_roce_packets_low[0x20];
5027 u8 np_cnp_sent_high[0x20];
5029 u8 np_cnp_sent_low[0x20];
5031 u8 reserved_at_320[0x560];
5034 struct mlx5_ifc_query_cong_statistics_in_bits {
5036 u8 reserved_at_10[0x10];
5038 u8 reserved_at_20[0x10];
5042 u8 reserved_at_41[0x1f];
5044 u8 reserved_at_60[0x20];
5047 struct mlx5_ifc_query_cong_params_out_bits {
5049 u8 reserved_at_8[0x18];
5053 u8 reserved_at_40[0x40];
5055 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5058 struct mlx5_ifc_query_cong_params_in_bits {
5060 u8 reserved_at_10[0x10];
5062 u8 reserved_at_20[0x10];
5065 u8 reserved_at_40[0x1c];
5066 u8 cong_protocol[0x4];
5068 u8 reserved_at_60[0x20];
5071 struct mlx5_ifc_query_adapter_out_bits {
5073 u8 reserved_at_8[0x18];
5077 u8 reserved_at_40[0x40];
5079 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5082 struct mlx5_ifc_query_adapter_in_bits {
5084 u8 reserved_at_10[0x10];
5086 u8 reserved_at_20[0x10];
5089 u8 reserved_at_40[0x40];
5092 struct mlx5_ifc_qp_2rst_out_bits {
5094 u8 reserved_at_8[0x18];
5098 u8 reserved_at_40[0x40];
5101 struct mlx5_ifc_qp_2rst_in_bits {
5103 u8 reserved_at_10[0x10];
5105 u8 reserved_at_20[0x10];
5108 u8 reserved_at_40[0x8];
5111 u8 reserved_at_60[0x20];
5114 struct mlx5_ifc_qp_2err_out_bits {
5116 u8 reserved_at_8[0x18];
5120 u8 reserved_at_40[0x40];
5123 struct mlx5_ifc_qp_2err_in_bits {
5125 u8 reserved_at_10[0x10];
5127 u8 reserved_at_20[0x10];
5130 u8 reserved_at_40[0x8];
5133 u8 reserved_at_60[0x20];
5136 struct mlx5_ifc_page_fault_resume_out_bits {
5138 u8 reserved_at_8[0x18];
5142 u8 reserved_at_40[0x40];
5145 struct mlx5_ifc_page_fault_resume_in_bits {
5147 u8 reserved_at_10[0x10];
5149 u8 reserved_at_20[0x10];
5153 u8 reserved_at_41[0x4];
5154 u8 page_fault_type[0x3];
5157 u8 reserved_at_60[0x8];
5161 struct mlx5_ifc_nop_out_bits {
5163 u8 reserved_at_8[0x18];
5167 u8 reserved_at_40[0x40];
5170 struct mlx5_ifc_nop_in_bits {
5172 u8 reserved_at_10[0x10];
5174 u8 reserved_at_20[0x10];
5177 u8 reserved_at_40[0x40];
5180 struct mlx5_ifc_modify_vport_state_out_bits {
5182 u8 reserved_at_8[0x18];
5186 u8 reserved_at_40[0x40];
5189 struct mlx5_ifc_modify_vport_state_in_bits {
5191 u8 reserved_at_10[0x10];
5193 u8 reserved_at_20[0x10];
5196 u8 other_vport[0x1];
5197 u8 reserved_at_41[0xf];
5198 u8 vport_number[0x10];
5200 u8 reserved_at_60[0x18];
5201 u8 admin_state[0x4];
5202 u8 reserved_at_7c[0x4];
5205 struct mlx5_ifc_modify_tis_out_bits {
5207 u8 reserved_at_8[0x18];
5211 u8 reserved_at_40[0x40];
5214 struct mlx5_ifc_modify_tis_bitmask_bits {
5215 u8 reserved_at_0[0x20];
5217 u8 reserved_at_20[0x1d];
5218 u8 lag_tx_port_affinity[0x1];
5219 u8 strict_lag_tx_port_affinity[0x1];
5223 struct mlx5_ifc_modify_tis_in_bits {
5225 u8 reserved_at_10[0x10];
5227 u8 reserved_at_20[0x10];
5230 u8 reserved_at_40[0x8];
5233 u8 reserved_at_60[0x20];
5235 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5237 u8 reserved_at_c0[0x40];
5239 struct mlx5_ifc_tisc_bits ctx;
5242 struct mlx5_ifc_modify_tir_bitmask_bits {
5243 u8 reserved_at_0[0x20];
5245 u8 reserved_at_20[0x1b];
5247 u8 reserved_at_3c[0x1];
5249 u8 reserved_at_3e[0x1];
5253 struct mlx5_ifc_modify_tir_out_bits {
5255 u8 reserved_at_8[0x18];
5259 u8 reserved_at_40[0x40];
5262 struct mlx5_ifc_modify_tir_in_bits {
5264 u8 reserved_at_10[0x10];
5266 u8 reserved_at_20[0x10];
5269 u8 reserved_at_40[0x8];
5272 u8 reserved_at_60[0x20];
5274 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5276 u8 reserved_at_c0[0x40];
5278 struct mlx5_ifc_tirc_bits ctx;
5281 struct mlx5_ifc_modify_sq_out_bits {
5283 u8 reserved_at_8[0x18];
5287 u8 reserved_at_40[0x40];
5290 struct mlx5_ifc_modify_sq_in_bits {
5292 u8 reserved_at_10[0x10];
5294 u8 reserved_at_20[0x10];
5298 u8 reserved_at_44[0x4];
5301 u8 reserved_at_60[0x20];
5303 u8 modify_bitmask[0x40];
5305 u8 reserved_at_c0[0x40];
5307 struct mlx5_ifc_sqc_bits ctx;
5310 struct mlx5_ifc_modify_scheduling_element_out_bits {
5312 u8 reserved_at_8[0x18];
5316 u8 reserved_at_40[0x1c0];
5320 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5321 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5324 struct mlx5_ifc_modify_scheduling_element_in_bits {
5326 u8 reserved_at_10[0x10];
5328 u8 reserved_at_20[0x10];
5331 u8 scheduling_hierarchy[0x8];
5332 u8 reserved_at_48[0x18];
5334 u8 scheduling_element_id[0x20];
5336 u8 reserved_at_80[0x20];
5338 u8 modify_bitmask[0x20];
5340 u8 reserved_at_c0[0x40];
5342 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5344 u8 reserved_at_300[0x100];
5347 struct mlx5_ifc_modify_rqt_out_bits {
5349 u8 reserved_at_8[0x18];
5353 u8 reserved_at_40[0x40];
5356 struct mlx5_ifc_rqt_bitmask_bits {
5357 u8 reserved_at_0[0x20];
5359 u8 reserved_at_20[0x1f];
5363 struct mlx5_ifc_modify_rqt_in_bits {
5365 u8 reserved_at_10[0x10];
5367 u8 reserved_at_20[0x10];
5370 u8 reserved_at_40[0x8];
5373 u8 reserved_at_60[0x20];
5375 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5377 u8 reserved_at_c0[0x40];
5379 struct mlx5_ifc_rqtc_bits ctx;
5382 struct mlx5_ifc_modify_rq_out_bits {
5384 u8 reserved_at_8[0x18];
5388 u8 reserved_at_40[0x40];
5392 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5393 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5394 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5397 struct mlx5_ifc_modify_rq_in_bits {
5399 u8 reserved_at_10[0x10];
5401 u8 reserved_at_20[0x10];
5405 u8 reserved_at_44[0x4];
5408 u8 reserved_at_60[0x20];
5410 u8 modify_bitmask[0x40];
5412 u8 reserved_at_c0[0x40];
5414 struct mlx5_ifc_rqc_bits ctx;
5417 struct mlx5_ifc_modify_rmp_out_bits {
5419 u8 reserved_at_8[0x18];
5423 u8 reserved_at_40[0x40];
5426 struct mlx5_ifc_rmp_bitmask_bits {
5427 u8 reserved_at_0[0x20];
5429 u8 reserved_at_20[0x1f];
5433 struct mlx5_ifc_modify_rmp_in_bits {
5435 u8 reserved_at_10[0x10];
5437 u8 reserved_at_20[0x10];
5441 u8 reserved_at_44[0x4];
5444 u8 reserved_at_60[0x20];
5446 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5448 u8 reserved_at_c0[0x40];
5450 struct mlx5_ifc_rmpc_bits ctx;
5453 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5455 u8 reserved_at_8[0x18];
5459 u8 reserved_at_40[0x40];
5462 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5463 u8 reserved_at_0[0x12];
5464 u8 affiliation[0x1];
5465 u8 reserved_at_e[0x1];
5466 u8 disable_uc_local_lb[0x1];
5467 u8 disable_mc_local_lb[0x1];
5472 u8 change_event[0x1];
5474 u8 permanent_address[0x1];
5475 u8 addresses_list[0x1];
5477 u8 reserved_at_1f[0x1];
5480 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5482 u8 reserved_at_10[0x10];
5484 u8 reserved_at_20[0x10];
5487 u8 other_vport[0x1];
5488 u8 reserved_at_41[0xf];
5489 u8 vport_number[0x10];
5491 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5493 u8 reserved_at_80[0x780];
5495 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5498 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5500 u8 reserved_at_8[0x18];
5504 u8 reserved_at_40[0x40];
5507 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5509 u8 reserved_at_10[0x10];
5511 u8 reserved_at_20[0x10];
5514 u8 other_vport[0x1];
5515 u8 reserved_at_41[0xb];
5517 u8 vport_number[0x10];
5519 u8 reserved_at_60[0x20];
5521 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5524 struct mlx5_ifc_modify_cq_out_bits {
5526 u8 reserved_at_8[0x18];
5530 u8 reserved_at_40[0x40];
5534 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5535 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5538 struct mlx5_ifc_modify_cq_in_bits {
5540 u8 reserved_at_10[0x10];
5542 u8 reserved_at_20[0x10];
5545 u8 reserved_at_40[0x8];
5548 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5550 struct mlx5_ifc_cqc_bits cq_context;
5552 u8 reserved_at_280[0x600];
5557 struct mlx5_ifc_modify_cong_status_out_bits {
5559 u8 reserved_at_8[0x18];
5563 u8 reserved_at_40[0x40];
5566 struct mlx5_ifc_modify_cong_status_in_bits {
5568 u8 reserved_at_10[0x10];
5570 u8 reserved_at_20[0x10];
5573 u8 reserved_at_40[0x18];
5575 u8 cong_protocol[0x4];
5579 u8 reserved_at_62[0x1e];
5582 struct mlx5_ifc_modify_cong_params_out_bits {
5584 u8 reserved_at_8[0x18];
5588 u8 reserved_at_40[0x40];
5591 struct mlx5_ifc_modify_cong_params_in_bits {
5593 u8 reserved_at_10[0x10];
5595 u8 reserved_at_20[0x10];
5598 u8 reserved_at_40[0x1c];
5599 u8 cong_protocol[0x4];
5601 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5603 u8 reserved_at_80[0x80];
5605 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5608 struct mlx5_ifc_manage_pages_out_bits {
5610 u8 reserved_at_8[0x18];
5614 u8 output_num_entries[0x20];
5616 u8 reserved_at_60[0x20];
5622 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5623 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5624 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5627 struct mlx5_ifc_manage_pages_in_bits {
5629 u8 reserved_at_10[0x10];
5631 u8 reserved_at_20[0x10];
5634 u8 reserved_at_40[0x10];
5635 u8 function_id[0x10];
5637 u8 input_num_entries[0x20];
5642 struct mlx5_ifc_mad_ifc_out_bits {
5644 u8 reserved_at_8[0x18];
5648 u8 reserved_at_40[0x40];
5650 u8 response_mad_packet[256][0x8];
5653 struct mlx5_ifc_mad_ifc_in_bits {
5655 u8 reserved_at_10[0x10];
5657 u8 reserved_at_20[0x10];
5660 u8 remote_lid[0x10];
5661 u8 reserved_at_50[0x8];
5664 u8 reserved_at_60[0x20];
5669 struct mlx5_ifc_init_hca_out_bits {
5671 u8 reserved_at_8[0x18];
5675 u8 reserved_at_40[0x40];
5678 struct mlx5_ifc_init_hca_in_bits {
5680 u8 reserved_at_10[0x10];
5682 u8 reserved_at_20[0x10];
5685 u8 reserved_at_40[0x40];
5686 u8 sw_owner_id[4][0x20];
5689 struct mlx5_ifc_init2rtr_qp_out_bits {
5691 u8 reserved_at_8[0x18];
5695 u8 reserved_at_40[0x40];
5698 struct mlx5_ifc_init2rtr_qp_in_bits {
5700 u8 reserved_at_10[0x10];
5702 u8 reserved_at_20[0x10];
5705 u8 reserved_at_40[0x8];
5708 u8 reserved_at_60[0x20];
5710 u8 opt_param_mask[0x20];
5712 u8 reserved_at_a0[0x20];
5714 struct mlx5_ifc_qpc_bits qpc;
5716 u8 reserved_at_800[0x80];
5719 struct mlx5_ifc_init2init_qp_out_bits {
5721 u8 reserved_at_8[0x18];
5725 u8 reserved_at_40[0x40];
5728 struct mlx5_ifc_init2init_qp_in_bits {
5730 u8 reserved_at_10[0x10];
5732 u8 reserved_at_20[0x10];
5735 u8 reserved_at_40[0x8];
5738 u8 reserved_at_60[0x20];
5740 u8 opt_param_mask[0x20];
5742 u8 reserved_at_a0[0x20];
5744 struct mlx5_ifc_qpc_bits qpc;
5746 u8 reserved_at_800[0x80];
5749 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5751 u8 reserved_at_8[0x18];
5755 u8 reserved_at_40[0x40];
5757 u8 packet_headers_log[128][0x8];
5759 u8 packet_syndrome[64][0x8];
5762 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5764 u8 reserved_at_10[0x10];
5766 u8 reserved_at_20[0x10];
5769 u8 reserved_at_40[0x40];
5772 struct mlx5_ifc_gen_eqe_in_bits {
5774 u8 reserved_at_10[0x10];
5776 u8 reserved_at_20[0x10];
5779 u8 reserved_at_40[0x18];
5782 u8 reserved_at_60[0x20];
5787 struct mlx5_ifc_gen_eq_out_bits {
5789 u8 reserved_at_8[0x18];
5793 u8 reserved_at_40[0x40];
5796 struct mlx5_ifc_enable_hca_out_bits {
5798 u8 reserved_at_8[0x18];
5802 u8 reserved_at_40[0x20];
5805 struct mlx5_ifc_enable_hca_in_bits {
5807 u8 reserved_at_10[0x10];
5809 u8 reserved_at_20[0x10];
5812 u8 reserved_at_40[0x10];
5813 u8 function_id[0x10];
5815 u8 reserved_at_60[0x20];
5818 struct mlx5_ifc_drain_dct_out_bits {
5820 u8 reserved_at_8[0x18];
5824 u8 reserved_at_40[0x40];
5827 struct mlx5_ifc_drain_dct_in_bits {
5829 u8 reserved_at_10[0x10];
5831 u8 reserved_at_20[0x10];
5834 u8 reserved_at_40[0x8];
5837 u8 reserved_at_60[0x20];
5840 struct mlx5_ifc_disable_hca_out_bits {
5842 u8 reserved_at_8[0x18];
5846 u8 reserved_at_40[0x20];
5849 struct mlx5_ifc_disable_hca_in_bits {
5851 u8 reserved_at_10[0x10];
5853 u8 reserved_at_20[0x10];
5856 u8 reserved_at_40[0x10];
5857 u8 function_id[0x10];
5859 u8 reserved_at_60[0x20];
5862 struct mlx5_ifc_detach_from_mcg_out_bits {
5864 u8 reserved_at_8[0x18];
5868 u8 reserved_at_40[0x40];
5871 struct mlx5_ifc_detach_from_mcg_in_bits {
5873 u8 reserved_at_10[0x10];
5875 u8 reserved_at_20[0x10];
5878 u8 reserved_at_40[0x8];
5881 u8 reserved_at_60[0x20];
5883 u8 multicast_gid[16][0x8];
5886 struct mlx5_ifc_destroy_xrq_out_bits {
5888 u8 reserved_at_8[0x18];
5892 u8 reserved_at_40[0x40];
5895 struct mlx5_ifc_destroy_xrq_in_bits {
5897 u8 reserved_at_10[0x10];
5899 u8 reserved_at_20[0x10];
5902 u8 reserved_at_40[0x8];
5905 u8 reserved_at_60[0x20];
5908 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5910 u8 reserved_at_8[0x18];
5914 u8 reserved_at_40[0x40];
5917 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5919 u8 reserved_at_10[0x10];
5921 u8 reserved_at_20[0x10];
5924 u8 reserved_at_40[0x8];
5927 u8 reserved_at_60[0x20];
5930 struct mlx5_ifc_destroy_tis_out_bits {
5932 u8 reserved_at_8[0x18];
5936 u8 reserved_at_40[0x40];
5939 struct mlx5_ifc_destroy_tis_in_bits {
5941 u8 reserved_at_10[0x10];
5943 u8 reserved_at_20[0x10];
5946 u8 reserved_at_40[0x8];
5949 u8 reserved_at_60[0x20];
5952 struct mlx5_ifc_destroy_tir_out_bits {
5954 u8 reserved_at_8[0x18];
5958 u8 reserved_at_40[0x40];
5961 struct mlx5_ifc_destroy_tir_in_bits {
5963 u8 reserved_at_10[0x10];
5965 u8 reserved_at_20[0x10];
5968 u8 reserved_at_40[0x8];
5971 u8 reserved_at_60[0x20];
5974 struct mlx5_ifc_destroy_srq_out_bits {
5976 u8 reserved_at_8[0x18];
5980 u8 reserved_at_40[0x40];
5983 struct mlx5_ifc_destroy_srq_in_bits {
5985 u8 reserved_at_10[0x10];
5987 u8 reserved_at_20[0x10];
5990 u8 reserved_at_40[0x8];
5993 u8 reserved_at_60[0x20];
5996 struct mlx5_ifc_destroy_sq_out_bits {
5998 u8 reserved_at_8[0x18];
6002 u8 reserved_at_40[0x40];
6005 struct mlx5_ifc_destroy_sq_in_bits {
6007 u8 reserved_at_10[0x10];
6009 u8 reserved_at_20[0x10];
6012 u8 reserved_at_40[0x8];
6015 u8 reserved_at_60[0x20];
6018 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6020 u8 reserved_at_8[0x18];
6024 u8 reserved_at_40[0x1c0];
6027 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6029 u8 reserved_at_10[0x10];
6031 u8 reserved_at_20[0x10];
6034 u8 scheduling_hierarchy[0x8];
6035 u8 reserved_at_48[0x18];
6037 u8 scheduling_element_id[0x20];
6039 u8 reserved_at_80[0x180];
6042 struct mlx5_ifc_destroy_rqt_out_bits {
6044 u8 reserved_at_8[0x18];
6048 u8 reserved_at_40[0x40];
6051 struct mlx5_ifc_destroy_rqt_in_bits {
6053 u8 reserved_at_10[0x10];
6055 u8 reserved_at_20[0x10];
6058 u8 reserved_at_40[0x8];
6061 u8 reserved_at_60[0x20];
6064 struct mlx5_ifc_destroy_rq_out_bits {
6066 u8 reserved_at_8[0x18];
6070 u8 reserved_at_40[0x40];
6073 struct mlx5_ifc_destroy_rq_in_bits {
6075 u8 reserved_at_10[0x10];
6077 u8 reserved_at_20[0x10];
6080 u8 reserved_at_40[0x8];
6083 u8 reserved_at_60[0x20];
6086 struct mlx5_ifc_set_delay_drop_params_in_bits {
6088 u8 reserved_at_10[0x10];
6090 u8 reserved_at_20[0x10];
6093 u8 reserved_at_40[0x20];
6095 u8 reserved_at_60[0x10];
6096 u8 delay_drop_timeout[0x10];
6099 struct mlx5_ifc_set_delay_drop_params_out_bits {
6101 u8 reserved_at_8[0x18];
6105 u8 reserved_at_40[0x40];
6108 struct mlx5_ifc_destroy_rmp_out_bits {
6110 u8 reserved_at_8[0x18];
6114 u8 reserved_at_40[0x40];
6117 struct mlx5_ifc_destroy_rmp_in_bits {
6119 u8 reserved_at_10[0x10];
6121 u8 reserved_at_20[0x10];
6124 u8 reserved_at_40[0x8];
6127 u8 reserved_at_60[0x20];
6130 struct mlx5_ifc_destroy_qp_out_bits {
6132 u8 reserved_at_8[0x18];
6136 u8 reserved_at_40[0x40];
6139 struct mlx5_ifc_destroy_qp_in_bits {
6141 u8 reserved_at_10[0x10];
6143 u8 reserved_at_20[0x10];
6146 u8 reserved_at_40[0x8];
6149 u8 reserved_at_60[0x20];
6152 struct mlx5_ifc_destroy_psv_out_bits {
6154 u8 reserved_at_8[0x18];
6158 u8 reserved_at_40[0x40];
6161 struct mlx5_ifc_destroy_psv_in_bits {
6163 u8 reserved_at_10[0x10];
6165 u8 reserved_at_20[0x10];
6168 u8 reserved_at_40[0x8];
6171 u8 reserved_at_60[0x20];
6174 struct mlx5_ifc_destroy_mkey_out_bits {
6176 u8 reserved_at_8[0x18];
6180 u8 reserved_at_40[0x40];
6183 struct mlx5_ifc_destroy_mkey_in_bits {
6185 u8 reserved_at_10[0x10];
6187 u8 reserved_at_20[0x10];
6190 u8 reserved_at_40[0x8];
6191 u8 mkey_index[0x18];
6193 u8 reserved_at_60[0x20];
6196 struct mlx5_ifc_destroy_flow_table_out_bits {
6198 u8 reserved_at_8[0x18];
6202 u8 reserved_at_40[0x40];
6205 struct mlx5_ifc_destroy_flow_table_in_bits {
6207 u8 reserved_at_10[0x10];
6209 u8 reserved_at_20[0x10];
6212 u8 other_vport[0x1];
6213 u8 reserved_at_41[0xf];
6214 u8 vport_number[0x10];
6216 u8 reserved_at_60[0x20];
6219 u8 reserved_at_88[0x18];
6221 u8 reserved_at_a0[0x8];
6224 u8 reserved_at_c0[0x140];
6227 struct mlx5_ifc_destroy_flow_group_out_bits {
6229 u8 reserved_at_8[0x18];
6233 u8 reserved_at_40[0x40];
6236 struct mlx5_ifc_destroy_flow_group_in_bits {
6238 u8 reserved_at_10[0x10];
6240 u8 reserved_at_20[0x10];
6243 u8 other_vport[0x1];
6244 u8 reserved_at_41[0xf];
6245 u8 vport_number[0x10];
6247 u8 reserved_at_60[0x20];
6250 u8 reserved_at_88[0x18];
6252 u8 reserved_at_a0[0x8];
6257 u8 reserved_at_e0[0x120];
6260 struct mlx5_ifc_destroy_eq_out_bits {
6262 u8 reserved_at_8[0x18];
6266 u8 reserved_at_40[0x40];
6269 struct mlx5_ifc_destroy_eq_in_bits {
6271 u8 reserved_at_10[0x10];
6273 u8 reserved_at_20[0x10];
6276 u8 reserved_at_40[0x18];
6279 u8 reserved_at_60[0x20];
6282 struct mlx5_ifc_destroy_dct_out_bits {
6284 u8 reserved_at_8[0x18];
6288 u8 reserved_at_40[0x40];
6291 struct mlx5_ifc_destroy_dct_in_bits {
6293 u8 reserved_at_10[0x10];
6295 u8 reserved_at_20[0x10];
6298 u8 reserved_at_40[0x8];
6301 u8 reserved_at_60[0x20];
6304 struct mlx5_ifc_destroy_cq_out_bits {
6306 u8 reserved_at_8[0x18];
6310 u8 reserved_at_40[0x40];
6313 struct mlx5_ifc_destroy_cq_in_bits {
6315 u8 reserved_at_10[0x10];
6317 u8 reserved_at_20[0x10];
6320 u8 reserved_at_40[0x8];
6323 u8 reserved_at_60[0x20];
6326 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6328 u8 reserved_at_8[0x18];
6332 u8 reserved_at_40[0x40];
6335 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6337 u8 reserved_at_10[0x10];
6339 u8 reserved_at_20[0x10];
6342 u8 reserved_at_40[0x20];
6344 u8 reserved_at_60[0x10];
6345 u8 vxlan_udp_port[0x10];
6348 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6350 u8 reserved_at_8[0x18];
6354 u8 reserved_at_40[0x40];
6357 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6359 u8 reserved_at_10[0x10];
6361 u8 reserved_at_20[0x10];
6364 u8 reserved_at_40[0x60];
6366 u8 reserved_at_a0[0x8];
6367 u8 table_index[0x18];
6369 u8 reserved_at_c0[0x140];
6372 struct mlx5_ifc_delete_fte_out_bits {
6374 u8 reserved_at_8[0x18];
6378 u8 reserved_at_40[0x40];
6381 struct mlx5_ifc_delete_fte_in_bits {
6383 u8 reserved_at_10[0x10];
6385 u8 reserved_at_20[0x10];
6388 u8 other_vport[0x1];
6389 u8 reserved_at_41[0xf];
6390 u8 vport_number[0x10];
6392 u8 reserved_at_60[0x20];
6395 u8 reserved_at_88[0x18];
6397 u8 reserved_at_a0[0x8];
6400 u8 reserved_at_c0[0x40];
6402 u8 flow_index[0x20];
6404 u8 reserved_at_120[0xe0];
6407 struct mlx5_ifc_dealloc_xrcd_out_bits {
6409 u8 reserved_at_8[0x18];
6413 u8 reserved_at_40[0x40];
6416 struct mlx5_ifc_dealloc_xrcd_in_bits {
6418 u8 reserved_at_10[0x10];
6420 u8 reserved_at_20[0x10];
6423 u8 reserved_at_40[0x8];
6426 u8 reserved_at_60[0x20];
6429 struct mlx5_ifc_dealloc_uar_out_bits {
6431 u8 reserved_at_8[0x18];
6435 u8 reserved_at_40[0x40];
6438 struct mlx5_ifc_dealloc_uar_in_bits {
6440 u8 reserved_at_10[0x10];
6442 u8 reserved_at_20[0x10];
6445 u8 reserved_at_40[0x8];
6448 u8 reserved_at_60[0x20];
6451 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6453 u8 reserved_at_8[0x18];
6457 u8 reserved_at_40[0x40];
6460 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6462 u8 reserved_at_10[0x10];
6464 u8 reserved_at_20[0x10];
6467 u8 reserved_at_40[0x8];
6468 u8 transport_domain[0x18];
6470 u8 reserved_at_60[0x20];
6473 struct mlx5_ifc_dealloc_q_counter_out_bits {
6475 u8 reserved_at_8[0x18];
6479 u8 reserved_at_40[0x40];
6482 struct mlx5_ifc_dealloc_q_counter_in_bits {
6484 u8 reserved_at_10[0x10];
6486 u8 reserved_at_20[0x10];
6489 u8 reserved_at_40[0x18];
6490 u8 counter_set_id[0x8];
6492 u8 reserved_at_60[0x20];
6495 struct mlx5_ifc_dealloc_pd_out_bits {
6497 u8 reserved_at_8[0x18];
6501 u8 reserved_at_40[0x40];
6504 struct mlx5_ifc_dealloc_pd_in_bits {
6506 u8 reserved_at_10[0x10];
6508 u8 reserved_at_20[0x10];
6511 u8 reserved_at_40[0x8];
6514 u8 reserved_at_60[0x20];
6517 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6519 u8 reserved_at_8[0x18];
6523 u8 reserved_at_40[0x40];
6526 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6528 u8 reserved_at_10[0x10];
6530 u8 reserved_at_20[0x10];
6533 u8 flow_counter_id[0x20];
6535 u8 reserved_at_60[0x20];
6538 struct mlx5_ifc_create_xrq_out_bits {
6540 u8 reserved_at_8[0x18];
6544 u8 reserved_at_40[0x8];
6547 u8 reserved_at_60[0x20];
6550 struct mlx5_ifc_create_xrq_in_bits {
6552 u8 reserved_at_10[0x10];
6554 u8 reserved_at_20[0x10];
6557 u8 reserved_at_40[0x40];
6559 struct mlx5_ifc_xrqc_bits xrq_context;
6562 struct mlx5_ifc_create_xrc_srq_out_bits {
6564 u8 reserved_at_8[0x18];
6568 u8 reserved_at_40[0x8];
6571 u8 reserved_at_60[0x20];
6574 struct mlx5_ifc_create_xrc_srq_in_bits {
6576 u8 reserved_at_10[0x10];
6578 u8 reserved_at_20[0x10];
6581 u8 reserved_at_40[0x40];
6583 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6585 u8 reserved_at_280[0x600];
6590 struct mlx5_ifc_create_tis_out_bits {
6592 u8 reserved_at_8[0x18];
6596 u8 reserved_at_40[0x8];
6599 u8 reserved_at_60[0x20];
6602 struct mlx5_ifc_create_tis_in_bits {
6604 u8 reserved_at_10[0x10];
6606 u8 reserved_at_20[0x10];
6609 u8 reserved_at_40[0xc0];
6611 struct mlx5_ifc_tisc_bits ctx;
6614 struct mlx5_ifc_create_tir_out_bits {
6616 u8 reserved_at_8[0x18];
6620 u8 reserved_at_40[0x8];
6623 u8 reserved_at_60[0x20];
6626 struct mlx5_ifc_create_tir_in_bits {
6628 u8 reserved_at_10[0x10];
6630 u8 reserved_at_20[0x10];
6633 u8 reserved_at_40[0xc0];
6635 struct mlx5_ifc_tirc_bits ctx;
6638 struct mlx5_ifc_create_srq_out_bits {
6640 u8 reserved_at_8[0x18];
6644 u8 reserved_at_40[0x8];
6647 u8 reserved_at_60[0x20];
6650 struct mlx5_ifc_create_srq_in_bits {
6652 u8 reserved_at_10[0x10];
6654 u8 reserved_at_20[0x10];
6657 u8 reserved_at_40[0x40];
6659 struct mlx5_ifc_srqc_bits srq_context_entry;
6661 u8 reserved_at_280[0x600];
6666 struct mlx5_ifc_create_sq_out_bits {
6668 u8 reserved_at_8[0x18];
6672 u8 reserved_at_40[0x8];
6675 u8 reserved_at_60[0x20];
6678 struct mlx5_ifc_create_sq_in_bits {
6680 u8 reserved_at_10[0x10];
6682 u8 reserved_at_20[0x10];
6685 u8 reserved_at_40[0xc0];
6687 struct mlx5_ifc_sqc_bits ctx;
6690 struct mlx5_ifc_create_scheduling_element_out_bits {
6692 u8 reserved_at_8[0x18];
6696 u8 reserved_at_40[0x40];
6698 u8 scheduling_element_id[0x20];
6700 u8 reserved_at_a0[0x160];
6703 struct mlx5_ifc_create_scheduling_element_in_bits {
6705 u8 reserved_at_10[0x10];
6707 u8 reserved_at_20[0x10];
6710 u8 scheduling_hierarchy[0x8];
6711 u8 reserved_at_48[0x18];
6713 u8 reserved_at_60[0xa0];
6715 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6717 u8 reserved_at_300[0x100];
6720 struct mlx5_ifc_create_rqt_out_bits {
6722 u8 reserved_at_8[0x18];
6726 u8 reserved_at_40[0x8];
6729 u8 reserved_at_60[0x20];
6732 struct mlx5_ifc_create_rqt_in_bits {
6734 u8 reserved_at_10[0x10];
6736 u8 reserved_at_20[0x10];
6739 u8 reserved_at_40[0xc0];
6741 struct mlx5_ifc_rqtc_bits rqt_context;
6744 struct mlx5_ifc_create_rq_out_bits {
6746 u8 reserved_at_8[0x18];
6750 u8 reserved_at_40[0x8];
6753 u8 reserved_at_60[0x20];
6756 struct mlx5_ifc_create_rq_in_bits {
6758 u8 reserved_at_10[0x10];
6760 u8 reserved_at_20[0x10];
6763 u8 reserved_at_40[0xc0];
6765 struct mlx5_ifc_rqc_bits ctx;
6768 struct mlx5_ifc_create_rmp_out_bits {
6770 u8 reserved_at_8[0x18];
6774 u8 reserved_at_40[0x8];
6777 u8 reserved_at_60[0x20];
6780 struct mlx5_ifc_create_rmp_in_bits {
6782 u8 reserved_at_10[0x10];
6784 u8 reserved_at_20[0x10];
6787 u8 reserved_at_40[0xc0];
6789 struct mlx5_ifc_rmpc_bits ctx;
6792 struct mlx5_ifc_create_qp_out_bits {
6794 u8 reserved_at_8[0x18];
6798 u8 reserved_at_40[0x8];
6801 u8 reserved_at_60[0x20];
6804 struct mlx5_ifc_create_qp_in_bits {
6806 u8 reserved_at_10[0x10];
6808 u8 reserved_at_20[0x10];
6811 u8 reserved_at_40[0x40];
6813 u8 opt_param_mask[0x20];
6815 u8 reserved_at_a0[0x20];
6817 struct mlx5_ifc_qpc_bits qpc;
6819 u8 reserved_at_800[0x80];
6824 struct mlx5_ifc_create_psv_out_bits {
6826 u8 reserved_at_8[0x18];
6830 u8 reserved_at_40[0x40];
6832 u8 reserved_at_80[0x8];
6833 u8 psv0_index[0x18];
6835 u8 reserved_at_a0[0x8];
6836 u8 psv1_index[0x18];
6838 u8 reserved_at_c0[0x8];
6839 u8 psv2_index[0x18];
6841 u8 reserved_at_e0[0x8];
6842 u8 psv3_index[0x18];
6845 struct mlx5_ifc_create_psv_in_bits {
6847 u8 reserved_at_10[0x10];
6849 u8 reserved_at_20[0x10];
6853 u8 reserved_at_44[0x4];
6856 u8 reserved_at_60[0x20];
6859 struct mlx5_ifc_create_mkey_out_bits {
6861 u8 reserved_at_8[0x18];
6865 u8 reserved_at_40[0x8];
6866 u8 mkey_index[0x18];
6868 u8 reserved_at_60[0x20];
6871 struct mlx5_ifc_create_mkey_in_bits {
6873 u8 reserved_at_10[0x10];
6875 u8 reserved_at_20[0x10];
6878 u8 reserved_at_40[0x20];
6881 u8 reserved_at_61[0x1f];
6883 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6885 u8 reserved_at_280[0x80];
6887 u8 translations_octword_actual_size[0x20];
6889 u8 reserved_at_320[0x560];
6891 u8 klm_pas_mtt[0][0x20];
6894 struct mlx5_ifc_create_flow_table_out_bits {
6896 u8 reserved_at_8[0x18];
6900 u8 reserved_at_40[0x8];
6903 u8 reserved_at_60[0x20];
6906 struct mlx5_ifc_flow_table_context_bits {
6909 u8 reserved_at_2[0x2];
6910 u8 table_miss_action[0x4];
6912 u8 reserved_at_10[0x8];
6915 u8 reserved_at_20[0x8];
6916 u8 table_miss_id[0x18];
6918 u8 reserved_at_40[0x8];
6919 u8 lag_master_next_table_id[0x18];
6921 u8 reserved_at_60[0xe0];
6924 struct mlx5_ifc_create_flow_table_in_bits {
6926 u8 reserved_at_10[0x10];
6928 u8 reserved_at_20[0x10];
6931 u8 other_vport[0x1];
6932 u8 reserved_at_41[0xf];
6933 u8 vport_number[0x10];
6935 u8 reserved_at_60[0x20];
6938 u8 reserved_at_88[0x18];
6940 u8 reserved_at_a0[0x20];
6942 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6945 struct mlx5_ifc_create_flow_group_out_bits {
6947 u8 reserved_at_8[0x18];
6951 u8 reserved_at_40[0x8];
6954 u8 reserved_at_60[0x20];
6958 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6959 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6960 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6963 struct mlx5_ifc_create_flow_group_in_bits {
6965 u8 reserved_at_10[0x10];
6967 u8 reserved_at_20[0x10];
6970 u8 other_vport[0x1];
6971 u8 reserved_at_41[0xf];
6972 u8 vport_number[0x10];
6974 u8 reserved_at_60[0x20];
6977 u8 reserved_at_88[0x18];
6979 u8 reserved_at_a0[0x8];
6982 u8 source_eswitch_owner_vhca_id_valid[0x1];
6984 u8 reserved_at_c1[0x1f];
6986 u8 start_flow_index[0x20];
6988 u8 reserved_at_100[0x20];
6990 u8 end_flow_index[0x20];
6992 u8 reserved_at_140[0xa0];
6994 u8 reserved_at_1e0[0x18];
6995 u8 match_criteria_enable[0x8];
6997 struct mlx5_ifc_fte_match_param_bits match_criteria;
6999 u8 reserved_at_1200[0xe00];
7002 struct mlx5_ifc_create_eq_out_bits {
7004 u8 reserved_at_8[0x18];
7008 u8 reserved_at_40[0x18];
7011 u8 reserved_at_60[0x20];
7014 struct mlx5_ifc_create_eq_in_bits {
7016 u8 reserved_at_10[0x10];
7018 u8 reserved_at_20[0x10];
7021 u8 reserved_at_40[0x40];
7023 struct mlx5_ifc_eqc_bits eq_context_entry;
7025 u8 reserved_at_280[0x40];
7027 u8 event_bitmask[0x40];
7029 u8 reserved_at_300[0x580];
7034 struct mlx5_ifc_create_dct_out_bits {
7036 u8 reserved_at_8[0x18];
7040 u8 reserved_at_40[0x8];
7043 u8 reserved_at_60[0x20];
7046 struct mlx5_ifc_create_dct_in_bits {
7048 u8 reserved_at_10[0x10];
7050 u8 reserved_at_20[0x10];
7053 u8 reserved_at_40[0x40];
7055 struct mlx5_ifc_dctc_bits dct_context_entry;
7057 u8 reserved_at_280[0x180];
7060 struct mlx5_ifc_create_cq_out_bits {
7062 u8 reserved_at_8[0x18];
7066 u8 reserved_at_40[0x8];
7069 u8 reserved_at_60[0x20];
7072 struct mlx5_ifc_create_cq_in_bits {
7074 u8 reserved_at_10[0x10];
7076 u8 reserved_at_20[0x10];
7079 u8 reserved_at_40[0x40];
7081 struct mlx5_ifc_cqc_bits cq_context;
7083 u8 reserved_at_280[0x600];
7088 struct mlx5_ifc_config_int_moderation_out_bits {
7090 u8 reserved_at_8[0x18];
7094 u8 reserved_at_40[0x4];
7096 u8 int_vector[0x10];
7098 u8 reserved_at_60[0x20];
7102 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7103 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7106 struct mlx5_ifc_config_int_moderation_in_bits {
7108 u8 reserved_at_10[0x10];
7110 u8 reserved_at_20[0x10];
7113 u8 reserved_at_40[0x4];
7115 u8 int_vector[0x10];
7117 u8 reserved_at_60[0x20];
7120 struct mlx5_ifc_attach_to_mcg_out_bits {
7122 u8 reserved_at_8[0x18];
7126 u8 reserved_at_40[0x40];
7129 struct mlx5_ifc_attach_to_mcg_in_bits {
7131 u8 reserved_at_10[0x10];
7133 u8 reserved_at_20[0x10];
7136 u8 reserved_at_40[0x8];
7139 u8 reserved_at_60[0x20];
7141 u8 multicast_gid[16][0x8];
7144 struct mlx5_ifc_arm_xrq_out_bits {
7146 u8 reserved_at_8[0x18];
7150 u8 reserved_at_40[0x40];
7153 struct mlx5_ifc_arm_xrq_in_bits {
7155 u8 reserved_at_10[0x10];
7157 u8 reserved_at_20[0x10];
7160 u8 reserved_at_40[0x8];
7163 u8 reserved_at_60[0x10];
7167 struct mlx5_ifc_arm_xrc_srq_out_bits {
7169 u8 reserved_at_8[0x18];
7173 u8 reserved_at_40[0x40];
7177 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7180 struct mlx5_ifc_arm_xrc_srq_in_bits {
7182 u8 reserved_at_10[0x10];
7184 u8 reserved_at_20[0x10];
7187 u8 reserved_at_40[0x8];
7190 u8 reserved_at_60[0x10];
7194 struct mlx5_ifc_arm_rq_out_bits {
7196 u8 reserved_at_8[0x18];
7200 u8 reserved_at_40[0x40];
7204 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7205 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7208 struct mlx5_ifc_arm_rq_in_bits {
7210 u8 reserved_at_10[0x10];
7212 u8 reserved_at_20[0x10];
7215 u8 reserved_at_40[0x8];
7216 u8 srq_number[0x18];
7218 u8 reserved_at_60[0x10];
7222 struct mlx5_ifc_arm_dct_out_bits {
7224 u8 reserved_at_8[0x18];
7228 u8 reserved_at_40[0x40];
7231 struct mlx5_ifc_arm_dct_in_bits {
7233 u8 reserved_at_10[0x10];
7235 u8 reserved_at_20[0x10];
7238 u8 reserved_at_40[0x8];
7239 u8 dct_number[0x18];
7241 u8 reserved_at_60[0x20];
7244 struct mlx5_ifc_alloc_xrcd_out_bits {
7246 u8 reserved_at_8[0x18];
7250 u8 reserved_at_40[0x8];
7253 u8 reserved_at_60[0x20];
7256 struct mlx5_ifc_alloc_xrcd_in_bits {
7258 u8 reserved_at_10[0x10];
7260 u8 reserved_at_20[0x10];
7263 u8 reserved_at_40[0x40];
7266 struct mlx5_ifc_alloc_uar_out_bits {
7268 u8 reserved_at_8[0x18];
7272 u8 reserved_at_40[0x8];
7275 u8 reserved_at_60[0x20];
7278 struct mlx5_ifc_alloc_uar_in_bits {
7280 u8 reserved_at_10[0x10];
7282 u8 reserved_at_20[0x10];
7285 u8 reserved_at_40[0x40];
7288 struct mlx5_ifc_alloc_transport_domain_out_bits {
7290 u8 reserved_at_8[0x18];
7294 u8 reserved_at_40[0x8];
7295 u8 transport_domain[0x18];
7297 u8 reserved_at_60[0x20];
7300 struct mlx5_ifc_alloc_transport_domain_in_bits {
7302 u8 reserved_at_10[0x10];
7304 u8 reserved_at_20[0x10];
7307 u8 reserved_at_40[0x40];
7310 struct mlx5_ifc_alloc_q_counter_out_bits {
7312 u8 reserved_at_8[0x18];
7316 u8 reserved_at_40[0x18];
7317 u8 counter_set_id[0x8];
7319 u8 reserved_at_60[0x20];
7322 struct mlx5_ifc_alloc_q_counter_in_bits {
7324 u8 reserved_at_10[0x10];
7326 u8 reserved_at_20[0x10];
7329 u8 reserved_at_40[0x40];
7332 struct mlx5_ifc_alloc_pd_out_bits {
7334 u8 reserved_at_8[0x18];
7338 u8 reserved_at_40[0x8];
7341 u8 reserved_at_60[0x20];
7344 struct mlx5_ifc_alloc_pd_in_bits {
7346 u8 reserved_at_10[0x10];
7348 u8 reserved_at_20[0x10];
7351 u8 reserved_at_40[0x40];
7354 struct mlx5_ifc_alloc_flow_counter_out_bits {
7356 u8 reserved_at_8[0x18];
7360 u8 flow_counter_id[0x20];
7362 u8 reserved_at_60[0x20];
7365 struct mlx5_ifc_alloc_flow_counter_in_bits {
7367 u8 reserved_at_10[0x10];
7369 u8 reserved_at_20[0x10];
7372 u8 reserved_at_40[0x40];
7375 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7377 u8 reserved_at_8[0x18];
7381 u8 reserved_at_40[0x40];
7384 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7386 u8 reserved_at_10[0x10];
7388 u8 reserved_at_20[0x10];
7391 u8 reserved_at_40[0x20];
7393 u8 reserved_at_60[0x10];
7394 u8 vxlan_udp_port[0x10];
7397 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7399 u8 reserved_at_8[0x18];
7403 u8 reserved_at_40[0x40];
7406 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7408 u8 reserved_at_10[0x10];
7410 u8 reserved_at_20[0x10];
7413 u8 reserved_at_40[0x10];
7414 u8 rate_limit_index[0x10];
7416 u8 reserved_at_60[0x20];
7418 u8 rate_limit[0x20];
7420 u8 burst_upper_bound[0x20];
7422 u8 reserved_at_c0[0x10];
7423 u8 typical_packet_size[0x10];
7425 u8 reserved_at_e0[0x120];
7428 struct mlx5_ifc_access_register_out_bits {
7430 u8 reserved_at_8[0x18];
7434 u8 reserved_at_40[0x40];
7436 u8 register_data[0][0x20];
7440 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7441 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7444 struct mlx5_ifc_access_register_in_bits {
7446 u8 reserved_at_10[0x10];
7448 u8 reserved_at_20[0x10];
7451 u8 reserved_at_40[0x10];
7452 u8 register_id[0x10];
7456 u8 register_data[0][0x20];
7459 struct mlx5_ifc_sltp_reg_bits {
7464 u8 reserved_at_12[0x2];
7466 u8 reserved_at_18[0x8];
7468 u8 reserved_at_20[0x20];
7470 u8 reserved_at_40[0x7];
7476 u8 reserved_at_60[0xc];
7477 u8 ob_preemp_mode[0x4];
7481 u8 reserved_at_80[0x20];
7484 struct mlx5_ifc_slrg_reg_bits {
7489 u8 reserved_at_12[0x2];
7491 u8 reserved_at_18[0x8];
7493 u8 time_to_link_up[0x10];
7494 u8 reserved_at_30[0xc];
7495 u8 grade_lane_speed[0x4];
7497 u8 grade_version[0x8];
7500 u8 reserved_at_60[0x4];
7501 u8 height_grade_type[0x4];
7502 u8 height_grade[0x18];
7507 u8 reserved_at_a0[0x10];
7508 u8 height_sigma[0x10];
7510 u8 reserved_at_c0[0x20];
7512 u8 reserved_at_e0[0x4];
7513 u8 phase_grade_type[0x4];
7514 u8 phase_grade[0x18];
7516 u8 reserved_at_100[0x8];
7517 u8 phase_eo_pos[0x8];
7518 u8 reserved_at_110[0x8];
7519 u8 phase_eo_neg[0x8];
7521 u8 ffe_set_tested[0x10];
7522 u8 test_errors_per_lane[0x10];
7525 struct mlx5_ifc_pvlc_reg_bits {
7526 u8 reserved_at_0[0x8];
7528 u8 reserved_at_10[0x10];
7530 u8 reserved_at_20[0x1c];
7533 u8 reserved_at_40[0x1c];
7536 u8 reserved_at_60[0x1c];
7537 u8 vl_operational[0x4];
7540 struct mlx5_ifc_pude_reg_bits {
7543 u8 reserved_at_10[0x4];
7544 u8 admin_status[0x4];
7545 u8 reserved_at_18[0x4];
7546 u8 oper_status[0x4];
7548 u8 reserved_at_20[0x60];
7551 struct mlx5_ifc_ptys_reg_bits {
7552 u8 reserved_at_0[0x1];
7553 u8 an_disable_admin[0x1];
7554 u8 an_disable_cap[0x1];
7555 u8 reserved_at_3[0x5];
7557 u8 reserved_at_10[0xd];
7561 u8 reserved_at_24[0x3c];
7563 u8 eth_proto_capability[0x20];
7565 u8 ib_link_width_capability[0x10];
7566 u8 ib_proto_capability[0x10];
7568 u8 reserved_at_a0[0x20];
7570 u8 eth_proto_admin[0x20];
7572 u8 ib_link_width_admin[0x10];
7573 u8 ib_proto_admin[0x10];
7575 u8 reserved_at_100[0x20];
7577 u8 eth_proto_oper[0x20];
7579 u8 ib_link_width_oper[0x10];
7580 u8 ib_proto_oper[0x10];
7582 u8 reserved_at_160[0x1c];
7583 u8 connector_type[0x4];
7585 u8 eth_proto_lp_advertise[0x20];
7587 u8 reserved_at_1a0[0x60];
7590 struct mlx5_ifc_mlcr_reg_bits {
7591 u8 reserved_at_0[0x8];
7593 u8 reserved_at_10[0x20];
7595 u8 beacon_duration[0x10];
7596 u8 reserved_at_40[0x10];
7598 u8 beacon_remain[0x10];
7601 struct mlx5_ifc_ptas_reg_bits {
7602 u8 reserved_at_0[0x20];
7604 u8 algorithm_options[0x10];
7605 u8 reserved_at_30[0x4];
7606 u8 repetitions_mode[0x4];
7607 u8 num_of_repetitions[0x8];
7609 u8 grade_version[0x8];
7610 u8 height_grade_type[0x4];
7611 u8 phase_grade_type[0x4];
7612 u8 height_grade_weight[0x8];
7613 u8 phase_grade_weight[0x8];
7615 u8 gisim_measure_bits[0x10];
7616 u8 adaptive_tap_measure_bits[0x10];
7618 u8 ber_bath_high_error_threshold[0x10];
7619 u8 ber_bath_mid_error_threshold[0x10];
7621 u8 ber_bath_low_error_threshold[0x10];
7622 u8 one_ratio_high_threshold[0x10];
7624 u8 one_ratio_high_mid_threshold[0x10];
7625 u8 one_ratio_low_mid_threshold[0x10];
7627 u8 one_ratio_low_threshold[0x10];
7628 u8 ndeo_error_threshold[0x10];
7630 u8 mixer_offset_step_size[0x10];
7631 u8 reserved_at_110[0x8];
7632 u8 mix90_phase_for_voltage_bath[0x8];
7634 u8 mixer_offset_start[0x10];
7635 u8 mixer_offset_end[0x10];
7637 u8 reserved_at_140[0x15];
7638 u8 ber_test_time[0xb];
7641 struct mlx5_ifc_pspa_reg_bits {
7645 u8 reserved_at_18[0x8];
7647 u8 reserved_at_20[0x20];
7650 struct mlx5_ifc_pqdr_reg_bits {
7651 u8 reserved_at_0[0x8];
7653 u8 reserved_at_10[0x5];
7655 u8 reserved_at_18[0x6];
7658 u8 reserved_at_20[0x20];
7660 u8 reserved_at_40[0x10];
7661 u8 min_threshold[0x10];
7663 u8 reserved_at_60[0x10];
7664 u8 max_threshold[0x10];
7666 u8 reserved_at_80[0x10];
7667 u8 mark_probability_denominator[0x10];
7669 u8 reserved_at_a0[0x60];
7672 struct mlx5_ifc_ppsc_reg_bits {
7673 u8 reserved_at_0[0x8];
7675 u8 reserved_at_10[0x10];
7677 u8 reserved_at_20[0x60];
7679 u8 reserved_at_80[0x1c];
7682 u8 reserved_at_a0[0x1c];
7683 u8 wrps_status[0x4];
7685 u8 reserved_at_c0[0x8];
7686 u8 up_threshold[0x8];
7687 u8 reserved_at_d0[0x8];
7688 u8 down_threshold[0x8];
7690 u8 reserved_at_e0[0x20];
7692 u8 reserved_at_100[0x1c];
7695 u8 reserved_at_120[0x1c];
7696 u8 srps_status[0x4];
7698 u8 reserved_at_140[0x40];
7701 struct mlx5_ifc_pplr_reg_bits {
7702 u8 reserved_at_0[0x8];
7704 u8 reserved_at_10[0x10];
7706 u8 reserved_at_20[0x8];
7708 u8 reserved_at_30[0x8];
7712 struct mlx5_ifc_pplm_reg_bits {
7713 u8 reserved_at_0[0x8];
7715 u8 reserved_at_10[0x10];
7717 u8 reserved_at_20[0x20];
7719 u8 port_profile_mode[0x8];
7720 u8 static_port_profile[0x8];
7721 u8 active_port_profile[0x8];
7722 u8 reserved_at_58[0x8];
7724 u8 retransmission_active[0x8];
7725 u8 fec_mode_active[0x18];
7727 u8 reserved_at_80[0x20];
7730 struct mlx5_ifc_ppcnt_reg_bits {
7734 u8 reserved_at_12[0x8];
7738 u8 reserved_at_21[0x1c];
7741 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7744 struct mlx5_ifc_mpcnt_reg_bits {
7745 u8 reserved_at_0[0x8];
7747 u8 reserved_at_10[0xa];
7751 u8 reserved_at_21[0x1f];
7753 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7756 struct mlx5_ifc_ppad_reg_bits {
7757 u8 reserved_at_0[0x3];
7759 u8 reserved_at_4[0x4];
7765 u8 reserved_at_40[0x40];
7768 struct mlx5_ifc_pmtu_reg_bits {
7769 u8 reserved_at_0[0x8];
7771 u8 reserved_at_10[0x10];
7774 u8 reserved_at_30[0x10];
7777 u8 reserved_at_50[0x10];
7780 u8 reserved_at_70[0x10];
7783 struct mlx5_ifc_pmpr_reg_bits {
7784 u8 reserved_at_0[0x8];
7786 u8 reserved_at_10[0x10];
7788 u8 reserved_at_20[0x18];
7789 u8 attenuation_5g[0x8];
7791 u8 reserved_at_40[0x18];
7792 u8 attenuation_7g[0x8];
7794 u8 reserved_at_60[0x18];
7795 u8 attenuation_12g[0x8];
7798 struct mlx5_ifc_pmpe_reg_bits {
7799 u8 reserved_at_0[0x8];
7801 u8 reserved_at_10[0xc];
7802 u8 module_status[0x4];
7804 u8 reserved_at_20[0x60];
7807 struct mlx5_ifc_pmpc_reg_bits {
7808 u8 module_state_updated[32][0x8];
7811 struct mlx5_ifc_pmlpn_reg_bits {
7812 u8 reserved_at_0[0x4];
7813 u8 mlpn_status[0x4];
7815 u8 reserved_at_10[0x10];
7818 u8 reserved_at_21[0x1f];
7821 struct mlx5_ifc_pmlp_reg_bits {
7823 u8 reserved_at_1[0x7];
7825 u8 reserved_at_10[0x8];
7828 u8 lane0_module_mapping[0x20];
7830 u8 lane1_module_mapping[0x20];
7832 u8 lane2_module_mapping[0x20];
7834 u8 lane3_module_mapping[0x20];
7836 u8 reserved_at_a0[0x160];
7839 struct mlx5_ifc_pmaos_reg_bits {
7840 u8 reserved_at_0[0x8];
7842 u8 reserved_at_10[0x4];
7843 u8 admin_status[0x4];
7844 u8 reserved_at_18[0x4];
7845 u8 oper_status[0x4];
7849 u8 reserved_at_22[0x1c];
7852 u8 reserved_at_40[0x40];
7855 struct mlx5_ifc_plpc_reg_bits {
7856 u8 reserved_at_0[0x4];
7858 u8 reserved_at_10[0x4];
7860 u8 reserved_at_18[0x8];
7862 u8 reserved_at_20[0x10];
7863 u8 lane_speed[0x10];
7865 u8 reserved_at_40[0x17];
7867 u8 fec_mode_policy[0x8];
7869 u8 retransmission_capability[0x8];
7870 u8 fec_mode_capability[0x18];
7872 u8 retransmission_support_admin[0x8];
7873 u8 fec_mode_support_admin[0x18];
7875 u8 retransmission_request_admin[0x8];
7876 u8 fec_mode_request_admin[0x18];
7878 u8 reserved_at_c0[0x80];
7881 struct mlx5_ifc_plib_reg_bits {
7882 u8 reserved_at_0[0x8];
7884 u8 reserved_at_10[0x8];
7887 u8 reserved_at_20[0x60];
7890 struct mlx5_ifc_plbf_reg_bits {
7891 u8 reserved_at_0[0x8];
7893 u8 reserved_at_10[0xd];
7896 u8 reserved_at_20[0x20];
7899 struct mlx5_ifc_pipg_reg_bits {
7900 u8 reserved_at_0[0x8];
7902 u8 reserved_at_10[0x10];
7905 u8 reserved_at_21[0x19];
7907 u8 reserved_at_3e[0x2];
7910 struct mlx5_ifc_pifr_reg_bits {
7911 u8 reserved_at_0[0x8];
7913 u8 reserved_at_10[0x10];
7915 u8 reserved_at_20[0xe0];
7917 u8 port_filter[8][0x20];
7919 u8 port_filter_update_en[8][0x20];
7922 struct mlx5_ifc_pfcc_reg_bits {
7923 u8 reserved_at_0[0x8];
7925 u8 reserved_at_10[0xb];
7926 u8 ppan_mask_n[0x1];
7927 u8 minor_stall_mask[0x1];
7928 u8 critical_stall_mask[0x1];
7929 u8 reserved_at_1e[0x2];
7932 u8 reserved_at_24[0x4];
7933 u8 prio_mask_tx[0x8];
7934 u8 reserved_at_30[0x8];
7935 u8 prio_mask_rx[0x8];
7939 u8 pptx_mask_n[0x1];
7940 u8 reserved_at_43[0x5];
7942 u8 reserved_at_50[0x10];
7946 u8 pprx_mask_n[0x1];
7947 u8 reserved_at_63[0x5];
7949 u8 reserved_at_70[0x10];
7951 u8 device_stall_minor_watermark[0x10];
7952 u8 device_stall_critical_watermark[0x10];
7954 u8 reserved_at_a0[0x60];
7957 struct mlx5_ifc_pelc_reg_bits {
7959 u8 reserved_at_4[0x4];
7961 u8 reserved_at_10[0x10];
7964 u8 op_capability[0x8];
7970 u8 capability[0x40];
7976 u8 reserved_at_140[0x80];
7979 struct mlx5_ifc_peir_reg_bits {
7980 u8 reserved_at_0[0x8];
7982 u8 reserved_at_10[0x10];
7984 u8 reserved_at_20[0xc];
7985 u8 error_count[0x4];
7986 u8 reserved_at_30[0x10];
7988 u8 reserved_at_40[0xc];
7990 u8 reserved_at_50[0x8];
7994 struct mlx5_ifc_pcam_enhanced_features_bits {
7995 u8 reserved_at_0[0x76];
7998 u8 reserved_at_77[0x4];
7999 u8 rx_buffer_fullness_counters[0x1];
8000 u8 ptys_connector_type[0x1];
8001 u8 reserved_at_7d[0x1];
8002 u8 ppcnt_discard_group[0x1];
8003 u8 ppcnt_statistical_group[0x1];
8006 struct mlx5_ifc_pcam_reg_bits {
8007 u8 reserved_at_0[0x8];
8008 u8 feature_group[0x8];
8009 u8 reserved_at_10[0x8];
8010 u8 access_reg_group[0x8];
8012 u8 reserved_at_20[0x20];
8015 u8 reserved_at_0[0x80];
8016 } port_access_reg_cap_mask;
8018 u8 reserved_at_c0[0x80];
8021 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8022 u8 reserved_at_0[0x80];
8025 u8 reserved_at_1c0[0xc0];
8028 struct mlx5_ifc_mcam_enhanced_features_bits {
8029 u8 reserved_at_0[0x7b];
8030 u8 pcie_outbound_stalled[0x1];
8031 u8 tx_overflow_buffer_pkt[0x1];
8032 u8 mtpps_enh_out_per_adj[0x1];
8034 u8 pcie_performance_group[0x1];
8037 struct mlx5_ifc_mcam_access_reg_bits {
8038 u8 reserved_at_0[0x1c];
8042 u8 reserved_at_1f[0x1];
8044 u8 regs_95_to_64[0x20];
8045 u8 regs_63_to_32[0x20];
8046 u8 regs_31_to_0[0x20];
8049 struct mlx5_ifc_mcam_reg_bits {
8050 u8 reserved_at_0[0x8];
8051 u8 feature_group[0x8];
8052 u8 reserved_at_10[0x8];
8053 u8 access_reg_group[0x8];
8055 u8 reserved_at_20[0x20];
8058 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8059 u8 reserved_at_0[0x80];
8060 } mng_access_reg_cap_mask;
8062 u8 reserved_at_c0[0x80];
8065 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8066 u8 reserved_at_0[0x80];
8067 } mng_feature_cap_mask;
8069 u8 reserved_at_1c0[0x80];
8072 struct mlx5_ifc_qcam_access_reg_cap_mask {
8073 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8075 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8079 u8 qcam_access_reg_cap_mask_0[0x1];
8082 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8083 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8084 u8 qpts_trust_both[0x1];
8087 struct mlx5_ifc_qcam_reg_bits {
8088 u8 reserved_at_0[0x8];
8089 u8 feature_group[0x8];
8090 u8 reserved_at_10[0x8];
8091 u8 access_reg_group[0x8];
8092 u8 reserved_at_20[0x20];
8095 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8096 u8 reserved_at_0[0x80];
8097 } qos_access_reg_cap_mask;
8099 u8 reserved_at_c0[0x80];
8102 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8103 u8 reserved_at_0[0x80];
8104 } qos_feature_cap_mask;
8106 u8 reserved_at_1c0[0x80];
8109 struct mlx5_ifc_pcap_reg_bits {
8110 u8 reserved_at_0[0x8];
8112 u8 reserved_at_10[0x10];
8114 u8 port_capability_mask[4][0x20];
8117 struct mlx5_ifc_paos_reg_bits {
8120 u8 reserved_at_10[0x4];
8121 u8 admin_status[0x4];
8122 u8 reserved_at_18[0x4];
8123 u8 oper_status[0x4];
8127 u8 reserved_at_22[0x1c];
8130 u8 reserved_at_40[0x40];
8133 struct mlx5_ifc_pamp_reg_bits {
8134 u8 reserved_at_0[0x8];
8135 u8 opamp_group[0x8];
8136 u8 reserved_at_10[0xc];
8137 u8 opamp_group_type[0x4];
8139 u8 start_index[0x10];
8140 u8 reserved_at_30[0x4];
8141 u8 num_of_indices[0xc];
8143 u8 index_data[18][0x10];
8146 struct mlx5_ifc_pcmr_reg_bits {
8147 u8 reserved_at_0[0x8];
8149 u8 reserved_at_10[0x2e];
8151 u8 reserved_at_3f[0x1f];
8153 u8 reserved_at_5f[0x1];
8156 struct mlx5_ifc_lane_2_module_mapping_bits {
8157 u8 reserved_at_0[0x6];
8159 u8 reserved_at_8[0x6];
8161 u8 reserved_at_10[0x8];
8165 struct mlx5_ifc_bufferx_reg_bits {
8166 u8 reserved_at_0[0x6];
8169 u8 reserved_at_8[0xc];
8172 u8 xoff_threshold[0x10];
8173 u8 xon_threshold[0x10];
8176 struct mlx5_ifc_set_node_in_bits {
8177 u8 node_description[64][0x8];
8180 struct mlx5_ifc_register_power_settings_bits {
8181 u8 reserved_at_0[0x18];
8182 u8 power_settings_level[0x8];
8184 u8 reserved_at_20[0x60];
8187 struct mlx5_ifc_register_host_endianness_bits {
8189 u8 reserved_at_1[0x1f];
8191 u8 reserved_at_20[0x60];
8194 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8195 u8 reserved_at_0[0x20];
8199 u8 addressh_63_32[0x20];
8201 u8 addressl_31_0[0x20];
8204 struct mlx5_ifc_ud_adrs_vector_bits {
8208 u8 reserved_at_41[0x7];
8209 u8 destination_qp_dct[0x18];
8211 u8 static_rate[0x4];
8212 u8 sl_eth_prio[0x4];
8215 u8 rlid_udp_sport[0x10];
8217 u8 reserved_at_80[0x20];
8219 u8 rmac_47_16[0x20];
8225 u8 reserved_at_e0[0x1];
8227 u8 reserved_at_e2[0x2];
8228 u8 src_addr_index[0x8];
8229 u8 flow_label[0x14];
8231 u8 rgid_rip[16][0x8];
8234 struct mlx5_ifc_pages_req_event_bits {
8235 u8 reserved_at_0[0x10];
8236 u8 function_id[0x10];
8240 u8 reserved_at_40[0xa0];
8243 struct mlx5_ifc_eqe_bits {
8244 u8 reserved_at_0[0x8];
8246 u8 reserved_at_10[0x8];
8247 u8 event_sub_type[0x8];
8249 u8 reserved_at_20[0xe0];
8251 union mlx5_ifc_event_auto_bits event_data;
8253 u8 reserved_at_1e0[0x10];
8255 u8 reserved_at_1f8[0x7];
8260 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8263 struct mlx5_ifc_cmd_queue_entry_bits {
8265 u8 reserved_at_8[0x18];
8267 u8 input_length[0x20];
8269 u8 input_mailbox_pointer_63_32[0x20];
8271 u8 input_mailbox_pointer_31_9[0x17];
8272 u8 reserved_at_77[0x9];
8274 u8 command_input_inline_data[16][0x8];
8276 u8 command_output_inline_data[16][0x8];
8278 u8 output_mailbox_pointer_63_32[0x20];
8280 u8 output_mailbox_pointer_31_9[0x17];
8281 u8 reserved_at_1b7[0x9];
8283 u8 output_length[0x20];
8287 u8 reserved_at_1f0[0x8];
8292 struct mlx5_ifc_cmd_out_bits {
8294 u8 reserved_at_8[0x18];
8298 u8 command_output[0x20];
8301 struct mlx5_ifc_cmd_in_bits {
8303 u8 reserved_at_10[0x10];
8305 u8 reserved_at_20[0x10];
8308 u8 command[0][0x20];
8311 struct mlx5_ifc_cmd_if_box_bits {
8312 u8 mailbox_data[512][0x8];
8314 u8 reserved_at_1000[0x180];
8316 u8 next_pointer_63_32[0x20];
8318 u8 next_pointer_31_10[0x16];
8319 u8 reserved_at_11b6[0xa];
8321 u8 block_number[0x20];
8323 u8 reserved_at_11e0[0x8];
8325 u8 ctrl_signature[0x8];
8329 struct mlx5_ifc_mtt_bits {
8330 u8 ptag_63_32[0x20];
8333 u8 reserved_at_38[0x6];
8338 struct mlx5_ifc_query_wol_rol_out_bits {
8340 u8 reserved_at_8[0x18];
8344 u8 reserved_at_40[0x10];
8348 u8 reserved_at_60[0x20];
8351 struct mlx5_ifc_query_wol_rol_in_bits {
8353 u8 reserved_at_10[0x10];
8355 u8 reserved_at_20[0x10];
8358 u8 reserved_at_40[0x40];
8361 struct mlx5_ifc_set_wol_rol_out_bits {
8363 u8 reserved_at_8[0x18];
8367 u8 reserved_at_40[0x40];
8370 struct mlx5_ifc_set_wol_rol_in_bits {
8372 u8 reserved_at_10[0x10];
8374 u8 reserved_at_20[0x10];
8377 u8 rol_mode_valid[0x1];
8378 u8 wol_mode_valid[0x1];
8379 u8 reserved_at_42[0xe];
8383 u8 reserved_at_60[0x20];
8387 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8388 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8389 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8393 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8394 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8395 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8399 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8400 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8401 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8402 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8403 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8404 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8405 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8406 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8407 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8408 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8409 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8412 struct mlx5_ifc_initial_seg_bits {
8413 u8 fw_rev_minor[0x10];
8414 u8 fw_rev_major[0x10];
8416 u8 cmd_interface_rev[0x10];
8417 u8 fw_rev_subminor[0x10];
8419 u8 reserved_at_40[0x40];
8421 u8 cmdq_phy_addr_63_32[0x20];
8423 u8 cmdq_phy_addr_31_12[0x14];
8424 u8 reserved_at_b4[0x2];
8425 u8 nic_interface[0x2];
8426 u8 log_cmdq_size[0x4];
8427 u8 log_cmdq_stride[0x4];
8429 u8 command_doorbell_vector[0x20];
8431 u8 reserved_at_e0[0xf00];
8433 u8 initializing[0x1];
8434 u8 reserved_at_fe1[0x4];
8435 u8 nic_interface_supported[0x3];
8436 u8 reserved_at_fe8[0x18];
8438 struct mlx5_ifc_health_buffer_bits health_buffer;
8440 u8 no_dram_nic_offset[0x20];
8442 u8 reserved_at_1220[0x6e40];
8444 u8 reserved_at_8060[0x1f];
8447 u8 health_syndrome[0x8];
8448 u8 health_counter[0x18];
8450 u8 reserved_at_80a0[0x17fc0];
8453 struct mlx5_ifc_mtpps_reg_bits {
8454 u8 reserved_at_0[0xc];
8455 u8 cap_number_of_pps_pins[0x4];
8456 u8 reserved_at_10[0x4];
8457 u8 cap_max_num_of_pps_in_pins[0x4];
8458 u8 reserved_at_18[0x4];
8459 u8 cap_max_num_of_pps_out_pins[0x4];
8461 u8 reserved_at_20[0x24];
8462 u8 cap_pin_3_mode[0x4];
8463 u8 reserved_at_48[0x4];
8464 u8 cap_pin_2_mode[0x4];
8465 u8 reserved_at_50[0x4];
8466 u8 cap_pin_1_mode[0x4];
8467 u8 reserved_at_58[0x4];
8468 u8 cap_pin_0_mode[0x4];
8470 u8 reserved_at_60[0x4];
8471 u8 cap_pin_7_mode[0x4];
8472 u8 reserved_at_68[0x4];
8473 u8 cap_pin_6_mode[0x4];
8474 u8 reserved_at_70[0x4];
8475 u8 cap_pin_5_mode[0x4];
8476 u8 reserved_at_78[0x4];
8477 u8 cap_pin_4_mode[0x4];
8479 u8 field_select[0x20];
8480 u8 reserved_at_a0[0x60];
8483 u8 reserved_at_101[0xb];
8485 u8 reserved_at_110[0x4];
8489 u8 reserved_at_120[0x20];
8491 u8 time_stamp[0x40];
8493 u8 out_pulse_duration[0x10];
8494 u8 out_periodic_adjustment[0x10];
8495 u8 enhanced_out_periodic_adjustment[0x20];
8497 u8 reserved_at_1c0[0x20];
8500 struct mlx5_ifc_mtppse_reg_bits {
8501 u8 reserved_at_0[0x18];
8504 u8 reserved_at_21[0x1b];
8505 u8 event_generation_mode[0x4];
8506 u8 reserved_at_40[0x40];
8509 struct mlx5_ifc_mcqi_cap_bits {
8510 u8 supported_info_bitmask[0x20];
8512 u8 component_size[0x20];
8514 u8 max_component_size[0x20];
8516 u8 log_mcda_word_size[0x4];
8517 u8 reserved_at_64[0xc];
8518 u8 mcda_max_write_size[0x10];
8521 u8 reserved_at_81[0x1];
8522 u8 match_chip_id[0x1];
8524 u8 check_user_timestamp[0x1];
8525 u8 match_base_guid_mac[0x1];
8526 u8 reserved_at_86[0x1a];
8529 struct mlx5_ifc_mcqi_reg_bits {
8530 u8 read_pending_component[0x1];
8531 u8 reserved_at_1[0xf];
8532 u8 component_index[0x10];
8534 u8 reserved_at_20[0x20];
8536 u8 reserved_at_40[0x1b];
8543 u8 reserved_at_a0[0x10];
8549 struct mlx5_ifc_mcc_reg_bits {
8550 u8 reserved_at_0[0x4];
8551 u8 time_elapsed_since_last_cmd[0xc];
8552 u8 reserved_at_10[0x8];
8553 u8 instruction[0x8];
8555 u8 reserved_at_20[0x10];
8556 u8 component_index[0x10];
8558 u8 reserved_at_40[0x8];
8559 u8 update_handle[0x18];
8561 u8 handle_owner_type[0x4];
8562 u8 handle_owner_host_id[0x4];
8563 u8 reserved_at_68[0x1];
8564 u8 control_progress[0x7];
8566 u8 reserved_at_78[0x4];
8567 u8 control_state[0x4];
8569 u8 component_size[0x20];
8571 u8 reserved_at_a0[0x60];
8574 struct mlx5_ifc_mcda_reg_bits {
8575 u8 reserved_at_0[0x8];
8576 u8 update_handle[0x18];
8580 u8 reserved_at_40[0x10];
8583 u8 reserved_at_60[0x20];
8588 union mlx5_ifc_ports_control_registers_document_bits {
8589 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8590 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8591 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8592 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8593 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8594 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8595 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8596 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8597 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8598 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8599 struct mlx5_ifc_paos_reg_bits paos_reg;
8600 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8601 struct mlx5_ifc_peir_reg_bits peir_reg;
8602 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8603 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8604 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8605 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8606 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8607 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8608 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8609 struct mlx5_ifc_plib_reg_bits plib_reg;
8610 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8611 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8612 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8613 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8614 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8615 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8616 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8617 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8618 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8619 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8620 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8621 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8622 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8623 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8624 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8625 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8626 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8627 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8628 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8629 struct mlx5_ifc_pude_reg_bits pude_reg;
8630 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8631 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8632 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8633 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8634 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8635 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8636 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8637 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8638 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8639 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8640 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8641 u8 reserved_at_0[0x60e0];
8644 union mlx5_ifc_debug_enhancements_document_bits {
8645 struct mlx5_ifc_health_buffer_bits health_buffer;
8646 u8 reserved_at_0[0x200];
8649 union mlx5_ifc_uplink_pci_interface_document_bits {
8650 struct mlx5_ifc_initial_seg_bits initial_seg;
8651 u8 reserved_at_0[0x20060];
8654 struct mlx5_ifc_set_flow_table_root_out_bits {
8656 u8 reserved_at_8[0x18];
8660 u8 reserved_at_40[0x40];
8663 struct mlx5_ifc_set_flow_table_root_in_bits {
8665 u8 reserved_at_10[0x10];
8667 u8 reserved_at_20[0x10];
8670 u8 other_vport[0x1];
8671 u8 reserved_at_41[0xf];
8672 u8 vport_number[0x10];
8674 u8 reserved_at_60[0x20];
8677 u8 reserved_at_88[0x18];
8679 u8 reserved_at_a0[0x8];
8682 u8 reserved_at_c0[0x8];
8683 u8 underlay_qpn[0x18];
8684 u8 reserved_at_e0[0x120];
8688 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8689 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8692 struct mlx5_ifc_modify_flow_table_out_bits {
8694 u8 reserved_at_8[0x18];
8698 u8 reserved_at_40[0x40];
8701 struct mlx5_ifc_modify_flow_table_in_bits {
8703 u8 reserved_at_10[0x10];
8705 u8 reserved_at_20[0x10];
8708 u8 other_vport[0x1];
8709 u8 reserved_at_41[0xf];
8710 u8 vport_number[0x10];
8712 u8 reserved_at_60[0x10];
8713 u8 modify_field_select[0x10];
8716 u8 reserved_at_88[0x18];
8718 u8 reserved_at_a0[0x8];
8721 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8724 struct mlx5_ifc_ets_tcn_config_reg_bits {
8728 u8 reserved_at_3[0x9];
8730 u8 reserved_at_10[0x9];
8731 u8 bw_allocation[0x7];
8733 u8 reserved_at_20[0xc];
8734 u8 max_bw_units[0x4];
8735 u8 reserved_at_30[0x8];
8736 u8 max_bw_value[0x8];
8739 struct mlx5_ifc_ets_global_config_reg_bits {
8740 u8 reserved_at_0[0x2];
8742 u8 reserved_at_3[0x1d];
8744 u8 reserved_at_20[0xc];
8745 u8 max_bw_units[0x4];
8746 u8 reserved_at_30[0x8];
8747 u8 max_bw_value[0x8];
8750 struct mlx5_ifc_qetc_reg_bits {
8751 u8 reserved_at_0[0x8];
8752 u8 port_number[0x8];
8753 u8 reserved_at_10[0x30];
8755 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8756 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8759 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8761 u8 reserved_at_01[0x0b];
8765 struct mlx5_ifc_qpdpm_reg_bits {
8766 u8 reserved_at_0[0x8];
8768 u8 reserved_at_10[0x10];
8769 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8772 struct mlx5_ifc_qpts_reg_bits {
8773 u8 reserved_at_0[0x8];
8775 u8 reserved_at_10[0x2d];
8776 u8 trust_state[0x3];
8779 struct mlx5_ifc_qtct_reg_bits {
8780 u8 reserved_at_0[0x8];
8781 u8 port_number[0x8];
8782 u8 reserved_at_10[0xd];
8785 u8 reserved_at_20[0x1d];
8789 struct mlx5_ifc_mcia_reg_bits {
8791 u8 reserved_at_1[0x7];
8793 u8 reserved_at_10[0x8];
8796 u8 i2c_device_address[0x8];
8797 u8 page_number[0x8];
8798 u8 device_address[0x10];
8800 u8 reserved_at_40[0x10];
8803 u8 reserved_at_60[0x20];
8819 struct mlx5_ifc_dcbx_param_bits {
8820 u8 dcbx_cee_cap[0x1];
8821 u8 dcbx_ieee_cap[0x1];
8822 u8 dcbx_standby_cap[0x1];
8823 u8 reserved_at_0[0x5];
8824 u8 port_number[0x8];
8825 u8 reserved_at_10[0xa];
8826 u8 max_application_table_size[6];
8827 u8 reserved_at_20[0x15];
8828 u8 version_oper[0x3];
8829 u8 reserved_at_38[5];
8830 u8 version_admin[0x3];
8831 u8 willing_admin[0x1];
8832 u8 reserved_at_41[0x3];
8833 u8 pfc_cap_oper[0x4];
8834 u8 reserved_at_48[0x4];
8835 u8 pfc_cap_admin[0x4];
8836 u8 reserved_at_50[0x4];
8837 u8 num_of_tc_oper[0x4];
8838 u8 reserved_at_58[0x4];
8839 u8 num_of_tc_admin[0x4];
8840 u8 remote_willing[0x1];
8841 u8 reserved_at_61[3];
8842 u8 remote_pfc_cap[4];
8843 u8 reserved_at_68[0x14];
8844 u8 remote_num_of_tc[0x4];
8845 u8 reserved_at_80[0x18];
8847 u8 reserved_at_a0[0x160];
8850 struct mlx5_ifc_lagc_bits {
8851 u8 reserved_at_0[0x1d];
8854 u8 reserved_at_20[0x14];
8855 u8 tx_remap_affinity_2[0x4];
8856 u8 reserved_at_38[0x4];
8857 u8 tx_remap_affinity_1[0x4];
8860 struct mlx5_ifc_create_lag_out_bits {
8862 u8 reserved_at_8[0x18];
8866 u8 reserved_at_40[0x40];
8869 struct mlx5_ifc_create_lag_in_bits {
8871 u8 reserved_at_10[0x10];
8873 u8 reserved_at_20[0x10];
8876 struct mlx5_ifc_lagc_bits ctx;
8879 struct mlx5_ifc_modify_lag_out_bits {
8881 u8 reserved_at_8[0x18];
8885 u8 reserved_at_40[0x40];
8888 struct mlx5_ifc_modify_lag_in_bits {
8890 u8 reserved_at_10[0x10];
8892 u8 reserved_at_20[0x10];
8895 u8 reserved_at_40[0x20];
8896 u8 field_select[0x20];
8898 struct mlx5_ifc_lagc_bits ctx;
8901 struct mlx5_ifc_query_lag_out_bits {
8903 u8 reserved_at_8[0x18];
8907 u8 reserved_at_40[0x40];
8909 struct mlx5_ifc_lagc_bits ctx;
8912 struct mlx5_ifc_query_lag_in_bits {
8914 u8 reserved_at_10[0x10];
8916 u8 reserved_at_20[0x10];
8919 u8 reserved_at_40[0x40];
8922 struct mlx5_ifc_destroy_lag_out_bits {
8924 u8 reserved_at_8[0x18];
8928 u8 reserved_at_40[0x40];
8931 struct mlx5_ifc_destroy_lag_in_bits {
8933 u8 reserved_at_10[0x10];
8935 u8 reserved_at_20[0x10];
8938 u8 reserved_at_40[0x40];
8941 struct mlx5_ifc_create_vport_lag_out_bits {
8943 u8 reserved_at_8[0x18];
8947 u8 reserved_at_40[0x40];
8950 struct mlx5_ifc_create_vport_lag_in_bits {
8952 u8 reserved_at_10[0x10];
8954 u8 reserved_at_20[0x10];
8957 u8 reserved_at_40[0x40];
8960 struct mlx5_ifc_destroy_vport_lag_out_bits {
8962 u8 reserved_at_8[0x18];
8966 u8 reserved_at_40[0x40];
8969 struct mlx5_ifc_destroy_vport_lag_in_bits {
8971 u8 reserved_at_10[0x10];
8973 u8 reserved_at_20[0x10];
8976 u8 reserved_at_40[0x40];
8979 struct mlx5_ifc_alloc_memic_in_bits {
8981 u8 reserved_at_10[0x10];
8983 u8 reserved_at_20[0x10];
8986 u8 reserved_at_30[0x20];
8988 u8 reserved_at_40[0x18];
8989 u8 log_memic_addr_alignment[0x8];
8991 u8 range_start_addr[0x40];
8993 u8 range_size[0x20];
8995 u8 memic_size[0x20];
8998 struct mlx5_ifc_alloc_memic_out_bits {
9000 u8 reserved_at_8[0x18];
9004 u8 memic_start_addr[0x40];
9007 struct mlx5_ifc_dealloc_memic_in_bits {
9009 u8 reserved_at_10[0x10];
9011 u8 reserved_at_20[0x10];
9014 u8 reserved_at_40[0x40];
9016 u8 memic_start_addr[0x40];
9018 u8 memic_size[0x20];
9020 u8 reserved_at_e0[0x20];
9023 struct mlx5_ifc_dealloc_memic_out_bits {
9025 u8 reserved_at_8[0x18];
9029 u8 reserved_at_40[0x40];
9032 #endif /* MLX5_IFC_H */