include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  68         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  69         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  70         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  71         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
  72         MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
  73 };
  74
  75 enum {
  76         MLX5_SHARED_RESOURCE_UID = 0xffff,
  77 };
  78
  79 enum {
  80         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  81         MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
  82 };
  83
  84 enum {
  85         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  86         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  87         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  88         MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
  89                 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
  91 };
  92
  93 enum {
  94         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  95         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  96         MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
  97         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  98         MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
  99         MLX5_OBJ_TYPE_MKEY = 0xff01,
 100         MLX5_OBJ_TYPE_QP = 0xff02,
 101         MLX5_OBJ_TYPE_PSV = 0xff03,
 102         MLX5_OBJ_TYPE_RMP = 0xff04,
 103         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 104         MLX5_OBJ_TYPE_RQ = 0xff06,
 105         MLX5_OBJ_TYPE_SQ = 0xff07,
 106         MLX5_OBJ_TYPE_TIR = 0xff08,
 107         MLX5_OBJ_TYPE_TIS = 0xff09,
 108         MLX5_OBJ_TYPE_DCT = 0xff0a,
 109         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 110         MLX5_OBJ_TYPE_RQT = 0xff0e,
 111         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 112         MLX5_OBJ_TYPE_CQ = 0xff10,
 113 };
 114
 115 enum {
 116         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 117         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 118         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 119         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 120         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 121         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 122         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 123         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 124         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 125         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 126         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 127         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 128         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 129         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 130         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 131         MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
 132         MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
 133         MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
 134         MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
 135         MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
 136         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 137         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 138         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 139         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 140         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 141         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 142         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 143         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 144         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 145         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 146         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 147         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 148         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 149         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 150         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 151         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 152         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 153         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 154         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 155         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 156         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 157         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 158         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 159         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 160         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 161         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 162         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 163         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 164         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 165         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 166         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 167         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 168         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 169         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 170         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 171         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 172         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 173         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 174         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 175         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 176         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 177         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 178         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 179         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 180         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 181         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 182         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 183         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 184         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 185         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 186         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 187         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 188         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 189         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 190         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 191         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 192         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 193         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 194         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 195         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 196         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 197         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 198         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 199         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 200         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 201         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 202         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 203         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 204         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 205         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 206         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 207         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 208         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 209         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 210         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 211         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 212         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 213         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 214         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 215         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 216         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 217         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 218         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 219         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 220         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 221         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 222         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 223         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 224         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 225         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 226         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 227         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 228         MLX5_CMD_OP_NOP                           = 0x80d,
 229         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 230         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 231         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 232         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 233         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 234         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 235         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 236         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 237         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 238         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 239         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 240         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 241         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 242         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 243         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 244         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 245         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 246         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 247         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 248         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 249         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 250         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 251         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 252         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 253         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 254         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 255         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 256         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 257         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 258         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 259         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 260         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 261         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 262         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 263         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 264         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 265         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 266         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 267         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 268         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 269         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 270         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 271         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 272         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 273         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 274         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 275         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 276         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 277         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 278         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 279         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 280         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 281         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 282         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 283         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 284         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 285         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 286         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 287         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 288         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 289         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 290         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 291         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 292         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 293         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 294         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 295         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 296         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 297         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 298         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 299         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 300         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 301         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 302         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 303         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 304         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 305         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 306         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 307         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 308         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 309         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 310         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 311         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 312         MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
 313         MLX5_CMD_OP_MAX
 314 };
 315
 316 /* Valid range for general commands that don't work over an object */
 317 enum {
 318         MLX5_CMD_OP_GENERAL_START = 0xb00,
 319         MLX5_CMD_OP_GENERAL_END = 0xd00,
 320 };
 321
 322 enum {
 323         MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
 324         MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
 325 };
 326
 327 enum {
 328         MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
 329 };
 330
 331 struct mlx5_ifc_flow_table_fields_supported_bits {
 332         u8         outer_dmac[0x1];
 333         u8         outer_smac[0x1];
 334         u8         outer_ether_type[0x1];
 335         u8         outer_ip_version[0x1];
 336         u8         outer_first_prio[0x1];
 337         u8         outer_first_cfi[0x1];
 338         u8         outer_first_vid[0x1];
 339         u8         outer_ipv4_ttl[0x1];
 340         u8         outer_second_prio[0x1];
 341         u8         outer_second_cfi[0x1];
 342         u8         outer_second_vid[0x1];
 343         u8         reserved_at_b[0x1];
 344         u8         outer_sip[0x1];
 345         u8         outer_dip[0x1];
 346         u8         outer_frag[0x1];
 347         u8         outer_ip_protocol[0x1];
 348         u8         outer_ip_ecn[0x1];
 349         u8         outer_ip_dscp[0x1];
 350         u8         outer_udp_sport[0x1];
 351         u8         outer_udp_dport[0x1];
 352         u8         outer_tcp_sport[0x1];
 353         u8         outer_tcp_dport[0x1];
 354         u8         outer_tcp_flags[0x1];
 355         u8         outer_gre_protocol[0x1];
 356         u8         outer_gre_key[0x1];
 357         u8         outer_vxlan_vni[0x1];
 358         u8         outer_geneve_vni[0x1];
 359         u8         outer_geneve_oam[0x1];
 360         u8         outer_geneve_protocol_type[0x1];
 361         u8         outer_geneve_opt_len[0x1];
 362         u8         source_vhca_port[0x1];
 363         u8         source_eswitch_port[0x1];
 364
 365         u8         inner_dmac[0x1];
 366         u8         inner_smac[0x1];
 367         u8         inner_ether_type[0x1];
 368         u8         inner_ip_version[0x1];
 369         u8         inner_first_prio[0x1];
 370         u8         inner_first_cfi[0x1];
 371         u8         inner_first_vid[0x1];
 372         u8         reserved_at_27[0x1];
 373         u8         inner_second_prio[0x1];
 374         u8         inner_second_cfi[0x1];
 375         u8         inner_second_vid[0x1];
 376         u8         reserved_at_2b[0x1];
 377         u8         inner_sip[0x1];
 378         u8         inner_dip[0x1];
 379         u8         inner_frag[0x1];
 380         u8         inner_ip_protocol[0x1];
 381         u8         inner_ip_ecn[0x1];
 382         u8         inner_ip_dscp[0x1];
 383         u8         inner_udp_sport[0x1];
 384         u8         inner_udp_dport[0x1];
 385         u8         inner_tcp_sport[0x1];
 386         u8         inner_tcp_dport[0x1];
 387         u8         inner_tcp_flags[0x1];
 388         u8         reserved_at_37[0x9];
 389
 390         u8         geneve_tlv_option_0_data[0x1];
 391         u8         geneve_tlv_option_0_exist[0x1];
 392         u8         reserved_at_42[0x3];
 393         u8         outer_first_mpls_over_udp[0x4];
 394         u8         outer_first_mpls_over_gre[0x4];
 395         u8         inner_first_mpls[0x4];
 396         u8         outer_first_mpls[0x4];
 397         u8         reserved_at_55[0x2];
 398         u8         outer_esp_spi[0x1];
 399         u8         reserved_at_58[0x2];
 400         u8         bth_dst_qp[0x1];
 401         u8         reserved_at_5b[0x5];
 402
 403         u8         reserved_at_60[0x18];
 404         u8         metadata_reg_c_7[0x1];
 405         u8         metadata_reg_c_6[0x1];
 406         u8         metadata_reg_c_5[0x1];
 407         u8         metadata_reg_c_4[0x1];
 408         u8         metadata_reg_c_3[0x1];
 409         u8         metadata_reg_c_2[0x1];
 410         u8         metadata_reg_c_1[0x1];
 411         u8         metadata_reg_c_0[0x1];
 412 };
 413
 414 /* Table 2170 - Flow Table Fields Supported 2 Format */
 415 struct mlx5_ifc_flow_table_fields_supported_2_bits {
 416         u8         reserved_at_0[0xe];
 417         u8         bth_opcode[0x1];
 418         u8         reserved_at_f[0x1];
 419         u8         tunnel_header_0_1[0x1];
 420         u8         reserved_at_11[0xf];
 421
 422         u8         reserved_at_20[0x60];
 423 };
 424
 425 struct mlx5_ifc_flow_table_prop_layout_bits {
 426         u8         ft_support[0x1];
 427         u8         reserved_at_1[0x1];
 428         u8         flow_counter[0x1];
 429         u8         flow_modify_en[0x1];
 430         u8         modify_root[0x1];
 431         u8         identified_miss_table_mode[0x1];
 432         u8         flow_table_modify[0x1];
 433         u8         reformat[0x1];
 434         u8         decap[0x1];
 435         u8         reserved_at_9[0x1];
 436         u8         pop_vlan[0x1];
 437         u8         push_vlan[0x1];
 438         u8         reserved_at_c[0x1];
 439         u8         pop_vlan_2[0x1];
 440         u8         push_vlan_2[0x1];
 441         u8         reformat_and_vlan_action[0x1];
 442         u8         reserved_at_10[0x1];
 443         u8         sw_owner[0x1];
 444         u8         reformat_l3_tunnel_to_l2[0x1];
 445         u8         reformat_l2_to_l3_tunnel[0x1];
 446         u8         reformat_and_modify_action[0x1];
 447         u8         ignore_flow_level[0x1];
 448         u8         reserved_at_16[0x1];
 449         u8         table_miss_action_domain[0x1];
 450         u8         termination_table[0x1];
 451         u8         reformat_and_fwd_to_table[0x1];
 452         u8         reserved_at_1a[0x2];
 453         u8         ipsec_encrypt[0x1];
 454         u8         ipsec_decrypt[0x1];
 455         u8         sw_owner_v2[0x1];
 456         u8         reserved_at_1f[0x1];
 457
 458         u8         termination_table_raw_traffic[0x1];
 459         u8         reserved_at_21[0x1];
 460         u8         log_max_ft_size[0x6];
 461         u8         log_max_modify_header_context[0x8];
 462         u8         max_modify_header_actions[0x8];
 463         u8         max_ft_level[0x8];
 464
 465         u8         reformat_add_esp_trasport[0x1];
 466         u8         reformat_l2_to_l3_esp_tunnel[0x1];
 467         u8         reformat_add_esp_transport_over_udp[0x1];
 468         u8         reformat_del_esp_trasport[0x1];
 469         u8         reformat_l3_esp_tunnel_to_l2[0x1];
 470         u8         reformat_del_esp_transport_over_udp[0x1];
 471         u8         execute_aso[0x1];
 472         u8         reserved_at_47[0x19];
 473
 474         u8         reserved_at_60[0x2];
 475         u8         reformat_insert[0x1];
 476         u8         reformat_remove[0x1];
 477         u8         macsec_encrypt[0x1];
 478         u8         macsec_decrypt[0x1];
 479         u8         reserved_at_66[0x2];
 480         u8         reformat_add_macsec[0x1];
 481         u8         reformat_remove_macsec[0x1];
 482         u8         reserved_at_6a[0xe];
 483         u8         log_max_ft_num[0x8];
 484
 485         u8         reserved_at_80[0x10];
 486         u8         log_max_flow_counter[0x8];
 487         u8         log_max_destination[0x8];
 488
 489         u8         reserved_at_a0[0x18];
 490         u8         log_max_flow[0x8];
 491
 492         u8         reserved_at_c0[0x40];
 493
 494         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 495
 496         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 497 };
 498
 499 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 500         u8         send[0x1];
 501         u8         receive[0x1];
 502         u8         write[0x1];
 503         u8         read[0x1];
 504         u8         atomic[0x1];
 505         u8         srq_receive[0x1];
 506         u8         reserved_at_6[0x1a];
 507 };
 508
 509 struct mlx5_ifc_ipv4_layout_bits {
 510         u8         reserved_at_0[0x60];
 511
 512         u8         ipv4[0x20];
 513 };
 514
 515 struct mlx5_ifc_ipv6_layout_bits {
 516         u8         ipv6[16][0x8];
 517 };
 518
 519 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 520         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 521         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 522         u8         reserved_at_0[0x80];
 523 };
 524
 525 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 526         u8         smac_47_16[0x20];
 527
 528         u8         smac_15_0[0x10];
 529         u8         ethertype[0x10];
 530
 531         u8         dmac_47_16[0x20];
 532
 533         u8         dmac_15_0[0x10];
 534         u8         first_prio[0x3];
 535         u8         first_cfi[0x1];
 536         u8         first_vid[0xc];
 537
 538         u8         ip_protocol[0x8];
 539         u8         ip_dscp[0x6];
 540         u8         ip_ecn[0x2];
 541         u8         cvlan_tag[0x1];
 542         u8         svlan_tag[0x1];
 543         u8         frag[0x1];
 544         u8         ip_version[0x4];
 545         u8         tcp_flags[0x9];
 546
 547         u8         tcp_sport[0x10];
 548         u8         tcp_dport[0x10];
 549
 550         u8         reserved_at_c0[0x10];
 551         u8         ipv4_ihl[0x4];
 552         u8         reserved_at_c4[0x4];
 553
 554         u8         ttl_hoplimit[0x8];
 555
 556         u8         udp_sport[0x10];
 557         u8         udp_dport[0x10];
 558
 559         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 560
 561         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 562 };
 563
 564 struct mlx5_ifc_nvgre_key_bits {
 565         u8 hi[0x18];
 566         u8 lo[0x8];
 567 };
 568
 569 union mlx5_ifc_gre_key_bits {
 570         struct mlx5_ifc_nvgre_key_bits nvgre;
 571         u8 key[0x20];
 572 };
 573
 574 struct mlx5_ifc_fte_match_set_misc_bits {
 575         u8         gre_c_present[0x1];
 576         u8         reserved_at_1[0x1];
 577         u8         gre_k_present[0x1];
 578         u8         gre_s_present[0x1];
 579         u8         source_vhca_port[0x4];
 580         u8         source_sqn[0x18];
 581
 582         u8         source_eswitch_owner_vhca_id[0x10];
 583         u8         source_port[0x10];
 584
 585         u8         outer_second_prio[0x3];
 586         u8         outer_second_cfi[0x1];
 587         u8         outer_second_vid[0xc];
 588         u8         inner_second_prio[0x3];
 589         u8         inner_second_cfi[0x1];
 590         u8         inner_second_vid[0xc];
 591
 592         u8         outer_second_cvlan_tag[0x1];
 593         u8         inner_second_cvlan_tag[0x1];
 594         u8         outer_second_svlan_tag[0x1];
 595         u8         inner_second_svlan_tag[0x1];
 596         u8         reserved_at_64[0xc];
 597         u8         gre_protocol[0x10];
 598
 599         union mlx5_ifc_gre_key_bits gre_key;
 600
 601         u8         vxlan_vni[0x18];
 602         u8         bth_opcode[0x8];
 603
 604         u8         geneve_vni[0x18];
 605         u8         reserved_at_d8[0x6];
 606         u8         geneve_tlv_option_0_exist[0x1];
 607         u8         geneve_oam[0x1];
 608
 609         u8         reserved_at_e0[0xc];
 610         u8         outer_ipv6_flow_label[0x14];
 611
 612         u8         reserved_at_100[0xc];
 613         u8         inner_ipv6_flow_label[0x14];
 614
 615         u8         reserved_at_120[0xa];
 616         u8         geneve_opt_len[0x6];
 617         u8         geneve_protocol_type[0x10];
 618
 619         u8         reserved_at_140[0x8];
 620         u8         bth_dst_qp[0x18];
 621         u8         reserved_at_160[0x20];
 622         u8         outer_esp_spi[0x20];
 623         u8         reserved_at_1a0[0x60];
 624 };
 625
 626 struct mlx5_ifc_fte_match_mpls_bits {
 627         u8         mpls_label[0x14];
 628         u8         mpls_exp[0x3];
 629         u8         mpls_s_bos[0x1];
 630         u8         mpls_ttl[0x8];
 631 };
 632
 633 struct mlx5_ifc_fte_match_set_misc2_bits {
 634         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 635
 636         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 637
 638         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 639
 640         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 641
 642         u8         metadata_reg_c_7[0x20];
 643
 644         u8         metadata_reg_c_6[0x20];
 645
 646         u8         metadata_reg_c_5[0x20];
 647
 648         u8         metadata_reg_c_4[0x20];
 649
 650         u8         metadata_reg_c_3[0x20];
 651
 652         u8         metadata_reg_c_2[0x20];
 653
 654         u8         metadata_reg_c_1[0x20];
 655
 656         u8         metadata_reg_c_0[0x20];
 657
 658         u8         metadata_reg_a[0x20];
 659
 660         u8         reserved_at_1a0[0x8];
 661
 662         u8         macsec_syndrome[0x8];
 663         u8         ipsec_syndrome[0x8];
 664         u8         reserved_at_1b8[0x8];
 665
 666         u8         reserved_at_1c0[0x40];
 667 };
 668
 669 struct mlx5_ifc_fte_match_set_misc3_bits {
 670         u8         inner_tcp_seq_num[0x20];
 671
 672         u8         outer_tcp_seq_num[0x20];
 673
 674         u8         inner_tcp_ack_num[0x20];
 675
 676         u8         outer_tcp_ack_num[0x20];
 677
 678         u8         reserved_at_80[0x8];
 679         u8         outer_vxlan_gpe_vni[0x18];
 680
 681         u8         outer_vxlan_gpe_next_protocol[0x8];
 682         u8         outer_vxlan_gpe_flags[0x8];
 683         u8         reserved_at_b0[0x10];
 684
 685         u8         icmp_header_data[0x20];
 686
 687         u8         icmpv6_header_data[0x20];
 688
 689         u8         icmp_type[0x8];
 690         u8         icmp_code[0x8];
 691         u8         icmpv6_type[0x8];
 692         u8         icmpv6_code[0x8];
 693
 694         u8         geneve_tlv_option_0_data[0x20];
 695
 696         u8         gtpu_teid[0x20];
 697
 698         u8         gtpu_msg_type[0x8];
 699         u8         gtpu_msg_flags[0x8];
 700         u8         reserved_at_170[0x10];
 701
 702         u8         gtpu_dw_2[0x20];
 703
 704         u8         gtpu_first_ext_dw_0[0x20];
 705
 706         u8         gtpu_dw_0[0x20];
 707
 708         u8         reserved_at_1e0[0x20];
 709 };
 710
 711 struct mlx5_ifc_fte_match_set_misc4_bits {
 712         u8         prog_sample_field_value_0[0x20];
 713
 714         u8         prog_sample_field_id_0[0x20];
 715
 716         u8         prog_sample_field_value_1[0x20];
 717
 718         u8         prog_sample_field_id_1[0x20];
 719
 720         u8         prog_sample_field_value_2[0x20];
 721
 722         u8         prog_sample_field_id_2[0x20];
 723
 724         u8         prog_sample_field_value_3[0x20];
 725
 726         u8         prog_sample_field_id_3[0x20];
 727
 728         u8         reserved_at_100[0x100];
 729 };
 730
 731 struct mlx5_ifc_fte_match_set_misc5_bits {
 732         u8         macsec_tag_0[0x20];
 733
 734         u8         macsec_tag_1[0x20];
 735
 736         u8         macsec_tag_2[0x20];
 737
 738         u8         macsec_tag_3[0x20];
 739
 740         u8         tunnel_header_0[0x20];
 741
 742         u8         tunnel_header_1[0x20];
 743
 744         u8         tunnel_header_2[0x20];
 745
 746         u8         tunnel_header_3[0x20];
 747
 748         u8         reserved_at_100[0x100];
 749 };
 750
 751 struct mlx5_ifc_cmd_pas_bits {
 752         u8         pa_h[0x20];
 753
 754         u8         pa_l[0x14];
 755         u8         reserved_at_34[0xc];
 756 };
 757
 758 struct mlx5_ifc_uint64_bits {
 759         u8         hi[0x20];
 760
 761         u8         lo[0x20];
 762 };
 763
 764 enum {
 765         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 766         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 767         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 768         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 769         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 770         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 771         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 772         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 773         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 774         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 775 };
 776
 777 struct mlx5_ifc_ads_bits {
 778         u8         fl[0x1];
 779         u8         free_ar[0x1];
 780         u8         reserved_at_2[0xe];
 781         u8         pkey_index[0x10];
 782
 783         u8         reserved_at_20[0x8];
 784         u8         grh[0x1];
 785         u8         mlid[0x7];
 786         u8         rlid[0x10];
 787
 788         u8         ack_timeout[0x5];
 789         u8         reserved_at_45[0x3];
 790         u8         src_addr_index[0x8];
 791         u8         reserved_at_50[0x4];
 792         u8         stat_rate[0x4];
 793         u8         hop_limit[0x8];
 794
 795         u8         reserved_at_60[0x4];
 796         u8         tclass[0x8];
 797         u8         flow_label[0x14];
 798
 799         u8         rgid_rip[16][0x8];
 800
 801         u8         reserved_at_100[0x4];
 802         u8         f_dscp[0x1];
 803         u8         f_ecn[0x1];
 804         u8         reserved_at_106[0x1];
 805         u8         f_eth_prio[0x1];
 806         u8         ecn[0x2];
 807         u8         dscp[0x6];
 808         u8         udp_sport[0x10];
 809
 810         u8         dei_cfi[0x1];
 811         u8         eth_prio[0x3];
 812         u8         sl[0x4];
 813         u8         vhca_port_num[0x8];
 814         u8         rmac_47_32[0x10];
 815
 816         u8         rmac_31_0[0x20];
 817 };
 818
 819 struct mlx5_ifc_flow_table_nic_cap_bits {
 820         u8         nic_rx_multi_path_tirs[0x1];
 821         u8         nic_rx_multi_path_tirs_fts[0x1];
 822         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 823         u8         reserved_at_3[0x4];
 824         u8         sw_owner_reformat_supported[0x1];
 825         u8         reserved_at_8[0x18];
 826
 827         u8         encap_general_header[0x1];
 828         u8         reserved_at_21[0xa];
 829         u8         log_max_packet_reformat_context[0x5];
 830         u8         reserved_at_30[0x6];
 831         u8         max_encap_header_size[0xa];
 832         u8         reserved_at_40[0x1c0];
 833
 834         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 835
 836         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 837
 838         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 839
 840         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 841
 842         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 843
 844         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 845
 846         u8         reserved_at_e00[0x700];
 847
 848         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
 849
 850         u8         reserved_at_1580[0x280];
 851
 852         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
 853
 854         u8         reserved_at_1880[0x780];
 855
 856         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 857
 858         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 859
 860         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 861
 862         u8         reserved_at_20c0[0x5f40];
 863 };
 864
 865 struct mlx5_ifc_port_selection_cap_bits {
 866         u8         reserved_at_0[0x10];
 867         u8         port_select_flow_table[0x1];
 868         u8         reserved_at_11[0x1];
 869         u8         port_select_flow_table_bypass[0x1];
 870         u8         reserved_at_13[0xd];
 871
 872         u8         reserved_at_20[0x1e0];
 873
 874         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 875
 876         u8         reserved_at_400[0x7c00];
 877 };
 878
 879 enum {
 880         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 881         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 882         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 883         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 884         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 885         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 886         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 887         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 888 };
 889
 890 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 891         u8      fdb_to_vport_reg_c_id[0x8];
 892         u8      reserved_at_8[0x5];
 893         u8      fdb_uplink_hairpin[0x1];
 894         u8      fdb_multi_path_any_table_limit_regc[0x1];
 895         u8      reserved_at_f[0x3];
 896         u8      fdb_multi_path_any_table[0x1];
 897         u8      reserved_at_13[0x2];
 898         u8      fdb_modify_header_fwd_to_table[0x1];
 899         u8      fdb_ipv4_ttl_modify[0x1];
 900         u8      flow_source[0x1];
 901         u8      reserved_at_18[0x2];
 902         u8      multi_fdb_encap[0x1];
 903         u8      egress_acl_forward_to_vport[0x1];
 904         u8      fdb_multi_path_to_table[0x1];
 905         u8      reserved_at_1d[0x3];
 906
 907         u8      reserved_at_20[0x1e0];
 908
 909         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 910
 911         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 912
 913         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 914
 915         u8      reserved_at_800[0xC00];
 916
 917         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
 918
 919         struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
 920
 921         u8      reserved_at_1500[0x300];
 922
 923         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 924
 925         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 926
 927         u8      sw_steering_uplink_icm_address_rx[0x40];
 928
 929         u8      sw_steering_uplink_icm_address_tx[0x40];
 930
 931         u8      reserved_at_1900[0x6700];
 932 };
 933
 934 enum {
 935         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 936         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 937 };
 938
 939 struct mlx5_ifc_e_switch_cap_bits {
 940         u8         vport_svlan_strip[0x1];
 941         u8         vport_cvlan_strip[0x1];
 942         u8         vport_svlan_insert[0x1];
 943         u8         vport_cvlan_insert_if_not_exist[0x1];
 944         u8         vport_cvlan_insert_overwrite[0x1];
 945         u8         reserved_at_5[0x1];
 946         u8         vport_cvlan_insert_always[0x1];
 947         u8         esw_shared_ingress_acl[0x1];
 948         u8         esw_uplink_ingress_acl[0x1];
 949         u8         root_ft_on_other_esw[0x1];
 950         u8         reserved_at_a[0xf];
 951         u8         esw_functions_changed[0x1];
 952         u8         reserved_at_1a[0x1];
 953         u8         ecpf_vport_exists[0x1];
 954         u8         counter_eswitch_affinity[0x1];
 955         u8         merged_eswitch[0x1];
 956         u8         nic_vport_node_guid_modify[0x1];
 957         u8         nic_vport_port_guid_modify[0x1];
 958
 959         u8         vxlan_encap_decap[0x1];
 960         u8         nvgre_encap_decap[0x1];
 961         u8         reserved_at_22[0x1];
 962         u8         log_max_fdb_encap_uplink[0x5];
 963         u8         reserved_at_21[0x3];
 964         u8         log_max_packet_reformat_context[0x5];
 965         u8         reserved_2b[0x6];
 966         u8         max_encap_header_size[0xa];
 967
 968         u8         reserved_at_40[0xb];
 969         u8         log_max_esw_sf[0x5];
 970         u8         esw_sf_base_id[0x10];
 971
 972         u8         reserved_at_60[0x7a0];
 973
 974 };
 975
 976 struct mlx5_ifc_qos_cap_bits {
 977         u8         packet_pacing[0x1];
 978         u8         esw_scheduling[0x1];
 979         u8         esw_bw_share[0x1];
 980         u8         esw_rate_limit[0x1];
 981         u8         reserved_at_4[0x1];
 982         u8         packet_pacing_burst_bound[0x1];
 983         u8         packet_pacing_typical_size[0x1];
 984         u8         reserved_at_7[0x1];
 985         u8         nic_sq_scheduling[0x1];
 986         u8         nic_bw_share[0x1];
 987         u8         nic_rate_limit[0x1];
 988         u8         packet_pacing_uid[0x1];
 989         u8         log_esw_max_sched_depth[0x4];
 990         u8         reserved_at_10[0x10];
 991
 992         u8         reserved_at_20[0xb];
 993         u8         log_max_qos_nic_queue_group[0x5];
 994         u8         reserved_at_30[0x10];
 995
 996         u8         packet_pacing_max_rate[0x20];
 997
 998         u8         packet_pacing_min_rate[0x20];
 999
1000         u8         reserved_at_80[0x10];
1001         u8         packet_pacing_rate_table_size[0x10];
1002
1003         u8         esw_element_type[0x10];
1004         u8         esw_tsar_type[0x10];
1005
1006         u8         reserved_at_c0[0x10];
1007         u8         max_qos_para_vport[0x10];
1008
1009         u8         max_tsar_bw_share[0x20];
1010
1011         u8         reserved_at_100[0x20];
1012
1013         u8         reserved_at_120[0x3];
1014         u8         log_meter_aso_granularity[0x5];
1015         u8         reserved_at_128[0x3];
1016         u8         log_meter_aso_max_alloc[0x5];
1017         u8         reserved_at_130[0x3];
1018         u8         log_max_num_meter_aso[0x5];
1019         u8         reserved_at_138[0x8];
1020
1021         u8         reserved_at_140[0x6c0];
1022 };
1023
1024 struct mlx5_ifc_debug_cap_bits {
1025         u8         core_dump_general[0x1];
1026         u8         core_dump_qp[0x1];
1027         u8         reserved_at_2[0x7];
1028         u8         resource_dump[0x1];
1029         u8         reserved_at_a[0x16];
1030
1031         u8         reserved_at_20[0x2];
1032         u8         stall_detect[0x1];
1033         u8         reserved_at_23[0x1d];
1034
1035         u8         reserved_at_40[0x7c0];
1036 };
1037
1038 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1039         u8         csum_cap[0x1];
1040         u8         vlan_cap[0x1];
1041         u8         lro_cap[0x1];
1042         u8         lro_psh_flag[0x1];
1043         u8         lro_time_stamp[0x1];
1044         u8         reserved_at_5[0x2];
1045         u8         wqe_vlan_insert[0x1];
1046         u8         self_lb_en_modifiable[0x1];
1047         u8         reserved_at_9[0x2];
1048         u8         max_lso_cap[0x5];
1049         u8         multi_pkt_send_wqe[0x2];
1050         u8         wqe_inline_mode[0x2];
1051         u8         rss_ind_tbl_cap[0x4];
1052         u8         reg_umr_sq[0x1];
1053         u8         scatter_fcs[0x1];
1054         u8         enhanced_multi_pkt_send_wqe[0x1];
1055         u8         tunnel_lso_const_out_ip_id[0x1];
1056         u8         tunnel_lro_gre[0x1];
1057         u8         tunnel_lro_vxlan[0x1];
1058         u8         tunnel_stateless_gre[0x1];
1059         u8         tunnel_stateless_vxlan[0x1];
1060
1061         u8         swp[0x1];
1062         u8         swp_csum[0x1];
1063         u8         swp_lso[0x1];
1064         u8         cqe_checksum_full[0x1];
1065         u8         tunnel_stateless_geneve_tx[0x1];
1066         u8         tunnel_stateless_mpls_over_udp[0x1];
1067         u8         tunnel_stateless_mpls_over_gre[0x1];
1068         u8         tunnel_stateless_vxlan_gpe[0x1];
1069         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1070         u8         tunnel_stateless_ip_over_ip[0x1];
1071         u8         insert_trailer[0x1];
1072         u8         reserved_at_2b[0x1];
1073         u8         tunnel_stateless_ip_over_ip_rx[0x1];
1074         u8         tunnel_stateless_ip_over_ip_tx[0x1];
1075         u8         reserved_at_2e[0x2];
1076         u8         max_vxlan_udp_ports[0x8];
1077         u8         reserved_at_38[0x6];
1078         u8         max_geneve_opt_len[0x1];
1079         u8         tunnel_stateless_geneve_rx[0x1];
1080
1081         u8         reserved_at_40[0x10];
1082         u8         lro_min_mss_size[0x10];
1083
1084         u8         reserved_at_60[0x120];
1085
1086         u8         lro_timer_supported_periods[4][0x20];
1087
1088         u8         reserved_at_200[0x600];
1089 };
1090
1091 enum {
1092         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1093         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1094         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1095 };
1096
1097 struct mlx5_ifc_roce_cap_bits {
1098         u8         roce_apm[0x1];
1099         u8         reserved_at_1[0x3];
1100         u8         sw_r_roce_src_udp_port[0x1];
1101         u8         fl_rc_qp_when_roce_disabled[0x1];
1102         u8         fl_rc_qp_when_roce_enabled[0x1];
1103         u8         reserved_at_7[0x1];
1104         u8         qp_ooo_transmit_default[0x1];
1105         u8         reserved_at_9[0x15];
1106         u8         qp_ts_format[0x2];
1107
1108         u8         reserved_at_20[0x60];
1109
1110         u8         reserved_at_80[0xc];
1111         u8         l3_type[0x4];
1112         u8         reserved_at_90[0x8];
1113         u8         roce_version[0x8];
1114
1115         u8         reserved_at_a0[0x10];
1116         u8         r_roce_dest_udp_port[0x10];
1117
1118         u8         r_roce_max_src_udp_port[0x10];
1119         u8         r_roce_min_src_udp_port[0x10];
1120
1121         u8         reserved_at_e0[0x10];
1122         u8         roce_address_table_size[0x10];
1123
1124         u8         reserved_at_100[0x700];
1125 };
1126
1127 struct mlx5_ifc_sync_steering_in_bits {
1128         u8         opcode[0x10];
1129         u8         uid[0x10];
1130
1131         u8         reserved_at_20[0x10];
1132         u8         op_mod[0x10];
1133
1134         u8         reserved_at_40[0xc0];
1135 };
1136
1137 struct mlx5_ifc_sync_steering_out_bits {
1138         u8         status[0x8];
1139         u8         reserved_at_8[0x18];
1140
1141         u8         syndrome[0x20];
1142
1143         u8         reserved_at_40[0x40];
1144 };
1145
1146 struct mlx5_ifc_sync_crypto_in_bits {
1147         u8         opcode[0x10];
1148         u8         uid[0x10];
1149
1150         u8         reserved_at_20[0x10];
1151         u8         op_mod[0x10];
1152
1153         u8         reserved_at_40[0x20];
1154
1155         u8         reserved_at_60[0x10];
1156         u8         crypto_type[0x10];
1157
1158         u8         reserved_at_80[0x80];
1159 };
1160
1161 struct mlx5_ifc_sync_crypto_out_bits {
1162         u8         status[0x8];
1163         u8         reserved_at_8[0x18];
1164
1165         u8         syndrome[0x20];
1166
1167         u8         reserved_at_40[0x40];
1168 };
1169
1170 struct mlx5_ifc_device_mem_cap_bits {
1171         u8         memic[0x1];
1172         u8         reserved_at_1[0x1f];
1173
1174         u8         reserved_at_20[0xb];
1175         u8         log_min_memic_alloc_size[0x5];
1176         u8         reserved_at_30[0x8];
1177         u8         log_max_memic_addr_alignment[0x8];
1178
1179         u8         memic_bar_start_addr[0x40];
1180
1181         u8         memic_bar_size[0x20];
1182
1183         u8         max_memic_size[0x20];
1184
1185         u8         steering_sw_icm_start_address[0x40];
1186
1187         u8         reserved_at_100[0x8];
1188         u8         log_header_modify_sw_icm_size[0x8];
1189         u8         reserved_at_110[0x2];
1190         u8         log_sw_icm_alloc_granularity[0x6];
1191         u8         log_steering_sw_icm_size[0x8];
1192
1193         u8         reserved_at_120[0x18];
1194         u8         log_header_modify_pattern_sw_icm_size[0x8];
1195
1196         u8         header_modify_sw_icm_start_address[0x40];
1197
1198         u8         reserved_at_180[0x40];
1199
1200         u8         header_modify_pattern_sw_icm_start_address[0x40];
1201
1202         u8         memic_operations[0x20];
1203
1204         u8         reserved_at_220[0x5e0];
1205 };
1206
1207 struct mlx5_ifc_device_event_cap_bits {
1208         u8         user_affiliated_events[4][0x40];
1209
1210         u8         user_unaffiliated_events[4][0x40];
1211 };
1212
1213 struct mlx5_ifc_virtio_emulation_cap_bits {
1214         u8         desc_tunnel_offload_type[0x1];
1215         u8         eth_frame_offload_type[0x1];
1216         u8         virtio_version_1_0[0x1];
1217         u8         device_features_bits_mask[0xd];
1218         u8         event_mode[0x8];
1219         u8         virtio_queue_type[0x8];
1220
1221         u8         max_tunnel_desc[0x10];
1222         u8         reserved_at_30[0x3];
1223         u8         log_doorbell_stride[0x5];
1224         u8         reserved_at_38[0x3];
1225         u8         log_doorbell_bar_size[0x5];
1226
1227         u8         doorbell_bar_offset[0x40];
1228
1229         u8         max_emulated_devices[0x8];
1230         u8         max_num_virtio_queues[0x18];
1231
1232         u8         reserved_at_a0[0x60];
1233
1234         u8         umem_1_buffer_param_a[0x20];
1235
1236         u8         umem_1_buffer_param_b[0x20];
1237
1238         u8         umem_2_buffer_param_a[0x20];
1239
1240         u8         umem_2_buffer_param_b[0x20];
1241
1242         u8         umem_3_buffer_param_a[0x20];
1243
1244         u8         umem_3_buffer_param_b[0x20];
1245
1246         u8         reserved_at_1c0[0x640];
1247 };
1248
1249 enum {
1250         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1251         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1252         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1253         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1254         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1255         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1256         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1257         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1258         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1259 };
1260
1261 enum {
1262         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1263         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1264         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1265         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1266         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1267         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1268         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1269         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1270         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1271 };
1272
1273 struct mlx5_ifc_atomic_caps_bits {
1274         u8         reserved_at_0[0x40];
1275
1276         u8         atomic_req_8B_endianness_mode[0x2];
1277         u8         reserved_at_42[0x4];
1278         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1279
1280         u8         reserved_at_47[0x19];
1281
1282         u8         reserved_at_60[0x20];
1283
1284         u8         reserved_at_80[0x10];
1285         u8         atomic_operations[0x10];
1286
1287         u8         reserved_at_a0[0x10];
1288         u8         atomic_size_qp[0x10];
1289
1290         u8         reserved_at_c0[0x10];
1291         u8         atomic_size_dc[0x10];
1292
1293         u8         reserved_at_e0[0x720];
1294 };
1295
1296 struct mlx5_ifc_odp_cap_bits {
1297         u8         reserved_at_0[0x40];
1298
1299         u8         sig[0x1];
1300         u8         reserved_at_41[0x1f];
1301
1302         u8         reserved_at_60[0x20];
1303
1304         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1305
1306         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1307
1308         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1309
1310         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1311
1312         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1313
1314         u8         reserved_at_120[0x6E0];
1315 };
1316
1317 struct mlx5_ifc_calc_op {
1318         u8        reserved_at_0[0x10];
1319         u8        reserved_at_10[0x9];
1320         u8        op_swap_endianness[0x1];
1321         u8        op_min[0x1];
1322         u8        op_xor[0x1];
1323         u8        op_or[0x1];
1324         u8        op_and[0x1];
1325         u8        op_max[0x1];
1326         u8        op_add[0x1];
1327 };
1328
1329 struct mlx5_ifc_vector_calc_cap_bits {
1330         u8         calc_matrix[0x1];
1331         u8         reserved_at_1[0x1f];
1332         u8         reserved_at_20[0x8];
1333         u8         max_vec_count[0x8];
1334         u8         reserved_at_30[0xd];
1335         u8         max_chunk_size[0x3];
1336         struct mlx5_ifc_calc_op calc0;
1337         struct mlx5_ifc_calc_op calc1;
1338         struct mlx5_ifc_calc_op calc2;
1339         struct mlx5_ifc_calc_op calc3;
1340
1341         u8         reserved_at_c0[0x720];
1342 };
1343
1344 struct mlx5_ifc_tls_cap_bits {
1345         u8         tls_1_2_aes_gcm_128[0x1];
1346         u8         tls_1_3_aes_gcm_128[0x1];
1347         u8         tls_1_2_aes_gcm_256[0x1];
1348         u8         tls_1_3_aes_gcm_256[0x1];
1349         u8         reserved_at_4[0x1c];
1350
1351         u8         reserved_at_20[0x7e0];
1352 };
1353
1354 struct mlx5_ifc_ipsec_cap_bits {
1355         u8         ipsec_full_offload[0x1];
1356         u8         ipsec_crypto_offload[0x1];
1357         u8         ipsec_esn[0x1];
1358         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1359         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1360         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1361         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1362         u8         reserved_at_7[0x4];
1363         u8         log_max_ipsec_offload[0x5];
1364         u8         reserved_at_10[0x10];
1365
1366         u8         min_log_ipsec_full_replay_window[0x8];
1367         u8         max_log_ipsec_full_replay_window[0x8];
1368         u8         reserved_at_30[0x7d0];
1369 };
1370
1371 struct mlx5_ifc_macsec_cap_bits {
1372         u8    macsec_epn[0x1];
1373         u8    reserved_at_1[0x2];
1374         u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1375         u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1376         u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1377         u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1378         u8    reserved_at_7[0x4];
1379         u8    log_max_macsec_offload[0x5];
1380         u8    reserved_at_10[0x10];
1381
1382         u8    min_log_macsec_full_replay_window[0x8];
1383         u8    max_log_macsec_full_replay_window[0x8];
1384         u8    reserved_at_30[0x10];
1385
1386         u8    reserved_at_40[0x7c0];
1387 };
1388
1389 enum {
1390         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1391         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1392         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1393         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1394 };
1395
1396 enum {
1397         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1398         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1399 };
1400
1401 enum {
1402         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1403         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1404         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1405         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1406         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1407 };
1408
1409 enum {
1410         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1411         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1412         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1413         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1414         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1415         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1416 };
1417
1418 enum {
1419         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1420         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1421 };
1422
1423 enum {
1424         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1425         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1426         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1427 };
1428
1429 enum {
1430         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1431         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1432 };
1433
1434 enum {
1435         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1436         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1437         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1438 };
1439
1440 enum {
1441         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1442         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1443         MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1444         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1445         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1446         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1447         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1448         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1449         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1450         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1451         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1452         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1453 };
1454
1455 enum {
1456         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1457         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1458 };
1459
1460 #define MLX5_FC_BULK_SIZE_FACTOR 128
1461
1462 enum mlx5_fc_bulk_alloc_bitmask {
1463         MLX5_FC_BULK_128   = (1 << 0),
1464         MLX5_FC_BULK_256   = (1 << 1),
1465         MLX5_FC_BULK_512   = (1 << 2),
1466         MLX5_FC_BULK_1024  = (1 << 3),
1467         MLX5_FC_BULK_2048  = (1 << 4),
1468         MLX5_FC_BULK_4096  = (1 << 5),
1469         MLX5_FC_BULK_8192  = (1 << 6),
1470         MLX5_FC_BULK_16384 = (1 << 7),
1471 };
1472
1473 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1474
1475 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1476
1477 enum {
1478         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1479         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1480         MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1481 };
1482
1483 struct mlx5_ifc_cmd_hca_cap_bits {
1484         u8         reserved_at_0[0x10];
1485         u8         shared_object_to_user_object_allowed[0x1];
1486         u8         reserved_at_13[0xe];
1487         u8         vhca_resource_manager[0x1];
1488
1489         u8         hca_cap_2[0x1];
1490         u8         create_lag_when_not_master_up[0x1];
1491         u8         dtor[0x1];
1492         u8         event_on_vhca_state_teardown_request[0x1];
1493         u8         event_on_vhca_state_in_use[0x1];
1494         u8         event_on_vhca_state_active[0x1];
1495         u8         event_on_vhca_state_allocated[0x1];
1496         u8         event_on_vhca_state_invalid[0x1];
1497         u8         reserved_at_28[0x8];
1498         u8         vhca_id[0x10];
1499
1500         u8         reserved_at_40[0x40];
1501
1502         u8         log_max_srq_sz[0x8];
1503         u8         log_max_qp_sz[0x8];
1504         u8         event_cap[0x1];
1505         u8         reserved_at_91[0x2];
1506         u8         isolate_vl_tc_new[0x1];
1507         u8         reserved_at_94[0x4];
1508         u8         prio_tag_required[0x1];
1509         u8         reserved_at_99[0x2];
1510         u8         log_max_qp[0x5];
1511
1512         u8         reserved_at_a0[0x3];
1513         u8         ece_support[0x1];
1514         u8         reserved_at_a4[0x5];
1515         u8         reg_c_preserve[0x1];
1516         u8         reserved_at_aa[0x1];
1517         u8         log_max_srq[0x5];
1518         u8         reserved_at_b0[0x1];
1519         u8         uplink_follow[0x1];
1520         u8         ts_cqe_to_dest_cqn[0x1];
1521         u8         reserved_at_b3[0x6];
1522         u8         go_back_n[0x1];
1523         u8         shampo[0x1];
1524         u8         reserved_at_bb[0x5];
1525
1526         u8         max_sgl_for_optimized_performance[0x8];
1527         u8         log_max_cq_sz[0x8];
1528         u8         relaxed_ordering_write_umr[0x1];
1529         u8         relaxed_ordering_read_umr[0x1];
1530         u8         reserved_at_d2[0x7];
1531         u8         virtio_net_device_emualtion_manager[0x1];
1532         u8         virtio_blk_device_emualtion_manager[0x1];
1533         u8         log_max_cq[0x5];
1534
1535         u8         log_max_eq_sz[0x8];
1536         u8         relaxed_ordering_write[0x1];
1537         u8         relaxed_ordering_read_pci_enabled[0x1];
1538         u8         log_max_mkey[0x6];
1539         u8         reserved_at_f0[0x6];
1540         u8         terminate_scatter_list_mkey[0x1];
1541         u8         repeated_mkey[0x1];
1542         u8         dump_fill_mkey[0x1];
1543         u8         reserved_at_f9[0x2];
1544         u8         fast_teardown[0x1];
1545         u8         log_max_eq[0x4];
1546
1547         u8         max_indirection[0x8];
1548         u8         fixed_buffer_size[0x1];
1549         u8         log_max_mrw_sz[0x7];
1550         u8         force_teardown[0x1];
1551         u8         reserved_at_111[0x1];
1552         u8         log_max_bsf_list_size[0x6];
1553         u8         umr_extended_translation_offset[0x1];
1554         u8         null_mkey[0x1];
1555         u8         log_max_klm_list_size[0x6];
1556
1557         u8         reserved_at_120[0x2];
1558         u8         qpc_extension[0x1];
1559         u8         reserved_at_123[0x7];
1560         u8         log_max_ra_req_dc[0x6];
1561         u8         reserved_at_130[0x2];
1562         u8         eth_wqe_too_small[0x1];
1563         u8         reserved_at_133[0x6];
1564         u8         vnic_env_cq_overrun[0x1];
1565         u8         log_max_ra_res_dc[0x6];
1566
1567         u8         reserved_at_140[0x5];
1568         u8         release_all_pages[0x1];
1569         u8         must_not_use[0x1];
1570         u8         reserved_at_147[0x2];
1571         u8         roce_accl[0x1];
1572         u8         log_max_ra_req_qp[0x6];
1573         u8         reserved_at_150[0xa];
1574         u8         log_max_ra_res_qp[0x6];
1575
1576         u8         end_pad[0x1];
1577         u8         cc_query_allowed[0x1];
1578         u8         cc_modify_allowed[0x1];
1579         u8         start_pad[0x1];
1580         u8         cache_line_128byte[0x1];
1581         u8         reserved_at_165[0x4];
1582         u8         rts2rts_qp_counters_set_id[0x1];
1583         u8         reserved_at_16a[0x2];
1584         u8         vnic_env_int_rq_oob[0x1];
1585         u8         sbcam_reg[0x1];
1586         u8         reserved_at_16e[0x1];
1587         u8         qcam_reg[0x1];
1588         u8         gid_table_size[0x10];
1589
1590         u8         out_of_seq_cnt[0x1];
1591         u8         vport_counters[0x1];
1592         u8         retransmission_q_counters[0x1];
1593         u8         debug[0x1];
1594         u8         modify_rq_counter_set_id[0x1];
1595         u8         rq_delay_drop[0x1];
1596         u8         max_qp_cnt[0xa];
1597         u8         pkey_table_size[0x10];
1598
1599         u8         vport_group_manager[0x1];
1600         u8         vhca_group_manager[0x1];
1601         u8         ib_virt[0x1];
1602         u8         eth_virt[0x1];
1603         u8         vnic_env_queue_counters[0x1];
1604         u8         ets[0x1];
1605         u8         nic_flow_table[0x1];
1606         u8         eswitch_manager[0x1];
1607         u8         device_memory[0x1];
1608         u8         mcam_reg[0x1];
1609         u8         pcam_reg[0x1];
1610         u8         local_ca_ack_delay[0x5];
1611         u8         port_module_event[0x1];
1612         u8         enhanced_error_q_counters[0x1];
1613         u8         ports_check[0x1];
1614         u8         reserved_at_1b3[0x1];
1615         u8         disable_link_up[0x1];
1616         u8         beacon_led[0x1];
1617         u8         port_type[0x2];
1618         u8         num_ports[0x8];
1619
1620         u8         reserved_at_1c0[0x1];
1621         u8         pps[0x1];
1622         u8         pps_modify[0x1];
1623         u8         log_max_msg[0x5];
1624         u8         reserved_at_1c8[0x4];
1625         u8         max_tc[0x4];
1626         u8         temp_warn_event[0x1];
1627         u8         dcbx[0x1];
1628         u8         general_notification_event[0x1];
1629         u8         reserved_at_1d3[0x2];
1630         u8         fpga[0x1];
1631         u8         rol_s[0x1];
1632         u8         rol_g[0x1];
1633         u8         reserved_at_1d8[0x1];
1634         u8         wol_s[0x1];
1635         u8         wol_g[0x1];
1636         u8         wol_a[0x1];
1637         u8         wol_b[0x1];
1638         u8         wol_m[0x1];
1639         u8         wol_u[0x1];
1640         u8         wol_p[0x1];
1641
1642         u8         stat_rate_support[0x10];
1643         u8         reserved_at_1f0[0x1];
1644         u8         pci_sync_for_fw_update_event[0x1];
1645         u8         reserved_at_1f2[0x6];
1646         u8         init2_lag_tx_port_affinity[0x1];
1647         u8         reserved_at_1fa[0x3];
1648         u8         cqe_version[0x4];
1649
1650         u8         compact_address_vector[0x1];
1651         u8         striding_rq[0x1];
1652         u8         reserved_at_202[0x1];
1653         u8         ipoib_enhanced_offloads[0x1];
1654         u8         ipoib_basic_offloads[0x1];
1655         u8         reserved_at_205[0x1];
1656         u8         repeated_block_disabled[0x1];
1657         u8         umr_modify_entity_size_disabled[0x1];
1658         u8         umr_modify_atomic_disabled[0x1];
1659         u8         umr_indirect_mkey_disabled[0x1];
1660         u8         umr_fence[0x2];
1661         u8         dc_req_scat_data_cqe[0x1];
1662         u8         reserved_at_20d[0x2];
1663         u8         drain_sigerr[0x1];
1664         u8         cmdif_checksum[0x2];
1665         u8         sigerr_cqe[0x1];
1666         u8         reserved_at_213[0x1];
1667         u8         wq_signature[0x1];
1668         u8         sctr_data_cqe[0x1];
1669         u8         reserved_at_216[0x1];
1670         u8         sho[0x1];
1671         u8         tph[0x1];
1672         u8         rf[0x1];
1673         u8         dct[0x1];
1674         u8         qos[0x1];
1675         u8         eth_net_offloads[0x1];
1676         u8         roce[0x1];
1677         u8         atomic[0x1];
1678         u8         reserved_at_21f[0x1];
1679
1680         u8         cq_oi[0x1];
1681         u8         cq_resize[0x1];
1682         u8         cq_moderation[0x1];
1683         u8         reserved_at_223[0x3];
1684         u8         cq_eq_remap[0x1];
1685         u8         pg[0x1];
1686         u8         block_lb_mc[0x1];
1687         u8         reserved_at_229[0x1];
1688         u8         scqe_break_moderation[0x1];
1689         u8         cq_period_start_from_cqe[0x1];
1690         u8         cd[0x1];
1691         u8         reserved_at_22d[0x1];
1692         u8         apm[0x1];
1693         u8         vector_calc[0x1];
1694         u8         umr_ptr_rlky[0x1];
1695         u8         imaicl[0x1];
1696         u8         qp_packet_based[0x1];
1697         u8         reserved_at_233[0x3];
1698         u8         qkv[0x1];
1699         u8         pkv[0x1];
1700         u8         set_deth_sqpn[0x1];
1701         u8         reserved_at_239[0x3];
1702         u8         xrc[0x1];
1703         u8         ud[0x1];
1704         u8         uc[0x1];
1705         u8         rc[0x1];
1706
1707         u8         uar_4k[0x1];
1708         u8         reserved_at_241[0x7];
1709         u8         fl_rc_qp_when_roce_disabled[0x1];
1710         u8         regexp_params[0x1];
1711         u8         uar_sz[0x6];
1712         u8         port_selection_cap[0x1];
1713         u8         reserved_at_251[0x1];
1714         u8         umem_uid_0[0x1];
1715         u8         reserved_at_253[0x5];
1716         u8         log_pg_sz[0x8];
1717
1718         u8         bf[0x1];
1719         u8         driver_version[0x1];
1720         u8         pad_tx_eth_packet[0x1];
1721         u8         reserved_at_263[0x3];
1722         u8         mkey_by_name[0x1];
1723         u8         reserved_at_267[0x4];
1724
1725         u8         log_bf_reg_size[0x5];
1726
1727         u8         reserved_at_270[0x3];
1728         u8         qp_error_syndrome[0x1];
1729         u8         reserved_at_274[0x2];
1730         u8         lag_dct[0x2];
1731         u8         lag_tx_port_affinity[0x1];
1732         u8         lag_native_fdb_selection[0x1];
1733         u8         reserved_at_27a[0x1];
1734         u8         lag_master[0x1];
1735         u8         num_lag_ports[0x4];
1736
1737         u8         reserved_at_280[0x10];
1738         u8         max_wqe_sz_sq[0x10];
1739
1740         u8         reserved_at_2a0[0x10];
1741         u8         max_wqe_sz_rq[0x10];
1742
1743         u8         max_flow_counter_31_16[0x10];
1744         u8         max_wqe_sz_sq_dc[0x10];
1745
1746         u8         reserved_at_2e0[0x7];
1747         u8         max_qp_mcg[0x19];
1748
1749         u8         reserved_at_300[0x10];
1750         u8         flow_counter_bulk_alloc[0x8];
1751         u8         log_max_mcg[0x8];
1752
1753         u8         reserved_at_320[0x3];
1754         u8         log_max_transport_domain[0x5];
1755         u8         reserved_at_328[0x2];
1756         u8         relaxed_ordering_read[0x1];
1757         u8         log_max_pd[0x5];
1758         u8         reserved_at_330[0x6];
1759         u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1760         u8         vnic_env_cnt_steering_fail[0x1];
1761         u8         vport_counter_local_loopback[0x1];
1762         u8         q_counter_aggregation[0x1];
1763         u8         q_counter_other_vport[0x1];
1764         u8         log_max_xrcd[0x5];
1765
1766         u8         nic_receive_steering_discard[0x1];
1767         u8         receive_discard_vport_down[0x1];
1768         u8         transmit_discard_vport_down[0x1];
1769         u8         eq_overrun_count[0x1];
1770         u8         reserved_at_344[0x1];
1771         u8         invalid_command_count[0x1];
1772         u8         quota_exceeded_count[0x1];
1773         u8         reserved_at_347[0x1];
1774         u8         log_max_flow_counter_bulk[0x8];
1775         u8         max_flow_counter_15_0[0x10];
1776
1777
1778         u8         reserved_at_360[0x3];
1779         u8         log_max_rq[0x5];
1780         u8         reserved_at_368[0x3];
1781         u8         log_max_sq[0x5];
1782         u8         reserved_at_370[0x3];
1783         u8         log_max_tir[0x5];
1784         u8         reserved_at_378[0x3];
1785         u8         log_max_tis[0x5];
1786
1787         u8         basic_cyclic_rcv_wqe[0x1];
1788         u8         reserved_at_381[0x2];
1789         u8         log_max_rmp[0x5];
1790         u8         reserved_at_388[0x3];
1791         u8         log_max_rqt[0x5];
1792         u8         reserved_at_390[0x3];
1793         u8         log_max_rqt_size[0x5];
1794         u8         reserved_at_398[0x3];
1795         u8         log_max_tis_per_sq[0x5];
1796
1797         u8         ext_stride_num_range[0x1];
1798         u8         roce_rw_supported[0x1];
1799         u8         log_max_current_uc_list_wr_supported[0x1];
1800         u8         log_max_stride_sz_rq[0x5];
1801         u8         reserved_at_3a8[0x3];
1802         u8         log_min_stride_sz_rq[0x5];
1803         u8         reserved_at_3b0[0x3];
1804         u8         log_max_stride_sz_sq[0x5];
1805         u8         reserved_at_3b8[0x3];
1806         u8         log_min_stride_sz_sq[0x5];
1807
1808         u8         hairpin[0x1];
1809         u8         reserved_at_3c1[0x2];
1810         u8         log_max_hairpin_queues[0x5];
1811         u8         reserved_at_3c8[0x3];
1812         u8         log_max_hairpin_wq_data_sz[0x5];
1813         u8         reserved_at_3d0[0x3];
1814         u8         log_max_hairpin_num_packets[0x5];
1815         u8         reserved_at_3d8[0x3];
1816         u8         log_max_wq_sz[0x5];
1817
1818         u8         nic_vport_change_event[0x1];
1819         u8         disable_local_lb_uc[0x1];
1820         u8         disable_local_lb_mc[0x1];
1821         u8         log_min_hairpin_wq_data_sz[0x5];
1822         u8         reserved_at_3e8[0x2];
1823         u8         vhca_state[0x1];
1824         u8         log_max_vlan_list[0x5];
1825         u8         reserved_at_3f0[0x3];
1826         u8         log_max_current_mc_list[0x5];
1827         u8         reserved_at_3f8[0x3];
1828         u8         log_max_current_uc_list[0x5];
1829
1830         u8         general_obj_types[0x40];
1831
1832         u8         sq_ts_format[0x2];
1833         u8         rq_ts_format[0x2];
1834         u8         steering_format_version[0x4];
1835         u8         create_qp_start_hint[0x18];
1836
1837         u8         reserved_at_460[0x1];
1838         u8         ats[0x1];
1839         u8         reserved_at_462[0x1];
1840         u8         log_max_uctx[0x5];
1841         u8         reserved_at_468[0x1];
1842         u8         crypto[0x1];
1843         u8         ipsec_offload[0x1];
1844         u8         log_max_umem[0x5];
1845         u8         max_num_eqs[0x10];
1846
1847         u8         reserved_at_480[0x1];
1848         u8         tls_tx[0x1];
1849         u8         tls_rx[0x1];
1850         u8         log_max_l2_table[0x5];
1851         u8         reserved_at_488[0x8];
1852         u8         log_uar_page_sz[0x10];
1853
1854         u8         reserved_at_4a0[0x20];
1855         u8         device_frequency_mhz[0x20];
1856         u8         device_frequency_khz[0x20];
1857
1858         u8         reserved_at_500[0x20];
1859         u8         num_of_uars_per_page[0x20];
1860
1861         u8         flex_parser_protocols[0x20];
1862
1863         u8         max_geneve_tlv_options[0x8];
1864         u8         reserved_at_568[0x3];
1865         u8         max_geneve_tlv_option_data_len[0x5];
1866         u8         reserved_at_570[0x9];
1867         u8         adv_virtualization[0x1];
1868         u8         reserved_at_57a[0x6];
1869
1870         u8         reserved_at_580[0xb];
1871         u8         log_max_dci_stream_channels[0x5];
1872         u8         reserved_at_590[0x3];
1873         u8         log_max_dci_errored_streams[0x5];
1874         u8         reserved_at_598[0x8];
1875
1876         u8         reserved_at_5a0[0x10];
1877         u8         enhanced_cqe_compression[0x1];
1878         u8         reserved_at_5b1[0x2];
1879         u8         log_max_dek[0x5];
1880         u8         reserved_at_5b8[0x4];
1881         u8         mini_cqe_resp_stride_index[0x1];
1882         u8         cqe_128_always[0x1];
1883         u8         cqe_compression_128[0x1];
1884         u8         cqe_compression[0x1];
1885
1886         u8         cqe_compression_timeout[0x10];
1887         u8         cqe_compression_max_num[0x10];
1888
1889         u8         reserved_at_5e0[0x8];
1890         u8         flex_parser_id_gtpu_dw_0[0x4];
1891         u8         reserved_at_5ec[0x4];
1892         u8         tag_matching[0x1];
1893         u8         rndv_offload_rc[0x1];
1894         u8         rndv_offload_dc[0x1];
1895         u8         log_tag_matching_list_sz[0x5];
1896         u8         reserved_at_5f8[0x3];
1897         u8         log_max_xrq[0x5];
1898
1899         u8         affiliate_nic_vport_criteria[0x8];
1900         u8         native_port_num[0x8];
1901         u8         num_vhca_ports[0x8];
1902         u8         flex_parser_id_gtpu_teid[0x4];
1903         u8         reserved_at_61c[0x2];
1904         u8         sw_owner_id[0x1];
1905         u8         reserved_at_61f[0x1];
1906
1907         u8         max_num_of_monitor_counters[0x10];
1908         u8         num_ppcnt_monitor_counters[0x10];
1909
1910         u8         max_num_sf[0x10];
1911         u8         num_q_monitor_counters[0x10];
1912
1913         u8         reserved_at_660[0x20];
1914
1915         u8         sf[0x1];
1916         u8         sf_set_partition[0x1];
1917         u8         reserved_at_682[0x1];
1918         u8         log_max_sf[0x5];
1919         u8         apu[0x1];
1920         u8         reserved_at_689[0x4];
1921         u8         migration[0x1];
1922         u8         reserved_at_68e[0x2];
1923         u8         log_min_sf_size[0x8];
1924         u8         max_num_sf_partitions[0x8];
1925
1926         u8         uctx_cap[0x20];
1927
1928         u8         reserved_at_6c0[0x4];
1929         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1930         u8         flex_parser_id_icmp_dw1[0x4];
1931         u8         flex_parser_id_icmp_dw0[0x4];
1932         u8         flex_parser_id_icmpv6_dw1[0x4];
1933         u8         flex_parser_id_icmpv6_dw0[0x4];
1934         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1935         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1936
1937         u8         max_num_match_definer[0x10];
1938         u8         sf_base_id[0x10];
1939
1940         u8         flex_parser_id_gtpu_dw_2[0x4];
1941         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1942         u8         num_total_dynamic_vf_msix[0x18];
1943         u8         reserved_at_720[0x14];
1944         u8         dynamic_msix_table_size[0xc];
1945         u8         reserved_at_740[0xc];
1946         u8         min_dynamic_vf_msix_table_size[0x4];
1947         u8         reserved_at_750[0x4];
1948         u8         max_dynamic_vf_msix_table_size[0xc];
1949
1950         u8         reserved_at_760[0x3];
1951         u8         log_max_num_header_modify_argument[0x5];
1952         u8         reserved_at_768[0x4];
1953         u8         log_header_modify_argument_granularity[0x4];
1954         u8         reserved_at_770[0x3];
1955         u8         log_header_modify_argument_max_alloc[0x5];
1956         u8         reserved_at_778[0x8];
1957
1958         u8         vhca_tunnel_commands[0x40];
1959         u8         match_definer_format_supported[0x40];
1960 };
1961
1962 struct mlx5_ifc_cmd_hca_cap_2_bits {
1963         u8         reserved_at_0[0x80];
1964
1965         u8         migratable[0x1];
1966         u8         reserved_at_81[0x1f];
1967
1968         u8         max_reformat_insert_size[0x8];
1969         u8         max_reformat_insert_offset[0x8];
1970         u8         max_reformat_remove_size[0x8];
1971         u8         max_reformat_remove_offset[0x8];
1972
1973         u8         reserved_at_c0[0x8];
1974         u8         migration_multi_load[0x1];
1975         u8         migration_tracking_state[0x1];
1976         u8         reserved_at_ca[0x16];
1977
1978         u8         reserved_at_e0[0xc0];
1979
1980         u8         flow_table_type_2_type[0x8];
1981         u8         reserved_at_1a8[0x3];
1982         u8         log_min_mkey_entity_size[0x5];
1983         u8         reserved_at_1b0[0x10];
1984
1985         u8         reserved_at_1c0[0x60];
1986
1987         u8         reserved_at_220[0x1];
1988         u8         sw_vhca_id_valid[0x1];
1989         u8         sw_vhca_id[0xe];
1990         u8         reserved_at_230[0x10];
1991
1992         u8         reserved_at_240[0xb];
1993         u8         ts_cqe_metadata_size2wqe_counter[0x5];
1994         u8         reserved_at_250[0x10];
1995
1996         u8         reserved_at_260[0x120];
1997         u8         reserved_at_380[0x10];
1998         u8         ec_vf_vport_base[0x10];
1999         u8         reserved_at_3a0[0x460];
2000 };
2001
2002 enum mlx5_ifc_flow_destination_type {
2003         MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2004         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2005         MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2006         MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2007         MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2008         MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2009 };
2010
2011 enum mlx5_flow_table_miss_action {
2012         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2013         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2014         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2015 };
2016
2017 struct mlx5_ifc_dest_format_struct_bits {
2018         u8         destination_type[0x8];
2019         u8         destination_id[0x18];
2020
2021         u8         destination_eswitch_owner_vhca_id_valid[0x1];
2022         u8         packet_reformat[0x1];
2023         u8         reserved_at_22[0x6];
2024         u8         destination_table_type[0x8];
2025         u8         destination_eswitch_owner_vhca_id[0x10];
2026 };
2027
2028 struct mlx5_ifc_flow_counter_list_bits {
2029         u8         flow_counter_id[0x20];
2030
2031         u8         reserved_at_20[0x20];
2032 };
2033
2034 struct mlx5_ifc_extended_dest_format_bits {
2035         struct mlx5_ifc_dest_format_struct_bits destination_entry;
2036
2037         u8         packet_reformat_id[0x20];
2038
2039         u8         reserved_at_60[0x20];
2040 };
2041
2042 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2043         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2044         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2045 };
2046
2047 struct mlx5_ifc_fte_match_param_bits {
2048         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2049
2050         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2051
2052         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2053
2054         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2055
2056         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2057
2058         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2059
2060         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2061
2062         u8         reserved_at_e00[0x200];
2063 };
2064
2065 enum {
2066         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2067         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2068         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2069         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2070         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2071 };
2072
2073 struct mlx5_ifc_rx_hash_field_select_bits {
2074         u8         l3_prot_type[0x1];
2075         u8         l4_prot_type[0x1];
2076         u8         selected_fields[0x1e];
2077 };
2078
2079 enum {
2080         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2081         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2082 };
2083
2084 enum {
2085         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2086         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2087 };
2088
2089 struct mlx5_ifc_wq_bits {
2090         u8         wq_type[0x4];
2091         u8         wq_signature[0x1];
2092         u8         end_padding_mode[0x2];
2093         u8         cd_slave[0x1];
2094         u8         reserved_at_8[0x18];
2095
2096         u8         hds_skip_first_sge[0x1];
2097         u8         log2_hds_buf_size[0x3];
2098         u8         reserved_at_24[0x7];
2099         u8         page_offset[0x5];
2100         u8         lwm[0x10];
2101
2102         u8         reserved_at_40[0x8];
2103         u8         pd[0x18];
2104
2105         u8         reserved_at_60[0x8];
2106         u8         uar_page[0x18];
2107
2108         u8         dbr_addr[0x40];
2109
2110         u8         hw_counter[0x20];
2111
2112         u8         sw_counter[0x20];
2113
2114         u8         reserved_at_100[0xc];
2115         u8         log_wq_stride[0x4];
2116         u8         reserved_at_110[0x3];
2117         u8         log_wq_pg_sz[0x5];
2118         u8         reserved_at_118[0x3];
2119         u8         log_wq_sz[0x5];
2120
2121         u8         dbr_umem_valid[0x1];
2122         u8         wq_umem_valid[0x1];
2123         u8         reserved_at_122[0x1];
2124         u8         log_hairpin_num_packets[0x5];
2125         u8         reserved_at_128[0x3];
2126         u8         log_hairpin_data_sz[0x5];
2127
2128         u8         reserved_at_130[0x4];
2129         u8         log_wqe_num_of_strides[0x4];
2130         u8         two_byte_shift_en[0x1];
2131         u8         reserved_at_139[0x4];
2132         u8         log_wqe_stride_size[0x3];
2133
2134         u8         reserved_at_140[0x80];
2135
2136         u8         headers_mkey[0x20];
2137
2138         u8         shampo_enable[0x1];
2139         u8         reserved_at_1e1[0x4];
2140         u8         log_reservation_size[0x3];
2141         u8         reserved_at_1e8[0x5];
2142         u8         log_max_num_of_packets_per_reservation[0x3];
2143         u8         reserved_at_1f0[0x6];
2144         u8         log_headers_entry_size[0x2];
2145         u8         reserved_at_1f8[0x4];
2146         u8         log_headers_buffer_entry_num[0x4];
2147
2148         u8         reserved_at_200[0x400];
2149
2150         struct mlx5_ifc_cmd_pas_bits pas[];
2151 };
2152
2153 struct mlx5_ifc_rq_num_bits {
2154         u8         reserved_at_0[0x8];
2155         u8         rq_num[0x18];
2156 };
2157
2158 struct mlx5_ifc_mac_address_layout_bits {
2159         u8         reserved_at_0[0x10];
2160         u8         mac_addr_47_32[0x10];
2161
2162         u8         mac_addr_31_0[0x20];
2163 };
2164
2165 struct mlx5_ifc_vlan_layout_bits {
2166         u8         reserved_at_0[0x14];
2167         u8         vlan[0x0c];
2168
2169         u8         reserved_at_20[0x20];
2170 };
2171
2172 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2173         u8         reserved_at_0[0xa0];
2174
2175         u8         min_time_between_cnps[0x20];
2176
2177         u8         reserved_at_c0[0x12];
2178         u8         cnp_dscp[0x6];
2179         u8         reserved_at_d8[0x4];
2180         u8         cnp_prio_mode[0x1];
2181         u8         cnp_802p_prio[0x3];
2182
2183         u8         reserved_at_e0[0x720];
2184 };
2185
2186 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2187         u8         reserved_at_0[0x60];
2188
2189         u8         reserved_at_60[0x4];
2190         u8         clamp_tgt_rate[0x1];
2191         u8         reserved_at_65[0x3];
2192         u8         clamp_tgt_rate_after_time_inc[0x1];
2193         u8         reserved_at_69[0x17];
2194
2195         u8         reserved_at_80[0x20];
2196
2197         u8         rpg_time_reset[0x20];
2198
2199         u8         rpg_byte_reset[0x20];
2200
2201         u8         rpg_threshold[0x20];
2202
2203         u8         rpg_max_rate[0x20];
2204
2205         u8         rpg_ai_rate[0x20];
2206
2207         u8         rpg_hai_rate[0x20];
2208
2209         u8         rpg_gd[0x20];
2210
2211         u8         rpg_min_dec_fac[0x20];
2212
2213         u8         rpg_min_rate[0x20];
2214
2215         u8         reserved_at_1c0[0xe0];
2216
2217         u8         rate_to_set_on_first_cnp[0x20];
2218
2219         u8         dce_tcp_g[0x20];
2220
2221         u8         dce_tcp_rtt[0x20];
2222
2223         u8         rate_reduce_monitor_period[0x20];
2224
2225         u8         reserved_at_320[0x20];
2226
2227         u8         initial_alpha_value[0x20];
2228
2229         u8         reserved_at_360[0x4a0];
2230 };
2231
2232 struct mlx5_ifc_cong_control_r_roce_general_bits {
2233         u8         reserved_at_0[0x80];
2234
2235         u8         reserved_at_80[0x10];
2236         u8         rtt_resp_dscp_valid[0x1];
2237         u8         reserved_at_91[0x9];
2238         u8         rtt_resp_dscp[0x6];
2239
2240         u8         reserved_at_a0[0x760];
2241 };
2242
2243 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2244         u8         reserved_at_0[0x80];
2245
2246         u8         rppp_max_rps[0x20];
2247
2248         u8         rpg_time_reset[0x20];
2249
2250         u8         rpg_byte_reset[0x20];
2251
2252         u8         rpg_threshold[0x20];
2253
2254         u8         rpg_max_rate[0x20];
2255
2256         u8         rpg_ai_rate[0x20];
2257
2258         u8         rpg_hai_rate[0x20];
2259
2260         u8         rpg_gd[0x20];
2261
2262         u8         rpg_min_dec_fac[0x20];
2263
2264         u8         rpg_min_rate[0x20];
2265
2266         u8         reserved_at_1c0[0x640];
2267 };
2268
2269 enum {
2270         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2271         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2272         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2273 };
2274
2275 struct mlx5_ifc_resize_field_select_bits {
2276         u8         resize_field_select[0x20];
2277 };
2278
2279 struct mlx5_ifc_resource_dump_bits {
2280         u8         more_dump[0x1];
2281         u8         inline_dump[0x1];
2282         u8         reserved_at_2[0xa];
2283         u8         seq_num[0x4];
2284         u8         segment_type[0x10];
2285
2286         u8         reserved_at_20[0x10];
2287         u8         vhca_id[0x10];
2288
2289         u8         index1[0x20];
2290
2291         u8         index2[0x20];
2292
2293         u8         num_of_obj1[0x10];
2294         u8         num_of_obj2[0x10];
2295
2296         u8         reserved_at_a0[0x20];
2297
2298         u8         device_opaque[0x40];
2299
2300         u8         mkey[0x20];
2301
2302         u8         size[0x20];
2303
2304         u8         address[0x40];
2305
2306         u8         inline_data[52][0x20];
2307 };
2308
2309 struct mlx5_ifc_resource_dump_menu_record_bits {
2310         u8         reserved_at_0[0x4];
2311         u8         num_of_obj2_supports_active[0x1];
2312         u8         num_of_obj2_supports_all[0x1];
2313         u8         must_have_num_of_obj2[0x1];
2314         u8         support_num_of_obj2[0x1];
2315         u8         num_of_obj1_supports_active[0x1];
2316         u8         num_of_obj1_supports_all[0x1];
2317         u8         must_have_num_of_obj1[0x1];
2318         u8         support_num_of_obj1[0x1];
2319         u8         must_have_index2[0x1];
2320         u8         support_index2[0x1];
2321         u8         must_have_index1[0x1];
2322         u8         support_index1[0x1];
2323         u8         segment_type[0x10];
2324
2325         u8         segment_name[4][0x20];
2326
2327         u8         index1_name[4][0x20];
2328
2329         u8         index2_name[4][0x20];
2330 };
2331
2332 struct mlx5_ifc_resource_dump_segment_header_bits {
2333         u8         length_dw[0x10];
2334         u8         segment_type[0x10];
2335 };
2336
2337 struct mlx5_ifc_resource_dump_command_segment_bits {
2338         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2339
2340         u8         segment_called[0x10];
2341         u8         vhca_id[0x10];
2342
2343         u8         index1[0x20];
2344
2345         u8         index2[0x20];
2346
2347         u8         num_of_obj1[0x10];
2348         u8         num_of_obj2[0x10];
2349 };
2350
2351 struct mlx5_ifc_resource_dump_error_segment_bits {
2352         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2353
2354         u8         reserved_at_20[0x10];
2355         u8         syndrome_id[0x10];
2356
2357         u8         reserved_at_40[0x40];
2358
2359         u8         error[8][0x20];
2360 };
2361
2362 struct mlx5_ifc_resource_dump_info_segment_bits {
2363         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2364
2365         u8         reserved_at_20[0x18];
2366         u8         dump_version[0x8];
2367
2368         u8         hw_version[0x20];
2369
2370         u8         fw_version[0x20];
2371 };
2372
2373 struct mlx5_ifc_resource_dump_menu_segment_bits {
2374         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2375
2376         u8         reserved_at_20[0x10];
2377         u8         num_of_records[0x10];
2378
2379         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2380 };
2381
2382 struct mlx5_ifc_resource_dump_resource_segment_bits {
2383         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2384
2385         u8         reserved_at_20[0x20];
2386
2387         u8         index1[0x20];
2388
2389         u8         index2[0x20];
2390
2391         u8         payload[][0x20];
2392 };
2393
2394 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2395         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2396 };
2397
2398 struct mlx5_ifc_menu_resource_dump_response_bits {
2399         struct mlx5_ifc_resource_dump_info_segment_bits info;
2400         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2401         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2402         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2403 };
2404
2405 enum {
2406         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2407         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2408         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2409         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2410 };
2411
2412 struct mlx5_ifc_modify_field_select_bits {
2413         u8         modify_field_select[0x20];
2414 };
2415
2416 struct mlx5_ifc_field_select_r_roce_np_bits {
2417         u8         field_select_r_roce_np[0x20];
2418 };
2419
2420 struct mlx5_ifc_field_select_r_roce_rp_bits {
2421         u8         field_select_r_roce_rp[0x20];
2422 };
2423
2424 enum {
2425         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2426         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2427         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2428         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2429         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2430         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2431         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2432         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2433         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2434         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2435 };
2436
2437 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2438         u8         field_select_8021qaurp[0x20];
2439 };
2440
2441 struct mlx5_ifc_phys_layer_cntrs_bits {
2442         u8         time_since_last_clear_high[0x20];
2443
2444         u8         time_since_last_clear_low[0x20];
2445
2446         u8         symbol_errors_high[0x20];
2447
2448         u8         symbol_errors_low[0x20];
2449
2450         u8         sync_headers_errors_high[0x20];
2451
2452         u8         sync_headers_errors_low[0x20];
2453
2454         u8         edpl_bip_errors_lane0_high[0x20];
2455
2456         u8         edpl_bip_errors_lane0_low[0x20];
2457
2458         u8         edpl_bip_errors_lane1_high[0x20];
2459
2460         u8         edpl_bip_errors_lane1_low[0x20];
2461
2462         u8         edpl_bip_errors_lane2_high[0x20];
2463
2464         u8         edpl_bip_errors_lane2_low[0x20];
2465
2466         u8         edpl_bip_errors_lane3_high[0x20];
2467
2468         u8         edpl_bip_errors_lane3_low[0x20];
2469
2470         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2471
2472         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2473
2474         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2475
2476         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2477
2478         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2479
2480         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2481
2482         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2483
2484         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2485
2486         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2487
2488         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2489
2490         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2491
2492         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2493
2494         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2495
2496         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2497
2498         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2499
2500         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2501
2502         u8         rs_fec_corrected_blocks_high[0x20];
2503
2504         u8         rs_fec_corrected_blocks_low[0x20];
2505
2506         u8         rs_fec_uncorrectable_blocks_high[0x20];
2507
2508         u8         rs_fec_uncorrectable_blocks_low[0x20];
2509
2510         u8         rs_fec_no_errors_blocks_high[0x20];
2511
2512         u8         rs_fec_no_errors_blocks_low[0x20];
2513
2514         u8         rs_fec_single_error_blocks_high[0x20];
2515
2516         u8         rs_fec_single_error_blocks_low[0x20];
2517
2518         u8         rs_fec_corrected_symbols_total_high[0x20];
2519
2520         u8         rs_fec_corrected_symbols_total_low[0x20];
2521
2522         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2523
2524         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2525
2526         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2527
2528         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2529
2530         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2531
2532         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2533
2534         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2535
2536         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2537
2538         u8         link_down_events[0x20];
2539
2540         u8         successful_recovery_events[0x20];
2541
2542         u8         reserved_at_640[0x180];
2543 };
2544
2545 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2546         u8         time_since_last_clear_high[0x20];
2547
2548         u8         time_since_last_clear_low[0x20];
2549
2550         u8         phy_received_bits_high[0x20];
2551
2552         u8         phy_received_bits_low[0x20];
2553
2554         u8         phy_symbol_errors_high[0x20];
2555
2556         u8         phy_symbol_errors_low[0x20];
2557
2558         u8         phy_corrected_bits_high[0x20];
2559
2560         u8         phy_corrected_bits_low[0x20];
2561
2562         u8         phy_corrected_bits_lane0_high[0x20];
2563
2564         u8         phy_corrected_bits_lane0_low[0x20];
2565
2566         u8         phy_corrected_bits_lane1_high[0x20];
2567
2568         u8         phy_corrected_bits_lane1_low[0x20];
2569
2570         u8         phy_corrected_bits_lane2_high[0x20];
2571
2572         u8         phy_corrected_bits_lane2_low[0x20];
2573
2574         u8         phy_corrected_bits_lane3_high[0x20];
2575
2576         u8         phy_corrected_bits_lane3_low[0x20];
2577
2578         u8         reserved_at_200[0x5c0];
2579 };
2580
2581 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2582         u8         symbol_error_counter[0x10];
2583
2584         u8         link_error_recovery_counter[0x8];
2585
2586         u8         link_downed_counter[0x8];
2587
2588         u8         port_rcv_errors[0x10];
2589
2590         u8         port_rcv_remote_physical_errors[0x10];
2591
2592         u8         port_rcv_switch_relay_errors[0x10];
2593
2594         u8         port_xmit_discards[0x10];
2595
2596         u8         port_xmit_constraint_errors[0x8];
2597
2598         u8         port_rcv_constraint_errors[0x8];
2599
2600         u8         reserved_at_70[0x8];
2601
2602         u8         link_overrun_errors[0x8];
2603
2604         u8         reserved_at_80[0x10];
2605
2606         u8         vl_15_dropped[0x10];
2607
2608         u8         reserved_at_a0[0x80];
2609
2610         u8         port_xmit_wait[0x20];
2611 };
2612
2613 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2614         u8         transmit_queue_high[0x20];
2615
2616         u8         transmit_queue_low[0x20];
2617
2618         u8         no_buffer_discard_uc_high[0x20];
2619
2620         u8         no_buffer_discard_uc_low[0x20];
2621
2622         u8         reserved_at_80[0x740];
2623 };
2624
2625 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2626         u8         wred_discard_high[0x20];
2627
2628         u8         wred_discard_low[0x20];
2629
2630         u8         ecn_marked_tc_high[0x20];
2631
2632         u8         ecn_marked_tc_low[0x20];
2633
2634         u8         reserved_at_80[0x740];
2635 };
2636
2637 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2638         u8         rx_octets_high[0x20];
2639
2640         u8         rx_octets_low[0x20];
2641
2642         u8         reserved_at_40[0xc0];
2643
2644         u8         rx_frames_high[0x20];
2645
2646         u8         rx_frames_low[0x20];
2647
2648         u8         tx_octets_high[0x20];
2649
2650         u8         tx_octets_low[0x20];
2651
2652         u8         reserved_at_180[0xc0];
2653
2654         u8         tx_frames_high[0x20];
2655
2656         u8         tx_frames_low[0x20];
2657
2658         u8         rx_pause_high[0x20];
2659
2660         u8         rx_pause_low[0x20];
2661
2662         u8         rx_pause_duration_high[0x20];
2663
2664         u8         rx_pause_duration_low[0x20];
2665
2666         u8         tx_pause_high[0x20];
2667
2668         u8         tx_pause_low[0x20];
2669
2670         u8         tx_pause_duration_high[0x20];
2671
2672         u8         tx_pause_duration_low[0x20];
2673
2674         u8         rx_pause_transition_high[0x20];
2675
2676         u8         rx_pause_transition_low[0x20];
2677
2678         u8         rx_discards_high[0x20];
2679
2680         u8         rx_discards_low[0x20];
2681
2682         u8         device_stall_minor_watermark_cnt_high[0x20];
2683
2684         u8         device_stall_minor_watermark_cnt_low[0x20];
2685
2686         u8         device_stall_critical_watermark_cnt_high[0x20];
2687
2688         u8         device_stall_critical_watermark_cnt_low[0x20];
2689
2690         u8         reserved_at_480[0x340];
2691 };
2692
2693 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2694         u8         port_transmit_wait_high[0x20];
2695
2696         u8         port_transmit_wait_low[0x20];
2697
2698         u8         reserved_at_40[0x100];
2699
2700         u8         rx_buffer_almost_full_high[0x20];
2701
2702         u8         rx_buffer_almost_full_low[0x20];
2703
2704         u8         rx_buffer_full_high[0x20];
2705
2706         u8         rx_buffer_full_low[0x20];
2707
2708         u8         rx_icrc_encapsulated_high[0x20];
2709
2710         u8         rx_icrc_encapsulated_low[0x20];
2711
2712         u8         reserved_at_200[0x5c0];
2713 };
2714
2715 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2716         u8         dot3stats_alignment_errors_high[0x20];
2717
2718         u8         dot3stats_alignment_errors_low[0x20];
2719
2720         u8         dot3stats_fcs_errors_high[0x20];
2721
2722         u8         dot3stats_fcs_errors_low[0x20];
2723
2724         u8         dot3stats_single_collision_frames_high[0x20];
2725
2726         u8         dot3stats_single_collision_frames_low[0x20];
2727
2728         u8         dot3stats_multiple_collision_frames_high[0x20];
2729
2730         u8         dot3stats_multiple_collision_frames_low[0x20];
2731
2732         u8         dot3stats_sqe_test_errors_high[0x20];
2733
2734         u8         dot3stats_sqe_test_errors_low[0x20];
2735
2736         u8         dot3stats_deferred_transmissions_high[0x20];
2737
2738         u8         dot3stats_deferred_transmissions_low[0x20];
2739
2740         u8         dot3stats_late_collisions_high[0x20];
2741
2742         u8         dot3stats_late_collisions_low[0x20];
2743
2744         u8         dot3stats_excessive_collisions_high[0x20];
2745
2746         u8         dot3stats_excessive_collisions_low[0x20];
2747
2748         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2749
2750         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2751
2752         u8         dot3stats_carrier_sense_errors_high[0x20];
2753
2754         u8         dot3stats_carrier_sense_errors_low[0x20];
2755
2756         u8         dot3stats_frame_too_longs_high[0x20];
2757
2758         u8         dot3stats_frame_too_longs_low[0x20];
2759
2760         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2761
2762         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2763
2764         u8         dot3stats_symbol_errors_high[0x20];
2765
2766         u8         dot3stats_symbol_errors_low[0x20];
2767
2768         u8         dot3control_in_unknown_opcodes_high[0x20];
2769
2770         u8         dot3control_in_unknown_opcodes_low[0x20];
2771
2772         u8         dot3in_pause_frames_high[0x20];
2773
2774         u8         dot3in_pause_frames_low[0x20];
2775
2776         u8         dot3out_pause_frames_high[0x20];
2777
2778         u8         dot3out_pause_frames_low[0x20];
2779
2780         u8         reserved_at_400[0x3c0];
2781 };
2782
2783 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2784         u8         ether_stats_drop_events_high[0x20];
2785
2786         u8         ether_stats_drop_events_low[0x20];
2787
2788         u8         ether_stats_octets_high[0x20];
2789
2790         u8         ether_stats_octets_low[0x20];
2791
2792         u8         ether_stats_pkts_high[0x20];
2793
2794         u8         ether_stats_pkts_low[0x20];
2795
2796         u8         ether_stats_broadcast_pkts_high[0x20];
2797
2798         u8         ether_stats_broadcast_pkts_low[0x20];
2799
2800         u8         ether_stats_multicast_pkts_high[0x20];
2801
2802         u8         ether_stats_multicast_pkts_low[0x20];
2803
2804         u8         ether_stats_crc_align_errors_high[0x20];
2805
2806         u8         ether_stats_crc_align_errors_low[0x20];
2807
2808         u8         ether_stats_undersize_pkts_high[0x20];
2809
2810         u8         ether_stats_undersize_pkts_low[0x20];
2811
2812         u8         ether_stats_oversize_pkts_high[0x20];
2813
2814         u8         ether_stats_oversize_pkts_low[0x20];
2815
2816         u8         ether_stats_fragments_high[0x20];
2817
2818         u8         ether_stats_fragments_low[0x20];
2819
2820         u8         ether_stats_jabbers_high[0x20];
2821
2822         u8         ether_stats_jabbers_low[0x20];
2823
2824         u8         ether_stats_collisions_high[0x20];
2825
2826         u8         ether_stats_collisions_low[0x20];
2827
2828         u8         ether_stats_pkts64octets_high[0x20];
2829
2830         u8         ether_stats_pkts64octets_low[0x20];
2831
2832         u8         ether_stats_pkts65to127octets_high[0x20];
2833
2834         u8         ether_stats_pkts65to127octets_low[0x20];
2835
2836         u8         ether_stats_pkts128to255octets_high[0x20];
2837
2838         u8         ether_stats_pkts128to255octets_low[0x20];
2839
2840         u8         ether_stats_pkts256to511octets_high[0x20];
2841
2842         u8         ether_stats_pkts256to511octets_low[0x20];
2843
2844         u8         ether_stats_pkts512to1023octets_high[0x20];
2845
2846         u8         ether_stats_pkts512to1023octets_low[0x20];
2847
2848         u8         ether_stats_pkts1024to1518octets_high[0x20];
2849
2850         u8         ether_stats_pkts1024to1518octets_low[0x20];
2851
2852         u8         ether_stats_pkts1519to2047octets_high[0x20];
2853
2854         u8         ether_stats_pkts1519to2047octets_low[0x20];
2855
2856         u8         ether_stats_pkts2048to4095octets_high[0x20];
2857
2858         u8         ether_stats_pkts2048to4095octets_low[0x20];
2859
2860         u8         ether_stats_pkts4096to8191octets_high[0x20];
2861
2862         u8         ether_stats_pkts4096to8191octets_low[0x20];
2863
2864         u8         ether_stats_pkts8192to10239octets_high[0x20];
2865
2866         u8         ether_stats_pkts8192to10239octets_low[0x20];
2867
2868         u8         reserved_at_540[0x280];
2869 };
2870
2871 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2872         u8         if_in_octets_high[0x20];
2873
2874         u8         if_in_octets_low[0x20];
2875
2876         u8         if_in_ucast_pkts_high[0x20];
2877
2878         u8         if_in_ucast_pkts_low[0x20];
2879
2880         u8         if_in_discards_high[0x20];
2881
2882         u8         if_in_discards_low[0x20];
2883
2884         u8         if_in_errors_high[0x20];
2885
2886         u8         if_in_errors_low[0x20];
2887
2888         u8         if_in_unknown_protos_high[0x20];
2889
2890         u8         if_in_unknown_protos_low[0x20];
2891
2892         u8         if_out_octets_high[0x20];
2893
2894         u8         if_out_octets_low[0x20];
2895
2896         u8         if_out_ucast_pkts_high[0x20];
2897
2898         u8         if_out_ucast_pkts_low[0x20];
2899
2900         u8         if_out_discards_high[0x20];
2901
2902         u8         if_out_discards_low[0x20];
2903
2904         u8         if_out_errors_high[0x20];
2905
2906         u8         if_out_errors_low[0x20];
2907
2908         u8         if_in_multicast_pkts_high[0x20];
2909
2910         u8         if_in_multicast_pkts_low[0x20];
2911
2912         u8         if_in_broadcast_pkts_high[0x20];
2913
2914         u8         if_in_broadcast_pkts_low[0x20];
2915
2916         u8         if_out_multicast_pkts_high[0x20];
2917
2918         u8         if_out_multicast_pkts_low[0x20];
2919
2920         u8         if_out_broadcast_pkts_high[0x20];
2921
2922         u8         if_out_broadcast_pkts_low[0x20];
2923
2924         u8         reserved_at_340[0x480];
2925 };
2926
2927 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2928         u8         a_frames_transmitted_ok_high[0x20];
2929
2930         u8         a_frames_transmitted_ok_low[0x20];
2931
2932         u8         a_frames_received_ok_high[0x20];
2933
2934         u8         a_frames_received_ok_low[0x20];
2935
2936         u8         a_frame_check_sequence_errors_high[0x20];
2937
2938         u8         a_frame_check_sequence_errors_low[0x20];
2939
2940         u8         a_alignment_errors_high[0x20];
2941
2942         u8         a_alignment_errors_low[0x20];
2943
2944         u8         a_octets_transmitted_ok_high[0x20];
2945
2946         u8         a_octets_transmitted_ok_low[0x20];
2947
2948         u8         a_octets_received_ok_high[0x20];
2949
2950         u8         a_octets_received_ok_low[0x20];
2951
2952         u8         a_multicast_frames_xmitted_ok_high[0x20];
2953
2954         u8         a_multicast_frames_xmitted_ok_low[0x20];
2955
2956         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2957
2958         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2959
2960         u8         a_multicast_frames_received_ok_high[0x20];
2961
2962         u8         a_multicast_frames_received_ok_low[0x20];
2963
2964         u8         a_broadcast_frames_received_ok_high[0x20];
2965
2966         u8         a_broadcast_frames_received_ok_low[0x20];
2967
2968         u8         a_in_range_length_errors_high[0x20];
2969
2970         u8         a_in_range_length_errors_low[0x20];
2971
2972         u8         a_out_of_range_length_field_high[0x20];
2973
2974         u8         a_out_of_range_length_field_low[0x20];
2975
2976         u8         a_frame_too_long_errors_high[0x20];
2977
2978         u8         a_frame_too_long_errors_low[0x20];
2979
2980         u8         a_symbol_error_during_carrier_high[0x20];
2981
2982         u8         a_symbol_error_during_carrier_low[0x20];
2983
2984         u8         a_mac_control_frames_transmitted_high[0x20];
2985
2986         u8         a_mac_control_frames_transmitted_low[0x20];
2987
2988         u8         a_mac_control_frames_received_high[0x20];
2989
2990         u8         a_mac_control_frames_received_low[0x20];
2991
2992         u8         a_unsupported_opcodes_received_high[0x20];
2993
2994         u8         a_unsupported_opcodes_received_low[0x20];
2995
2996         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2997
2998         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2999
3000         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3001
3002         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3003
3004         u8         reserved_at_4c0[0x300];
3005 };
3006
3007 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3008         u8         life_time_counter_high[0x20];
3009
3010         u8         life_time_counter_low[0x20];
3011
3012         u8         rx_errors[0x20];
3013
3014         u8         tx_errors[0x20];
3015
3016         u8         l0_to_recovery_eieos[0x20];
3017
3018         u8         l0_to_recovery_ts[0x20];
3019
3020         u8         l0_to_recovery_framing[0x20];
3021
3022         u8         l0_to_recovery_retrain[0x20];
3023
3024         u8         crc_error_dllp[0x20];
3025
3026         u8         crc_error_tlp[0x20];
3027
3028         u8         tx_overflow_buffer_pkt_high[0x20];
3029
3030         u8         tx_overflow_buffer_pkt_low[0x20];
3031
3032         u8         outbound_stalled_reads[0x20];
3033
3034         u8         outbound_stalled_writes[0x20];
3035
3036         u8         outbound_stalled_reads_events[0x20];
3037
3038         u8         outbound_stalled_writes_events[0x20];
3039
3040         u8         reserved_at_200[0x5c0];
3041 };
3042
3043 struct mlx5_ifc_cmd_inter_comp_event_bits {
3044         u8         command_completion_vector[0x20];
3045
3046         u8         reserved_at_20[0xc0];
3047 };
3048
3049 struct mlx5_ifc_stall_vl_event_bits {
3050         u8         reserved_at_0[0x18];
3051         u8         port_num[0x1];
3052         u8         reserved_at_19[0x3];
3053         u8         vl[0x4];
3054
3055         u8         reserved_at_20[0xa0];
3056 };
3057
3058 struct mlx5_ifc_db_bf_congestion_event_bits {
3059         u8         event_subtype[0x8];
3060         u8         reserved_at_8[0x8];
3061         u8         congestion_level[0x8];
3062         u8         reserved_at_18[0x8];
3063
3064         u8         reserved_at_20[0xa0];
3065 };
3066
3067 struct mlx5_ifc_gpio_event_bits {
3068         u8         reserved_at_0[0x60];
3069
3070         u8         gpio_event_hi[0x20];
3071
3072         u8         gpio_event_lo[0x20];
3073
3074         u8         reserved_at_a0[0x40];
3075 };
3076
3077 struct mlx5_ifc_port_state_change_event_bits {
3078         u8         reserved_at_0[0x40];
3079
3080         u8         port_num[0x4];
3081         u8         reserved_at_44[0x1c];
3082
3083         u8         reserved_at_60[0x80];
3084 };
3085
3086 struct mlx5_ifc_dropped_packet_logged_bits {
3087         u8         reserved_at_0[0xe0];
3088 };
3089
3090 struct mlx5_ifc_default_timeout_bits {
3091         u8         to_multiplier[0x3];
3092         u8         reserved_at_3[0x9];
3093         u8         to_value[0x14];
3094 };
3095
3096 struct mlx5_ifc_dtor_reg_bits {
3097         u8         reserved_at_0[0x20];
3098
3099         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3100
3101         u8         reserved_at_40[0x60];
3102
3103         struct mlx5_ifc_default_timeout_bits health_poll_to;
3104
3105         struct mlx5_ifc_default_timeout_bits full_crdump_to;
3106
3107         struct mlx5_ifc_default_timeout_bits fw_reset_to;
3108
3109         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3110
3111         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3112
3113         struct mlx5_ifc_default_timeout_bits tear_down_to;
3114
3115         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3116
3117         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3118
3119         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3120
3121         struct mlx5_ifc_default_timeout_bits reset_unload_to;
3122
3123         u8         reserved_at_1c0[0x20];
3124 };
3125
3126 enum {
3127         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3128         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3129 };
3130
3131 struct mlx5_ifc_cq_error_bits {
3132         u8         reserved_at_0[0x8];
3133         u8         cqn[0x18];
3134
3135         u8         reserved_at_20[0x20];
3136
3137         u8         reserved_at_40[0x18];
3138         u8         syndrome[0x8];
3139
3140         u8         reserved_at_60[0x80];
3141 };
3142
3143 struct mlx5_ifc_rdma_page_fault_event_bits {
3144         u8         bytes_committed[0x20];
3145
3146         u8         r_key[0x20];
3147
3148         u8         reserved_at_40[0x10];
3149         u8         packet_len[0x10];
3150
3151         u8         rdma_op_len[0x20];
3152
3153         u8         rdma_va[0x40];
3154
3155         u8         reserved_at_c0[0x5];
3156         u8         rdma[0x1];
3157         u8         write[0x1];
3158         u8         requestor[0x1];
3159         u8         qp_number[0x18];
3160 };
3161
3162 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3163         u8         bytes_committed[0x20];
3164
3165         u8         reserved_at_20[0x10];
3166         u8         wqe_index[0x10];
3167
3168         u8         reserved_at_40[0x10];
3169         u8         len[0x10];
3170
3171         u8         reserved_at_60[0x60];
3172
3173         u8         reserved_at_c0[0x5];
3174         u8         rdma[0x1];
3175         u8         write_read[0x1];
3176         u8         requestor[0x1];
3177         u8         qpn[0x18];
3178 };
3179
3180 struct mlx5_ifc_qp_events_bits {
3181         u8         reserved_at_0[0xa0];
3182
3183         u8         type[0x8];
3184         u8         reserved_at_a8[0x18];
3185
3186         u8         reserved_at_c0[0x8];
3187         u8         qpn_rqn_sqn[0x18];
3188 };
3189
3190 struct mlx5_ifc_dct_events_bits {
3191         u8         reserved_at_0[0xc0];
3192
3193         u8         reserved_at_c0[0x8];
3194         u8         dct_number[0x18];
3195 };
3196
3197 struct mlx5_ifc_comp_event_bits {
3198         u8         reserved_at_0[0xc0];
3199
3200         u8         reserved_at_c0[0x8];
3201         u8         cq_number[0x18];
3202 };
3203
3204 enum {
3205         MLX5_QPC_STATE_RST        = 0x0,
3206         MLX5_QPC_STATE_INIT       = 0x1,
3207         MLX5_QPC_STATE_RTR        = 0x2,
3208         MLX5_QPC_STATE_RTS        = 0x3,
3209         MLX5_QPC_STATE_SQER       = 0x4,
3210         MLX5_QPC_STATE_ERR        = 0x6,
3211         MLX5_QPC_STATE_SQD        = 0x7,
3212         MLX5_QPC_STATE_SUSPENDED  = 0x9,
3213 };
3214
3215 enum {
3216         MLX5_QPC_ST_RC            = 0x0,
3217         MLX5_QPC_ST_UC            = 0x1,
3218         MLX5_QPC_ST_UD            = 0x2,
3219         MLX5_QPC_ST_XRC           = 0x3,
3220         MLX5_QPC_ST_DCI           = 0x5,
3221         MLX5_QPC_ST_QP0           = 0x7,
3222         MLX5_QPC_ST_QP1           = 0x8,
3223         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3224         MLX5_QPC_ST_REG_UMR       = 0xc,
3225 };
3226
3227 enum {
3228         MLX5_QPC_PM_STATE_ARMED     = 0x0,
3229         MLX5_QPC_PM_STATE_REARM     = 0x1,
3230         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3231         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3232 };
3233
3234 enum {
3235         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3236 };
3237
3238 enum {
3239         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3240         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3241 };
3242
3243 enum {
3244         MLX5_QPC_MTU_256_BYTES        = 0x1,
3245         MLX5_QPC_MTU_512_BYTES        = 0x2,
3246         MLX5_QPC_MTU_1K_BYTES         = 0x3,
3247         MLX5_QPC_MTU_2K_BYTES         = 0x4,
3248         MLX5_QPC_MTU_4K_BYTES         = 0x5,
3249         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3250 };
3251
3252 enum {
3253         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3254         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3255         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3256         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3257         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3258         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3259         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3260         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3261 };
3262
3263 enum {
3264         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3265         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3266         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3267 };
3268
3269 enum {
3270         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3271         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3272         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3273 };
3274
3275 enum {
3276         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3277         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3278         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3279 };
3280
3281 struct mlx5_ifc_qpc_bits {
3282         u8         state[0x4];
3283         u8         lag_tx_port_affinity[0x4];
3284         u8         st[0x8];
3285         u8         reserved_at_10[0x2];
3286         u8         isolate_vl_tc[0x1];
3287         u8         pm_state[0x2];
3288         u8         reserved_at_15[0x1];
3289         u8         req_e2e_credit_mode[0x2];
3290         u8         offload_type[0x4];
3291         u8         end_padding_mode[0x2];
3292         u8         reserved_at_1e[0x2];
3293
3294         u8         wq_signature[0x1];
3295         u8         block_lb_mc[0x1];
3296         u8         atomic_like_write_en[0x1];
3297         u8         latency_sensitive[0x1];
3298         u8         reserved_at_24[0x1];
3299         u8         drain_sigerr[0x1];
3300         u8         reserved_at_26[0x2];
3301         u8         pd[0x18];
3302
3303         u8         mtu[0x3];
3304         u8         log_msg_max[0x5];
3305         u8         reserved_at_48[0x1];
3306         u8         log_rq_size[0x4];
3307         u8         log_rq_stride[0x3];
3308         u8         no_sq[0x1];
3309         u8         log_sq_size[0x4];
3310         u8         reserved_at_55[0x1];
3311         u8         retry_mode[0x2];
3312         u8         ts_format[0x2];
3313         u8         reserved_at_5a[0x1];
3314         u8         rlky[0x1];
3315         u8         ulp_stateless_offload_mode[0x4];
3316
3317         u8         counter_set_id[0x8];
3318         u8         uar_page[0x18];
3319
3320         u8         reserved_at_80[0x8];
3321         u8         user_index[0x18];
3322
3323         u8         reserved_at_a0[0x3];
3324         u8         log_page_size[0x5];
3325         u8         remote_qpn[0x18];
3326
3327         struct mlx5_ifc_ads_bits primary_address_path;
3328
3329         struct mlx5_ifc_ads_bits secondary_address_path;
3330
3331         u8         log_ack_req_freq[0x4];
3332         u8         reserved_at_384[0x4];
3333         u8         log_sra_max[0x3];
3334         u8         reserved_at_38b[0x2];
3335         u8         retry_count[0x3];
3336         u8         rnr_retry[0x3];
3337         u8         reserved_at_393[0x1];
3338         u8         fre[0x1];
3339         u8         cur_rnr_retry[0x3];
3340         u8         cur_retry_count[0x3];
3341         u8         reserved_at_39b[0x5];
3342
3343         u8         reserved_at_3a0[0x20];
3344
3345         u8         reserved_at_3c0[0x8];
3346         u8         next_send_psn[0x18];
3347
3348         u8         reserved_at_3e0[0x3];
3349         u8         log_num_dci_stream_channels[0x5];
3350         u8         cqn_snd[0x18];
3351
3352         u8         reserved_at_400[0x3];
3353         u8         log_num_dci_errored_streams[0x5];
3354         u8         deth_sqpn[0x18];
3355
3356         u8         reserved_at_420[0x20];
3357
3358         u8         reserved_at_440[0x8];
3359         u8         last_acked_psn[0x18];
3360
3361         u8         reserved_at_460[0x8];
3362         u8         ssn[0x18];
3363
3364         u8         reserved_at_480[0x8];
3365         u8         log_rra_max[0x3];
3366         u8         reserved_at_48b[0x1];
3367         u8         atomic_mode[0x4];
3368         u8         rre[0x1];
3369         u8         rwe[0x1];
3370         u8         rae[0x1];
3371         u8         reserved_at_493[0x1];
3372         u8         page_offset[0x6];
3373         u8         reserved_at_49a[0x3];
3374         u8         cd_slave_receive[0x1];
3375         u8         cd_slave_send[0x1];
3376         u8         cd_master[0x1];
3377
3378         u8         reserved_at_4a0[0x3];
3379         u8         min_rnr_nak[0x5];
3380         u8         next_rcv_psn[0x18];
3381
3382         u8         reserved_at_4c0[0x8];
3383         u8         xrcd[0x18];
3384
3385         u8         reserved_at_4e0[0x8];
3386         u8         cqn_rcv[0x18];
3387
3388         u8         dbr_addr[0x40];
3389
3390         u8         q_key[0x20];
3391
3392         u8         reserved_at_560[0x5];
3393         u8         rq_type[0x3];
3394         u8         srqn_rmpn_xrqn[0x18];
3395
3396         u8         reserved_at_580[0x8];
3397         u8         rmsn[0x18];
3398
3399         u8         hw_sq_wqebb_counter[0x10];
3400         u8         sw_sq_wqebb_counter[0x10];
3401
3402         u8         hw_rq_counter[0x20];
3403
3404         u8         sw_rq_counter[0x20];
3405
3406         u8         reserved_at_600[0x20];
3407
3408         u8         reserved_at_620[0xf];
3409         u8         cgs[0x1];
3410         u8         cs_req[0x8];
3411         u8         cs_res[0x8];
3412
3413         u8         dc_access_key[0x40];
3414
3415         u8         reserved_at_680[0x3];
3416         u8         dbr_umem_valid[0x1];
3417
3418         u8         reserved_at_684[0xbc];
3419 };
3420
3421 struct mlx5_ifc_roce_addr_layout_bits {
3422         u8         source_l3_address[16][0x8];
3423
3424         u8         reserved_at_80[0x3];
3425         u8         vlan_valid[0x1];
3426         u8         vlan_id[0xc];
3427         u8         source_mac_47_32[0x10];
3428
3429         u8         source_mac_31_0[0x20];
3430
3431         u8         reserved_at_c0[0x14];
3432         u8         roce_l3_type[0x4];
3433         u8         roce_version[0x8];
3434
3435         u8         reserved_at_e0[0x20];
3436 };
3437
3438 struct mlx5_ifc_shampo_cap_bits {
3439         u8    reserved_at_0[0x3];
3440         u8    shampo_log_max_reservation_size[0x5];
3441         u8    reserved_at_8[0x3];
3442         u8    shampo_log_min_reservation_size[0x5];
3443         u8    shampo_min_mss_size[0x10];
3444
3445         u8    reserved_at_20[0x3];
3446         u8    shampo_max_log_headers_entry_size[0x5];
3447         u8    reserved_at_28[0x18];
3448
3449         u8    reserved_at_40[0x7c0];
3450 };
3451
3452 struct mlx5_ifc_crypto_cap_bits {
3453         u8    reserved_at_0[0x3];
3454         u8    synchronize_dek[0x1];
3455         u8    int_kek_manual[0x1];
3456         u8    int_kek_auto[0x1];
3457         u8    reserved_at_6[0x1a];
3458
3459         u8    reserved_at_20[0x3];
3460         u8    log_dek_max_alloc[0x5];
3461         u8    reserved_at_28[0x3];
3462         u8    log_max_num_deks[0x5];
3463         u8    reserved_at_30[0x10];
3464
3465         u8    reserved_at_40[0x20];
3466
3467         u8    reserved_at_60[0x3];
3468         u8    log_dek_granularity[0x5];
3469         u8    reserved_at_68[0x3];
3470         u8    log_max_num_int_kek[0x5];
3471         u8    sw_wrapped_dek[0x10];
3472
3473         u8    reserved_at_80[0x780];
3474 };
3475
3476 union mlx5_ifc_hca_cap_union_bits {
3477         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3478         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3479         struct mlx5_ifc_odp_cap_bits odp_cap;
3480         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3481         struct mlx5_ifc_roce_cap_bits roce_cap;
3482         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3483         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3484         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3485         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3486         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3487         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3488         struct mlx5_ifc_qos_cap_bits qos_cap;
3489         struct mlx5_ifc_debug_cap_bits debug_cap;
3490         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3491         struct mlx5_ifc_tls_cap_bits tls_cap;
3492         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3493         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3494         struct mlx5_ifc_shampo_cap_bits shampo_cap;
3495         struct mlx5_ifc_macsec_cap_bits macsec_cap;
3496         struct mlx5_ifc_crypto_cap_bits crypto_cap;
3497         u8         reserved_at_0[0x8000];
3498 };
3499
3500 enum {
3501         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3502         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3503         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3504         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3505         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3506         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3507         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3508         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3509         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3510         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3511         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3512         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3513         MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3514         MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3515 };
3516
3517 enum {
3518         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3519         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3520         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3521 };
3522
3523 enum {
3524         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3525         MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3526 };
3527
3528 struct mlx5_ifc_vlan_bits {
3529         u8         ethtype[0x10];
3530         u8         prio[0x3];
3531         u8         cfi[0x1];
3532         u8         vid[0xc];
3533 };
3534
3535 enum {
3536         MLX5_FLOW_METER_COLOR_RED       = 0x0,
3537         MLX5_FLOW_METER_COLOR_YELLOW    = 0x1,
3538         MLX5_FLOW_METER_COLOR_GREEN     = 0x2,
3539         MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3540 };
3541
3542 enum {
3543         MLX5_EXE_ASO_FLOW_METER         = 0x2,
3544 };
3545
3546 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3547         u8        return_reg_id[0x4];
3548         u8        aso_type[0x4];
3549         u8        reserved_at_8[0x14];
3550         u8        action[0x1];
3551         u8        init_color[0x2];
3552         u8        meter_id[0x1];
3553 };
3554
3555 union mlx5_ifc_exe_aso_ctrl {
3556         struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3557 };
3558
3559 struct mlx5_ifc_execute_aso_bits {
3560         u8        valid[0x1];
3561         u8        reserved_at_1[0x7];
3562         u8        aso_object_id[0x18];
3563
3564         union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3565 };
3566
3567 struct mlx5_ifc_flow_context_bits {
3568         struct mlx5_ifc_vlan_bits push_vlan;
3569
3570         u8         group_id[0x20];
3571
3572         u8         reserved_at_40[0x8];
3573         u8         flow_tag[0x18];
3574
3575         u8         reserved_at_60[0x10];
3576         u8         action[0x10];
3577
3578         u8         extended_destination[0x1];
3579         u8         reserved_at_81[0x1];
3580         u8         flow_source[0x2];
3581         u8         encrypt_decrypt_type[0x4];
3582         u8         destination_list_size[0x18];
3583
3584         u8         reserved_at_a0[0x8];
3585         u8         flow_counter_list_size[0x18];
3586
3587         u8         packet_reformat_id[0x20];
3588
3589         u8         modify_header_id[0x20];
3590
3591         struct mlx5_ifc_vlan_bits push_vlan_2;
3592
3593         u8         encrypt_decrypt_obj_id[0x20];
3594         u8         reserved_at_140[0xc0];
3595
3596         struct mlx5_ifc_fte_match_param_bits match_value;
3597
3598         struct mlx5_ifc_execute_aso_bits execute_aso[4];
3599
3600         u8         reserved_at_1300[0x500];
3601
3602         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3603 };
3604
3605 enum {
3606         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3607         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3608 };
3609
3610 struct mlx5_ifc_xrc_srqc_bits {
3611         u8         state[0x4];
3612         u8         log_xrc_srq_size[0x4];
3613         u8         reserved_at_8[0x18];
3614
3615         u8         wq_signature[0x1];
3616         u8         cont_srq[0x1];
3617         u8         reserved_at_22[0x1];
3618         u8         rlky[0x1];
3619         u8         basic_cyclic_rcv_wqe[0x1];
3620         u8         log_rq_stride[0x3];
3621         u8         xrcd[0x18];
3622
3623         u8         page_offset[0x6];
3624         u8         reserved_at_46[0x1];
3625         u8         dbr_umem_valid[0x1];
3626         u8         cqn[0x18];
3627
3628         u8         reserved_at_60[0x20];
3629
3630         u8         user_index_equal_xrc_srqn[0x1];
3631         u8         reserved_at_81[0x1];
3632         u8         log_page_size[0x6];
3633         u8         user_index[0x18];
3634
3635         u8         reserved_at_a0[0x20];
3636
3637         u8         reserved_at_c0[0x8];
3638         u8         pd[0x18];
3639
3640         u8         lwm[0x10];
3641         u8         wqe_cnt[0x10];
3642
3643         u8         reserved_at_100[0x40];
3644
3645         u8         db_record_addr_h[0x20];
3646
3647         u8         db_record_addr_l[0x1e];
3648         u8         reserved_at_17e[0x2];
3649
3650         u8         reserved_at_180[0x80];
3651 };
3652
3653 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3654         u8         counter_error_queues[0x20];
3655
3656         u8         total_error_queues[0x20];
3657
3658         u8         send_queue_priority_update_flow[0x20];
3659
3660         u8         reserved_at_60[0x20];
3661
3662         u8         nic_receive_steering_discard[0x40];
3663
3664         u8         receive_discard_vport_down[0x40];
3665
3666         u8         transmit_discard_vport_down[0x40];
3667
3668         u8         async_eq_overrun[0x20];
3669
3670         u8         comp_eq_overrun[0x20];
3671
3672         u8         reserved_at_180[0x20];
3673
3674         u8         invalid_command[0x20];
3675
3676         u8         quota_exceeded_command[0x20];
3677
3678         u8         internal_rq_out_of_buffer[0x20];
3679
3680         u8         cq_overrun[0x20];
3681
3682         u8         eth_wqe_too_small[0x20];
3683
3684         u8         reserved_at_220[0xc0];
3685
3686         u8         generated_pkt_steering_fail[0x40];
3687
3688         u8         handled_pkt_steering_fail[0x40];
3689
3690         u8         reserved_at_360[0xc80];
3691 };
3692
3693 struct mlx5_ifc_traffic_counter_bits {
3694         u8         packets[0x40];
3695
3696         u8         octets[0x40];
3697 };
3698
3699 struct mlx5_ifc_tisc_bits {
3700         u8         strict_lag_tx_port_affinity[0x1];
3701         u8         tls_en[0x1];
3702         u8         reserved_at_2[0x2];
3703         u8         lag_tx_port_affinity[0x04];
3704
3705         u8         reserved_at_8[0x4];
3706         u8         prio[0x4];
3707         u8         reserved_at_10[0x10];
3708
3709         u8         reserved_at_20[0x100];
3710
3711         u8         reserved_at_120[0x8];
3712         u8         transport_domain[0x18];
3713
3714         u8         reserved_at_140[0x8];
3715         u8         underlay_qpn[0x18];
3716
3717         u8         reserved_at_160[0x8];
3718         u8         pd[0x18];
3719
3720         u8         reserved_at_180[0x380];
3721 };
3722
3723 enum {
3724         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3725         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3726 };
3727
3728 enum {
3729         MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3730         MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3731 };
3732
3733 enum {
3734         MLX5_RX_HASH_FN_NONE           = 0x0,
3735         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3736         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3737 };
3738
3739 enum {
3740         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3741         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3742 };
3743
3744 struct mlx5_ifc_tirc_bits {
3745         u8         reserved_at_0[0x20];
3746
3747         u8         disp_type[0x4];
3748         u8         tls_en[0x1];
3749         u8         reserved_at_25[0x1b];
3750
3751         u8         reserved_at_40[0x40];
3752
3753         u8         reserved_at_80[0x4];
3754         u8         lro_timeout_period_usecs[0x10];
3755         u8         packet_merge_mask[0x4];
3756         u8         lro_max_ip_payload_size[0x8];
3757
3758         u8         reserved_at_a0[0x40];
3759
3760         u8         reserved_at_e0[0x8];
3761         u8         inline_rqn[0x18];
3762
3763         u8         rx_hash_symmetric[0x1];
3764         u8         reserved_at_101[0x1];
3765         u8         tunneled_offload_en[0x1];
3766         u8         reserved_at_103[0x5];
3767         u8         indirect_table[0x18];
3768
3769         u8         rx_hash_fn[0x4];
3770         u8         reserved_at_124[0x2];
3771         u8         self_lb_block[0x2];
3772         u8         transport_domain[0x18];
3773
3774         u8         rx_hash_toeplitz_key[10][0x20];
3775
3776         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3777
3778         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3779
3780         u8         reserved_at_2c0[0x4c0];
3781 };
3782
3783 enum {
3784         MLX5_SRQC_STATE_GOOD   = 0x0,
3785         MLX5_SRQC_STATE_ERROR  = 0x1,
3786 };
3787
3788 struct mlx5_ifc_srqc_bits {
3789         u8         state[0x4];
3790         u8         log_srq_size[0x4];
3791         u8         reserved_at_8[0x18];
3792
3793         u8         wq_signature[0x1];
3794         u8         cont_srq[0x1];
3795         u8         reserved_at_22[0x1];
3796         u8         rlky[0x1];
3797         u8         reserved_at_24[0x1];
3798         u8         log_rq_stride[0x3];
3799         u8         xrcd[0x18];
3800
3801         u8         page_offset[0x6];
3802         u8         reserved_at_46[0x2];
3803         u8         cqn[0x18];
3804
3805         u8         reserved_at_60[0x20];
3806
3807         u8         reserved_at_80[0x2];
3808         u8         log_page_size[0x6];
3809         u8         reserved_at_88[0x18];
3810
3811         u8         reserved_at_a0[0x20];
3812
3813         u8         reserved_at_c0[0x8];
3814         u8         pd[0x18];
3815
3816         u8         lwm[0x10];
3817         u8         wqe_cnt[0x10];
3818
3819         u8         reserved_at_100[0x40];
3820
3821         u8         dbr_addr[0x40];
3822
3823         u8         reserved_at_180[0x80];
3824 };
3825
3826 enum {
3827         MLX5_SQC_STATE_RST  = 0x0,
3828         MLX5_SQC_STATE_RDY  = 0x1,
3829         MLX5_SQC_STATE_ERR  = 0x3,
3830 };
3831
3832 struct mlx5_ifc_sqc_bits {
3833         u8         rlky[0x1];
3834         u8         cd_master[0x1];
3835         u8         fre[0x1];
3836         u8         flush_in_error_en[0x1];
3837         u8         allow_multi_pkt_send_wqe[0x1];
3838         u8         min_wqe_inline_mode[0x3];
3839         u8         state[0x4];
3840         u8         reg_umr[0x1];
3841         u8         allow_swp[0x1];
3842         u8         hairpin[0x1];
3843         u8         reserved_at_f[0xb];
3844         u8         ts_format[0x2];
3845         u8         reserved_at_1c[0x4];
3846
3847         u8         reserved_at_20[0x8];
3848         u8         user_index[0x18];
3849
3850         u8         reserved_at_40[0x8];
3851         u8         cqn[0x18];
3852
3853         u8         reserved_at_60[0x8];
3854         u8         hairpin_peer_rq[0x18];
3855
3856         u8         reserved_at_80[0x10];
3857         u8         hairpin_peer_vhca[0x10];
3858
3859         u8         reserved_at_a0[0x20];
3860
3861         u8         reserved_at_c0[0x8];
3862         u8         ts_cqe_to_dest_cqn[0x18];
3863
3864         u8         reserved_at_e0[0x10];
3865         u8         packet_pacing_rate_limit_index[0x10];
3866         u8         tis_lst_sz[0x10];
3867         u8         qos_queue_group_id[0x10];
3868
3869         u8         reserved_at_120[0x40];
3870
3871         u8         reserved_at_160[0x8];
3872         u8         tis_num_0[0x18];
3873
3874         struct mlx5_ifc_wq_bits wq;
3875 };
3876
3877 enum {
3878         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3879         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3880         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3881         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3882         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3883 };
3884
3885 enum {
3886         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3887         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3888         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3889         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3890 };
3891
3892 struct mlx5_ifc_scheduling_context_bits {
3893         u8         element_type[0x8];
3894         u8         reserved_at_8[0x18];
3895
3896         u8         element_attributes[0x20];
3897
3898         u8         parent_element_id[0x20];
3899
3900         u8         reserved_at_60[0x40];
3901
3902         u8         bw_share[0x20];
3903
3904         u8         max_average_bw[0x20];
3905
3906         u8         reserved_at_e0[0x120];
3907 };
3908
3909 struct mlx5_ifc_rqtc_bits {
3910         u8    reserved_at_0[0xa0];
3911
3912         u8    reserved_at_a0[0x5];
3913         u8    list_q_type[0x3];
3914         u8    reserved_at_a8[0x8];
3915         u8    rqt_max_size[0x10];
3916
3917         u8    rq_vhca_id_format[0x1];
3918         u8    reserved_at_c1[0xf];
3919         u8    rqt_actual_size[0x10];
3920
3921         u8    reserved_at_e0[0x6a0];
3922
3923         struct mlx5_ifc_rq_num_bits rq_num[];
3924 };
3925
3926 enum {
3927         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3928         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3929 };
3930
3931 enum {
3932         MLX5_RQC_STATE_RST  = 0x0,
3933         MLX5_RQC_STATE_RDY  = 0x1,
3934         MLX5_RQC_STATE_ERR  = 0x3,
3935 };
3936
3937 enum {
3938         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3939         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3940         MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3941 };
3942
3943 enum {
3944         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3945         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3946         MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3947 };
3948
3949 struct mlx5_ifc_rqc_bits {
3950         u8         rlky[0x1];
3951         u8         delay_drop_en[0x1];
3952         u8         scatter_fcs[0x1];
3953         u8         vsd[0x1];
3954         u8         mem_rq_type[0x4];
3955         u8         state[0x4];
3956         u8         reserved_at_c[0x1];
3957         u8         flush_in_error_en[0x1];
3958         u8         hairpin[0x1];
3959         u8         reserved_at_f[0xb];
3960         u8         ts_format[0x2];
3961         u8         reserved_at_1c[0x4];
3962
3963         u8         reserved_at_20[0x8];
3964         u8         user_index[0x18];
3965
3966         u8         reserved_at_40[0x8];
3967         u8         cqn[0x18];
3968
3969         u8         counter_set_id[0x8];
3970         u8         reserved_at_68[0x18];
3971
3972         u8         reserved_at_80[0x8];
3973         u8         rmpn[0x18];
3974
3975         u8         reserved_at_a0[0x8];
3976         u8         hairpin_peer_sq[0x18];
3977
3978         u8         reserved_at_c0[0x10];
3979         u8         hairpin_peer_vhca[0x10];
3980
3981         u8         reserved_at_e0[0x46];
3982         u8         shampo_no_match_alignment_granularity[0x2];
3983         u8         reserved_at_128[0x6];
3984         u8         shampo_match_criteria_type[0x2];
3985         u8         reservation_timeout[0x10];
3986
3987         u8         reserved_at_140[0x40];
3988
3989         struct mlx5_ifc_wq_bits wq;
3990 };
3991
3992 enum {
3993         MLX5_RMPC_STATE_RDY  = 0x1,
3994         MLX5_RMPC_STATE_ERR  = 0x3,
3995 };
3996
3997 struct mlx5_ifc_rmpc_bits {
3998         u8         reserved_at_0[0x8];
3999         u8         state[0x4];
4000         u8         reserved_at_c[0x14];
4001
4002         u8         basic_cyclic_rcv_wqe[0x1];
4003         u8         reserved_at_21[0x1f];
4004
4005         u8         reserved_at_40[0x140];
4006
4007         struct mlx5_ifc_wq_bits wq;
4008 };
4009
4010 enum {
4011         VHCA_ID_TYPE_HW = 0,
4012         VHCA_ID_TYPE_SW = 1,
4013 };
4014
4015 struct mlx5_ifc_nic_vport_context_bits {
4016         u8         reserved_at_0[0x5];
4017         u8         min_wqe_inline_mode[0x3];
4018         u8         reserved_at_8[0x15];
4019         u8         disable_mc_local_lb[0x1];
4020         u8         disable_uc_local_lb[0x1];
4021         u8         roce_en[0x1];
4022
4023         u8         arm_change_event[0x1];
4024         u8         reserved_at_21[0x1a];
4025         u8         event_on_mtu[0x1];
4026         u8         event_on_promisc_change[0x1];
4027         u8         event_on_vlan_change[0x1];
4028         u8         event_on_mc_address_change[0x1];
4029         u8         event_on_uc_address_change[0x1];
4030
4031         u8         vhca_id_type[0x1];
4032         u8         reserved_at_41[0xb];
4033         u8         affiliation_criteria[0x4];
4034         u8         affiliated_vhca_id[0x10];
4035
4036         u8         reserved_at_60[0xd0];
4037
4038         u8         mtu[0x10];
4039
4040         u8         system_image_guid[0x40];
4041         u8         port_guid[0x40];
4042         u8         node_guid[0x40];
4043
4044         u8         reserved_at_200[0x140];
4045         u8         qkey_violation_counter[0x10];
4046         u8         reserved_at_350[0x430];
4047
4048         u8         promisc_uc[0x1];
4049         u8         promisc_mc[0x1];
4050         u8         promisc_all[0x1];
4051         u8         reserved_at_783[0x2];
4052         u8         allowed_list_type[0x3];
4053         u8         reserved_at_788[0xc];
4054         u8         allowed_list_size[0xc];
4055
4056         struct mlx5_ifc_mac_address_layout_bits permanent_address;
4057
4058         u8         reserved_at_7e0[0x20];
4059
4060         u8         current_uc_mac_address[][0x40];
4061 };
4062
4063 enum {
4064         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4065         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4066         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4067         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4068         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4069         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4070 };
4071
4072 struct mlx5_ifc_mkc_bits {
4073         u8         reserved_at_0[0x1];
4074         u8         free[0x1];
4075         u8         reserved_at_2[0x1];
4076         u8         access_mode_4_2[0x3];
4077         u8         reserved_at_6[0x7];
4078         u8         relaxed_ordering_write[0x1];
4079         u8         reserved_at_e[0x1];
4080         u8         small_fence_on_rdma_read_response[0x1];
4081         u8         umr_en[0x1];
4082         u8         a[0x1];
4083         u8         rw[0x1];
4084         u8         rr[0x1];
4085         u8         lw[0x1];
4086         u8         lr[0x1];
4087         u8         access_mode_1_0[0x2];
4088         u8         reserved_at_18[0x2];
4089         u8         ma_translation_mode[0x2];
4090         u8         reserved_at_1c[0x4];
4091
4092         u8         qpn[0x18];
4093         u8         mkey_7_0[0x8];
4094
4095         u8         reserved_at_40[0x20];
4096
4097         u8         length64[0x1];
4098         u8         bsf_en[0x1];
4099         u8         sync_umr[0x1];
4100         u8         reserved_at_63[0x2];
4101         u8         expected_sigerr_count[0x1];
4102         u8         reserved_at_66[0x1];
4103         u8         en_rinval[0x1];
4104         u8         pd[0x18];
4105
4106         u8         start_addr[0x40];
4107
4108         u8         len[0x40];
4109
4110         u8         bsf_octword_size[0x20];
4111
4112         u8         reserved_at_120[0x80];
4113
4114         u8         translations_octword_size[0x20];
4115
4116         u8         reserved_at_1c0[0x19];
4117         u8         relaxed_ordering_read[0x1];
4118         u8         reserved_at_1d9[0x1];
4119         u8         log_page_size[0x5];
4120
4121         u8         reserved_at_1e0[0x20];
4122 };
4123
4124 struct mlx5_ifc_pkey_bits {
4125         u8         reserved_at_0[0x10];
4126         u8         pkey[0x10];
4127 };
4128
4129 struct mlx5_ifc_array128_auto_bits {
4130         u8         array128_auto[16][0x8];
4131 };
4132
4133 struct mlx5_ifc_hca_vport_context_bits {
4134         u8         field_select[0x20];
4135
4136         u8         reserved_at_20[0xe0];
4137
4138         u8         sm_virt_aware[0x1];
4139         u8         has_smi[0x1];
4140         u8         has_raw[0x1];
4141         u8         grh_required[0x1];
4142         u8         reserved_at_104[0xc];
4143         u8         port_physical_state[0x4];
4144         u8         vport_state_policy[0x4];
4145         u8         port_state[0x4];
4146         u8         vport_state[0x4];
4147
4148         u8         reserved_at_120[0x20];
4149
4150         u8         system_image_guid[0x40];
4151
4152         u8         port_guid[0x40];
4153
4154         u8         node_guid[0x40];
4155
4156         u8         cap_mask1[0x20];
4157
4158         u8         cap_mask1_field_select[0x20];
4159
4160         u8         cap_mask2[0x20];
4161
4162         u8         cap_mask2_field_select[0x20];
4163
4164         u8         reserved_at_280[0x80];
4165
4166         u8         lid[0x10];
4167         u8         reserved_at_310[0x4];
4168         u8         init_type_reply[0x4];
4169         u8         lmc[0x3];
4170         u8         subnet_timeout[0x5];
4171
4172         u8         sm_lid[0x10];
4173         u8         sm_sl[0x4];
4174         u8         reserved_at_334[0xc];
4175
4176         u8         qkey_violation_counter[0x10];
4177         u8         pkey_violation_counter[0x10];
4178
4179         u8         reserved_at_360[0xca0];
4180 };
4181
4182 struct mlx5_ifc_esw_vport_context_bits {
4183         u8         fdb_to_vport_reg_c[0x1];
4184         u8         reserved_at_1[0x2];
4185         u8         vport_svlan_strip[0x1];
4186         u8         vport_cvlan_strip[0x1];
4187         u8         vport_svlan_insert[0x1];
4188         u8         vport_cvlan_insert[0x2];
4189         u8         fdb_to_vport_reg_c_id[0x8];
4190         u8         reserved_at_10[0x10];
4191
4192         u8         reserved_at_20[0x20];
4193
4194         u8         svlan_cfi[0x1];
4195         u8         svlan_pcp[0x3];
4196         u8         svlan_id[0xc];
4197         u8         cvlan_cfi[0x1];
4198         u8         cvlan_pcp[0x3];
4199         u8         cvlan_id[0xc];
4200
4201         u8         reserved_at_60[0x720];
4202
4203         u8         sw_steering_vport_icm_address_rx[0x40];
4204
4205         u8         sw_steering_vport_icm_address_tx[0x40];
4206 };
4207
4208 enum {
4209         MLX5_EQC_STATUS_OK                = 0x0,
4210         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4211 };
4212
4213 enum {
4214         MLX5_EQC_ST_ARMED  = 0x9,
4215         MLX5_EQC_ST_FIRED  = 0xa,
4216 };
4217
4218 struct mlx5_ifc_eqc_bits {
4219         u8         status[0x4];
4220         u8         reserved_at_4[0x9];
4221         u8         ec[0x1];
4222         u8         oi[0x1];
4223         u8         reserved_at_f[0x5];
4224         u8         st[0x4];
4225         u8         reserved_at_18[0x8];
4226
4227         u8         reserved_at_20[0x20];
4228
4229         u8         reserved_at_40[0x14];
4230         u8         page_offset[0x6];
4231         u8         reserved_at_5a[0x6];
4232
4233         u8         reserved_at_60[0x3];
4234         u8         log_eq_size[0x5];
4235         u8         uar_page[0x18];
4236
4237         u8         reserved_at_80[0x20];
4238
4239         u8         reserved_at_a0[0x14];
4240         u8         intr[0xc];
4241
4242         u8         reserved_at_c0[0x3];
4243         u8         log_page_size[0x5];
4244         u8         reserved_at_c8[0x18];
4245
4246         u8         reserved_at_e0[0x60];
4247
4248         u8         reserved_at_140[0x8];
4249         u8         consumer_counter[0x18];
4250
4251         u8         reserved_at_160[0x8];
4252         u8         producer_counter[0x18];
4253
4254         u8         reserved_at_180[0x80];
4255 };
4256
4257 enum {
4258         MLX5_DCTC_STATE_ACTIVE    = 0x0,
4259         MLX5_DCTC_STATE_DRAINING  = 0x1,
4260         MLX5_DCTC_STATE_DRAINED   = 0x2,
4261 };
4262
4263 enum {
4264         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4265         MLX5_DCTC_CS_RES_NA         = 0x1,
4266         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4267 };
4268
4269 enum {
4270         MLX5_DCTC_MTU_256_BYTES  = 0x1,
4271         MLX5_DCTC_MTU_512_BYTES  = 0x2,
4272         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4273         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4274         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4275 };
4276
4277 struct mlx5_ifc_dctc_bits {
4278         u8         reserved_at_0[0x4];
4279         u8         state[0x4];
4280         u8         reserved_at_8[0x18];
4281
4282         u8         reserved_at_20[0x8];
4283         u8         user_index[0x18];
4284
4285         u8         reserved_at_40[0x8];
4286         u8         cqn[0x18];
4287
4288         u8         counter_set_id[0x8];
4289         u8         atomic_mode[0x4];
4290         u8         rre[0x1];
4291         u8         rwe[0x1];
4292         u8         rae[0x1];
4293         u8         atomic_like_write_en[0x1];
4294         u8         latency_sensitive[0x1];
4295         u8         rlky[0x1];
4296         u8         free_ar[0x1];
4297         u8         reserved_at_73[0xd];
4298
4299         u8         reserved_at_80[0x8];
4300         u8         cs_res[0x8];
4301         u8         reserved_at_90[0x3];
4302         u8         min_rnr_nak[0x5];
4303         u8         reserved_at_98[0x8];
4304
4305         u8         reserved_at_a0[0x8];
4306         u8         srqn_xrqn[0x18];
4307
4308         u8         reserved_at_c0[0x8];
4309         u8         pd[0x18];
4310
4311         u8         tclass[0x8];
4312         u8         reserved_at_e8[0x4];
4313         u8         flow_label[0x14];
4314
4315         u8         dc_access_key[0x40];
4316
4317         u8         reserved_at_140[0x5];
4318         u8         mtu[0x3];
4319         u8         port[0x8];
4320         u8         pkey_index[0x10];
4321
4322         u8         reserved_at_160[0x8];
4323         u8         my_addr_index[0x8];
4324         u8         reserved_at_170[0x8];
4325         u8         hop_limit[0x8];
4326
4327         u8         dc_access_key_violation_count[0x20];
4328
4329         u8         reserved_at_1a0[0x14];
4330         u8         dei_cfi[0x1];
4331         u8         eth_prio[0x3];
4332         u8         ecn[0x2];
4333         u8         dscp[0x6];
4334
4335         u8         reserved_at_1c0[0x20];
4336         u8         ece[0x20];
4337 };
4338
4339 enum {
4340         MLX5_CQC_STATUS_OK             = 0x0,
4341         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4342         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4343 };
4344
4345 enum {
4346         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4347         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4348 };
4349
4350 enum {
4351         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4352         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4353         MLX5_CQC_ST_FIRED                                 = 0xa,
4354 };
4355
4356 enum {
4357         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4358         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4359         MLX5_CQ_PERIOD_NUM_MODES
4360 };
4361
4362 struct mlx5_ifc_cqc_bits {
4363         u8         status[0x4];
4364         u8         reserved_at_4[0x2];
4365         u8         dbr_umem_valid[0x1];
4366         u8         apu_cq[0x1];
4367         u8         cqe_sz[0x3];
4368         u8         cc[0x1];
4369         u8         reserved_at_c[0x1];
4370         u8         scqe_break_moderation_en[0x1];
4371         u8         oi[0x1];
4372         u8         cq_period_mode[0x2];
4373         u8         cqe_comp_en[0x1];
4374         u8         mini_cqe_res_format[0x2];
4375         u8         st[0x4];
4376         u8         reserved_at_18[0x6];
4377         u8         cqe_compression_layout[0x2];
4378
4379         u8         reserved_at_20[0x20];
4380
4381         u8         reserved_at_40[0x14];
4382         u8         page_offset[0x6];
4383         u8         reserved_at_5a[0x6];
4384
4385         u8         reserved_at_60[0x3];
4386         u8         log_cq_size[0x5];
4387         u8         uar_page[0x18];
4388
4389         u8         reserved_at_80[0x4];
4390         u8         cq_period[0xc];
4391         u8         cq_max_count[0x10];
4392
4393         u8         c_eqn_or_apu_element[0x20];
4394
4395         u8         reserved_at_c0[0x3];
4396         u8         log_page_size[0x5];
4397         u8         reserved_at_c8[0x18];
4398
4399         u8         reserved_at_e0[0x20];
4400
4401         u8         reserved_at_100[0x8];
4402         u8         last_notified_index[0x18];
4403
4404         u8         reserved_at_120[0x8];
4405         u8         last_solicit_index[0x18];
4406
4407         u8         reserved_at_140[0x8];
4408         u8         consumer_counter[0x18];
4409
4410         u8         reserved_at_160[0x8];
4411         u8         producer_counter[0x18];
4412
4413         u8         reserved_at_180[0x40];
4414
4415         u8         dbr_addr[0x40];
4416 };
4417
4418 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4419         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4420         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4421         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4422         struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4423         u8         reserved_at_0[0x800];
4424 };
4425
4426 struct mlx5_ifc_query_adapter_param_block_bits {
4427         u8         reserved_at_0[0xc0];
4428
4429         u8         reserved_at_c0[0x8];
4430         u8         ieee_vendor_id[0x18];
4431
4432         u8         reserved_at_e0[0x10];
4433         u8         vsd_vendor_id[0x10];
4434
4435         u8         vsd[208][0x8];
4436
4437         u8         vsd_contd_psid[16][0x8];
4438 };
4439
4440 enum {
4441         MLX5_XRQC_STATE_GOOD   = 0x0,
4442         MLX5_XRQC_STATE_ERROR  = 0x1,
4443 };
4444
4445 enum {
4446         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4447         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4448 };
4449
4450 enum {
4451         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4452 };
4453
4454 struct mlx5_ifc_tag_matching_topology_context_bits {
4455         u8         log_matching_list_sz[0x4];
4456         u8         reserved_at_4[0xc];
4457         u8         append_next_index[0x10];
4458
4459         u8         sw_phase_cnt[0x10];
4460         u8         hw_phase_cnt[0x10];
4461
4462         u8         reserved_at_40[0x40];
4463 };
4464
4465 struct mlx5_ifc_xrqc_bits {
4466         u8         state[0x4];
4467         u8         rlkey[0x1];
4468         u8         reserved_at_5[0xf];
4469         u8         topology[0x4];
4470         u8         reserved_at_18[0x4];
4471         u8         offload[0x4];
4472
4473         u8         reserved_at_20[0x8];
4474         u8         user_index[0x18];
4475
4476         u8         reserved_at_40[0x8];
4477         u8         cqn[0x18];
4478
4479         u8         reserved_at_60[0xa0];
4480
4481         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4482
4483         u8         reserved_at_180[0x280];
4484
4485         struct mlx5_ifc_wq_bits wq;
4486 };
4487
4488 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4489         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4490         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4491         u8         reserved_at_0[0x20];
4492 };
4493
4494 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4495         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4496         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4497         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4498         u8         reserved_at_0[0x20];
4499 };
4500
4501 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4502         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4503         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4504         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4505         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4506         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4507         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4508         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4509         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4510         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4511         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4512         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4513         u8         reserved_at_0[0x7c0];
4514 };
4515
4516 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4517         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4518         u8         reserved_at_0[0x7c0];
4519 };
4520
4521 union mlx5_ifc_event_auto_bits {
4522         struct mlx5_ifc_comp_event_bits comp_event;
4523         struct mlx5_ifc_dct_events_bits dct_events;
4524         struct mlx5_ifc_qp_events_bits qp_events;
4525         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4526         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4527         struct mlx5_ifc_cq_error_bits cq_error;
4528         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4529         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4530         struct mlx5_ifc_gpio_event_bits gpio_event;
4531         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4532         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4533         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4534         u8         reserved_at_0[0xe0];
4535 };
4536
4537 struct mlx5_ifc_health_buffer_bits {
4538         u8         reserved_at_0[0x100];
4539
4540         u8         assert_existptr[0x20];
4541
4542         u8         assert_callra[0x20];
4543
4544         u8         reserved_at_140[0x20];
4545
4546         u8         time[0x20];
4547
4548         u8         fw_version[0x20];
4549
4550         u8         hw_id[0x20];
4551
4552         u8         rfr[0x1];
4553         u8         reserved_at_1c1[0x3];
4554         u8         valid[0x1];
4555         u8         severity[0x3];
4556         u8         reserved_at_1c8[0x18];
4557
4558         u8         irisc_index[0x8];
4559         u8         synd[0x8];
4560         u8         ext_synd[0x10];
4561 };
4562
4563 struct mlx5_ifc_register_loopback_control_bits {
4564         u8         no_lb[0x1];
4565         u8         reserved_at_1[0x7];
4566         u8         port[0x8];
4567         u8         reserved_at_10[0x10];
4568
4569         u8         reserved_at_20[0x60];
4570 };
4571
4572 struct mlx5_ifc_vport_tc_element_bits {
4573         u8         traffic_class[0x4];
4574         u8         reserved_at_4[0xc];
4575         u8         vport_number[0x10];
4576 };
4577
4578 struct mlx5_ifc_vport_element_bits {
4579         u8         reserved_at_0[0x10];
4580         u8         vport_number[0x10];
4581 };
4582
4583 enum {
4584         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4585         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4586         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4587 };
4588
4589 struct mlx5_ifc_tsar_element_bits {
4590         u8         reserved_at_0[0x8];
4591         u8         tsar_type[0x8];
4592         u8         reserved_at_10[0x10];
4593 };
4594
4595 enum {
4596         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4597         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4598 };
4599
4600 struct mlx5_ifc_teardown_hca_out_bits {
4601         u8         status[0x8];
4602         u8         reserved_at_8[0x18];
4603
4604         u8         syndrome[0x20];
4605
4606         u8         reserved_at_40[0x3f];
4607
4608         u8         state[0x1];
4609 };
4610
4611 enum {
4612         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4613         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4614         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4615 };
4616
4617 struct mlx5_ifc_teardown_hca_in_bits {
4618         u8         opcode[0x10];
4619         u8         reserved_at_10[0x10];
4620
4621         u8         reserved_at_20[0x10];
4622         u8         op_mod[0x10];
4623
4624         u8         reserved_at_40[0x10];
4625         u8         profile[0x10];
4626
4627         u8         reserved_at_60[0x20];
4628 };
4629
4630 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4631         u8         status[0x8];
4632         u8         reserved_at_8[0x18];
4633
4634         u8         syndrome[0x20];
4635
4636         u8         reserved_at_40[0x40];
4637 };
4638
4639 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4640         u8         opcode[0x10];
4641         u8         uid[0x10];
4642
4643         u8         reserved_at_20[0x10];
4644         u8         op_mod[0x10];
4645
4646         u8         reserved_at_40[0x8];
4647         u8         qpn[0x18];
4648
4649         u8         reserved_at_60[0x20];
4650
4651         u8         opt_param_mask[0x20];
4652
4653         u8         reserved_at_a0[0x20];
4654
4655         struct mlx5_ifc_qpc_bits qpc;
4656
4657         u8         reserved_at_800[0x80];
4658 };
4659
4660 struct mlx5_ifc_sqd2rts_qp_out_bits {
4661         u8         status[0x8];
4662         u8         reserved_at_8[0x18];
4663
4664         u8         syndrome[0x20];
4665
4666         u8         reserved_at_40[0x40];
4667 };
4668
4669 struct mlx5_ifc_sqd2rts_qp_in_bits {
4670         u8         opcode[0x10];
4671         u8         uid[0x10];
4672
4673         u8         reserved_at_20[0x10];
4674         u8         op_mod[0x10];
4675
4676         u8         reserved_at_40[0x8];
4677         u8         qpn[0x18];
4678
4679         u8         reserved_at_60[0x20];
4680
4681         u8         opt_param_mask[0x20];
4682
4683         u8         reserved_at_a0[0x20];
4684
4685         struct mlx5_ifc_qpc_bits qpc;
4686
4687         u8         reserved_at_800[0x80];
4688 };
4689
4690 struct mlx5_ifc_set_roce_address_out_bits {
4691         u8         status[0x8];
4692         u8         reserved_at_8[0x18];
4693
4694         u8         syndrome[0x20];
4695
4696         u8         reserved_at_40[0x40];
4697 };
4698
4699 struct mlx5_ifc_set_roce_address_in_bits {
4700         u8         opcode[0x10];
4701         u8         reserved_at_10[0x10];
4702
4703         u8         reserved_at_20[0x10];
4704         u8         op_mod[0x10];
4705
4706         u8         roce_address_index[0x10];
4707         u8         reserved_at_50[0xc];
4708         u8         vhca_port_num[0x4];
4709
4710         u8         reserved_at_60[0x20];
4711
4712         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4713 };
4714
4715 struct mlx5_ifc_set_mad_demux_out_bits {
4716         u8         status[0x8];
4717         u8         reserved_at_8[0x18];
4718
4719         u8         syndrome[0x20];
4720
4721         u8         reserved_at_40[0x40];
4722 };
4723
4724 enum {
4725         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4726         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4727 };
4728
4729 struct mlx5_ifc_set_mad_demux_in_bits {
4730         u8         opcode[0x10];
4731         u8         reserved_at_10[0x10];
4732
4733         u8         reserved_at_20[0x10];
4734         u8         op_mod[0x10];
4735
4736         u8         reserved_at_40[0x20];
4737
4738         u8         reserved_at_60[0x6];
4739         u8         demux_mode[0x2];
4740         u8         reserved_at_68[0x18];
4741 };
4742
4743 struct mlx5_ifc_set_l2_table_entry_out_bits {
4744         u8         status[0x8];
4745         u8         reserved_at_8[0x18];
4746
4747         u8         syndrome[0x20];
4748
4749         u8         reserved_at_40[0x40];
4750 };
4751
4752 struct mlx5_ifc_set_l2_table_entry_in_bits {
4753         u8         opcode[0x10];
4754         u8         reserved_at_10[0x10];
4755
4756         u8         reserved_at_20[0x10];
4757         u8         op_mod[0x10];
4758
4759         u8         reserved_at_40[0x60];
4760
4761         u8         reserved_at_a0[0x8];
4762         u8         table_index[0x18];
4763
4764         u8         reserved_at_c0[0x20];
4765
4766         u8         reserved_at_e0[0x13];
4767         u8         vlan_valid[0x1];
4768         u8         vlan[0xc];
4769
4770         struct mlx5_ifc_mac_address_layout_bits mac_address;
4771
4772         u8         reserved_at_140[0xc0];
4773 };
4774
4775 struct mlx5_ifc_set_issi_out_bits {
4776         u8         status[0x8];
4777         u8         reserved_at_8[0x18];
4778
4779         u8         syndrome[0x20];
4780
4781         u8         reserved_at_40[0x40];
4782 };
4783
4784 struct mlx5_ifc_set_issi_in_bits {
4785         u8         opcode[0x10];
4786         u8         reserved_at_10[0x10];
4787
4788         u8         reserved_at_20[0x10];
4789         u8         op_mod[0x10];
4790
4791         u8         reserved_at_40[0x10];
4792         u8         current_issi[0x10];
4793
4794         u8         reserved_at_60[0x20];
4795 };
4796
4797 struct mlx5_ifc_set_hca_cap_out_bits {
4798         u8         status[0x8];
4799         u8         reserved_at_8[0x18];
4800
4801         u8         syndrome[0x20];
4802
4803         u8         reserved_at_40[0x40];
4804 };
4805
4806 struct mlx5_ifc_set_hca_cap_in_bits {
4807         u8         opcode[0x10];
4808         u8         reserved_at_10[0x10];
4809
4810         u8         reserved_at_20[0x10];
4811         u8         op_mod[0x10];
4812
4813         u8         other_function[0x1];
4814         u8         ec_vf_function[0x1];
4815         u8         reserved_at_42[0xe];
4816         u8         function_id[0x10];
4817
4818         u8         reserved_at_60[0x20];
4819
4820         union mlx5_ifc_hca_cap_union_bits capability;
4821 };
4822
4823 enum {
4824         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4825         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4826         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4827         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4828         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4829 };
4830
4831 struct mlx5_ifc_set_fte_out_bits {
4832         u8         status[0x8];
4833         u8         reserved_at_8[0x18];
4834
4835         u8         syndrome[0x20];
4836
4837         u8         reserved_at_40[0x40];
4838 };
4839
4840 struct mlx5_ifc_set_fte_in_bits {
4841         u8         opcode[0x10];
4842         u8         reserved_at_10[0x10];
4843
4844         u8         reserved_at_20[0x10];
4845         u8         op_mod[0x10];
4846
4847         u8         other_vport[0x1];
4848         u8         reserved_at_41[0xf];
4849         u8         vport_number[0x10];
4850
4851         u8         reserved_at_60[0x20];
4852
4853         u8         table_type[0x8];
4854         u8         reserved_at_88[0x18];
4855
4856         u8         reserved_at_a0[0x8];
4857         u8         table_id[0x18];
4858
4859         u8         ignore_flow_level[0x1];
4860         u8         reserved_at_c1[0x17];
4861         u8         modify_enable_mask[0x8];
4862
4863         u8         reserved_at_e0[0x20];
4864
4865         u8         flow_index[0x20];
4866
4867         u8         reserved_at_120[0xe0];
4868
4869         struct mlx5_ifc_flow_context_bits flow_context;
4870 };
4871
4872 struct mlx5_ifc_rts2rts_qp_out_bits {
4873         u8         status[0x8];
4874         u8         reserved_at_8[0x18];
4875
4876         u8         syndrome[0x20];
4877
4878         u8         reserved_at_40[0x20];
4879         u8         ece[0x20];
4880 };
4881
4882 struct mlx5_ifc_rts2rts_qp_in_bits {
4883         u8         opcode[0x10];
4884         u8         uid[0x10];
4885
4886         u8         reserved_at_20[0x10];
4887         u8         op_mod[0x10];
4888
4889         u8         reserved_at_40[0x8];
4890         u8         qpn[0x18];
4891
4892         u8         reserved_at_60[0x20];
4893
4894         u8         opt_param_mask[0x20];
4895
4896         u8         ece[0x20];
4897
4898         struct mlx5_ifc_qpc_bits qpc;
4899
4900         u8         reserved_at_800[0x80];
4901 };
4902
4903 struct mlx5_ifc_rtr2rts_qp_out_bits {
4904         u8         status[0x8];
4905         u8         reserved_at_8[0x18];
4906
4907         u8         syndrome[0x20];
4908
4909         u8         reserved_at_40[0x20];
4910         u8         ece[0x20];
4911 };
4912
4913 struct mlx5_ifc_rtr2rts_qp_in_bits {
4914         u8         opcode[0x10];
4915         u8         uid[0x10];
4916
4917         u8         reserved_at_20[0x10];
4918         u8         op_mod[0x10];
4919
4920         u8         reserved_at_40[0x8];
4921         u8         qpn[0x18];
4922
4923         u8         reserved_at_60[0x20];
4924
4925         u8         opt_param_mask[0x20];
4926
4927         u8         ece[0x20];
4928
4929         struct mlx5_ifc_qpc_bits qpc;
4930
4931         u8         reserved_at_800[0x80];
4932 };
4933
4934 struct mlx5_ifc_rst2init_qp_out_bits {
4935         u8         status[0x8];
4936         u8         reserved_at_8[0x18];
4937
4938         u8         syndrome[0x20];
4939
4940         u8         reserved_at_40[0x20];
4941         u8         ece[0x20];
4942 };
4943
4944 struct mlx5_ifc_rst2init_qp_in_bits {
4945         u8         opcode[0x10];
4946         u8         uid[0x10];
4947
4948         u8         reserved_at_20[0x10];
4949         u8         op_mod[0x10];
4950
4951         u8         reserved_at_40[0x8];
4952         u8         qpn[0x18];
4953
4954         u8         reserved_at_60[0x20];
4955
4956         u8         opt_param_mask[0x20];
4957
4958         u8         ece[0x20];
4959
4960         struct mlx5_ifc_qpc_bits qpc;
4961
4962         u8         reserved_at_800[0x80];
4963 };
4964
4965 struct mlx5_ifc_query_xrq_out_bits {
4966         u8         status[0x8];
4967         u8         reserved_at_8[0x18];
4968
4969         u8         syndrome[0x20];
4970
4971         u8         reserved_at_40[0x40];
4972
4973         struct mlx5_ifc_xrqc_bits xrq_context;
4974 };
4975
4976 struct mlx5_ifc_query_xrq_in_bits {
4977         u8         opcode[0x10];
4978         u8         reserved_at_10[0x10];
4979
4980         u8         reserved_at_20[0x10];
4981         u8         op_mod[0x10];
4982
4983         u8         reserved_at_40[0x8];
4984         u8         xrqn[0x18];
4985
4986         u8         reserved_at_60[0x20];
4987 };
4988
4989 struct mlx5_ifc_query_xrc_srq_out_bits {
4990         u8         status[0x8];
4991         u8         reserved_at_8[0x18];
4992
4993         u8         syndrome[0x20];
4994
4995         u8         reserved_at_40[0x40];
4996
4997         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4998
4999         u8         reserved_at_280[0x600];
5000
5001         u8         pas[][0x40];
5002 };
5003
5004 struct mlx5_ifc_query_xrc_srq_in_bits {
5005         u8         opcode[0x10];
5006         u8         reserved_at_10[0x10];
5007
5008         u8         reserved_at_20[0x10];
5009         u8         op_mod[0x10];
5010
5011         u8         reserved_at_40[0x8];
5012         u8         xrc_srqn[0x18];
5013
5014         u8         reserved_at_60[0x20];
5015 };
5016
5017 enum {
5018         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5019         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5020 };
5021
5022 struct mlx5_ifc_query_vport_state_out_bits {
5023         u8         status[0x8];
5024         u8         reserved_at_8[0x18];
5025
5026         u8         syndrome[0x20];
5027
5028         u8         reserved_at_40[0x20];
5029
5030         u8         reserved_at_60[0x18];
5031         u8         admin_state[0x4];
5032         u8         state[0x4];
5033 };
5034
5035 enum {
5036         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5037         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5038         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5039 };
5040
5041 struct mlx5_ifc_arm_monitor_counter_in_bits {
5042         u8         opcode[0x10];
5043         u8         uid[0x10];
5044
5045         u8         reserved_at_20[0x10];
5046         u8         op_mod[0x10];
5047
5048         u8         reserved_at_40[0x20];
5049
5050         u8         reserved_at_60[0x20];
5051 };
5052
5053 struct mlx5_ifc_arm_monitor_counter_out_bits {
5054         u8         status[0x8];
5055         u8         reserved_at_8[0x18];
5056
5057         u8         syndrome[0x20];
5058
5059         u8         reserved_at_40[0x40];
5060 };
5061
5062 enum {
5063         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5064         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5065 };
5066
5067 enum mlx5_monitor_counter_ppcnt {
5068         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5069         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5070         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5071         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5072         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5073         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5074 };
5075
5076 enum {
5077         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5078 };
5079
5080 struct mlx5_ifc_monitor_counter_output_bits {
5081         u8         reserved_at_0[0x4];
5082         u8         type[0x4];
5083         u8         reserved_at_8[0x8];
5084         u8         counter[0x10];
5085
5086         u8         counter_group_id[0x20];
5087 };
5088
5089 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5090 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5091 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5092                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5093
5094 struct mlx5_ifc_set_monitor_counter_in_bits {
5095         u8         opcode[0x10];
5096         u8         uid[0x10];
5097
5098         u8         reserved_at_20[0x10];
5099         u8         op_mod[0x10];
5100
5101         u8         reserved_at_40[0x10];
5102         u8         num_of_counters[0x10];
5103
5104         u8         reserved_at_60[0x20];
5105
5106         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5107 };
5108
5109 struct mlx5_ifc_set_monitor_counter_out_bits {
5110         u8         status[0x8];
5111         u8         reserved_at_8[0x18];
5112
5113         u8         syndrome[0x20];
5114
5115         u8         reserved_at_40[0x40];
5116 };
5117
5118 struct mlx5_ifc_query_vport_state_in_bits {
5119         u8         opcode[0x10];
5120         u8         reserved_at_10[0x10];
5121
5122         u8         reserved_at_20[0x10];
5123         u8         op_mod[0x10];
5124
5125         u8         other_vport[0x1];
5126         u8         reserved_at_41[0xf];
5127         u8         vport_number[0x10];
5128
5129         u8         reserved_at_60[0x20];
5130 };
5131
5132 struct mlx5_ifc_query_vnic_env_out_bits {
5133         u8         status[0x8];
5134         u8         reserved_at_8[0x18];
5135
5136         u8         syndrome[0x20];
5137
5138         u8         reserved_at_40[0x40];
5139
5140         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5141 };
5142
5143 enum {
5144         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5145 };
5146
5147 struct mlx5_ifc_query_vnic_env_in_bits {
5148         u8         opcode[0x10];
5149         u8         reserved_at_10[0x10];
5150
5151         u8         reserved_at_20[0x10];
5152         u8         op_mod[0x10];
5153
5154         u8         other_vport[0x1];
5155         u8         reserved_at_41[0xf];
5156         u8         vport_number[0x10];
5157
5158         u8         reserved_at_60[0x20];
5159 };
5160
5161 struct mlx5_ifc_query_vport_counter_out_bits {
5162         u8         status[0x8];
5163         u8         reserved_at_8[0x18];
5164
5165         u8         syndrome[0x20];
5166
5167         u8         reserved_at_40[0x40];
5168
5169         struct mlx5_ifc_traffic_counter_bits received_errors;
5170
5171         struct mlx5_ifc_traffic_counter_bits transmit_errors;
5172
5173         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5174
5175         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5176
5177         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5178
5179         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5180
5181         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5182
5183         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5184
5185         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5186
5187         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5188
5189         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5190
5191         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5192
5193         struct mlx5_ifc_traffic_counter_bits local_loopback;
5194
5195         u8         reserved_at_700[0x980];
5196 };
5197
5198 enum {
5199         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5200 };
5201
5202 struct mlx5_ifc_query_vport_counter_in_bits {
5203         u8         opcode[0x10];
5204         u8         reserved_at_10[0x10];
5205
5206         u8         reserved_at_20[0x10];
5207         u8         op_mod[0x10];
5208
5209         u8         other_vport[0x1];
5210         u8         reserved_at_41[0xb];
5211         u8         port_num[0x4];
5212         u8         vport_number[0x10];
5213
5214         u8         reserved_at_60[0x60];
5215
5216         u8         clear[0x1];
5217         u8         reserved_at_c1[0x1f];
5218
5219         u8         reserved_at_e0[0x20];
5220 };
5221
5222 struct mlx5_ifc_query_tis_out_bits {
5223         u8         status[0x8];
5224         u8         reserved_at_8[0x18];
5225
5226         u8         syndrome[0x20];
5227
5228         u8         reserved_at_40[0x40];
5229
5230         struct mlx5_ifc_tisc_bits tis_context;
5231 };
5232
5233 struct mlx5_ifc_query_tis_in_bits {
5234         u8         opcode[0x10];
5235         u8         reserved_at_10[0x10];
5236
5237         u8         reserved_at_20[0x10];
5238         u8         op_mod[0x10];
5239
5240         u8         reserved_at_40[0x8];
5241         u8         tisn[0x18];
5242
5243         u8         reserved_at_60[0x20];
5244 };
5245
5246 struct mlx5_ifc_query_tir_out_bits {
5247         u8         status[0x8];
5248         u8         reserved_at_8[0x18];
5249
5250         u8         syndrome[0x20];
5251
5252         u8         reserved_at_40[0xc0];
5253
5254         struct mlx5_ifc_tirc_bits tir_context;
5255 };
5256
5257 struct mlx5_ifc_query_tir_in_bits {
5258         u8         opcode[0x10];
5259         u8         reserved_at_10[0x10];
5260
5261         u8         reserved_at_20[0x10];
5262         u8         op_mod[0x10];
5263
5264         u8         reserved_at_40[0x8];
5265         u8         tirn[0x18];
5266
5267         u8         reserved_at_60[0x20];
5268 };
5269
5270 struct mlx5_ifc_query_srq_out_bits {
5271         u8         status[0x8];
5272         u8         reserved_at_8[0x18];
5273
5274         u8         syndrome[0x20];
5275
5276         u8         reserved_at_40[0x40];
5277
5278         struct mlx5_ifc_srqc_bits srq_context_entry;
5279
5280         u8         reserved_at_280[0x600];
5281
5282         u8         pas[][0x40];
5283 };
5284
5285 struct mlx5_ifc_query_srq_in_bits {
5286         u8         opcode[0x10];
5287         u8         reserved_at_10[0x10];
5288
5289         u8         reserved_at_20[0x10];
5290         u8         op_mod[0x10];
5291
5292         u8         reserved_at_40[0x8];
5293         u8         srqn[0x18];
5294
5295         u8         reserved_at_60[0x20];
5296 };
5297
5298 struct mlx5_ifc_query_sq_out_bits {
5299         u8         status[0x8];
5300         u8         reserved_at_8[0x18];
5301
5302         u8         syndrome[0x20];
5303
5304         u8         reserved_at_40[0xc0];
5305
5306         struct mlx5_ifc_sqc_bits sq_context;
5307 };
5308
5309 struct mlx5_ifc_query_sq_in_bits {
5310         u8         opcode[0x10];
5311         u8         reserved_at_10[0x10];
5312
5313         u8         reserved_at_20[0x10];
5314         u8         op_mod[0x10];
5315
5316         u8         reserved_at_40[0x8];
5317         u8         sqn[0x18];
5318
5319         u8         reserved_at_60[0x20];
5320 };
5321
5322 struct mlx5_ifc_query_special_contexts_out_bits {
5323         u8         status[0x8];
5324         u8         reserved_at_8[0x18];
5325
5326         u8         syndrome[0x20];
5327
5328         u8         dump_fill_mkey[0x20];
5329
5330         u8         resd_lkey[0x20];
5331
5332         u8         null_mkey[0x20];
5333
5334         u8         terminate_scatter_list_mkey[0x20];
5335
5336         u8         repeated_mkey[0x20];
5337
5338         u8         reserved_at_a0[0x20];
5339 };
5340
5341 struct mlx5_ifc_query_special_contexts_in_bits {
5342         u8         opcode[0x10];
5343         u8         reserved_at_10[0x10];
5344
5345         u8         reserved_at_20[0x10];
5346         u8         op_mod[0x10];
5347
5348         u8         reserved_at_40[0x40];
5349 };
5350
5351 struct mlx5_ifc_query_scheduling_element_out_bits {
5352         u8         opcode[0x10];
5353         u8         reserved_at_10[0x10];
5354
5355         u8         reserved_at_20[0x10];
5356         u8         op_mod[0x10];
5357
5358         u8         reserved_at_40[0xc0];
5359
5360         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5361
5362         u8         reserved_at_300[0x100];
5363 };
5364
5365 enum {
5366         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5367         SCHEDULING_HIERARCHY_NIC = 0x3,
5368 };
5369
5370 struct mlx5_ifc_query_scheduling_element_in_bits {
5371         u8         opcode[0x10];
5372         u8         reserved_at_10[0x10];
5373
5374         u8         reserved_at_20[0x10];
5375         u8         op_mod[0x10];
5376
5377         u8         scheduling_hierarchy[0x8];
5378         u8         reserved_at_48[0x18];
5379
5380         u8         scheduling_element_id[0x20];
5381
5382         u8         reserved_at_80[0x180];
5383 };
5384
5385 struct mlx5_ifc_query_rqt_out_bits {
5386         u8         status[0x8];
5387         u8         reserved_at_8[0x18];
5388
5389         u8         syndrome[0x20];
5390
5391         u8         reserved_at_40[0xc0];
5392
5393         struct mlx5_ifc_rqtc_bits rqt_context;
5394 };
5395
5396 struct mlx5_ifc_query_rqt_in_bits {
5397         u8         opcode[0x10];
5398         u8         reserved_at_10[0x10];
5399
5400         u8         reserved_at_20[0x10];
5401         u8         op_mod[0x10];
5402
5403         u8         reserved_at_40[0x8];
5404         u8         rqtn[0x18];
5405
5406         u8         reserved_at_60[0x20];
5407 };
5408
5409 struct mlx5_ifc_query_rq_out_bits {
5410         u8         status[0x8];
5411         u8         reserved_at_8[0x18];
5412
5413         u8         syndrome[0x20];
5414
5415         u8         reserved_at_40[0xc0];
5416
5417         struct mlx5_ifc_rqc_bits rq_context;
5418 };
5419
5420 struct mlx5_ifc_query_rq_in_bits {
5421         u8         opcode[0x10];
5422         u8         reserved_at_10[0x10];
5423
5424         u8         reserved_at_20[0x10];
5425         u8         op_mod[0x10];
5426
5427         u8         reserved_at_40[0x8];
5428         u8         rqn[0x18];
5429
5430         u8         reserved_at_60[0x20];
5431 };
5432
5433 struct mlx5_ifc_query_roce_address_out_bits {
5434         u8         status[0x8];
5435         u8         reserved_at_8[0x18];
5436
5437         u8         syndrome[0x20];
5438
5439         u8         reserved_at_40[0x40];
5440
5441         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5442 };
5443
5444 struct mlx5_ifc_query_roce_address_in_bits {
5445         u8         opcode[0x10];
5446         u8         reserved_at_10[0x10];
5447
5448         u8         reserved_at_20[0x10];
5449         u8         op_mod[0x10];
5450
5451         u8         roce_address_index[0x10];
5452         u8         reserved_at_50[0xc];
5453         u8         vhca_port_num[0x4];
5454
5455         u8         reserved_at_60[0x20];
5456 };
5457
5458 struct mlx5_ifc_query_rmp_out_bits {
5459         u8         status[0x8];
5460         u8         reserved_at_8[0x18];
5461
5462         u8         syndrome[0x20];
5463
5464         u8         reserved_at_40[0xc0];
5465
5466         struct mlx5_ifc_rmpc_bits rmp_context;
5467 };
5468
5469 struct mlx5_ifc_query_rmp_in_bits {
5470         u8         opcode[0x10];
5471         u8         reserved_at_10[0x10];
5472
5473         u8         reserved_at_20[0x10];
5474         u8         op_mod[0x10];
5475
5476         u8         reserved_at_40[0x8];
5477         u8         rmpn[0x18];
5478
5479         u8         reserved_at_60[0x20];
5480 };
5481
5482 struct mlx5_ifc_cqe_error_syndrome_bits {
5483         u8         hw_error_syndrome[0x8];
5484         u8         hw_syndrome_type[0x4];
5485         u8         reserved_at_c[0x4];
5486         u8         vendor_error_syndrome[0x8];
5487         u8         syndrome[0x8];
5488 };
5489
5490 struct mlx5_ifc_qp_context_extension_bits {
5491         u8         reserved_at_0[0x60];
5492
5493         struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5494
5495         u8         reserved_at_80[0x580];
5496 };
5497
5498 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5499         struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5500
5501         u8         pas[0][0x40];
5502 };
5503
5504 struct mlx5_ifc_qp_pas_list_in_bits {
5505         struct mlx5_ifc_cmd_pas_bits pas[0];
5506 };
5507
5508 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5509         struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5510         struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5511 };
5512
5513 struct mlx5_ifc_query_qp_out_bits {
5514         u8         status[0x8];
5515         u8         reserved_at_8[0x18];
5516
5517         u8         syndrome[0x20];
5518
5519         u8         reserved_at_40[0x40];
5520
5521         u8         opt_param_mask[0x20];
5522
5523         u8         ece[0x20];
5524
5525         struct mlx5_ifc_qpc_bits qpc;
5526
5527         u8         reserved_at_800[0x80];
5528
5529         union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5530 };
5531
5532 struct mlx5_ifc_query_qp_in_bits {
5533         u8         opcode[0x10];
5534         u8         reserved_at_10[0x10];
5535
5536         u8         reserved_at_20[0x10];
5537         u8         op_mod[0x10];
5538
5539         u8         qpc_ext[0x1];
5540         u8         reserved_at_41[0x7];
5541         u8         qpn[0x18];
5542
5543         u8         reserved_at_60[0x20];
5544 };
5545
5546 struct mlx5_ifc_query_q_counter_out_bits {
5547         u8         status[0x8];
5548         u8         reserved_at_8[0x18];
5549
5550         u8         syndrome[0x20];
5551
5552         u8         reserved_at_40[0x40];
5553
5554         u8         rx_write_requests[0x20];
5555
5556         u8         reserved_at_a0[0x20];
5557
5558         u8         rx_read_requests[0x20];
5559
5560         u8         reserved_at_e0[0x20];
5561
5562         u8         rx_atomic_requests[0x20];
5563
5564         u8         reserved_at_120[0x20];
5565
5566         u8         rx_dct_connect[0x20];
5567
5568         u8         reserved_at_160[0x20];
5569
5570         u8         out_of_buffer[0x20];
5571
5572         u8         reserved_at_1a0[0x20];
5573
5574         u8         out_of_sequence[0x20];
5575
5576         u8         reserved_at_1e0[0x20];
5577
5578         u8         duplicate_request[0x20];
5579
5580         u8         reserved_at_220[0x20];
5581
5582         u8         rnr_nak_retry_err[0x20];
5583
5584         u8         reserved_at_260[0x20];
5585
5586         u8         packet_seq_err[0x20];
5587
5588         u8         reserved_at_2a0[0x20];
5589
5590         u8         implied_nak_seq_err[0x20];
5591
5592         u8         reserved_at_2e0[0x20];
5593
5594         u8         local_ack_timeout_err[0x20];
5595
5596         u8         reserved_at_320[0xa0];
5597
5598         u8         resp_local_length_error[0x20];
5599
5600         u8         req_local_length_error[0x20];
5601
5602         u8         resp_local_qp_error[0x20];
5603
5604         u8         local_operation_error[0x20];
5605
5606         u8         resp_local_protection[0x20];
5607
5608         u8         req_local_protection[0x20];
5609
5610         u8         resp_cqe_error[0x20];
5611
5612         u8         req_cqe_error[0x20];
5613
5614         u8         req_mw_binding[0x20];
5615
5616         u8         req_bad_response[0x20];
5617
5618         u8         req_remote_invalid_request[0x20];
5619
5620         u8         resp_remote_invalid_request[0x20];
5621
5622         u8         req_remote_access_errors[0x20];
5623
5624         u8         resp_remote_access_errors[0x20];
5625
5626         u8         req_remote_operation_errors[0x20];
5627
5628         u8         req_transport_retries_exceeded[0x20];
5629
5630         u8         cq_overflow[0x20];
5631
5632         u8         resp_cqe_flush_error[0x20];
5633
5634         u8         req_cqe_flush_error[0x20];
5635
5636         u8         reserved_at_620[0x20];
5637
5638         u8         roce_adp_retrans[0x20];
5639
5640         u8         roce_adp_retrans_to[0x20];
5641
5642         u8         roce_slow_restart[0x20];
5643
5644         u8         roce_slow_restart_cnps[0x20];
5645
5646         u8         roce_slow_restart_trans[0x20];
5647
5648         u8         reserved_at_6e0[0x120];
5649 };
5650
5651 struct mlx5_ifc_query_q_counter_in_bits {
5652         u8         opcode[0x10];
5653         u8         reserved_at_10[0x10];
5654
5655         u8         reserved_at_20[0x10];
5656         u8         op_mod[0x10];
5657
5658         u8         other_vport[0x1];
5659         u8         reserved_at_41[0xf];
5660         u8         vport_number[0x10];
5661
5662         u8         reserved_at_60[0x60];
5663
5664         u8         clear[0x1];
5665         u8         aggregate[0x1];
5666         u8         reserved_at_c2[0x1e];
5667
5668         u8         reserved_at_e0[0x18];
5669         u8         counter_set_id[0x8];
5670 };
5671
5672 struct mlx5_ifc_query_pages_out_bits {
5673         u8         status[0x8];
5674         u8         reserved_at_8[0x18];
5675
5676         u8         syndrome[0x20];
5677
5678         u8         embedded_cpu_function[0x1];
5679         u8         reserved_at_41[0xf];
5680         u8         function_id[0x10];
5681
5682         u8         num_pages[0x20];
5683 };
5684
5685 enum {
5686         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5687         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5688         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5689 };
5690
5691 struct mlx5_ifc_query_pages_in_bits {
5692         u8         opcode[0x10];
5693         u8         reserved_at_10[0x10];
5694
5695         u8         reserved_at_20[0x10];
5696         u8         op_mod[0x10];
5697
5698         u8         embedded_cpu_function[0x1];
5699         u8         reserved_at_41[0xf];
5700         u8         function_id[0x10];
5701
5702         u8         reserved_at_60[0x20];
5703 };
5704
5705 struct mlx5_ifc_query_nic_vport_context_out_bits {
5706         u8         status[0x8];
5707         u8         reserved_at_8[0x18];
5708
5709         u8         syndrome[0x20];
5710
5711         u8         reserved_at_40[0x40];
5712
5713         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5714 };
5715
5716 struct mlx5_ifc_query_nic_vport_context_in_bits {
5717         u8         opcode[0x10];
5718         u8         reserved_at_10[0x10];
5719
5720         u8         reserved_at_20[0x10];
5721         u8         op_mod[0x10];
5722
5723         u8         other_vport[0x1];
5724         u8         reserved_at_41[0xf];
5725         u8         vport_number[0x10];
5726
5727         u8         reserved_at_60[0x5];
5728         u8         allowed_list_type[0x3];
5729         u8         reserved_at_68[0x18];
5730 };
5731
5732 struct mlx5_ifc_query_mkey_out_bits {
5733         u8         status[0x8];
5734         u8         reserved_at_8[0x18];
5735
5736         u8         syndrome[0x20];
5737
5738         u8         reserved_at_40[0x40];
5739
5740         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5741
5742         u8         reserved_at_280[0x600];
5743
5744         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5745
5746         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5747 };
5748
5749 struct mlx5_ifc_query_mkey_in_bits {
5750         u8         opcode[0x10];
5751         u8         reserved_at_10[0x10];
5752
5753         u8         reserved_at_20[0x10];
5754         u8         op_mod[0x10];
5755
5756         u8         reserved_at_40[0x8];
5757         u8         mkey_index[0x18];
5758
5759         u8         pg_access[0x1];
5760         u8         reserved_at_61[0x1f];
5761 };
5762
5763 struct mlx5_ifc_query_mad_demux_out_bits {
5764         u8         status[0x8];
5765         u8         reserved_at_8[0x18];
5766
5767         u8         syndrome[0x20];
5768
5769         u8         reserved_at_40[0x40];
5770
5771         u8         mad_dumux_parameters_block[0x20];
5772 };
5773
5774 struct mlx5_ifc_query_mad_demux_in_bits {
5775         u8         opcode[0x10];
5776         u8         reserved_at_10[0x10];
5777
5778         u8         reserved_at_20[0x10];
5779         u8         op_mod[0x10];
5780
5781         u8         reserved_at_40[0x40];
5782 };
5783
5784 struct mlx5_ifc_query_l2_table_entry_out_bits {
5785         u8         status[0x8];
5786         u8         reserved_at_8[0x18];
5787
5788         u8         syndrome[0x20];
5789
5790         u8         reserved_at_40[0xa0];
5791
5792         u8         reserved_at_e0[0x13];
5793         u8         vlan_valid[0x1];
5794         u8         vlan[0xc];
5795
5796         struct mlx5_ifc_mac_address_layout_bits mac_address;
5797
5798         u8         reserved_at_140[0xc0];
5799 };
5800
5801 struct mlx5_ifc_query_l2_table_entry_in_bits {
5802         u8         opcode[0x10];
5803         u8         reserved_at_10[0x10];
5804
5805         u8         reserved_at_20[0x10];
5806         u8         op_mod[0x10];
5807
5808         u8         reserved_at_40[0x60];
5809
5810         u8         reserved_at_a0[0x8];
5811         u8         table_index[0x18];
5812
5813         u8         reserved_at_c0[0x140];
5814 };
5815
5816 struct mlx5_ifc_query_issi_out_bits {
5817         u8         status[0x8];
5818         u8         reserved_at_8[0x18];
5819
5820         u8         syndrome[0x20];
5821
5822         u8         reserved_at_40[0x10];
5823         u8         current_issi[0x10];
5824
5825         u8         reserved_at_60[0xa0];
5826
5827         u8         reserved_at_100[76][0x8];
5828         u8         supported_issi_dw0[0x20];
5829 };
5830
5831 struct mlx5_ifc_query_issi_in_bits {
5832         u8         opcode[0x10];
5833         u8         reserved_at_10[0x10];
5834
5835         u8         reserved_at_20[0x10];
5836         u8         op_mod[0x10];
5837
5838         u8         reserved_at_40[0x40];
5839 };
5840
5841 struct mlx5_ifc_set_driver_version_out_bits {
5842         u8         status[0x8];
5843         u8         reserved_0[0x18];
5844
5845         u8         syndrome[0x20];
5846         u8         reserved_1[0x40];
5847 };
5848
5849 struct mlx5_ifc_set_driver_version_in_bits {
5850         u8         opcode[0x10];
5851         u8         reserved_0[0x10];
5852
5853         u8         reserved_1[0x10];
5854         u8         op_mod[0x10];
5855
5856         u8         reserved_2[0x40];
5857         u8         driver_version[64][0x8];
5858 };
5859
5860 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5861         u8         status[0x8];
5862         u8         reserved_at_8[0x18];
5863
5864         u8         syndrome[0x20];
5865
5866         u8         reserved_at_40[0x40];
5867
5868         struct mlx5_ifc_pkey_bits pkey[];
5869 };
5870
5871 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5872         u8         opcode[0x10];
5873         u8         reserved_at_10[0x10];
5874
5875         u8         reserved_at_20[0x10];
5876         u8         op_mod[0x10];
5877
5878         u8         other_vport[0x1];
5879         u8         reserved_at_41[0xb];
5880         u8         port_num[0x4];
5881         u8         vport_number[0x10];
5882
5883         u8         reserved_at_60[0x10];
5884         u8         pkey_index[0x10];
5885 };
5886
5887 enum {
5888         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5889         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5890         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5891 };
5892
5893 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5894         u8         status[0x8];
5895         u8         reserved_at_8[0x18];
5896
5897         u8         syndrome[0x20];
5898
5899         u8         reserved_at_40[0x20];
5900
5901         u8         gids_num[0x10];
5902         u8         reserved_at_70[0x10];
5903
5904         struct mlx5_ifc_array128_auto_bits gid[];
5905 };
5906
5907 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5908         u8         opcode[0x10];
5909         u8         reserved_at_10[0x10];
5910
5911         u8         reserved_at_20[0x10];
5912         u8         op_mod[0x10];
5913
5914         u8         other_vport[0x1];
5915         u8         reserved_at_41[0xb];
5916         u8         port_num[0x4];
5917         u8         vport_number[0x10];
5918
5919         u8         reserved_at_60[0x10];
5920         u8         gid_index[0x10];
5921 };
5922
5923 struct mlx5_ifc_query_hca_vport_context_out_bits {
5924         u8         status[0x8];
5925         u8         reserved_at_8[0x18];
5926
5927         u8         syndrome[0x20];
5928
5929         u8         reserved_at_40[0x40];
5930
5931         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5932 };
5933
5934 struct mlx5_ifc_query_hca_vport_context_in_bits {
5935         u8         opcode[0x10];
5936         u8         reserved_at_10[0x10];
5937
5938         u8         reserved_at_20[0x10];
5939         u8         op_mod[0x10];
5940
5941         u8         other_vport[0x1];
5942         u8         reserved_at_41[0xb];
5943         u8         port_num[0x4];
5944         u8         vport_number[0x10];
5945
5946         u8         reserved_at_60[0x20];
5947 };
5948
5949 struct mlx5_ifc_query_hca_cap_out_bits {
5950         u8         status[0x8];
5951         u8         reserved_at_8[0x18];
5952
5953         u8         syndrome[0x20];
5954
5955         u8         reserved_at_40[0x40];
5956
5957         union mlx5_ifc_hca_cap_union_bits capability;
5958 };
5959
5960 struct mlx5_ifc_query_hca_cap_in_bits {
5961         u8         opcode[0x10];
5962         u8         reserved_at_10[0x10];
5963
5964         u8         reserved_at_20[0x10];
5965         u8         op_mod[0x10];
5966
5967         u8         other_function[0x1];
5968         u8         ec_vf_function[0x1];
5969         u8         reserved_at_42[0xe];
5970         u8         function_id[0x10];
5971
5972         u8         reserved_at_60[0x20];
5973 };
5974
5975 struct mlx5_ifc_other_hca_cap_bits {
5976         u8         roce[0x1];
5977         u8         reserved_at_1[0x27f];
5978 };
5979
5980 struct mlx5_ifc_query_other_hca_cap_out_bits {
5981         u8         status[0x8];
5982         u8         reserved_at_8[0x18];
5983
5984         u8         syndrome[0x20];
5985
5986         u8         reserved_at_40[0x40];
5987
5988         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5989 };
5990
5991 struct mlx5_ifc_query_other_hca_cap_in_bits {
5992         u8         opcode[0x10];
5993         u8         reserved_at_10[0x10];
5994
5995         u8         reserved_at_20[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         reserved_at_40[0x10];
5999         u8         function_id[0x10];
6000
6001         u8         reserved_at_60[0x20];
6002 };
6003
6004 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x40];
6011 };
6012
6013 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6014         u8         opcode[0x10];
6015         u8         reserved_at_10[0x10];
6016
6017         u8         reserved_at_20[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_at_40[0x10];
6021         u8         function_id[0x10];
6022         u8         field_select[0x20];
6023
6024         struct     mlx5_ifc_other_hca_cap_bits other_capability;
6025 };
6026
6027 struct mlx5_ifc_flow_table_context_bits {
6028         u8         reformat_en[0x1];
6029         u8         decap_en[0x1];
6030         u8         sw_owner[0x1];
6031         u8         termination_table[0x1];
6032         u8         table_miss_action[0x4];
6033         u8         level[0x8];
6034         u8         reserved_at_10[0x8];
6035         u8         log_size[0x8];
6036
6037         u8         reserved_at_20[0x8];
6038         u8         table_miss_id[0x18];
6039
6040         u8         reserved_at_40[0x8];
6041         u8         lag_master_next_table_id[0x18];
6042
6043         u8         reserved_at_60[0x60];
6044
6045         u8         sw_owner_icm_root_1[0x40];
6046
6047         u8         sw_owner_icm_root_0[0x40];
6048
6049 };
6050
6051 struct mlx5_ifc_query_flow_table_out_bits {
6052         u8         status[0x8];
6053         u8         reserved_at_8[0x18];
6054
6055         u8         syndrome[0x20];
6056
6057         u8         reserved_at_40[0x80];
6058
6059         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6060 };
6061
6062 struct mlx5_ifc_query_flow_table_in_bits {
6063         u8         opcode[0x10];
6064         u8         reserved_at_10[0x10];
6065
6066         u8         reserved_at_20[0x10];
6067         u8         op_mod[0x10];
6068
6069         u8         reserved_at_40[0x40];
6070
6071         u8         table_type[0x8];
6072         u8         reserved_at_88[0x18];
6073
6074         u8         reserved_at_a0[0x8];
6075         u8         table_id[0x18];
6076
6077         u8         reserved_at_c0[0x140];
6078 };
6079
6080 struct mlx5_ifc_query_fte_out_bits {
6081         u8         status[0x8];
6082         u8         reserved_at_8[0x18];
6083
6084         u8         syndrome[0x20];
6085
6086         u8         reserved_at_40[0x1c0];
6087
6088         struct mlx5_ifc_flow_context_bits flow_context;
6089 };
6090
6091 struct mlx5_ifc_query_fte_in_bits {
6092         u8         opcode[0x10];
6093         u8         reserved_at_10[0x10];
6094
6095         u8         reserved_at_20[0x10];
6096         u8         op_mod[0x10];
6097
6098         u8         reserved_at_40[0x40];
6099
6100         u8         table_type[0x8];
6101         u8         reserved_at_88[0x18];
6102
6103         u8         reserved_at_a0[0x8];
6104         u8         table_id[0x18];
6105
6106         u8         reserved_at_c0[0x40];
6107
6108         u8         flow_index[0x20];
6109
6110         u8         reserved_at_120[0xe0];
6111 };
6112
6113 struct mlx5_ifc_match_definer_format_0_bits {
6114         u8         reserved_at_0[0x100];
6115
6116         u8         metadata_reg_c_0[0x20];
6117
6118         u8         metadata_reg_c_1[0x20];
6119
6120         u8         outer_dmac_47_16[0x20];
6121
6122         u8         outer_dmac_15_0[0x10];
6123         u8         outer_ethertype[0x10];
6124
6125         u8         reserved_at_180[0x1];
6126         u8         sx_sniffer[0x1];
6127         u8         functional_lb[0x1];
6128         u8         outer_ip_frag[0x1];
6129         u8         outer_qp_type[0x2];
6130         u8         outer_encap_type[0x2];
6131         u8         port_number[0x2];
6132         u8         outer_l3_type[0x2];
6133         u8         outer_l4_type[0x2];
6134         u8         outer_first_vlan_type[0x2];
6135         u8         outer_first_vlan_prio[0x3];
6136         u8         outer_first_vlan_cfi[0x1];
6137         u8         outer_first_vlan_vid[0xc];
6138
6139         u8         outer_l4_type_ext[0x4];
6140         u8         reserved_at_1a4[0x2];
6141         u8         outer_ipsec_layer[0x2];
6142         u8         outer_l2_type[0x2];
6143         u8         force_lb[0x1];
6144         u8         outer_l2_ok[0x1];
6145         u8         outer_l3_ok[0x1];
6146         u8         outer_l4_ok[0x1];
6147         u8         outer_second_vlan_type[0x2];
6148         u8         outer_second_vlan_prio[0x3];
6149         u8         outer_second_vlan_cfi[0x1];
6150         u8         outer_second_vlan_vid[0xc];
6151
6152         u8         outer_smac_47_16[0x20];
6153
6154         u8         outer_smac_15_0[0x10];
6155         u8         inner_ipv4_checksum_ok[0x1];
6156         u8         inner_l4_checksum_ok[0x1];
6157         u8         outer_ipv4_checksum_ok[0x1];
6158         u8         outer_l4_checksum_ok[0x1];
6159         u8         inner_l3_ok[0x1];
6160         u8         inner_l4_ok[0x1];
6161         u8         outer_l3_ok_duplicate[0x1];
6162         u8         outer_l4_ok_duplicate[0x1];
6163         u8         outer_tcp_cwr[0x1];
6164         u8         outer_tcp_ece[0x1];
6165         u8         outer_tcp_urg[0x1];
6166         u8         outer_tcp_ack[0x1];
6167         u8         outer_tcp_psh[0x1];
6168         u8         outer_tcp_rst[0x1];
6169         u8         outer_tcp_syn[0x1];
6170         u8         outer_tcp_fin[0x1];
6171 };
6172
6173 struct mlx5_ifc_match_definer_format_22_bits {
6174         u8         reserved_at_0[0x100];
6175
6176         u8         outer_ip_src_addr[0x20];
6177
6178         u8         outer_ip_dest_addr[0x20];
6179
6180         u8         outer_l4_sport[0x10];
6181         u8         outer_l4_dport[0x10];
6182
6183         u8         reserved_at_160[0x1];
6184         u8         sx_sniffer[0x1];
6185         u8         functional_lb[0x1];
6186         u8         outer_ip_frag[0x1];
6187         u8         outer_qp_type[0x2];
6188         u8         outer_encap_type[0x2];
6189         u8         port_number[0x2];
6190         u8         outer_l3_type[0x2];
6191         u8         outer_l4_type[0x2];
6192         u8         outer_first_vlan_type[0x2];
6193         u8         outer_first_vlan_prio[0x3];
6194         u8         outer_first_vlan_cfi[0x1];
6195         u8         outer_first_vlan_vid[0xc];
6196
6197         u8         metadata_reg_c_0[0x20];
6198
6199         u8         outer_dmac_47_16[0x20];
6200
6201         u8         outer_smac_47_16[0x20];
6202
6203         u8         outer_smac_15_0[0x10];
6204         u8         outer_dmac_15_0[0x10];
6205 };
6206
6207 struct mlx5_ifc_match_definer_format_23_bits {
6208         u8         reserved_at_0[0x100];
6209
6210         u8         inner_ip_src_addr[0x20];
6211
6212         u8         inner_ip_dest_addr[0x20];
6213
6214         u8         inner_l4_sport[0x10];
6215         u8         inner_l4_dport[0x10];
6216
6217         u8         reserved_at_160[0x1];
6218         u8         sx_sniffer[0x1];
6219         u8         functional_lb[0x1];
6220         u8         inner_ip_frag[0x1];
6221         u8         inner_qp_type[0x2];
6222         u8         inner_encap_type[0x2];
6223         u8         port_number[0x2];
6224         u8         inner_l3_type[0x2];
6225         u8         inner_l4_type[0x2];
6226         u8         inner_first_vlan_type[0x2];
6227         u8         inner_first_vlan_prio[0x3];
6228         u8         inner_first_vlan_cfi[0x1];
6229         u8         inner_first_vlan_vid[0xc];
6230
6231         u8         tunnel_header_0[0x20];
6232
6233         u8         inner_dmac_47_16[0x20];
6234
6235         u8         inner_smac_47_16[0x20];
6236
6237         u8         inner_smac_15_0[0x10];
6238         u8         inner_dmac_15_0[0x10];
6239 };
6240
6241 struct mlx5_ifc_match_definer_format_29_bits {
6242         u8         reserved_at_0[0xc0];
6243
6244         u8         outer_ip_dest_addr[0x80];
6245
6246         u8         outer_ip_src_addr[0x80];
6247
6248         u8         outer_l4_sport[0x10];
6249         u8         outer_l4_dport[0x10];
6250
6251         u8         reserved_at_1e0[0x20];
6252 };
6253
6254 struct mlx5_ifc_match_definer_format_30_bits {
6255         u8         reserved_at_0[0xa0];
6256
6257         u8         outer_ip_dest_addr[0x80];
6258
6259         u8         outer_ip_src_addr[0x80];
6260
6261         u8         outer_dmac_47_16[0x20];
6262
6263         u8         outer_smac_47_16[0x20];
6264
6265         u8         outer_smac_15_0[0x10];
6266         u8         outer_dmac_15_0[0x10];
6267 };
6268
6269 struct mlx5_ifc_match_definer_format_31_bits {
6270         u8         reserved_at_0[0xc0];
6271
6272         u8         inner_ip_dest_addr[0x80];
6273
6274         u8         inner_ip_src_addr[0x80];
6275
6276         u8         inner_l4_sport[0x10];
6277         u8         inner_l4_dport[0x10];
6278
6279         u8         reserved_at_1e0[0x20];
6280 };
6281
6282 struct mlx5_ifc_match_definer_format_32_bits {
6283         u8         reserved_at_0[0xa0];
6284
6285         u8         inner_ip_dest_addr[0x80];
6286
6287         u8         inner_ip_src_addr[0x80];
6288
6289         u8         inner_dmac_47_16[0x20];
6290
6291         u8         inner_smac_47_16[0x20];
6292
6293         u8         inner_smac_15_0[0x10];
6294         u8         inner_dmac_15_0[0x10];
6295 };
6296
6297 enum {
6298         MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6299 };
6300
6301 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6302 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6303 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6304 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6305
6306 struct mlx5_ifc_match_definer_match_mask_bits {
6307         u8         reserved_at_1c0[5][0x20];
6308         u8         match_dw_8[0x20];
6309         u8         match_dw_7[0x20];
6310         u8         match_dw_6[0x20];
6311         u8         match_dw_5[0x20];
6312         u8         match_dw_4[0x20];
6313         u8         match_dw_3[0x20];
6314         u8         match_dw_2[0x20];
6315         u8         match_dw_1[0x20];
6316         u8         match_dw_0[0x20];
6317
6318         u8         match_byte_7[0x8];
6319         u8         match_byte_6[0x8];
6320         u8         match_byte_5[0x8];
6321         u8         match_byte_4[0x8];
6322
6323         u8         match_byte_3[0x8];
6324         u8         match_byte_2[0x8];
6325         u8         match_byte_1[0x8];
6326         u8         match_byte_0[0x8];
6327 };
6328
6329 struct mlx5_ifc_match_definer_bits {
6330         u8         modify_field_select[0x40];
6331
6332         u8         reserved_at_40[0x40];
6333
6334         u8         reserved_at_80[0x10];
6335         u8         format_id[0x10];
6336
6337         u8         reserved_at_a0[0x60];
6338
6339         u8         format_select_dw3[0x8];
6340         u8         format_select_dw2[0x8];
6341         u8         format_select_dw1[0x8];
6342         u8         format_select_dw0[0x8];
6343
6344         u8         format_select_dw7[0x8];
6345         u8         format_select_dw6[0x8];
6346         u8         format_select_dw5[0x8];
6347         u8         format_select_dw4[0x8];
6348
6349         u8         reserved_at_100[0x18];
6350         u8         format_select_dw8[0x8];
6351
6352         u8         reserved_at_120[0x20];
6353
6354         u8         format_select_byte3[0x8];
6355         u8         format_select_byte2[0x8];
6356         u8         format_select_byte1[0x8];
6357         u8         format_select_byte0[0x8];
6358
6359         u8         format_select_byte7[0x8];
6360         u8         format_select_byte6[0x8];
6361         u8         format_select_byte5[0x8];
6362         u8         format_select_byte4[0x8];
6363
6364         u8         reserved_at_180[0x40];
6365
6366         union {
6367                 struct {
6368                         u8         match_mask[16][0x20];
6369                 };
6370                 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6371         };
6372 };
6373
6374 struct mlx5_ifc_general_obj_create_param_bits {
6375         u8         alias_object[0x1];
6376         u8         reserved_at_1[0x2];
6377         u8         log_obj_range[0x5];
6378         u8         reserved_at_8[0x18];
6379 };
6380
6381 struct mlx5_ifc_general_obj_query_param_bits {
6382         u8         alias_object[0x1];
6383         u8         obj_offset[0x1f];
6384 };
6385
6386 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6387         u8         opcode[0x10];
6388         u8         uid[0x10];
6389
6390         u8         vhca_tunnel_id[0x10];
6391         u8         obj_type[0x10];
6392
6393         u8         obj_id[0x20];
6394
6395         union {
6396                 struct mlx5_ifc_general_obj_create_param_bits create;
6397                 struct mlx5_ifc_general_obj_query_param_bits query;
6398         } op_param;
6399 };
6400
6401 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6402         u8         status[0x8];
6403         u8         reserved_at_8[0x18];
6404
6405         u8         syndrome[0x20];
6406
6407         u8         obj_id[0x20];
6408
6409         u8         reserved_at_60[0x20];
6410 };
6411
6412 struct mlx5_ifc_modify_header_arg_bits {
6413         u8         reserved_at_0[0x80];
6414
6415         u8         reserved_at_80[0x8];
6416         u8         access_pd[0x18];
6417 };
6418
6419 struct mlx5_ifc_create_modify_header_arg_in_bits {
6420         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6421         struct mlx5_ifc_modify_header_arg_bits arg;
6422 };
6423
6424 struct mlx5_ifc_create_match_definer_in_bits {
6425         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6426
6427         struct mlx5_ifc_match_definer_bits obj_context;
6428 };
6429
6430 struct mlx5_ifc_create_match_definer_out_bits {
6431         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6432 };
6433
6434 enum {
6435         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6436         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6437         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6438         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6439         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6440         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6441         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6442 };
6443
6444 struct mlx5_ifc_query_flow_group_out_bits {
6445         u8         status[0x8];
6446         u8         reserved_at_8[0x18];
6447
6448         u8         syndrome[0x20];
6449
6450         u8         reserved_at_40[0xa0];
6451
6452         u8         start_flow_index[0x20];
6453
6454         u8         reserved_at_100[0x20];
6455
6456         u8         end_flow_index[0x20];
6457
6458         u8         reserved_at_140[0xa0];
6459
6460         u8         reserved_at_1e0[0x18];
6461         u8         match_criteria_enable[0x8];
6462
6463         struct mlx5_ifc_fte_match_param_bits match_criteria;
6464
6465         u8         reserved_at_1200[0xe00];
6466 };
6467
6468 struct mlx5_ifc_query_flow_group_in_bits {
6469         u8         opcode[0x10];
6470         u8         reserved_at_10[0x10];
6471
6472         u8         reserved_at_20[0x10];
6473         u8         op_mod[0x10];
6474
6475         u8         reserved_at_40[0x40];
6476
6477         u8         table_type[0x8];
6478         u8         reserved_at_88[0x18];
6479
6480         u8         reserved_at_a0[0x8];
6481         u8         table_id[0x18];
6482
6483         u8         group_id[0x20];
6484
6485         u8         reserved_at_e0[0x120];
6486 };
6487
6488 struct mlx5_ifc_query_flow_counter_out_bits {
6489         u8         status[0x8];
6490         u8         reserved_at_8[0x18];
6491
6492         u8         syndrome[0x20];
6493
6494         u8         reserved_at_40[0x40];
6495
6496         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6497 };
6498
6499 struct mlx5_ifc_query_flow_counter_in_bits {
6500         u8         opcode[0x10];
6501         u8         reserved_at_10[0x10];
6502
6503         u8         reserved_at_20[0x10];
6504         u8         op_mod[0x10];
6505
6506         u8         reserved_at_40[0x80];
6507
6508         u8         clear[0x1];
6509         u8         reserved_at_c1[0xf];
6510         u8         num_of_counters[0x10];
6511
6512         u8         flow_counter_id[0x20];
6513 };
6514
6515 struct mlx5_ifc_query_esw_vport_context_out_bits {
6516         u8         status[0x8];
6517         u8         reserved_at_8[0x18];
6518
6519         u8         syndrome[0x20];
6520
6521         u8         reserved_at_40[0x40];
6522
6523         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6524 };
6525
6526 struct mlx5_ifc_query_esw_vport_context_in_bits {
6527         u8         opcode[0x10];
6528         u8         reserved_at_10[0x10];
6529
6530         u8         reserved_at_20[0x10];
6531         u8         op_mod[0x10];
6532
6533         u8         other_vport[0x1];
6534         u8         reserved_at_41[0xf];
6535         u8         vport_number[0x10];
6536
6537         u8         reserved_at_60[0x20];
6538 };
6539
6540 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6541         u8         status[0x8];
6542         u8         reserved_at_8[0x18];
6543
6544         u8         syndrome[0x20];
6545
6546         u8         reserved_at_40[0x40];
6547 };
6548
6549 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6550         u8         reserved_at_0[0x1b];
6551         u8         fdb_to_vport_reg_c_id[0x1];
6552         u8         vport_cvlan_insert[0x1];
6553         u8         vport_svlan_insert[0x1];
6554         u8         vport_cvlan_strip[0x1];
6555         u8         vport_svlan_strip[0x1];
6556 };
6557
6558 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6559         u8         opcode[0x10];
6560         u8         reserved_at_10[0x10];
6561
6562         u8         reserved_at_20[0x10];
6563         u8         op_mod[0x10];
6564
6565         u8         other_vport[0x1];
6566         u8         reserved_at_41[0xf];
6567         u8         vport_number[0x10];
6568
6569         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6570
6571         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6572 };
6573
6574 struct mlx5_ifc_query_eq_out_bits {
6575         u8         status[0x8];
6576         u8         reserved_at_8[0x18];
6577
6578         u8         syndrome[0x20];
6579
6580         u8         reserved_at_40[0x40];
6581
6582         struct mlx5_ifc_eqc_bits eq_context_entry;
6583
6584         u8         reserved_at_280[0x40];
6585
6586         u8         event_bitmask[0x40];
6587
6588         u8         reserved_at_300[0x580];
6589
6590         u8         pas[][0x40];
6591 };
6592
6593 struct mlx5_ifc_query_eq_in_bits {
6594         u8         opcode[0x10];
6595         u8         reserved_at_10[0x10];
6596
6597         u8         reserved_at_20[0x10];
6598         u8         op_mod[0x10];
6599
6600         u8         reserved_at_40[0x18];
6601         u8         eq_number[0x8];
6602
6603         u8         reserved_at_60[0x20];
6604 };
6605
6606 struct mlx5_ifc_packet_reformat_context_in_bits {
6607         u8         reformat_type[0x8];
6608         u8         reserved_at_8[0x4];
6609         u8         reformat_param_0[0x4];
6610         u8         reserved_at_10[0x6];
6611         u8         reformat_data_size[0xa];
6612
6613         u8         reformat_param_1[0x8];
6614         u8         reserved_at_28[0x8];
6615         u8         reformat_data[2][0x8];
6616
6617         u8         more_reformat_data[][0x8];
6618 };
6619
6620 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6621         u8         status[0x8];
6622         u8         reserved_at_8[0x18];
6623
6624         u8         syndrome[0x20];
6625
6626         u8         reserved_at_40[0xa0];
6627
6628         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6629 };
6630
6631 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6632         u8         opcode[0x10];
6633         u8         reserved_at_10[0x10];
6634
6635         u8         reserved_at_20[0x10];
6636         u8         op_mod[0x10];
6637
6638         u8         packet_reformat_id[0x20];
6639
6640         u8         reserved_at_60[0xa0];
6641 };
6642
6643 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6644         u8         status[0x8];
6645         u8         reserved_at_8[0x18];
6646
6647         u8         syndrome[0x20];
6648
6649         u8         packet_reformat_id[0x20];
6650
6651         u8         reserved_at_60[0x20];
6652 };
6653
6654 enum {
6655         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6656         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6657         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6658 };
6659
6660 enum mlx5_reformat_ctx_type {
6661         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6662         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6663         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6664         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6665         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6666         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6667         MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6668         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6669         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6670         MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6671         MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6672         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6673         MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6674         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6675         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6676         MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6677         MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6678 };
6679
6680 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6681         u8         opcode[0x10];
6682         u8         reserved_at_10[0x10];
6683
6684         u8         reserved_at_20[0x10];
6685         u8         op_mod[0x10];
6686
6687         u8         reserved_at_40[0xa0];
6688
6689         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6690 };
6691
6692 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6693         u8         status[0x8];
6694         u8         reserved_at_8[0x18];
6695
6696         u8         syndrome[0x20];
6697
6698         u8         reserved_at_40[0x40];
6699 };
6700
6701 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6702         u8         opcode[0x10];
6703         u8         reserved_at_10[0x10];
6704
6705         u8         reserved_20[0x10];
6706         u8         op_mod[0x10];
6707
6708         u8         packet_reformat_id[0x20];
6709
6710         u8         reserved_60[0x20];
6711 };
6712
6713 struct mlx5_ifc_set_action_in_bits {
6714         u8         action_type[0x4];
6715         u8         field[0xc];
6716         u8         reserved_at_10[0x3];
6717         u8         offset[0x5];
6718         u8         reserved_at_18[0x3];
6719         u8         length[0x5];
6720
6721         u8         data[0x20];
6722 };
6723
6724 struct mlx5_ifc_add_action_in_bits {
6725         u8         action_type[0x4];
6726         u8         field[0xc];
6727         u8         reserved_at_10[0x10];
6728
6729         u8         data[0x20];
6730 };
6731
6732 struct mlx5_ifc_copy_action_in_bits {
6733         u8         action_type[0x4];
6734         u8         src_field[0xc];
6735         u8         reserved_at_10[0x3];
6736         u8         src_offset[0x5];
6737         u8         reserved_at_18[0x3];
6738         u8         length[0x5];
6739
6740         u8         reserved_at_20[0x4];
6741         u8         dst_field[0xc];
6742         u8         reserved_at_30[0x3];
6743         u8         dst_offset[0x5];
6744         u8         reserved_at_38[0x8];
6745 };
6746
6747 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6748         struct mlx5_ifc_set_action_in_bits  set_action_in;
6749         struct mlx5_ifc_add_action_in_bits  add_action_in;
6750         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6751         u8         reserved_at_0[0x40];
6752 };
6753
6754 enum {
6755         MLX5_ACTION_TYPE_SET   = 0x1,
6756         MLX5_ACTION_TYPE_ADD   = 0x2,
6757         MLX5_ACTION_TYPE_COPY  = 0x3,
6758 };
6759
6760 enum {
6761         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6762         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6763         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6764         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6765         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6766         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6767         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6768         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6769         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6770         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6771         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6772         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6773         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6774         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6775         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6776         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6777         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6778         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6779         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6780         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6781         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6782         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6783         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6784         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6785         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6786         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6787         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6788         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6789         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6790         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6791         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6792         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6793         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6794         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6795         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6796         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6797         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6798         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6799         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6800 };
6801
6802 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6803         u8         status[0x8];
6804         u8         reserved_at_8[0x18];
6805
6806         u8         syndrome[0x20];
6807
6808         u8         modify_header_id[0x20];
6809
6810         u8         reserved_at_60[0x20];
6811 };
6812
6813 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6814         u8         opcode[0x10];
6815         u8         reserved_at_10[0x10];
6816
6817         u8         reserved_at_20[0x10];
6818         u8         op_mod[0x10];
6819
6820         u8         reserved_at_40[0x20];
6821
6822         u8         table_type[0x8];
6823         u8         reserved_at_68[0x10];
6824         u8         num_of_actions[0x8];
6825
6826         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6827 };
6828
6829 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6830         u8         status[0x8];
6831         u8         reserved_at_8[0x18];
6832
6833         u8         syndrome[0x20];
6834
6835         u8         reserved_at_40[0x40];
6836 };
6837
6838 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6839         u8         opcode[0x10];
6840         u8         reserved_at_10[0x10];
6841
6842         u8         reserved_at_20[0x10];
6843         u8         op_mod[0x10];
6844
6845         u8         modify_header_id[0x20];
6846
6847         u8         reserved_at_60[0x20];
6848 };
6849
6850 struct mlx5_ifc_query_modify_header_context_in_bits {
6851         u8         opcode[0x10];
6852         u8         uid[0x10];
6853
6854         u8         reserved_at_20[0x10];
6855         u8         op_mod[0x10];
6856
6857         u8         modify_header_id[0x20];
6858
6859         u8         reserved_at_60[0xa0];
6860 };
6861
6862 struct mlx5_ifc_query_dct_out_bits {
6863         u8         status[0x8];
6864         u8         reserved_at_8[0x18];
6865
6866         u8         syndrome[0x20];
6867
6868         u8         reserved_at_40[0x40];
6869
6870         struct mlx5_ifc_dctc_bits dct_context_entry;
6871
6872         u8         reserved_at_280[0x180];
6873 };
6874
6875 struct mlx5_ifc_query_dct_in_bits {
6876         u8         opcode[0x10];
6877         u8         reserved_at_10[0x10];
6878
6879         u8         reserved_at_20[0x10];
6880         u8         op_mod[0x10];
6881
6882         u8         reserved_at_40[0x8];
6883         u8         dctn[0x18];
6884
6885         u8         reserved_at_60[0x20];
6886 };
6887
6888 struct mlx5_ifc_query_cq_out_bits {
6889         u8         status[0x8];
6890         u8         reserved_at_8[0x18];
6891
6892         u8         syndrome[0x20];
6893
6894         u8         reserved_at_40[0x40];
6895
6896         struct mlx5_ifc_cqc_bits cq_context;
6897
6898         u8         reserved_at_280[0x600];
6899
6900         u8         pas[][0x40];
6901 };
6902
6903 struct mlx5_ifc_query_cq_in_bits {
6904         u8         opcode[0x10];
6905         u8         reserved_at_10[0x10];
6906
6907         u8         reserved_at_20[0x10];
6908         u8         op_mod[0x10];
6909
6910         u8         reserved_at_40[0x8];
6911         u8         cqn[0x18];
6912
6913         u8         reserved_at_60[0x20];
6914 };
6915
6916 struct mlx5_ifc_query_cong_status_out_bits {
6917         u8         status[0x8];
6918         u8         reserved_at_8[0x18];
6919
6920         u8         syndrome[0x20];
6921
6922         u8         reserved_at_40[0x20];
6923
6924         u8         enable[0x1];
6925         u8         tag_enable[0x1];
6926         u8         reserved_at_62[0x1e];
6927 };
6928
6929 struct mlx5_ifc_query_cong_status_in_bits {
6930         u8         opcode[0x10];
6931         u8         reserved_at_10[0x10];
6932
6933         u8         reserved_at_20[0x10];
6934         u8         op_mod[0x10];
6935
6936         u8         reserved_at_40[0x18];
6937         u8         priority[0x4];
6938         u8         cong_protocol[0x4];
6939
6940         u8         reserved_at_60[0x20];
6941 };
6942
6943 struct mlx5_ifc_query_cong_statistics_out_bits {
6944         u8         status[0x8];
6945         u8         reserved_at_8[0x18];
6946
6947         u8         syndrome[0x20];
6948
6949         u8         reserved_at_40[0x40];
6950
6951         u8         rp_cur_flows[0x20];
6952
6953         u8         sum_flows[0x20];
6954
6955         u8         rp_cnp_ignored_high[0x20];
6956
6957         u8         rp_cnp_ignored_low[0x20];
6958
6959         u8         rp_cnp_handled_high[0x20];
6960
6961         u8         rp_cnp_handled_low[0x20];
6962
6963         u8         reserved_at_140[0x100];
6964
6965         u8         time_stamp_high[0x20];
6966
6967         u8         time_stamp_low[0x20];
6968
6969         u8         accumulators_period[0x20];
6970
6971         u8         np_ecn_marked_roce_packets_high[0x20];
6972
6973         u8         np_ecn_marked_roce_packets_low[0x20];
6974
6975         u8         np_cnp_sent_high[0x20];
6976
6977         u8         np_cnp_sent_low[0x20];
6978
6979         u8         reserved_at_320[0x560];
6980 };
6981
6982 struct mlx5_ifc_query_cong_statistics_in_bits {
6983         u8         opcode[0x10];
6984         u8         reserved_at_10[0x10];
6985
6986         u8         reserved_at_20[0x10];
6987         u8         op_mod[0x10];
6988
6989         u8         clear[0x1];
6990         u8         reserved_at_41[0x1f];
6991
6992         u8         reserved_at_60[0x20];
6993 };
6994
6995 struct mlx5_ifc_query_cong_params_out_bits {
6996         u8         status[0x8];
6997         u8         reserved_at_8[0x18];
6998
6999         u8         syndrome[0x20];
7000
7001         u8         reserved_at_40[0x40];
7002
7003         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7004 };
7005
7006 struct mlx5_ifc_query_cong_params_in_bits {
7007         u8         opcode[0x10];
7008         u8         reserved_at_10[0x10];
7009
7010         u8         reserved_at_20[0x10];
7011         u8         op_mod[0x10];
7012
7013         u8         reserved_at_40[0x1c];
7014         u8         cong_protocol[0x4];
7015
7016         u8         reserved_at_60[0x20];
7017 };
7018
7019 struct mlx5_ifc_query_adapter_out_bits {
7020         u8         status[0x8];
7021         u8         reserved_at_8[0x18];
7022
7023         u8         syndrome[0x20];
7024
7025         u8         reserved_at_40[0x40];
7026
7027         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7028 };
7029
7030 struct mlx5_ifc_query_adapter_in_bits {
7031         u8         opcode[0x10];
7032         u8         reserved_at_10[0x10];
7033
7034         u8         reserved_at_20[0x10];
7035         u8         op_mod[0x10];
7036
7037         u8         reserved_at_40[0x40];
7038 };
7039
7040 struct mlx5_ifc_qp_2rst_out_bits {
7041         u8         status[0x8];
7042         u8         reserved_at_8[0x18];
7043
7044         u8         syndrome[0x20];
7045
7046         u8         reserved_at_40[0x40];
7047 };
7048
7049 struct mlx5_ifc_qp_2rst_in_bits {
7050         u8         opcode[0x10];
7051         u8         uid[0x10];
7052
7053         u8         reserved_at_20[0x10];
7054         u8         op_mod[0x10];
7055
7056         u8         reserved_at_40[0x8];
7057         u8         qpn[0x18];
7058
7059         u8         reserved_at_60[0x20];
7060 };
7061
7062 struct mlx5_ifc_qp_2err_out_bits {
7063         u8         status[0x8];
7064         u8         reserved_at_8[0x18];
7065
7066         u8         syndrome[0x20];
7067
7068         u8         reserved_at_40[0x40];
7069 };
7070
7071 struct mlx5_ifc_qp_2err_in_bits {
7072         u8         opcode[0x10];
7073         u8         uid[0x10];
7074
7075         u8         reserved_at_20[0x10];
7076         u8         op_mod[0x10];
7077
7078         u8         reserved_at_40[0x8];
7079         u8         qpn[0x18];
7080
7081         u8         reserved_at_60[0x20];
7082 };
7083
7084 struct mlx5_ifc_page_fault_resume_out_bits {
7085         u8         status[0x8];
7086         u8         reserved_at_8[0x18];
7087
7088         u8         syndrome[0x20];
7089
7090         u8         reserved_at_40[0x40];
7091 };
7092
7093 struct mlx5_ifc_page_fault_resume_in_bits {
7094         u8         opcode[0x10];
7095         u8         reserved_at_10[0x10];
7096
7097         u8         reserved_at_20[0x10];
7098         u8         op_mod[0x10];
7099
7100         u8         error[0x1];
7101         u8         reserved_at_41[0x4];
7102         u8         page_fault_type[0x3];
7103         u8         wq_number[0x18];
7104
7105         u8         reserved_at_60[0x8];
7106         u8         token[0x18];
7107 };
7108
7109 struct mlx5_ifc_nop_out_bits {
7110         u8         status[0x8];
7111         u8         reserved_at_8[0x18];
7112
7113         u8         syndrome[0x20];
7114
7115         u8         reserved_at_40[0x40];
7116 };
7117
7118 struct mlx5_ifc_nop_in_bits {
7119         u8         opcode[0x10];
7120         u8         reserved_at_10[0x10];
7121
7122         u8         reserved_at_20[0x10];
7123         u8         op_mod[0x10];
7124
7125         u8         reserved_at_40[0x40];
7126 };
7127
7128 struct mlx5_ifc_modify_vport_state_out_bits {
7129         u8         status[0x8];
7130         u8         reserved_at_8[0x18];
7131
7132         u8         syndrome[0x20];
7133
7134         u8         reserved_at_40[0x40];
7135 };
7136
7137 struct mlx5_ifc_modify_vport_state_in_bits {
7138         u8         opcode[0x10];
7139         u8         reserved_at_10[0x10];
7140
7141         u8         reserved_at_20[0x10];
7142         u8         op_mod[0x10];
7143
7144         u8         other_vport[0x1];
7145         u8         reserved_at_41[0xf];
7146         u8         vport_number[0x10];
7147
7148         u8         reserved_at_60[0x18];
7149         u8         admin_state[0x4];
7150         u8         reserved_at_7c[0x4];
7151 };
7152
7153 struct mlx5_ifc_modify_tis_out_bits {
7154         u8         status[0x8];
7155         u8         reserved_at_8[0x18];
7156
7157         u8         syndrome[0x20];
7158
7159         u8         reserved_at_40[0x40];
7160 };
7161
7162 struct mlx5_ifc_modify_tis_bitmask_bits {
7163         u8         reserved_at_0[0x20];
7164
7165         u8         reserved_at_20[0x1d];
7166         u8         lag_tx_port_affinity[0x1];
7167         u8         strict_lag_tx_port_affinity[0x1];
7168         u8         prio[0x1];
7169 };
7170
7171 struct mlx5_ifc_modify_tis_in_bits {
7172         u8         opcode[0x10];
7173         u8         uid[0x10];
7174
7175         u8         reserved_at_20[0x10];
7176         u8         op_mod[0x10];
7177
7178         u8         reserved_at_40[0x8];
7179         u8         tisn[0x18];
7180
7181         u8         reserved_at_60[0x20];
7182
7183         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7184
7185         u8         reserved_at_c0[0x40];
7186
7187         struct mlx5_ifc_tisc_bits ctx;
7188 };
7189
7190 struct mlx5_ifc_modify_tir_bitmask_bits {
7191         u8         reserved_at_0[0x20];
7192
7193         u8         reserved_at_20[0x1b];
7194         u8         self_lb_en[0x1];
7195         u8         reserved_at_3c[0x1];
7196         u8         hash[0x1];
7197         u8         reserved_at_3e[0x1];
7198         u8         packet_merge[0x1];
7199 };
7200
7201 struct mlx5_ifc_modify_tir_out_bits {
7202         u8         status[0x8];
7203         u8         reserved_at_8[0x18];
7204
7205         u8         syndrome[0x20];
7206
7207         u8         reserved_at_40[0x40];
7208 };
7209
7210 struct mlx5_ifc_modify_tir_in_bits {
7211         u8         opcode[0x10];
7212         u8         uid[0x10];
7213
7214         u8         reserved_at_20[0x10];
7215         u8         op_mod[0x10];
7216
7217         u8         reserved_at_40[0x8];
7218         u8         tirn[0x18];
7219
7220         u8         reserved_at_60[0x20];
7221
7222         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7223
7224         u8         reserved_at_c0[0x40];
7225
7226         struct mlx5_ifc_tirc_bits ctx;
7227 };
7228
7229 struct mlx5_ifc_modify_sq_out_bits {
7230         u8         status[0x8];
7231         u8         reserved_at_8[0x18];
7232
7233         u8         syndrome[0x20];
7234
7235         u8         reserved_at_40[0x40];
7236 };
7237
7238 struct mlx5_ifc_modify_sq_in_bits {
7239         u8         opcode[0x10];
7240         u8         uid[0x10];
7241
7242         u8         reserved_at_20[0x10];
7243         u8         op_mod[0x10];
7244
7245         u8         sq_state[0x4];
7246         u8         reserved_at_44[0x4];
7247         u8         sqn[0x18];
7248
7249         u8         reserved_at_60[0x20];
7250
7251         u8         modify_bitmask[0x40];
7252
7253         u8         reserved_at_c0[0x40];
7254
7255         struct mlx5_ifc_sqc_bits ctx;
7256 };
7257
7258 struct mlx5_ifc_modify_scheduling_element_out_bits {
7259         u8         status[0x8];
7260         u8         reserved_at_8[0x18];
7261
7262         u8         syndrome[0x20];
7263
7264         u8         reserved_at_40[0x1c0];
7265 };
7266
7267 enum {
7268         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7269         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7270 };
7271
7272 struct mlx5_ifc_modify_scheduling_element_in_bits {
7273         u8         opcode[0x10];
7274         u8         reserved_at_10[0x10];
7275
7276         u8         reserved_at_20[0x10];
7277         u8         op_mod[0x10];
7278
7279         u8         scheduling_hierarchy[0x8];
7280         u8         reserved_at_48[0x18];
7281
7282         u8         scheduling_element_id[0x20];
7283
7284         u8         reserved_at_80[0x20];
7285
7286         u8         modify_bitmask[0x20];
7287
7288         u8         reserved_at_c0[0x40];
7289
7290         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7291
7292         u8         reserved_at_300[0x100];
7293 };
7294
7295 struct mlx5_ifc_modify_rqt_out_bits {
7296         u8         status[0x8];
7297         u8         reserved_at_8[0x18];
7298
7299         u8         syndrome[0x20];
7300
7301         u8         reserved_at_40[0x40];
7302 };
7303
7304 struct mlx5_ifc_rqt_bitmask_bits {
7305         u8         reserved_at_0[0x20];
7306
7307         u8         reserved_at_20[0x1f];
7308         u8         rqn_list[0x1];
7309 };
7310
7311 struct mlx5_ifc_modify_rqt_in_bits {
7312         u8         opcode[0x10];
7313         u8         uid[0x10];
7314
7315         u8         reserved_at_20[0x10];
7316         u8         op_mod[0x10];
7317
7318         u8         reserved_at_40[0x8];
7319         u8         rqtn[0x18];
7320
7321         u8         reserved_at_60[0x20];
7322
7323         struct mlx5_ifc_rqt_bitmask_bits bitmask;
7324
7325         u8         reserved_at_c0[0x40];
7326
7327         struct mlx5_ifc_rqtc_bits ctx;
7328 };
7329
7330 struct mlx5_ifc_modify_rq_out_bits {
7331         u8         status[0x8];
7332         u8         reserved_at_8[0x18];
7333
7334         u8         syndrome[0x20];
7335
7336         u8         reserved_at_40[0x40];
7337 };
7338
7339 enum {
7340         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7341         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7342         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7343 };
7344
7345 struct mlx5_ifc_modify_rq_in_bits {
7346         u8         opcode[0x10];
7347         u8         uid[0x10];
7348
7349         u8         reserved_at_20[0x10];
7350         u8         op_mod[0x10];
7351
7352         u8         rq_state[0x4];
7353         u8         reserved_at_44[0x4];
7354         u8         rqn[0x18];
7355
7356         u8         reserved_at_60[0x20];
7357
7358         u8         modify_bitmask[0x40];
7359
7360         u8         reserved_at_c0[0x40];
7361
7362         struct mlx5_ifc_rqc_bits ctx;
7363 };
7364
7365 struct mlx5_ifc_modify_rmp_out_bits {
7366         u8         status[0x8];
7367         u8         reserved_at_8[0x18];
7368
7369         u8         syndrome[0x20];
7370
7371         u8         reserved_at_40[0x40];
7372 };
7373
7374 struct mlx5_ifc_rmp_bitmask_bits {
7375         u8         reserved_at_0[0x20];
7376
7377         u8         reserved_at_20[0x1f];
7378         u8         lwm[0x1];
7379 };
7380
7381 struct mlx5_ifc_modify_rmp_in_bits {
7382         u8         opcode[0x10];
7383         u8         uid[0x10];
7384
7385         u8         reserved_at_20[0x10];
7386         u8         op_mod[0x10];
7387
7388         u8         rmp_state[0x4];
7389         u8         reserved_at_44[0x4];
7390         u8         rmpn[0x18];
7391
7392         u8         reserved_at_60[0x20];
7393
7394         struct mlx5_ifc_rmp_bitmask_bits bitmask;
7395
7396         u8         reserved_at_c0[0x40];
7397
7398         struct mlx5_ifc_rmpc_bits ctx;
7399 };
7400
7401 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7402         u8         status[0x8];
7403         u8         reserved_at_8[0x18];
7404
7405         u8         syndrome[0x20];
7406
7407         u8         reserved_at_40[0x40];
7408 };
7409
7410 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7411         u8         reserved_at_0[0x12];
7412         u8         affiliation[0x1];
7413         u8         reserved_at_13[0x1];
7414         u8         disable_uc_local_lb[0x1];
7415         u8         disable_mc_local_lb[0x1];
7416         u8         node_guid[0x1];
7417         u8         port_guid[0x1];
7418         u8         min_inline[0x1];
7419         u8         mtu[0x1];
7420         u8         change_event[0x1];
7421         u8         promisc[0x1];
7422         u8         permanent_address[0x1];
7423         u8         addresses_list[0x1];
7424         u8         roce_en[0x1];
7425         u8         reserved_at_1f[0x1];
7426 };
7427
7428 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7429         u8         opcode[0x10];
7430         u8         reserved_at_10[0x10];
7431
7432         u8         reserved_at_20[0x10];
7433         u8         op_mod[0x10];
7434
7435         u8         other_vport[0x1];
7436         u8         reserved_at_41[0xf];
7437         u8         vport_number[0x10];
7438
7439         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7440
7441         u8         reserved_at_80[0x780];
7442
7443         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7444 };
7445
7446 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7447         u8         status[0x8];
7448         u8         reserved_at_8[0x18];
7449
7450         u8         syndrome[0x20];
7451
7452         u8         reserved_at_40[0x40];
7453 };
7454
7455 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7456         u8         opcode[0x10];
7457         u8         reserved_at_10[0x10];
7458
7459         u8         reserved_at_20[0x10];
7460         u8         op_mod[0x10];
7461
7462         u8         other_vport[0x1];
7463         u8         reserved_at_41[0xb];
7464         u8         port_num[0x4];
7465         u8         vport_number[0x10];
7466
7467         u8         reserved_at_60[0x20];
7468
7469         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7470 };
7471
7472 struct mlx5_ifc_modify_cq_out_bits {
7473         u8         status[0x8];
7474         u8         reserved_at_8[0x18];
7475
7476         u8         syndrome[0x20];
7477
7478         u8         reserved_at_40[0x40];
7479 };
7480
7481 enum {
7482         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7483         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7484 };
7485
7486 struct mlx5_ifc_modify_cq_in_bits {
7487         u8         opcode[0x10];
7488         u8         uid[0x10];
7489
7490         u8         reserved_at_20[0x10];
7491         u8         op_mod[0x10];
7492
7493         u8         reserved_at_40[0x8];
7494         u8         cqn[0x18];
7495
7496         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7497
7498         struct mlx5_ifc_cqc_bits cq_context;
7499
7500         u8         reserved_at_280[0x60];
7501
7502         u8         cq_umem_valid[0x1];
7503         u8         reserved_at_2e1[0x1f];
7504
7505         u8         reserved_at_300[0x580];
7506
7507         u8         pas[][0x40];
7508 };
7509
7510 struct mlx5_ifc_modify_cong_status_out_bits {
7511         u8         status[0x8];
7512         u8         reserved_at_8[0x18];
7513
7514         u8         syndrome[0x20];
7515
7516         u8         reserved_at_40[0x40];
7517 };
7518
7519 struct mlx5_ifc_modify_cong_status_in_bits {
7520         u8         opcode[0x10];
7521         u8         reserved_at_10[0x10];
7522
7523         u8         reserved_at_20[0x10];
7524         u8         op_mod[0x10];
7525
7526         u8         reserved_at_40[0x18];
7527         u8         priority[0x4];
7528         u8         cong_protocol[0x4];
7529
7530         u8         enable[0x1];
7531         u8         tag_enable[0x1];
7532         u8         reserved_at_62[0x1e];
7533 };
7534
7535 struct mlx5_ifc_modify_cong_params_out_bits {
7536         u8         status[0x8];
7537         u8         reserved_at_8[0x18];
7538
7539         u8         syndrome[0x20];
7540
7541         u8         reserved_at_40[0x40];
7542 };
7543
7544 struct mlx5_ifc_modify_cong_params_in_bits {
7545         u8         opcode[0x10];
7546         u8         reserved_at_10[0x10];
7547
7548         u8         reserved_at_20[0x10];
7549         u8         op_mod[0x10];
7550
7551         u8         reserved_at_40[0x1c];
7552         u8         cong_protocol[0x4];
7553
7554         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7555
7556         u8         reserved_at_80[0x80];
7557
7558         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7559 };
7560
7561 struct mlx5_ifc_manage_pages_out_bits {
7562         u8         status[0x8];
7563         u8         reserved_at_8[0x18];
7564
7565         u8         syndrome[0x20];
7566
7567         u8         output_num_entries[0x20];
7568
7569         u8         reserved_at_60[0x20];
7570
7571         u8         pas[][0x40];
7572 };
7573
7574 enum {
7575         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7576         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7577         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7578 };
7579
7580 struct mlx5_ifc_manage_pages_in_bits {
7581         u8         opcode[0x10];
7582         u8         reserved_at_10[0x10];
7583
7584         u8         reserved_at_20[0x10];
7585         u8         op_mod[0x10];
7586
7587         u8         embedded_cpu_function[0x1];
7588         u8         reserved_at_41[0xf];
7589         u8         function_id[0x10];
7590
7591         u8         input_num_entries[0x20];
7592
7593         u8         pas[][0x40];
7594 };
7595
7596 struct mlx5_ifc_mad_ifc_out_bits {
7597         u8         status[0x8];
7598         u8         reserved_at_8[0x18];
7599
7600         u8         syndrome[0x20];
7601
7602         u8         reserved_at_40[0x40];
7603
7604         u8         response_mad_packet[256][0x8];
7605 };
7606
7607 struct mlx5_ifc_mad_ifc_in_bits {
7608         u8         opcode[0x10];
7609         u8         reserved_at_10[0x10];
7610
7611         u8         reserved_at_20[0x10];
7612         u8         op_mod[0x10];
7613
7614         u8         remote_lid[0x10];
7615         u8         reserved_at_50[0x8];
7616         u8         port[0x8];
7617
7618         u8         reserved_at_60[0x20];
7619
7620         u8         mad[256][0x8];
7621 };
7622
7623 struct mlx5_ifc_init_hca_out_bits {
7624         u8         status[0x8];
7625         u8         reserved_at_8[0x18];
7626
7627         u8         syndrome[0x20];
7628
7629         u8         reserved_at_40[0x40];
7630 };
7631
7632 struct mlx5_ifc_init_hca_in_bits {
7633         u8         opcode[0x10];
7634         u8         reserved_at_10[0x10];
7635
7636         u8         reserved_at_20[0x10];
7637         u8         op_mod[0x10];
7638
7639         u8         reserved_at_40[0x20];
7640
7641         u8         reserved_at_60[0x2];
7642         u8         sw_vhca_id[0xe];
7643         u8         reserved_at_70[0x10];
7644
7645         u8         sw_owner_id[4][0x20];
7646 };
7647
7648 struct mlx5_ifc_init2rtr_qp_out_bits {
7649         u8         status[0x8];
7650         u8         reserved_at_8[0x18];
7651
7652         u8         syndrome[0x20];
7653
7654         u8         reserved_at_40[0x20];
7655         u8         ece[0x20];
7656 };
7657
7658 struct mlx5_ifc_init2rtr_qp_in_bits {
7659         u8         opcode[0x10];
7660         u8         uid[0x10];
7661
7662         u8         reserved_at_20[0x10];
7663         u8         op_mod[0x10];
7664
7665         u8         reserved_at_40[0x8];
7666         u8         qpn[0x18];
7667
7668         u8         reserved_at_60[0x20];
7669
7670         u8         opt_param_mask[0x20];
7671
7672         u8         ece[0x20];
7673
7674         struct mlx5_ifc_qpc_bits qpc;
7675
7676         u8         reserved_at_800[0x80];
7677 };
7678
7679 struct mlx5_ifc_init2init_qp_out_bits {
7680         u8         status[0x8];
7681         u8         reserved_at_8[0x18];
7682
7683         u8         syndrome[0x20];
7684
7685         u8         reserved_at_40[0x20];
7686         u8         ece[0x20];
7687 };
7688
7689 struct mlx5_ifc_init2init_qp_in_bits {
7690         u8         opcode[0x10];
7691         u8         uid[0x10];
7692
7693         u8         reserved_at_20[0x10];
7694         u8         op_mod[0x10];
7695
7696         u8         reserved_at_40[0x8];
7697         u8         qpn[0x18];
7698
7699         u8         reserved_at_60[0x20];
7700
7701         u8         opt_param_mask[0x20];
7702
7703         u8         ece[0x20];
7704
7705         struct mlx5_ifc_qpc_bits qpc;
7706
7707         u8         reserved_at_800[0x80];
7708 };
7709
7710 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7711         u8         status[0x8];
7712         u8         reserved_at_8[0x18];
7713
7714         u8         syndrome[0x20];
7715
7716         u8         reserved_at_40[0x40];
7717
7718         u8         packet_headers_log[128][0x8];
7719
7720         u8         packet_syndrome[64][0x8];
7721 };
7722
7723 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7724         u8         opcode[0x10];
7725         u8         reserved_at_10[0x10];
7726
7727         u8         reserved_at_20[0x10];
7728         u8         op_mod[0x10];
7729
7730         u8         reserved_at_40[0x40];
7731 };
7732
7733 struct mlx5_ifc_gen_eqe_in_bits {
7734         u8         opcode[0x10];
7735         u8         reserved_at_10[0x10];
7736
7737         u8         reserved_at_20[0x10];
7738         u8         op_mod[0x10];
7739
7740         u8         reserved_at_40[0x18];
7741         u8         eq_number[0x8];
7742
7743         u8         reserved_at_60[0x20];
7744
7745         u8         eqe[64][0x8];
7746 };
7747
7748 struct mlx5_ifc_gen_eq_out_bits {
7749         u8         status[0x8];
7750         u8         reserved_at_8[0x18];
7751
7752         u8         syndrome[0x20];
7753
7754         u8         reserved_at_40[0x40];
7755 };
7756
7757 struct mlx5_ifc_enable_hca_out_bits {
7758         u8         status[0x8];
7759         u8         reserved_at_8[0x18];
7760
7761         u8         syndrome[0x20];
7762
7763         u8         reserved_at_40[0x20];
7764 };
7765
7766 struct mlx5_ifc_enable_hca_in_bits {
7767         u8         opcode[0x10];
7768         u8         reserved_at_10[0x10];
7769
7770         u8         reserved_at_20[0x10];
7771         u8         op_mod[0x10];
7772
7773         u8         embedded_cpu_function[0x1];
7774         u8         reserved_at_41[0xf];
7775         u8         function_id[0x10];
7776
7777         u8         reserved_at_60[0x20];
7778 };
7779
7780 struct mlx5_ifc_drain_dct_out_bits {
7781         u8         status[0x8];
7782         u8         reserved_at_8[0x18];
7783
7784         u8         syndrome[0x20];
7785
7786         u8         reserved_at_40[0x40];
7787 };
7788
7789 struct mlx5_ifc_drain_dct_in_bits {
7790         u8         opcode[0x10];
7791         u8         uid[0x10];
7792
7793         u8         reserved_at_20[0x10];
7794         u8         op_mod[0x10];
7795
7796         u8         reserved_at_40[0x8];
7797         u8         dctn[0x18];
7798
7799         u8         reserved_at_60[0x20];
7800 };
7801
7802 struct mlx5_ifc_disable_hca_out_bits {
7803         u8         status[0x8];
7804         u8         reserved_at_8[0x18];
7805
7806         u8         syndrome[0x20];
7807
7808         u8         reserved_at_40[0x20];
7809 };
7810
7811 struct mlx5_ifc_disable_hca_in_bits {
7812         u8         opcode[0x10];
7813         u8         reserved_at_10[0x10];
7814
7815         u8         reserved_at_20[0x10];
7816         u8         op_mod[0x10];
7817
7818         u8         embedded_cpu_function[0x1];
7819         u8         reserved_at_41[0xf];
7820         u8         function_id[0x10];
7821
7822         u8         reserved_at_60[0x20];
7823 };
7824
7825 struct mlx5_ifc_detach_from_mcg_out_bits {
7826         u8         status[0x8];
7827         u8         reserved_at_8[0x18];
7828
7829         u8         syndrome[0x20];
7830
7831         u8         reserved_at_40[0x40];
7832 };
7833
7834 struct mlx5_ifc_detach_from_mcg_in_bits {
7835         u8         opcode[0x10];
7836         u8         uid[0x10];
7837
7838         u8         reserved_at_20[0x10];
7839         u8         op_mod[0x10];
7840
7841         u8         reserved_at_40[0x8];
7842         u8         qpn[0x18];
7843
7844         u8         reserved_at_60[0x20];
7845
7846         u8         multicast_gid[16][0x8];
7847 };
7848
7849 struct mlx5_ifc_destroy_xrq_out_bits {
7850         u8         status[0x8];
7851         u8         reserved_at_8[0x18];
7852
7853         u8         syndrome[0x20];
7854
7855         u8         reserved_at_40[0x40];
7856 };
7857
7858 struct mlx5_ifc_destroy_xrq_in_bits {
7859         u8         opcode[0x10];
7860         u8         uid[0x10];
7861
7862         u8         reserved_at_20[0x10];
7863         u8         op_mod[0x10];
7864
7865         u8         reserved_at_40[0x8];
7866         u8         xrqn[0x18];
7867
7868         u8         reserved_at_60[0x20];
7869 };
7870
7871 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7872         u8         status[0x8];
7873         u8         reserved_at_8[0x18];
7874
7875         u8         syndrome[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878 };
7879
7880 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7881         u8         opcode[0x10];
7882         u8         uid[0x10];
7883
7884         u8         reserved_at_20[0x10];
7885         u8         op_mod[0x10];
7886
7887         u8         reserved_at_40[0x8];
7888         u8         xrc_srqn[0x18];
7889
7890         u8         reserved_at_60[0x20];
7891 };
7892
7893 struct mlx5_ifc_destroy_tis_out_bits {
7894         u8         status[0x8];
7895         u8         reserved_at_8[0x18];
7896
7897         u8         syndrome[0x20];
7898
7899         u8         reserved_at_40[0x40];
7900 };
7901
7902 struct mlx5_ifc_destroy_tis_in_bits {
7903         u8         opcode[0x10];
7904         u8         uid[0x10];
7905
7906         u8         reserved_at_20[0x10];
7907         u8         op_mod[0x10];
7908
7909         u8         reserved_at_40[0x8];
7910         u8         tisn[0x18];
7911
7912         u8         reserved_at_60[0x20];
7913 };
7914
7915 struct mlx5_ifc_destroy_tir_out_bits {
7916         u8         status[0x8];
7917         u8         reserved_at_8[0x18];
7918
7919         u8         syndrome[0x20];
7920
7921         u8         reserved_at_40[0x40];
7922 };
7923
7924 struct mlx5_ifc_destroy_tir_in_bits {
7925         u8         opcode[0x10];
7926         u8         uid[0x10];
7927
7928         u8         reserved_at_20[0x10];
7929         u8         op_mod[0x10];
7930
7931         u8         reserved_at_40[0x8];
7932         u8         tirn[0x18];
7933
7934         u8         reserved_at_60[0x20];
7935 };
7936
7937 struct mlx5_ifc_destroy_srq_out_bits {
7938         u8         status[0x8];
7939         u8         reserved_at_8[0x18];
7940
7941         u8         syndrome[0x20];
7942
7943         u8         reserved_at_40[0x40];
7944 };
7945
7946 struct mlx5_ifc_destroy_srq_in_bits {
7947         u8         opcode[0x10];
7948         u8         uid[0x10];
7949
7950         u8         reserved_at_20[0x10];
7951         u8         op_mod[0x10];
7952
7953         u8         reserved_at_40[0x8];
7954         u8         srqn[0x18];
7955
7956         u8         reserved_at_60[0x20];
7957 };
7958
7959 struct mlx5_ifc_destroy_sq_out_bits {
7960         u8         status[0x8];
7961         u8         reserved_at_8[0x18];
7962
7963         u8         syndrome[0x20];
7964
7965         u8         reserved_at_40[0x40];
7966 };
7967
7968 struct mlx5_ifc_destroy_sq_in_bits {
7969         u8         opcode[0x10];
7970         u8         uid[0x10];
7971
7972         u8         reserved_at_20[0x10];
7973         u8         op_mod[0x10];
7974
7975         u8         reserved_at_40[0x8];
7976         u8         sqn[0x18];
7977
7978         u8         reserved_at_60[0x20];
7979 };
7980
7981 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7982         u8         status[0x8];
7983         u8         reserved_at_8[0x18];
7984
7985         u8         syndrome[0x20];
7986
7987         u8         reserved_at_40[0x1c0];
7988 };
7989
7990 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7991         u8         opcode[0x10];
7992         u8         reserved_at_10[0x10];
7993
7994         u8         reserved_at_20[0x10];
7995         u8         op_mod[0x10];
7996
7997         u8         scheduling_hierarchy[0x8];
7998         u8         reserved_at_48[0x18];
7999
8000         u8         scheduling_element_id[0x20];
8001
8002         u8         reserved_at_80[0x180];
8003 };
8004
8005 struct mlx5_ifc_destroy_rqt_out_bits {
8006         u8         status[0x8];
8007         u8         reserved_at_8[0x18];
8008
8009         u8         syndrome[0x20];
8010
8011         u8         reserved_at_40[0x40];
8012 };
8013
8014 struct mlx5_ifc_destroy_rqt_in_bits {
8015         u8         opcode[0x10];
8016         u8         uid[0x10];
8017
8018         u8         reserved_at_20[0x10];
8019         u8         op_mod[0x10];
8020
8021         u8         reserved_at_40[0x8];
8022         u8         rqtn[0x18];
8023
8024         u8         reserved_at_60[0x20];
8025 };
8026
8027 struct mlx5_ifc_destroy_rq_out_bits {
8028         u8         status[0x8];
8029         u8         reserved_at_8[0x18];
8030
8031         u8         syndrome[0x20];
8032
8033         u8         reserved_at_40[0x40];
8034 };
8035
8036 struct mlx5_ifc_destroy_rq_in_bits {
8037         u8         opcode[0x10];
8038         u8         uid[0x10];
8039
8040         u8         reserved_at_20[0x10];
8041         u8         op_mod[0x10];
8042
8043         u8         reserved_at_40[0x8];
8044         u8         rqn[0x18];
8045
8046         u8         reserved_at_60[0x20];
8047 };
8048
8049 struct mlx5_ifc_set_delay_drop_params_in_bits {
8050         u8         opcode[0x10];
8051         u8         reserved_at_10[0x10];
8052
8053         u8         reserved_at_20[0x10];
8054         u8         op_mod[0x10];
8055
8056         u8         reserved_at_40[0x20];
8057
8058         u8         reserved_at_60[0x10];
8059         u8         delay_drop_timeout[0x10];
8060 };
8061
8062 struct mlx5_ifc_set_delay_drop_params_out_bits {
8063         u8         status[0x8];
8064         u8         reserved_at_8[0x18];
8065
8066         u8         syndrome[0x20];
8067
8068         u8         reserved_at_40[0x40];
8069 };
8070
8071 struct mlx5_ifc_destroy_rmp_out_bits {
8072         u8         status[0x8];
8073         u8         reserved_at_8[0x18];
8074
8075         u8         syndrome[0x20];
8076
8077         u8         reserved_at_40[0x40];
8078 };
8079
8080 struct mlx5_ifc_destroy_rmp_in_bits {
8081         u8         opcode[0x10];
8082         u8         uid[0x10];
8083
8084         u8         reserved_at_20[0x10];
8085         u8         op_mod[0x10];
8086
8087         u8         reserved_at_40[0x8];
8088         u8         rmpn[0x18];
8089
8090         u8         reserved_at_60[0x20];
8091 };
8092
8093 struct mlx5_ifc_destroy_qp_out_bits {
8094         u8         status[0x8];
8095         u8         reserved_at_8[0x18];
8096
8097         u8         syndrome[0x20];
8098
8099         u8         reserved_at_40[0x40];
8100 };
8101
8102 struct mlx5_ifc_destroy_qp_in_bits {
8103         u8         opcode[0x10];
8104         u8         uid[0x10];
8105
8106         u8         reserved_at_20[0x10];
8107         u8         op_mod[0x10];
8108
8109         u8         reserved_at_40[0x8];
8110         u8         qpn[0x18];
8111
8112         u8         reserved_at_60[0x20];
8113 };
8114
8115 struct mlx5_ifc_destroy_psv_out_bits {
8116         u8         status[0x8];
8117         u8         reserved_at_8[0x18];
8118
8119         u8         syndrome[0x20];
8120
8121         u8         reserved_at_40[0x40];
8122 };
8123
8124 struct mlx5_ifc_destroy_psv_in_bits {
8125         u8         opcode[0x10];
8126         u8         reserved_at_10[0x10];
8127
8128         u8         reserved_at_20[0x10];
8129         u8         op_mod[0x10];
8130
8131         u8         reserved_at_40[0x8];
8132         u8         psvn[0x18];
8133
8134         u8         reserved_at_60[0x20];
8135 };
8136
8137 struct mlx5_ifc_destroy_mkey_out_bits {
8138         u8         status[0x8];
8139         u8         reserved_at_8[0x18];
8140
8141         u8         syndrome[0x20];
8142
8143         u8         reserved_at_40[0x40];
8144 };
8145
8146 struct mlx5_ifc_destroy_mkey_in_bits {
8147         u8         opcode[0x10];
8148         u8         uid[0x10];
8149
8150         u8         reserved_at_20[0x10];
8151         u8         op_mod[0x10];
8152
8153         u8         reserved_at_40[0x8];
8154         u8         mkey_index[0x18];
8155
8156         u8         reserved_at_60[0x20];
8157 };
8158
8159 struct mlx5_ifc_destroy_flow_table_out_bits {
8160         u8         status[0x8];
8161         u8         reserved_at_8[0x18];
8162
8163         u8         syndrome[0x20];
8164
8165         u8         reserved_at_40[0x40];
8166 };
8167
8168 struct mlx5_ifc_destroy_flow_table_in_bits {
8169         u8         opcode[0x10];
8170         u8         reserved_at_10[0x10];
8171
8172         u8         reserved_at_20[0x10];
8173         u8         op_mod[0x10];
8174
8175         u8         other_vport[0x1];
8176         u8         reserved_at_41[0xf];
8177         u8         vport_number[0x10];
8178
8179         u8         reserved_at_60[0x20];
8180
8181         u8         table_type[0x8];
8182         u8         reserved_at_88[0x18];
8183
8184         u8         reserved_at_a0[0x8];
8185         u8         table_id[0x18];
8186
8187         u8         reserved_at_c0[0x140];
8188 };
8189
8190 struct mlx5_ifc_destroy_flow_group_out_bits {
8191         u8         status[0x8];
8192         u8         reserved_at_8[0x18];
8193
8194         u8         syndrome[0x20];
8195
8196         u8         reserved_at_40[0x40];
8197 };
8198
8199 struct mlx5_ifc_destroy_flow_group_in_bits {
8200         u8         opcode[0x10];
8201         u8         reserved_at_10[0x10];
8202
8203         u8         reserved_at_20[0x10];
8204         u8         op_mod[0x10];
8205
8206         u8         other_vport[0x1];
8207         u8         reserved_at_41[0xf];
8208         u8         vport_number[0x10];
8209
8210         u8         reserved_at_60[0x20];
8211
8212         u8         table_type[0x8];
8213         u8         reserved_at_88[0x18];
8214
8215         u8         reserved_at_a0[0x8];
8216         u8         table_id[0x18];
8217
8218         u8         group_id[0x20];
8219
8220         u8         reserved_at_e0[0x120];
8221 };
8222
8223 struct mlx5_ifc_destroy_eq_out_bits {
8224         u8         status[0x8];
8225         u8         reserved_at_8[0x18];
8226
8227         u8         syndrome[0x20];
8228
8229         u8         reserved_at_40[0x40];
8230 };
8231
8232 struct mlx5_ifc_destroy_eq_in_bits {
8233         u8         opcode[0x10];
8234         u8         reserved_at_10[0x10];
8235
8236         u8         reserved_at_20[0x10];
8237         u8         op_mod[0x10];
8238
8239         u8         reserved_at_40[0x18];
8240         u8         eq_number[0x8];
8241
8242         u8         reserved_at_60[0x20];
8243 };
8244
8245 struct mlx5_ifc_destroy_dct_out_bits {
8246         u8         status[0x8];
8247         u8         reserved_at_8[0x18];
8248
8249         u8         syndrome[0x20];
8250
8251         u8         reserved_at_40[0x40];
8252 };
8253
8254 struct mlx5_ifc_destroy_dct_in_bits {
8255         u8         opcode[0x10];
8256         u8         uid[0x10];
8257
8258         u8         reserved_at_20[0x10];
8259         u8         op_mod[0x10];
8260
8261         u8         reserved_at_40[0x8];
8262         u8         dctn[0x18];
8263
8264         u8         reserved_at_60[0x20];
8265 };
8266
8267 struct mlx5_ifc_destroy_cq_out_bits {
8268         u8         status[0x8];
8269         u8         reserved_at_8[0x18];
8270
8271         u8         syndrome[0x20];
8272
8273         u8         reserved_at_40[0x40];
8274 };
8275
8276 struct mlx5_ifc_destroy_cq_in_bits {
8277         u8         opcode[0x10];
8278         u8         uid[0x10];
8279
8280         u8         reserved_at_20[0x10];
8281         u8         op_mod[0x10];
8282
8283         u8         reserved_at_40[0x8];
8284         u8         cqn[0x18];
8285
8286         u8         reserved_at_60[0x20];
8287 };
8288
8289 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8290         u8         status[0x8];
8291         u8         reserved_at_8[0x18];
8292
8293         u8         syndrome[0x20];
8294
8295         u8         reserved_at_40[0x40];
8296 };
8297
8298 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8299         u8         opcode[0x10];
8300         u8         reserved_at_10[0x10];
8301
8302         u8         reserved_at_20[0x10];
8303         u8         op_mod[0x10];
8304
8305         u8         reserved_at_40[0x20];
8306
8307         u8         reserved_at_60[0x10];
8308         u8         vxlan_udp_port[0x10];
8309 };
8310
8311 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8312         u8         status[0x8];
8313         u8         reserved_at_8[0x18];
8314
8315         u8         syndrome[0x20];
8316
8317         u8         reserved_at_40[0x40];
8318 };
8319
8320 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8321         u8         opcode[0x10];
8322         u8         reserved_at_10[0x10];
8323
8324         u8         reserved_at_20[0x10];
8325         u8         op_mod[0x10];
8326
8327         u8         reserved_at_40[0x60];
8328
8329         u8         reserved_at_a0[0x8];
8330         u8         table_index[0x18];
8331
8332         u8         reserved_at_c0[0x140];
8333 };
8334
8335 struct mlx5_ifc_delete_fte_out_bits {
8336         u8         status[0x8];
8337         u8         reserved_at_8[0x18];
8338
8339         u8         syndrome[0x20];
8340
8341         u8         reserved_at_40[0x40];
8342 };
8343
8344 struct mlx5_ifc_delete_fte_in_bits {
8345         u8         opcode[0x10];
8346         u8         reserved_at_10[0x10];
8347
8348         u8         reserved_at_20[0x10];
8349         u8         op_mod[0x10];
8350
8351         u8         other_vport[0x1];
8352         u8         reserved_at_41[0xf];
8353         u8         vport_number[0x10];
8354
8355         u8         reserved_at_60[0x20];
8356
8357         u8         table_type[0x8];
8358         u8         reserved_at_88[0x18];
8359
8360         u8         reserved_at_a0[0x8];
8361         u8         table_id[0x18];
8362
8363         u8         reserved_at_c0[0x40];
8364
8365         u8         flow_index[0x20];
8366
8367         u8         reserved_at_120[0xe0];
8368 };
8369
8370 struct mlx5_ifc_dealloc_xrcd_out_bits {
8371         u8         status[0x8];
8372         u8         reserved_at_8[0x18];
8373
8374         u8         syndrome[0x20];
8375
8376         u8         reserved_at_40[0x40];
8377 };
8378
8379 struct mlx5_ifc_dealloc_xrcd_in_bits {
8380         u8         opcode[0x10];
8381         u8         uid[0x10];
8382
8383         u8         reserved_at_20[0x10];
8384         u8         op_mod[0x10];
8385
8386         u8         reserved_at_40[0x8];
8387         u8         xrcd[0x18];
8388
8389         u8         reserved_at_60[0x20];
8390 };
8391
8392 struct mlx5_ifc_dealloc_uar_out_bits {
8393         u8         status[0x8];
8394         u8         reserved_at_8[0x18];
8395
8396         u8         syndrome[0x20];
8397
8398         u8         reserved_at_40[0x40];
8399 };
8400
8401 struct mlx5_ifc_dealloc_uar_in_bits {
8402         u8         opcode[0x10];
8403         u8         uid[0x10];
8404
8405         u8         reserved_at_20[0x10];
8406         u8         op_mod[0x10];
8407
8408         u8         reserved_at_40[0x8];
8409         u8         uar[0x18];
8410
8411         u8         reserved_at_60[0x20];
8412 };
8413
8414 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8415         u8         status[0x8];
8416         u8         reserved_at_8[0x18];
8417
8418         u8         syndrome[0x20];
8419
8420         u8         reserved_at_40[0x40];
8421 };
8422
8423 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8424         u8         opcode[0x10];
8425         u8         uid[0x10];
8426
8427         u8         reserved_at_20[0x10];
8428         u8         op_mod[0x10];
8429
8430         u8         reserved_at_40[0x8];
8431         u8         transport_domain[0x18];
8432
8433         u8         reserved_at_60[0x20];
8434 };
8435
8436 struct mlx5_ifc_dealloc_q_counter_out_bits {
8437         u8         status[0x8];
8438         u8         reserved_at_8[0x18];
8439
8440         u8         syndrome[0x20];
8441
8442         u8         reserved_at_40[0x40];
8443 };
8444
8445 struct mlx5_ifc_dealloc_q_counter_in_bits {
8446         u8         opcode[0x10];
8447         u8         reserved_at_10[0x10];
8448
8449         u8         reserved_at_20[0x10];
8450         u8         op_mod[0x10];
8451
8452         u8         reserved_at_40[0x18];
8453         u8         counter_set_id[0x8];
8454
8455         u8         reserved_at_60[0x20];
8456 };
8457
8458 struct mlx5_ifc_dealloc_pd_out_bits {
8459         u8         status[0x8];
8460         u8         reserved_at_8[0x18];
8461
8462         u8         syndrome[0x20];
8463
8464         u8         reserved_at_40[0x40];
8465 };
8466
8467 struct mlx5_ifc_dealloc_pd_in_bits {
8468         u8         opcode[0x10];
8469         u8         uid[0x10];
8470
8471         u8         reserved_at_20[0x10];
8472         u8         op_mod[0x10];
8473
8474         u8         reserved_at_40[0x8];
8475         u8         pd[0x18];
8476
8477         u8         reserved_at_60[0x20];
8478 };
8479
8480 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8481         u8         status[0x8];
8482         u8         reserved_at_8[0x18];
8483
8484         u8         syndrome[0x20];
8485
8486         u8         reserved_at_40[0x40];
8487 };
8488
8489 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8490         u8         opcode[0x10];
8491         u8         reserved_at_10[0x10];
8492
8493         u8         reserved_at_20[0x10];
8494         u8         op_mod[0x10];
8495
8496         u8         flow_counter_id[0x20];
8497
8498         u8         reserved_at_60[0x20];
8499 };
8500
8501 struct mlx5_ifc_create_xrq_out_bits {
8502         u8         status[0x8];
8503         u8         reserved_at_8[0x18];
8504
8505         u8         syndrome[0x20];
8506
8507         u8         reserved_at_40[0x8];
8508         u8         xrqn[0x18];
8509
8510         u8         reserved_at_60[0x20];
8511 };
8512
8513 struct mlx5_ifc_create_xrq_in_bits {
8514         u8         opcode[0x10];
8515         u8         uid[0x10];
8516
8517         u8         reserved_at_20[0x10];
8518         u8         op_mod[0x10];
8519
8520         u8         reserved_at_40[0x40];
8521
8522         struct mlx5_ifc_xrqc_bits xrq_context;
8523 };
8524
8525 struct mlx5_ifc_create_xrc_srq_out_bits {
8526         u8         status[0x8];
8527         u8         reserved_at_8[0x18];
8528
8529         u8         syndrome[0x20];
8530
8531         u8         reserved_at_40[0x8];
8532         u8         xrc_srqn[0x18];
8533
8534         u8         reserved_at_60[0x20];
8535 };
8536
8537 struct mlx5_ifc_create_xrc_srq_in_bits {
8538         u8         opcode[0x10];
8539         u8         uid[0x10];
8540
8541         u8         reserved_at_20[0x10];
8542         u8         op_mod[0x10];
8543
8544         u8         reserved_at_40[0x40];
8545
8546         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8547
8548         u8         reserved_at_280[0x60];
8549
8550         u8         xrc_srq_umem_valid[0x1];
8551         u8         reserved_at_2e1[0x1f];
8552
8553         u8         reserved_at_300[0x580];
8554
8555         u8         pas[][0x40];
8556 };
8557
8558 struct mlx5_ifc_create_tis_out_bits {
8559         u8         status[0x8];
8560         u8         reserved_at_8[0x18];
8561
8562         u8         syndrome[0x20];
8563
8564         u8         reserved_at_40[0x8];
8565         u8         tisn[0x18];
8566
8567         u8         reserved_at_60[0x20];
8568 };
8569
8570 struct mlx5_ifc_create_tis_in_bits {
8571         u8         opcode[0x10];
8572         u8         uid[0x10];
8573
8574         u8         reserved_at_20[0x10];
8575         u8         op_mod[0x10];
8576
8577         u8         reserved_at_40[0xc0];
8578
8579         struct mlx5_ifc_tisc_bits ctx;
8580 };
8581
8582 struct mlx5_ifc_create_tir_out_bits {
8583         u8         status[0x8];
8584         u8         icm_address_63_40[0x18];
8585
8586         u8         syndrome[0x20];
8587
8588         u8         icm_address_39_32[0x8];
8589         u8         tirn[0x18];
8590
8591         u8         icm_address_31_0[0x20];
8592 };
8593
8594 struct mlx5_ifc_create_tir_in_bits {
8595         u8         opcode[0x10];
8596         u8         uid[0x10];
8597
8598         u8         reserved_at_20[0x10];
8599         u8         op_mod[0x10];
8600
8601         u8         reserved_at_40[0xc0];
8602
8603         struct mlx5_ifc_tirc_bits ctx;
8604 };
8605
8606 struct mlx5_ifc_create_srq_out_bits {
8607         u8         status[0x8];
8608         u8         reserved_at_8[0x18];
8609
8610         u8         syndrome[0x20];
8611
8612         u8         reserved_at_40[0x8];
8613         u8         srqn[0x18];
8614
8615         u8         reserved_at_60[0x20];
8616 };
8617
8618 struct mlx5_ifc_create_srq_in_bits {
8619         u8         opcode[0x10];
8620         u8         uid[0x10];
8621
8622         u8         reserved_at_20[0x10];
8623         u8         op_mod[0x10];
8624
8625         u8         reserved_at_40[0x40];
8626
8627         struct mlx5_ifc_srqc_bits srq_context_entry;
8628
8629         u8         reserved_at_280[0x600];
8630
8631         u8         pas[][0x40];
8632 };
8633
8634 struct mlx5_ifc_create_sq_out_bits {
8635         u8         status[0x8];
8636         u8         reserved_at_8[0x18];
8637
8638         u8         syndrome[0x20];
8639
8640         u8         reserved_at_40[0x8];
8641         u8         sqn[0x18];
8642
8643         u8         reserved_at_60[0x20];
8644 };
8645
8646 struct mlx5_ifc_create_sq_in_bits {
8647         u8         opcode[0x10];
8648         u8         uid[0x10];
8649
8650         u8         reserved_at_20[0x10];
8651         u8         op_mod[0x10];
8652
8653         u8         reserved_at_40[0xc0];
8654
8655         struct mlx5_ifc_sqc_bits ctx;
8656 };
8657
8658 struct mlx5_ifc_create_scheduling_element_out_bits {
8659         u8         status[0x8];
8660         u8         reserved_at_8[0x18];
8661
8662         u8         syndrome[0x20];
8663
8664         u8         reserved_at_40[0x40];
8665
8666         u8         scheduling_element_id[0x20];
8667
8668         u8         reserved_at_a0[0x160];
8669 };
8670
8671 struct mlx5_ifc_create_scheduling_element_in_bits {
8672         u8         opcode[0x10];
8673         u8         reserved_at_10[0x10];
8674
8675         u8         reserved_at_20[0x10];
8676         u8         op_mod[0x10];
8677
8678         u8         scheduling_hierarchy[0x8];
8679         u8         reserved_at_48[0x18];
8680
8681         u8         reserved_at_60[0xa0];
8682
8683         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8684
8685         u8         reserved_at_300[0x100];
8686 };
8687
8688 struct mlx5_ifc_create_rqt_out_bits {
8689         u8         status[0x8];
8690         u8         reserved_at_8[0x18];
8691
8692         u8         syndrome[0x20];
8693
8694         u8         reserved_at_40[0x8];
8695         u8         rqtn[0x18];
8696
8697         u8         reserved_at_60[0x20];
8698 };
8699
8700 struct mlx5_ifc_create_rqt_in_bits {
8701         u8         opcode[0x10];
8702         u8         uid[0x10];
8703
8704         u8         reserved_at_20[0x10];
8705         u8         op_mod[0x10];
8706
8707         u8         reserved_at_40[0xc0];
8708
8709         struct mlx5_ifc_rqtc_bits rqt_context;
8710 };
8711
8712 struct mlx5_ifc_create_rq_out_bits {
8713         u8         status[0x8];
8714         u8         reserved_at_8[0x18];
8715
8716         u8         syndrome[0x20];
8717
8718         u8         reserved_at_40[0x8];
8719         u8         rqn[0x18];
8720
8721         u8         reserved_at_60[0x20];
8722 };
8723
8724 struct mlx5_ifc_create_rq_in_bits {
8725         u8         opcode[0x10];
8726         u8         uid[0x10];
8727
8728         u8         reserved_at_20[0x10];
8729         u8         op_mod[0x10];
8730
8731         u8         reserved_at_40[0xc0];
8732
8733         struct mlx5_ifc_rqc_bits ctx;
8734 };
8735
8736 struct mlx5_ifc_create_rmp_out_bits {
8737         u8         status[0x8];
8738         u8         reserved_at_8[0x18];
8739
8740         u8         syndrome[0x20];
8741
8742         u8         reserved_at_40[0x8];
8743         u8         rmpn[0x18];
8744
8745         u8         reserved_at_60[0x20];
8746 };
8747
8748 struct mlx5_ifc_create_rmp_in_bits {
8749         u8         opcode[0x10];
8750         u8         uid[0x10];
8751
8752         u8         reserved_at_20[0x10];
8753         u8         op_mod[0x10];
8754
8755         u8         reserved_at_40[0xc0];
8756
8757         struct mlx5_ifc_rmpc_bits ctx;
8758 };
8759
8760 struct mlx5_ifc_create_qp_out_bits {
8761         u8         status[0x8];
8762         u8         reserved_at_8[0x18];
8763
8764         u8         syndrome[0x20];
8765
8766         u8         reserved_at_40[0x8];
8767         u8         qpn[0x18];
8768
8769         u8         ece[0x20];
8770 };
8771
8772 struct mlx5_ifc_create_qp_in_bits {
8773         u8         opcode[0x10];
8774         u8         uid[0x10];
8775
8776         u8         reserved_at_20[0x10];
8777         u8         op_mod[0x10];
8778
8779         u8         qpc_ext[0x1];
8780         u8         reserved_at_41[0x7];
8781         u8         input_qpn[0x18];
8782
8783         u8         reserved_at_60[0x20];
8784         u8         opt_param_mask[0x20];
8785
8786         u8         ece[0x20];
8787
8788         struct mlx5_ifc_qpc_bits qpc;
8789
8790         u8         reserved_at_800[0x60];
8791
8792         u8         wq_umem_valid[0x1];
8793         u8         reserved_at_861[0x1f];
8794
8795         u8         pas[][0x40];
8796 };
8797
8798 struct mlx5_ifc_create_psv_out_bits {
8799         u8         status[0x8];
8800         u8         reserved_at_8[0x18];
8801
8802         u8         syndrome[0x20];
8803
8804         u8         reserved_at_40[0x40];
8805
8806         u8         reserved_at_80[0x8];
8807         u8         psv0_index[0x18];
8808
8809         u8         reserved_at_a0[0x8];
8810         u8         psv1_index[0x18];
8811
8812         u8         reserved_at_c0[0x8];
8813         u8         psv2_index[0x18];
8814
8815         u8         reserved_at_e0[0x8];
8816         u8         psv3_index[0x18];
8817 };
8818
8819 struct mlx5_ifc_create_psv_in_bits {
8820         u8         opcode[0x10];
8821         u8         reserved_at_10[0x10];
8822
8823         u8         reserved_at_20[0x10];
8824         u8         op_mod[0x10];
8825
8826         u8         num_psv[0x4];
8827         u8         reserved_at_44[0x4];
8828         u8         pd[0x18];
8829
8830         u8         reserved_at_60[0x20];
8831 };
8832
8833 struct mlx5_ifc_create_mkey_out_bits {
8834         u8         status[0x8];
8835         u8         reserved_at_8[0x18];
8836
8837         u8         syndrome[0x20];
8838
8839         u8         reserved_at_40[0x8];
8840         u8         mkey_index[0x18];
8841
8842         u8         reserved_at_60[0x20];
8843 };
8844
8845 struct mlx5_ifc_create_mkey_in_bits {
8846         u8         opcode[0x10];
8847         u8         uid[0x10];
8848
8849         u8         reserved_at_20[0x10];
8850         u8         op_mod[0x10];
8851
8852         u8         reserved_at_40[0x20];
8853
8854         u8         pg_access[0x1];
8855         u8         mkey_umem_valid[0x1];
8856         u8         reserved_at_62[0x1e];
8857
8858         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8859
8860         u8         reserved_at_280[0x80];
8861
8862         u8         translations_octword_actual_size[0x20];
8863
8864         u8         reserved_at_320[0x560];
8865
8866         u8         klm_pas_mtt[][0x20];
8867 };
8868
8869 enum {
8870         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8871         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8872         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8873         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8874         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8875         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8876         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8877 };
8878
8879 struct mlx5_ifc_create_flow_table_out_bits {
8880         u8         status[0x8];
8881         u8         icm_address_63_40[0x18];
8882
8883         u8         syndrome[0x20];
8884
8885         u8         icm_address_39_32[0x8];
8886         u8         table_id[0x18];
8887
8888         u8         icm_address_31_0[0x20];
8889 };
8890
8891 struct mlx5_ifc_create_flow_table_in_bits {
8892         u8         opcode[0x10];
8893         u8         uid[0x10];
8894
8895         u8         reserved_at_20[0x10];
8896         u8         op_mod[0x10];
8897
8898         u8         other_vport[0x1];
8899         u8         reserved_at_41[0xf];
8900         u8         vport_number[0x10];
8901
8902         u8         reserved_at_60[0x20];
8903
8904         u8         table_type[0x8];
8905         u8         reserved_at_88[0x18];
8906
8907         u8         reserved_at_a0[0x20];
8908
8909         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8910 };
8911
8912 struct mlx5_ifc_create_flow_group_out_bits {
8913         u8         status[0x8];
8914         u8         reserved_at_8[0x18];
8915
8916         u8         syndrome[0x20];
8917
8918         u8         reserved_at_40[0x8];
8919         u8         group_id[0x18];
8920
8921         u8         reserved_at_60[0x20];
8922 };
8923
8924 enum {
8925         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8926         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8927 };
8928
8929 enum {
8930         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8931         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8932         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8933         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8934 };
8935
8936 struct mlx5_ifc_create_flow_group_in_bits {
8937         u8         opcode[0x10];
8938         u8         reserved_at_10[0x10];
8939
8940         u8         reserved_at_20[0x10];
8941         u8         op_mod[0x10];
8942
8943         u8         other_vport[0x1];
8944         u8         reserved_at_41[0xf];
8945         u8         vport_number[0x10];
8946
8947         u8         reserved_at_60[0x20];
8948
8949         u8         table_type[0x8];
8950         u8         reserved_at_88[0x4];
8951         u8         group_type[0x4];
8952         u8         reserved_at_90[0x10];
8953
8954         u8         reserved_at_a0[0x8];
8955         u8         table_id[0x18];
8956
8957         u8         source_eswitch_owner_vhca_id_valid[0x1];
8958
8959         u8         reserved_at_c1[0x1f];
8960
8961         u8         start_flow_index[0x20];
8962
8963         u8         reserved_at_100[0x20];
8964
8965         u8         end_flow_index[0x20];
8966
8967         u8         reserved_at_140[0x10];
8968         u8         match_definer_id[0x10];
8969
8970         u8         reserved_at_160[0x80];
8971
8972         u8         reserved_at_1e0[0x18];
8973         u8         match_criteria_enable[0x8];
8974
8975         struct mlx5_ifc_fte_match_param_bits match_criteria;
8976
8977         u8         reserved_at_1200[0xe00];
8978 };
8979
8980 struct mlx5_ifc_create_eq_out_bits {
8981         u8         status[0x8];
8982         u8         reserved_at_8[0x18];
8983
8984         u8         syndrome[0x20];
8985
8986         u8         reserved_at_40[0x18];
8987         u8         eq_number[0x8];
8988
8989         u8         reserved_at_60[0x20];
8990 };
8991
8992 struct mlx5_ifc_create_eq_in_bits {
8993         u8         opcode[0x10];
8994         u8         uid[0x10];
8995
8996         u8         reserved_at_20[0x10];
8997         u8         op_mod[0x10];
8998
8999         u8         reserved_at_40[0x40];
9000
9001         struct mlx5_ifc_eqc_bits eq_context_entry;
9002
9003         u8         reserved_at_280[0x40];
9004
9005         u8         event_bitmask[4][0x40];
9006
9007         u8         reserved_at_3c0[0x4c0];
9008
9009         u8         pas[][0x40];
9010 };
9011
9012 struct mlx5_ifc_create_dct_out_bits {
9013         u8         status[0x8];
9014         u8         reserved_at_8[0x18];
9015
9016         u8         syndrome[0x20];
9017
9018         u8         reserved_at_40[0x8];
9019         u8         dctn[0x18];
9020
9021         u8         ece[0x20];
9022 };
9023
9024 struct mlx5_ifc_create_dct_in_bits {
9025         u8         opcode[0x10];
9026         u8         uid[0x10];
9027
9028         u8         reserved_at_20[0x10];
9029         u8         op_mod[0x10];
9030
9031         u8         reserved_at_40[0x40];
9032
9033         struct mlx5_ifc_dctc_bits dct_context_entry;
9034
9035         u8         reserved_at_280[0x180];
9036 };
9037
9038 struct mlx5_ifc_create_cq_out_bits {
9039         u8         status[0x8];
9040         u8         reserved_at_8[0x18];
9041
9042         u8         syndrome[0x20];
9043
9044         u8         reserved_at_40[0x8];
9045         u8         cqn[0x18];
9046
9047         u8         reserved_at_60[0x20];
9048 };
9049
9050 struct mlx5_ifc_create_cq_in_bits {
9051         u8         opcode[0x10];
9052         u8         uid[0x10];
9053
9054         u8         reserved_at_20[0x10];
9055         u8         op_mod[0x10];
9056
9057         u8         reserved_at_40[0x40];
9058
9059         struct mlx5_ifc_cqc_bits cq_context;
9060
9061         u8         reserved_at_280[0x60];
9062
9063         u8         cq_umem_valid[0x1];
9064         u8         reserved_at_2e1[0x59f];
9065
9066         u8         pas[][0x40];
9067 };
9068
9069 struct mlx5_ifc_config_int_moderation_out_bits {
9070         u8         status[0x8];
9071         u8         reserved_at_8[0x18];
9072
9073         u8         syndrome[0x20];
9074
9075         u8         reserved_at_40[0x4];
9076         u8         min_delay[0xc];
9077         u8         int_vector[0x10];
9078
9079         u8         reserved_at_60[0x20];
9080 };
9081
9082 enum {
9083         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9084         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9085 };
9086
9087 struct mlx5_ifc_config_int_moderation_in_bits {
9088         u8         opcode[0x10];
9089         u8         reserved_at_10[0x10];
9090
9091         u8         reserved_at_20[0x10];
9092         u8         op_mod[0x10];
9093
9094         u8         reserved_at_40[0x4];
9095         u8         min_delay[0xc];
9096         u8         int_vector[0x10];
9097
9098         u8         reserved_at_60[0x20];
9099 };
9100
9101 struct mlx5_ifc_attach_to_mcg_out_bits {
9102         u8         status[0x8];
9103         u8         reserved_at_8[0x18];
9104
9105         u8         syndrome[0x20];
9106
9107         u8         reserved_at_40[0x40];
9108 };
9109
9110 struct mlx5_ifc_attach_to_mcg_in_bits {
9111         u8         opcode[0x10];
9112         u8         uid[0x10];
9113
9114         u8         reserved_at_20[0x10];
9115         u8         op_mod[0x10];
9116
9117         u8         reserved_at_40[0x8];
9118         u8         qpn[0x18];
9119
9120         u8         reserved_at_60[0x20];
9121
9122         u8         multicast_gid[16][0x8];
9123 };
9124
9125 struct mlx5_ifc_arm_xrq_out_bits {
9126         u8         status[0x8];
9127         u8         reserved_at_8[0x18];
9128
9129         u8         syndrome[0x20];
9130
9131         u8         reserved_at_40[0x40];
9132 };
9133
9134 struct mlx5_ifc_arm_xrq_in_bits {
9135         u8         opcode[0x10];
9136         u8         reserved_at_10[0x10];
9137
9138         u8         reserved_at_20[0x10];
9139         u8         op_mod[0x10];
9140
9141         u8         reserved_at_40[0x8];
9142         u8         xrqn[0x18];
9143
9144         u8         reserved_at_60[0x10];
9145         u8         lwm[0x10];
9146 };
9147
9148 struct mlx5_ifc_arm_xrc_srq_out_bits {
9149         u8         status[0x8];
9150         u8         reserved_at_8[0x18];
9151
9152         u8         syndrome[0x20];
9153
9154         u8         reserved_at_40[0x40];
9155 };
9156
9157 enum {
9158         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9159 };
9160
9161 struct mlx5_ifc_arm_xrc_srq_in_bits {
9162         u8         opcode[0x10];
9163         u8         uid[0x10];
9164
9165         u8         reserved_at_20[0x10];
9166         u8         op_mod[0x10];
9167
9168         u8         reserved_at_40[0x8];
9169         u8         xrc_srqn[0x18];
9170
9171         u8         reserved_at_60[0x10];
9172         u8         lwm[0x10];
9173 };
9174
9175 struct mlx5_ifc_arm_rq_out_bits {
9176         u8         status[0x8];
9177         u8         reserved_at_8[0x18];
9178
9179         u8         syndrome[0x20];
9180
9181         u8         reserved_at_40[0x40];
9182 };
9183
9184 enum {
9185         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9186         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9187 };
9188
9189 struct mlx5_ifc_arm_rq_in_bits {
9190         u8         opcode[0x10];
9191         u8         uid[0x10];
9192
9193         u8         reserved_at_20[0x10];
9194         u8         op_mod[0x10];
9195
9196         u8         reserved_at_40[0x8];
9197         u8         srq_number[0x18];
9198
9199         u8         reserved_at_60[0x10];
9200         u8         lwm[0x10];
9201 };
9202
9203 struct mlx5_ifc_arm_dct_out_bits {
9204         u8         status[0x8];
9205         u8         reserved_at_8[0x18];
9206
9207         u8         syndrome[0x20];
9208
9209         u8         reserved_at_40[0x40];
9210 };
9211
9212 struct mlx5_ifc_arm_dct_in_bits {
9213         u8         opcode[0x10];
9214         u8         reserved_at_10[0x10];
9215
9216         u8         reserved_at_20[0x10];
9217         u8         op_mod[0x10];
9218
9219         u8         reserved_at_40[0x8];
9220         u8         dct_number[0x18];
9221
9222         u8         reserved_at_60[0x20];
9223 };
9224
9225 struct mlx5_ifc_alloc_xrcd_out_bits {
9226         u8         status[0x8];
9227         u8         reserved_at_8[0x18];
9228
9229         u8         syndrome[0x20];
9230
9231         u8         reserved_at_40[0x8];
9232         u8         xrcd[0x18];
9233
9234         u8         reserved_at_60[0x20];
9235 };
9236
9237 struct mlx5_ifc_alloc_xrcd_in_bits {
9238         u8         opcode[0x10];
9239         u8         uid[0x10];
9240
9241         u8         reserved_at_20[0x10];
9242         u8         op_mod[0x10];
9243
9244         u8         reserved_at_40[0x40];
9245 };
9246
9247 struct mlx5_ifc_alloc_uar_out_bits {
9248         u8         status[0x8];
9249         u8         reserved_at_8[0x18];
9250
9251         u8         syndrome[0x20];
9252
9253         u8         reserved_at_40[0x8];
9254         u8         uar[0x18];
9255
9256         u8         reserved_at_60[0x20];
9257 };
9258
9259 struct mlx5_ifc_alloc_uar_in_bits {
9260         u8         opcode[0x10];
9261         u8         uid[0x10];
9262
9263         u8         reserved_at_20[0x10];
9264         u8         op_mod[0x10];
9265
9266         u8         reserved_at_40[0x40];
9267 };
9268
9269 struct mlx5_ifc_alloc_transport_domain_out_bits {
9270         u8         status[0x8];
9271         u8         reserved_at_8[0x18];
9272
9273         u8         syndrome[0x20];
9274
9275         u8         reserved_at_40[0x8];
9276         u8         transport_domain[0x18];
9277
9278         u8         reserved_at_60[0x20];
9279 };
9280
9281 struct mlx5_ifc_alloc_transport_domain_in_bits {
9282         u8         opcode[0x10];
9283         u8         uid[0x10];
9284
9285         u8         reserved_at_20[0x10];
9286         u8         op_mod[0x10];
9287
9288         u8         reserved_at_40[0x40];
9289 };
9290
9291 struct mlx5_ifc_alloc_q_counter_out_bits {
9292         u8         status[0x8];
9293         u8         reserved_at_8[0x18];
9294
9295         u8         syndrome[0x20];
9296
9297         u8         reserved_at_40[0x18];
9298         u8         counter_set_id[0x8];
9299
9300         u8         reserved_at_60[0x20];
9301 };
9302
9303 struct mlx5_ifc_alloc_q_counter_in_bits {
9304         u8         opcode[0x10];
9305         u8         uid[0x10];
9306
9307         u8         reserved_at_20[0x10];
9308         u8         op_mod[0x10];
9309
9310         u8         reserved_at_40[0x40];
9311 };
9312
9313 struct mlx5_ifc_alloc_pd_out_bits {
9314         u8         status[0x8];
9315         u8         reserved_at_8[0x18];
9316
9317         u8         syndrome[0x20];
9318
9319         u8         reserved_at_40[0x8];
9320         u8         pd[0x18];
9321
9322         u8         reserved_at_60[0x20];
9323 };
9324
9325 struct mlx5_ifc_alloc_pd_in_bits {
9326         u8         opcode[0x10];
9327         u8         uid[0x10];
9328
9329         u8         reserved_at_20[0x10];
9330         u8         op_mod[0x10];
9331
9332         u8         reserved_at_40[0x40];
9333 };
9334
9335 struct mlx5_ifc_alloc_flow_counter_out_bits {
9336         u8         status[0x8];
9337         u8         reserved_at_8[0x18];
9338
9339         u8         syndrome[0x20];
9340
9341         u8         flow_counter_id[0x20];
9342
9343         u8         reserved_at_60[0x20];
9344 };
9345
9346 struct mlx5_ifc_alloc_flow_counter_in_bits {
9347         u8         opcode[0x10];
9348         u8         reserved_at_10[0x10];
9349
9350         u8         reserved_at_20[0x10];
9351         u8         op_mod[0x10];
9352
9353         u8         reserved_at_40[0x33];
9354         u8         flow_counter_bulk_log_size[0x5];
9355         u8         flow_counter_bulk[0x8];
9356 };
9357
9358 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9359         u8         status[0x8];
9360         u8         reserved_at_8[0x18];
9361
9362         u8         syndrome[0x20];
9363
9364         u8         reserved_at_40[0x40];
9365 };
9366
9367 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9368         u8         opcode[0x10];
9369         u8         reserved_at_10[0x10];
9370
9371         u8         reserved_at_20[0x10];
9372         u8         op_mod[0x10];
9373
9374         u8         reserved_at_40[0x20];
9375
9376         u8         reserved_at_60[0x10];
9377         u8         vxlan_udp_port[0x10];
9378 };
9379
9380 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9381         u8         status[0x8];
9382         u8         reserved_at_8[0x18];
9383
9384         u8         syndrome[0x20];
9385
9386         u8         reserved_at_40[0x40];
9387 };
9388
9389 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9390         u8         rate_limit[0x20];
9391
9392         u8         burst_upper_bound[0x20];
9393
9394         u8         reserved_at_40[0x10];
9395         u8         typical_packet_size[0x10];
9396
9397         u8         reserved_at_60[0x120];
9398 };
9399
9400 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9401         u8         opcode[0x10];
9402         u8         uid[0x10];
9403
9404         u8         reserved_at_20[0x10];
9405         u8         op_mod[0x10];
9406
9407         u8         reserved_at_40[0x10];
9408         u8         rate_limit_index[0x10];
9409
9410         u8         reserved_at_60[0x20];
9411
9412         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9413 };
9414
9415 struct mlx5_ifc_access_register_out_bits {
9416         u8         status[0x8];
9417         u8         reserved_at_8[0x18];
9418
9419         u8         syndrome[0x20];
9420
9421         u8         reserved_at_40[0x40];
9422
9423         u8         register_data[][0x20];
9424 };
9425
9426 enum {
9427         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9428         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9429 };
9430
9431 struct mlx5_ifc_access_register_in_bits {
9432         u8         opcode[0x10];
9433         u8         reserved_at_10[0x10];
9434
9435         u8         reserved_at_20[0x10];
9436         u8         op_mod[0x10];
9437
9438         u8         reserved_at_40[0x10];
9439         u8         register_id[0x10];
9440
9441         u8         argument[0x20];
9442
9443         u8         register_data[][0x20];
9444 };
9445
9446 struct mlx5_ifc_sltp_reg_bits {
9447         u8         status[0x4];
9448         u8         version[0x4];
9449         u8         local_port[0x8];
9450         u8         pnat[0x2];
9451         u8         reserved_at_12[0x2];
9452         u8         lane[0x4];
9453         u8         reserved_at_18[0x8];
9454
9455         u8         reserved_at_20[0x20];
9456
9457         u8         reserved_at_40[0x7];
9458         u8         polarity[0x1];
9459         u8         ob_tap0[0x8];
9460         u8         ob_tap1[0x8];
9461         u8         ob_tap2[0x8];
9462
9463         u8         reserved_at_60[0xc];
9464         u8         ob_preemp_mode[0x4];
9465         u8         ob_reg[0x8];
9466         u8         ob_bias[0x8];
9467
9468         u8         reserved_at_80[0x20];
9469 };
9470
9471 struct mlx5_ifc_slrg_reg_bits {
9472         u8         status[0x4];
9473         u8         version[0x4];
9474         u8         local_port[0x8];
9475         u8         pnat[0x2];
9476         u8         reserved_at_12[0x2];
9477         u8         lane[0x4];
9478         u8         reserved_at_18[0x8];
9479
9480         u8         time_to_link_up[0x10];
9481         u8         reserved_at_30[0xc];
9482         u8         grade_lane_speed[0x4];
9483
9484         u8         grade_version[0x8];
9485         u8         grade[0x18];
9486
9487         u8         reserved_at_60[0x4];
9488         u8         height_grade_type[0x4];
9489         u8         height_grade[0x18];
9490
9491         u8         height_dz[0x10];
9492         u8         height_dv[0x10];
9493
9494         u8         reserved_at_a0[0x10];
9495         u8         height_sigma[0x10];
9496
9497         u8         reserved_at_c0[0x20];
9498
9499         u8         reserved_at_e0[0x4];
9500         u8         phase_grade_type[0x4];
9501         u8         phase_grade[0x18];
9502
9503         u8         reserved_at_100[0x8];
9504         u8         phase_eo_pos[0x8];
9505         u8         reserved_at_110[0x8];
9506         u8         phase_eo_neg[0x8];
9507
9508         u8         ffe_set_tested[0x10];
9509         u8         test_errors_per_lane[0x10];
9510 };
9511
9512 struct mlx5_ifc_pvlc_reg_bits {
9513         u8         reserved_at_0[0x8];
9514         u8         local_port[0x8];
9515         u8         reserved_at_10[0x10];
9516
9517         u8         reserved_at_20[0x1c];
9518         u8         vl_hw_cap[0x4];
9519
9520         u8         reserved_at_40[0x1c];
9521         u8         vl_admin[0x4];
9522
9523         u8         reserved_at_60[0x1c];
9524         u8         vl_operational[0x4];
9525 };
9526
9527 struct mlx5_ifc_pude_reg_bits {
9528         u8         swid[0x8];
9529         u8         local_port[0x8];
9530         u8         reserved_at_10[0x4];
9531         u8         admin_status[0x4];
9532         u8         reserved_at_18[0x4];
9533         u8         oper_status[0x4];
9534
9535         u8         reserved_at_20[0x60];
9536 };
9537
9538 struct mlx5_ifc_ptys_reg_bits {
9539         u8         reserved_at_0[0x1];
9540         u8         an_disable_admin[0x1];
9541         u8         an_disable_cap[0x1];
9542         u8         reserved_at_3[0x5];
9543         u8         local_port[0x8];
9544         u8         reserved_at_10[0xd];
9545         u8         proto_mask[0x3];
9546
9547         u8         an_status[0x4];
9548         u8         reserved_at_24[0xc];
9549         u8         data_rate_oper[0x10];
9550
9551         u8         ext_eth_proto_capability[0x20];
9552
9553         u8         eth_proto_capability[0x20];
9554
9555         u8         ib_link_width_capability[0x10];
9556         u8         ib_proto_capability[0x10];
9557
9558         u8         ext_eth_proto_admin[0x20];
9559
9560         u8         eth_proto_admin[0x20];
9561
9562         u8         ib_link_width_admin[0x10];
9563         u8         ib_proto_admin[0x10];
9564
9565         u8         ext_eth_proto_oper[0x20];
9566
9567         u8         eth_proto_oper[0x20];
9568
9569         u8         ib_link_width_oper[0x10];
9570         u8         ib_proto_oper[0x10];
9571
9572         u8         reserved_at_160[0x1c];
9573         u8         connector_type[0x4];
9574
9575         u8         eth_proto_lp_advertise[0x20];
9576
9577         u8         reserved_at_1a0[0x60];
9578 };
9579
9580 struct mlx5_ifc_mlcr_reg_bits {
9581         u8         reserved_at_0[0x8];
9582         u8         local_port[0x8];
9583         u8         reserved_at_10[0x20];
9584
9585         u8         beacon_duration[0x10];
9586         u8         reserved_at_40[0x10];
9587
9588         u8         beacon_remain[0x10];
9589 };
9590
9591 struct mlx5_ifc_ptas_reg_bits {
9592         u8         reserved_at_0[0x20];
9593
9594         u8         algorithm_options[0x10];
9595         u8         reserved_at_30[0x4];
9596         u8         repetitions_mode[0x4];
9597         u8         num_of_repetitions[0x8];
9598
9599         u8         grade_version[0x8];
9600         u8         height_grade_type[0x4];
9601         u8         phase_grade_type[0x4];
9602         u8         height_grade_weight[0x8];
9603         u8         phase_grade_weight[0x8];
9604
9605         u8         gisim_measure_bits[0x10];
9606         u8         adaptive_tap_measure_bits[0x10];
9607
9608         u8         ber_bath_high_error_threshold[0x10];
9609         u8         ber_bath_mid_error_threshold[0x10];
9610
9611         u8         ber_bath_low_error_threshold[0x10];
9612         u8         one_ratio_high_threshold[0x10];
9613
9614         u8         one_ratio_high_mid_threshold[0x10];
9615         u8         one_ratio_low_mid_threshold[0x10];
9616
9617         u8         one_ratio_low_threshold[0x10];
9618         u8         ndeo_error_threshold[0x10];
9619
9620         u8         mixer_offset_step_size[0x10];
9621         u8         reserved_at_110[0x8];
9622         u8         mix90_phase_for_voltage_bath[0x8];
9623
9624         u8         mixer_offset_start[0x10];
9625         u8         mixer_offset_end[0x10];
9626
9627         u8         reserved_at_140[0x15];
9628         u8         ber_test_time[0xb];
9629 };
9630
9631 struct mlx5_ifc_pspa_reg_bits {
9632         u8         swid[0x8];
9633         u8         local_port[0x8];
9634         u8         sub_port[0x8];
9635         u8         reserved_at_18[0x8];
9636
9637         u8         reserved_at_20[0x20];
9638 };
9639
9640 struct mlx5_ifc_pqdr_reg_bits {
9641         u8         reserved_at_0[0x8];
9642         u8         local_port[0x8];
9643         u8         reserved_at_10[0x5];
9644         u8         prio[0x3];
9645         u8         reserved_at_18[0x6];
9646         u8         mode[0x2];
9647
9648         u8         reserved_at_20[0x20];
9649
9650         u8         reserved_at_40[0x10];
9651         u8         min_threshold[0x10];
9652
9653         u8         reserved_at_60[0x10];
9654         u8         max_threshold[0x10];
9655
9656         u8         reserved_at_80[0x10];
9657         u8         mark_probability_denominator[0x10];
9658
9659         u8         reserved_at_a0[0x60];
9660 };
9661
9662 struct mlx5_ifc_ppsc_reg_bits {
9663         u8         reserved_at_0[0x8];
9664         u8         local_port[0x8];
9665         u8         reserved_at_10[0x10];
9666
9667         u8         reserved_at_20[0x60];
9668
9669         u8         reserved_at_80[0x1c];
9670         u8         wrps_admin[0x4];
9671
9672         u8         reserved_at_a0[0x1c];
9673         u8         wrps_status[0x4];
9674
9675         u8         reserved_at_c0[0x8];
9676         u8         up_threshold[0x8];
9677         u8         reserved_at_d0[0x8];
9678         u8         down_threshold[0x8];
9679
9680         u8         reserved_at_e0[0x20];
9681
9682         u8         reserved_at_100[0x1c];
9683         u8         srps_admin[0x4];
9684
9685         u8         reserved_at_120[0x1c];
9686         u8         srps_status[0x4];
9687
9688         u8         reserved_at_140[0x40];
9689 };
9690
9691 struct mlx5_ifc_pplr_reg_bits {
9692         u8         reserved_at_0[0x8];
9693         u8         local_port[0x8];
9694         u8         reserved_at_10[0x10];
9695
9696         u8         reserved_at_20[0x8];
9697         u8         lb_cap[0x8];
9698         u8         reserved_at_30[0x8];
9699         u8         lb_en[0x8];
9700 };
9701
9702 struct mlx5_ifc_pplm_reg_bits {
9703         u8         reserved_at_0[0x8];
9704         u8         local_port[0x8];
9705         u8         reserved_at_10[0x10];
9706
9707         u8         reserved_at_20[0x20];
9708
9709         u8         port_profile_mode[0x8];
9710         u8         static_port_profile[0x8];
9711         u8         active_port_profile[0x8];
9712         u8         reserved_at_58[0x8];
9713
9714         u8         retransmission_active[0x8];
9715         u8         fec_mode_active[0x18];
9716
9717         u8         rs_fec_correction_bypass_cap[0x4];
9718         u8         reserved_at_84[0x8];
9719         u8         fec_override_cap_56g[0x4];
9720         u8         fec_override_cap_100g[0x4];
9721         u8         fec_override_cap_50g[0x4];
9722         u8         fec_override_cap_25g[0x4];
9723         u8         fec_override_cap_10g_40g[0x4];
9724
9725         u8         rs_fec_correction_bypass_admin[0x4];
9726         u8         reserved_at_a4[0x8];
9727         u8         fec_override_admin_56g[0x4];
9728         u8         fec_override_admin_100g[0x4];
9729         u8         fec_override_admin_50g[0x4];
9730         u8         fec_override_admin_25g[0x4];
9731         u8         fec_override_admin_10g_40g[0x4];
9732
9733         u8         fec_override_cap_400g_8x[0x10];
9734         u8         fec_override_cap_200g_4x[0x10];
9735
9736         u8         fec_override_cap_100g_2x[0x10];
9737         u8         fec_override_cap_50g_1x[0x10];
9738
9739         u8         fec_override_admin_400g_8x[0x10];
9740         u8         fec_override_admin_200g_4x[0x10];
9741
9742         u8         fec_override_admin_100g_2x[0x10];
9743         u8         fec_override_admin_50g_1x[0x10];
9744
9745         u8         reserved_at_140[0x140];
9746 };
9747
9748 struct mlx5_ifc_ppcnt_reg_bits {
9749         u8         swid[0x8];
9750         u8         local_port[0x8];
9751         u8         pnat[0x2];
9752         u8         reserved_at_12[0x8];
9753         u8         grp[0x6];
9754
9755         u8         clr[0x1];
9756         u8         reserved_at_21[0x1c];
9757         u8         prio_tc[0x3];
9758
9759         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9760 };
9761
9762 struct mlx5_ifc_mpein_reg_bits {
9763         u8         reserved_at_0[0x2];
9764         u8         depth[0x6];
9765         u8         pcie_index[0x8];
9766         u8         node[0x8];
9767         u8         reserved_at_18[0x8];
9768
9769         u8         capability_mask[0x20];
9770
9771         u8         reserved_at_40[0x8];
9772         u8         link_width_enabled[0x8];
9773         u8         link_speed_enabled[0x10];
9774
9775         u8         lane0_physical_position[0x8];
9776         u8         link_width_active[0x8];
9777         u8         link_speed_active[0x10];
9778
9779         u8         num_of_pfs[0x10];
9780         u8         num_of_vfs[0x10];
9781
9782         u8         bdf0[0x10];
9783         u8         reserved_at_b0[0x10];
9784
9785         u8         max_read_request_size[0x4];
9786         u8         max_payload_size[0x4];
9787         u8         reserved_at_c8[0x5];
9788         u8         pwr_status[0x3];
9789         u8         port_type[0x4];
9790         u8         reserved_at_d4[0xb];
9791         u8         lane_reversal[0x1];
9792
9793         u8         reserved_at_e0[0x14];
9794         u8         pci_power[0xc];
9795
9796         u8         reserved_at_100[0x20];
9797
9798         u8         device_status[0x10];
9799         u8         port_state[0x8];
9800         u8         reserved_at_138[0x8];
9801
9802         u8         reserved_at_140[0x10];
9803         u8         receiver_detect_result[0x10];
9804
9805         u8         reserved_at_160[0x20];
9806 };
9807
9808 struct mlx5_ifc_mpcnt_reg_bits {
9809         u8         reserved_at_0[0x8];
9810         u8         pcie_index[0x8];
9811         u8         reserved_at_10[0xa];
9812         u8         grp[0x6];
9813
9814         u8         clr[0x1];
9815         u8         reserved_at_21[0x1f];
9816
9817         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9818 };
9819
9820 struct mlx5_ifc_ppad_reg_bits {
9821         u8         reserved_at_0[0x3];
9822         u8         single_mac[0x1];
9823         u8         reserved_at_4[0x4];
9824         u8         local_port[0x8];
9825         u8         mac_47_32[0x10];
9826
9827         u8         mac_31_0[0x20];
9828
9829         u8         reserved_at_40[0x40];
9830 };
9831
9832 struct mlx5_ifc_pmtu_reg_bits {
9833         u8         reserved_at_0[0x8];
9834         u8         local_port[0x8];
9835         u8         reserved_at_10[0x10];
9836
9837         u8         max_mtu[0x10];
9838         u8         reserved_at_30[0x10];
9839
9840         u8         admin_mtu[0x10];
9841         u8         reserved_at_50[0x10];
9842
9843         u8         oper_mtu[0x10];
9844         u8         reserved_at_70[0x10];
9845 };
9846
9847 struct mlx5_ifc_pmpr_reg_bits {
9848         u8         reserved_at_0[0x8];
9849         u8         module[0x8];
9850         u8         reserved_at_10[0x10];
9851
9852         u8         reserved_at_20[0x18];
9853         u8         attenuation_5g[0x8];
9854
9855         u8         reserved_at_40[0x18];
9856         u8         attenuation_7g[0x8];
9857
9858         u8         reserved_at_60[0x18];
9859         u8         attenuation_12g[0x8];
9860 };
9861
9862 struct mlx5_ifc_pmpe_reg_bits {
9863         u8         reserved_at_0[0x8];
9864         u8         module[0x8];
9865         u8         reserved_at_10[0xc];
9866         u8         module_status[0x4];
9867
9868         u8         reserved_at_20[0x60];
9869 };
9870
9871 struct mlx5_ifc_pmpc_reg_bits {
9872         u8         module_state_updated[32][0x8];
9873 };
9874
9875 struct mlx5_ifc_pmlpn_reg_bits {
9876         u8         reserved_at_0[0x4];
9877         u8         mlpn_status[0x4];
9878         u8         local_port[0x8];
9879         u8         reserved_at_10[0x10];
9880
9881         u8         e[0x1];
9882         u8         reserved_at_21[0x1f];
9883 };
9884
9885 struct mlx5_ifc_pmlp_reg_bits {
9886         u8         rxtx[0x1];
9887         u8         reserved_at_1[0x7];
9888         u8         local_port[0x8];
9889         u8         reserved_at_10[0x8];
9890         u8         width[0x8];
9891
9892         u8         lane0_module_mapping[0x20];
9893
9894         u8         lane1_module_mapping[0x20];
9895
9896         u8         lane2_module_mapping[0x20];
9897
9898         u8         lane3_module_mapping[0x20];
9899
9900         u8         reserved_at_a0[0x160];
9901 };
9902
9903 struct mlx5_ifc_pmaos_reg_bits {
9904         u8         reserved_at_0[0x8];
9905         u8         module[0x8];
9906         u8         reserved_at_10[0x4];
9907         u8         admin_status[0x4];
9908         u8         reserved_at_18[0x4];
9909         u8         oper_status[0x4];
9910
9911         u8         ase[0x1];
9912         u8         ee[0x1];
9913         u8         reserved_at_22[0x1c];
9914         u8         e[0x2];
9915
9916         u8         reserved_at_40[0x40];
9917 };
9918
9919 struct mlx5_ifc_plpc_reg_bits {
9920         u8         reserved_at_0[0x4];
9921         u8         profile_id[0xc];
9922         u8         reserved_at_10[0x4];
9923         u8         proto_mask[0x4];
9924         u8         reserved_at_18[0x8];
9925
9926         u8         reserved_at_20[0x10];
9927         u8         lane_speed[0x10];
9928
9929         u8         reserved_at_40[0x17];
9930         u8         lpbf[0x1];
9931         u8         fec_mode_policy[0x8];
9932
9933         u8         retransmission_capability[0x8];
9934         u8         fec_mode_capability[0x18];
9935
9936         u8         retransmission_support_admin[0x8];
9937         u8         fec_mode_support_admin[0x18];
9938
9939         u8         retransmission_request_admin[0x8];
9940         u8         fec_mode_request_admin[0x18];
9941
9942         u8         reserved_at_c0[0x80];
9943 };
9944
9945 struct mlx5_ifc_plib_reg_bits {
9946         u8         reserved_at_0[0x8];
9947         u8         local_port[0x8];
9948         u8         reserved_at_10[0x8];
9949         u8         ib_port[0x8];
9950
9951         u8         reserved_at_20[0x60];
9952 };
9953
9954 struct mlx5_ifc_plbf_reg_bits {
9955         u8         reserved_at_0[0x8];
9956         u8         local_port[0x8];
9957         u8         reserved_at_10[0xd];
9958         u8         lbf_mode[0x3];
9959
9960         u8         reserved_at_20[0x20];
9961 };
9962
9963 struct mlx5_ifc_pipg_reg_bits {
9964         u8         reserved_at_0[0x8];
9965         u8         local_port[0x8];
9966         u8         reserved_at_10[0x10];
9967
9968         u8         dic[0x1];
9969         u8         reserved_at_21[0x19];
9970         u8         ipg[0x4];
9971         u8         reserved_at_3e[0x2];
9972 };
9973
9974 struct mlx5_ifc_pifr_reg_bits {
9975         u8         reserved_at_0[0x8];
9976         u8         local_port[0x8];
9977         u8         reserved_at_10[0x10];
9978
9979         u8         reserved_at_20[0xe0];
9980
9981         u8         port_filter[8][0x20];
9982
9983         u8         port_filter_update_en[8][0x20];
9984 };
9985
9986 struct mlx5_ifc_pfcc_reg_bits {
9987         u8         reserved_at_0[0x8];
9988         u8         local_port[0x8];
9989         u8         reserved_at_10[0xb];
9990         u8         ppan_mask_n[0x1];
9991         u8         minor_stall_mask[0x1];
9992         u8         critical_stall_mask[0x1];
9993         u8         reserved_at_1e[0x2];
9994
9995         u8         ppan[0x4];
9996         u8         reserved_at_24[0x4];
9997         u8         prio_mask_tx[0x8];
9998         u8         reserved_at_30[0x8];
9999         u8         prio_mask_rx[0x8];
10000
10001         u8         pptx[0x1];
10002         u8         aptx[0x1];
10003         u8         pptx_mask_n[0x1];
10004         u8         reserved_at_43[0x5];
10005         u8         pfctx[0x8];
10006         u8         reserved_at_50[0x10];
10007
10008         u8         pprx[0x1];
10009         u8         aprx[0x1];
10010         u8         pprx_mask_n[0x1];
10011         u8         reserved_at_63[0x5];
10012         u8         pfcrx[0x8];
10013         u8         reserved_at_70[0x10];
10014
10015         u8         device_stall_minor_watermark[0x10];
10016         u8         device_stall_critical_watermark[0x10];
10017
10018         u8         reserved_at_a0[0x60];
10019 };
10020
10021 struct mlx5_ifc_pelc_reg_bits {
10022         u8         op[0x4];
10023         u8         reserved_at_4[0x4];
10024         u8         local_port[0x8];
10025         u8         reserved_at_10[0x10];
10026
10027         u8         op_admin[0x8];
10028         u8         op_capability[0x8];
10029         u8         op_request[0x8];
10030         u8         op_active[0x8];
10031
10032         u8         admin[0x40];
10033
10034         u8         capability[0x40];
10035
10036         u8         request[0x40];
10037
10038         u8         active[0x40];
10039
10040         u8         reserved_at_140[0x80];
10041 };
10042
10043 struct mlx5_ifc_peir_reg_bits {
10044         u8         reserved_at_0[0x8];
10045         u8         local_port[0x8];
10046         u8         reserved_at_10[0x10];
10047
10048         u8         reserved_at_20[0xc];
10049         u8         error_count[0x4];
10050         u8         reserved_at_30[0x10];
10051
10052         u8         reserved_at_40[0xc];
10053         u8         lane[0x4];
10054         u8         reserved_at_50[0x8];
10055         u8         error_type[0x8];
10056 };
10057
10058 struct mlx5_ifc_mpegc_reg_bits {
10059         u8         reserved_at_0[0x30];
10060         u8         field_select[0x10];
10061
10062         u8         tx_overflow_sense[0x1];
10063         u8         mark_cqe[0x1];
10064         u8         mark_cnp[0x1];
10065         u8         reserved_at_43[0x1b];
10066         u8         tx_lossy_overflow_oper[0x2];
10067
10068         u8         reserved_at_60[0x100];
10069 };
10070
10071 enum {
10072         MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10073         MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10074 };
10075
10076 enum {
10077         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10078         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10079         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10080 };
10081
10082 struct mlx5_ifc_mtutc_reg_bits {
10083         u8         reserved_at_0[0x5];
10084         u8         freq_adj_units[0x3];
10085         u8         reserved_at_8[0x14];
10086         u8         operation[0x4];
10087
10088         u8         freq_adjustment[0x20];
10089
10090         u8         reserved_at_40[0x40];
10091
10092         u8         utc_sec[0x20];
10093
10094         u8         reserved_at_a0[0x2];
10095         u8         utc_nsec[0x1e];
10096
10097         u8         time_adjustment[0x20];
10098 };
10099
10100 struct mlx5_ifc_pcam_enhanced_features_bits {
10101         u8         reserved_at_0[0x68];
10102         u8         fec_50G_per_lane_in_pplm[0x1];
10103         u8         reserved_at_69[0x4];
10104         u8         rx_icrc_encapsulated_counter[0x1];
10105         u8         reserved_at_6e[0x4];
10106         u8         ptys_extended_ethernet[0x1];
10107         u8         reserved_at_73[0x3];
10108         u8         pfcc_mask[0x1];
10109         u8         reserved_at_77[0x3];
10110         u8         per_lane_error_counters[0x1];
10111         u8         rx_buffer_fullness_counters[0x1];
10112         u8         ptys_connector_type[0x1];
10113         u8         reserved_at_7d[0x1];
10114         u8         ppcnt_discard_group[0x1];
10115         u8         ppcnt_statistical_group[0x1];
10116 };
10117
10118 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10119         u8         port_access_reg_cap_mask_127_to_96[0x20];
10120         u8         port_access_reg_cap_mask_95_to_64[0x20];
10121
10122         u8         port_access_reg_cap_mask_63_to_36[0x1c];
10123         u8         pplm[0x1];
10124         u8         port_access_reg_cap_mask_34_to_32[0x3];
10125
10126         u8         port_access_reg_cap_mask_31_to_13[0x13];
10127         u8         pbmc[0x1];
10128         u8         pptb[0x1];
10129         u8         port_access_reg_cap_mask_10_to_09[0x2];
10130         u8         ppcnt[0x1];
10131         u8         port_access_reg_cap_mask_07_to_00[0x8];
10132 };
10133
10134 struct mlx5_ifc_pcam_reg_bits {
10135         u8         reserved_at_0[0x8];
10136         u8         feature_group[0x8];
10137         u8         reserved_at_10[0x8];
10138         u8         access_reg_group[0x8];
10139
10140         u8         reserved_at_20[0x20];
10141
10142         union {
10143                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10144                 u8         reserved_at_0[0x80];
10145         } port_access_reg_cap_mask;
10146
10147         u8         reserved_at_c0[0x80];
10148
10149         union {
10150                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10151                 u8         reserved_at_0[0x80];
10152         } feature_cap_mask;
10153
10154         u8         reserved_at_1c0[0xc0];
10155 };
10156
10157 struct mlx5_ifc_mcam_enhanced_features_bits {
10158         u8         reserved_at_0[0x50];
10159         u8         mtutc_freq_adj_units[0x1];
10160         u8         mtutc_time_adjustment_extended_range[0x1];
10161         u8         reserved_at_52[0xb];
10162         u8         mcia_32dwords[0x1];
10163         u8         out_pulse_duration_ns[0x1];
10164         u8         npps_period[0x1];
10165         u8         reserved_at_60[0xa];
10166         u8         reset_state[0x1];
10167         u8         ptpcyc2realtime_modify[0x1];
10168         u8         reserved_at_6c[0x2];
10169         u8         pci_status_and_power[0x1];
10170         u8         reserved_at_6f[0x5];
10171         u8         mark_tx_action_cnp[0x1];
10172         u8         mark_tx_action_cqe[0x1];
10173         u8         dynamic_tx_overflow[0x1];
10174         u8         reserved_at_77[0x4];
10175         u8         pcie_outbound_stalled[0x1];
10176         u8         tx_overflow_buffer_pkt[0x1];
10177         u8         mtpps_enh_out_per_adj[0x1];
10178         u8         mtpps_fs[0x1];
10179         u8         pcie_performance_group[0x1];
10180 };
10181
10182 struct mlx5_ifc_mcam_access_reg_bits {
10183         u8         reserved_at_0[0x1c];
10184         u8         mcda[0x1];
10185         u8         mcc[0x1];
10186         u8         mcqi[0x1];
10187         u8         mcqs[0x1];
10188
10189         u8         regs_95_to_87[0x9];
10190         u8         mpegc[0x1];
10191         u8         mtutc[0x1];
10192         u8         regs_84_to_68[0x11];
10193         u8         tracer_registers[0x4];
10194
10195         u8         regs_63_to_46[0x12];
10196         u8         mrtc[0x1];
10197         u8         regs_44_to_32[0xd];
10198
10199         u8         regs_31_to_0[0x20];
10200 };
10201
10202 struct mlx5_ifc_mcam_access_reg_bits1 {
10203         u8         regs_127_to_96[0x20];
10204
10205         u8         regs_95_to_64[0x20];
10206
10207         u8         regs_63_to_32[0x20];
10208
10209         u8         regs_31_to_0[0x20];
10210 };
10211
10212 struct mlx5_ifc_mcam_access_reg_bits2 {
10213         u8         regs_127_to_99[0x1d];
10214         u8         mirc[0x1];
10215         u8         regs_97_to_96[0x2];
10216
10217         u8         regs_95_to_64[0x20];
10218
10219         u8         regs_63_to_32[0x20];
10220
10221         u8         regs_31_to_0[0x20];
10222 };
10223
10224 struct mlx5_ifc_mcam_reg_bits {
10225         u8         reserved_at_0[0x8];
10226         u8         feature_group[0x8];
10227         u8         reserved_at_10[0x8];
10228         u8         access_reg_group[0x8];
10229
10230         u8         reserved_at_20[0x20];
10231
10232         union {
10233                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
10234                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10235                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10236                 u8         reserved_at_0[0x80];
10237         } mng_access_reg_cap_mask;
10238
10239         u8         reserved_at_c0[0x80];
10240
10241         union {
10242                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10243                 u8         reserved_at_0[0x80];
10244         } mng_feature_cap_mask;
10245
10246         u8         reserved_at_1c0[0x80];
10247 };
10248
10249 struct mlx5_ifc_qcam_access_reg_cap_mask {
10250         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10251         u8         qpdpm[0x1];
10252         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10253         u8         qdpm[0x1];
10254         u8         qpts[0x1];
10255         u8         qcap[0x1];
10256         u8         qcam_access_reg_cap_mask_0[0x1];
10257 };
10258
10259 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10260         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10261         u8         qpts_trust_both[0x1];
10262 };
10263
10264 struct mlx5_ifc_qcam_reg_bits {
10265         u8         reserved_at_0[0x8];
10266         u8         feature_group[0x8];
10267         u8         reserved_at_10[0x8];
10268         u8         access_reg_group[0x8];
10269         u8         reserved_at_20[0x20];
10270
10271         union {
10272                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10273                 u8  reserved_at_0[0x80];
10274         } qos_access_reg_cap_mask;
10275
10276         u8         reserved_at_c0[0x80];
10277
10278         union {
10279                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10280                 u8  reserved_at_0[0x80];
10281         } qos_feature_cap_mask;
10282
10283         u8         reserved_at_1c0[0x80];
10284 };
10285
10286 struct mlx5_ifc_core_dump_reg_bits {
10287         u8         reserved_at_0[0x18];
10288         u8         core_dump_type[0x8];
10289
10290         u8         reserved_at_20[0x30];
10291         u8         vhca_id[0x10];
10292
10293         u8         reserved_at_60[0x8];
10294         u8         qpn[0x18];
10295         u8         reserved_at_80[0x180];
10296 };
10297
10298 struct mlx5_ifc_pcap_reg_bits {
10299         u8         reserved_at_0[0x8];
10300         u8         local_port[0x8];
10301         u8         reserved_at_10[0x10];
10302
10303         u8         port_capability_mask[4][0x20];
10304 };
10305
10306 struct mlx5_ifc_paos_reg_bits {
10307         u8         swid[0x8];
10308         u8         local_port[0x8];
10309         u8         reserved_at_10[0x4];
10310         u8         admin_status[0x4];
10311         u8         reserved_at_18[0x4];
10312         u8         oper_status[0x4];
10313
10314         u8         ase[0x1];
10315         u8         ee[0x1];
10316         u8         reserved_at_22[0x1c];
10317         u8         e[0x2];
10318
10319         u8         reserved_at_40[0x40];
10320 };
10321
10322 struct mlx5_ifc_pamp_reg_bits {
10323         u8         reserved_at_0[0x8];
10324         u8         opamp_group[0x8];
10325         u8         reserved_at_10[0xc];
10326         u8         opamp_group_type[0x4];
10327
10328         u8         start_index[0x10];
10329         u8         reserved_at_30[0x4];
10330         u8         num_of_indices[0xc];
10331
10332         u8         index_data[18][0x10];
10333 };
10334
10335 struct mlx5_ifc_pcmr_reg_bits {
10336         u8         reserved_at_0[0x8];
10337         u8         local_port[0x8];
10338         u8         reserved_at_10[0x10];
10339
10340         u8         entropy_force_cap[0x1];
10341         u8         entropy_calc_cap[0x1];
10342         u8         entropy_gre_calc_cap[0x1];
10343         u8         reserved_at_23[0xf];
10344         u8         rx_ts_over_crc_cap[0x1];
10345         u8         reserved_at_33[0xb];
10346         u8         fcs_cap[0x1];
10347         u8         reserved_at_3f[0x1];
10348
10349         u8         entropy_force[0x1];
10350         u8         entropy_calc[0x1];
10351         u8         entropy_gre_calc[0x1];
10352         u8         reserved_at_43[0xf];
10353         u8         rx_ts_over_crc[0x1];
10354         u8         reserved_at_53[0xb];
10355         u8         fcs_chk[0x1];
10356         u8         reserved_at_5f[0x1];
10357 };
10358
10359 struct mlx5_ifc_lane_2_module_mapping_bits {
10360         u8         reserved_at_0[0x4];
10361         u8         rx_lane[0x4];
10362         u8         reserved_at_8[0x4];
10363         u8         tx_lane[0x4];
10364         u8         reserved_at_10[0x8];
10365         u8         module[0x8];
10366 };
10367
10368 struct mlx5_ifc_bufferx_reg_bits {
10369         u8         reserved_at_0[0x6];
10370         u8         lossy[0x1];
10371         u8         epsb[0x1];
10372         u8         reserved_at_8[0x8];
10373         u8         size[0x10];
10374
10375         u8         xoff_threshold[0x10];
10376         u8         xon_threshold[0x10];
10377 };
10378
10379 struct mlx5_ifc_set_node_in_bits {
10380         u8         node_description[64][0x8];
10381 };
10382
10383 struct mlx5_ifc_register_power_settings_bits {
10384         u8         reserved_at_0[0x18];
10385         u8         power_settings_level[0x8];
10386
10387         u8         reserved_at_20[0x60];
10388 };
10389
10390 struct mlx5_ifc_register_host_endianness_bits {
10391         u8         he[0x1];
10392         u8         reserved_at_1[0x1f];
10393
10394         u8         reserved_at_20[0x60];
10395 };
10396
10397 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10398         u8         reserved_at_0[0x20];
10399
10400         u8         mkey[0x20];
10401
10402         u8         addressh_63_32[0x20];
10403
10404         u8         addressl_31_0[0x20];
10405 };
10406
10407 struct mlx5_ifc_ud_adrs_vector_bits {
10408         u8         dc_key[0x40];
10409
10410         u8         ext[0x1];
10411         u8         reserved_at_41[0x7];
10412         u8         destination_qp_dct[0x18];
10413
10414         u8         static_rate[0x4];
10415         u8         sl_eth_prio[0x4];
10416         u8         fl[0x1];
10417         u8         mlid[0x7];
10418         u8         rlid_udp_sport[0x10];
10419
10420         u8         reserved_at_80[0x20];
10421
10422         u8         rmac_47_16[0x20];
10423
10424         u8         rmac_15_0[0x10];
10425         u8         tclass[0x8];
10426         u8         hop_limit[0x8];
10427
10428         u8         reserved_at_e0[0x1];
10429         u8         grh[0x1];
10430         u8         reserved_at_e2[0x2];
10431         u8         src_addr_index[0x8];
10432         u8         flow_label[0x14];
10433
10434         u8         rgid_rip[16][0x8];
10435 };
10436
10437 struct mlx5_ifc_pages_req_event_bits {
10438         u8         reserved_at_0[0x10];
10439         u8         function_id[0x10];
10440
10441         u8         num_pages[0x20];
10442
10443         u8         reserved_at_40[0xa0];
10444 };
10445
10446 struct mlx5_ifc_eqe_bits {
10447         u8         reserved_at_0[0x8];
10448         u8         event_type[0x8];
10449         u8         reserved_at_10[0x8];
10450         u8         event_sub_type[0x8];
10451
10452         u8         reserved_at_20[0xe0];
10453
10454         union mlx5_ifc_event_auto_bits event_data;
10455
10456         u8         reserved_at_1e0[0x10];
10457         u8         signature[0x8];
10458         u8         reserved_at_1f8[0x7];
10459         u8         owner[0x1];
10460 };
10461
10462 enum {
10463         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10464 };
10465
10466 struct mlx5_ifc_cmd_queue_entry_bits {
10467         u8         type[0x8];
10468         u8         reserved_at_8[0x18];
10469
10470         u8         input_length[0x20];
10471
10472         u8         input_mailbox_pointer_63_32[0x20];
10473
10474         u8         input_mailbox_pointer_31_9[0x17];
10475         u8         reserved_at_77[0x9];
10476
10477         u8         command_input_inline_data[16][0x8];
10478
10479         u8         command_output_inline_data[16][0x8];
10480
10481         u8         output_mailbox_pointer_63_32[0x20];
10482
10483         u8         output_mailbox_pointer_31_9[0x17];
10484         u8         reserved_at_1b7[0x9];
10485
10486         u8         output_length[0x20];
10487
10488         u8         token[0x8];
10489         u8         signature[0x8];
10490         u8         reserved_at_1f0[0x8];
10491         u8         status[0x7];
10492         u8         ownership[0x1];
10493 };
10494
10495 struct mlx5_ifc_cmd_out_bits {
10496         u8         status[0x8];
10497         u8         reserved_at_8[0x18];
10498
10499         u8         syndrome[0x20];
10500
10501         u8         command_output[0x20];
10502 };
10503
10504 struct mlx5_ifc_cmd_in_bits {
10505         u8         opcode[0x10];
10506         u8         reserved_at_10[0x10];
10507
10508         u8         reserved_at_20[0x10];
10509         u8         op_mod[0x10];
10510
10511         u8         command[][0x20];
10512 };
10513
10514 struct mlx5_ifc_cmd_if_box_bits {
10515         u8         mailbox_data[512][0x8];
10516
10517         u8         reserved_at_1000[0x180];
10518
10519         u8         next_pointer_63_32[0x20];
10520
10521         u8         next_pointer_31_10[0x16];
10522         u8         reserved_at_11b6[0xa];
10523
10524         u8         block_number[0x20];
10525
10526         u8         reserved_at_11e0[0x8];
10527         u8         token[0x8];
10528         u8         ctrl_signature[0x8];
10529         u8         signature[0x8];
10530 };
10531
10532 struct mlx5_ifc_mtt_bits {
10533         u8         ptag_63_32[0x20];
10534
10535         u8         ptag_31_8[0x18];
10536         u8         reserved_at_38[0x6];
10537         u8         wr_en[0x1];
10538         u8         rd_en[0x1];
10539 };
10540
10541 struct mlx5_ifc_query_wol_rol_out_bits {
10542         u8         status[0x8];
10543         u8         reserved_at_8[0x18];
10544
10545         u8         syndrome[0x20];
10546
10547         u8         reserved_at_40[0x10];
10548         u8         rol_mode[0x8];
10549         u8         wol_mode[0x8];
10550
10551         u8         reserved_at_60[0x20];
10552 };
10553
10554 struct mlx5_ifc_query_wol_rol_in_bits {
10555         u8         opcode[0x10];
10556         u8         reserved_at_10[0x10];
10557
10558         u8         reserved_at_20[0x10];
10559         u8         op_mod[0x10];
10560
10561         u8         reserved_at_40[0x40];
10562 };
10563
10564 struct mlx5_ifc_set_wol_rol_out_bits {
10565         u8         status[0x8];
10566         u8         reserved_at_8[0x18];
10567
10568         u8         syndrome[0x20];
10569
10570         u8         reserved_at_40[0x40];
10571 };
10572
10573 struct mlx5_ifc_set_wol_rol_in_bits {
10574         u8         opcode[0x10];
10575         u8         reserved_at_10[0x10];
10576
10577         u8         reserved_at_20[0x10];
10578         u8         op_mod[0x10];
10579
10580         u8         rol_mode_valid[0x1];
10581         u8         wol_mode_valid[0x1];
10582         u8         reserved_at_42[0xe];
10583         u8         rol_mode[0x8];
10584         u8         wol_mode[0x8];
10585
10586         u8         reserved_at_60[0x20];
10587 };
10588
10589 enum {
10590         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10591         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10592         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10593 };
10594
10595 enum {
10596         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10597         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10598         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10599 };
10600
10601 enum {
10602         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10603         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10604         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10605         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10606         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10607         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10608         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10609         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10610         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10611         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10612         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10613 };
10614
10615 struct mlx5_ifc_initial_seg_bits {
10616         u8         fw_rev_minor[0x10];
10617         u8         fw_rev_major[0x10];
10618
10619         u8         cmd_interface_rev[0x10];
10620         u8         fw_rev_subminor[0x10];
10621
10622         u8         reserved_at_40[0x40];
10623
10624         u8         cmdq_phy_addr_63_32[0x20];
10625
10626         u8         cmdq_phy_addr_31_12[0x14];
10627         u8         reserved_at_b4[0x2];
10628         u8         nic_interface[0x2];
10629         u8         log_cmdq_size[0x4];
10630         u8         log_cmdq_stride[0x4];
10631
10632         u8         command_doorbell_vector[0x20];
10633
10634         u8         reserved_at_e0[0xf00];
10635
10636         u8         initializing[0x1];
10637         u8         reserved_at_fe1[0x4];
10638         u8         nic_interface_supported[0x3];
10639         u8         embedded_cpu[0x1];
10640         u8         reserved_at_fe9[0x17];
10641
10642         struct mlx5_ifc_health_buffer_bits health_buffer;
10643
10644         u8         no_dram_nic_offset[0x20];
10645
10646         u8         reserved_at_1220[0x6e40];
10647
10648         u8         reserved_at_8060[0x1f];
10649         u8         clear_int[0x1];
10650
10651         u8         health_syndrome[0x8];
10652         u8         health_counter[0x18];
10653
10654         u8         reserved_at_80a0[0x17fc0];
10655 };
10656
10657 struct mlx5_ifc_mtpps_reg_bits {
10658         u8         reserved_at_0[0xc];
10659         u8         cap_number_of_pps_pins[0x4];
10660         u8         reserved_at_10[0x4];
10661         u8         cap_max_num_of_pps_in_pins[0x4];
10662         u8         reserved_at_18[0x4];
10663         u8         cap_max_num_of_pps_out_pins[0x4];
10664
10665         u8         reserved_at_20[0x13];
10666         u8         cap_log_min_npps_period[0x5];
10667         u8         reserved_at_38[0x3];
10668         u8         cap_log_min_out_pulse_duration_ns[0x5];
10669
10670         u8         reserved_at_40[0x4];
10671         u8         cap_pin_3_mode[0x4];
10672         u8         reserved_at_48[0x4];
10673         u8         cap_pin_2_mode[0x4];
10674         u8         reserved_at_50[0x4];
10675         u8         cap_pin_1_mode[0x4];
10676         u8         reserved_at_58[0x4];
10677         u8         cap_pin_0_mode[0x4];
10678
10679         u8         reserved_at_60[0x4];
10680         u8         cap_pin_7_mode[0x4];
10681         u8         reserved_at_68[0x4];
10682         u8         cap_pin_6_mode[0x4];
10683         u8         reserved_at_70[0x4];
10684         u8         cap_pin_5_mode[0x4];
10685         u8         reserved_at_78[0x4];
10686         u8         cap_pin_4_mode[0x4];
10687
10688         u8         field_select[0x20];
10689         u8         reserved_at_a0[0x20];
10690
10691         u8         npps_period[0x40];
10692
10693         u8         enable[0x1];
10694         u8         reserved_at_101[0xb];
10695         u8         pattern[0x4];
10696         u8         reserved_at_110[0x4];
10697         u8         pin_mode[0x4];
10698         u8         pin[0x8];
10699
10700         u8         reserved_at_120[0x2];
10701         u8         out_pulse_duration_ns[0x1e];
10702
10703         u8         time_stamp[0x40];
10704
10705         u8         out_pulse_duration[0x10];
10706         u8         out_periodic_adjustment[0x10];
10707         u8         enhanced_out_periodic_adjustment[0x20];
10708
10709         u8         reserved_at_1c0[0x20];
10710 };
10711
10712 struct mlx5_ifc_mtppse_reg_bits {
10713         u8         reserved_at_0[0x18];
10714         u8         pin[0x8];
10715         u8         event_arm[0x1];
10716         u8         reserved_at_21[0x1b];
10717         u8         event_generation_mode[0x4];
10718         u8         reserved_at_40[0x40];
10719 };
10720
10721 struct mlx5_ifc_mcqs_reg_bits {
10722         u8         last_index_flag[0x1];
10723         u8         reserved_at_1[0x7];
10724         u8         fw_device[0x8];
10725         u8         component_index[0x10];
10726
10727         u8         reserved_at_20[0x10];
10728         u8         identifier[0x10];
10729
10730         u8         reserved_at_40[0x17];
10731         u8         component_status[0x5];
10732         u8         component_update_state[0x4];
10733
10734         u8         last_update_state_changer_type[0x4];
10735         u8         last_update_state_changer_host_id[0x4];
10736         u8         reserved_at_68[0x18];
10737 };
10738
10739 struct mlx5_ifc_mcqi_cap_bits {
10740         u8         supported_info_bitmask[0x20];
10741
10742         u8         component_size[0x20];
10743
10744         u8         max_component_size[0x20];
10745
10746         u8         log_mcda_word_size[0x4];
10747         u8         reserved_at_64[0xc];
10748         u8         mcda_max_write_size[0x10];
10749
10750         u8         rd_en[0x1];
10751         u8         reserved_at_81[0x1];
10752         u8         match_chip_id[0x1];
10753         u8         match_psid[0x1];
10754         u8         check_user_timestamp[0x1];
10755         u8         match_base_guid_mac[0x1];
10756         u8         reserved_at_86[0x1a];
10757 };
10758
10759 struct mlx5_ifc_mcqi_version_bits {
10760         u8         reserved_at_0[0x2];
10761         u8         build_time_valid[0x1];
10762         u8         user_defined_time_valid[0x1];
10763         u8         reserved_at_4[0x14];
10764         u8         version_string_length[0x8];
10765
10766         u8         version[0x20];
10767
10768         u8         build_time[0x40];
10769
10770         u8         user_defined_time[0x40];
10771
10772         u8         build_tool_version[0x20];
10773
10774         u8         reserved_at_e0[0x20];
10775
10776         u8         version_string[92][0x8];
10777 };
10778
10779 struct mlx5_ifc_mcqi_activation_method_bits {
10780         u8         pending_server_ac_power_cycle[0x1];
10781         u8         pending_server_dc_power_cycle[0x1];
10782         u8         pending_server_reboot[0x1];
10783         u8         pending_fw_reset[0x1];
10784         u8         auto_activate[0x1];
10785         u8         all_hosts_sync[0x1];
10786         u8         device_hw_reset[0x1];
10787         u8         reserved_at_7[0x19];
10788 };
10789
10790 union mlx5_ifc_mcqi_reg_data_bits {
10791         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10792         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10793         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10794 };
10795
10796 struct mlx5_ifc_mcqi_reg_bits {
10797         u8         read_pending_component[0x1];
10798         u8         reserved_at_1[0xf];
10799         u8         component_index[0x10];
10800
10801         u8         reserved_at_20[0x20];
10802
10803         u8         reserved_at_40[0x1b];
10804         u8         info_type[0x5];
10805
10806         u8         info_size[0x20];
10807
10808         u8         offset[0x20];
10809
10810         u8         reserved_at_a0[0x10];
10811         u8         data_size[0x10];
10812
10813         union mlx5_ifc_mcqi_reg_data_bits data[];
10814 };
10815
10816 struct mlx5_ifc_mcc_reg_bits {
10817         u8         reserved_at_0[0x4];
10818         u8         time_elapsed_since_last_cmd[0xc];
10819         u8         reserved_at_10[0x8];
10820         u8         instruction[0x8];
10821
10822         u8         reserved_at_20[0x10];
10823         u8         component_index[0x10];
10824
10825         u8         reserved_at_40[0x8];
10826         u8         update_handle[0x18];
10827
10828         u8         handle_owner_type[0x4];
10829         u8         handle_owner_host_id[0x4];
10830         u8         reserved_at_68[0x1];
10831         u8         control_progress[0x7];
10832         u8         error_code[0x8];
10833         u8         reserved_at_78[0x4];
10834         u8         control_state[0x4];
10835
10836         u8         component_size[0x20];
10837
10838         u8         reserved_at_a0[0x60];
10839 };
10840
10841 struct mlx5_ifc_mcda_reg_bits {
10842         u8         reserved_at_0[0x8];
10843         u8         update_handle[0x18];
10844
10845         u8         offset[0x20];
10846
10847         u8         reserved_at_40[0x10];
10848         u8         size[0x10];
10849
10850         u8         reserved_at_60[0x20];
10851
10852         u8         data[][0x20];
10853 };
10854
10855 enum {
10856         MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10857         MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10858         MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10859         MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10860         MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10861 };
10862
10863 enum {
10864         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10865         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10866 };
10867
10868 enum {
10869         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10870         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10871         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10872 };
10873
10874 struct mlx5_ifc_mfrl_reg_bits {
10875         u8         reserved_at_0[0x20];
10876
10877         u8         reserved_at_20[0x2];
10878         u8         pci_sync_for_fw_update_start[0x1];
10879         u8         pci_sync_for_fw_update_resp[0x2];
10880         u8         rst_type_sel[0x3];
10881         u8         reserved_at_28[0x4];
10882         u8         reset_state[0x4];
10883         u8         reset_type[0x8];
10884         u8         reset_level[0x8];
10885 };
10886
10887 struct mlx5_ifc_mirc_reg_bits {
10888         u8         reserved_at_0[0x18];
10889         u8         status_code[0x8];
10890
10891         u8         reserved_at_20[0x20];
10892 };
10893
10894 struct mlx5_ifc_pddr_monitor_opcode_bits {
10895         u8         reserved_at_0[0x10];
10896         u8         monitor_opcode[0x10];
10897 };
10898
10899 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10900         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10901         u8         reserved_at_0[0x20];
10902 };
10903
10904 enum {
10905         /* Monitor opcodes */
10906         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10907 };
10908
10909 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10910         u8         reserved_at_0[0x10];
10911         u8         group_opcode[0x10];
10912
10913         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10914
10915         u8         reserved_at_40[0x20];
10916
10917         u8         status_message[59][0x20];
10918 };
10919
10920 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10921         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10922         u8         reserved_at_0[0x7c0];
10923 };
10924
10925 enum {
10926         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10927 };
10928
10929 struct mlx5_ifc_pddr_reg_bits {
10930         u8         reserved_at_0[0x8];
10931         u8         local_port[0x8];
10932         u8         pnat[0x2];
10933         u8         reserved_at_12[0xe];
10934
10935         u8         reserved_at_20[0x18];
10936         u8         page_select[0x8];
10937
10938         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10939 };
10940
10941 struct mlx5_ifc_mrtc_reg_bits {
10942         u8         time_synced[0x1];
10943         u8         reserved_at_1[0x1f];
10944
10945         u8         reserved_at_20[0x20];
10946
10947         u8         time_h[0x20];
10948
10949         u8         time_l[0x20];
10950 };
10951
10952 struct mlx5_ifc_mtmp_reg_bits {
10953         u8         reserved_at_0[0x14];
10954         u8         sensor_index[0xc];
10955
10956         u8         reserved_at_20[0x10];
10957         u8         temperature[0x10];
10958
10959         u8         mte[0x1];
10960         u8         mtr[0x1];
10961         u8         reserved_at_42[0xe];
10962         u8         max_temperature[0x10];
10963
10964         u8         tee[0x2];
10965         u8         reserved_at_62[0xe];
10966         u8         temp_threshold_hi[0x10];
10967
10968         u8         reserved_at_80[0x10];
10969         u8         temp_threshold_lo[0x10];
10970
10971         u8         reserved_at_a0[0x20];
10972
10973         u8         sensor_name_hi[0x20];
10974         u8         sensor_name_lo[0x20];
10975 };
10976
10977 union mlx5_ifc_ports_control_registers_document_bits {
10978         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10979         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10980         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10981         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10982         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10983         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10984         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10985         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10986         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10987         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10988         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10989         struct mlx5_ifc_paos_reg_bits paos_reg;
10990         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10991         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10992         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10993         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10994         struct mlx5_ifc_peir_reg_bits peir_reg;
10995         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10996         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10997         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10998         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10999         struct mlx5_ifc_pifr_reg_bits pifr_reg;
11000         struct mlx5_ifc_pipg_reg_bits pipg_reg;
11001         struct mlx5_ifc_plbf_reg_bits plbf_reg;
11002         struct mlx5_ifc_plib_reg_bits plib_reg;
11003         struct mlx5_ifc_plpc_reg_bits plpc_reg;
11004         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11005         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11006         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11007         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11008         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11009         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11010         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11011         struct mlx5_ifc_ppad_reg_bits ppad_reg;
11012         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11013         struct mlx5_ifc_mpein_reg_bits mpein_reg;
11014         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11015         struct mlx5_ifc_pplm_reg_bits pplm_reg;
11016         struct mlx5_ifc_pplr_reg_bits pplr_reg;
11017         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11018         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11019         struct mlx5_ifc_pspa_reg_bits pspa_reg;
11020         struct mlx5_ifc_ptas_reg_bits ptas_reg;
11021         struct mlx5_ifc_ptys_reg_bits ptys_reg;
11022         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11023         struct mlx5_ifc_pude_reg_bits pude_reg;
11024         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11025         struct mlx5_ifc_slrg_reg_bits slrg_reg;
11026         struct mlx5_ifc_sltp_reg_bits sltp_reg;
11027         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11028         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11029         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11030         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11031         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11032         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11033         struct mlx5_ifc_mcc_reg_bits mcc_reg;
11034         struct mlx5_ifc_mcda_reg_bits mcda_reg;
11035         struct mlx5_ifc_mirc_reg_bits mirc_reg;
11036         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11037         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11038         struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11039         struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11040         u8         reserved_at_0[0x60e0];
11041 };
11042
11043 union mlx5_ifc_debug_enhancements_document_bits {
11044         struct mlx5_ifc_health_buffer_bits health_buffer;
11045         u8         reserved_at_0[0x200];
11046 };
11047
11048 union mlx5_ifc_uplink_pci_interface_document_bits {
11049         struct mlx5_ifc_initial_seg_bits initial_seg;
11050         u8         reserved_at_0[0x20060];
11051 };
11052
11053 struct mlx5_ifc_set_flow_table_root_out_bits {
11054         u8         status[0x8];
11055         u8         reserved_at_8[0x18];
11056
11057         u8         syndrome[0x20];
11058
11059         u8         reserved_at_40[0x40];
11060 };
11061
11062 struct mlx5_ifc_set_flow_table_root_in_bits {
11063         u8         opcode[0x10];
11064         u8         reserved_at_10[0x10];
11065
11066         u8         reserved_at_20[0x10];
11067         u8         op_mod[0x10];
11068
11069         u8         other_vport[0x1];
11070         u8         reserved_at_41[0xf];
11071         u8         vport_number[0x10];
11072
11073         u8         reserved_at_60[0x20];
11074
11075         u8         table_type[0x8];
11076         u8         reserved_at_88[0x7];
11077         u8         table_of_other_vport[0x1];
11078         u8         table_vport_number[0x10];
11079
11080         u8         reserved_at_a0[0x8];
11081         u8         table_id[0x18];
11082
11083         u8         reserved_at_c0[0x8];
11084         u8         underlay_qpn[0x18];
11085         u8         table_eswitch_owner_vhca_id_valid[0x1];
11086         u8         reserved_at_e1[0xf];
11087         u8         table_eswitch_owner_vhca_id[0x10];
11088         u8         reserved_at_100[0x100];
11089 };
11090
11091 enum {
11092         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11093         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11094 };
11095
11096 struct mlx5_ifc_modify_flow_table_out_bits {
11097         u8         status[0x8];
11098         u8         reserved_at_8[0x18];
11099
11100         u8         syndrome[0x20];
11101
11102         u8         reserved_at_40[0x40];
11103 };
11104
11105 struct mlx5_ifc_modify_flow_table_in_bits {
11106         u8         opcode[0x10];
11107         u8         reserved_at_10[0x10];
11108
11109         u8         reserved_at_20[0x10];
11110         u8         op_mod[0x10];
11111
11112         u8         other_vport[0x1];
11113         u8         reserved_at_41[0xf];
11114         u8         vport_number[0x10];
11115
11116         u8         reserved_at_60[0x10];
11117         u8         modify_field_select[0x10];
11118
11119         u8         table_type[0x8];
11120         u8         reserved_at_88[0x18];
11121
11122         u8         reserved_at_a0[0x8];
11123         u8         table_id[0x18];
11124
11125         struct mlx5_ifc_flow_table_context_bits flow_table_context;
11126 };
11127
11128 struct mlx5_ifc_ets_tcn_config_reg_bits {
11129         u8         g[0x1];
11130         u8         b[0x1];
11131         u8         r[0x1];
11132         u8         reserved_at_3[0x9];
11133         u8         group[0x4];
11134         u8         reserved_at_10[0x9];
11135         u8         bw_allocation[0x7];
11136
11137         u8         reserved_at_20[0xc];
11138         u8         max_bw_units[0x4];
11139         u8         reserved_at_30[0x8];
11140         u8         max_bw_value[0x8];
11141 };
11142
11143 struct mlx5_ifc_ets_global_config_reg_bits {
11144         u8         reserved_at_0[0x2];
11145         u8         r[0x1];
11146         u8         reserved_at_3[0x1d];
11147
11148         u8         reserved_at_20[0xc];
11149         u8         max_bw_units[0x4];
11150         u8         reserved_at_30[0x8];
11151         u8         max_bw_value[0x8];
11152 };
11153
11154 struct mlx5_ifc_qetc_reg_bits {
11155         u8                                         reserved_at_0[0x8];
11156         u8                                         port_number[0x8];
11157         u8                                         reserved_at_10[0x30];
11158
11159         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11160         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11161 };
11162
11163 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11164         u8         e[0x1];
11165         u8         reserved_at_01[0x0b];
11166         u8         prio[0x04];
11167 };
11168
11169 struct mlx5_ifc_qpdpm_reg_bits {
11170         u8                                     reserved_at_0[0x8];
11171         u8                                     local_port[0x8];
11172         u8                                     reserved_at_10[0x10];
11173         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11174 };
11175
11176 struct mlx5_ifc_qpts_reg_bits {
11177         u8         reserved_at_0[0x8];
11178         u8         local_port[0x8];
11179         u8         reserved_at_10[0x2d];
11180         u8         trust_state[0x3];
11181 };
11182
11183 struct mlx5_ifc_pptb_reg_bits {
11184         u8         reserved_at_0[0x2];
11185         u8         mm[0x2];
11186         u8         reserved_at_4[0x4];
11187         u8         local_port[0x8];
11188         u8         reserved_at_10[0x6];
11189         u8         cm[0x1];
11190         u8         um[0x1];
11191         u8         pm[0x8];
11192
11193         u8         prio_x_buff[0x20];
11194
11195         u8         pm_msb[0x8];
11196         u8         reserved_at_48[0x10];
11197         u8         ctrl_buff[0x4];
11198         u8         untagged_buff[0x4];
11199 };
11200
11201 struct mlx5_ifc_sbcam_reg_bits {
11202         u8         reserved_at_0[0x8];
11203         u8         feature_group[0x8];
11204         u8         reserved_at_10[0x8];
11205         u8         access_reg_group[0x8];
11206
11207         u8         reserved_at_20[0x20];
11208
11209         u8         sb_access_reg_cap_mask[4][0x20];
11210
11211         u8         reserved_at_c0[0x80];
11212
11213         u8         sb_feature_cap_mask[4][0x20];
11214
11215         u8         reserved_at_1c0[0x40];
11216
11217         u8         cap_total_buffer_size[0x20];
11218
11219         u8         cap_cell_size[0x10];
11220         u8         cap_max_pg_buffers[0x8];
11221         u8         cap_num_pool_supported[0x8];
11222
11223         u8         reserved_at_240[0x8];
11224         u8         cap_sbsr_stat_size[0x8];
11225         u8         cap_max_tclass_data[0x8];
11226         u8         cap_max_cpu_ingress_tclass_sb[0x8];
11227 };
11228
11229 struct mlx5_ifc_pbmc_reg_bits {
11230         u8         reserved_at_0[0x8];
11231         u8         local_port[0x8];
11232         u8         reserved_at_10[0x10];
11233
11234         u8         xoff_timer_value[0x10];
11235         u8         xoff_refresh[0x10];
11236
11237         u8         reserved_at_40[0x9];
11238         u8         fullness_threshold[0x7];
11239         u8         port_buffer_size[0x10];
11240
11241         struct mlx5_ifc_bufferx_reg_bits buffer[10];
11242
11243         u8         reserved_at_2e0[0x80];
11244 };
11245
11246 struct mlx5_ifc_sbpr_reg_bits {
11247         u8         desc[0x1];
11248         u8         snap[0x1];
11249         u8         reserved_at_2[0x4];
11250         u8         dir[0x2];
11251         u8         reserved_at_8[0x14];
11252         u8         pool[0x4];
11253
11254         u8         infi_size[0x1];
11255         u8         reserved_at_21[0x7];
11256         u8         size[0x18];
11257
11258         u8         reserved_at_40[0x1c];
11259         u8         mode[0x4];
11260
11261         u8         reserved_at_60[0x8];
11262         u8         buff_occupancy[0x18];
11263
11264         u8         clr[0x1];
11265         u8         reserved_at_81[0x7];
11266         u8         max_buff_occupancy[0x18];
11267
11268         u8         reserved_at_a0[0x8];
11269         u8         ext_buff_occupancy[0x18];
11270 };
11271
11272 struct mlx5_ifc_sbcm_reg_bits {
11273         u8         desc[0x1];
11274         u8         snap[0x1];
11275         u8         reserved_at_2[0x6];
11276         u8         local_port[0x8];
11277         u8         pnat[0x2];
11278         u8         pg_buff[0x6];
11279         u8         reserved_at_18[0x6];
11280         u8         dir[0x2];
11281
11282         u8         reserved_at_20[0x1f];
11283         u8         exc[0x1];
11284
11285         u8         reserved_at_40[0x40];
11286
11287         u8         reserved_at_80[0x8];
11288         u8         buff_occupancy[0x18];
11289
11290         u8         clr[0x1];
11291         u8         reserved_at_a1[0x7];
11292         u8         max_buff_occupancy[0x18];
11293
11294         u8         reserved_at_c0[0x8];
11295         u8         min_buff[0x18];
11296
11297         u8         infi_max[0x1];
11298         u8         reserved_at_e1[0x7];
11299         u8         max_buff[0x18];
11300
11301         u8         reserved_at_100[0x20];
11302
11303         u8         reserved_at_120[0x1c];
11304         u8         pool[0x4];
11305 };
11306
11307 struct mlx5_ifc_qtct_reg_bits {
11308         u8         reserved_at_0[0x8];
11309         u8         port_number[0x8];
11310         u8         reserved_at_10[0xd];
11311         u8         prio[0x3];
11312
11313         u8         reserved_at_20[0x1d];
11314         u8         tclass[0x3];
11315 };
11316
11317 struct mlx5_ifc_mcia_reg_bits {
11318         u8         l[0x1];
11319         u8         reserved_at_1[0x7];
11320         u8         module[0x8];
11321         u8         reserved_at_10[0x8];
11322         u8         status[0x8];
11323
11324         u8         i2c_device_address[0x8];
11325         u8         page_number[0x8];
11326         u8         device_address[0x10];
11327
11328         u8         reserved_at_40[0x10];
11329         u8         size[0x10];
11330
11331         u8         reserved_at_60[0x20];
11332
11333         u8         dword_0[0x20];
11334         u8         dword_1[0x20];
11335         u8         dword_2[0x20];
11336         u8         dword_3[0x20];
11337         u8         dword_4[0x20];
11338         u8         dword_5[0x20];
11339         u8         dword_6[0x20];
11340         u8         dword_7[0x20];
11341         u8         dword_8[0x20];
11342         u8         dword_9[0x20];
11343         u8         dword_10[0x20];
11344         u8         dword_11[0x20];
11345 };
11346
11347 struct mlx5_ifc_dcbx_param_bits {
11348         u8         dcbx_cee_cap[0x1];
11349         u8         dcbx_ieee_cap[0x1];
11350         u8         dcbx_standby_cap[0x1];
11351         u8         reserved_at_3[0x5];
11352         u8         port_number[0x8];
11353         u8         reserved_at_10[0xa];
11354         u8         max_application_table_size[6];
11355         u8         reserved_at_20[0x15];
11356         u8         version_oper[0x3];
11357         u8         reserved_at_38[5];
11358         u8         version_admin[0x3];
11359         u8         willing_admin[0x1];
11360         u8         reserved_at_41[0x3];
11361         u8         pfc_cap_oper[0x4];
11362         u8         reserved_at_48[0x4];
11363         u8         pfc_cap_admin[0x4];
11364         u8         reserved_at_50[0x4];
11365         u8         num_of_tc_oper[0x4];
11366         u8         reserved_at_58[0x4];
11367         u8         num_of_tc_admin[0x4];
11368         u8         remote_willing[0x1];
11369         u8         reserved_at_61[3];
11370         u8         remote_pfc_cap[4];
11371         u8         reserved_at_68[0x14];
11372         u8         remote_num_of_tc[0x4];
11373         u8         reserved_at_80[0x18];
11374         u8         error[0x8];
11375         u8         reserved_at_a0[0x160];
11376 };
11377
11378 enum {
11379         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11380         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11381         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11382 };
11383
11384 struct mlx5_ifc_lagc_bits {
11385         u8         fdb_selection_mode[0x1];
11386         u8         reserved_at_1[0x14];
11387         u8         port_select_mode[0x3];
11388         u8         reserved_at_18[0x5];
11389         u8         lag_state[0x3];
11390
11391         u8         reserved_at_20[0xc];
11392         u8         active_port[0x4];
11393         u8         reserved_at_30[0x4];
11394         u8         tx_remap_affinity_2[0x4];
11395         u8         reserved_at_38[0x4];
11396         u8         tx_remap_affinity_1[0x4];
11397 };
11398
11399 struct mlx5_ifc_create_lag_out_bits {
11400         u8         status[0x8];
11401         u8         reserved_at_8[0x18];
11402
11403         u8         syndrome[0x20];
11404
11405         u8         reserved_at_40[0x40];
11406 };
11407
11408 struct mlx5_ifc_create_lag_in_bits {
11409         u8         opcode[0x10];
11410         u8         reserved_at_10[0x10];
11411
11412         u8         reserved_at_20[0x10];
11413         u8         op_mod[0x10];
11414
11415         struct mlx5_ifc_lagc_bits ctx;
11416 };
11417
11418 struct mlx5_ifc_modify_lag_out_bits {
11419         u8         status[0x8];
11420         u8         reserved_at_8[0x18];
11421
11422         u8         syndrome[0x20];
11423
11424         u8         reserved_at_40[0x40];
11425 };
11426
11427 struct mlx5_ifc_modify_lag_in_bits {
11428         u8         opcode[0x10];
11429         u8         reserved_at_10[0x10];
11430
11431         u8         reserved_at_20[0x10];
11432         u8         op_mod[0x10];
11433
11434         u8         reserved_at_40[0x20];
11435         u8         field_select[0x20];
11436
11437         struct mlx5_ifc_lagc_bits ctx;
11438 };
11439
11440 struct mlx5_ifc_query_lag_out_bits {
11441         u8         status[0x8];
11442         u8         reserved_at_8[0x18];
11443
11444         u8         syndrome[0x20];
11445
11446         struct mlx5_ifc_lagc_bits ctx;
11447 };
11448
11449 struct mlx5_ifc_query_lag_in_bits {
11450         u8         opcode[0x10];
11451         u8         reserved_at_10[0x10];
11452
11453         u8         reserved_at_20[0x10];
11454         u8         op_mod[0x10];
11455
11456         u8         reserved_at_40[0x40];
11457 };
11458
11459 struct mlx5_ifc_destroy_lag_out_bits {
11460         u8         status[0x8];
11461         u8         reserved_at_8[0x18];
11462
11463         u8         syndrome[0x20];
11464
11465         u8         reserved_at_40[0x40];
11466 };
11467
11468 struct mlx5_ifc_destroy_lag_in_bits {
11469         u8         opcode[0x10];
11470         u8         reserved_at_10[0x10];
11471
11472         u8         reserved_at_20[0x10];
11473         u8         op_mod[0x10];
11474
11475         u8         reserved_at_40[0x40];
11476 };
11477
11478 struct mlx5_ifc_create_vport_lag_out_bits {
11479         u8         status[0x8];
11480         u8         reserved_at_8[0x18];
11481
11482         u8         syndrome[0x20];
11483
11484         u8         reserved_at_40[0x40];
11485 };
11486
11487 struct mlx5_ifc_create_vport_lag_in_bits {
11488         u8         opcode[0x10];
11489         u8         reserved_at_10[0x10];
11490
11491         u8         reserved_at_20[0x10];
11492         u8         op_mod[0x10];
11493
11494         u8         reserved_at_40[0x40];
11495 };
11496
11497 struct mlx5_ifc_destroy_vport_lag_out_bits {
11498         u8         status[0x8];
11499         u8         reserved_at_8[0x18];
11500
11501         u8         syndrome[0x20];
11502
11503         u8         reserved_at_40[0x40];
11504 };
11505
11506 struct mlx5_ifc_destroy_vport_lag_in_bits {
11507         u8         opcode[0x10];
11508         u8         reserved_at_10[0x10];
11509
11510         u8         reserved_at_20[0x10];
11511         u8         op_mod[0x10];
11512
11513         u8         reserved_at_40[0x40];
11514 };
11515
11516 enum {
11517         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11518         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11519 };
11520
11521 struct mlx5_ifc_modify_memic_in_bits {
11522         u8         opcode[0x10];
11523         u8         uid[0x10];
11524
11525         u8         reserved_at_20[0x10];
11526         u8         op_mod[0x10];
11527
11528         u8         reserved_at_40[0x20];
11529
11530         u8         reserved_at_60[0x18];
11531         u8         memic_operation_type[0x8];
11532
11533         u8         memic_start_addr[0x40];
11534
11535         u8         reserved_at_c0[0x140];
11536 };
11537
11538 struct mlx5_ifc_modify_memic_out_bits {
11539         u8         status[0x8];
11540         u8         reserved_at_8[0x18];
11541
11542         u8         syndrome[0x20];
11543
11544         u8         reserved_at_40[0x40];
11545
11546         u8         memic_operation_addr[0x40];
11547
11548         u8         reserved_at_c0[0x140];
11549 };
11550
11551 struct mlx5_ifc_alloc_memic_in_bits {
11552         u8         opcode[0x10];
11553         u8         reserved_at_10[0x10];
11554
11555         u8         reserved_at_20[0x10];
11556         u8         op_mod[0x10];
11557
11558         u8         reserved_at_30[0x20];
11559
11560         u8         reserved_at_40[0x18];
11561         u8         log_memic_addr_alignment[0x8];
11562
11563         u8         range_start_addr[0x40];
11564
11565         u8         range_size[0x20];
11566
11567         u8         memic_size[0x20];
11568 };
11569
11570 struct mlx5_ifc_alloc_memic_out_bits {
11571         u8         status[0x8];
11572         u8         reserved_at_8[0x18];
11573
11574         u8         syndrome[0x20];
11575
11576         u8         memic_start_addr[0x40];
11577 };
11578
11579 struct mlx5_ifc_dealloc_memic_in_bits {
11580         u8         opcode[0x10];
11581         u8         reserved_at_10[0x10];
11582
11583         u8         reserved_at_20[0x10];
11584         u8         op_mod[0x10];
11585
11586         u8         reserved_at_40[0x40];
11587
11588         u8         memic_start_addr[0x40];
11589
11590         u8         memic_size[0x20];
11591
11592         u8         reserved_at_e0[0x20];
11593 };
11594
11595 struct mlx5_ifc_dealloc_memic_out_bits {
11596         u8         status[0x8];
11597         u8         reserved_at_8[0x18];
11598
11599         u8         syndrome[0x20];
11600
11601         u8         reserved_at_40[0x40];
11602 };
11603
11604 struct mlx5_ifc_umem_bits {
11605         u8         reserved_at_0[0x80];
11606
11607         u8         ats[0x1];
11608         u8         reserved_at_81[0x1a];
11609         u8         log_page_size[0x5];
11610
11611         u8         page_offset[0x20];
11612
11613         u8         num_of_mtt[0x40];
11614
11615         struct mlx5_ifc_mtt_bits  mtt[];
11616 };
11617
11618 struct mlx5_ifc_uctx_bits {
11619         u8         cap[0x20];
11620
11621         u8         reserved_at_20[0x160];
11622 };
11623
11624 struct mlx5_ifc_sw_icm_bits {
11625         u8         modify_field_select[0x40];
11626
11627         u8         reserved_at_40[0x18];
11628         u8         log_sw_icm_size[0x8];
11629
11630         u8         reserved_at_60[0x20];
11631
11632         u8         sw_icm_start_addr[0x40];
11633
11634         u8         reserved_at_c0[0x140];
11635 };
11636
11637 struct mlx5_ifc_geneve_tlv_option_bits {
11638         u8         modify_field_select[0x40];
11639
11640         u8         reserved_at_40[0x18];
11641         u8         geneve_option_fte_index[0x8];
11642
11643         u8         option_class[0x10];
11644         u8         option_type[0x8];
11645         u8         reserved_at_78[0x3];
11646         u8         option_data_length[0x5];
11647
11648         u8         reserved_at_80[0x180];
11649 };
11650
11651 struct mlx5_ifc_create_umem_in_bits {
11652         u8         opcode[0x10];
11653         u8         uid[0x10];
11654
11655         u8         reserved_at_20[0x10];
11656         u8         op_mod[0x10];
11657
11658         u8         reserved_at_40[0x40];
11659
11660         struct mlx5_ifc_umem_bits  umem;
11661 };
11662
11663 struct mlx5_ifc_create_umem_out_bits {
11664         u8         status[0x8];
11665         u8         reserved_at_8[0x18];
11666
11667         u8         syndrome[0x20];
11668
11669         u8         reserved_at_40[0x8];
11670         u8         umem_id[0x18];
11671
11672         u8         reserved_at_60[0x20];
11673 };
11674
11675 struct mlx5_ifc_destroy_umem_in_bits {
11676         u8        opcode[0x10];
11677         u8        uid[0x10];
11678
11679         u8        reserved_at_20[0x10];
11680         u8        op_mod[0x10];
11681
11682         u8        reserved_at_40[0x8];
11683         u8        umem_id[0x18];
11684
11685         u8        reserved_at_60[0x20];
11686 };
11687
11688 struct mlx5_ifc_destroy_umem_out_bits {
11689         u8        status[0x8];
11690         u8        reserved_at_8[0x18];
11691
11692         u8        syndrome[0x20];
11693
11694         u8        reserved_at_40[0x40];
11695 };
11696
11697 struct mlx5_ifc_create_uctx_in_bits {
11698         u8         opcode[0x10];
11699         u8         reserved_at_10[0x10];
11700
11701         u8         reserved_at_20[0x10];
11702         u8         op_mod[0x10];
11703
11704         u8         reserved_at_40[0x40];
11705
11706         struct mlx5_ifc_uctx_bits  uctx;
11707 };
11708
11709 struct mlx5_ifc_create_uctx_out_bits {
11710         u8         status[0x8];
11711         u8         reserved_at_8[0x18];
11712
11713         u8         syndrome[0x20];
11714
11715         u8         reserved_at_40[0x10];
11716         u8         uid[0x10];
11717
11718         u8         reserved_at_60[0x20];
11719 };
11720
11721 struct mlx5_ifc_destroy_uctx_in_bits {
11722         u8         opcode[0x10];
11723         u8         reserved_at_10[0x10];
11724
11725         u8         reserved_at_20[0x10];
11726         u8         op_mod[0x10];
11727
11728         u8         reserved_at_40[0x10];
11729         u8         uid[0x10];
11730
11731         u8         reserved_at_60[0x20];
11732 };
11733
11734 struct mlx5_ifc_destroy_uctx_out_bits {
11735         u8         status[0x8];
11736         u8         reserved_at_8[0x18];
11737
11738         u8         syndrome[0x20];
11739
11740         u8          reserved_at_40[0x40];
11741 };
11742
11743 struct mlx5_ifc_create_sw_icm_in_bits {
11744         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11745         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11746 };
11747
11748 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11749         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11750         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11751 };
11752
11753 struct mlx5_ifc_mtrc_string_db_param_bits {
11754         u8         string_db_base_address[0x20];
11755
11756         u8         reserved_at_20[0x8];
11757         u8         string_db_size[0x18];
11758 };
11759
11760 struct mlx5_ifc_mtrc_cap_bits {
11761         u8         trace_owner[0x1];
11762         u8         trace_to_memory[0x1];
11763         u8         reserved_at_2[0x4];
11764         u8         trc_ver[0x2];
11765         u8         reserved_at_8[0x14];
11766         u8         num_string_db[0x4];
11767
11768         u8         first_string_trace[0x8];
11769         u8         num_string_trace[0x8];
11770         u8         reserved_at_30[0x28];
11771
11772         u8         log_max_trace_buffer_size[0x8];
11773
11774         u8         reserved_at_60[0x20];
11775
11776         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11777
11778         u8         reserved_at_280[0x180];
11779 };
11780
11781 struct mlx5_ifc_mtrc_conf_bits {
11782         u8         reserved_at_0[0x1c];
11783         u8         trace_mode[0x4];
11784         u8         reserved_at_20[0x18];
11785         u8         log_trace_buffer_size[0x8];
11786         u8         trace_mkey[0x20];
11787         u8         reserved_at_60[0x3a0];
11788 };
11789
11790 struct mlx5_ifc_mtrc_stdb_bits {
11791         u8         string_db_index[0x4];
11792         u8         reserved_at_4[0x4];
11793         u8         read_size[0x18];
11794         u8         start_offset[0x20];
11795         u8         string_db_data[];
11796 };
11797
11798 struct mlx5_ifc_mtrc_ctrl_bits {
11799         u8         trace_status[0x2];
11800         u8         reserved_at_2[0x2];
11801         u8         arm_event[0x1];
11802         u8         reserved_at_5[0xb];
11803         u8         modify_field_select[0x10];
11804         u8         reserved_at_20[0x2b];
11805         u8         current_timestamp52_32[0x15];
11806         u8         current_timestamp31_0[0x20];
11807         u8         reserved_at_80[0x180];
11808 };
11809
11810 struct mlx5_ifc_host_params_context_bits {
11811         u8         host_number[0x8];
11812         u8         reserved_at_8[0x7];
11813         u8         host_pf_disabled[0x1];
11814         u8         host_num_of_vfs[0x10];
11815
11816         u8         host_total_vfs[0x10];
11817         u8         host_pci_bus[0x10];
11818
11819         u8         reserved_at_40[0x10];
11820         u8         host_pci_device[0x10];
11821
11822         u8         reserved_at_60[0x10];
11823         u8         host_pci_function[0x10];
11824
11825         u8         reserved_at_80[0x180];
11826 };
11827
11828 struct mlx5_ifc_query_esw_functions_in_bits {
11829         u8         opcode[0x10];
11830         u8         reserved_at_10[0x10];
11831
11832         u8         reserved_at_20[0x10];
11833         u8         op_mod[0x10];
11834
11835         u8         reserved_at_40[0x40];
11836 };
11837
11838 struct mlx5_ifc_query_esw_functions_out_bits {
11839         u8         status[0x8];
11840         u8         reserved_at_8[0x18];
11841
11842         u8         syndrome[0x20];
11843
11844         u8         reserved_at_40[0x40];
11845
11846         struct mlx5_ifc_host_params_context_bits host_params_context;
11847
11848         u8         reserved_at_280[0x180];
11849         u8         host_sf_enable[][0x40];
11850 };
11851
11852 struct mlx5_ifc_sf_partition_bits {
11853         u8         reserved_at_0[0x10];
11854         u8         log_num_sf[0x8];
11855         u8         log_sf_bar_size[0x8];
11856 };
11857
11858 struct mlx5_ifc_query_sf_partitions_out_bits {
11859         u8         status[0x8];
11860         u8         reserved_at_8[0x18];
11861
11862         u8         syndrome[0x20];
11863
11864         u8         reserved_at_40[0x18];
11865         u8         num_sf_partitions[0x8];
11866
11867         u8         reserved_at_60[0x20];
11868
11869         struct mlx5_ifc_sf_partition_bits sf_partition[];
11870 };
11871
11872 struct mlx5_ifc_query_sf_partitions_in_bits {
11873         u8         opcode[0x10];
11874         u8         reserved_at_10[0x10];
11875
11876         u8         reserved_at_20[0x10];
11877         u8         op_mod[0x10];
11878
11879         u8         reserved_at_40[0x40];
11880 };
11881
11882 struct mlx5_ifc_dealloc_sf_out_bits {
11883         u8         status[0x8];
11884         u8         reserved_at_8[0x18];
11885
11886         u8         syndrome[0x20];
11887
11888         u8         reserved_at_40[0x40];
11889 };
11890
11891 struct mlx5_ifc_dealloc_sf_in_bits {
11892         u8         opcode[0x10];
11893         u8         reserved_at_10[0x10];
11894
11895         u8         reserved_at_20[0x10];
11896         u8         op_mod[0x10];
11897
11898         u8         reserved_at_40[0x10];
11899         u8         function_id[0x10];
11900
11901         u8         reserved_at_60[0x20];
11902 };
11903
11904 struct mlx5_ifc_alloc_sf_out_bits {
11905         u8         status[0x8];
11906         u8         reserved_at_8[0x18];
11907
11908         u8         syndrome[0x20];
11909
11910         u8         reserved_at_40[0x40];
11911 };
11912
11913 struct mlx5_ifc_alloc_sf_in_bits {
11914         u8         opcode[0x10];
11915         u8         reserved_at_10[0x10];
11916
11917         u8         reserved_at_20[0x10];
11918         u8         op_mod[0x10];
11919
11920         u8         reserved_at_40[0x10];
11921         u8         function_id[0x10];
11922
11923         u8         reserved_at_60[0x20];
11924 };
11925
11926 struct mlx5_ifc_affiliated_event_header_bits {
11927         u8         reserved_at_0[0x10];
11928         u8         obj_type[0x10];
11929
11930         u8         obj_id[0x20];
11931 };
11932
11933 enum {
11934         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11935         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11936         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11937         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11938 };
11939
11940 enum {
11941         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11942         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11943         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11944         MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11945         MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11946         MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
11947 };
11948
11949 enum {
11950         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11951 };
11952
11953 enum {
11954         MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11955         MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11956         MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11957         MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11958 };
11959
11960 enum {
11961         MLX5_IPSEC_ASO_MODE              = 0x0,
11962         MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11963         MLX5_IPSEC_ASO_INC_SN            = 0x2,
11964 };
11965
11966 struct mlx5_ifc_ipsec_aso_bits {
11967         u8         valid[0x1];
11968         u8         reserved_at_201[0x1];
11969         u8         mode[0x2];
11970         u8         window_sz[0x2];
11971         u8         soft_lft_arm[0x1];
11972         u8         hard_lft_arm[0x1];
11973         u8         remove_flow_enable[0x1];
11974         u8         esn_event_arm[0x1];
11975         u8         reserved_at_20a[0x16];
11976
11977         u8         remove_flow_pkt_cnt[0x20];
11978
11979         u8         remove_flow_soft_lft[0x20];
11980
11981         u8         reserved_at_260[0x80];
11982
11983         u8         mode_parameter[0x20];
11984
11985         u8         replay_protection_window[0x100];
11986 };
11987
11988 struct mlx5_ifc_ipsec_obj_bits {
11989         u8         modify_field_select[0x40];
11990         u8         full_offload[0x1];
11991         u8         reserved_at_41[0x1];
11992         u8         esn_en[0x1];
11993         u8         esn_overlap[0x1];
11994         u8         reserved_at_44[0x2];
11995         u8         icv_length[0x2];
11996         u8         reserved_at_48[0x4];
11997         u8         aso_return_reg[0x4];
11998         u8         reserved_at_50[0x10];
11999
12000         u8         esn_msb[0x20];
12001
12002         u8         reserved_at_80[0x8];
12003         u8         dekn[0x18];
12004
12005         u8         salt[0x20];
12006
12007         u8         implicit_iv[0x40];
12008
12009         u8         reserved_at_100[0x8];
12010         u8         ipsec_aso_access_pd[0x18];
12011         u8         reserved_at_120[0xe0];
12012
12013         struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12014 };
12015
12016 struct mlx5_ifc_create_ipsec_obj_in_bits {
12017         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12018         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12019 };
12020
12021 enum {
12022         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12023         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12024 };
12025
12026 struct mlx5_ifc_query_ipsec_obj_out_bits {
12027         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12028         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12029 };
12030
12031 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12032         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12033         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12034 };
12035
12036 enum {
12037         MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12038 };
12039
12040 enum {
12041         MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12042         MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12043         MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12044         MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12045 };
12046
12047 #define MLX5_MACSEC_ASO_INC_SN  0x2
12048 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12049
12050 struct mlx5_ifc_macsec_aso_bits {
12051         u8    valid[0x1];
12052         u8    reserved_at_1[0x1];
12053         u8    mode[0x2];
12054         u8    window_size[0x2];
12055         u8    soft_lifetime_arm[0x1];
12056         u8    hard_lifetime_arm[0x1];
12057         u8    remove_flow_enable[0x1];
12058         u8    epn_event_arm[0x1];
12059         u8    reserved_at_a[0x16];
12060
12061         u8    remove_flow_packet_count[0x20];
12062
12063         u8    remove_flow_soft_lifetime[0x20];
12064
12065         u8    reserved_at_60[0x80];
12066
12067         u8    mode_parameter[0x20];
12068
12069         u8    replay_protection_window[8][0x20];
12070 };
12071
12072 struct mlx5_ifc_macsec_offload_obj_bits {
12073         u8    modify_field_select[0x40];
12074
12075         u8    confidentiality_en[0x1];
12076         u8    reserved_at_41[0x1];
12077         u8    epn_en[0x1];
12078         u8    epn_overlap[0x1];
12079         u8    reserved_at_44[0x2];
12080         u8    confidentiality_offset[0x2];
12081         u8    reserved_at_48[0x4];
12082         u8    aso_return_reg[0x4];
12083         u8    reserved_at_50[0x10];
12084
12085         u8    epn_msb[0x20];
12086
12087         u8    reserved_at_80[0x8];
12088         u8    dekn[0x18];
12089
12090         u8    reserved_at_a0[0x20];
12091
12092         u8    sci[0x40];
12093
12094         u8    reserved_at_100[0x8];
12095         u8    macsec_aso_access_pd[0x18];
12096
12097         u8    reserved_at_120[0x60];
12098
12099         u8    salt[3][0x20];
12100
12101         u8    reserved_at_1e0[0x20];
12102
12103         struct mlx5_ifc_macsec_aso_bits macsec_aso;
12104 };
12105
12106 struct mlx5_ifc_create_macsec_obj_in_bits {
12107         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12108         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12109 };
12110
12111 struct mlx5_ifc_modify_macsec_obj_in_bits {
12112         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12113         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12114 };
12115
12116 enum {
12117         MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12118         MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12119 };
12120
12121 struct mlx5_ifc_query_macsec_obj_out_bits {
12122         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12123         struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12124 };
12125
12126 struct mlx5_ifc_wrapped_dek_bits {
12127         u8         gcm_iv[0x60];
12128
12129         u8         reserved_at_60[0x20];
12130
12131         u8         const0[0x1];
12132         u8         key_size[0x1];
12133         u8         reserved_at_82[0x2];
12134         u8         key2_invalid[0x1];
12135         u8         reserved_at_85[0x3];
12136         u8         pd[0x18];
12137
12138         u8         key_purpose[0x5];
12139         u8         reserved_at_a5[0x13];
12140         u8         kek_id[0x8];
12141
12142         u8         reserved_at_c0[0x40];
12143
12144         u8         key1[0x8][0x20];
12145
12146         u8         key2[0x8][0x20];
12147
12148         u8         reserved_at_300[0x40];
12149
12150         u8         const1[0x1];
12151         u8         reserved_at_341[0x1f];
12152
12153         u8         reserved_at_360[0x20];
12154
12155         u8         auth_tag[0x80];
12156 };
12157
12158 struct mlx5_ifc_encryption_key_obj_bits {
12159         u8         modify_field_select[0x40];
12160
12161         u8         state[0x8];
12162         u8         sw_wrapped[0x1];
12163         u8         reserved_at_49[0xb];
12164         u8         key_size[0x4];
12165         u8         reserved_at_58[0x4];
12166         u8         key_purpose[0x4];
12167
12168         u8         reserved_at_60[0x8];
12169         u8         pd[0x18];
12170
12171         u8         reserved_at_80[0x100];
12172
12173         u8         opaque[0x40];
12174
12175         u8         reserved_at_1c0[0x40];
12176
12177         u8         key[8][0x80];
12178
12179         u8         sw_wrapped_dek[8][0x80];
12180
12181         u8         reserved_at_a00[0x600];
12182 };
12183
12184 struct mlx5_ifc_create_encryption_key_in_bits {
12185         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12186         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12187 };
12188
12189 struct mlx5_ifc_modify_encryption_key_in_bits {
12190         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12191         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12192 };
12193
12194 enum {
12195         MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH            = 0x0,
12196         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2         = 0x1,
12197         MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG     = 0x2,
12198         MLX5_FLOW_METER_MODE_NUM_PACKETS                = 0x3,
12199 };
12200
12201 struct mlx5_ifc_flow_meter_parameters_bits {
12202         u8         valid[0x1];
12203         u8         bucket_overflow[0x1];
12204         u8         start_color[0x2];
12205         u8         both_buckets_on_green[0x1];
12206         u8         reserved_at_5[0x1];
12207         u8         meter_mode[0x2];
12208         u8         reserved_at_8[0x18];
12209
12210         u8         reserved_at_20[0x20];
12211
12212         u8         reserved_at_40[0x3];
12213         u8         cbs_exponent[0x5];
12214         u8         cbs_mantissa[0x8];
12215         u8         reserved_at_50[0x3];
12216         u8         cir_exponent[0x5];
12217         u8         cir_mantissa[0x8];
12218
12219         u8         reserved_at_60[0x20];
12220
12221         u8         reserved_at_80[0x3];
12222         u8         ebs_exponent[0x5];
12223         u8         ebs_mantissa[0x8];
12224         u8         reserved_at_90[0x3];
12225         u8         eir_exponent[0x5];
12226         u8         eir_mantissa[0x8];
12227
12228         u8         reserved_at_a0[0x60];
12229 };
12230
12231 struct mlx5_ifc_flow_meter_aso_obj_bits {
12232         u8         modify_field_select[0x40];
12233
12234         u8         reserved_at_40[0x40];
12235
12236         u8         reserved_at_80[0x8];
12237         u8         meter_aso_access_pd[0x18];
12238
12239         u8         reserved_at_a0[0x160];
12240
12241         struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12242 };
12243
12244 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12245         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12246         struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12247 };
12248
12249 struct mlx5_ifc_int_kek_obj_bits {
12250         u8         modify_field_select[0x40];
12251
12252         u8         state[0x8];
12253         u8         auto_gen[0x1];
12254         u8         reserved_at_49[0xb];
12255         u8         key_size[0x4];
12256         u8         reserved_at_58[0x8];
12257
12258         u8         reserved_at_60[0x8];
12259         u8         pd[0x18];
12260
12261         u8         reserved_at_80[0x180];
12262         u8         key[8][0x80];
12263
12264         u8         reserved_at_600[0x200];
12265 };
12266
12267 struct mlx5_ifc_create_int_kek_obj_in_bits {
12268         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12269         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12270 };
12271
12272 struct mlx5_ifc_create_int_kek_obj_out_bits {
12273         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12274         struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12275 };
12276
12277 struct mlx5_ifc_sampler_obj_bits {
12278         u8         modify_field_select[0x40];
12279
12280         u8         table_type[0x8];
12281         u8         level[0x8];
12282         u8         reserved_at_50[0xf];
12283         u8         ignore_flow_level[0x1];
12284
12285         u8         sample_ratio[0x20];
12286
12287         u8         reserved_at_80[0x8];
12288         u8         sample_table_id[0x18];
12289
12290         u8         reserved_at_a0[0x8];
12291         u8         default_table_id[0x18];
12292
12293         u8         sw_steering_icm_address_rx[0x40];
12294         u8         sw_steering_icm_address_tx[0x40];
12295
12296         u8         reserved_at_140[0xa0];
12297 };
12298
12299 struct mlx5_ifc_create_sampler_obj_in_bits {
12300         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12301         struct mlx5_ifc_sampler_obj_bits sampler_object;
12302 };
12303
12304 struct mlx5_ifc_query_sampler_obj_out_bits {
12305         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12306         struct mlx5_ifc_sampler_obj_bits sampler_object;
12307 };
12308
12309 enum {
12310         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12311         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12312 };
12313
12314 enum {
12315         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12316         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12317         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12318 };
12319
12320 struct mlx5_ifc_tls_static_params_bits {
12321         u8         const_2[0x2];
12322         u8         tls_version[0x4];
12323         u8         const_1[0x2];
12324         u8         reserved_at_8[0x14];
12325         u8         encryption_standard[0x4];
12326
12327         u8         reserved_at_20[0x20];
12328
12329         u8         initial_record_number[0x40];
12330
12331         u8         resync_tcp_sn[0x20];
12332
12333         u8         gcm_iv[0x20];
12334
12335         u8         implicit_iv[0x40];
12336
12337         u8         reserved_at_100[0x8];
12338         u8         dek_index[0x18];
12339
12340         u8         reserved_at_120[0xe0];
12341 };
12342
12343 struct mlx5_ifc_tls_progress_params_bits {
12344         u8         next_record_tcp_sn[0x20];
12345
12346         u8         hw_resync_tcp_sn[0x20];
12347
12348         u8         record_tracker_state[0x2];
12349         u8         auth_state[0x2];
12350         u8         reserved_at_44[0x4];
12351         u8         hw_offset_record_number[0x18];
12352 };
12353
12354 enum {
12355         MLX5_MTT_PERM_READ      = 1 << 0,
12356         MLX5_MTT_PERM_WRITE     = 1 << 1,
12357         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12358 };
12359
12360 enum {
12361         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12362         MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12363 };
12364
12365 struct mlx5_ifc_suspend_vhca_in_bits {
12366         u8         opcode[0x10];
12367         u8         uid[0x10];
12368
12369         u8         reserved_at_20[0x10];
12370         u8         op_mod[0x10];
12371
12372         u8         reserved_at_40[0x10];
12373         u8         vhca_id[0x10];
12374
12375         u8         reserved_at_60[0x20];
12376 };
12377
12378 struct mlx5_ifc_suspend_vhca_out_bits {
12379         u8         status[0x8];
12380         u8         reserved_at_8[0x18];
12381
12382         u8         syndrome[0x20];
12383
12384         u8         reserved_at_40[0x40];
12385 };
12386
12387 enum {
12388         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12389         MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12390 };
12391
12392 struct mlx5_ifc_resume_vhca_in_bits {
12393         u8         opcode[0x10];
12394         u8         uid[0x10];
12395
12396         u8         reserved_at_20[0x10];
12397         u8         op_mod[0x10];
12398
12399         u8         reserved_at_40[0x10];
12400         u8         vhca_id[0x10];
12401
12402         u8         reserved_at_60[0x20];
12403 };
12404
12405 struct mlx5_ifc_resume_vhca_out_bits {
12406         u8         status[0x8];
12407         u8         reserved_at_8[0x18];
12408
12409         u8         syndrome[0x20];
12410
12411         u8         reserved_at_40[0x40];
12412 };
12413
12414 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12415         u8         opcode[0x10];
12416         u8         uid[0x10];
12417
12418         u8         reserved_at_20[0x10];
12419         u8         op_mod[0x10];
12420
12421         u8         incremental[0x1];
12422         u8         reserved_at_41[0xf];
12423         u8         vhca_id[0x10];
12424
12425         u8         reserved_at_60[0x20];
12426 };
12427
12428 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12429         u8         status[0x8];
12430         u8         reserved_at_8[0x18];
12431
12432         u8         syndrome[0x20];
12433
12434         u8         reserved_at_40[0x40];
12435
12436         u8         required_umem_size[0x20];
12437
12438         u8         reserved_at_a0[0x160];
12439 };
12440
12441 struct mlx5_ifc_save_vhca_state_in_bits {
12442         u8         opcode[0x10];
12443         u8         uid[0x10];
12444
12445         u8         reserved_at_20[0x10];
12446         u8         op_mod[0x10];
12447
12448         u8         incremental[0x1];
12449         u8         set_track[0x1];
12450         u8         reserved_at_42[0xe];
12451         u8         vhca_id[0x10];
12452
12453         u8         reserved_at_60[0x20];
12454
12455         u8         va[0x40];
12456
12457         u8         mkey[0x20];
12458
12459         u8         size[0x20];
12460 };
12461
12462 struct mlx5_ifc_save_vhca_state_out_bits {
12463         u8         status[0x8];
12464         u8         reserved_at_8[0x18];
12465
12466         u8         syndrome[0x20];
12467
12468         u8         actual_image_size[0x20];
12469
12470         u8         reserved_at_60[0x20];
12471 };
12472
12473 struct mlx5_ifc_load_vhca_state_in_bits {
12474         u8         opcode[0x10];
12475         u8         uid[0x10];
12476
12477         u8         reserved_at_20[0x10];
12478         u8         op_mod[0x10];
12479
12480         u8         reserved_at_40[0x10];
12481         u8         vhca_id[0x10];
12482
12483         u8         reserved_at_60[0x20];
12484
12485         u8         va[0x40];
12486
12487         u8         mkey[0x20];
12488
12489         u8         size[0x20];
12490 };
12491
12492 struct mlx5_ifc_load_vhca_state_out_bits {
12493         u8         status[0x8];
12494         u8         reserved_at_8[0x18];
12495
12496         u8         syndrome[0x20];
12497
12498         u8         reserved_at_40[0x40];
12499 };
12500
12501 struct mlx5_ifc_adv_virtualization_cap_bits {
12502         u8         reserved_at_0[0x3];
12503         u8         pg_track_log_max_num[0x5];
12504         u8         pg_track_max_num_range[0x8];
12505         u8         pg_track_log_min_addr_space[0x8];
12506         u8         pg_track_log_max_addr_space[0x8];
12507
12508         u8         reserved_at_20[0x3];
12509         u8         pg_track_log_min_msg_size[0x5];
12510         u8         reserved_at_28[0x3];
12511         u8         pg_track_log_max_msg_size[0x5];
12512         u8         reserved_at_30[0x3];
12513         u8         pg_track_log_min_page_size[0x5];
12514         u8         reserved_at_38[0x3];
12515         u8         pg_track_log_max_page_size[0x5];
12516
12517         u8         reserved_at_40[0x7c0];
12518 };
12519
12520 struct mlx5_ifc_page_track_report_entry_bits {
12521         u8         dirty_address_high[0x20];
12522
12523         u8         dirty_address_low[0x20];
12524 };
12525
12526 enum {
12527         MLX5_PAGE_TRACK_STATE_TRACKING,
12528         MLX5_PAGE_TRACK_STATE_REPORTING,
12529         MLX5_PAGE_TRACK_STATE_ERROR,
12530 };
12531
12532 struct mlx5_ifc_page_track_range_bits {
12533         u8         start_address[0x40];
12534
12535         u8         length[0x40];
12536 };
12537
12538 struct mlx5_ifc_page_track_bits {
12539         u8         modify_field_select[0x40];
12540
12541         u8         reserved_at_40[0x10];
12542         u8         vhca_id[0x10];
12543
12544         u8         reserved_at_60[0x20];
12545
12546         u8         state[0x4];
12547         u8         track_type[0x4];
12548         u8         log_addr_space_size[0x8];
12549         u8         reserved_at_90[0x3];
12550         u8         log_page_size[0x5];
12551         u8         reserved_at_98[0x3];
12552         u8         log_msg_size[0x5];
12553
12554         u8         reserved_at_a0[0x8];
12555         u8         reporting_qpn[0x18];
12556
12557         u8         reserved_at_c0[0x18];
12558         u8         num_ranges[0x8];
12559
12560         u8         reserved_at_e0[0x20];
12561
12562         u8         range_start_address[0x40];
12563
12564         u8         length[0x40];
12565
12566         struct     mlx5_ifc_page_track_range_bits track_range[0];
12567 };
12568
12569 struct mlx5_ifc_create_page_track_obj_in_bits {
12570         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12571         struct mlx5_ifc_page_track_bits obj_context;
12572 };
12573
12574 struct mlx5_ifc_modify_page_track_obj_in_bits {
12575         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12576         struct mlx5_ifc_page_track_bits obj_context;
12577 };
12578
12579 #endif /* MLX5_IFC_H */