include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
  97         MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
  98         MLX5_OBJ_TYPE_MKEY = 0xff01,
  99         MLX5_OBJ_TYPE_QP = 0xff02,
 100         MLX5_OBJ_TYPE_PSV = 0xff03,
 101         MLX5_OBJ_TYPE_RMP = 0xff04,
 102         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 103         MLX5_OBJ_TYPE_RQ = 0xff06,
 104         MLX5_OBJ_TYPE_SQ = 0xff07,
 105         MLX5_OBJ_TYPE_TIR = 0xff08,
 106         MLX5_OBJ_TYPE_TIS = 0xff09,
 107         MLX5_OBJ_TYPE_DCT = 0xff0a,
 108         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 109         MLX5_OBJ_TYPE_RQT = 0xff0e,
 110         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 111         MLX5_OBJ_TYPE_CQ = 0xff10,
 112 };
 113
 114 enum {
 115         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 116         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 117         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 118         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 119         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 120         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 121         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 122         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 123         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 124         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 125         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 126         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 127         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 128         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 129         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 130         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 131         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 132         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 133         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 134         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 135         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 136         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 137         MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
 138         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 139         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 140         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 141         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 142         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 143         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 144         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 145         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 146         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 147         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 148         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 149         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 150         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 151         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 152         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 153         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 154         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 155         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 156         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 157         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 158         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 159         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 160         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 161         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 162         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 163         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 164         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 165         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 166         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 167         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 168         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 169         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 170         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 171         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 172         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 173         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 174         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 175         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 176         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 177         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 178         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 179         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 180         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 181         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 182         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 183         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 184         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 185         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 186         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 187         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 188         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 189         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 190         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 191         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 192         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 193         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 194         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 195         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 196         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 197         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 198         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 199         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 200         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 201         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 202         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 203         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 204         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 205         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 206         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 207         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 208         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 209         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 210         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 211         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 212         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 213         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 214         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 215         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 216         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 217         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 218         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 219         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 220         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 221         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 222         MLX5_CMD_OP_NOP                           = 0x80d,
 223         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 224         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 225         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 226         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 227         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 228         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 229         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 230         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 231         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 232         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 233         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 234         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 235         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 236         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 237         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 238         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 239         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 240         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 241         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 242         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 243         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 244         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 245         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 246         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 247         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 248         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 249         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 250         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 251         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 252         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 253         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 254         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 255         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 256         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 257         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 258         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 259         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 260         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 261         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 262         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 263         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 264         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 265         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 266         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 267         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 268         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 269         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 270         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 271         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 272         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 273         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 274         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 275         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 276         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 277         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 278         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 279         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 280         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 281         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 282         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 283         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 284         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 285         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 286         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 287         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 288         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 289         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 290         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 291         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 292         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 293         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 294         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 295         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 296         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 297         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 298         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 299         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 300         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 301         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 302         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 303         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 304         MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
 305         MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
 306         MLX5_CMD_OP_MAX
 307 };
 308
 309 /* Valid range for general commands that don't work over an object */
 310 enum {
 311         MLX5_CMD_OP_GENERAL_START = 0xb00,
 312         MLX5_CMD_OP_GENERAL_END = 0xd00,
 313 };
 314
 315 struct mlx5_ifc_flow_table_fields_supported_bits {
 316         u8         outer_dmac[0x1];
 317         u8         outer_smac[0x1];
 318         u8         outer_ether_type[0x1];
 319         u8         outer_ip_version[0x1];
 320         u8         outer_first_prio[0x1];
 321         u8         outer_first_cfi[0x1];
 322         u8         outer_first_vid[0x1];
 323         u8         outer_ipv4_ttl[0x1];
 324         u8         outer_second_prio[0x1];
 325         u8         outer_second_cfi[0x1];
 326         u8         outer_second_vid[0x1];
 327         u8         reserved_at_b[0x1];
 328         u8         outer_sip[0x1];
 329         u8         outer_dip[0x1];
 330         u8         outer_frag[0x1];
 331         u8         outer_ip_protocol[0x1];
 332         u8         outer_ip_ecn[0x1];
 333         u8         outer_ip_dscp[0x1];
 334         u8         outer_udp_sport[0x1];
 335         u8         outer_udp_dport[0x1];
 336         u8         outer_tcp_sport[0x1];
 337         u8         outer_tcp_dport[0x1];
 338         u8         outer_tcp_flags[0x1];
 339         u8         outer_gre_protocol[0x1];
 340         u8         outer_gre_key[0x1];
 341         u8         outer_vxlan_vni[0x1];
 342         u8         outer_geneve_vni[0x1];
 343         u8         outer_geneve_oam[0x1];
 344         u8         outer_geneve_protocol_type[0x1];
 345         u8         outer_geneve_opt_len[0x1];
 346         u8         reserved_at_1e[0x1];
 347         u8         source_eswitch_port[0x1];
 348
 349         u8         inner_dmac[0x1];
 350         u8         inner_smac[0x1];
 351         u8         inner_ether_type[0x1];
 352         u8         inner_ip_version[0x1];
 353         u8         inner_first_prio[0x1];
 354         u8         inner_first_cfi[0x1];
 355         u8         inner_first_vid[0x1];
 356         u8         reserved_at_27[0x1];
 357         u8         inner_second_prio[0x1];
 358         u8         inner_second_cfi[0x1];
 359         u8         inner_second_vid[0x1];
 360         u8         reserved_at_2b[0x1];
 361         u8         inner_sip[0x1];
 362         u8         inner_dip[0x1];
 363         u8         inner_frag[0x1];
 364         u8         inner_ip_protocol[0x1];
 365         u8         inner_ip_ecn[0x1];
 366         u8         inner_ip_dscp[0x1];
 367         u8         inner_udp_sport[0x1];
 368         u8         inner_udp_dport[0x1];
 369         u8         inner_tcp_sport[0x1];
 370         u8         inner_tcp_dport[0x1];
 371         u8         inner_tcp_flags[0x1];
 372         u8         reserved_at_37[0x9];
 373
 374         u8         geneve_tlv_option_0_data[0x1];
 375         u8         reserved_at_41[0x4];
 376         u8         outer_first_mpls_over_udp[0x4];
 377         u8         outer_first_mpls_over_gre[0x4];
 378         u8         inner_first_mpls[0x4];
 379         u8         outer_first_mpls[0x4];
 380         u8         reserved_at_55[0x2];
 381         u8         outer_esp_spi[0x1];
 382         u8         reserved_at_58[0x2];
 383         u8         bth_dst_qp[0x1];
 384         u8         reserved_at_5b[0x5];
 385
 386         u8         reserved_at_60[0x18];
 387         u8         metadata_reg_c_7[0x1];
 388         u8         metadata_reg_c_6[0x1];
 389         u8         metadata_reg_c_5[0x1];
 390         u8         metadata_reg_c_4[0x1];
 391         u8         metadata_reg_c_3[0x1];
 392         u8         metadata_reg_c_2[0x1];
 393         u8         metadata_reg_c_1[0x1];
 394         u8         metadata_reg_c_0[0x1];
 395 };
 396
 397 struct mlx5_ifc_flow_table_prop_layout_bits {
 398         u8         ft_support[0x1];
 399         u8         reserved_at_1[0x1];
 400         u8         flow_counter[0x1];
 401         u8         flow_modify_en[0x1];
 402         u8         modify_root[0x1];
 403         u8         identified_miss_table_mode[0x1];
 404         u8         flow_table_modify[0x1];
 405         u8         reformat[0x1];
 406         u8         decap[0x1];
 407         u8         reserved_at_9[0x1];
 408         u8         pop_vlan[0x1];
 409         u8         push_vlan[0x1];
 410         u8         reserved_at_c[0x1];
 411         u8         pop_vlan_2[0x1];
 412         u8         push_vlan_2[0x1];
 413         u8         reformat_and_vlan_action[0x1];
 414         u8         reserved_at_10[0x1];
 415         u8         sw_owner[0x1];
 416         u8         reformat_l3_tunnel_to_l2[0x1];
 417         u8         reformat_l2_to_l3_tunnel[0x1];
 418         u8         reformat_and_modify_action[0x1];
 419         u8         ignore_flow_level[0x1];
 420         u8         reserved_at_16[0x1];
 421         u8         table_miss_action_domain[0x1];
 422         u8         termination_table[0x1];
 423         u8         reformat_and_fwd_to_table[0x1];
 424         u8         reserved_at_1a[0x2];
 425         u8         ipsec_encrypt[0x1];
 426         u8         ipsec_decrypt[0x1];
 427         u8         sw_owner_v2[0x1];
 428         u8         reserved_at_1f[0x1];
 429
 430         u8         termination_table_raw_traffic[0x1];
 431         u8         reserved_at_21[0x1];
 432         u8         log_max_ft_size[0x6];
 433         u8         log_max_modify_header_context[0x8];
 434         u8         max_modify_header_actions[0x8];
 435         u8         max_ft_level[0x8];
 436
 437         u8         reserved_at_40[0x20];
 438
 439         u8         reserved_at_60[0x2];
 440         u8         reformat_insert[0x1];
 441         u8         reformat_remove[0x1];
 442         u8         reserver_at_64[0x14];
 443         u8         log_max_ft_num[0x8];
 444
 445         u8         reserved_at_80[0x10];
 446         u8         log_max_flow_counter[0x8];
 447         u8         log_max_destination[0x8];
 448
 449         u8         reserved_at_a0[0x18];
 450         u8         log_max_flow[0x8];
 451
 452         u8         reserved_at_c0[0x40];
 453
 454         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 455
 456         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 457 };
 458
 459 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 460         u8         send[0x1];
 461         u8         receive[0x1];
 462         u8         write[0x1];
 463         u8         read[0x1];
 464         u8         atomic[0x1];
 465         u8         srq_receive[0x1];
 466         u8         reserved_at_6[0x1a];
 467 };
 468
 469 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 470         u8         smac_47_16[0x20];
 471
 472         u8         smac_15_0[0x10];
 473         u8         ethertype[0x10];
 474
 475         u8         dmac_47_16[0x20];
 476
 477         u8         dmac_15_0[0x10];
 478         u8         first_prio[0x3];
 479         u8         first_cfi[0x1];
 480         u8         first_vid[0xc];
 481
 482         u8         ip_protocol[0x8];
 483         u8         ip_dscp[0x6];
 484         u8         ip_ecn[0x2];
 485         u8         cvlan_tag[0x1];
 486         u8         svlan_tag[0x1];
 487         u8         frag[0x1];
 488         u8         ip_version[0x4];
 489         u8         tcp_flags[0x9];
 490
 491         u8         tcp_sport[0x10];
 492         u8         tcp_dport[0x10];
 493
 494         u8         reserved_at_c0[0x18];
 495         u8         ttl_hoplimit[0x8];
 496
 497         u8         udp_sport[0x10];
 498         u8         udp_dport[0x10];
 499
 500         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 501
 502         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 503 };
 504
 505 struct mlx5_ifc_nvgre_key_bits {
 506         u8 hi[0x18];
 507         u8 lo[0x8];
 508 };
 509
 510 union mlx5_ifc_gre_key_bits {
 511         struct mlx5_ifc_nvgre_key_bits nvgre;
 512         u8 key[0x20];
 513 };
 514
 515 struct mlx5_ifc_fte_match_set_misc_bits {
 516         u8         gre_c_present[0x1];
 517         u8         reserved_at_1[0x1];
 518         u8         gre_k_present[0x1];
 519         u8         gre_s_present[0x1];
 520         u8         source_vhca_port[0x4];
 521         u8         source_sqn[0x18];
 522
 523         u8         source_eswitch_owner_vhca_id[0x10];
 524         u8         source_port[0x10];
 525
 526         u8         outer_second_prio[0x3];
 527         u8         outer_second_cfi[0x1];
 528         u8         outer_second_vid[0xc];
 529         u8         inner_second_prio[0x3];
 530         u8         inner_second_cfi[0x1];
 531         u8         inner_second_vid[0xc];
 532
 533         u8         outer_second_cvlan_tag[0x1];
 534         u8         inner_second_cvlan_tag[0x1];
 535         u8         outer_second_svlan_tag[0x1];
 536         u8         inner_second_svlan_tag[0x1];
 537         u8         reserved_at_64[0xc];
 538         u8         gre_protocol[0x10];
 539
 540         union mlx5_ifc_gre_key_bits gre_key;
 541
 542         u8         vxlan_vni[0x18];
 543         u8         reserved_at_b8[0x8];
 544
 545         u8         geneve_vni[0x18];
 546         u8         reserved_at_d8[0x7];
 547         u8         geneve_oam[0x1];
 548
 549         u8         reserved_at_e0[0xc];
 550         u8         outer_ipv6_flow_label[0x14];
 551
 552         u8         reserved_at_100[0xc];
 553         u8         inner_ipv6_flow_label[0x14];
 554
 555         u8         reserved_at_120[0xa];
 556         u8         geneve_opt_len[0x6];
 557         u8         geneve_protocol_type[0x10];
 558
 559         u8         reserved_at_140[0x8];
 560         u8         bth_dst_qp[0x18];
 561         u8         reserved_at_160[0x20];
 562         u8         outer_esp_spi[0x20];
 563         u8         reserved_at_1a0[0x60];
 564 };
 565
 566 struct mlx5_ifc_fte_match_mpls_bits {
 567         u8         mpls_label[0x14];
 568         u8         mpls_exp[0x3];
 569         u8         mpls_s_bos[0x1];
 570         u8         mpls_ttl[0x8];
 571 };
 572
 573 struct mlx5_ifc_fte_match_set_misc2_bits {
 574         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 575
 576         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 577
 578         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 579
 580         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 581
 582         u8         metadata_reg_c_7[0x20];
 583
 584         u8         metadata_reg_c_6[0x20];
 585
 586         u8         metadata_reg_c_5[0x20];
 587
 588         u8         metadata_reg_c_4[0x20];
 589
 590         u8         metadata_reg_c_3[0x20];
 591
 592         u8         metadata_reg_c_2[0x20];
 593
 594         u8         metadata_reg_c_1[0x20];
 595
 596         u8         metadata_reg_c_0[0x20];
 597
 598         u8         metadata_reg_a[0x20];
 599
 600         u8         reserved_at_1a0[0x60];
 601 };
 602
 603 struct mlx5_ifc_fte_match_set_misc3_bits {
 604         u8         inner_tcp_seq_num[0x20];
 605
 606         u8         outer_tcp_seq_num[0x20];
 607
 608         u8         inner_tcp_ack_num[0x20];
 609
 610         u8         outer_tcp_ack_num[0x20];
 611
 612         u8         reserved_at_80[0x8];
 613         u8         outer_vxlan_gpe_vni[0x18];
 614
 615         u8         outer_vxlan_gpe_next_protocol[0x8];
 616         u8         outer_vxlan_gpe_flags[0x8];
 617         u8         reserved_at_b0[0x10];
 618
 619         u8         icmp_header_data[0x20];
 620
 621         u8         icmpv6_header_data[0x20];
 622
 623         u8         icmp_type[0x8];
 624         u8         icmp_code[0x8];
 625         u8         icmpv6_type[0x8];
 626         u8         icmpv6_code[0x8];
 627
 628         u8         geneve_tlv_option_0_data[0x20];
 629
 630         u8         gtpu_teid[0x20];
 631
 632         u8         gtpu_msg_type[0x8];
 633         u8         gtpu_msg_flags[0x8];
 634         u8         reserved_at_170[0x10];
 635
 636         u8         gtpu_dw_2[0x20];
 637
 638         u8         gtpu_first_ext_dw_0[0x20];
 639
 640         u8         gtpu_dw_0[0x20];
 641
 642         u8         reserved_at_1e0[0x20];
 643 };
 644
 645 struct mlx5_ifc_fte_match_set_misc4_bits {
 646         u8         prog_sample_field_value_0[0x20];
 647
 648         u8         prog_sample_field_id_0[0x20];
 649
 650         u8         prog_sample_field_value_1[0x20];
 651
 652         u8         prog_sample_field_id_1[0x20];
 653
 654         u8         prog_sample_field_value_2[0x20];
 655
 656         u8         prog_sample_field_id_2[0x20];
 657
 658         u8         prog_sample_field_value_3[0x20];
 659
 660         u8         prog_sample_field_id_3[0x20];
 661
 662         u8         reserved_at_100[0x100];
 663 };
 664
 665 struct mlx5_ifc_cmd_pas_bits {
 666         u8         pa_h[0x20];
 667
 668         u8         pa_l[0x14];
 669         u8         reserved_at_34[0xc];
 670 };
 671
 672 struct mlx5_ifc_uint64_bits {
 673         u8         hi[0x20];
 674
 675         u8         lo[0x20];
 676 };
 677
 678 enum {
 679         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 680         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 681         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 682         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 683         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 684         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 685         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 686         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 687         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 688         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 689 };
 690
 691 struct mlx5_ifc_ads_bits {
 692         u8         fl[0x1];
 693         u8         free_ar[0x1];
 694         u8         reserved_at_2[0xe];
 695         u8         pkey_index[0x10];
 696
 697         u8         reserved_at_20[0x8];
 698         u8         grh[0x1];
 699         u8         mlid[0x7];
 700         u8         rlid[0x10];
 701
 702         u8         ack_timeout[0x5];
 703         u8         reserved_at_45[0x3];
 704         u8         src_addr_index[0x8];
 705         u8         reserved_at_50[0x4];
 706         u8         stat_rate[0x4];
 707         u8         hop_limit[0x8];
 708
 709         u8         reserved_at_60[0x4];
 710         u8         tclass[0x8];
 711         u8         flow_label[0x14];
 712
 713         u8         rgid_rip[16][0x8];
 714
 715         u8         reserved_at_100[0x4];
 716         u8         f_dscp[0x1];
 717         u8         f_ecn[0x1];
 718         u8         reserved_at_106[0x1];
 719         u8         f_eth_prio[0x1];
 720         u8         ecn[0x2];
 721         u8         dscp[0x6];
 722         u8         udp_sport[0x10];
 723
 724         u8         dei_cfi[0x1];
 725         u8         eth_prio[0x3];
 726         u8         sl[0x4];
 727         u8         vhca_port_num[0x8];
 728         u8         rmac_47_32[0x10];
 729
 730         u8         rmac_31_0[0x20];
 731 };
 732
 733 struct mlx5_ifc_flow_table_nic_cap_bits {
 734         u8         nic_rx_multi_path_tirs[0x1];
 735         u8         nic_rx_multi_path_tirs_fts[0x1];
 736         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 737         u8         reserved_at_3[0x4];
 738         u8         sw_owner_reformat_supported[0x1];
 739         u8         reserved_at_8[0x18];
 740
 741         u8         encap_general_header[0x1];
 742         u8         reserved_at_21[0xa];
 743         u8         log_max_packet_reformat_context[0x5];
 744         u8         reserved_at_30[0x6];
 745         u8         max_encap_header_size[0xa];
 746         u8         reserved_at_40[0x1c0];
 747
 748         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 749
 750         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 757
 758         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 759
 760         u8         reserved_at_e00[0x1200];
 761
 762         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 763
 764         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 765
 766         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 767
 768         u8         reserved_at_20c0[0x5f40];
 769 };
 770
 771 struct mlx5_ifc_port_selection_cap_bits {
 772         u8         reserved_at_0[0x10];
 773         u8         port_select_flow_table[0x1];
 774         u8         reserved_at_11[0xf];
 775
 776         u8         reserved_at_20[0x1e0];
 777
 778         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
 779
 780         u8         reserved_at_400[0x7c00];
 781 };
 782
 783 enum {
 784         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 785         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 786         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 787         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 788         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 789         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 790         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 791         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 792 };
 793
 794 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 795         u8      fdb_to_vport_reg_c_id[0x8];
 796         u8      reserved_at_8[0xd];
 797         u8      fdb_modify_header_fwd_to_table[0x1];
 798         u8      reserved_at_16[0x1];
 799         u8      flow_source[0x1];
 800         u8      reserved_at_18[0x2];
 801         u8      multi_fdb_encap[0x1];
 802         u8      egress_acl_forward_to_vport[0x1];
 803         u8      fdb_multi_path_to_table[0x1];
 804         u8      reserved_at_1d[0x3];
 805
 806         u8      reserved_at_20[0x1e0];
 807
 808         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 809
 810         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 811
 812         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 813
 814         u8      reserved_at_800[0x1000];
 815
 816         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 817
 818         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 819
 820         u8      sw_steering_uplink_icm_address_rx[0x40];
 821
 822         u8      sw_steering_uplink_icm_address_tx[0x40];
 823
 824         u8      reserved_at_1900[0x6700];
 825 };
 826
 827 enum {
 828         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 829         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 830 };
 831
 832 struct mlx5_ifc_e_switch_cap_bits {
 833         u8         vport_svlan_strip[0x1];
 834         u8         vport_cvlan_strip[0x1];
 835         u8         vport_svlan_insert[0x1];
 836         u8         vport_cvlan_insert_if_not_exist[0x1];
 837         u8         vport_cvlan_insert_overwrite[0x1];
 838         u8         reserved_at_5[0x2];
 839         u8         esw_shared_ingress_acl[0x1];
 840         u8         esw_uplink_ingress_acl[0x1];
 841         u8         root_ft_on_other_esw[0x1];
 842         u8         reserved_at_a[0xf];
 843         u8         esw_functions_changed[0x1];
 844         u8         reserved_at_1a[0x1];
 845         u8         ecpf_vport_exists[0x1];
 846         u8         counter_eswitch_affinity[0x1];
 847         u8         merged_eswitch[0x1];
 848         u8         nic_vport_node_guid_modify[0x1];
 849         u8         nic_vport_port_guid_modify[0x1];
 850
 851         u8         vxlan_encap_decap[0x1];
 852         u8         nvgre_encap_decap[0x1];
 853         u8         reserved_at_22[0x1];
 854         u8         log_max_fdb_encap_uplink[0x5];
 855         u8         reserved_at_21[0x3];
 856         u8         log_max_packet_reformat_context[0x5];
 857         u8         reserved_2b[0x6];
 858         u8         max_encap_header_size[0xa];
 859
 860         u8         reserved_at_40[0xb];
 861         u8         log_max_esw_sf[0x5];
 862         u8         esw_sf_base_id[0x10];
 863
 864         u8         reserved_at_60[0x7a0];
 865
 866 };
 867
 868 struct mlx5_ifc_qos_cap_bits {
 869         u8         packet_pacing[0x1];
 870         u8         esw_scheduling[0x1];
 871         u8         esw_bw_share[0x1];
 872         u8         esw_rate_limit[0x1];
 873         u8         reserved_at_4[0x1];
 874         u8         packet_pacing_burst_bound[0x1];
 875         u8         packet_pacing_typical_size[0x1];
 876         u8         reserved_at_7[0x1];
 877         u8         nic_sq_scheduling[0x1];
 878         u8         nic_bw_share[0x1];
 879         u8         nic_rate_limit[0x1];
 880         u8         packet_pacing_uid[0x1];
 881         u8         log_esw_max_sched_depth[0x4];
 882         u8         reserved_at_10[0x10];
 883
 884         u8         reserved_at_20[0xb];
 885         u8         log_max_qos_nic_queue_group[0x5];
 886         u8         reserved_at_30[0x10];
 887
 888         u8         packet_pacing_max_rate[0x20];
 889
 890         u8         packet_pacing_min_rate[0x20];
 891
 892         u8         reserved_at_80[0x10];
 893         u8         packet_pacing_rate_table_size[0x10];
 894
 895         u8         esw_element_type[0x10];
 896         u8         esw_tsar_type[0x10];
 897
 898         u8         reserved_at_c0[0x10];
 899         u8         max_qos_para_vport[0x10];
 900
 901         u8         max_tsar_bw_share[0x20];
 902
 903         u8         reserved_at_100[0x700];
 904 };
 905
 906 struct mlx5_ifc_debug_cap_bits {
 907         u8         core_dump_general[0x1];
 908         u8         core_dump_qp[0x1];
 909         u8         reserved_at_2[0x7];
 910         u8         resource_dump[0x1];
 911         u8         reserved_at_a[0x16];
 912
 913         u8         reserved_at_20[0x2];
 914         u8         stall_detect[0x1];
 915         u8         reserved_at_23[0x1d];
 916
 917         u8         reserved_at_40[0x7c0];
 918 };
 919
 920 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 921         u8         csum_cap[0x1];
 922         u8         vlan_cap[0x1];
 923         u8         lro_cap[0x1];
 924         u8         lro_psh_flag[0x1];
 925         u8         lro_time_stamp[0x1];
 926         u8         reserved_at_5[0x2];
 927         u8         wqe_vlan_insert[0x1];
 928         u8         self_lb_en_modifiable[0x1];
 929         u8         reserved_at_9[0x2];
 930         u8         max_lso_cap[0x5];
 931         u8         multi_pkt_send_wqe[0x2];
 932         u8         wqe_inline_mode[0x2];
 933         u8         rss_ind_tbl_cap[0x4];
 934         u8         reg_umr_sq[0x1];
 935         u8         scatter_fcs[0x1];
 936         u8         enhanced_multi_pkt_send_wqe[0x1];
 937         u8         tunnel_lso_const_out_ip_id[0x1];
 938         u8         tunnel_lro_gre[0x1];
 939         u8         tunnel_lro_vxlan[0x1];
 940         u8         tunnel_stateless_gre[0x1];
 941         u8         tunnel_stateless_vxlan[0x1];
 942
 943         u8         swp[0x1];
 944         u8         swp_csum[0x1];
 945         u8         swp_lso[0x1];
 946         u8         cqe_checksum_full[0x1];
 947         u8         tunnel_stateless_geneve_tx[0x1];
 948         u8         tunnel_stateless_mpls_over_udp[0x1];
 949         u8         tunnel_stateless_mpls_over_gre[0x1];
 950         u8         tunnel_stateless_vxlan_gpe[0x1];
 951         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 952         u8         tunnel_stateless_ip_over_ip[0x1];
 953         u8         insert_trailer[0x1];
 954         u8         reserved_at_2b[0x1];
 955         u8         tunnel_stateless_ip_over_ip_rx[0x1];
 956         u8         tunnel_stateless_ip_over_ip_tx[0x1];
 957         u8         reserved_at_2e[0x2];
 958         u8         max_vxlan_udp_ports[0x8];
 959         u8         reserved_at_38[0x6];
 960         u8         max_geneve_opt_len[0x1];
 961         u8         tunnel_stateless_geneve_rx[0x1];
 962
 963         u8         reserved_at_40[0x10];
 964         u8         lro_min_mss_size[0x10];
 965
 966         u8         reserved_at_60[0x120];
 967
 968         u8         lro_timer_supported_periods[4][0x20];
 969
 970         u8         reserved_at_200[0x600];
 971 };
 972
 973 enum {
 974         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
 975         MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
 976         MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
 977 };
 978
 979 struct mlx5_ifc_roce_cap_bits {
 980         u8         roce_apm[0x1];
 981         u8         reserved_at_1[0x3];
 982         u8         sw_r_roce_src_udp_port[0x1];
 983         u8         fl_rc_qp_when_roce_disabled[0x1];
 984         u8         fl_rc_qp_when_roce_enabled[0x1];
 985         u8         reserved_at_7[0x17];
 986         u8         qp_ts_format[0x2];
 987
 988         u8         reserved_at_20[0x60];
 989
 990         u8         reserved_at_80[0xc];
 991         u8         l3_type[0x4];
 992         u8         reserved_at_90[0x8];
 993         u8         roce_version[0x8];
 994
 995         u8         reserved_at_a0[0x10];
 996         u8         r_roce_dest_udp_port[0x10];
 997
 998         u8         r_roce_max_src_udp_port[0x10];
 999         u8         r_roce_min_src_udp_port[0x10];
1000
1001         u8         reserved_at_e0[0x10];
1002         u8         roce_address_table_size[0x10];
1003
1004         u8         reserved_at_100[0x700];
1005 };
1006
1007 struct mlx5_ifc_sync_steering_in_bits {
1008         u8         opcode[0x10];
1009         u8         uid[0x10];
1010
1011         u8         reserved_at_20[0x10];
1012         u8         op_mod[0x10];
1013
1014         u8         reserved_at_40[0xc0];
1015 };
1016
1017 struct mlx5_ifc_sync_steering_out_bits {
1018         u8         status[0x8];
1019         u8         reserved_at_8[0x18];
1020
1021         u8         syndrome[0x20];
1022
1023         u8         reserved_at_40[0x40];
1024 };
1025
1026 struct mlx5_ifc_device_mem_cap_bits {
1027         u8         memic[0x1];
1028         u8         reserved_at_1[0x1f];
1029
1030         u8         reserved_at_20[0xb];
1031         u8         log_min_memic_alloc_size[0x5];
1032         u8         reserved_at_30[0x8];
1033         u8         log_max_memic_addr_alignment[0x8];
1034
1035         u8         memic_bar_start_addr[0x40];
1036
1037         u8         memic_bar_size[0x20];
1038
1039         u8         max_memic_size[0x20];
1040
1041         u8         steering_sw_icm_start_address[0x40];
1042
1043         u8         reserved_at_100[0x8];
1044         u8         log_header_modify_sw_icm_size[0x8];
1045         u8         reserved_at_110[0x2];
1046         u8         log_sw_icm_alloc_granularity[0x6];
1047         u8         log_steering_sw_icm_size[0x8];
1048
1049         u8         reserved_at_120[0x20];
1050
1051         u8         header_modify_sw_icm_start_address[0x40];
1052
1053         u8         reserved_at_180[0x80];
1054
1055         u8         memic_operations[0x20];
1056
1057         u8         reserved_at_220[0x5e0];
1058 };
1059
1060 struct mlx5_ifc_device_event_cap_bits {
1061         u8         user_affiliated_events[4][0x40];
1062
1063         u8         user_unaffiliated_events[4][0x40];
1064 };
1065
1066 struct mlx5_ifc_virtio_emulation_cap_bits {
1067         u8         desc_tunnel_offload_type[0x1];
1068         u8         eth_frame_offload_type[0x1];
1069         u8         virtio_version_1_0[0x1];
1070         u8         device_features_bits_mask[0xd];
1071         u8         event_mode[0x8];
1072         u8         virtio_queue_type[0x8];
1073
1074         u8         max_tunnel_desc[0x10];
1075         u8         reserved_at_30[0x3];
1076         u8         log_doorbell_stride[0x5];
1077         u8         reserved_at_38[0x3];
1078         u8         log_doorbell_bar_size[0x5];
1079
1080         u8         doorbell_bar_offset[0x40];
1081
1082         u8         max_emulated_devices[0x8];
1083         u8         max_num_virtio_queues[0x18];
1084
1085         u8         reserved_at_a0[0x60];
1086
1087         u8         umem_1_buffer_param_a[0x20];
1088
1089         u8         umem_1_buffer_param_b[0x20];
1090
1091         u8         umem_2_buffer_param_a[0x20];
1092
1093         u8         umem_2_buffer_param_b[0x20];
1094
1095         u8         umem_3_buffer_param_a[0x20];
1096
1097         u8         umem_3_buffer_param_b[0x20];
1098
1099         u8         reserved_at_1c0[0x640];
1100 };
1101
1102 enum {
1103         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1104         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1105         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1106         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1107         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1108         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1109         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1110         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1111         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1112 };
1113
1114 enum {
1115         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1116         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1117         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1118         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1119         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1120         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1121         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1122         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1123         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1124 };
1125
1126 struct mlx5_ifc_atomic_caps_bits {
1127         u8         reserved_at_0[0x40];
1128
1129         u8         atomic_req_8B_endianness_mode[0x2];
1130         u8         reserved_at_42[0x4];
1131         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1132
1133         u8         reserved_at_47[0x19];
1134
1135         u8         reserved_at_60[0x20];
1136
1137         u8         reserved_at_80[0x10];
1138         u8         atomic_operations[0x10];
1139
1140         u8         reserved_at_a0[0x10];
1141         u8         atomic_size_qp[0x10];
1142
1143         u8         reserved_at_c0[0x10];
1144         u8         atomic_size_dc[0x10];
1145
1146         u8         reserved_at_e0[0x720];
1147 };
1148
1149 struct mlx5_ifc_odp_cap_bits {
1150         u8         reserved_at_0[0x40];
1151
1152         u8         sig[0x1];
1153         u8         reserved_at_41[0x1f];
1154
1155         u8         reserved_at_60[0x20];
1156
1157         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1158
1159         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1160
1161         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1162
1163         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1164
1165         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1166
1167         u8         reserved_at_120[0x6E0];
1168 };
1169
1170 struct mlx5_ifc_calc_op {
1171         u8        reserved_at_0[0x10];
1172         u8        reserved_at_10[0x9];
1173         u8        op_swap_endianness[0x1];
1174         u8        op_min[0x1];
1175         u8        op_xor[0x1];
1176         u8        op_or[0x1];
1177         u8        op_and[0x1];
1178         u8        op_max[0x1];
1179         u8        op_add[0x1];
1180 };
1181
1182 struct mlx5_ifc_vector_calc_cap_bits {
1183         u8         calc_matrix[0x1];
1184         u8         reserved_at_1[0x1f];
1185         u8         reserved_at_20[0x8];
1186         u8         max_vec_count[0x8];
1187         u8         reserved_at_30[0xd];
1188         u8         max_chunk_size[0x3];
1189         struct mlx5_ifc_calc_op calc0;
1190         struct mlx5_ifc_calc_op calc1;
1191         struct mlx5_ifc_calc_op calc2;
1192         struct mlx5_ifc_calc_op calc3;
1193
1194         u8         reserved_at_c0[0x720];
1195 };
1196
1197 struct mlx5_ifc_tls_cap_bits {
1198         u8         tls_1_2_aes_gcm_128[0x1];
1199         u8         tls_1_3_aes_gcm_128[0x1];
1200         u8         tls_1_2_aes_gcm_256[0x1];
1201         u8         tls_1_3_aes_gcm_256[0x1];
1202         u8         reserved_at_4[0x1c];
1203
1204         u8         reserved_at_20[0x7e0];
1205 };
1206
1207 struct mlx5_ifc_ipsec_cap_bits {
1208         u8         ipsec_full_offload[0x1];
1209         u8         ipsec_crypto_offload[0x1];
1210         u8         ipsec_esn[0x1];
1211         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1212         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1213         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1214         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1215         u8         reserved_at_7[0x4];
1216         u8         log_max_ipsec_offload[0x5];
1217         u8         reserved_at_10[0x10];
1218
1219         u8         min_log_ipsec_full_replay_window[0x8];
1220         u8         max_log_ipsec_full_replay_window[0x8];
1221         u8         reserved_at_30[0x7d0];
1222 };
1223
1224 enum {
1225         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1226         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1227         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1228         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1229 };
1230
1231 enum {
1232         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1233         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1234 };
1235
1236 enum {
1237         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1238         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1239         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1240         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1241         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1242 };
1243
1244 enum {
1245         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1246         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1247         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1248         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1249         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1250         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1251 };
1252
1253 enum {
1254         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1255         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1256 };
1257
1258 enum {
1259         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1260         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1261         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1262 };
1263
1264 enum {
1265         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1266         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1267 };
1268
1269 enum {
1270         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1271         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1272         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1273 };
1274
1275 enum {
1276         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1277         MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED  = 1 << 4,
1278         mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED  = 1 << 5,
1279         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1280         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1281         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1282         MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1283         MLX5_FLEX_PARSER_GTPU_ENABLED           = 1 << 11,
1284         MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED      = 1 << 16,
1285         MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1286         MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED      = 1 << 18,
1287         MLX5_FLEX_PARSER_GTPU_TEID_ENABLED      = 1 << 19,
1288 };
1289
1290 enum {
1291         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1292         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1293 };
1294
1295 #define MLX5_FC_BULK_SIZE_FACTOR 128
1296
1297 enum mlx5_fc_bulk_alloc_bitmask {
1298         MLX5_FC_BULK_128   = (1 << 0),
1299         MLX5_FC_BULK_256   = (1 << 1),
1300         MLX5_FC_BULK_512   = (1 << 2),
1301         MLX5_FC_BULK_1024  = (1 << 3),
1302         MLX5_FC_BULK_2048  = (1 << 4),
1303         MLX5_FC_BULK_4096  = (1 << 5),
1304         MLX5_FC_BULK_8192  = (1 << 6),
1305         MLX5_FC_BULK_16384 = (1 << 7),
1306 };
1307
1308 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1309
1310 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1311
1312 enum {
1313         MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1314         MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1315 };
1316
1317 struct mlx5_ifc_cmd_hca_cap_bits {
1318         u8         reserved_at_0[0x1f];
1319         u8         vhca_resource_manager[0x1];
1320
1321         u8         hca_cap_2[0x1];
1322         u8         reserved_at_21[0x1];
1323         u8         dtor[0x1];
1324         u8         event_on_vhca_state_teardown_request[0x1];
1325         u8         event_on_vhca_state_in_use[0x1];
1326         u8         event_on_vhca_state_active[0x1];
1327         u8         event_on_vhca_state_allocated[0x1];
1328         u8         event_on_vhca_state_invalid[0x1];
1329         u8         reserved_at_28[0x8];
1330         u8         vhca_id[0x10];
1331
1332         u8         reserved_at_40[0x40];
1333
1334         u8         log_max_srq_sz[0x8];
1335         u8         log_max_qp_sz[0x8];
1336         u8         event_cap[0x1];
1337         u8         reserved_at_91[0x2];
1338         u8         isolate_vl_tc_new[0x1];
1339         u8         reserved_at_94[0x4];
1340         u8         prio_tag_required[0x1];
1341         u8         reserved_at_99[0x2];
1342         u8         log_max_qp[0x5];
1343
1344         u8         reserved_at_a0[0x3];
1345         u8         ece_support[0x1];
1346         u8         reserved_at_a4[0x5];
1347         u8         reg_c_preserve[0x1];
1348         u8         reserved_at_aa[0x1];
1349         u8         log_max_srq[0x5];
1350         u8         reserved_at_b0[0x1];
1351         u8         uplink_follow[0x1];
1352         u8         ts_cqe_to_dest_cqn[0x1];
1353         u8         reserved_at_b3[0xd];
1354
1355         u8         max_sgl_for_optimized_performance[0x8];
1356         u8         log_max_cq_sz[0x8];
1357         u8         relaxed_ordering_write_umr[0x1];
1358         u8         relaxed_ordering_read_umr[0x1];
1359         u8         reserved_at_d2[0x7];
1360         u8         virtio_net_device_emualtion_manager[0x1];
1361         u8         virtio_blk_device_emualtion_manager[0x1];
1362         u8         log_max_cq[0x5];
1363
1364         u8         log_max_eq_sz[0x8];
1365         u8         relaxed_ordering_write[0x1];
1366         u8         relaxed_ordering_read[0x1];
1367         u8         log_max_mkey[0x6];
1368         u8         reserved_at_f0[0x8];
1369         u8         dump_fill_mkey[0x1];
1370         u8         reserved_at_f9[0x2];
1371         u8         fast_teardown[0x1];
1372         u8         log_max_eq[0x4];
1373
1374         u8         max_indirection[0x8];
1375         u8         fixed_buffer_size[0x1];
1376         u8         log_max_mrw_sz[0x7];
1377         u8         force_teardown[0x1];
1378         u8         reserved_at_111[0x1];
1379         u8         log_max_bsf_list_size[0x6];
1380         u8         umr_extended_translation_offset[0x1];
1381         u8         null_mkey[0x1];
1382         u8         log_max_klm_list_size[0x6];
1383
1384         u8         reserved_at_120[0xa];
1385         u8         log_max_ra_req_dc[0x6];
1386         u8         reserved_at_130[0xa];
1387         u8         log_max_ra_res_dc[0x6];
1388
1389         u8         reserved_at_140[0x6];
1390         u8         release_all_pages[0x1];
1391         u8         reserved_at_147[0x2];
1392         u8         roce_accl[0x1];
1393         u8         log_max_ra_req_qp[0x6];
1394         u8         reserved_at_150[0xa];
1395         u8         log_max_ra_res_qp[0x6];
1396
1397         u8         end_pad[0x1];
1398         u8         cc_query_allowed[0x1];
1399         u8         cc_modify_allowed[0x1];
1400         u8         start_pad[0x1];
1401         u8         cache_line_128byte[0x1];
1402         u8         reserved_at_165[0x4];
1403         u8         rts2rts_qp_counters_set_id[0x1];
1404         u8         reserved_at_16a[0x2];
1405         u8         vnic_env_int_rq_oob[0x1];
1406         u8         sbcam_reg[0x1];
1407         u8         reserved_at_16e[0x1];
1408         u8         qcam_reg[0x1];
1409         u8         gid_table_size[0x10];
1410
1411         u8         out_of_seq_cnt[0x1];
1412         u8         vport_counters[0x1];
1413         u8         retransmission_q_counters[0x1];
1414         u8         debug[0x1];
1415         u8         modify_rq_counter_set_id[0x1];
1416         u8         rq_delay_drop[0x1];
1417         u8         max_qp_cnt[0xa];
1418         u8         pkey_table_size[0x10];
1419
1420         u8         vport_group_manager[0x1];
1421         u8         vhca_group_manager[0x1];
1422         u8         ib_virt[0x1];
1423         u8         eth_virt[0x1];
1424         u8         vnic_env_queue_counters[0x1];
1425         u8         ets[0x1];
1426         u8         nic_flow_table[0x1];
1427         u8         eswitch_manager[0x1];
1428         u8         device_memory[0x1];
1429         u8         mcam_reg[0x1];
1430         u8         pcam_reg[0x1];
1431         u8         local_ca_ack_delay[0x5];
1432         u8         port_module_event[0x1];
1433         u8         enhanced_error_q_counters[0x1];
1434         u8         ports_check[0x1];
1435         u8         reserved_at_1b3[0x1];
1436         u8         disable_link_up[0x1];
1437         u8         beacon_led[0x1];
1438         u8         port_type[0x2];
1439         u8         num_ports[0x8];
1440
1441         u8         reserved_at_1c0[0x1];
1442         u8         pps[0x1];
1443         u8         pps_modify[0x1];
1444         u8         log_max_msg[0x5];
1445         u8         reserved_at_1c8[0x4];
1446         u8         max_tc[0x4];
1447         u8         temp_warn_event[0x1];
1448         u8         dcbx[0x1];
1449         u8         general_notification_event[0x1];
1450         u8         reserved_at_1d3[0x2];
1451         u8         fpga[0x1];
1452         u8         rol_s[0x1];
1453         u8         rol_g[0x1];
1454         u8         reserved_at_1d8[0x1];
1455         u8         wol_s[0x1];
1456         u8         wol_g[0x1];
1457         u8         wol_a[0x1];
1458         u8         wol_b[0x1];
1459         u8         wol_m[0x1];
1460         u8         wol_u[0x1];
1461         u8         wol_p[0x1];
1462
1463         u8         stat_rate_support[0x10];
1464         u8         reserved_at_1f0[0x1];
1465         u8         pci_sync_for_fw_update_event[0x1];
1466         u8         reserved_at_1f2[0x6];
1467         u8         init2_lag_tx_port_affinity[0x1];
1468         u8         reserved_at_1fa[0x3];
1469         u8         cqe_version[0x4];
1470
1471         u8         compact_address_vector[0x1];
1472         u8         striding_rq[0x1];
1473         u8         reserved_at_202[0x1];
1474         u8         ipoib_enhanced_offloads[0x1];
1475         u8         ipoib_basic_offloads[0x1];
1476         u8         reserved_at_205[0x1];
1477         u8         repeated_block_disabled[0x1];
1478         u8         umr_modify_entity_size_disabled[0x1];
1479         u8         umr_modify_atomic_disabled[0x1];
1480         u8         umr_indirect_mkey_disabled[0x1];
1481         u8         umr_fence[0x2];
1482         u8         dc_req_scat_data_cqe[0x1];
1483         u8         reserved_at_20d[0x2];
1484         u8         drain_sigerr[0x1];
1485         u8         cmdif_checksum[0x2];
1486         u8         sigerr_cqe[0x1];
1487         u8         reserved_at_213[0x1];
1488         u8         wq_signature[0x1];
1489         u8         sctr_data_cqe[0x1];
1490         u8         reserved_at_216[0x1];
1491         u8         sho[0x1];
1492         u8         tph[0x1];
1493         u8         rf[0x1];
1494         u8         dct[0x1];
1495         u8         qos[0x1];
1496         u8         eth_net_offloads[0x1];
1497         u8         roce[0x1];
1498         u8         atomic[0x1];
1499         u8         reserved_at_21f[0x1];
1500
1501         u8         cq_oi[0x1];
1502         u8         cq_resize[0x1];
1503         u8         cq_moderation[0x1];
1504         u8         reserved_at_223[0x3];
1505         u8         cq_eq_remap[0x1];
1506         u8         pg[0x1];
1507         u8         block_lb_mc[0x1];
1508         u8         reserved_at_229[0x1];
1509         u8         scqe_break_moderation[0x1];
1510         u8         cq_period_start_from_cqe[0x1];
1511         u8         cd[0x1];
1512         u8         reserved_at_22d[0x1];
1513         u8         apm[0x1];
1514         u8         vector_calc[0x1];
1515         u8         umr_ptr_rlky[0x1];
1516         u8         imaicl[0x1];
1517         u8         qp_packet_based[0x1];
1518         u8         reserved_at_233[0x3];
1519         u8         qkv[0x1];
1520         u8         pkv[0x1];
1521         u8         set_deth_sqpn[0x1];
1522         u8         reserved_at_239[0x3];
1523         u8         xrc[0x1];
1524         u8         ud[0x1];
1525         u8         uc[0x1];
1526         u8         rc[0x1];
1527
1528         u8         uar_4k[0x1];
1529         u8         reserved_at_241[0x9];
1530         u8         uar_sz[0x6];
1531         u8         port_selection_cap[0x1];
1532         u8         reserved_at_248[0x1];
1533         u8         umem_uid_0[0x1];
1534         u8         reserved_at_250[0x5];
1535         u8         log_pg_sz[0x8];
1536
1537         u8         bf[0x1];
1538         u8         driver_version[0x1];
1539         u8         pad_tx_eth_packet[0x1];
1540         u8         reserved_at_263[0x3];
1541         u8         mkey_by_name[0x1];
1542         u8         reserved_at_267[0x4];
1543
1544         u8         log_bf_reg_size[0x5];
1545
1546         u8         reserved_at_270[0x6];
1547         u8         lag_dct[0x2];
1548         u8         lag_tx_port_affinity[0x1];
1549         u8         lag_native_fdb_selection[0x1];
1550         u8         reserved_at_27a[0x1];
1551         u8         lag_master[0x1];
1552         u8         num_lag_ports[0x4];
1553
1554         u8         reserved_at_280[0x10];
1555         u8         max_wqe_sz_sq[0x10];
1556
1557         u8         reserved_at_2a0[0x10];
1558         u8         max_wqe_sz_rq[0x10];
1559
1560         u8         max_flow_counter_31_16[0x10];
1561         u8         max_wqe_sz_sq_dc[0x10];
1562
1563         u8         reserved_at_2e0[0x7];
1564         u8         max_qp_mcg[0x19];
1565
1566         u8         reserved_at_300[0x10];
1567         u8         flow_counter_bulk_alloc[0x8];
1568         u8         log_max_mcg[0x8];
1569
1570         u8         reserved_at_320[0x3];
1571         u8         log_max_transport_domain[0x5];
1572         u8         reserved_at_328[0x3];
1573         u8         log_max_pd[0x5];
1574         u8         reserved_at_330[0xb];
1575         u8         log_max_xrcd[0x5];
1576
1577         u8         nic_receive_steering_discard[0x1];
1578         u8         receive_discard_vport_down[0x1];
1579         u8         transmit_discard_vport_down[0x1];
1580         u8         reserved_at_343[0x5];
1581         u8         log_max_flow_counter_bulk[0x8];
1582         u8         max_flow_counter_15_0[0x10];
1583
1584
1585         u8         reserved_at_360[0x3];
1586         u8         log_max_rq[0x5];
1587         u8         reserved_at_368[0x3];
1588         u8         log_max_sq[0x5];
1589         u8         reserved_at_370[0x3];
1590         u8         log_max_tir[0x5];
1591         u8         reserved_at_378[0x3];
1592         u8         log_max_tis[0x5];
1593
1594         u8         basic_cyclic_rcv_wqe[0x1];
1595         u8         reserved_at_381[0x2];
1596         u8         log_max_rmp[0x5];
1597         u8         reserved_at_388[0x3];
1598         u8         log_max_rqt[0x5];
1599         u8         reserved_at_390[0x3];
1600         u8         log_max_rqt_size[0x5];
1601         u8         reserved_at_398[0x3];
1602         u8         log_max_tis_per_sq[0x5];
1603
1604         u8         ext_stride_num_range[0x1];
1605         u8         roce_rw_supported[0x1];
1606         u8         reserved_at_3a2[0x1];
1607         u8         log_max_stride_sz_rq[0x5];
1608         u8         reserved_at_3a8[0x3];
1609         u8         log_min_stride_sz_rq[0x5];
1610         u8         reserved_at_3b0[0x3];
1611         u8         log_max_stride_sz_sq[0x5];
1612         u8         reserved_at_3b8[0x3];
1613         u8         log_min_stride_sz_sq[0x5];
1614
1615         u8         hairpin[0x1];
1616         u8         reserved_at_3c1[0x2];
1617         u8         log_max_hairpin_queues[0x5];
1618         u8         reserved_at_3c8[0x3];
1619         u8         log_max_hairpin_wq_data_sz[0x5];
1620         u8         reserved_at_3d0[0x3];
1621         u8         log_max_hairpin_num_packets[0x5];
1622         u8         reserved_at_3d8[0x3];
1623         u8         log_max_wq_sz[0x5];
1624
1625         u8         nic_vport_change_event[0x1];
1626         u8         disable_local_lb_uc[0x1];
1627         u8         disable_local_lb_mc[0x1];
1628         u8         log_min_hairpin_wq_data_sz[0x5];
1629         u8         reserved_at_3e8[0x2];
1630         u8         vhca_state[0x1];
1631         u8         log_max_vlan_list[0x5];
1632         u8         reserved_at_3f0[0x3];
1633         u8         log_max_current_mc_list[0x5];
1634         u8         reserved_at_3f8[0x3];
1635         u8         log_max_current_uc_list[0x5];
1636
1637         u8         general_obj_types[0x40];
1638
1639         u8         sq_ts_format[0x2];
1640         u8         rq_ts_format[0x2];
1641         u8         steering_format_version[0x4];
1642         u8         create_qp_start_hint[0x18];
1643
1644         u8         reserved_at_460[0x3];
1645         u8         log_max_uctx[0x5];
1646         u8         reserved_at_468[0x2];
1647         u8         ipsec_offload[0x1];
1648         u8         log_max_umem[0x5];
1649         u8         max_num_eqs[0x10];
1650
1651         u8         reserved_at_480[0x1];
1652         u8         tls_tx[0x1];
1653         u8         tls_rx[0x1];
1654         u8         log_max_l2_table[0x5];
1655         u8         reserved_at_488[0x8];
1656         u8         log_uar_page_sz[0x10];
1657
1658         u8         reserved_at_4a0[0x20];
1659         u8         device_frequency_mhz[0x20];
1660         u8         device_frequency_khz[0x20];
1661
1662         u8         reserved_at_500[0x20];
1663         u8         num_of_uars_per_page[0x20];
1664
1665         u8         flex_parser_protocols[0x20];
1666
1667         u8         max_geneve_tlv_options[0x8];
1668         u8         reserved_at_568[0x3];
1669         u8         max_geneve_tlv_option_data_len[0x5];
1670         u8         reserved_at_570[0x10];
1671
1672         u8         reserved_at_580[0xb];
1673         u8         log_max_dci_stream_channels[0x5];
1674         u8         reserved_at_590[0x3];
1675         u8         log_max_dci_errored_streams[0x5];
1676         u8         reserved_at_598[0x8];
1677
1678         u8         reserved_at_5a0[0x13];
1679         u8         log_max_dek[0x5];
1680         u8         reserved_at_5b8[0x4];
1681         u8         mini_cqe_resp_stride_index[0x1];
1682         u8         cqe_128_always[0x1];
1683         u8         cqe_compression_128[0x1];
1684         u8         cqe_compression[0x1];
1685
1686         u8         cqe_compression_timeout[0x10];
1687         u8         cqe_compression_max_num[0x10];
1688
1689         u8         reserved_at_5e0[0x8];
1690         u8         flex_parser_id_gtpu_dw_0[0x4];
1691         u8         reserved_at_5ec[0x4];
1692         u8         tag_matching[0x1];
1693         u8         rndv_offload_rc[0x1];
1694         u8         rndv_offload_dc[0x1];
1695         u8         log_tag_matching_list_sz[0x5];
1696         u8         reserved_at_5f8[0x3];
1697         u8         log_max_xrq[0x5];
1698
1699         u8         affiliate_nic_vport_criteria[0x8];
1700         u8         native_port_num[0x8];
1701         u8         num_vhca_ports[0x8];
1702         u8         flex_parser_id_gtpu_teid[0x4];
1703         u8         reserved_at_61c[0x2];
1704         u8         sw_owner_id[0x1];
1705         u8         reserved_at_61f[0x1];
1706
1707         u8         max_num_of_monitor_counters[0x10];
1708         u8         num_ppcnt_monitor_counters[0x10];
1709
1710         u8         max_num_sf[0x10];
1711         u8         num_q_monitor_counters[0x10];
1712
1713         u8         reserved_at_660[0x20];
1714
1715         u8         sf[0x1];
1716         u8         sf_set_partition[0x1];
1717         u8         reserved_at_682[0x1];
1718         u8         log_max_sf[0x5];
1719         u8         apu[0x1];
1720         u8         reserved_at_689[0x7];
1721         u8         log_min_sf_size[0x8];
1722         u8         max_num_sf_partitions[0x8];
1723
1724         u8         uctx_cap[0x20];
1725
1726         u8         reserved_at_6c0[0x4];
1727         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1728         u8         flex_parser_id_icmp_dw1[0x4];
1729         u8         flex_parser_id_icmp_dw0[0x4];
1730         u8         flex_parser_id_icmpv6_dw1[0x4];
1731         u8         flex_parser_id_icmpv6_dw0[0x4];
1732         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1733         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1734
1735         u8         max_num_match_definer[0x10];
1736         u8         sf_base_id[0x10];
1737
1738         u8         flex_parser_id_gtpu_dw_2[0x4];
1739         u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1740         u8         num_total_dynamic_vf_msix[0x18];
1741         u8         reserved_at_720[0x14];
1742         u8         dynamic_msix_table_size[0xc];
1743         u8         reserved_at_740[0xc];
1744         u8         min_dynamic_vf_msix_table_size[0x4];
1745         u8         reserved_at_750[0x4];
1746         u8         max_dynamic_vf_msix_table_size[0xc];
1747
1748         u8         reserved_at_760[0x20];
1749         u8         vhca_tunnel_commands[0x40];
1750         u8         match_definer_format_supported[0x40];
1751 };
1752
1753 struct mlx5_ifc_cmd_hca_cap_2_bits {
1754         u8         reserved_at_0[0xa0];
1755
1756         u8         max_reformat_insert_size[0x8];
1757         u8         max_reformat_insert_offset[0x8];
1758         u8         max_reformat_remove_size[0x8];
1759         u8         max_reformat_remove_offset[0x8];
1760
1761         u8         reserved_at_c0[0x740];
1762 };
1763
1764 enum mlx5_flow_destination_type {
1765         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1766         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1767         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1768         MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1769         MLX5_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1770
1771         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1772         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1773         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1774 };
1775
1776 enum mlx5_flow_table_miss_action {
1777         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1778         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1779         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1780 };
1781
1782 struct mlx5_ifc_dest_format_struct_bits {
1783         u8         destination_type[0x8];
1784         u8         destination_id[0x18];
1785
1786         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1787         u8         packet_reformat[0x1];
1788         u8         reserved_at_22[0xe];
1789         u8         destination_eswitch_owner_vhca_id[0x10];
1790 };
1791
1792 struct mlx5_ifc_flow_counter_list_bits {
1793         u8         flow_counter_id[0x20];
1794
1795         u8         reserved_at_20[0x20];
1796 };
1797
1798 struct mlx5_ifc_extended_dest_format_bits {
1799         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1800
1801         u8         packet_reformat_id[0x20];
1802
1803         u8         reserved_at_60[0x20];
1804 };
1805
1806 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1807         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1808         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1809 };
1810
1811 struct mlx5_ifc_fte_match_param_bits {
1812         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1813
1814         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1815
1816         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1817
1818         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1819
1820         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1821
1822         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1823
1824         u8         reserved_at_c00[0x400];
1825 };
1826
1827 enum {
1828         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1829         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1830         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1831         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1832         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1833 };
1834
1835 struct mlx5_ifc_rx_hash_field_select_bits {
1836         u8         l3_prot_type[0x1];
1837         u8         l4_prot_type[0x1];
1838         u8         selected_fields[0x1e];
1839 };
1840
1841 enum {
1842         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1843         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1844 };
1845
1846 enum {
1847         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1848         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1849 };
1850
1851 struct mlx5_ifc_wq_bits {
1852         u8         wq_type[0x4];
1853         u8         wq_signature[0x1];
1854         u8         end_padding_mode[0x2];
1855         u8         cd_slave[0x1];
1856         u8         reserved_at_8[0x18];
1857
1858         u8         hds_skip_first_sge[0x1];
1859         u8         log2_hds_buf_size[0x3];
1860         u8         reserved_at_24[0x7];
1861         u8         page_offset[0x5];
1862         u8         lwm[0x10];
1863
1864         u8         reserved_at_40[0x8];
1865         u8         pd[0x18];
1866
1867         u8         reserved_at_60[0x8];
1868         u8         uar_page[0x18];
1869
1870         u8         dbr_addr[0x40];
1871
1872         u8         hw_counter[0x20];
1873
1874         u8         sw_counter[0x20];
1875
1876         u8         reserved_at_100[0xc];
1877         u8         log_wq_stride[0x4];
1878         u8         reserved_at_110[0x3];
1879         u8         log_wq_pg_sz[0x5];
1880         u8         reserved_at_118[0x3];
1881         u8         log_wq_sz[0x5];
1882
1883         u8         dbr_umem_valid[0x1];
1884         u8         wq_umem_valid[0x1];
1885         u8         reserved_at_122[0x1];
1886         u8         log_hairpin_num_packets[0x5];
1887         u8         reserved_at_128[0x3];
1888         u8         log_hairpin_data_sz[0x5];
1889
1890         u8         reserved_at_130[0x4];
1891         u8         log_wqe_num_of_strides[0x4];
1892         u8         two_byte_shift_en[0x1];
1893         u8         reserved_at_139[0x4];
1894         u8         log_wqe_stride_size[0x3];
1895
1896         u8         reserved_at_140[0x4c0];
1897
1898         struct mlx5_ifc_cmd_pas_bits pas[];
1899 };
1900
1901 struct mlx5_ifc_rq_num_bits {
1902         u8         reserved_at_0[0x8];
1903         u8         rq_num[0x18];
1904 };
1905
1906 struct mlx5_ifc_mac_address_layout_bits {
1907         u8         reserved_at_0[0x10];
1908         u8         mac_addr_47_32[0x10];
1909
1910         u8         mac_addr_31_0[0x20];
1911 };
1912
1913 struct mlx5_ifc_vlan_layout_bits {
1914         u8         reserved_at_0[0x14];
1915         u8         vlan[0x0c];
1916
1917         u8         reserved_at_20[0x20];
1918 };
1919
1920 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1921         u8         reserved_at_0[0xa0];
1922
1923         u8         min_time_between_cnps[0x20];
1924
1925         u8         reserved_at_c0[0x12];
1926         u8         cnp_dscp[0x6];
1927         u8         reserved_at_d8[0x4];
1928         u8         cnp_prio_mode[0x1];
1929         u8         cnp_802p_prio[0x3];
1930
1931         u8         reserved_at_e0[0x720];
1932 };
1933
1934 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1935         u8         reserved_at_0[0x60];
1936
1937         u8         reserved_at_60[0x4];
1938         u8         clamp_tgt_rate[0x1];
1939         u8         reserved_at_65[0x3];
1940         u8         clamp_tgt_rate_after_time_inc[0x1];
1941         u8         reserved_at_69[0x17];
1942
1943         u8         reserved_at_80[0x20];
1944
1945         u8         rpg_time_reset[0x20];
1946
1947         u8         rpg_byte_reset[0x20];
1948
1949         u8         rpg_threshold[0x20];
1950
1951         u8         rpg_max_rate[0x20];
1952
1953         u8         rpg_ai_rate[0x20];
1954
1955         u8         rpg_hai_rate[0x20];
1956
1957         u8         rpg_gd[0x20];
1958
1959         u8         rpg_min_dec_fac[0x20];
1960
1961         u8         rpg_min_rate[0x20];
1962
1963         u8         reserved_at_1c0[0xe0];
1964
1965         u8         rate_to_set_on_first_cnp[0x20];
1966
1967         u8         dce_tcp_g[0x20];
1968
1969         u8         dce_tcp_rtt[0x20];
1970
1971         u8         rate_reduce_monitor_period[0x20];
1972
1973         u8         reserved_at_320[0x20];
1974
1975         u8         initial_alpha_value[0x20];
1976
1977         u8         reserved_at_360[0x4a0];
1978 };
1979
1980 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1981         u8         reserved_at_0[0x80];
1982
1983         u8         rppp_max_rps[0x20];
1984
1985         u8         rpg_time_reset[0x20];
1986
1987         u8         rpg_byte_reset[0x20];
1988
1989         u8         rpg_threshold[0x20];
1990
1991         u8         rpg_max_rate[0x20];
1992
1993         u8         rpg_ai_rate[0x20];
1994
1995         u8         rpg_hai_rate[0x20];
1996
1997         u8         rpg_gd[0x20];
1998
1999         u8         rpg_min_dec_fac[0x20];
2000
2001         u8         rpg_min_rate[0x20];
2002
2003         u8         reserved_at_1c0[0x640];
2004 };
2005
2006 enum {
2007         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2008         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2009         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2010 };
2011
2012 struct mlx5_ifc_resize_field_select_bits {
2013         u8         resize_field_select[0x20];
2014 };
2015
2016 struct mlx5_ifc_resource_dump_bits {
2017         u8         more_dump[0x1];
2018         u8         inline_dump[0x1];
2019         u8         reserved_at_2[0xa];
2020         u8         seq_num[0x4];
2021         u8         segment_type[0x10];
2022
2023         u8         reserved_at_20[0x10];
2024         u8         vhca_id[0x10];
2025
2026         u8         index1[0x20];
2027
2028         u8         index2[0x20];
2029
2030         u8         num_of_obj1[0x10];
2031         u8         num_of_obj2[0x10];
2032
2033         u8         reserved_at_a0[0x20];
2034
2035         u8         device_opaque[0x40];
2036
2037         u8         mkey[0x20];
2038
2039         u8         size[0x20];
2040
2041         u8         address[0x40];
2042
2043         u8         inline_data[52][0x20];
2044 };
2045
2046 struct mlx5_ifc_resource_dump_menu_record_bits {
2047         u8         reserved_at_0[0x4];
2048         u8         num_of_obj2_supports_active[0x1];
2049         u8         num_of_obj2_supports_all[0x1];
2050         u8         must_have_num_of_obj2[0x1];
2051         u8         support_num_of_obj2[0x1];
2052         u8         num_of_obj1_supports_active[0x1];
2053         u8         num_of_obj1_supports_all[0x1];
2054         u8         must_have_num_of_obj1[0x1];
2055         u8         support_num_of_obj1[0x1];
2056         u8         must_have_index2[0x1];
2057         u8         support_index2[0x1];
2058         u8         must_have_index1[0x1];
2059         u8         support_index1[0x1];
2060         u8         segment_type[0x10];
2061
2062         u8         segment_name[4][0x20];
2063
2064         u8         index1_name[4][0x20];
2065
2066         u8         index2_name[4][0x20];
2067 };
2068
2069 struct mlx5_ifc_resource_dump_segment_header_bits {
2070         u8         length_dw[0x10];
2071         u8         segment_type[0x10];
2072 };
2073
2074 struct mlx5_ifc_resource_dump_command_segment_bits {
2075         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2076
2077         u8         segment_called[0x10];
2078         u8         vhca_id[0x10];
2079
2080         u8         index1[0x20];
2081
2082         u8         index2[0x20];
2083
2084         u8         num_of_obj1[0x10];
2085         u8         num_of_obj2[0x10];
2086 };
2087
2088 struct mlx5_ifc_resource_dump_error_segment_bits {
2089         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2090
2091         u8         reserved_at_20[0x10];
2092         u8         syndrome_id[0x10];
2093
2094         u8         reserved_at_40[0x40];
2095
2096         u8         error[8][0x20];
2097 };
2098
2099 struct mlx5_ifc_resource_dump_info_segment_bits {
2100         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2101
2102         u8         reserved_at_20[0x18];
2103         u8         dump_version[0x8];
2104
2105         u8         hw_version[0x20];
2106
2107         u8         fw_version[0x20];
2108 };
2109
2110 struct mlx5_ifc_resource_dump_menu_segment_bits {
2111         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2112
2113         u8         reserved_at_20[0x10];
2114         u8         num_of_records[0x10];
2115
2116         struct mlx5_ifc_resource_dump_menu_record_bits record[];
2117 };
2118
2119 struct mlx5_ifc_resource_dump_resource_segment_bits {
2120         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2121
2122         u8         reserved_at_20[0x20];
2123
2124         u8         index1[0x20];
2125
2126         u8         index2[0x20];
2127
2128         u8         payload[][0x20];
2129 };
2130
2131 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2132         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2133 };
2134
2135 struct mlx5_ifc_menu_resource_dump_response_bits {
2136         struct mlx5_ifc_resource_dump_info_segment_bits info;
2137         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2138         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2139         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2140 };
2141
2142 enum {
2143         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2144         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2145         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2146         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2147 };
2148
2149 struct mlx5_ifc_modify_field_select_bits {
2150         u8         modify_field_select[0x20];
2151 };
2152
2153 struct mlx5_ifc_field_select_r_roce_np_bits {
2154         u8         field_select_r_roce_np[0x20];
2155 };
2156
2157 struct mlx5_ifc_field_select_r_roce_rp_bits {
2158         u8         field_select_r_roce_rp[0x20];
2159 };
2160
2161 enum {
2162         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2163         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2164         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2165         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2166         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2167         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2168         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2169         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2170         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2171         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2172 };
2173
2174 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2175         u8         field_select_8021qaurp[0x20];
2176 };
2177
2178 struct mlx5_ifc_phys_layer_cntrs_bits {
2179         u8         time_since_last_clear_high[0x20];
2180
2181         u8         time_since_last_clear_low[0x20];
2182
2183         u8         symbol_errors_high[0x20];
2184
2185         u8         symbol_errors_low[0x20];
2186
2187         u8         sync_headers_errors_high[0x20];
2188
2189         u8         sync_headers_errors_low[0x20];
2190
2191         u8         edpl_bip_errors_lane0_high[0x20];
2192
2193         u8         edpl_bip_errors_lane0_low[0x20];
2194
2195         u8         edpl_bip_errors_lane1_high[0x20];
2196
2197         u8         edpl_bip_errors_lane1_low[0x20];
2198
2199         u8         edpl_bip_errors_lane2_high[0x20];
2200
2201         u8         edpl_bip_errors_lane2_low[0x20];
2202
2203         u8         edpl_bip_errors_lane3_high[0x20];
2204
2205         u8         edpl_bip_errors_lane3_low[0x20];
2206
2207         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2208
2209         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2210
2211         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2212
2213         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2214
2215         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2216
2217         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2218
2219         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2220
2221         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2222
2223         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2224
2225         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2226
2227         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2228
2229         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2230
2231         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2232
2233         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2234
2235         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2236
2237         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2238
2239         u8         rs_fec_corrected_blocks_high[0x20];
2240
2241         u8         rs_fec_corrected_blocks_low[0x20];
2242
2243         u8         rs_fec_uncorrectable_blocks_high[0x20];
2244
2245         u8         rs_fec_uncorrectable_blocks_low[0x20];
2246
2247         u8         rs_fec_no_errors_blocks_high[0x20];
2248
2249         u8         rs_fec_no_errors_blocks_low[0x20];
2250
2251         u8         rs_fec_single_error_blocks_high[0x20];
2252
2253         u8         rs_fec_single_error_blocks_low[0x20];
2254
2255         u8         rs_fec_corrected_symbols_total_high[0x20];
2256
2257         u8         rs_fec_corrected_symbols_total_low[0x20];
2258
2259         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2260
2261         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2262
2263         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2264
2265         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2266
2267         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2268
2269         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2270
2271         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2272
2273         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2274
2275         u8         link_down_events[0x20];
2276
2277         u8         successful_recovery_events[0x20];
2278
2279         u8         reserved_at_640[0x180];
2280 };
2281
2282 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2283         u8         time_since_last_clear_high[0x20];
2284
2285         u8         time_since_last_clear_low[0x20];
2286
2287         u8         phy_received_bits_high[0x20];
2288
2289         u8         phy_received_bits_low[0x20];
2290
2291         u8         phy_symbol_errors_high[0x20];
2292
2293         u8         phy_symbol_errors_low[0x20];
2294
2295         u8         phy_corrected_bits_high[0x20];
2296
2297         u8         phy_corrected_bits_low[0x20];
2298
2299         u8         phy_corrected_bits_lane0_high[0x20];
2300
2301         u8         phy_corrected_bits_lane0_low[0x20];
2302
2303         u8         phy_corrected_bits_lane1_high[0x20];
2304
2305         u8         phy_corrected_bits_lane1_low[0x20];
2306
2307         u8         phy_corrected_bits_lane2_high[0x20];
2308
2309         u8         phy_corrected_bits_lane2_low[0x20];
2310
2311         u8         phy_corrected_bits_lane3_high[0x20];
2312
2313         u8         phy_corrected_bits_lane3_low[0x20];
2314
2315         u8         reserved_at_200[0x5c0];
2316 };
2317
2318 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2319         u8         symbol_error_counter[0x10];
2320
2321         u8         link_error_recovery_counter[0x8];
2322
2323         u8         link_downed_counter[0x8];
2324
2325         u8         port_rcv_errors[0x10];
2326
2327         u8         port_rcv_remote_physical_errors[0x10];
2328
2329         u8         port_rcv_switch_relay_errors[0x10];
2330
2331         u8         port_xmit_discards[0x10];
2332
2333         u8         port_xmit_constraint_errors[0x8];
2334
2335         u8         port_rcv_constraint_errors[0x8];
2336
2337         u8         reserved_at_70[0x8];
2338
2339         u8         link_overrun_errors[0x8];
2340
2341         u8         reserved_at_80[0x10];
2342
2343         u8         vl_15_dropped[0x10];
2344
2345         u8         reserved_at_a0[0x80];
2346
2347         u8         port_xmit_wait[0x20];
2348 };
2349
2350 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2351         u8         transmit_queue_high[0x20];
2352
2353         u8         transmit_queue_low[0x20];
2354
2355         u8         no_buffer_discard_uc_high[0x20];
2356
2357         u8         no_buffer_discard_uc_low[0x20];
2358
2359         u8         reserved_at_80[0x740];
2360 };
2361
2362 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2363         u8         wred_discard_high[0x20];
2364
2365         u8         wred_discard_low[0x20];
2366
2367         u8         ecn_marked_tc_high[0x20];
2368
2369         u8         ecn_marked_tc_low[0x20];
2370
2371         u8         reserved_at_80[0x740];
2372 };
2373
2374 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2375         u8         rx_octets_high[0x20];
2376
2377         u8         rx_octets_low[0x20];
2378
2379         u8         reserved_at_40[0xc0];
2380
2381         u8         rx_frames_high[0x20];
2382
2383         u8         rx_frames_low[0x20];
2384
2385         u8         tx_octets_high[0x20];
2386
2387         u8         tx_octets_low[0x20];
2388
2389         u8         reserved_at_180[0xc0];
2390
2391         u8         tx_frames_high[0x20];
2392
2393         u8         tx_frames_low[0x20];
2394
2395         u8         rx_pause_high[0x20];
2396
2397         u8         rx_pause_low[0x20];
2398
2399         u8         rx_pause_duration_high[0x20];
2400
2401         u8         rx_pause_duration_low[0x20];
2402
2403         u8         tx_pause_high[0x20];
2404
2405         u8         tx_pause_low[0x20];
2406
2407         u8         tx_pause_duration_high[0x20];
2408
2409         u8         tx_pause_duration_low[0x20];
2410
2411         u8         rx_pause_transition_high[0x20];
2412
2413         u8         rx_pause_transition_low[0x20];
2414
2415         u8         rx_discards_high[0x20];
2416
2417         u8         rx_discards_low[0x20];
2418
2419         u8         device_stall_minor_watermark_cnt_high[0x20];
2420
2421         u8         device_stall_minor_watermark_cnt_low[0x20];
2422
2423         u8         device_stall_critical_watermark_cnt_high[0x20];
2424
2425         u8         device_stall_critical_watermark_cnt_low[0x20];
2426
2427         u8         reserved_at_480[0x340];
2428 };
2429
2430 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2431         u8         port_transmit_wait_high[0x20];
2432
2433         u8         port_transmit_wait_low[0x20];
2434
2435         u8         reserved_at_40[0x100];
2436
2437         u8         rx_buffer_almost_full_high[0x20];
2438
2439         u8         rx_buffer_almost_full_low[0x20];
2440
2441         u8         rx_buffer_full_high[0x20];
2442
2443         u8         rx_buffer_full_low[0x20];
2444
2445         u8         rx_icrc_encapsulated_high[0x20];
2446
2447         u8         rx_icrc_encapsulated_low[0x20];
2448
2449         u8         reserved_at_200[0x5c0];
2450 };
2451
2452 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2453         u8         dot3stats_alignment_errors_high[0x20];
2454
2455         u8         dot3stats_alignment_errors_low[0x20];
2456
2457         u8         dot3stats_fcs_errors_high[0x20];
2458
2459         u8         dot3stats_fcs_errors_low[0x20];
2460
2461         u8         dot3stats_single_collision_frames_high[0x20];
2462
2463         u8         dot3stats_single_collision_frames_low[0x20];
2464
2465         u8         dot3stats_multiple_collision_frames_high[0x20];
2466
2467         u8         dot3stats_multiple_collision_frames_low[0x20];
2468
2469         u8         dot3stats_sqe_test_errors_high[0x20];
2470
2471         u8         dot3stats_sqe_test_errors_low[0x20];
2472
2473         u8         dot3stats_deferred_transmissions_high[0x20];
2474
2475         u8         dot3stats_deferred_transmissions_low[0x20];
2476
2477         u8         dot3stats_late_collisions_high[0x20];
2478
2479         u8         dot3stats_late_collisions_low[0x20];
2480
2481         u8         dot3stats_excessive_collisions_high[0x20];
2482
2483         u8         dot3stats_excessive_collisions_low[0x20];
2484
2485         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2486
2487         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2488
2489         u8         dot3stats_carrier_sense_errors_high[0x20];
2490
2491         u8         dot3stats_carrier_sense_errors_low[0x20];
2492
2493         u8         dot3stats_frame_too_longs_high[0x20];
2494
2495         u8         dot3stats_frame_too_longs_low[0x20];
2496
2497         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2498
2499         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2500
2501         u8         dot3stats_symbol_errors_high[0x20];
2502
2503         u8         dot3stats_symbol_errors_low[0x20];
2504
2505         u8         dot3control_in_unknown_opcodes_high[0x20];
2506
2507         u8         dot3control_in_unknown_opcodes_low[0x20];
2508
2509         u8         dot3in_pause_frames_high[0x20];
2510
2511         u8         dot3in_pause_frames_low[0x20];
2512
2513         u8         dot3out_pause_frames_high[0x20];
2514
2515         u8         dot3out_pause_frames_low[0x20];
2516
2517         u8         reserved_at_400[0x3c0];
2518 };
2519
2520 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2521         u8         ether_stats_drop_events_high[0x20];
2522
2523         u8         ether_stats_drop_events_low[0x20];
2524
2525         u8         ether_stats_octets_high[0x20];
2526
2527         u8         ether_stats_octets_low[0x20];
2528
2529         u8         ether_stats_pkts_high[0x20];
2530
2531         u8         ether_stats_pkts_low[0x20];
2532
2533         u8         ether_stats_broadcast_pkts_high[0x20];
2534
2535         u8         ether_stats_broadcast_pkts_low[0x20];
2536
2537         u8         ether_stats_multicast_pkts_high[0x20];
2538
2539         u8         ether_stats_multicast_pkts_low[0x20];
2540
2541         u8         ether_stats_crc_align_errors_high[0x20];
2542
2543         u8         ether_stats_crc_align_errors_low[0x20];
2544
2545         u8         ether_stats_undersize_pkts_high[0x20];
2546
2547         u8         ether_stats_undersize_pkts_low[0x20];
2548
2549         u8         ether_stats_oversize_pkts_high[0x20];
2550
2551         u8         ether_stats_oversize_pkts_low[0x20];
2552
2553         u8         ether_stats_fragments_high[0x20];
2554
2555         u8         ether_stats_fragments_low[0x20];
2556
2557         u8         ether_stats_jabbers_high[0x20];
2558
2559         u8         ether_stats_jabbers_low[0x20];
2560
2561         u8         ether_stats_collisions_high[0x20];
2562
2563         u8         ether_stats_collisions_low[0x20];
2564
2565         u8         ether_stats_pkts64octets_high[0x20];
2566
2567         u8         ether_stats_pkts64octets_low[0x20];
2568
2569         u8         ether_stats_pkts65to127octets_high[0x20];
2570
2571         u8         ether_stats_pkts65to127octets_low[0x20];
2572
2573         u8         ether_stats_pkts128to255octets_high[0x20];
2574
2575         u8         ether_stats_pkts128to255octets_low[0x20];
2576
2577         u8         ether_stats_pkts256to511octets_high[0x20];
2578
2579         u8         ether_stats_pkts256to511octets_low[0x20];
2580
2581         u8         ether_stats_pkts512to1023octets_high[0x20];
2582
2583         u8         ether_stats_pkts512to1023octets_low[0x20];
2584
2585         u8         ether_stats_pkts1024to1518octets_high[0x20];
2586
2587         u8         ether_stats_pkts1024to1518octets_low[0x20];
2588
2589         u8         ether_stats_pkts1519to2047octets_high[0x20];
2590
2591         u8         ether_stats_pkts1519to2047octets_low[0x20];
2592
2593         u8         ether_stats_pkts2048to4095octets_high[0x20];
2594
2595         u8         ether_stats_pkts2048to4095octets_low[0x20];
2596
2597         u8         ether_stats_pkts4096to8191octets_high[0x20];
2598
2599         u8         ether_stats_pkts4096to8191octets_low[0x20];
2600
2601         u8         ether_stats_pkts8192to10239octets_high[0x20];
2602
2603         u8         ether_stats_pkts8192to10239octets_low[0x20];
2604
2605         u8         reserved_at_540[0x280];
2606 };
2607
2608 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2609         u8         if_in_octets_high[0x20];
2610
2611         u8         if_in_octets_low[0x20];
2612
2613         u8         if_in_ucast_pkts_high[0x20];
2614
2615         u8         if_in_ucast_pkts_low[0x20];
2616
2617         u8         if_in_discards_high[0x20];
2618
2619         u8         if_in_discards_low[0x20];
2620
2621         u8         if_in_errors_high[0x20];
2622
2623         u8         if_in_errors_low[0x20];
2624
2625         u8         if_in_unknown_protos_high[0x20];
2626
2627         u8         if_in_unknown_protos_low[0x20];
2628
2629         u8         if_out_octets_high[0x20];
2630
2631         u8         if_out_octets_low[0x20];
2632
2633         u8         if_out_ucast_pkts_high[0x20];
2634
2635         u8         if_out_ucast_pkts_low[0x20];
2636
2637         u8         if_out_discards_high[0x20];
2638
2639         u8         if_out_discards_low[0x20];
2640
2641         u8         if_out_errors_high[0x20];
2642
2643         u8         if_out_errors_low[0x20];
2644
2645         u8         if_in_multicast_pkts_high[0x20];
2646
2647         u8         if_in_multicast_pkts_low[0x20];
2648
2649         u8         if_in_broadcast_pkts_high[0x20];
2650
2651         u8         if_in_broadcast_pkts_low[0x20];
2652
2653         u8         if_out_multicast_pkts_high[0x20];
2654
2655         u8         if_out_multicast_pkts_low[0x20];
2656
2657         u8         if_out_broadcast_pkts_high[0x20];
2658
2659         u8         if_out_broadcast_pkts_low[0x20];
2660
2661         u8         reserved_at_340[0x480];
2662 };
2663
2664 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2665         u8         a_frames_transmitted_ok_high[0x20];
2666
2667         u8         a_frames_transmitted_ok_low[0x20];
2668
2669         u8         a_frames_received_ok_high[0x20];
2670
2671         u8         a_frames_received_ok_low[0x20];
2672
2673         u8         a_frame_check_sequence_errors_high[0x20];
2674
2675         u8         a_frame_check_sequence_errors_low[0x20];
2676
2677         u8         a_alignment_errors_high[0x20];
2678
2679         u8         a_alignment_errors_low[0x20];
2680
2681         u8         a_octets_transmitted_ok_high[0x20];
2682
2683         u8         a_octets_transmitted_ok_low[0x20];
2684
2685         u8         a_octets_received_ok_high[0x20];
2686
2687         u8         a_octets_received_ok_low[0x20];
2688
2689         u8         a_multicast_frames_xmitted_ok_high[0x20];
2690
2691         u8         a_multicast_frames_xmitted_ok_low[0x20];
2692
2693         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2694
2695         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2696
2697         u8         a_multicast_frames_received_ok_high[0x20];
2698
2699         u8         a_multicast_frames_received_ok_low[0x20];
2700
2701         u8         a_broadcast_frames_received_ok_high[0x20];
2702
2703         u8         a_broadcast_frames_received_ok_low[0x20];
2704
2705         u8         a_in_range_length_errors_high[0x20];
2706
2707         u8         a_in_range_length_errors_low[0x20];
2708
2709         u8         a_out_of_range_length_field_high[0x20];
2710
2711         u8         a_out_of_range_length_field_low[0x20];
2712
2713         u8         a_frame_too_long_errors_high[0x20];
2714
2715         u8         a_frame_too_long_errors_low[0x20];
2716
2717         u8         a_symbol_error_during_carrier_high[0x20];
2718
2719         u8         a_symbol_error_during_carrier_low[0x20];
2720
2721         u8         a_mac_control_frames_transmitted_high[0x20];
2722
2723         u8         a_mac_control_frames_transmitted_low[0x20];
2724
2725         u8         a_mac_control_frames_received_high[0x20];
2726
2727         u8         a_mac_control_frames_received_low[0x20];
2728
2729         u8         a_unsupported_opcodes_received_high[0x20];
2730
2731         u8         a_unsupported_opcodes_received_low[0x20];
2732
2733         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2734
2735         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2736
2737         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2738
2739         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2740
2741         u8         reserved_at_4c0[0x300];
2742 };
2743
2744 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2745         u8         life_time_counter_high[0x20];
2746
2747         u8         life_time_counter_low[0x20];
2748
2749         u8         rx_errors[0x20];
2750
2751         u8         tx_errors[0x20];
2752
2753         u8         l0_to_recovery_eieos[0x20];
2754
2755         u8         l0_to_recovery_ts[0x20];
2756
2757         u8         l0_to_recovery_framing[0x20];
2758
2759         u8         l0_to_recovery_retrain[0x20];
2760
2761         u8         crc_error_dllp[0x20];
2762
2763         u8         crc_error_tlp[0x20];
2764
2765         u8         tx_overflow_buffer_pkt_high[0x20];
2766
2767         u8         tx_overflow_buffer_pkt_low[0x20];
2768
2769         u8         outbound_stalled_reads[0x20];
2770
2771         u8         outbound_stalled_writes[0x20];
2772
2773         u8         outbound_stalled_reads_events[0x20];
2774
2775         u8         outbound_stalled_writes_events[0x20];
2776
2777         u8         reserved_at_200[0x5c0];
2778 };
2779
2780 struct mlx5_ifc_cmd_inter_comp_event_bits {
2781         u8         command_completion_vector[0x20];
2782
2783         u8         reserved_at_20[0xc0];
2784 };
2785
2786 struct mlx5_ifc_stall_vl_event_bits {
2787         u8         reserved_at_0[0x18];
2788         u8         port_num[0x1];
2789         u8         reserved_at_19[0x3];
2790         u8         vl[0x4];
2791
2792         u8         reserved_at_20[0xa0];
2793 };
2794
2795 struct mlx5_ifc_db_bf_congestion_event_bits {
2796         u8         event_subtype[0x8];
2797         u8         reserved_at_8[0x8];
2798         u8         congestion_level[0x8];
2799         u8         reserved_at_18[0x8];
2800
2801         u8         reserved_at_20[0xa0];
2802 };
2803
2804 struct mlx5_ifc_gpio_event_bits {
2805         u8         reserved_at_0[0x60];
2806
2807         u8         gpio_event_hi[0x20];
2808
2809         u8         gpio_event_lo[0x20];
2810
2811         u8         reserved_at_a0[0x40];
2812 };
2813
2814 struct mlx5_ifc_port_state_change_event_bits {
2815         u8         reserved_at_0[0x40];
2816
2817         u8         port_num[0x4];
2818         u8         reserved_at_44[0x1c];
2819
2820         u8         reserved_at_60[0x80];
2821 };
2822
2823 struct mlx5_ifc_dropped_packet_logged_bits {
2824         u8         reserved_at_0[0xe0];
2825 };
2826
2827 struct mlx5_ifc_default_timeout_bits {
2828         u8         to_multiplier[0x3];
2829         u8         reserved_at_3[0x9];
2830         u8         to_value[0x14];
2831 };
2832
2833 struct mlx5_ifc_dtor_reg_bits {
2834         u8         reserved_at_0[0x20];
2835
2836         struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2837
2838         u8         reserved_at_40[0x60];
2839
2840         struct mlx5_ifc_default_timeout_bits health_poll_to;
2841
2842         struct mlx5_ifc_default_timeout_bits full_crdump_to;
2843
2844         struct mlx5_ifc_default_timeout_bits fw_reset_to;
2845
2846         struct mlx5_ifc_default_timeout_bits flush_on_err_to;
2847
2848         struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
2849
2850         struct mlx5_ifc_default_timeout_bits tear_down_to;
2851
2852         struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
2853
2854         struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
2855
2856         struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
2857
2858         u8         reserved_at_1c0[0x40];
2859 };
2860
2861 enum {
2862         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2863         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2864 };
2865
2866 struct mlx5_ifc_cq_error_bits {
2867         u8         reserved_at_0[0x8];
2868         u8         cqn[0x18];
2869
2870         u8         reserved_at_20[0x20];
2871
2872         u8         reserved_at_40[0x18];
2873         u8         syndrome[0x8];
2874
2875         u8         reserved_at_60[0x80];
2876 };
2877
2878 struct mlx5_ifc_rdma_page_fault_event_bits {
2879         u8         bytes_committed[0x20];
2880
2881         u8         r_key[0x20];
2882
2883         u8         reserved_at_40[0x10];
2884         u8         packet_len[0x10];
2885
2886         u8         rdma_op_len[0x20];
2887
2888         u8         rdma_va[0x40];
2889
2890         u8         reserved_at_c0[0x5];
2891         u8         rdma[0x1];
2892         u8         write[0x1];
2893         u8         requestor[0x1];
2894         u8         qp_number[0x18];
2895 };
2896
2897 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2898         u8         bytes_committed[0x20];
2899
2900         u8         reserved_at_20[0x10];
2901         u8         wqe_index[0x10];
2902
2903         u8         reserved_at_40[0x10];
2904         u8         len[0x10];
2905
2906         u8         reserved_at_60[0x60];
2907
2908         u8         reserved_at_c0[0x5];
2909         u8         rdma[0x1];
2910         u8         write_read[0x1];
2911         u8         requestor[0x1];
2912         u8         qpn[0x18];
2913 };
2914
2915 struct mlx5_ifc_qp_events_bits {
2916         u8         reserved_at_0[0xa0];
2917
2918         u8         type[0x8];
2919         u8         reserved_at_a8[0x18];
2920
2921         u8         reserved_at_c0[0x8];
2922         u8         qpn_rqn_sqn[0x18];
2923 };
2924
2925 struct mlx5_ifc_dct_events_bits {
2926         u8         reserved_at_0[0xc0];
2927
2928         u8         reserved_at_c0[0x8];
2929         u8         dct_number[0x18];
2930 };
2931
2932 struct mlx5_ifc_comp_event_bits {
2933         u8         reserved_at_0[0xc0];
2934
2935         u8         reserved_at_c0[0x8];
2936         u8         cq_number[0x18];
2937 };
2938
2939 enum {
2940         MLX5_QPC_STATE_RST        = 0x0,
2941         MLX5_QPC_STATE_INIT       = 0x1,
2942         MLX5_QPC_STATE_RTR        = 0x2,
2943         MLX5_QPC_STATE_RTS        = 0x3,
2944         MLX5_QPC_STATE_SQER       = 0x4,
2945         MLX5_QPC_STATE_ERR        = 0x6,
2946         MLX5_QPC_STATE_SQD        = 0x7,
2947         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2948 };
2949
2950 enum {
2951         MLX5_QPC_ST_RC            = 0x0,
2952         MLX5_QPC_ST_UC            = 0x1,
2953         MLX5_QPC_ST_UD            = 0x2,
2954         MLX5_QPC_ST_XRC           = 0x3,
2955         MLX5_QPC_ST_DCI           = 0x5,
2956         MLX5_QPC_ST_QP0           = 0x7,
2957         MLX5_QPC_ST_QP1           = 0x8,
2958         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2959         MLX5_QPC_ST_REG_UMR       = 0xc,
2960 };
2961
2962 enum {
2963         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2964         MLX5_QPC_PM_STATE_REARM     = 0x1,
2965         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2966         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2967 };
2968
2969 enum {
2970         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2971 };
2972
2973 enum {
2974         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2975         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2976 };
2977
2978 enum {
2979         MLX5_QPC_MTU_256_BYTES        = 0x1,
2980         MLX5_QPC_MTU_512_BYTES        = 0x2,
2981         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2982         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2983         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2984         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2985 };
2986
2987 enum {
2988         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2989         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2990         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2991         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2992         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2993         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2994         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2995         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2996 };
2997
2998 enum {
2999         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3000         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3001         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3002 };
3003
3004 enum {
3005         MLX5_QPC_CS_RES_DISABLE    = 0x0,
3006         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3007         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3008 };
3009
3010 enum {
3011         MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3012         MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3013         MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3014 };
3015
3016 struct mlx5_ifc_qpc_bits {
3017         u8         state[0x4];
3018         u8         lag_tx_port_affinity[0x4];
3019         u8         st[0x8];
3020         u8         reserved_at_10[0x2];
3021         u8         isolate_vl_tc[0x1];
3022         u8         pm_state[0x2];
3023         u8         reserved_at_15[0x1];
3024         u8         req_e2e_credit_mode[0x2];
3025         u8         offload_type[0x4];
3026         u8         end_padding_mode[0x2];
3027         u8         reserved_at_1e[0x2];
3028
3029         u8         wq_signature[0x1];
3030         u8         block_lb_mc[0x1];
3031         u8         atomic_like_write_en[0x1];
3032         u8         latency_sensitive[0x1];
3033         u8         reserved_at_24[0x1];
3034         u8         drain_sigerr[0x1];
3035         u8         reserved_at_26[0x2];
3036         u8         pd[0x18];
3037
3038         u8         mtu[0x3];
3039         u8         log_msg_max[0x5];
3040         u8         reserved_at_48[0x1];
3041         u8         log_rq_size[0x4];
3042         u8         log_rq_stride[0x3];
3043         u8         no_sq[0x1];
3044         u8         log_sq_size[0x4];
3045         u8         reserved_at_55[0x3];
3046         u8         ts_format[0x2];
3047         u8         reserved_at_5a[0x1];
3048         u8         rlky[0x1];
3049         u8         ulp_stateless_offload_mode[0x4];
3050
3051         u8         counter_set_id[0x8];
3052         u8         uar_page[0x18];
3053
3054         u8         reserved_at_80[0x8];
3055         u8         user_index[0x18];
3056
3057         u8         reserved_at_a0[0x3];
3058         u8         log_page_size[0x5];
3059         u8         remote_qpn[0x18];
3060
3061         struct mlx5_ifc_ads_bits primary_address_path;
3062
3063         struct mlx5_ifc_ads_bits secondary_address_path;
3064
3065         u8         log_ack_req_freq[0x4];
3066         u8         reserved_at_384[0x4];
3067         u8         log_sra_max[0x3];
3068         u8         reserved_at_38b[0x2];
3069         u8         retry_count[0x3];
3070         u8         rnr_retry[0x3];
3071         u8         reserved_at_393[0x1];
3072         u8         fre[0x1];
3073         u8         cur_rnr_retry[0x3];
3074         u8         cur_retry_count[0x3];
3075         u8         reserved_at_39b[0x5];
3076
3077         u8         reserved_at_3a0[0x20];
3078
3079         u8         reserved_at_3c0[0x8];
3080         u8         next_send_psn[0x18];
3081
3082         u8         reserved_at_3e0[0x3];
3083         u8         log_num_dci_stream_channels[0x5];
3084         u8         cqn_snd[0x18];
3085
3086         u8         reserved_at_400[0x3];
3087         u8         log_num_dci_errored_streams[0x5];
3088         u8         deth_sqpn[0x18];
3089
3090         u8         reserved_at_420[0x20];
3091
3092         u8         reserved_at_440[0x8];
3093         u8         last_acked_psn[0x18];
3094
3095         u8         reserved_at_460[0x8];
3096         u8         ssn[0x18];
3097
3098         u8         reserved_at_480[0x8];
3099         u8         log_rra_max[0x3];
3100         u8         reserved_at_48b[0x1];
3101         u8         atomic_mode[0x4];
3102         u8         rre[0x1];
3103         u8         rwe[0x1];
3104         u8         rae[0x1];
3105         u8         reserved_at_493[0x1];
3106         u8         page_offset[0x6];
3107         u8         reserved_at_49a[0x3];
3108         u8         cd_slave_receive[0x1];
3109         u8         cd_slave_send[0x1];
3110         u8         cd_master[0x1];
3111
3112         u8         reserved_at_4a0[0x3];
3113         u8         min_rnr_nak[0x5];
3114         u8         next_rcv_psn[0x18];
3115
3116         u8         reserved_at_4c0[0x8];
3117         u8         xrcd[0x18];
3118
3119         u8         reserved_at_4e0[0x8];
3120         u8         cqn_rcv[0x18];
3121
3122         u8         dbr_addr[0x40];
3123
3124         u8         q_key[0x20];
3125
3126         u8         reserved_at_560[0x5];
3127         u8         rq_type[0x3];
3128         u8         srqn_rmpn_xrqn[0x18];
3129
3130         u8         reserved_at_580[0x8];
3131         u8         rmsn[0x18];
3132
3133         u8         hw_sq_wqebb_counter[0x10];
3134         u8         sw_sq_wqebb_counter[0x10];
3135
3136         u8         hw_rq_counter[0x20];
3137
3138         u8         sw_rq_counter[0x20];
3139
3140         u8         reserved_at_600[0x20];
3141
3142         u8         reserved_at_620[0xf];
3143         u8         cgs[0x1];
3144         u8         cs_req[0x8];
3145         u8         cs_res[0x8];
3146
3147         u8         dc_access_key[0x40];
3148
3149         u8         reserved_at_680[0x3];
3150         u8         dbr_umem_valid[0x1];
3151
3152         u8         reserved_at_684[0xbc];
3153 };
3154
3155 struct mlx5_ifc_roce_addr_layout_bits {
3156         u8         source_l3_address[16][0x8];
3157
3158         u8         reserved_at_80[0x3];
3159         u8         vlan_valid[0x1];
3160         u8         vlan_id[0xc];
3161         u8         source_mac_47_32[0x10];
3162
3163         u8         source_mac_31_0[0x20];
3164
3165         u8         reserved_at_c0[0x14];
3166         u8         roce_l3_type[0x4];
3167         u8         roce_version[0x8];
3168
3169         u8         reserved_at_e0[0x20];
3170 };
3171
3172 union mlx5_ifc_hca_cap_union_bits {
3173         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3174         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3175         struct mlx5_ifc_odp_cap_bits odp_cap;
3176         struct mlx5_ifc_atomic_caps_bits atomic_caps;
3177         struct mlx5_ifc_roce_cap_bits roce_cap;
3178         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3179         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3180         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3181         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3182         struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3183         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3184         struct mlx5_ifc_qos_cap_bits qos_cap;
3185         struct mlx5_ifc_debug_cap_bits debug_cap;
3186         struct mlx5_ifc_fpga_cap_bits fpga_cap;
3187         struct mlx5_ifc_tls_cap_bits tls_cap;
3188         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3189         struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3190         u8         reserved_at_0[0x8000];
3191 };
3192
3193 enum {
3194         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3195         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3196         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3197         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3198         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3199         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3200         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3201         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3202         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3203         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3204         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3205         MLX5_FLOW_CONTEXT_ACTION_IPSEC_DECRYPT = 0x1000,
3206         MLX5_FLOW_CONTEXT_ACTION_IPSEC_ENCRYPT = 0x2000,
3207 };
3208
3209 enum {
3210         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3211         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3212         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3213 };
3214
3215 struct mlx5_ifc_vlan_bits {
3216         u8         ethtype[0x10];
3217         u8         prio[0x3];
3218         u8         cfi[0x1];
3219         u8         vid[0xc];
3220 };
3221
3222 struct mlx5_ifc_flow_context_bits {
3223         struct mlx5_ifc_vlan_bits push_vlan;
3224
3225         u8         group_id[0x20];
3226
3227         u8         reserved_at_40[0x8];
3228         u8         flow_tag[0x18];
3229
3230         u8         reserved_at_60[0x10];
3231         u8         action[0x10];
3232
3233         u8         extended_destination[0x1];
3234         u8         reserved_at_81[0x1];
3235         u8         flow_source[0x2];
3236         u8         reserved_at_84[0x4];
3237         u8         destination_list_size[0x18];
3238
3239         u8         reserved_at_a0[0x8];
3240         u8         flow_counter_list_size[0x18];
3241
3242         u8         packet_reformat_id[0x20];
3243
3244         u8         modify_header_id[0x20];
3245
3246         struct mlx5_ifc_vlan_bits push_vlan_2;
3247
3248         u8         ipsec_obj_id[0x20];
3249         u8         reserved_at_140[0xc0];
3250
3251         struct mlx5_ifc_fte_match_param_bits match_value;
3252
3253         u8         reserved_at_1200[0x600];
3254
3255         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3256 };
3257
3258 enum {
3259         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3260         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3261 };
3262
3263 struct mlx5_ifc_xrc_srqc_bits {
3264         u8         state[0x4];
3265         u8         log_xrc_srq_size[0x4];
3266         u8         reserved_at_8[0x18];
3267
3268         u8         wq_signature[0x1];
3269         u8         cont_srq[0x1];
3270         u8         reserved_at_22[0x1];
3271         u8         rlky[0x1];
3272         u8         basic_cyclic_rcv_wqe[0x1];
3273         u8         log_rq_stride[0x3];
3274         u8         xrcd[0x18];
3275
3276         u8         page_offset[0x6];
3277         u8         reserved_at_46[0x1];
3278         u8         dbr_umem_valid[0x1];
3279         u8         cqn[0x18];
3280
3281         u8         reserved_at_60[0x20];
3282
3283         u8         user_index_equal_xrc_srqn[0x1];
3284         u8         reserved_at_81[0x1];
3285         u8         log_page_size[0x6];
3286         u8         user_index[0x18];
3287
3288         u8         reserved_at_a0[0x20];
3289
3290         u8         reserved_at_c0[0x8];
3291         u8         pd[0x18];
3292
3293         u8         lwm[0x10];
3294         u8         wqe_cnt[0x10];
3295
3296         u8         reserved_at_100[0x40];
3297
3298         u8         db_record_addr_h[0x20];
3299
3300         u8         db_record_addr_l[0x1e];
3301         u8         reserved_at_17e[0x2];
3302
3303         u8         reserved_at_180[0x80];
3304 };
3305
3306 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3307         u8         counter_error_queues[0x20];
3308
3309         u8         total_error_queues[0x20];
3310
3311         u8         send_queue_priority_update_flow[0x20];
3312
3313         u8         reserved_at_60[0x20];
3314
3315         u8         nic_receive_steering_discard[0x40];
3316
3317         u8         receive_discard_vport_down[0x40];
3318
3319         u8         transmit_discard_vport_down[0x40];
3320
3321         u8         reserved_at_140[0xa0];
3322
3323         u8         internal_rq_out_of_buffer[0x20];
3324
3325         u8         reserved_at_200[0xe00];
3326 };
3327
3328 struct mlx5_ifc_traffic_counter_bits {
3329         u8         packets[0x40];
3330
3331         u8         octets[0x40];
3332 };
3333
3334 struct mlx5_ifc_tisc_bits {
3335         u8         strict_lag_tx_port_affinity[0x1];
3336         u8         tls_en[0x1];
3337         u8         reserved_at_2[0x2];
3338         u8         lag_tx_port_affinity[0x04];
3339
3340         u8         reserved_at_8[0x4];
3341         u8         prio[0x4];
3342         u8         reserved_at_10[0x10];
3343
3344         u8         reserved_at_20[0x100];
3345
3346         u8         reserved_at_120[0x8];
3347         u8         transport_domain[0x18];
3348
3349         u8         reserved_at_140[0x8];
3350         u8         underlay_qpn[0x18];
3351
3352         u8         reserved_at_160[0x8];
3353         u8         pd[0x18];
3354
3355         u8         reserved_at_180[0x380];
3356 };
3357
3358 enum {
3359         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3360         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3361 };
3362
3363 enum {
3364         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3365         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3366 };
3367
3368 enum {
3369         MLX5_RX_HASH_FN_NONE           = 0x0,
3370         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3371         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3372 };
3373
3374 enum {
3375         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3376         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3377 };
3378
3379 struct mlx5_ifc_tirc_bits {
3380         u8         reserved_at_0[0x20];
3381
3382         u8         disp_type[0x4];
3383         u8         tls_en[0x1];
3384         u8         reserved_at_25[0x1b];
3385
3386         u8         reserved_at_40[0x40];
3387
3388         u8         reserved_at_80[0x4];
3389         u8         lro_timeout_period_usecs[0x10];
3390         u8         lro_enable_mask[0x4];
3391         u8         lro_max_ip_payload_size[0x8];
3392
3393         u8         reserved_at_a0[0x40];
3394
3395         u8         reserved_at_e0[0x8];
3396         u8         inline_rqn[0x18];
3397
3398         u8         rx_hash_symmetric[0x1];
3399         u8         reserved_at_101[0x1];
3400         u8         tunneled_offload_en[0x1];
3401         u8         reserved_at_103[0x5];
3402         u8         indirect_table[0x18];
3403
3404         u8         rx_hash_fn[0x4];
3405         u8         reserved_at_124[0x2];
3406         u8         self_lb_block[0x2];
3407         u8         transport_domain[0x18];
3408
3409         u8         rx_hash_toeplitz_key[10][0x20];
3410
3411         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3412
3413         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3414
3415         u8         reserved_at_2c0[0x4c0];
3416 };
3417
3418 enum {
3419         MLX5_SRQC_STATE_GOOD   = 0x0,
3420         MLX5_SRQC_STATE_ERROR  = 0x1,
3421 };
3422
3423 struct mlx5_ifc_srqc_bits {
3424         u8         state[0x4];
3425         u8         log_srq_size[0x4];
3426         u8         reserved_at_8[0x18];
3427
3428         u8         wq_signature[0x1];
3429         u8         cont_srq[0x1];
3430         u8         reserved_at_22[0x1];
3431         u8         rlky[0x1];
3432         u8         reserved_at_24[0x1];
3433         u8         log_rq_stride[0x3];
3434         u8         xrcd[0x18];
3435
3436         u8         page_offset[0x6];
3437         u8         reserved_at_46[0x2];
3438         u8         cqn[0x18];
3439
3440         u8         reserved_at_60[0x20];
3441
3442         u8         reserved_at_80[0x2];
3443         u8         log_page_size[0x6];
3444         u8         reserved_at_88[0x18];
3445
3446         u8         reserved_at_a0[0x20];
3447
3448         u8         reserved_at_c0[0x8];
3449         u8         pd[0x18];
3450
3451         u8         lwm[0x10];
3452         u8         wqe_cnt[0x10];
3453
3454         u8         reserved_at_100[0x40];
3455
3456         u8         dbr_addr[0x40];
3457
3458         u8         reserved_at_180[0x80];
3459 };
3460
3461 enum {
3462         MLX5_SQC_STATE_RST  = 0x0,
3463         MLX5_SQC_STATE_RDY  = 0x1,
3464         MLX5_SQC_STATE_ERR  = 0x3,
3465 };
3466
3467 struct mlx5_ifc_sqc_bits {
3468         u8         rlky[0x1];
3469         u8         cd_master[0x1];
3470         u8         fre[0x1];
3471         u8         flush_in_error_en[0x1];
3472         u8         allow_multi_pkt_send_wqe[0x1];
3473         u8         min_wqe_inline_mode[0x3];
3474         u8         state[0x4];
3475         u8         reg_umr[0x1];
3476         u8         allow_swp[0x1];
3477         u8         hairpin[0x1];
3478         u8         reserved_at_f[0xb];
3479         u8         ts_format[0x2];
3480         u8         reserved_at_1c[0x4];
3481
3482         u8         reserved_at_20[0x8];
3483         u8         user_index[0x18];
3484
3485         u8         reserved_at_40[0x8];
3486         u8         cqn[0x18];
3487
3488         u8         reserved_at_60[0x8];
3489         u8         hairpin_peer_rq[0x18];
3490
3491         u8         reserved_at_80[0x10];
3492         u8         hairpin_peer_vhca[0x10];
3493
3494         u8         reserved_at_a0[0x20];
3495
3496         u8         reserved_at_c0[0x8];
3497         u8         ts_cqe_to_dest_cqn[0x18];
3498
3499         u8         reserved_at_e0[0x10];
3500         u8         packet_pacing_rate_limit_index[0x10];
3501         u8         tis_lst_sz[0x10];
3502         u8         qos_queue_group_id[0x10];
3503
3504         u8         reserved_at_120[0x40];
3505
3506         u8         reserved_at_160[0x8];
3507         u8         tis_num_0[0x18];
3508
3509         struct mlx5_ifc_wq_bits wq;
3510 };
3511
3512 enum {
3513         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3514         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3515         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3516         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3517         SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3518 };
3519
3520 enum {
3521         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3522         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3523         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3524         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3525 };
3526
3527 struct mlx5_ifc_scheduling_context_bits {
3528         u8         element_type[0x8];
3529         u8         reserved_at_8[0x18];
3530
3531         u8         element_attributes[0x20];
3532
3533         u8         parent_element_id[0x20];
3534
3535         u8         reserved_at_60[0x40];
3536
3537         u8         bw_share[0x20];
3538
3539         u8         max_average_bw[0x20];
3540
3541         u8         reserved_at_e0[0x120];
3542 };
3543
3544 struct mlx5_ifc_rqtc_bits {
3545         u8    reserved_at_0[0xa0];
3546
3547         u8    reserved_at_a0[0x5];
3548         u8    list_q_type[0x3];
3549         u8    reserved_at_a8[0x8];
3550         u8    rqt_max_size[0x10];
3551
3552         u8    rq_vhca_id_format[0x1];
3553         u8    reserved_at_c1[0xf];
3554         u8    rqt_actual_size[0x10];
3555
3556         u8    reserved_at_e0[0x6a0];
3557
3558         struct mlx5_ifc_rq_num_bits rq_num[];
3559 };
3560
3561 enum {
3562         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3563         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3564 };
3565
3566 enum {
3567         MLX5_RQC_STATE_RST  = 0x0,
3568         MLX5_RQC_STATE_RDY  = 0x1,
3569         MLX5_RQC_STATE_ERR  = 0x3,
3570 };
3571
3572 struct mlx5_ifc_rqc_bits {
3573         u8         rlky[0x1];
3574         u8         delay_drop_en[0x1];
3575         u8         scatter_fcs[0x1];
3576         u8         vsd[0x1];
3577         u8         mem_rq_type[0x4];
3578         u8         state[0x4];
3579         u8         reserved_at_c[0x1];
3580         u8         flush_in_error_en[0x1];
3581         u8         hairpin[0x1];
3582         u8         reserved_at_f[0xb];
3583         u8         ts_format[0x2];
3584         u8         reserved_at_1c[0x4];
3585
3586         u8         reserved_at_20[0x8];
3587         u8         user_index[0x18];
3588
3589         u8         reserved_at_40[0x8];
3590         u8         cqn[0x18];
3591
3592         u8         counter_set_id[0x8];
3593         u8         reserved_at_68[0x18];
3594
3595         u8         reserved_at_80[0x8];
3596         u8         rmpn[0x18];
3597
3598         u8         reserved_at_a0[0x8];
3599         u8         hairpin_peer_sq[0x18];
3600
3601         u8         reserved_at_c0[0x10];
3602         u8         hairpin_peer_vhca[0x10];
3603
3604         u8         reserved_at_e0[0xa0];
3605
3606         struct mlx5_ifc_wq_bits wq;
3607 };
3608
3609 enum {
3610         MLX5_RMPC_STATE_RDY  = 0x1,
3611         MLX5_RMPC_STATE_ERR  = 0x3,
3612 };
3613
3614 struct mlx5_ifc_rmpc_bits {
3615         u8         reserved_at_0[0x8];
3616         u8         state[0x4];
3617         u8         reserved_at_c[0x14];
3618
3619         u8         basic_cyclic_rcv_wqe[0x1];
3620         u8         reserved_at_21[0x1f];
3621
3622         u8         reserved_at_40[0x140];
3623
3624         struct mlx5_ifc_wq_bits wq;
3625 };
3626
3627 struct mlx5_ifc_nic_vport_context_bits {
3628         u8         reserved_at_0[0x5];
3629         u8         min_wqe_inline_mode[0x3];
3630         u8         reserved_at_8[0x15];
3631         u8         disable_mc_local_lb[0x1];
3632         u8         disable_uc_local_lb[0x1];
3633         u8         roce_en[0x1];
3634
3635         u8         arm_change_event[0x1];
3636         u8         reserved_at_21[0x1a];
3637         u8         event_on_mtu[0x1];
3638         u8         event_on_promisc_change[0x1];
3639         u8         event_on_vlan_change[0x1];
3640         u8         event_on_mc_address_change[0x1];
3641         u8         event_on_uc_address_change[0x1];
3642
3643         u8         reserved_at_40[0xc];
3644
3645         u8         affiliation_criteria[0x4];
3646         u8         affiliated_vhca_id[0x10];
3647
3648         u8         reserved_at_60[0xd0];
3649
3650         u8         mtu[0x10];
3651
3652         u8         system_image_guid[0x40];
3653         u8         port_guid[0x40];
3654         u8         node_guid[0x40];
3655
3656         u8         reserved_at_200[0x140];
3657         u8         qkey_violation_counter[0x10];
3658         u8         reserved_at_350[0x430];
3659
3660         u8         promisc_uc[0x1];
3661         u8         promisc_mc[0x1];
3662         u8         promisc_all[0x1];
3663         u8         reserved_at_783[0x2];
3664         u8         allowed_list_type[0x3];
3665         u8         reserved_at_788[0xc];
3666         u8         allowed_list_size[0xc];
3667
3668         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3669
3670         u8         reserved_at_7e0[0x20];
3671
3672         u8         current_uc_mac_address[][0x40];
3673 };
3674
3675 enum {
3676         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3677         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3678         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3679         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3680         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3681         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3682 };
3683
3684 struct mlx5_ifc_mkc_bits {
3685         u8         reserved_at_0[0x1];
3686         u8         free[0x1];
3687         u8         reserved_at_2[0x1];
3688         u8         access_mode_4_2[0x3];
3689         u8         reserved_at_6[0x7];
3690         u8         relaxed_ordering_write[0x1];
3691         u8         reserved_at_e[0x1];
3692         u8         small_fence_on_rdma_read_response[0x1];
3693         u8         umr_en[0x1];
3694         u8         a[0x1];
3695         u8         rw[0x1];
3696         u8         rr[0x1];
3697         u8         lw[0x1];
3698         u8         lr[0x1];
3699         u8         access_mode_1_0[0x2];
3700         u8         reserved_at_18[0x8];
3701
3702         u8         qpn[0x18];
3703         u8         mkey_7_0[0x8];
3704
3705         u8         reserved_at_40[0x20];
3706
3707         u8         length64[0x1];
3708         u8         bsf_en[0x1];
3709         u8         sync_umr[0x1];
3710         u8         reserved_at_63[0x2];
3711         u8         expected_sigerr_count[0x1];
3712         u8         reserved_at_66[0x1];
3713         u8         en_rinval[0x1];
3714         u8         pd[0x18];
3715
3716         u8         start_addr[0x40];
3717
3718         u8         len[0x40];
3719
3720         u8         bsf_octword_size[0x20];
3721
3722         u8         reserved_at_120[0x80];
3723
3724         u8         translations_octword_size[0x20];
3725
3726         u8         reserved_at_1c0[0x19];
3727         u8         relaxed_ordering_read[0x1];
3728         u8         reserved_at_1d9[0x1];
3729         u8         log_page_size[0x5];
3730
3731         u8         reserved_at_1e0[0x20];
3732 };
3733
3734 struct mlx5_ifc_pkey_bits {
3735         u8         reserved_at_0[0x10];
3736         u8         pkey[0x10];
3737 };
3738
3739 struct mlx5_ifc_array128_auto_bits {
3740         u8         array128_auto[16][0x8];
3741 };
3742
3743 struct mlx5_ifc_hca_vport_context_bits {
3744         u8         field_select[0x20];
3745
3746         u8         reserved_at_20[0xe0];
3747
3748         u8         sm_virt_aware[0x1];
3749         u8         has_smi[0x1];
3750         u8         has_raw[0x1];
3751         u8         grh_required[0x1];
3752         u8         reserved_at_104[0xc];
3753         u8         port_physical_state[0x4];
3754         u8         vport_state_policy[0x4];
3755         u8         port_state[0x4];
3756         u8         vport_state[0x4];
3757
3758         u8         reserved_at_120[0x20];
3759
3760         u8         system_image_guid[0x40];
3761
3762         u8         port_guid[0x40];
3763
3764         u8         node_guid[0x40];
3765
3766         u8         cap_mask1[0x20];
3767
3768         u8         cap_mask1_field_select[0x20];
3769
3770         u8         cap_mask2[0x20];
3771
3772         u8         cap_mask2_field_select[0x20];
3773
3774         u8         reserved_at_280[0x80];
3775
3776         u8         lid[0x10];
3777         u8         reserved_at_310[0x4];
3778         u8         init_type_reply[0x4];
3779         u8         lmc[0x3];
3780         u8         subnet_timeout[0x5];
3781
3782         u8         sm_lid[0x10];
3783         u8         sm_sl[0x4];
3784         u8         reserved_at_334[0xc];
3785
3786         u8         qkey_violation_counter[0x10];
3787         u8         pkey_violation_counter[0x10];
3788
3789         u8         reserved_at_360[0xca0];
3790 };
3791
3792 struct mlx5_ifc_esw_vport_context_bits {
3793         u8         fdb_to_vport_reg_c[0x1];
3794         u8         reserved_at_1[0x2];
3795         u8         vport_svlan_strip[0x1];
3796         u8         vport_cvlan_strip[0x1];
3797         u8         vport_svlan_insert[0x1];
3798         u8         vport_cvlan_insert[0x2];
3799         u8         fdb_to_vport_reg_c_id[0x8];
3800         u8         reserved_at_10[0x10];
3801
3802         u8         reserved_at_20[0x20];
3803
3804         u8         svlan_cfi[0x1];
3805         u8         svlan_pcp[0x3];
3806         u8         svlan_id[0xc];
3807         u8         cvlan_cfi[0x1];
3808         u8         cvlan_pcp[0x3];
3809         u8         cvlan_id[0xc];
3810
3811         u8         reserved_at_60[0x720];
3812
3813         u8         sw_steering_vport_icm_address_rx[0x40];
3814
3815         u8         sw_steering_vport_icm_address_tx[0x40];
3816 };
3817
3818 enum {
3819         MLX5_EQC_STATUS_OK                = 0x0,
3820         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3821 };
3822
3823 enum {
3824         MLX5_EQC_ST_ARMED  = 0x9,
3825         MLX5_EQC_ST_FIRED  = 0xa,
3826 };
3827
3828 struct mlx5_ifc_eqc_bits {
3829         u8         status[0x4];
3830         u8         reserved_at_4[0x9];
3831         u8         ec[0x1];
3832         u8         oi[0x1];
3833         u8         reserved_at_f[0x5];
3834         u8         st[0x4];
3835         u8         reserved_at_18[0x8];
3836
3837         u8         reserved_at_20[0x20];
3838
3839         u8         reserved_at_40[0x14];
3840         u8         page_offset[0x6];
3841         u8         reserved_at_5a[0x6];
3842
3843         u8         reserved_at_60[0x3];
3844         u8         log_eq_size[0x5];
3845         u8         uar_page[0x18];
3846
3847         u8         reserved_at_80[0x20];
3848
3849         u8         reserved_at_a0[0x14];
3850         u8         intr[0xc];
3851
3852         u8         reserved_at_c0[0x3];
3853         u8         log_page_size[0x5];
3854         u8         reserved_at_c8[0x18];
3855
3856         u8         reserved_at_e0[0x60];
3857
3858         u8         reserved_at_140[0x8];
3859         u8         consumer_counter[0x18];
3860
3861         u8         reserved_at_160[0x8];
3862         u8         producer_counter[0x18];
3863
3864         u8         reserved_at_180[0x80];
3865 };
3866
3867 enum {
3868         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3869         MLX5_DCTC_STATE_DRAINING  = 0x1,
3870         MLX5_DCTC_STATE_DRAINED   = 0x2,
3871 };
3872
3873 enum {
3874         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3875         MLX5_DCTC_CS_RES_NA         = 0x1,
3876         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3877 };
3878
3879 enum {
3880         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3881         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3882         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3883         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3884         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3885 };
3886
3887 struct mlx5_ifc_dctc_bits {
3888         u8         reserved_at_0[0x4];
3889         u8         state[0x4];
3890         u8         reserved_at_8[0x18];
3891
3892         u8         reserved_at_20[0x8];
3893         u8         user_index[0x18];
3894
3895         u8         reserved_at_40[0x8];
3896         u8         cqn[0x18];
3897
3898         u8         counter_set_id[0x8];
3899         u8         atomic_mode[0x4];
3900         u8         rre[0x1];
3901         u8         rwe[0x1];
3902         u8         rae[0x1];
3903         u8         atomic_like_write_en[0x1];
3904         u8         latency_sensitive[0x1];
3905         u8         rlky[0x1];
3906         u8         free_ar[0x1];
3907         u8         reserved_at_73[0xd];
3908
3909         u8         reserved_at_80[0x8];
3910         u8         cs_res[0x8];
3911         u8         reserved_at_90[0x3];
3912         u8         min_rnr_nak[0x5];
3913         u8         reserved_at_98[0x8];
3914
3915         u8         reserved_at_a0[0x8];
3916         u8         srqn_xrqn[0x18];
3917
3918         u8         reserved_at_c0[0x8];
3919         u8         pd[0x18];
3920
3921         u8         tclass[0x8];
3922         u8         reserved_at_e8[0x4];
3923         u8         flow_label[0x14];
3924
3925         u8         dc_access_key[0x40];
3926
3927         u8         reserved_at_140[0x5];
3928         u8         mtu[0x3];
3929         u8         port[0x8];
3930         u8         pkey_index[0x10];
3931
3932         u8         reserved_at_160[0x8];
3933         u8         my_addr_index[0x8];
3934         u8         reserved_at_170[0x8];
3935         u8         hop_limit[0x8];
3936
3937         u8         dc_access_key_violation_count[0x20];
3938
3939         u8         reserved_at_1a0[0x14];
3940         u8         dei_cfi[0x1];
3941         u8         eth_prio[0x3];
3942         u8         ecn[0x2];
3943         u8         dscp[0x6];
3944
3945         u8         reserved_at_1c0[0x20];
3946         u8         ece[0x20];
3947 };
3948
3949 enum {
3950         MLX5_CQC_STATUS_OK             = 0x0,
3951         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3952         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3953 };
3954
3955 enum {
3956         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3957         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3958 };
3959
3960 enum {
3961         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3962         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3963         MLX5_CQC_ST_FIRED                                 = 0xa,
3964 };
3965
3966 enum {
3967         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3968         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3969         MLX5_CQ_PERIOD_NUM_MODES
3970 };
3971
3972 struct mlx5_ifc_cqc_bits {
3973         u8         status[0x4];
3974         u8         reserved_at_4[0x2];
3975         u8         dbr_umem_valid[0x1];
3976         u8         apu_cq[0x1];
3977         u8         cqe_sz[0x3];
3978         u8         cc[0x1];
3979         u8         reserved_at_c[0x1];
3980         u8         scqe_break_moderation_en[0x1];
3981         u8         oi[0x1];
3982         u8         cq_period_mode[0x2];
3983         u8         cqe_comp_en[0x1];
3984         u8         mini_cqe_res_format[0x2];
3985         u8         st[0x4];
3986         u8         reserved_at_18[0x8];
3987
3988         u8         reserved_at_20[0x20];
3989
3990         u8         reserved_at_40[0x14];
3991         u8         page_offset[0x6];
3992         u8         reserved_at_5a[0x6];
3993
3994         u8         reserved_at_60[0x3];
3995         u8         log_cq_size[0x5];
3996         u8         uar_page[0x18];
3997
3998         u8         reserved_at_80[0x4];
3999         u8         cq_period[0xc];
4000         u8         cq_max_count[0x10];
4001
4002         u8         c_eqn_or_apu_element[0x20];
4003
4004         u8         reserved_at_c0[0x3];
4005         u8         log_page_size[0x5];
4006         u8         reserved_at_c8[0x18];
4007
4008         u8         reserved_at_e0[0x20];
4009
4010         u8         reserved_at_100[0x8];
4011         u8         last_notified_index[0x18];
4012
4013         u8         reserved_at_120[0x8];
4014         u8         last_solicit_index[0x18];
4015
4016         u8         reserved_at_140[0x8];
4017         u8         consumer_counter[0x18];
4018
4019         u8         reserved_at_160[0x8];
4020         u8         producer_counter[0x18];
4021
4022         u8         reserved_at_180[0x40];
4023
4024         u8         dbr_addr[0x40];
4025 };
4026
4027 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4028         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4029         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4030         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4031         u8         reserved_at_0[0x800];
4032 };
4033
4034 struct mlx5_ifc_query_adapter_param_block_bits {
4035         u8         reserved_at_0[0xc0];
4036
4037         u8         reserved_at_c0[0x8];
4038         u8         ieee_vendor_id[0x18];
4039
4040         u8         reserved_at_e0[0x10];
4041         u8         vsd_vendor_id[0x10];
4042
4043         u8         vsd[208][0x8];
4044
4045         u8         vsd_contd_psid[16][0x8];
4046 };
4047
4048 enum {
4049         MLX5_XRQC_STATE_GOOD   = 0x0,
4050         MLX5_XRQC_STATE_ERROR  = 0x1,
4051 };
4052
4053 enum {
4054         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4055         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4056 };
4057
4058 enum {
4059         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4060 };
4061
4062 struct mlx5_ifc_tag_matching_topology_context_bits {
4063         u8         log_matching_list_sz[0x4];
4064         u8         reserved_at_4[0xc];
4065         u8         append_next_index[0x10];
4066
4067         u8         sw_phase_cnt[0x10];
4068         u8         hw_phase_cnt[0x10];
4069
4070         u8         reserved_at_40[0x40];
4071 };
4072
4073 struct mlx5_ifc_xrqc_bits {
4074         u8         state[0x4];
4075         u8         rlkey[0x1];
4076         u8         reserved_at_5[0xf];
4077         u8         topology[0x4];
4078         u8         reserved_at_18[0x4];
4079         u8         offload[0x4];
4080
4081         u8         reserved_at_20[0x8];
4082         u8         user_index[0x18];
4083
4084         u8         reserved_at_40[0x8];
4085         u8         cqn[0x18];
4086
4087         u8         reserved_at_60[0xa0];
4088
4089         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4090
4091         u8         reserved_at_180[0x280];
4092
4093         struct mlx5_ifc_wq_bits wq;
4094 };
4095
4096 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4097         struct mlx5_ifc_modify_field_select_bits modify_field_select;
4098         struct mlx5_ifc_resize_field_select_bits resize_field_select;
4099         u8         reserved_at_0[0x20];
4100 };
4101
4102 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4103         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4104         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4105         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4106         u8         reserved_at_0[0x20];
4107 };
4108
4109 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4110         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4111         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4112         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4113         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4114         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4115         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4116         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4117         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4118         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4119         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4120         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4121         u8         reserved_at_0[0x7c0];
4122 };
4123
4124 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4125         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4126         u8         reserved_at_0[0x7c0];
4127 };
4128
4129 union mlx5_ifc_event_auto_bits {
4130         struct mlx5_ifc_comp_event_bits comp_event;
4131         struct mlx5_ifc_dct_events_bits dct_events;
4132         struct mlx5_ifc_qp_events_bits qp_events;
4133         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4134         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4135         struct mlx5_ifc_cq_error_bits cq_error;
4136         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4137         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4138         struct mlx5_ifc_gpio_event_bits gpio_event;
4139         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4140         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4141         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4142         u8         reserved_at_0[0xe0];
4143 };
4144
4145 struct mlx5_ifc_health_buffer_bits {
4146         u8         reserved_at_0[0x100];
4147
4148         u8         assert_existptr[0x20];
4149
4150         u8         assert_callra[0x20];
4151
4152         u8         reserved_at_140[0x20];
4153
4154         u8         time[0x20];
4155
4156         u8         fw_version[0x20];
4157
4158         u8         hw_id[0x20];
4159
4160         u8         rfr[0x1];
4161         u8         reserved_at_1c1[0x3];
4162         u8         valid[0x1];
4163         u8         severity[0x3];
4164         u8         reserved_at_1c8[0x18];
4165
4166         u8         irisc_index[0x8];
4167         u8         synd[0x8];
4168         u8         ext_synd[0x10];
4169 };
4170
4171 struct mlx5_ifc_register_loopback_control_bits {
4172         u8         no_lb[0x1];
4173         u8         reserved_at_1[0x7];
4174         u8         port[0x8];
4175         u8         reserved_at_10[0x10];
4176
4177         u8         reserved_at_20[0x60];
4178 };
4179
4180 struct mlx5_ifc_vport_tc_element_bits {
4181         u8         traffic_class[0x4];
4182         u8         reserved_at_4[0xc];
4183         u8         vport_number[0x10];
4184 };
4185
4186 struct mlx5_ifc_vport_element_bits {
4187         u8         reserved_at_0[0x10];
4188         u8         vport_number[0x10];
4189 };
4190
4191 enum {
4192         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4193         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4194         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4195 };
4196
4197 struct mlx5_ifc_tsar_element_bits {
4198         u8         reserved_at_0[0x8];
4199         u8         tsar_type[0x8];
4200         u8         reserved_at_10[0x10];
4201 };
4202
4203 enum {
4204         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4205         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4206 };
4207
4208 struct mlx5_ifc_teardown_hca_out_bits {
4209         u8         status[0x8];
4210         u8         reserved_at_8[0x18];
4211
4212         u8         syndrome[0x20];
4213
4214         u8         reserved_at_40[0x3f];
4215
4216         u8         state[0x1];
4217 };
4218
4219 enum {
4220         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4221         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4222         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4223 };
4224
4225 struct mlx5_ifc_teardown_hca_in_bits {
4226         u8         opcode[0x10];
4227         u8         reserved_at_10[0x10];
4228
4229         u8         reserved_at_20[0x10];
4230         u8         op_mod[0x10];
4231
4232         u8         reserved_at_40[0x10];
4233         u8         profile[0x10];
4234
4235         u8         reserved_at_60[0x20];
4236 };
4237
4238 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4239         u8         status[0x8];
4240         u8         reserved_at_8[0x18];
4241
4242         u8         syndrome[0x20];
4243
4244         u8         reserved_at_40[0x40];
4245 };
4246
4247 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4248         u8         opcode[0x10];
4249         u8         uid[0x10];
4250
4251         u8         reserved_at_20[0x10];
4252         u8         op_mod[0x10];
4253
4254         u8         reserved_at_40[0x8];
4255         u8         qpn[0x18];
4256
4257         u8         reserved_at_60[0x20];
4258
4259         u8         opt_param_mask[0x20];
4260
4261         u8         reserved_at_a0[0x20];
4262
4263         struct mlx5_ifc_qpc_bits qpc;
4264
4265         u8         reserved_at_800[0x80];
4266 };
4267
4268 struct mlx5_ifc_sqd2rts_qp_out_bits {
4269         u8         status[0x8];
4270         u8         reserved_at_8[0x18];
4271
4272         u8         syndrome[0x20];
4273
4274         u8         reserved_at_40[0x40];
4275 };
4276
4277 struct mlx5_ifc_sqd2rts_qp_in_bits {
4278         u8         opcode[0x10];
4279         u8         uid[0x10];
4280
4281         u8         reserved_at_20[0x10];
4282         u8         op_mod[0x10];
4283
4284         u8         reserved_at_40[0x8];
4285         u8         qpn[0x18];
4286
4287         u8         reserved_at_60[0x20];
4288
4289         u8         opt_param_mask[0x20];
4290
4291         u8         reserved_at_a0[0x20];
4292
4293         struct mlx5_ifc_qpc_bits qpc;
4294
4295         u8         reserved_at_800[0x80];
4296 };
4297
4298 struct mlx5_ifc_set_roce_address_out_bits {
4299         u8         status[0x8];
4300         u8         reserved_at_8[0x18];
4301
4302         u8         syndrome[0x20];
4303
4304         u8         reserved_at_40[0x40];
4305 };
4306
4307 struct mlx5_ifc_set_roce_address_in_bits {
4308         u8         opcode[0x10];
4309         u8         reserved_at_10[0x10];
4310
4311         u8         reserved_at_20[0x10];
4312         u8         op_mod[0x10];
4313
4314         u8         roce_address_index[0x10];
4315         u8         reserved_at_50[0xc];
4316         u8         vhca_port_num[0x4];
4317
4318         u8         reserved_at_60[0x20];
4319
4320         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4321 };
4322
4323 struct mlx5_ifc_set_mad_demux_out_bits {
4324         u8         status[0x8];
4325         u8         reserved_at_8[0x18];
4326
4327         u8         syndrome[0x20];
4328
4329         u8         reserved_at_40[0x40];
4330 };
4331
4332 enum {
4333         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4334         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4335 };
4336
4337 struct mlx5_ifc_set_mad_demux_in_bits {
4338         u8         opcode[0x10];
4339         u8         reserved_at_10[0x10];
4340
4341         u8         reserved_at_20[0x10];
4342         u8         op_mod[0x10];
4343
4344         u8         reserved_at_40[0x20];
4345
4346         u8         reserved_at_60[0x6];
4347         u8         demux_mode[0x2];
4348         u8         reserved_at_68[0x18];
4349 };
4350
4351 struct mlx5_ifc_set_l2_table_entry_out_bits {
4352         u8         status[0x8];
4353         u8         reserved_at_8[0x18];
4354
4355         u8         syndrome[0x20];
4356
4357         u8         reserved_at_40[0x40];
4358 };
4359
4360 struct mlx5_ifc_set_l2_table_entry_in_bits {
4361         u8         opcode[0x10];
4362         u8         reserved_at_10[0x10];
4363
4364         u8         reserved_at_20[0x10];
4365         u8         op_mod[0x10];
4366
4367         u8         reserved_at_40[0x60];
4368
4369         u8         reserved_at_a0[0x8];
4370         u8         table_index[0x18];
4371
4372         u8         reserved_at_c0[0x20];
4373
4374         u8         reserved_at_e0[0x13];
4375         u8         vlan_valid[0x1];
4376         u8         vlan[0xc];
4377
4378         struct mlx5_ifc_mac_address_layout_bits mac_address;
4379
4380         u8         reserved_at_140[0xc0];
4381 };
4382
4383 struct mlx5_ifc_set_issi_out_bits {
4384         u8         status[0x8];
4385         u8         reserved_at_8[0x18];
4386
4387         u8         syndrome[0x20];
4388
4389         u8         reserved_at_40[0x40];
4390 };
4391
4392 struct mlx5_ifc_set_issi_in_bits {
4393         u8         opcode[0x10];
4394         u8         reserved_at_10[0x10];
4395
4396         u8         reserved_at_20[0x10];
4397         u8         op_mod[0x10];
4398
4399         u8         reserved_at_40[0x10];
4400         u8         current_issi[0x10];
4401
4402         u8         reserved_at_60[0x20];
4403 };
4404
4405 struct mlx5_ifc_set_hca_cap_out_bits {
4406         u8         status[0x8];
4407         u8         reserved_at_8[0x18];
4408
4409         u8         syndrome[0x20];
4410
4411         u8         reserved_at_40[0x40];
4412 };
4413
4414 struct mlx5_ifc_set_hca_cap_in_bits {
4415         u8         opcode[0x10];
4416         u8         reserved_at_10[0x10];
4417
4418         u8         reserved_at_20[0x10];
4419         u8         op_mod[0x10];
4420
4421         u8         other_function[0x1];
4422         u8         reserved_at_41[0xf];
4423         u8         function_id[0x10];
4424
4425         u8         reserved_at_60[0x20];
4426
4427         union mlx5_ifc_hca_cap_union_bits capability;
4428 };
4429
4430 enum {
4431         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4432         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4433         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4434         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4435         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4436 };
4437
4438 struct mlx5_ifc_set_fte_out_bits {
4439         u8         status[0x8];
4440         u8         reserved_at_8[0x18];
4441
4442         u8         syndrome[0x20];
4443
4444         u8         reserved_at_40[0x40];
4445 };
4446
4447 struct mlx5_ifc_set_fte_in_bits {
4448         u8         opcode[0x10];
4449         u8         reserved_at_10[0x10];
4450
4451         u8         reserved_at_20[0x10];
4452         u8         op_mod[0x10];
4453
4454         u8         other_vport[0x1];
4455         u8         reserved_at_41[0xf];
4456         u8         vport_number[0x10];
4457
4458         u8         reserved_at_60[0x20];
4459
4460         u8         table_type[0x8];
4461         u8         reserved_at_88[0x18];
4462
4463         u8         reserved_at_a0[0x8];
4464         u8         table_id[0x18];
4465
4466         u8         ignore_flow_level[0x1];
4467         u8         reserved_at_c1[0x17];
4468         u8         modify_enable_mask[0x8];
4469
4470         u8         reserved_at_e0[0x20];
4471
4472         u8         flow_index[0x20];
4473
4474         u8         reserved_at_120[0xe0];
4475
4476         struct mlx5_ifc_flow_context_bits flow_context;
4477 };
4478
4479 struct mlx5_ifc_rts2rts_qp_out_bits {
4480         u8         status[0x8];
4481         u8         reserved_at_8[0x18];
4482
4483         u8         syndrome[0x20];
4484
4485         u8         reserved_at_40[0x20];
4486         u8         ece[0x20];
4487 };
4488
4489 struct mlx5_ifc_rts2rts_qp_in_bits {
4490         u8         opcode[0x10];
4491         u8         uid[0x10];
4492
4493         u8         reserved_at_20[0x10];
4494         u8         op_mod[0x10];
4495
4496         u8         reserved_at_40[0x8];
4497         u8         qpn[0x18];
4498
4499         u8         reserved_at_60[0x20];
4500
4501         u8         opt_param_mask[0x20];
4502
4503         u8         ece[0x20];
4504
4505         struct mlx5_ifc_qpc_bits qpc;
4506
4507         u8         reserved_at_800[0x80];
4508 };
4509
4510 struct mlx5_ifc_rtr2rts_qp_out_bits {
4511         u8         status[0x8];
4512         u8         reserved_at_8[0x18];
4513
4514         u8         syndrome[0x20];
4515
4516         u8         reserved_at_40[0x20];
4517         u8         ece[0x20];
4518 };
4519
4520 struct mlx5_ifc_rtr2rts_qp_in_bits {
4521         u8         opcode[0x10];
4522         u8         uid[0x10];
4523
4524         u8         reserved_at_20[0x10];
4525         u8         op_mod[0x10];
4526
4527         u8         reserved_at_40[0x8];
4528         u8         qpn[0x18];
4529
4530         u8         reserved_at_60[0x20];
4531
4532         u8         opt_param_mask[0x20];
4533
4534         u8         ece[0x20];
4535
4536         struct mlx5_ifc_qpc_bits qpc;
4537
4538         u8         reserved_at_800[0x80];
4539 };
4540
4541 struct mlx5_ifc_rst2init_qp_out_bits {
4542         u8         status[0x8];
4543         u8         reserved_at_8[0x18];
4544
4545         u8         syndrome[0x20];
4546
4547         u8         reserved_at_40[0x20];
4548         u8         ece[0x20];
4549 };
4550
4551 struct mlx5_ifc_rst2init_qp_in_bits {
4552         u8         opcode[0x10];
4553         u8         uid[0x10];
4554
4555         u8         reserved_at_20[0x10];
4556         u8         op_mod[0x10];
4557
4558         u8         reserved_at_40[0x8];
4559         u8         qpn[0x18];
4560
4561         u8         reserved_at_60[0x20];
4562
4563         u8         opt_param_mask[0x20];
4564
4565         u8         ece[0x20];
4566
4567         struct mlx5_ifc_qpc_bits qpc;
4568
4569         u8         reserved_at_800[0x80];
4570 };
4571
4572 struct mlx5_ifc_query_xrq_out_bits {
4573         u8         status[0x8];
4574         u8         reserved_at_8[0x18];
4575
4576         u8         syndrome[0x20];
4577
4578         u8         reserved_at_40[0x40];
4579
4580         struct mlx5_ifc_xrqc_bits xrq_context;
4581 };
4582
4583 struct mlx5_ifc_query_xrq_in_bits {
4584         u8         opcode[0x10];
4585         u8         reserved_at_10[0x10];
4586
4587         u8         reserved_at_20[0x10];
4588         u8         op_mod[0x10];
4589
4590         u8         reserved_at_40[0x8];
4591         u8         xrqn[0x18];
4592
4593         u8         reserved_at_60[0x20];
4594 };
4595
4596 struct mlx5_ifc_query_xrc_srq_out_bits {
4597         u8         status[0x8];
4598         u8         reserved_at_8[0x18];
4599
4600         u8         syndrome[0x20];
4601
4602         u8         reserved_at_40[0x40];
4603
4604         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4605
4606         u8         reserved_at_280[0x600];
4607
4608         u8         pas[][0x40];
4609 };
4610
4611 struct mlx5_ifc_query_xrc_srq_in_bits {
4612         u8         opcode[0x10];
4613         u8         reserved_at_10[0x10];
4614
4615         u8         reserved_at_20[0x10];
4616         u8         op_mod[0x10];
4617
4618         u8         reserved_at_40[0x8];
4619         u8         xrc_srqn[0x18];
4620
4621         u8         reserved_at_60[0x20];
4622 };
4623
4624 enum {
4625         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4626         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4627 };
4628
4629 struct mlx5_ifc_query_vport_state_out_bits {
4630         u8         status[0x8];
4631         u8         reserved_at_8[0x18];
4632
4633         u8         syndrome[0x20];
4634
4635         u8         reserved_at_40[0x20];
4636
4637         u8         reserved_at_60[0x18];
4638         u8         admin_state[0x4];
4639         u8         state[0x4];
4640 };
4641
4642 enum {
4643         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4644         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4645         MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4646 };
4647
4648 struct mlx5_ifc_arm_monitor_counter_in_bits {
4649         u8         opcode[0x10];
4650         u8         uid[0x10];
4651
4652         u8         reserved_at_20[0x10];
4653         u8         op_mod[0x10];
4654
4655         u8         reserved_at_40[0x20];
4656
4657         u8         reserved_at_60[0x20];
4658 };
4659
4660 struct mlx5_ifc_arm_monitor_counter_out_bits {
4661         u8         status[0x8];
4662         u8         reserved_at_8[0x18];
4663
4664         u8         syndrome[0x20];
4665
4666         u8         reserved_at_40[0x40];
4667 };
4668
4669 enum {
4670         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4671         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4672 };
4673
4674 enum mlx5_monitor_counter_ppcnt {
4675         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4676         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4677         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4678         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4679         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4680         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4681 };
4682
4683 enum {
4684         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4685 };
4686
4687 struct mlx5_ifc_monitor_counter_output_bits {
4688         u8         reserved_at_0[0x4];
4689         u8         type[0x4];
4690         u8         reserved_at_8[0x8];
4691         u8         counter[0x10];
4692
4693         u8         counter_group_id[0x20];
4694 };
4695
4696 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4697 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4698 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4699                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4700
4701 struct mlx5_ifc_set_monitor_counter_in_bits {
4702         u8         opcode[0x10];
4703         u8         uid[0x10];
4704
4705         u8         reserved_at_20[0x10];
4706         u8         op_mod[0x10];
4707
4708         u8         reserved_at_40[0x10];
4709         u8         num_of_counters[0x10];
4710
4711         u8         reserved_at_60[0x20];
4712
4713         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4714 };
4715
4716 struct mlx5_ifc_set_monitor_counter_out_bits {
4717         u8         status[0x8];
4718         u8         reserved_at_8[0x18];
4719
4720         u8         syndrome[0x20];
4721
4722         u8         reserved_at_40[0x40];
4723 };
4724
4725 struct mlx5_ifc_query_vport_state_in_bits {
4726         u8         opcode[0x10];
4727         u8         reserved_at_10[0x10];
4728
4729         u8         reserved_at_20[0x10];
4730         u8         op_mod[0x10];
4731
4732         u8         other_vport[0x1];
4733         u8         reserved_at_41[0xf];
4734         u8         vport_number[0x10];
4735
4736         u8         reserved_at_60[0x20];
4737 };
4738
4739 struct mlx5_ifc_query_vnic_env_out_bits {
4740         u8         status[0x8];
4741         u8         reserved_at_8[0x18];
4742
4743         u8         syndrome[0x20];
4744
4745         u8         reserved_at_40[0x40];
4746
4747         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4748 };
4749
4750 enum {
4751         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4752 };
4753
4754 struct mlx5_ifc_query_vnic_env_in_bits {
4755         u8         opcode[0x10];
4756         u8         reserved_at_10[0x10];
4757
4758         u8         reserved_at_20[0x10];
4759         u8         op_mod[0x10];
4760
4761         u8         other_vport[0x1];
4762         u8         reserved_at_41[0xf];
4763         u8         vport_number[0x10];
4764
4765         u8         reserved_at_60[0x20];
4766 };
4767
4768 struct mlx5_ifc_query_vport_counter_out_bits {
4769         u8         status[0x8];
4770         u8         reserved_at_8[0x18];
4771
4772         u8         syndrome[0x20];
4773
4774         u8         reserved_at_40[0x40];
4775
4776         struct mlx5_ifc_traffic_counter_bits received_errors;
4777
4778         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4779
4780         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4781
4782         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4783
4784         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4785
4786         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4787
4788         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4789
4790         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4791
4792         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4793
4794         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4795
4796         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4797
4798         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4799
4800         u8         reserved_at_680[0xa00];
4801 };
4802
4803 enum {
4804         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4805 };
4806
4807 struct mlx5_ifc_query_vport_counter_in_bits {
4808         u8         opcode[0x10];
4809         u8         reserved_at_10[0x10];
4810
4811         u8         reserved_at_20[0x10];
4812         u8         op_mod[0x10];
4813
4814         u8         other_vport[0x1];
4815         u8         reserved_at_41[0xb];
4816         u8         port_num[0x4];
4817         u8         vport_number[0x10];
4818
4819         u8         reserved_at_60[0x60];
4820
4821         u8         clear[0x1];
4822         u8         reserved_at_c1[0x1f];
4823
4824         u8         reserved_at_e0[0x20];
4825 };
4826
4827 struct mlx5_ifc_query_tis_out_bits {
4828         u8         status[0x8];
4829         u8         reserved_at_8[0x18];
4830
4831         u8         syndrome[0x20];
4832
4833         u8         reserved_at_40[0x40];
4834
4835         struct mlx5_ifc_tisc_bits tis_context;
4836 };
4837
4838 struct mlx5_ifc_query_tis_in_bits {
4839         u8         opcode[0x10];
4840         u8         reserved_at_10[0x10];
4841
4842         u8         reserved_at_20[0x10];
4843         u8         op_mod[0x10];
4844
4845         u8         reserved_at_40[0x8];
4846         u8         tisn[0x18];
4847
4848         u8         reserved_at_60[0x20];
4849 };
4850
4851 struct mlx5_ifc_query_tir_out_bits {
4852         u8         status[0x8];
4853         u8         reserved_at_8[0x18];
4854
4855         u8         syndrome[0x20];
4856
4857         u8         reserved_at_40[0xc0];
4858
4859         struct mlx5_ifc_tirc_bits tir_context;
4860 };
4861
4862 struct mlx5_ifc_query_tir_in_bits {
4863         u8         opcode[0x10];
4864         u8         reserved_at_10[0x10];
4865
4866         u8         reserved_at_20[0x10];
4867         u8         op_mod[0x10];
4868
4869         u8         reserved_at_40[0x8];
4870         u8         tirn[0x18];
4871
4872         u8         reserved_at_60[0x20];
4873 };
4874
4875 struct mlx5_ifc_query_srq_out_bits {
4876         u8         status[0x8];
4877         u8         reserved_at_8[0x18];
4878
4879         u8         syndrome[0x20];
4880
4881         u8         reserved_at_40[0x40];
4882
4883         struct mlx5_ifc_srqc_bits srq_context_entry;
4884
4885         u8         reserved_at_280[0x600];
4886
4887         u8         pas[][0x40];
4888 };
4889
4890 struct mlx5_ifc_query_srq_in_bits {
4891         u8         opcode[0x10];
4892         u8         reserved_at_10[0x10];
4893
4894         u8         reserved_at_20[0x10];
4895         u8         op_mod[0x10];
4896
4897         u8         reserved_at_40[0x8];
4898         u8         srqn[0x18];
4899
4900         u8         reserved_at_60[0x20];
4901 };
4902
4903 struct mlx5_ifc_query_sq_out_bits {
4904         u8         status[0x8];
4905         u8         reserved_at_8[0x18];
4906
4907         u8         syndrome[0x20];
4908
4909         u8         reserved_at_40[0xc0];
4910
4911         struct mlx5_ifc_sqc_bits sq_context;
4912 };
4913
4914 struct mlx5_ifc_query_sq_in_bits {
4915         u8         opcode[0x10];
4916         u8         reserved_at_10[0x10];
4917
4918         u8         reserved_at_20[0x10];
4919         u8         op_mod[0x10];
4920
4921         u8         reserved_at_40[0x8];
4922         u8         sqn[0x18];
4923
4924         u8         reserved_at_60[0x20];
4925 };
4926
4927 struct mlx5_ifc_query_special_contexts_out_bits {
4928         u8         status[0x8];
4929         u8         reserved_at_8[0x18];
4930
4931         u8         syndrome[0x20];
4932
4933         u8         dump_fill_mkey[0x20];
4934
4935         u8         resd_lkey[0x20];
4936
4937         u8         null_mkey[0x20];
4938
4939         u8         reserved_at_a0[0x60];
4940 };
4941
4942 struct mlx5_ifc_query_special_contexts_in_bits {
4943         u8         opcode[0x10];
4944         u8         reserved_at_10[0x10];
4945
4946         u8         reserved_at_20[0x10];
4947         u8         op_mod[0x10];
4948
4949         u8         reserved_at_40[0x40];
4950 };
4951
4952 struct mlx5_ifc_query_scheduling_element_out_bits {
4953         u8         opcode[0x10];
4954         u8         reserved_at_10[0x10];
4955
4956         u8         reserved_at_20[0x10];
4957         u8         op_mod[0x10];
4958
4959         u8         reserved_at_40[0xc0];
4960
4961         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4962
4963         u8         reserved_at_300[0x100];
4964 };
4965
4966 enum {
4967         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4968         SCHEDULING_HIERARCHY_NIC = 0x3,
4969 };
4970
4971 struct mlx5_ifc_query_scheduling_element_in_bits {
4972         u8         opcode[0x10];
4973         u8         reserved_at_10[0x10];
4974
4975         u8         reserved_at_20[0x10];
4976         u8         op_mod[0x10];
4977
4978         u8         scheduling_hierarchy[0x8];
4979         u8         reserved_at_48[0x18];
4980
4981         u8         scheduling_element_id[0x20];
4982
4983         u8         reserved_at_80[0x180];
4984 };
4985
4986 struct mlx5_ifc_query_rqt_out_bits {
4987         u8         status[0x8];
4988         u8         reserved_at_8[0x18];
4989
4990         u8         syndrome[0x20];
4991
4992         u8         reserved_at_40[0xc0];
4993
4994         struct mlx5_ifc_rqtc_bits rqt_context;
4995 };
4996
4997 struct mlx5_ifc_query_rqt_in_bits {
4998         u8         opcode[0x10];
4999         u8         reserved_at_10[0x10];
5000
5001         u8         reserved_at_20[0x10];
5002         u8         op_mod[0x10];
5003
5004         u8         reserved_at_40[0x8];
5005         u8         rqtn[0x18];
5006
5007         u8         reserved_at_60[0x20];
5008 };
5009
5010 struct mlx5_ifc_query_rq_out_bits {
5011         u8         status[0x8];
5012         u8         reserved_at_8[0x18];
5013
5014         u8         syndrome[0x20];
5015
5016         u8         reserved_at_40[0xc0];
5017
5018         struct mlx5_ifc_rqc_bits rq_context;
5019 };
5020
5021 struct mlx5_ifc_query_rq_in_bits {
5022         u8         opcode[0x10];
5023         u8         reserved_at_10[0x10];
5024
5025         u8         reserved_at_20[0x10];
5026         u8         op_mod[0x10];
5027
5028         u8         reserved_at_40[0x8];
5029         u8         rqn[0x18];
5030
5031         u8         reserved_at_60[0x20];
5032 };
5033
5034 struct mlx5_ifc_query_roce_address_out_bits {
5035         u8         status[0x8];
5036         u8         reserved_at_8[0x18];
5037
5038         u8         syndrome[0x20];
5039
5040         u8         reserved_at_40[0x40];
5041
5042         struct mlx5_ifc_roce_addr_layout_bits roce_address;
5043 };
5044
5045 struct mlx5_ifc_query_roce_address_in_bits {
5046         u8         opcode[0x10];
5047         u8         reserved_at_10[0x10];
5048
5049         u8         reserved_at_20[0x10];
5050         u8         op_mod[0x10];
5051
5052         u8         roce_address_index[0x10];
5053         u8         reserved_at_50[0xc];
5054         u8         vhca_port_num[0x4];
5055
5056         u8         reserved_at_60[0x20];
5057 };
5058
5059 struct mlx5_ifc_query_rmp_out_bits {
5060         u8         status[0x8];
5061         u8         reserved_at_8[0x18];
5062
5063         u8         syndrome[0x20];
5064
5065         u8         reserved_at_40[0xc0];
5066
5067         struct mlx5_ifc_rmpc_bits rmp_context;
5068 };
5069
5070 struct mlx5_ifc_query_rmp_in_bits {
5071         u8         opcode[0x10];
5072         u8         reserved_at_10[0x10];
5073
5074         u8         reserved_at_20[0x10];
5075         u8         op_mod[0x10];
5076
5077         u8         reserved_at_40[0x8];
5078         u8         rmpn[0x18];
5079
5080         u8         reserved_at_60[0x20];
5081 };
5082
5083 struct mlx5_ifc_query_qp_out_bits {
5084         u8         status[0x8];
5085         u8         reserved_at_8[0x18];
5086
5087         u8         syndrome[0x20];
5088
5089         u8         reserved_at_40[0x20];
5090         u8         ece[0x20];
5091
5092         u8         opt_param_mask[0x20];
5093
5094         u8         reserved_at_a0[0x20];
5095
5096         struct mlx5_ifc_qpc_bits qpc;
5097
5098         u8         reserved_at_800[0x80];
5099
5100         u8         pas[][0x40];
5101 };
5102
5103 struct mlx5_ifc_query_qp_in_bits {
5104         u8         opcode[0x10];
5105         u8         reserved_at_10[0x10];
5106
5107         u8         reserved_at_20[0x10];
5108         u8         op_mod[0x10];
5109
5110         u8         reserved_at_40[0x8];
5111         u8         qpn[0x18];
5112
5113         u8         reserved_at_60[0x20];
5114 };
5115
5116 struct mlx5_ifc_query_q_counter_out_bits {
5117         u8         status[0x8];
5118         u8         reserved_at_8[0x18];
5119
5120         u8         syndrome[0x20];
5121
5122         u8         reserved_at_40[0x40];
5123
5124         u8         rx_write_requests[0x20];
5125
5126         u8         reserved_at_a0[0x20];
5127
5128         u8         rx_read_requests[0x20];
5129
5130         u8         reserved_at_e0[0x20];
5131
5132         u8         rx_atomic_requests[0x20];
5133
5134         u8         reserved_at_120[0x20];
5135
5136         u8         rx_dct_connect[0x20];
5137
5138         u8         reserved_at_160[0x20];
5139
5140         u8         out_of_buffer[0x20];
5141
5142         u8         reserved_at_1a0[0x20];
5143
5144         u8         out_of_sequence[0x20];
5145
5146         u8         reserved_at_1e0[0x20];
5147
5148         u8         duplicate_request[0x20];
5149
5150         u8         reserved_at_220[0x20];
5151
5152         u8         rnr_nak_retry_err[0x20];
5153
5154         u8         reserved_at_260[0x20];
5155
5156         u8         packet_seq_err[0x20];
5157
5158         u8         reserved_at_2a0[0x20];
5159
5160         u8         implied_nak_seq_err[0x20];
5161
5162         u8         reserved_at_2e0[0x20];
5163
5164         u8         local_ack_timeout_err[0x20];
5165
5166         u8         reserved_at_320[0xa0];
5167
5168         u8         resp_local_length_error[0x20];
5169
5170         u8         req_local_length_error[0x20];
5171
5172         u8         resp_local_qp_error[0x20];
5173
5174         u8         local_operation_error[0x20];
5175
5176         u8         resp_local_protection[0x20];
5177
5178         u8         req_local_protection[0x20];
5179
5180         u8         resp_cqe_error[0x20];
5181
5182         u8         req_cqe_error[0x20];
5183
5184         u8         req_mw_binding[0x20];
5185
5186         u8         req_bad_response[0x20];
5187
5188         u8         req_remote_invalid_request[0x20];
5189
5190         u8         resp_remote_invalid_request[0x20];
5191
5192         u8         req_remote_access_errors[0x20];
5193
5194         u8         resp_remote_access_errors[0x20];
5195
5196         u8         req_remote_operation_errors[0x20];
5197
5198         u8         req_transport_retries_exceeded[0x20];
5199
5200         u8         cq_overflow[0x20];
5201
5202         u8         resp_cqe_flush_error[0x20];
5203
5204         u8         req_cqe_flush_error[0x20];
5205
5206         u8         reserved_at_620[0x20];
5207
5208         u8         roce_adp_retrans[0x20];
5209
5210         u8         roce_adp_retrans_to[0x20];
5211
5212         u8         roce_slow_restart[0x20];
5213
5214         u8         roce_slow_restart_cnps[0x20];
5215
5216         u8         roce_slow_restart_trans[0x20];
5217
5218         u8         reserved_at_6e0[0x120];
5219 };
5220
5221 struct mlx5_ifc_query_q_counter_in_bits {
5222         u8         opcode[0x10];
5223         u8         reserved_at_10[0x10];
5224
5225         u8         reserved_at_20[0x10];
5226         u8         op_mod[0x10];
5227
5228         u8         reserved_at_40[0x80];
5229
5230         u8         clear[0x1];
5231         u8         reserved_at_c1[0x1f];
5232
5233         u8         reserved_at_e0[0x18];
5234         u8         counter_set_id[0x8];
5235 };
5236
5237 struct mlx5_ifc_query_pages_out_bits {
5238         u8         status[0x8];
5239         u8         reserved_at_8[0x18];
5240
5241         u8         syndrome[0x20];
5242
5243         u8         embedded_cpu_function[0x1];
5244         u8         reserved_at_41[0xf];
5245         u8         function_id[0x10];
5246
5247         u8         num_pages[0x20];
5248 };
5249
5250 enum {
5251         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5252         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5253         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5254 };
5255
5256 struct mlx5_ifc_query_pages_in_bits {
5257         u8         opcode[0x10];
5258         u8         reserved_at_10[0x10];
5259
5260         u8         reserved_at_20[0x10];
5261         u8         op_mod[0x10];
5262
5263         u8         embedded_cpu_function[0x1];
5264         u8         reserved_at_41[0xf];
5265         u8         function_id[0x10];
5266
5267         u8         reserved_at_60[0x20];
5268 };
5269
5270 struct mlx5_ifc_query_nic_vport_context_out_bits {
5271         u8         status[0x8];
5272         u8         reserved_at_8[0x18];
5273
5274         u8         syndrome[0x20];
5275
5276         u8         reserved_at_40[0x40];
5277
5278         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5279 };
5280
5281 struct mlx5_ifc_query_nic_vport_context_in_bits {
5282         u8         opcode[0x10];
5283         u8         reserved_at_10[0x10];
5284
5285         u8         reserved_at_20[0x10];
5286         u8         op_mod[0x10];
5287
5288         u8         other_vport[0x1];
5289         u8         reserved_at_41[0xf];
5290         u8         vport_number[0x10];
5291
5292         u8         reserved_at_60[0x5];
5293         u8         allowed_list_type[0x3];
5294         u8         reserved_at_68[0x18];
5295 };
5296
5297 struct mlx5_ifc_query_mkey_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_at_8[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_at_40[0x40];
5304
5305         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5306
5307         u8         reserved_at_280[0x600];
5308
5309         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5310
5311         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5312 };
5313
5314 struct mlx5_ifc_query_mkey_in_bits {
5315         u8         opcode[0x10];
5316         u8         reserved_at_10[0x10];
5317
5318         u8         reserved_at_20[0x10];
5319         u8         op_mod[0x10];
5320
5321         u8         reserved_at_40[0x8];
5322         u8         mkey_index[0x18];
5323
5324         u8         pg_access[0x1];
5325         u8         reserved_at_61[0x1f];
5326 };
5327
5328 struct mlx5_ifc_query_mad_demux_out_bits {
5329         u8         status[0x8];
5330         u8         reserved_at_8[0x18];
5331
5332         u8         syndrome[0x20];
5333
5334         u8         reserved_at_40[0x40];
5335
5336         u8         mad_dumux_parameters_block[0x20];
5337 };
5338
5339 struct mlx5_ifc_query_mad_demux_in_bits {
5340         u8         opcode[0x10];
5341         u8         reserved_at_10[0x10];
5342
5343         u8         reserved_at_20[0x10];
5344         u8         op_mod[0x10];
5345
5346         u8         reserved_at_40[0x40];
5347 };
5348
5349 struct mlx5_ifc_query_l2_table_entry_out_bits {
5350         u8         status[0x8];
5351         u8         reserved_at_8[0x18];
5352
5353         u8         syndrome[0x20];
5354
5355         u8         reserved_at_40[0xa0];
5356
5357         u8         reserved_at_e0[0x13];
5358         u8         vlan_valid[0x1];
5359         u8         vlan[0xc];
5360
5361         struct mlx5_ifc_mac_address_layout_bits mac_address;
5362
5363         u8         reserved_at_140[0xc0];
5364 };
5365
5366 struct mlx5_ifc_query_l2_table_entry_in_bits {
5367         u8         opcode[0x10];
5368         u8         reserved_at_10[0x10];
5369
5370         u8         reserved_at_20[0x10];
5371         u8         op_mod[0x10];
5372
5373         u8         reserved_at_40[0x60];
5374
5375         u8         reserved_at_a0[0x8];
5376         u8         table_index[0x18];
5377
5378         u8         reserved_at_c0[0x140];
5379 };
5380
5381 struct mlx5_ifc_query_issi_out_bits {
5382         u8         status[0x8];
5383         u8         reserved_at_8[0x18];
5384
5385         u8         syndrome[0x20];
5386
5387         u8         reserved_at_40[0x10];
5388         u8         current_issi[0x10];
5389
5390         u8         reserved_at_60[0xa0];
5391
5392         u8         reserved_at_100[76][0x8];
5393         u8         supported_issi_dw0[0x20];
5394 };
5395
5396 struct mlx5_ifc_query_issi_in_bits {
5397         u8         opcode[0x10];
5398         u8         reserved_at_10[0x10];
5399
5400         u8         reserved_at_20[0x10];
5401         u8         op_mod[0x10];
5402
5403         u8         reserved_at_40[0x40];
5404 };
5405
5406 struct mlx5_ifc_set_driver_version_out_bits {
5407         u8         status[0x8];
5408         u8         reserved_0[0x18];
5409
5410         u8         syndrome[0x20];
5411         u8         reserved_1[0x40];
5412 };
5413
5414 struct mlx5_ifc_set_driver_version_in_bits {
5415         u8         opcode[0x10];
5416         u8         reserved_0[0x10];
5417
5418         u8         reserved_1[0x10];
5419         u8         op_mod[0x10];
5420
5421         u8         reserved_2[0x40];
5422         u8         driver_version[64][0x8];
5423 };
5424
5425 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5426         u8         status[0x8];
5427         u8         reserved_at_8[0x18];
5428
5429         u8         syndrome[0x20];
5430
5431         u8         reserved_at_40[0x40];
5432
5433         struct mlx5_ifc_pkey_bits pkey[];
5434 };
5435
5436 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5437         u8         opcode[0x10];
5438         u8         reserved_at_10[0x10];
5439
5440         u8         reserved_at_20[0x10];
5441         u8         op_mod[0x10];
5442
5443         u8         other_vport[0x1];
5444         u8         reserved_at_41[0xb];
5445         u8         port_num[0x4];
5446         u8         vport_number[0x10];
5447
5448         u8         reserved_at_60[0x10];
5449         u8         pkey_index[0x10];
5450 };
5451
5452 enum {
5453         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5454         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5455         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5456 };
5457
5458 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5459         u8         status[0x8];
5460         u8         reserved_at_8[0x18];
5461
5462         u8         syndrome[0x20];
5463
5464         u8         reserved_at_40[0x20];
5465
5466         u8         gids_num[0x10];
5467         u8         reserved_at_70[0x10];
5468
5469         struct mlx5_ifc_array128_auto_bits gid[];
5470 };
5471
5472 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5473         u8         opcode[0x10];
5474         u8         reserved_at_10[0x10];
5475
5476         u8         reserved_at_20[0x10];
5477         u8         op_mod[0x10];
5478
5479         u8         other_vport[0x1];
5480         u8         reserved_at_41[0xb];
5481         u8         port_num[0x4];
5482         u8         vport_number[0x10];
5483
5484         u8         reserved_at_60[0x10];
5485         u8         gid_index[0x10];
5486 };
5487
5488 struct mlx5_ifc_query_hca_vport_context_out_bits {
5489         u8         status[0x8];
5490         u8         reserved_at_8[0x18];
5491
5492         u8         syndrome[0x20];
5493
5494         u8         reserved_at_40[0x40];
5495
5496         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5497 };
5498
5499 struct mlx5_ifc_query_hca_vport_context_in_bits {
5500         u8         opcode[0x10];
5501         u8         reserved_at_10[0x10];
5502
5503         u8         reserved_at_20[0x10];
5504         u8         op_mod[0x10];
5505
5506         u8         other_vport[0x1];
5507         u8         reserved_at_41[0xb];
5508         u8         port_num[0x4];
5509         u8         vport_number[0x10];
5510
5511         u8         reserved_at_60[0x20];
5512 };
5513
5514 struct mlx5_ifc_query_hca_cap_out_bits {
5515         u8         status[0x8];
5516         u8         reserved_at_8[0x18];
5517
5518         u8         syndrome[0x20];
5519
5520         u8         reserved_at_40[0x40];
5521
5522         union mlx5_ifc_hca_cap_union_bits capability;
5523 };
5524
5525 struct mlx5_ifc_query_hca_cap_in_bits {
5526         u8         opcode[0x10];
5527         u8         reserved_at_10[0x10];
5528
5529         u8         reserved_at_20[0x10];
5530         u8         op_mod[0x10];
5531
5532         u8         other_function[0x1];
5533         u8         reserved_at_41[0xf];
5534         u8         function_id[0x10];
5535
5536         u8         reserved_at_60[0x20];
5537 };
5538
5539 struct mlx5_ifc_other_hca_cap_bits {
5540         u8         roce[0x1];
5541         u8         reserved_at_1[0x27f];
5542 };
5543
5544 struct mlx5_ifc_query_other_hca_cap_out_bits {
5545         u8         status[0x8];
5546         u8         reserved_at_8[0x18];
5547
5548         u8         syndrome[0x20];
5549
5550         u8         reserved_at_40[0x40];
5551
5552         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5553 };
5554
5555 struct mlx5_ifc_query_other_hca_cap_in_bits {
5556         u8         opcode[0x10];
5557         u8         reserved_at_10[0x10];
5558
5559         u8         reserved_at_20[0x10];
5560         u8         op_mod[0x10];
5561
5562         u8         reserved_at_40[0x10];
5563         u8         function_id[0x10];
5564
5565         u8         reserved_at_60[0x20];
5566 };
5567
5568 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5569         u8         status[0x8];
5570         u8         reserved_at_8[0x18];
5571
5572         u8         syndrome[0x20];
5573
5574         u8         reserved_at_40[0x40];
5575 };
5576
5577 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5578         u8         opcode[0x10];
5579         u8         reserved_at_10[0x10];
5580
5581         u8         reserved_at_20[0x10];
5582         u8         op_mod[0x10];
5583
5584         u8         reserved_at_40[0x10];
5585         u8         function_id[0x10];
5586         u8         field_select[0x20];
5587
5588         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5589 };
5590
5591 struct mlx5_ifc_flow_table_context_bits {
5592         u8         reformat_en[0x1];
5593         u8         decap_en[0x1];
5594         u8         sw_owner[0x1];
5595         u8         termination_table[0x1];
5596         u8         table_miss_action[0x4];
5597         u8         level[0x8];
5598         u8         reserved_at_10[0x8];
5599         u8         log_size[0x8];
5600
5601         u8         reserved_at_20[0x8];
5602         u8         table_miss_id[0x18];
5603
5604         u8         reserved_at_40[0x8];
5605         u8         lag_master_next_table_id[0x18];
5606
5607         u8         reserved_at_60[0x60];
5608
5609         u8         sw_owner_icm_root_1[0x40];
5610
5611         u8         sw_owner_icm_root_0[0x40];
5612
5613 };
5614
5615 struct mlx5_ifc_query_flow_table_out_bits {
5616         u8         status[0x8];
5617         u8         reserved_at_8[0x18];
5618
5619         u8         syndrome[0x20];
5620
5621         u8         reserved_at_40[0x80];
5622
5623         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5624 };
5625
5626 struct mlx5_ifc_query_flow_table_in_bits {
5627         u8         opcode[0x10];
5628         u8         reserved_at_10[0x10];
5629
5630         u8         reserved_at_20[0x10];
5631         u8         op_mod[0x10];
5632
5633         u8         reserved_at_40[0x40];
5634
5635         u8         table_type[0x8];
5636         u8         reserved_at_88[0x18];
5637
5638         u8         reserved_at_a0[0x8];
5639         u8         table_id[0x18];
5640
5641         u8         reserved_at_c0[0x140];
5642 };
5643
5644 struct mlx5_ifc_query_fte_out_bits {
5645         u8         status[0x8];
5646         u8         reserved_at_8[0x18];
5647
5648         u8         syndrome[0x20];
5649
5650         u8         reserved_at_40[0x1c0];
5651
5652         struct mlx5_ifc_flow_context_bits flow_context;
5653 };
5654
5655 struct mlx5_ifc_query_fte_in_bits {
5656         u8         opcode[0x10];
5657         u8         reserved_at_10[0x10];
5658
5659         u8         reserved_at_20[0x10];
5660         u8         op_mod[0x10];
5661
5662         u8         reserved_at_40[0x40];
5663
5664         u8         table_type[0x8];
5665         u8         reserved_at_88[0x18];
5666
5667         u8         reserved_at_a0[0x8];
5668         u8         table_id[0x18];
5669
5670         u8         reserved_at_c0[0x40];
5671
5672         u8         flow_index[0x20];
5673
5674         u8         reserved_at_120[0xe0];
5675 };
5676
5677 struct mlx5_ifc_match_definer_format_0_bits {
5678         u8         reserved_at_0[0x100];
5679
5680         u8         metadata_reg_c_0[0x20];
5681
5682         u8         metadata_reg_c_1[0x20];
5683
5684         u8         outer_dmac_47_16[0x20];
5685
5686         u8         outer_dmac_15_0[0x10];
5687         u8         outer_ethertype[0x10];
5688
5689         u8         reserved_at_180[0x1];
5690         u8         sx_sniffer[0x1];
5691         u8         functional_lb[0x1];
5692         u8         outer_ip_frag[0x1];
5693         u8         outer_qp_type[0x2];
5694         u8         outer_encap_type[0x2];
5695         u8         port_number[0x2];
5696         u8         outer_l3_type[0x2];
5697         u8         outer_l4_type[0x2];
5698         u8         outer_first_vlan_type[0x2];
5699         u8         outer_first_vlan_prio[0x3];
5700         u8         outer_first_vlan_cfi[0x1];
5701         u8         outer_first_vlan_vid[0xc];
5702
5703         u8         outer_l4_type_ext[0x4];
5704         u8         reserved_at_1a4[0x2];
5705         u8         outer_ipsec_layer[0x2];
5706         u8         outer_l2_type[0x2];
5707         u8         force_lb[0x1];
5708         u8         outer_l2_ok[0x1];
5709         u8         outer_l3_ok[0x1];
5710         u8         outer_l4_ok[0x1];
5711         u8         outer_second_vlan_type[0x2];
5712         u8         outer_second_vlan_prio[0x3];
5713         u8         outer_second_vlan_cfi[0x1];
5714         u8         outer_second_vlan_vid[0xc];
5715
5716         u8         outer_smac_47_16[0x20];
5717
5718         u8         outer_smac_15_0[0x10];
5719         u8         inner_ipv4_checksum_ok[0x1];
5720         u8         inner_l4_checksum_ok[0x1];
5721         u8         outer_ipv4_checksum_ok[0x1];
5722         u8         outer_l4_checksum_ok[0x1];
5723         u8         inner_l3_ok[0x1];
5724         u8         inner_l4_ok[0x1];
5725         u8         outer_l3_ok_duplicate[0x1];
5726         u8         outer_l4_ok_duplicate[0x1];
5727         u8         outer_tcp_cwr[0x1];
5728         u8         outer_tcp_ece[0x1];
5729         u8         outer_tcp_urg[0x1];
5730         u8         outer_tcp_ack[0x1];
5731         u8         outer_tcp_psh[0x1];
5732         u8         outer_tcp_rst[0x1];
5733         u8         outer_tcp_syn[0x1];
5734         u8         outer_tcp_fin[0x1];
5735 };
5736
5737 struct mlx5_ifc_match_definer_format_22_bits {
5738         u8         reserved_at_0[0x100];
5739
5740         u8         outer_ip_src_addr[0x20];
5741
5742         u8         outer_ip_dest_addr[0x20];
5743
5744         u8         outer_l4_sport[0x10];
5745         u8         outer_l4_dport[0x10];
5746
5747         u8         reserved_at_160[0x1];
5748         u8         sx_sniffer[0x1];
5749         u8         functional_lb[0x1];
5750         u8         outer_ip_frag[0x1];
5751         u8         outer_qp_type[0x2];
5752         u8         outer_encap_type[0x2];
5753         u8         port_number[0x2];
5754         u8         outer_l3_type[0x2];
5755         u8         outer_l4_type[0x2];
5756         u8         outer_first_vlan_type[0x2];
5757         u8         outer_first_vlan_prio[0x3];
5758         u8         outer_first_vlan_cfi[0x1];
5759         u8         outer_first_vlan_vid[0xc];
5760
5761         u8         metadata_reg_c_0[0x20];
5762
5763         u8         outer_dmac_47_16[0x20];
5764
5765         u8         outer_smac_47_16[0x20];
5766
5767         u8         outer_smac_15_0[0x10];
5768         u8         outer_dmac_15_0[0x10];
5769 };
5770
5771 struct mlx5_ifc_match_definer_format_23_bits {
5772         u8         reserved_at_0[0x100];
5773
5774         u8         inner_ip_src_addr[0x20];
5775
5776         u8         inner_ip_dest_addr[0x20];
5777
5778         u8         inner_l4_sport[0x10];
5779         u8         inner_l4_dport[0x10];
5780
5781         u8         reserved_at_160[0x1];
5782         u8         sx_sniffer[0x1];
5783         u8         functional_lb[0x1];
5784         u8         inner_ip_frag[0x1];
5785         u8         inner_qp_type[0x2];
5786         u8         inner_encap_type[0x2];
5787         u8         port_number[0x2];
5788         u8         inner_l3_type[0x2];
5789         u8         inner_l4_type[0x2];
5790         u8         inner_first_vlan_type[0x2];
5791         u8         inner_first_vlan_prio[0x3];
5792         u8         inner_first_vlan_cfi[0x1];
5793         u8         inner_first_vlan_vid[0xc];
5794
5795         u8         tunnel_header_0[0x20];
5796
5797         u8         inner_dmac_47_16[0x20];
5798
5799         u8         inner_smac_47_16[0x20];
5800
5801         u8         inner_smac_15_0[0x10];
5802         u8         inner_dmac_15_0[0x10];
5803 };
5804
5805 struct mlx5_ifc_match_definer_format_29_bits {
5806         u8         reserved_at_0[0xc0];
5807
5808         u8         outer_ip_dest_addr[0x80];
5809
5810         u8         outer_ip_src_addr[0x80];
5811
5812         u8         outer_l4_sport[0x10];
5813         u8         outer_l4_dport[0x10];
5814
5815         u8         reserved_at_1e0[0x20];
5816 };
5817
5818 struct mlx5_ifc_match_definer_format_30_bits {
5819         u8         reserved_at_0[0xa0];
5820
5821         u8         outer_ip_dest_addr[0x80];
5822
5823         u8         outer_ip_src_addr[0x80];
5824
5825         u8         outer_dmac_47_16[0x20];
5826
5827         u8         outer_smac_47_16[0x20];
5828
5829         u8         outer_smac_15_0[0x10];
5830         u8         outer_dmac_15_0[0x10];
5831 };
5832
5833 struct mlx5_ifc_match_definer_format_31_bits {
5834         u8         reserved_at_0[0xc0];
5835
5836         u8         inner_ip_dest_addr[0x80];
5837
5838         u8         inner_ip_src_addr[0x80];
5839
5840         u8         inner_l4_sport[0x10];
5841         u8         inner_l4_dport[0x10];
5842
5843         u8         reserved_at_1e0[0x20];
5844 };
5845
5846 struct mlx5_ifc_match_definer_format_32_bits {
5847         u8         reserved_at_0[0xa0];
5848
5849         u8         inner_ip_dest_addr[0x80];
5850
5851         u8         inner_ip_src_addr[0x80];
5852
5853         u8         inner_dmac_47_16[0x20];
5854
5855         u8         inner_smac_47_16[0x20];
5856
5857         u8         inner_smac_15_0[0x10];
5858         u8         inner_dmac_15_0[0x10];
5859 };
5860
5861 struct mlx5_ifc_match_definer_bits {
5862         u8         modify_field_select[0x40];
5863
5864         u8         reserved_at_40[0x40];
5865
5866         u8         reserved_at_80[0x10];
5867         u8         format_id[0x10];
5868
5869         u8         reserved_at_a0[0x160];
5870
5871         u8         match_mask[16][0x20];
5872 };
5873
5874 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
5875         u8         opcode[0x10];
5876         u8         uid[0x10];
5877
5878         u8         vhca_tunnel_id[0x10];
5879         u8         obj_type[0x10];
5880
5881         u8         obj_id[0x20];
5882
5883         u8         reserved_at_60[0x20];
5884 };
5885
5886 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
5887         u8         status[0x8];
5888         u8         reserved_at_8[0x18];
5889
5890         u8         syndrome[0x20];
5891
5892         u8         obj_id[0x20];
5893
5894         u8         reserved_at_60[0x20];
5895 };
5896
5897 struct mlx5_ifc_create_match_definer_in_bits {
5898         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
5899
5900         struct mlx5_ifc_match_definer_bits obj_context;
5901 };
5902
5903 struct mlx5_ifc_create_match_definer_out_bits {
5904         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
5905 };
5906
5907 enum {
5908         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5909         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5910         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5911         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5912         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5913         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
5914 };
5915
5916 struct mlx5_ifc_query_flow_group_out_bits {
5917         u8         status[0x8];
5918         u8         reserved_at_8[0x18];
5919
5920         u8         syndrome[0x20];
5921
5922         u8         reserved_at_40[0xa0];
5923
5924         u8         start_flow_index[0x20];
5925
5926         u8         reserved_at_100[0x20];
5927
5928         u8         end_flow_index[0x20];
5929
5930         u8         reserved_at_140[0xa0];
5931
5932         u8         reserved_at_1e0[0x18];
5933         u8         match_criteria_enable[0x8];
5934
5935         struct mlx5_ifc_fte_match_param_bits match_criteria;
5936
5937         u8         reserved_at_1200[0xe00];
5938 };
5939
5940 struct mlx5_ifc_query_flow_group_in_bits {
5941         u8         opcode[0x10];
5942         u8         reserved_at_10[0x10];
5943
5944         u8         reserved_at_20[0x10];
5945         u8         op_mod[0x10];
5946
5947         u8         reserved_at_40[0x40];
5948
5949         u8         table_type[0x8];
5950         u8         reserved_at_88[0x18];
5951
5952         u8         reserved_at_a0[0x8];
5953         u8         table_id[0x18];
5954
5955         u8         group_id[0x20];
5956
5957         u8         reserved_at_e0[0x120];
5958 };
5959
5960 struct mlx5_ifc_query_flow_counter_out_bits {
5961         u8         status[0x8];
5962         u8         reserved_at_8[0x18];
5963
5964         u8         syndrome[0x20];
5965
5966         u8         reserved_at_40[0x40];
5967
5968         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5969 };
5970
5971 struct mlx5_ifc_query_flow_counter_in_bits {
5972         u8         opcode[0x10];
5973         u8         reserved_at_10[0x10];
5974
5975         u8         reserved_at_20[0x10];
5976         u8         op_mod[0x10];
5977
5978         u8         reserved_at_40[0x80];
5979
5980         u8         clear[0x1];
5981         u8         reserved_at_c1[0xf];
5982         u8         num_of_counters[0x10];
5983
5984         u8         flow_counter_id[0x20];
5985 };
5986
5987 struct mlx5_ifc_query_esw_vport_context_out_bits {
5988         u8         status[0x8];
5989         u8         reserved_at_8[0x18];
5990
5991         u8         syndrome[0x20];
5992
5993         u8         reserved_at_40[0x40];
5994
5995         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5996 };
5997
5998 struct mlx5_ifc_query_esw_vport_context_in_bits {
5999         u8         opcode[0x10];
6000         u8         reserved_at_10[0x10];
6001
6002         u8         reserved_at_20[0x10];
6003         u8         op_mod[0x10];
6004
6005         u8         other_vport[0x1];
6006         u8         reserved_at_41[0xf];
6007         u8         vport_number[0x10];
6008
6009         u8         reserved_at_60[0x20];
6010 };
6011
6012 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6013         u8         status[0x8];
6014         u8         reserved_at_8[0x18];
6015
6016         u8         syndrome[0x20];
6017
6018         u8         reserved_at_40[0x40];
6019 };
6020
6021 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6022         u8         reserved_at_0[0x1b];
6023         u8         fdb_to_vport_reg_c_id[0x1];
6024         u8         vport_cvlan_insert[0x1];
6025         u8         vport_svlan_insert[0x1];
6026         u8         vport_cvlan_strip[0x1];
6027         u8         vport_svlan_strip[0x1];
6028 };
6029
6030 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6031         u8         opcode[0x10];
6032         u8         reserved_at_10[0x10];
6033
6034         u8         reserved_at_20[0x10];
6035         u8         op_mod[0x10];
6036
6037         u8         other_vport[0x1];
6038         u8         reserved_at_41[0xf];
6039         u8         vport_number[0x10];
6040
6041         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6042
6043         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6044 };
6045
6046 struct mlx5_ifc_query_eq_out_bits {
6047         u8         status[0x8];
6048         u8         reserved_at_8[0x18];
6049
6050         u8         syndrome[0x20];
6051
6052         u8         reserved_at_40[0x40];
6053
6054         struct mlx5_ifc_eqc_bits eq_context_entry;
6055
6056         u8         reserved_at_280[0x40];
6057
6058         u8         event_bitmask[0x40];
6059
6060         u8         reserved_at_300[0x580];
6061
6062         u8         pas[][0x40];
6063 };
6064
6065 struct mlx5_ifc_query_eq_in_bits {
6066         u8         opcode[0x10];
6067         u8         reserved_at_10[0x10];
6068
6069         u8         reserved_at_20[0x10];
6070         u8         op_mod[0x10];
6071
6072         u8         reserved_at_40[0x18];
6073         u8         eq_number[0x8];
6074
6075         u8         reserved_at_60[0x20];
6076 };
6077
6078 struct mlx5_ifc_packet_reformat_context_in_bits {
6079         u8         reformat_type[0x8];
6080         u8         reserved_at_8[0x4];
6081         u8         reformat_param_0[0x4];
6082         u8         reserved_at_10[0x6];
6083         u8         reformat_data_size[0xa];
6084
6085         u8         reformat_param_1[0x8];
6086         u8         reserved_at_28[0x8];
6087         u8         reformat_data[2][0x8];
6088
6089         u8         more_reformat_data[][0x8];
6090 };
6091
6092 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6093         u8         status[0x8];
6094         u8         reserved_at_8[0x18];
6095
6096         u8         syndrome[0x20];
6097
6098         u8         reserved_at_40[0xa0];
6099
6100         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6101 };
6102
6103 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6104         u8         opcode[0x10];
6105         u8         reserved_at_10[0x10];
6106
6107         u8         reserved_at_20[0x10];
6108         u8         op_mod[0x10];
6109
6110         u8         packet_reformat_id[0x20];
6111
6112         u8         reserved_at_60[0xa0];
6113 };
6114
6115 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6116         u8         status[0x8];
6117         u8         reserved_at_8[0x18];
6118
6119         u8         syndrome[0x20];
6120
6121         u8         packet_reformat_id[0x20];
6122
6123         u8         reserved_at_60[0x20];
6124 };
6125
6126 enum {
6127         MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6128         MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6129         MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6130 };
6131
6132 enum mlx5_reformat_ctx_type {
6133         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6134         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6135         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6136         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6137         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6138         MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6139         MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6140 };
6141
6142 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6143         u8         opcode[0x10];
6144         u8         reserved_at_10[0x10];
6145
6146         u8         reserved_at_20[0x10];
6147         u8         op_mod[0x10];
6148
6149         u8         reserved_at_40[0xa0];
6150
6151         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6152 };
6153
6154 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6155         u8         status[0x8];
6156         u8         reserved_at_8[0x18];
6157
6158         u8         syndrome[0x20];
6159
6160         u8         reserved_at_40[0x40];
6161 };
6162
6163 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6164         u8         opcode[0x10];
6165         u8         reserved_at_10[0x10];
6166
6167         u8         reserved_20[0x10];
6168         u8         op_mod[0x10];
6169
6170         u8         packet_reformat_id[0x20];
6171
6172         u8         reserved_60[0x20];
6173 };
6174
6175 struct mlx5_ifc_set_action_in_bits {
6176         u8         action_type[0x4];
6177         u8         field[0xc];
6178         u8         reserved_at_10[0x3];
6179         u8         offset[0x5];
6180         u8         reserved_at_18[0x3];
6181         u8         length[0x5];
6182
6183         u8         data[0x20];
6184 };
6185
6186 struct mlx5_ifc_add_action_in_bits {
6187         u8         action_type[0x4];
6188         u8         field[0xc];
6189         u8         reserved_at_10[0x10];
6190
6191         u8         data[0x20];
6192 };
6193
6194 struct mlx5_ifc_copy_action_in_bits {
6195         u8         action_type[0x4];
6196         u8         src_field[0xc];
6197         u8         reserved_at_10[0x3];
6198         u8         src_offset[0x5];
6199         u8         reserved_at_18[0x3];
6200         u8         length[0x5];
6201
6202         u8         reserved_at_20[0x4];
6203         u8         dst_field[0xc];
6204         u8         reserved_at_30[0x3];
6205         u8         dst_offset[0x5];
6206         u8         reserved_at_38[0x8];
6207 };
6208
6209 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6210         struct mlx5_ifc_set_action_in_bits  set_action_in;
6211         struct mlx5_ifc_add_action_in_bits  add_action_in;
6212         struct mlx5_ifc_copy_action_in_bits copy_action_in;
6213         u8         reserved_at_0[0x40];
6214 };
6215
6216 enum {
6217         MLX5_ACTION_TYPE_SET   = 0x1,
6218         MLX5_ACTION_TYPE_ADD   = 0x2,
6219         MLX5_ACTION_TYPE_COPY  = 0x3,
6220 };
6221
6222 enum {
6223         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6224         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6225         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6226         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6227         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6228         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6229         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6230         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6231         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6232         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6233         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6234         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6235         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6236         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6237         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6238         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6239         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6240         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6241         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6242         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6243         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6244         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6245         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6246         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6247         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6248         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6249         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6250         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6251         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6252         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6253         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6254         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6255         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6256         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6257         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6258         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6259         MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6260         MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6261         MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6262 };
6263
6264 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6265         u8         status[0x8];
6266         u8         reserved_at_8[0x18];
6267
6268         u8         syndrome[0x20];
6269
6270         u8         modify_header_id[0x20];
6271
6272         u8         reserved_at_60[0x20];
6273 };
6274
6275 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6276         u8         opcode[0x10];
6277         u8         reserved_at_10[0x10];
6278
6279         u8         reserved_at_20[0x10];
6280         u8         op_mod[0x10];
6281
6282         u8         reserved_at_40[0x20];
6283
6284         u8         table_type[0x8];
6285         u8         reserved_at_68[0x10];
6286         u8         num_of_actions[0x8];
6287
6288         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6289 };
6290
6291 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6292         u8         status[0x8];
6293         u8         reserved_at_8[0x18];
6294
6295         u8         syndrome[0x20];
6296
6297         u8         reserved_at_40[0x40];
6298 };
6299
6300 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6301         u8         opcode[0x10];
6302         u8         reserved_at_10[0x10];
6303
6304         u8         reserved_at_20[0x10];
6305         u8         op_mod[0x10];
6306
6307         u8         modify_header_id[0x20];
6308
6309         u8         reserved_at_60[0x20];
6310 };
6311
6312 struct mlx5_ifc_query_modify_header_context_in_bits {
6313         u8         opcode[0x10];
6314         u8         uid[0x10];
6315
6316         u8         reserved_at_20[0x10];
6317         u8         op_mod[0x10];
6318
6319         u8         modify_header_id[0x20];
6320
6321         u8         reserved_at_60[0xa0];
6322 };
6323
6324 struct mlx5_ifc_query_dct_out_bits {
6325         u8         status[0x8];
6326         u8         reserved_at_8[0x18];
6327
6328         u8         syndrome[0x20];
6329
6330         u8         reserved_at_40[0x40];
6331
6332         struct mlx5_ifc_dctc_bits dct_context_entry;
6333
6334         u8         reserved_at_280[0x180];
6335 };
6336
6337 struct mlx5_ifc_query_dct_in_bits {
6338         u8         opcode[0x10];
6339         u8         reserved_at_10[0x10];
6340
6341         u8         reserved_at_20[0x10];
6342         u8         op_mod[0x10];
6343
6344         u8         reserved_at_40[0x8];
6345         u8         dctn[0x18];
6346
6347         u8         reserved_at_60[0x20];
6348 };
6349
6350 struct mlx5_ifc_query_cq_out_bits {
6351         u8         status[0x8];
6352         u8         reserved_at_8[0x18];
6353
6354         u8         syndrome[0x20];
6355
6356         u8         reserved_at_40[0x40];
6357
6358         struct mlx5_ifc_cqc_bits cq_context;
6359
6360         u8         reserved_at_280[0x600];
6361
6362         u8         pas[][0x40];
6363 };
6364
6365 struct mlx5_ifc_query_cq_in_bits {
6366         u8         opcode[0x10];
6367         u8         reserved_at_10[0x10];
6368
6369         u8         reserved_at_20[0x10];
6370         u8         op_mod[0x10];
6371
6372         u8         reserved_at_40[0x8];
6373         u8         cqn[0x18];
6374
6375         u8         reserved_at_60[0x20];
6376 };
6377
6378 struct mlx5_ifc_query_cong_status_out_bits {
6379         u8         status[0x8];
6380         u8         reserved_at_8[0x18];
6381
6382         u8         syndrome[0x20];
6383
6384         u8         reserved_at_40[0x20];
6385
6386         u8         enable[0x1];
6387         u8         tag_enable[0x1];
6388         u8         reserved_at_62[0x1e];
6389 };
6390
6391 struct mlx5_ifc_query_cong_status_in_bits {
6392         u8         opcode[0x10];
6393         u8         reserved_at_10[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         reserved_at_40[0x18];
6399         u8         priority[0x4];
6400         u8         cong_protocol[0x4];
6401
6402         u8         reserved_at_60[0x20];
6403 };
6404
6405 struct mlx5_ifc_query_cong_statistics_out_bits {
6406         u8         status[0x8];
6407         u8         reserved_at_8[0x18];
6408
6409         u8         syndrome[0x20];
6410
6411         u8         reserved_at_40[0x40];
6412
6413         u8         rp_cur_flows[0x20];
6414
6415         u8         sum_flows[0x20];
6416
6417         u8         rp_cnp_ignored_high[0x20];
6418
6419         u8         rp_cnp_ignored_low[0x20];
6420
6421         u8         rp_cnp_handled_high[0x20];
6422
6423         u8         rp_cnp_handled_low[0x20];
6424
6425         u8         reserved_at_140[0x100];
6426
6427         u8         time_stamp_high[0x20];
6428
6429         u8         time_stamp_low[0x20];
6430
6431         u8         accumulators_period[0x20];
6432
6433         u8         np_ecn_marked_roce_packets_high[0x20];
6434
6435         u8         np_ecn_marked_roce_packets_low[0x20];
6436
6437         u8         np_cnp_sent_high[0x20];
6438
6439         u8         np_cnp_sent_low[0x20];
6440
6441         u8         reserved_at_320[0x560];
6442 };
6443
6444 struct mlx5_ifc_query_cong_statistics_in_bits {
6445         u8         opcode[0x10];
6446         u8         reserved_at_10[0x10];
6447
6448         u8         reserved_at_20[0x10];
6449         u8         op_mod[0x10];
6450
6451         u8         clear[0x1];
6452         u8         reserved_at_41[0x1f];
6453
6454         u8         reserved_at_60[0x20];
6455 };
6456
6457 struct mlx5_ifc_query_cong_params_out_bits {
6458         u8         status[0x8];
6459         u8         reserved_at_8[0x18];
6460
6461         u8         syndrome[0x20];
6462
6463         u8         reserved_at_40[0x40];
6464
6465         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6466 };
6467
6468 struct mlx5_ifc_query_cong_params_in_bits {
6469         u8         opcode[0x10];
6470         u8         reserved_at_10[0x10];
6471
6472         u8         reserved_at_20[0x10];
6473         u8         op_mod[0x10];
6474
6475         u8         reserved_at_40[0x1c];
6476         u8         cong_protocol[0x4];
6477
6478         u8         reserved_at_60[0x20];
6479 };
6480
6481 struct mlx5_ifc_query_adapter_out_bits {
6482         u8         status[0x8];
6483         u8         reserved_at_8[0x18];
6484
6485         u8         syndrome[0x20];
6486
6487         u8         reserved_at_40[0x40];
6488
6489         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6490 };
6491
6492 struct mlx5_ifc_query_adapter_in_bits {
6493         u8         opcode[0x10];
6494         u8         reserved_at_10[0x10];
6495
6496         u8         reserved_at_20[0x10];
6497         u8         op_mod[0x10];
6498
6499         u8         reserved_at_40[0x40];
6500 };
6501
6502 struct mlx5_ifc_qp_2rst_out_bits {
6503         u8         status[0x8];
6504         u8         reserved_at_8[0x18];
6505
6506         u8         syndrome[0x20];
6507
6508         u8         reserved_at_40[0x40];
6509 };
6510
6511 struct mlx5_ifc_qp_2rst_in_bits {
6512         u8         opcode[0x10];
6513         u8         uid[0x10];
6514
6515         u8         reserved_at_20[0x10];
6516         u8         op_mod[0x10];
6517
6518         u8         reserved_at_40[0x8];
6519         u8         qpn[0x18];
6520
6521         u8         reserved_at_60[0x20];
6522 };
6523
6524 struct mlx5_ifc_qp_2err_out_bits {
6525         u8         status[0x8];
6526         u8         reserved_at_8[0x18];
6527
6528         u8         syndrome[0x20];
6529
6530         u8         reserved_at_40[0x40];
6531 };
6532
6533 struct mlx5_ifc_qp_2err_in_bits {
6534         u8         opcode[0x10];
6535         u8         uid[0x10];
6536
6537         u8         reserved_at_20[0x10];
6538         u8         op_mod[0x10];
6539
6540         u8         reserved_at_40[0x8];
6541         u8         qpn[0x18];
6542
6543         u8         reserved_at_60[0x20];
6544 };
6545
6546 struct mlx5_ifc_page_fault_resume_out_bits {
6547         u8         status[0x8];
6548         u8         reserved_at_8[0x18];
6549
6550         u8         syndrome[0x20];
6551
6552         u8         reserved_at_40[0x40];
6553 };
6554
6555 struct mlx5_ifc_page_fault_resume_in_bits {
6556         u8         opcode[0x10];
6557         u8         reserved_at_10[0x10];
6558
6559         u8         reserved_at_20[0x10];
6560         u8         op_mod[0x10];
6561
6562         u8         error[0x1];
6563         u8         reserved_at_41[0x4];
6564         u8         page_fault_type[0x3];
6565         u8         wq_number[0x18];
6566
6567         u8         reserved_at_60[0x8];
6568         u8         token[0x18];
6569 };
6570
6571 struct mlx5_ifc_nop_out_bits {
6572         u8         status[0x8];
6573         u8         reserved_at_8[0x18];
6574
6575         u8         syndrome[0x20];
6576
6577         u8         reserved_at_40[0x40];
6578 };
6579
6580 struct mlx5_ifc_nop_in_bits {
6581         u8         opcode[0x10];
6582         u8         reserved_at_10[0x10];
6583
6584         u8         reserved_at_20[0x10];
6585         u8         op_mod[0x10];
6586
6587         u8         reserved_at_40[0x40];
6588 };
6589
6590 struct mlx5_ifc_modify_vport_state_out_bits {
6591         u8         status[0x8];
6592         u8         reserved_at_8[0x18];
6593
6594         u8         syndrome[0x20];
6595
6596         u8         reserved_at_40[0x40];
6597 };
6598
6599 struct mlx5_ifc_modify_vport_state_in_bits {
6600         u8         opcode[0x10];
6601         u8         reserved_at_10[0x10];
6602
6603         u8         reserved_at_20[0x10];
6604         u8         op_mod[0x10];
6605
6606         u8         other_vport[0x1];
6607         u8         reserved_at_41[0xf];
6608         u8         vport_number[0x10];
6609
6610         u8         reserved_at_60[0x18];
6611         u8         admin_state[0x4];
6612         u8         reserved_at_7c[0x4];
6613 };
6614
6615 struct mlx5_ifc_modify_tis_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_modify_tis_bitmask_bits {
6625         u8         reserved_at_0[0x20];
6626
6627         u8         reserved_at_20[0x1d];
6628         u8         lag_tx_port_affinity[0x1];
6629         u8         strict_lag_tx_port_affinity[0x1];
6630         u8         prio[0x1];
6631 };
6632
6633 struct mlx5_ifc_modify_tis_in_bits {
6634         u8         opcode[0x10];
6635         u8         uid[0x10];
6636
6637         u8         reserved_at_20[0x10];
6638         u8         op_mod[0x10];
6639
6640         u8         reserved_at_40[0x8];
6641         u8         tisn[0x18];
6642
6643         u8         reserved_at_60[0x20];
6644
6645         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6646
6647         u8         reserved_at_c0[0x40];
6648
6649         struct mlx5_ifc_tisc_bits ctx;
6650 };
6651
6652 struct mlx5_ifc_modify_tir_bitmask_bits {
6653         u8         reserved_at_0[0x20];
6654
6655         u8         reserved_at_20[0x1b];
6656         u8         self_lb_en[0x1];
6657         u8         reserved_at_3c[0x1];
6658         u8         hash[0x1];
6659         u8         reserved_at_3e[0x1];
6660         u8         lro[0x1];
6661 };
6662
6663 struct mlx5_ifc_modify_tir_out_bits {
6664         u8         status[0x8];
6665         u8         reserved_at_8[0x18];
6666
6667         u8         syndrome[0x20];
6668
6669         u8         reserved_at_40[0x40];
6670 };
6671
6672 struct mlx5_ifc_modify_tir_in_bits {
6673         u8         opcode[0x10];
6674         u8         uid[0x10];
6675
6676         u8         reserved_at_20[0x10];
6677         u8         op_mod[0x10];
6678
6679         u8         reserved_at_40[0x8];
6680         u8         tirn[0x18];
6681
6682         u8         reserved_at_60[0x20];
6683
6684         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6685
6686         u8         reserved_at_c0[0x40];
6687
6688         struct mlx5_ifc_tirc_bits ctx;
6689 };
6690
6691 struct mlx5_ifc_modify_sq_out_bits {
6692         u8         status[0x8];
6693         u8         reserved_at_8[0x18];
6694
6695         u8         syndrome[0x20];
6696
6697         u8         reserved_at_40[0x40];
6698 };
6699
6700 struct mlx5_ifc_modify_sq_in_bits {
6701         u8         opcode[0x10];
6702         u8         uid[0x10];
6703
6704         u8         reserved_at_20[0x10];
6705         u8         op_mod[0x10];
6706
6707         u8         sq_state[0x4];
6708         u8         reserved_at_44[0x4];
6709         u8         sqn[0x18];
6710
6711         u8         reserved_at_60[0x20];
6712
6713         u8         modify_bitmask[0x40];
6714
6715         u8         reserved_at_c0[0x40];
6716
6717         struct mlx5_ifc_sqc_bits ctx;
6718 };
6719
6720 struct mlx5_ifc_modify_scheduling_element_out_bits {
6721         u8         status[0x8];
6722         u8         reserved_at_8[0x18];
6723
6724         u8         syndrome[0x20];
6725
6726         u8         reserved_at_40[0x1c0];
6727 };
6728
6729 enum {
6730         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6731         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6732 };
6733
6734 struct mlx5_ifc_modify_scheduling_element_in_bits {
6735         u8         opcode[0x10];
6736         u8         reserved_at_10[0x10];
6737
6738         u8         reserved_at_20[0x10];
6739         u8         op_mod[0x10];
6740
6741         u8         scheduling_hierarchy[0x8];
6742         u8         reserved_at_48[0x18];
6743
6744         u8         scheduling_element_id[0x20];
6745
6746         u8         reserved_at_80[0x20];
6747
6748         u8         modify_bitmask[0x20];
6749
6750         u8         reserved_at_c0[0x40];
6751
6752         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6753
6754         u8         reserved_at_300[0x100];
6755 };
6756
6757 struct mlx5_ifc_modify_rqt_out_bits {
6758         u8         status[0x8];
6759         u8         reserved_at_8[0x18];
6760
6761         u8         syndrome[0x20];
6762
6763         u8         reserved_at_40[0x40];
6764 };
6765
6766 struct mlx5_ifc_rqt_bitmask_bits {
6767         u8         reserved_at_0[0x20];
6768
6769         u8         reserved_at_20[0x1f];
6770         u8         rqn_list[0x1];
6771 };
6772
6773 struct mlx5_ifc_modify_rqt_in_bits {
6774         u8         opcode[0x10];
6775         u8         uid[0x10];
6776
6777         u8         reserved_at_20[0x10];
6778         u8         op_mod[0x10];
6779
6780         u8         reserved_at_40[0x8];
6781         u8         rqtn[0x18];
6782
6783         u8         reserved_at_60[0x20];
6784
6785         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6786
6787         u8         reserved_at_c0[0x40];
6788
6789         struct mlx5_ifc_rqtc_bits ctx;
6790 };
6791
6792 struct mlx5_ifc_modify_rq_out_bits {
6793         u8         status[0x8];
6794         u8         reserved_at_8[0x18];
6795
6796         u8         syndrome[0x20];
6797
6798         u8         reserved_at_40[0x40];
6799 };
6800
6801 enum {
6802         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6803         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6804         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6805 };
6806
6807 struct mlx5_ifc_modify_rq_in_bits {
6808         u8         opcode[0x10];
6809         u8         uid[0x10];
6810
6811         u8         reserved_at_20[0x10];
6812         u8         op_mod[0x10];
6813
6814         u8         rq_state[0x4];
6815         u8         reserved_at_44[0x4];
6816         u8         rqn[0x18];
6817
6818         u8         reserved_at_60[0x20];
6819
6820         u8         modify_bitmask[0x40];
6821
6822         u8         reserved_at_c0[0x40];
6823
6824         struct mlx5_ifc_rqc_bits ctx;
6825 };
6826
6827 struct mlx5_ifc_modify_rmp_out_bits {
6828         u8         status[0x8];
6829         u8         reserved_at_8[0x18];
6830
6831         u8         syndrome[0x20];
6832
6833         u8         reserved_at_40[0x40];
6834 };
6835
6836 struct mlx5_ifc_rmp_bitmask_bits {
6837         u8         reserved_at_0[0x20];
6838
6839         u8         reserved_at_20[0x1f];
6840         u8         lwm[0x1];
6841 };
6842
6843 struct mlx5_ifc_modify_rmp_in_bits {
6844         u8         opcode[0x10];
6845         u8         uid[0x10];
6846
6847         u8         reserved_at_20[0x10];
6848         u8         op_mod[0x10];
6849
6850         u8         rmp_state[0x4];
6851         u8         reserved_at_44[0x4];
6852         u8         rmpn[0x18];
6853
6854         u8         reserved_at_60[0x20];
6855
6856         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6857
6858         u8         reserved_at_c0[0x40];
6859
6860         struct mlx5_ifc_rmpc_bits ctx;
6861 };
6862
6863 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6864         u8         status[0x8];
6865         u8         reserved_at_8[0x18];
6866
6867         u8         syndrome[0x20];
6868
6869         u8         reserved_at_40[0x40];
6870 };
6871
6872 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6873         u8         reserved_at_0[0x12];
6874         u8         affiliation[0x1];
6875         u8         reserved_at_13[0x1];
6876         u8         disable_uc_local_lb[0x1];
6877         u8         disable_mc_local_lb[0x1];
6878         u8         node_guid[0x1];
6879         u8         port_guid[0x1];
6880         u8         min_inline[0x1];
6881         u8         mtu[0x1];
6882         u8         change_event[0x1];
6883         u8         promisc[0x1];
6884         u8         permanent_address[0x1];
6885         u8         addresses_list[0x1];
6886         u8         roce_en[0x1];
6887         u8         reserved_at_1f[0x1];
6888 };
6889
6890 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6891         u8         opcode[0x10];
6892         u8         reserved_at_10[0x10];
6893
6894         u8         reserved_at_20[0x10];
6895         u8         op_mod[0x10];
6896
6897         u8         other_vport[0x1];
6898         u8         reserved_at_41[0xf];
6899         u8         vport_number[0x10];
6900
6901         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6902
6903         u8         reserved_at_80[0x780];
6904
6905         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6906 };
6907
6908 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x40];
6915 };
6916
6917 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6918         u8         opcode[0x10];
6919         u8         reserved_at_10[0x10];
6920
6921         u8         reserved_at_20[0x10];
6922         u8         op_mod[0x10];
6923
6924         u8         other_vport[0x1];
6925         u8         reserved_at_41[0xb];
6926         u8         port_num[0x4];
6927         u8         vport_number[0x10];
6928
6929         u8         reserved_at_60[0x20];
6930
6931         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6932 };
6933
6934 struct mlx5_ifc_modify_cq_out_bits {
6935         u8         status[0x8];
6936         u8         reserved_at_8[0x18];
6937
6938         u8         syndrome[0x20];
6939
6940         u8         reserved_at_40[0x40];
6941 };
6942
6943 enum {
6944         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6945         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6946 };
6947
6948 struct mlx5_ifc_modify_cq_in_bits {
6949         u8         opcode[0x10];
6950         u8         uid[0x10];
6951
6952         u8         reserved_at_20[0x10];
6953         u8         op_mod[0x10];
6954
6955         u8         reserved_at_40[0x8];
6956         u8         cqn[0x18];
6957
6958         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6959
6960         struct mlx5_ifc_cqc_bits cq_context;
6961
6962         u8         reserved_at_280[0x60];
6963
6964         u8         cq_umem_valid[0x1];
6965         u8         reserved_at_2e1[0x1f];
6966
6967         u8         reserved_at_300[0x580];
6968
6969         u8         pas[][0x40];
6970 };
6971
6972 struct mlx5_ifc_modify_cong_status_out_bits {
6973         u8         status[0x8];
6974         u8         reserved_at_8[0x18];
6975
6976         u8         syndrome[0x20];
6977
6978         u8         reserved_at_40[0x40];
6979 };
6980
6981 struct mlx5_ifc_modify_cong_status_in_bits {
6982         u8         opcode[0x10];
6983         u8         reserved_at_10[0x10];
6984
6985         u8         reserved_at_20[0x10];
6986         u8         op_mod[0x10];
6987
6988         u8         reserved_at_40[0x18];
6989         u8         priority[0x4];
6990         u8         cong_protocol[0x4];
6991
6992         u8         enable[0x1];
6993         u8         tag_enable[0x1];
6994         u8         reserved_at_62[0x1e];
6995 };
6996
6997 struct mlx5_ifc_modify_cong_params_out_bits {
6998         u8         status[0x8];
6999         u8         reserved_at_8[0x18];
7000
7001         u8         syndrome[0x20];
7002
7003         u8         reserved_at_40[0x40];
7004 };
7005
7006 struct mlx5_ifc_modify_cong_params_in_bits {
7007         u8         opcode[0x10];
7008         u8         reserved_at_10[0x10];
7009
7010         u8         reserved_at_20[0x10];
7011         u8         op_mod[0x10];
7012
7013         u8         reserved_at_40[0x1c];
7014         u8         cong_protocol[0x4];
7015
7016         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7017
7018         u8         reserved_at_80[0x80];
7019
7020         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7021 };
7022
7023 struct mlx5_ifc_manage_pages_out_bits {
7024         u8         status[0x8];
7025         u8         reserved_at_8[0x18];
7026
7027         u8         syndrome[0x20];
7028
7029         u8         output_num_entries[0x20];
7030
7031         u8         reserved_at_60[0x20];
7032
7033         u8         pas[][0x40];
7034 };
7035
7036 enum {
7037         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7038         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7039         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7040 };
7041
7042 struct mlx5_ifc_manage_pages_in_bits {
7043         u8         opcode[0x10];
7044         u8         reserved_at_10[0x10];
7045
7046         u8         reserved_at_20[0x10];
7047         u8         op_mod[0x10];
7048
7049         u8         embedded_cpu_function[0x1];
7050         u8         reserved_at_41[0xf];
7051         u8         function_id[0x10];
7052
7053         u8         input_num_entries[0x20];
7054
7055         u8         pas[][0x40];
7056 };
7057
7058 struct mlx5_ifc_mad_ifc_out_bits {
7059         u8         status[0x8];
7060         u8         reserved_at_8[0x18];
7061
7062         u8         syndrome[0x20];
7063
7064         u8         reserved_at_40[0x40];
7065
7066         u8         response_mad_packet[256][0x8];
7067 };
7068
7069 struct mlx5_ifc_mad_ifc_in_bits {
7070         u8         opcode[0x10];
7071         u8         reserved_at_10[0x10];
7072
7073         u8         reserved_at_20[0x10];
7074         u8         op_mod[0x10];
7075
7076         u8         remote_lid[0x10];
7077         u8         reserved_at_50[0x8];
7078         u8         port[0x8];
7079
7080         u8         reserved_at_60[0x20];
7081
7082         u8         mad[256][0x8];
7083 };
7084
7085 struct mlx5_ifc_init_hca_out_bits {
7086         u8         status[0x8];
7087         u8         reserved_at_8[0x18];
7088
7089         u8         syndrome[0x20];
7090
7091         u8         reserved_at_40[0x40];
7092 };
7093
7094 struct mlx5_ifc_init_hca_in_bits {
7095         u8         opcode[0x10];
7096         u8         reserved_at_10[0x10];
7097
7098         u8         reserved_at_20[0x10];
7099         u8         op_mod[0x10];
7100
7101         u8         reserved_at_40[0x40];
7102         u8         sw_owner_id[4][0x20];
7103 };
7104
7105 struct mlx5_ifc_init2rtr_qp_out_bits {
7106         u8         status[0x8];
7107         u8         reserved_at_8[0x18];
7108
7109         u8         syndrome[0x20];
7110
7111         u8         reserved_at_40[0x20];
7112         u8         ece[0x20];
7113 };
7114
7115 struct mlx5_ifc_init2rtr_qp_in_bits {
7116         u8         opcode[0x10];
7117         u8         uid[0x10];
7118
7119         u8         reserved_at_20[0x10];
7120         u8         op_mod[0x10];
7121
7122         u8         reserved_at_40[0x8];
7123         u8         qpn[0x18];
7124
7125         u8         reserved_at_60[0x20];
7126
7127         u8         opt_param_mask[0x20];
7128
7129         u8         ece[0x20];
7130
7131         struct mlx5_ifc_qpc_bits qpc;
7132
7133         u8         reserved_at_800[0x80];
7134 };
7135
7136 struct mlx5_ifc_init2init_qp_out_bits {
7137         u8         status[0x8];
7138         u8         reserved_at_8[0x18];
7139
7140         u8         syndrome[0x20];
7141
7142         u8         reserved_at_40[0x20];
7143         u8         ece[0x20];
7144 };
7145
7146 struct mlx5_ifc_init2init_qp_in_bits {
7147         u8         opcode[0x10];
7148         u8         uid[0x10];
7149
7150         u8         reserved_at_20[0x10];
7151         u8         op_mod[0x10];
7152
7153         u8         reserved_at_40[0x8];
7154         u8         qpn[0x18];
7155
7156         u8         reserved_at_60[0x20];
7157
7158         u8         opt_param_mask[0x20];
7159
7160         u8         ece[0x20];
7161
7162         struct mlx5_ifc_qpc_bits qpc;
7163
7164         u8         reserved_at_800[0x80];
7165 };
7166
7167 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7168         u8         status[0x8];
7169         u8         reserved_at_8[0x18];
7170
7171         u8         syndrome[0x20];
7172
7173         u8         reserved_at_40[0x40];
7174
7175         u8         packet_headers_log[128][0x8];
7176
7177         u8         packet_syndrome[64][0x8];
7178 };
7179
7180 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7181         u8         opcode[0x10];
7182         u8         reserved_at_10[0x10];
7183
7184         u8         reserved_at_20[0x10];
7185         u8         op_mod[0x10];
7186
7187         u8         reserved_at_40[0x40];
7188 };
7189
7190 struct mlx5_ifc_gen_eqe_in_bits {
7191         u8         opcode[0x10];
7192         u8         reserved_at_10[0x10];
7193
7194         u8         reserved_at_20[0x10];
7195         u8         op_mod[0x10];
7196
7197         u8         reserved_at_40[0x18];
7198         u8         eq_number[0x8];
7199
7200         u8         reserved_at_60[0x20];
7201
7202         u8         eqe[64][0x8];
7203 };
7204
7205 struct mlx5_ifc_gen_eq_out_bits {
7206         u8         status[0x8];
7207         u8         reserved_at_8[0x18];
7208
7209         u8         syndrome[0x20];
7210
7211         u8         reserved_at_40[0x40];
7212 };
7213
7214 struct mlx5_ifc_enable_hca_out_bits {
7215         u8         status[0x8];
7216         u8         reserved_at_8[0x18];
7217
7218         u8         syndrome[0x20];
7219
7220         u8         reserved_at_40[0x20];
7221 };
7222
7223 struct mlx5_ifc_enable_hca_in_bits {
7224         u8         opcode[0x10];
7225         u8         reserved_at_10[0x10];
7226
7227         u8         reserved_at_20[0x10];
7228         u8         op_mod[0x10];
7229
7230         u8         embedded_cpu_function[0x1];
7231         u8         reserved_at_41[0xf];
7232         u8         function_id[0x10];
7233
7234         u8         reserved_at_60[0x20];
7235 };
7236
7237 struct mlx5_ifc_drain_dct_out_bits {
7238         u8         status[0x8];
7239         u8         reserved_at_8[0x18];
7240
7241         u8         syndrome[0x20];
7242
7243         u8         reserved_at_40[0x40];
7244 };
7245
7246 struct mlx5_ifc_drain_dct_in_bits {
7247         u8         opcode[0x10];
7248         u8         uid[0x10];
7249
7250         u8         reserved_at_20[0x10];
7251         u8         op_mod[0x10];
7252
7253         u8         reserved_at_40[0x8];
7254         u8         dctn[0x18];
7255
7256         u8         reserved_at_60[0x20];
7257 };
7258
7259 struct mlx5_ifc_disable_hca_out_bits {
7260         u8         status[0x8];
7261         u8         reserved_at_8[0x18];
7262
7263         u8         syndrome[0x20];
7264
7265         u8         reserved_at_40[0x20];
7266 };
7267
7268 struct mlx5_ifc_disable_hca_in_bits {
7269         u8         opcode[0x10];
7270         u8         reserved_at_10[0x10];
7271
7272         u8         reserved_at_20[0x10];
7273         u8         op_mod[0x10];
7274
7275         u8         embedded_cpu_function[0x1];
7276         u8         reserved_at_41[0xf];
7277         u8         function_id[0x10];
7278
7279         u8         reserved_at_60[0x20];
7280 };
7281
7282 struct mlx5_ifc_detach_from_mcg_out_bits {
7283         u8         status[0x8];
7284         u8         reserved_at_8[0x18];
7285
7286         u8         syndrome[0x20];
7287
7288         u8         reserved_at_40[0x40];
7289 };
7290
7291 struct mlx5_ifc_detach_from_mcg_in_bits {
7292         u8         opcode[0x10];
7293         u8         uid[0x10];
7294
7295         u8         reserved_at_20[0x10];
7296         u8         op_mod[0x10];
7297
7298         u8         reserved_at_40[0x8];
7299         u8         qpn[0x18];
7300
7301         u8         reserved_at_60[0x20];
7302
7303         u8         multicast_gid[16][0x8];
7304 };
7305
7306 struct mlx5_ifc_destroy_xrq_out_bits {
7307         u8         status[0x8];
7308         u8         reserved_at_8[0x18];
7309
7310         u8         syndrome[0x20];
7311
7312         u8         reserved_at_40[0x40];
7313 };
7314
7315 struct mlx5_ifc_destroy_xrq_in_bits {
7316         u8         opcode[0x10];
7317         u8         uid[0x10];
7318
7319         u8         reserved_at_20[0x10];
7320         u8         op_mod[0x10];
7321
7322         u8         reserved_at_40[0x8];
7323         u8         xrqn[0x18];
7324
7325         u8         reserved_at_60[0x20];
7326 };
7327
7328 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7329         u8         status[0x8];
7330         u8         reserved_at_8[0x18];
7331
7332         u8         syndrome[0x20];
7333
7334         u8         reserved_at_40[0x40];
7335 };
7336
7337 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7338         u8         opcode[0x10];
7339         u8         uid[0x10];
7340
7341         u8         reserved_at_20[0x10];
7342         u8         op_mod[0x10];
7343
7344         u8         reserved_at_40[0x8];
7345         u8         xrc_srqn[0x18];
7346
7347         u8         reserved_at_60[0x20];
7348 };
7349
7350 struct mlx5_ifc_destroy_tis_out_bits {
7351         u8         status[0x8];
7352         u8         reserved_at_8[0x18];
7353
7354         u8         syndrome[0x20];
7355
7356         u8         reserved_at_40[0x40];
7357 };
7358
7359 struct mlx5_ifc_destroy_tis_in_bits {
7360         u8         opcode[0x10];
7361         u8         uid[0x10];
7362
7363         u8         reserved_at_20[0x10];
7364         u8         op_mod[0x10];
7365
7366         u8         reserved_at_40[0x8];
7367         u8         tisn[0x18];
7368
7369         u8         reserved_at_60[0x20];
7370 };
7371
7372 struct mlx5_ifc_destroy_tir_out_bits {
7373         u8         status[0x8];
7374         u8         reserved_at_8[0x18];
7375
7376         u8         syndrome[0x20];
7377
7378         u8         reserved_at_40[0x40];
7379 };
7380
7381 struct mlx5_ifc_destroy_tir_in_bits {
7382         u8         opcode[0x10];
7383         u8         uid[0x10];
7384
7385         u8         reserved_at_20[0x10];
7386         u8         op_mod[0x10];
7387
7388         u8         reserved_at_40[0x8];
7389         u8         tirn[0x18];
7390
7391         u8         reserved_at_60[0x20];
7392 };
7393
7394 struct mlx5_ifc_destroy_srq_out_bits {
7395         u8         status[0x8];
7396         u8         reserved_at_8[0x18];
7397
7398         u8         syndrome[0x20];
7399
7400         u8         reserved_at_40[0x40];
7401 };
7402
7403 struct mlx5_ifc_destroy_srq_in_bits {
7404         u8         opcode[0x10];
7405         u8         uid[0x10];
7406
7407         u8         reserved_at_20[0x10];
7408         u8         op_mod[0x10];
7409
7410         u8         reserved_at_40[0x8];
7411         u8         srqn[0x18];
7412
7413         u8         reserved_at_60[0x20];
7414 };
7415
7416 struct mlx5_ifc_destroy_sq_out_bits {
7417         u8         status[0x8];
7418         u8         reserved_at_8[0x18];
7419
7420         u8         syndrome[0x20];
7421
7422         u8         reserved_at_40[0x40];
7423 };
7424
7425 struct mlx5_ifc_destroy_sq_in_bits {
7426         u8         opcode[0x10];
7427         u8         uid[0x10];
7428
7429         u8         reserved_at_20[0x10];
7430         u8         op_mod[0x10];
7431
7432         u8         reserved_at_40[0x8];
7433         u8         sqn[0x18];
7434
7435         u8         reserved_at_60[0x20];
7436 };
7437
7438 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7439         u8         status[0x8];
7440         u8         reserved_at_8[0x18];
7441
7442         u8         syndrome[0x20];
7443
7444         u8         reserved_at_40[0x1c0];
7445 };
7446
7447 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7448         u8         opcode[0x10];
7449         u8         reserved_at_10[0x10];
7450
7451         u8         reserved_at_20[0x10];
7452         u8         op_mod[0x10];
7453
7454         u8         scheduling_hierarchy[0x8];
7455         u8         reserved_at_48[0x18];
7456
7457         u8         scheduling_element_id[0x20];
7458
7459         u8         reserved_at_80[0x180];
7460 };
7461
7462 struct mlx5_ifc_destroy_rqt_out_bits {
7463         u8         status[0x8];
7464         u8         reserved_at_8[0x18];
7465
7466         u8         syndrome[0x20];
7467
7468         u8         reserved_at_40[0x40];
7469 };
7470
7471 struct mlx5_ifc_destroy_rqt_in_bits {
7472         u8         opcode[0x10];
7473         u8         uid[0x10];
7474
7475         u8         reserved_at_20[0x10];
7476         u8         op_mod[0x10];
7477
7478         u8         reserved_at_40[0x8];
7479         u8         rqtn[0x18];
7480
7481         u8         reserved_at_60[0x20];
7482 };
7483
7484 struct mlx5_ifc_destroy_rq_out_bits {
7485         u8         status[0x8];
7486         u8         reserved_at_8[0x18];
7487
7488         u8         syndrome[0x20];
7489
7490         u8         reserved_at_40[0x40];
7491 };
7492
7493 struct mlx5_ifc_destroy_rq_in_bits {
7494         u8         opcode[0x10];
7495         u8         uid[0x10];
7496
7497         u8         reserved_at_20[0x10];
7498         u8         op_mod[0x10];
7499
7500         u8         reserved_at_40[0x8];
7501         u8         rqn[0x18];
7502
7503         u8         reserved_at_60[0x20];
7504 };
7505
7506 struct mlx5_ifc_set_delay_drop_params_in_bits {
7507         u8         opcode[0x10];
7508         u8         reserved_at_10[0x10];
7509
7510         u8         reserved_at_20[0x10];
7511         u8         op_mod[0x10];
7512
7513         u8         reserved_at_40[0x20];
7514
7515         u8         reserved_at_60[0x10];
7516         u8         delay_drop_timeout[0x10];
7517 };
7518
7519 struct mlx5_ifc_set_delay_drop_params_out_bits {
7520         u8         status[0x8];
7521         u8         reserved_at_8[0x18];
7522
7523         u8         syndrome[0x20];
7524
7525         u8         reserved_at_40[0x40];
7526 };
7527
7528 struct mlx5_ifc_destroy_rmp_out_bits {
7529         u8         status[0x8];
7530         u8         reserved_at_8[0x18];
7531
7532         u8         syndrome[0x20];
7533
7534         u8         reserved_at_40[0x40];
7535 };
7536
7537 struct mlx5_ifc_destroy_rmp_in_bits {
7538         u8         opcode[0x10];
7539         u8         uid[0x10];
7540
7541         u8         reserved_at_20[0x10];
7542         u8         op_mod[0x10];
7543
7544         u8         reserved_at_40[0x8];
7545         u8         rmpn[0x18];
7546
7547         u8         reserved_at_60[0x20];
7548 };
7549
7550 struct mlx5_ifc_destroy_qp_out_bits {
7551         u8         status[0x8];
7552         u8         reserved_at_8[0x18];
7553
7554         u8         syndrome[0x20];
7555
7556         u8         reserved_at_40[0x40];
7557 };
7558
7559 struct mlx5_ifc_destroy_qp_in_bits {
7560         u8         opcode[0x10];
7561         u8         uid[0x10];
7562
7563         u8         reserved_at_20[0x10];
7564         u8         op_mod[0x10];
7565
7566         u8         reserved_at_40[0x8];
7567         u8         qpn[0x18];
7568
7569         u8         reserved_at_60[0x20];
7570 };
7571
7572 struct mlx5_ifc_destroy_psv_out_bits {
7573         u8         status[0x8];
7574         u8         reserved_at_8[0x18];
7575
7576         u8         syndrome[0x20];
7577
7578         u8         reserved_at_40[0x40];
7579 };
7580
7581 struct mlx5_ifc_destroy_psv_in_bits {
7582         u8         opcode[0x10];
7583         u8         reserved_at_10[0x10];
7584
7585         u8         reserved_at_20[0x10];
7586         u8         op_mod[0x10];
7587
7588         u8         reserved_at_40[0x8];
7589         u8         psvn[0x18];
7590
7591         u8         reserved_at_60[0x20];
7592 };
7593
7594 struct mlx5_ifc_destroy_mkey_out_bits {
7595         u8         status[0x8];
7596         u8         reserved_at_8[0x18];
7597
7598         u8         syndrome[0x20];
7599
7600         u8         reserved_at_40[0x40];
7601 };
7602
7603 struct mlx5_ifc_destroy_mkey_in_bits {
7604         u8         opcode[0x10];
7605         u8         uid[0x10];
7606
7607         u8         reserved_at_20[0x10];
7608         u8         op_mod[0x10];
7609
7610         u8         reserved_at_40[0x8];
7611         u8         mkey_index[0x18];
7612
7613         u8         reserved_at_60[0x20];
7614 };
7615
7616 struct mlx5_ifc_destroy_flow_table_out_bits {
7617         u8         status[0x8];
7618         u8         reserved_at_8[0x18];
7619
7620         u8         syndrome[0x20];
7621
7622         u8         reserved_at_40[0x40];
7623 };
7624
7625 struct mlx5_ifc_destroy_flow_table_in_bits {
7626         u8         opcode[0x10];
7627         u8         reserved_at_10[0x10];
7628
7629         u8         reserved_at_20[0x10];
7630         u8         op_mod[0x10];
7631
7632         u8         other_vport[0x1];
7633         u8         reserved_at_41[0xf];
7634         u8         vport_number[0x10];
7635
7636         u8         reserved_at_60[0x20];
7637
7638         u8         table_type[0x8];
7639         u8         reserved_at_88[0x18];
7640
7641         u8         reserved_at_a0[0x8];
7642         u8         table_id[0x18];
7643
7644         u8         reserved_at_c0[0x140];
7645 };
7646
7647 struct mlx5_ifc_destroy_flow_group_out_bits {
7648         u8         status[0x8];
7649         u8         reserved_at_8[0x18];
7650
7651         u8         syndrome[0x20];
7652
7653         u8         reserved_at_40[0x40];
7654 };
7655
7656 struct mlx5_ifc_destroy_flow_group_in_bits {
7657         u8         opcode[0x10];
7658         u8         reserved_at_10[0x10];
7659
7660         u8         reserved_at_20[0x10];
7661         u8         op_mod[0x10];
7662
7663         u8         other_vport[0x1];
7664         u8         reserved_at_41[0xf];
7665         u8         vport_number[0x10];
7666
7667         u8         reserved_at_60[0x20];
7668
7669         u8         table_type[0x8];
7670         u8         reserved_at_88[0x18];
7671
7672         u8         reserved_at_a0[0x8];
7673         u8         table_id[0x18];
7674
7675         u8         group_id[0x20];
7676
7677         u8         reserved_at_e0[0x120];
7678 };
7679
7680 struct mlx5_ifc_destroy_eq_out_bits {
7681         u8         status[0x8];
7682         u8         reserved_at_8[0x18];
7683
7684         u8         syndrome[0x20];
7685
7686         u8         reserved_at_40[0x40];
7687 };
7688
7689 struct mlx5_ifc_destroy_eq_in_bits {
7690         u8         opcode[0x10];
7691         u8         reserved_at_10[0x10];
7692
7693         u8         reserved_at_20[0x10];
7694         u8         op_mod[0x10];
7695
7696         u8         reserved_at_40[0x18];
7697         u8         eq_number[0x8];
7698
7699         u8         reserved_at_60[0x20];
7700 };
7701
7702 struct mlx5_ifc_destroy_dct_out_bits {
7703         u8         status[0x8];
7704         u8         reserved_at_8[0x18];
7705
7706         u8         syndrome[0x20];
7707
7708         u8         reserved_at_40[0x40];
7709 };
7710
7711 struct mlx5_ifc_destroy_dct_in_bits {
7712         u8         opcode[0x10];
7713         u8         uid[0x10];
7714
7715         u8         reserved_at_20[0x10];
7716         u8         op_mod[0x10];
7717
7718         u8         reserved_at_40[0x8];
7719         u8         dctn[0x18];
7720
7721         u8         reserved_at_60[0x20];
7722 };
7723
7724 struct mlx5_ifc_destroy_cq_out_bits {
7725         u8         status[0x8];
7726         u8         reserved_at_8[0x18];
7727
7728         u8         syndrome[0x20];
7729
7730         u8         reserved_at_40[0x40];
7731 };
7732
7733 struct mlx5_ifc_destroy_cq_in_bits {
7734         u8         opcode[0x10];
7735         u8         uid[0x10];
7736
7737         u8         reserved_at_20[0x10];
7738         u8         op_mod[0x10];
7739
7740         u8         reserved_at_40[0x8];
7741         u8         cqn[0x18];
7742
7743         u8         reserved_at_60[0x20];
7744 };
7745
7746 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7747         u8         status[0x8];
7748         u8         reserved_at_8[0x18];
7749
7750         u8         syndrome[0x20];
7751
7752         u8         reserved_at_40[0x40];
7753 };
7754
7755 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7756         u8         opcode[0x10];
7757         u8         reserved_at_10[0x10];
7758
7759         u8         reserved_at_20[0x10];
7760         u8         op_mod[0x10];
7761
7762         u8         reserved_at_40[0x20];
7763
7764         u8         reserved_at_60[0x10];
7765         u8         vxlan_udp_port[0x10];
7766 };
7767
7768 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7769         u8         status[0x8];
7770         u8         reserved_at_8[0x18];
7771
7772         u8         syndrome[0x20];
7773
7774         u8         reserved_at_40[0x40];
7775 };
7776
7777 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7778         u8         opcode[0x10];
7779         u8         reserved_at_10[0x10];
7780
7781         u8         reserved_at_20[0x10];
7782         u8         op_mod[0x10];
7783
7784         u8         reserved_at_40[0x60];
7785
7786         u8         reserved_at_a0[0x8];
7787         u8         table_index[0x18];
7788
7789         u8         reserved_at_c0[0x140];
7790 };
7791
7792 struct mlx5_ifc_delete_fte_out_bits {
7793         u8         status[0x8];
7794         u8         reserved_at_8[0x18];
7795
7796         u8         syndrome[0x20];
7797
7798         u8         reserved_at_40[0x40];
7799 };
7800
7801 struct mlx5_ifc_delete_fte_in_bits {
7802         u8         opcode[0x10];
7803         u8         reserved_at_10[0x10];
7804
7805         u8         reserved_at_20[0x10];
7806         u8         op_mod[0x10];
7807
7808         u8         other_vport[0x1];
7809         u8         reserved_at_41[0xf];
7810         u8         vport_number[0x10];
7811
7812         u8         reserved_at_60[0x20];
7813
7814         u8         table_type[0x8];
7815         u8         reserved_at_88[0x18];
7816
7817         u8         reserved_at_a0[0x8];
7818         u8         table_id[0x18];
7819
7820         u8         reserved_at_c0[0x40];
7821
7822         u8         flow_index[0x20];
7823
7824         u8         reserved_at_120[0xe0];
7825 };
7826
7827 struct mlx5_ifc_dealloc_xrcd_out_bits {
7828         u8         status[0x8];
7829         u8         reserved_at_8[0x18];
7830
7831         u8         syndrome[0x20];
7832
7833         u8         reserved_at_40[0x40];
7834 };
7835
7836 struct mlx5_ifc_dealloc_xrcd_in_bits {
7837         u8         opcode[0x10];
7838         u8         uid[0x10];
7839
7840         u8         reserved_at_20[0x10];
7841         u8         op_mod[0x10];
7842
7843         u8         reserved_at_40[0x8];
7844         u8         xrcd[0x18];
7845
7846         u8         reserved_at_60[0x20];
7847 };
7848
7849 struct mlx5_ifc_dealloc_uar_out_bits {
7850         u8         status[0x8];
7851         u8         reserved_at_8[0x18];
7852
7853         u8         syndrome[0x20];
7854
7855         u8         reserved_at_40[0x40];
7856 };
7857
7858 struct mlx5_ifc_dealloc_uar_in_bits {
7859         u8         opcode[0x10];
7860         u8         reserved_at_10[0x10];
7861
7862         u8         reserved_at_20[0x10];
7863         u8         op_mod[0x10];
7864
7865         u8         reserved_at_40[0x8];
7866         u8         uar[0x18];
7867
7868         u8         reserved_at_60[0x20];
7869 };
7870
7871 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7872         u8         status[0x8];
7873         u8         reserved_at_8[0x18];
7874
7875         u8         syndrome[0x20];
7876
7877         u8         reserved_at_40[0x40];
7878 };
7879
7880 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7881         u8         opcode[0x10];
7882         u8         uid[0x10];
7883
7884         u8         reserved_at_20[0x10];
7885         u8         op_mod[0x10];
7886
7887         u8         reserved_at_40[0x8];
7888         u8         transport_domain[0x18];
7889
7890         u8         reserved_at_60[0x20];
7891 };
7892
7893 struct mlx5_ifc_dealloc_q_counter_out_bits {
7894         u8         status[0x8];
7895         u8         reserved_at_8[0x18];
7896
7897         u8         syndrome[0x20];
7898
7899         u8         reserved_at_40[0x40];
7900 };
7901
7902 struct mlx5_ifc_dealloc_q_counter_in_bits {
7903         u8         opcode[0x10];
7904         u8         reserved_at_10[0x10];
7905
7906         u8         reserved_at_20[0x10];
7907         u8         op_mod[0x10];
7908
7909         u8         reserved_at_40[0x18];
7910         u8         counter_set_id[0x8];
7911
7912         u8         reserved_at_60[0x20];
7913 };
7914
7915 struct mlx5_ifc_dealloc_pd_out_bits {
7916         u8         status[0x8];
7917         u8         reserved_at_8[0x18];
7918
7919         u8         syndrome[0x20];
7920
7921         u8         reserved_at_40[0x40];
7922 };
7923
7924 struct mlx5_ifc_dealloc_pd_in_bits {
7925         u8         opcode[0x10];
7926         u8         uid[0x10];
7927
7928         u8         reserved_at_20[0x10];
7929         u8         op_mod[0x10];
7930
7931         u8         reserved_at_40[0x8];
7932         u8         pd[0x18];
7933
7934         u8         reserved_at_60[0x20];
7935 };
7936
7937 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7938         u8         status[0x8];
7939         u8         reserved_at_8[0x18];
7940
7941         u8         syndrome[0x20];
7942
7943         u8         reserved_at_40[0x40];
7944 };
7945
7946 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7947         u8         opcode[0x10];
7948         u8         reserved_at_10[0x10];
7949
7950         u8         reserved_at_20[0x10];
7951         u8         op_mod[0x10];
7952
7953         u8         flow_counter_id[0x20];
7954
7955         u8         reserved_at_60[0x20];
7956 };
7957
7958 struct mlx5_ifc_create_xrq_out_bits {
7959         u8         status[0x8];
7960         u8         reserved_at_8[0x18];
7961
7962         u8         syndrome[0x20];
7963
7964         u8         reserved_at_40[0x8];
7965         u8         xrqn[0x18];
7966
7967         u8         reserved_at_60[0x20];
7968 };
7969
7970 struct mlx5_ifc_create_xrq_in_bits {
7971         u8         opcode[0x10];
7972         u8         uid[0x10];
7973
7974         u8         reserved_at_20[0x10];
7975         u8         op_mod[0x10];
7976
7977         u8         reserved_at_40[0x40];
7978
7979         struct mlx5_ifc_xrqc_bits xrq_context;
7980 };
7981
7982 struct mlx5_ifc_create_xrc_srq_out_bits {
7983         u8         status[0x8];
7984         u8         reserved_at_8[0x18];
7985
7986         u8         syndrome[0x20];
7987
7988         u8         reserved_at_40[0x8];
7989         u8         xrc_srqn[0x18];
7990
7991         u8         reserved_at_60[0x20];
7992 };
7993
7994 struct mlx5_ifc_create_xrc_srq_in_bits {
7995         u8         opcode[0x10];
7996         u8         uid[0x10];
7997
7998         u8         reserved_at_20[0x10];
7999         u8         op_mod[0x10];
8000
8001         u8         reserved_at_40[0x40];
8002
8003         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8004
8005         u8         reserved_at_280[0x60];
8006
8007         u8         xrc_srq_umem_valid[0x1];
8008         u8         reserved_at_2e1[0x1f];
8009
8010         u8         reserved_at_300[0x580];
8011
8012         u8         pas[][0x40];
8013 };
8014
8015 struct mlx5_ifc_create_tis_out_bits {
8016         u8         status[0x8];
8017         u8         reserved_at_8[0x18];
8018
8019         u8         syndrome[0x20];
8020
8021         u8         reserved_at_40[0x8];
8022         u8         tisn[0x18];
8023
8024         u8         reserved_at_60[0x20];
8025 };
8026
8027 struct mlx5_ifc_create_tis_in_bits {
8028         u8         opcode[0x10];
8029         u8         uid[0x10];
8030
8031         u8         reserved_at_20[0x10];
8032         u8         op_mod[0x10];
8033
8034         u8         reserved_at_40[0xc0];
8035
8036         struct mlx5_ifc_tisc_bits ctx;
8037 };
8038
8039 struct mlx5_ifc_create_tir_out_bits {
8040         u8         status[0x8];
8041         u8         icm_address_63_40[0x18];
8042
8043         u8         syndrome[0x20];
8044
8045         u8         icm_address_39_32[0x8];
8046         u8         tirn[0x18];
8047
8048         u8         icm_address_31_0[0x20];
8049 };
8050
8051 struct mlx5_ifc_create_tir_in_bits {
8052         u8         opcode[0x10];
8053         u8         uid[0x10];
8054
8055         u8         reserved_at_20[0x10];
8056         u8         op_mod[0x10];
8057
8058         u8         reserved_at_40[0xc0];
8059
8060         struct mlx5_ifc_tirc_bits ctx;
8061 };
8062
8063 struct mlx5_ifc_create_srq_out_bits {
8064         u8         status[0x8];
8065         u8         reserved_at_8[0x18];
8066
8067         u8         syndrome[0x20];
8068
8069         u8         reserved_at_40[0x8];
8070         u8         srqn[0x18];
8071
8072         u8         reserved_at_60[0x20];
8073 };
8074
8075 struct mlx5_ifc_create_srq_in_bits {
8076         u8         opcode[0x10];
8077         u8         uid[0x10];
8078
8079         u8         reserved_at_20[0x10];
8080         u8         op_mod[0x10];
8081
8082         u8         reserved_at_40[0x40];
8083
8084         struct mlx5_ifc_srqc_bits srq_context_entry;
8085
8086         u8         reserved_at_280[0x600];
8087
8088         u8         pas[][0x40];
8089 };
8090
8091 struct mlx5_ifc_create_sq_out_bits {
8092         u8         status[0x8];
8093         u8         reserved_at_8[0x18];
8094
8095         u8         syndrome[0x20];
8096
8097         u8         reserved_at_40[0x8];
8098         u8         sqn[0x18];
8099
8100         u8         reserved_at_60[0x20];
8101 };
8102
8103 struct mlx5_ifc_create_sq_in_bits {
8104         u8         opcode[0x10];
8105         u8         uid[0x10];
8106
8107         u8         reserved_at_20[0x10];
8108         u8         op_mod[0x10];
8109
8110         u8         reserved_at_40[0xc0];
8111
8112         struct mlx5_ifc_sqc_bits ctx;
8113 };
8114
8115 struct mlx5_ifc_create_scheduling_element_out_bits {
8116         u8         status[0x8];
8117         u8         reserved_at_8[0x18];
8118
8119         u8         syndrome[0x20];
8120
8121         u8         reserved_at_40[0x40];
8122
8123         u8         scheduling_element_id[0x20];
8124
8125         u8         reserved_at_a0[0x160];
8126 };
8127
8128 struct mlx5_ifc_create_scheduling_element_in_bits {
8129         u8         opcode[0x10];
8130         u8         reserved_at_10[0x10];
8131
8132         u8         reserved_at_20[0x10];
8133         u8         op_mod[0x10];
8134
8135         u8         scheduling_hierarchy[0x8];
8136         u8         reserved_at_48[0x18];
8137
8138         u8         reserved_at_60[0xa0];
8139
8140         struct mlx5_ifc_scheduling_context_bits scheduling_context;
8141
8142         u8         reserved_at_300[0x100];
8143 };
8144
8145 struct mlx5_ifc_create_rqt_out_bits {
8146         u8         status[0x8];
8147         u8         reserved_at_8[0x18];
8148
8149         u8         syndrome[0x20];
8150
8151         u8         reserved_at_40[0x8];
8152         u8         rqtn[0x18];
8153
8154         u8         reserved_at_60[0x20];
8155 };
8156
8157 struct mlx5_ifc_create_rqt_in_bits {
8158         u8         opcode[0x10];
8159         u8         uid[0x10];
8160
8161         u8         reserved_at_20[0x10];
8162         u8         op_mod[0x10];
8163
8164         u8         reserved_at_40[0xc0];
8165
8166         struct mlx5_ifc_rqtc_bits rqt_context;
8167 };
8168
8169 struct mlx5_ifc_create_rq_out_bits {
8170         u8         status[0x8];
8171         u8         reserved_at_8[0x18];
8172
8173         u8         syndrome[0x20];
8174
8175         u8         reserved_at_40[0x8];
8176         u8         rqn[0x18];
8177
8178         u8         reserved_at_60[0x20];
8179 };
8180
8181 struct mlx5_ifc_create_rq_in_bits {
8182         u8         opcode[0x10];
8183         u8         uid[0x10];
8184
8185         u8         reserved_at_20[0x10];
8186         u8         op_mod[0x10];
8187
8188         u8         reserved_at_40[0xc0];
8189
8190         struct mlx5_ifc_rqc_bits ctx;
8191 };
8192
8193 struct mlx5_ifc_create_rmp_out_bits {
8194         u8         status[0x8];
8195         u8         reserved_at_8[0x18];
8196
8197         u8         syndrome[0x20];
8198
8199         u8         reserved_at_40[0x8];
8200         u8         rmpn[0x18];
8201
8202         u8         reserved_at_60[0x20];
8203 };
8204
8205 struct mlx5_ifc_create_rmp_in_bits {
8206         u8         opcode[0x10];
8207         u8         uid[0x10];
8208
8209         u8         reserved_at_20[0x10];
8210         u8         op_mod[0x10];
8211
8212         u8         reserved_at_40[0xc0];
8213
8214         struct mlx5_ifc_rmpc_bits ctx;
8215 };
8216
8217 struct mlx5_ifc_create_qp_out_bits {
8218         u8         status[0x8];
8219         u8         reserved_at_8[0x18];
8220
8221         u8         syndrome[0x20];
8222
8223         u8         reserved_at_40[0x8];
8224         u8         qpn[0x18];
8225
8226         u8         ece[0x20];
8227 };
8228
8229 struct mlx5_ifc_create_qp_in_bits {
8230         u8         opcode[0x10];
8231         u8         uid[0x10];
8232
8233         u8         reserved_at_20[0x10];
8234         u8         op_mod[0x10];
8235
8236         u8         reserved_at_40[0x8];
8237         u8         input_qpn[0x18];
8238
8239         u8         reserved_at_60[0x20];
8240         u8         opt_param_mask[0x20];
8241
8242         u8         ece[0x20];
8243
8244         struct mlx5_ifc_qpc_bits qpc;
8245
8246         u8         reserved_at_800[0x60];
8247
8248         u8         wq_umem_valid[0x1];
8249         u8         reserved_at_861[0x1f];
8250
8251         u8         pas[][0x40];
8252 };
8253
8254 struct mlx5_ifc_create_psv_out_bits {
8255         u8         status[0x8];
8256         u8         reserved_at_8[0x18];
8257
8258         u8         syndrome[0x20];
8259
8260         u8         reserved_at_40[0x40];
8261
8262         u8         reserved_at_80[0x8];
8263         u8         psv0_index[0x18];
8264
8265         u8         reserved_at_a0[0x8];
8266         u8         psv1_index[0x18];
8267
8268         u8         reserved_at_c0[0x8];
8269         u8         psv2_index[0x18];
8270
8271         u8         reserved_at_e0[0x8];
8272         u8         psv3_index[0x18];
8273 };
8274
8275 struct mlx5_ifc_create_psv_in_bits {
8276         u8         opcode[0x10];
8277         u8         reserved_at_10[0x10];
8278
8279         u8         reserved_at_20[0x10];
8280         u8         op_mod[0x10];
8281
8282         u8         num_psv[0x4];
8283         u8         reserved_at_44[0x4];
8284         u8         pd[0x18];
8285
8286         u8         reserved_at_60[0x20];
8287 };
8288
8289 struct mlx5_ifc_create_mkey_out_bits {
8290         u8         status[0x8];
8291         u8         reserved_at_8[0x18];
8292
8293         u8         syndrome[0x20];
8294
8295         u8         reserved_at_40[0x8];
8296         u8         mkey_index[0x18];
8297
8298         u8         reserved_at_60[0x20];
8299 };
8300
8301 struct mlx5_ifc_create_mkey_in_bits {
8302         u8         opcode[0x10];
8303         u8         uid[0x10];
8304
8305         u8         reserved_at_20[0x10];
8306         u8         op_mod[0x10];
8307
8308         u8         reserved_at_40[0x20];
8309
8310         u8         pg_access[0x1];
8311         u8         mkey_umem_valid[0x1];
8312         u8         reserved_at_62[0x1e];
8313
8314         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8315
8316         u8         reserved_at_280[0x80];
8317
8318         u8         translations_octword_actual_size[0x20];
8319
8320         u8         reserved_at_320[0x560];
8321
8322         u8         klm_pas_mtt[][0x20];
8323 };
8324
8325 enum {
8326         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
8327         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
8328         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
8329         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
8330         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
8331         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
8332         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
8333 };
8334
8335 struct mlx5_ifc_create_flow_table_out_bits {
8336         u8         status[0x8];
8337         u8         icm_address_63_40[0x18];
8338
8339         u8         syndrome[0x20];
8340
8341         u8         icm_address_39_32[0x8];
8342         u8         table_id[0x18];
8343
8344         u8         icm_address_31_0[0x20];
8345 };
8346
8347 struct mlx5_ifc_create_flow_table_in_bits {
8348         u8         opcode[0x10];
8349         u8         reserved_at_10[0x10];
8350
8351         u8         reserved_at_20[0x10];
8352         u8         op_mod[0x10];
8353
8354         u8         other_vport[0x1];
8355         u8         reserved_at_41[0xf];
8356         u8         vport_number[0x10];
8357
8358         u8         reserved_at_60[0x20];
8359
8360         u8         table_type[0x8];
8361         u8         reserved_at_88[0x18];
8362
8363         u8         reserved_at_a0[0x20];
8364
8365         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8366 };
8367
8368 struct mlx5_ifc_create_flow_group_out_bits {
8369         u8         status[0x8];
8370         u8         reserved_at_8[0x18];
8371
8372         u8         syndrome[0x20];
8373
8374         u8         reserved_at_40[0x8];
8375         u8         group_id[0x18];
8376
8377         u8         reserved_at_60[0x20];
8378 };
8379
8380 enum {
8381         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8382         MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8383 };
8384
8385 enum {
8386         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8387         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8388         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8389         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8390 };
8391
8392 struct mlx5_ifc_create_flow_group_in_bits {
8393         u8         opcode[0x10];
8394         u8         reserved_at_10[0x10];
8395
8396         u8         reserved_at_20[0x10];
8397         u8         op_mod[0x10];
8398
8399         u8         other_vport[0x1];
8400         u8         reserved_at_41[0xf];
8401         u8         vport_number[0x10];
8402
8403         u8         reserved_at_60[0x20];
8404
8405         u8         table_type[0x8];
8406         u8         reserved_at_88[0x4];
8407         u8         group_type[0x4];
8408         u8         reserved_at_90[0x10];
8409
8410         u8         reserved_at_a0[0x8];
8411         u8         table_id[0x18];
8412
8413         u8         source_eswitch_owner_vhca_id_valid[0x1];
8414
8415         u8         reserved_at_c1[0x1f];
8416
8417         u8         start_flow_index[0x20];
8418
8419         u8         reserved_at_100[0x20];
8420
8421         u8         end_flow_index[0x20];
8422
8423         u8         reserved_at_140[0x10];
8424         u8         match_definer_id[0x10];
8425
8426         u8         reserved_at_160[0x80];
8427
8428         u8         reserved_at_1e0[0x18];
8429         u8         match_criteria_enable[0x8];
8430
8431         struct mlx5_ifc_fte_match_param_bits match_criteria;
8432
8433         u8         reserved_at_1200[0xe00];
8434 };
8435
8436 struct mlx5_ifc_create_eq_out_bits {
8437         u8         status[0x8];
8438         u8         reserved_at_8[0x18];
8439
8440         u8         syndrome[0x20];
8441
8442         u8         reserved_at_40[0x18];
8443         u8         eq_number[0x8];
8444
8445         u8         reserved_at_60[0x20];
8446 };
8447
8448 struct mlx5_ifc_create_eq_in_bits {
8449         u8         opcode[0x10];
8450         u8         uid[0x10];
8451
8452         u8         reserved_at_20[0x10];
8453         u8         op_mod[0x10];
8454
8455         u8         reserved_at_40[0x40];
8456
8457         struct mlx5_ifc_eqc_bits eq_context_entry;
8458
8459         u8         reserved_at_280[0x40];
8460
8461         u8         event_bitmask[4][0x40];
8462
8463         u8         reserved_at_3c0[0x4c0];
8464
8465         u8         pas[][0x40];
8466 };
8467
8468 struct mlx5_ifc_create_dct_out_bits {
8469         u8         status[0x8];
8470         u8         reserved_at_8[0x18];
8471
8472         u8         syndrome[0x20];
8473
8474         u8         reserved_at_40[0x8];
8475         u8         dctn[0x18];
8476
8477         u8         ece[0x20];
8478 };
8479
8480 struct mlx5_ifc_create_dct_in_bits {
8481         u8         opcode[0x10];
8482         u8         uid[0x10];
8483
8484         u8         reserved_at_20[0x10];
8485         u8         op_mod[0x10];
8486
8487         u8         reserved_at_40[0x40];
8488
8489         struct mlx5_ifc_dctc_bits dct_context_entry;
8490
8491         u8         reserved_at_280[0x180];
8492 };
8493
8494 struct mlx5_ifc_create_cq_out_bits {
8495         u8         status[0x8];
8496         u8         reserved_at_8[0x18];
8497
8498         u8         syndrome[0x20];
8499
8500         u8         reserved_at_40[0x8];
8501         u8         cqn[0x18];
8502
8503         u8         reserved_at_60[0x20];
8504 };
8505
8506 struct mlx5_ifc_create_cq_in_bits {
8507         u8         opcode[0x10];
8508         u8         uid[0x10];
8509
8510         u8         reserved_at_20[0x10];
8511         u8         op_mod[0x10];
8512
8513         u8         reserved_at_40[0x40];
8514
8515         struct mlx5_ifc_cqc_bits cq_context;
8516
8517         u8         reserved_at_280[0x60];
8518
8519         u8         cq_umem_valid[0x1];
8520         u8         reserved_at_2e1[0x59f];
8521
8522         u8         pas[][0x40];
8523 };
8524
8525 struct mlx5_ifc_config_int_moderation_out_bits {
8526         u8         status[0x8];
8527         u8         reserved_at_8[0x18];
8528
8529         u8         syndrome[0x20];
8530
8531         u8         reserved_at_40[0x4];
8532         u8         min_delay[0xc];
8533         u8         int_vector[0x10];
8534
8535         u8         reserved_at_60[0x20];
8536 };
8537
8538 enum {
8539         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8540         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8541 };
8542
8543 struct mlx5_ifc_config_int_moderation_in_bits {
8544         u8         opcode[0x10];
8545         u8         reserved_at_10[0x10];
8546
8547         u8         reserved_at_20[0x10];
8548         u8         op_mod[0x10];
8549
8550         u8         reserved_at_40[0x4];
8551         u8         min_delay[0xc];
8552         u8         int_vector[0x10];
8553
8554         u8         reserved_at_60[0x20];
8555 };
8556
8557 struct mlx5_ifc_attach_to_mcg_out_bits {
8558         u8         status[0x8];
8559         u8         reserved_at_8[0x18];
8560
8561         u8         syndrome[0x20];
8562
8563         u8         reserved_at_40[0x40];
8564 };
8565
8566 struct mlx5_ifc_attach_to_mcg_in_bits {
8567         u8         opcode[0x10];
8568         u8         uid[0x10];
8569
8570         u8         reserved_at_20[0x10];
8571         u8         op_mod[0x10];
8572
8573         u8         reserved_at_40[0x8];
8574         u8         qpn[0x18];
8575
8576         u8         reserved_at_60[0x20];
8577
8578         u8         multicast_gid[16][0x8];
8579 };
8580
8581 struct mlx5_ifc_arm_xrq_out_bits {
8582         u8         status[0x8];
8583         u8         reserved_at_8[0x18];
8584
8585         u8         syndrome[0x20];
8586
8587         u8         reserved_at_40[0x40];
8588 };
8589
8590 struct mlx5_ifc_arm_xrq_in_bits {
8591         u8         opcode[0x10];
8592         u8         reserved_at_10[0x10];
8593
8594         u8         reserved_at_20[0x10];
8595         u8         op_mod[0x10];
8596
8597         u8         reserved_at_40[0x8];
8598         u8         xrqn[0x18];
8599
8600         u8         reserved_at_60[0x10];
8601         u8         lwm[0x10];
8602 };
8603
8604 struct mlx5_ifc_arm_xrc_srq_out_bits {
8605         u8         status[0x8];
8606         u8         reserved_at_8[0x18];
8607
8608         u8         syndrome[0x20];
8609
8610         u8         reserved_at_40[0x40];
8611 };
8612
8613 enum {
8614         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8615 };
8616
8617 struct mlx5_ifc_arm_xrc_srq_in_bits {
8618         u8         opcode[0x10];
8619         u8         uid[0x10];
8620
8621         u8         reserved_at_20[0x10];
8622         u8         op_mod[0x10];
8623
8624         u8         reserved_at_40[0x8];
8625         u8         xrc_srqn[0x18];
8626
8627         u8         reserved_at_60[0x10];
8628         u8         lwm[0x10];
8629 };
8630
8631 struct mlx5_ifc_arm_rq_out_bits {
8632         u8         status[0x8];
8633         u8         reserved_at_8[0x18];
8634
8635         u8         syndrome[0x20];
8636
8637         u8         reserved_at_40[0x40];
8638 };
8639
8640 enum {
8641         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8642         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8643 };
8644
8645 struct mlx5_ifc_arm_rq_in_bits {
8646         u8         opcode[0x10];
8647         u8         uid[0x10];
8648
8649         u8         reserved_at_20[0x10];
8650         u8         op_mod[0x10];
8651
8652         u8         reserved_at_40[0x8];
8653         u8         srq_number[0x18];
8654
8655         u8         reserved_at_60[0x10];
8656         u8         lwm[0x10];
8657 };
8658
8659 struct mlx5_ifc_arm_dct_out_bits {
8660         u8         status[0x8];
8661         u8         reserved_at_8[0x18];
8662
8663         u8         syndrome[0x20];
8664
8665         u8         reserved_at_40[0x40];
8666 };
8667
8668 struct mlx5_ifc_arm_dct_in_bits {
8669         u8         opcode[0x10];
8670         u8         reserved_at_10[0x10];
8671
8672         u8         reserved_at_20[0x10];
8673         u8         op_mod[0x10];
8674
8675         u8         reserved_at_40[0x8];
8676         u8         dct_number[0x18];
8677
8678         u8         reserved_at_60[0x20];
8679 };
8680
8681 struct mlx5_ifc_alloc_xrcd_out_bits {
8682         u8         status[0x8];
8683         u8         reserved_at_8[0x18];
8684
8685         u8         syndrome[0x20];
8686
8687         u8         reserved_at_40[0x8];
8688         u8         xrcd[0x18];
8689
8690         u8         reserved_at_60[0x20];
8691 };
8692
8693 struct mlx5_ifc_alloc_xrcd_in_bits {
8694         u8         opcode[0x10];
8695         u8         uid[0x10];
8696
8697         u8         reserved_at_20[0x10];
8698         u8         op_mod[0x10];
8699
8700         u8         reserved_at_40[0x40];
8701 };
8702
8703 struct mlx5_ifc_alloc_uar_out_bits {
8704         u8         status[0x8];
8705         u8         reserved_at_8[0x18];
8706
8707         u8         syndrome[0x20];
8708
8709         u8         reserved_at_40[0x8];
8710         u8         uar[0x18];
8711
8712         u8         reserved_at_60[0x20];
8713 };
8714
8715 struct mlx5_ifc_alloc_uar_in_bits {
8716         u8         opcode[0x10];
8717         u8         reserved_at_10[0x10];
8718
8719         u8         reserved_at_20[0x10];
8720         u8         op_mod[0x10];
8721
8722         u8         reserved_at_40[0x40];
8723 };
8724
8725 struct mlx5_ifc_alloc_transport_domain_out_bits {
8726         u8         status[0x8];
8727         u8         reserved_at_8[0x18];
8728
8729         u8         syndrome[0x20];
8730
8731         u8         reserved_at_40[0x8];
8732         u8         transport_domain[0x18];
8733
8734         u8         reserved_at_60[0x20];
8735 };
8736
8737 struct mlx5_ifc_alloc_transport_domain_in_bits {
8738         u8         opcode[0x10];
8739         u8         uid[0x10];
8740
8741         u8         reserved_at_20[0x10];
8742         u8         op_mod[0x10];
8743
8744         u8         reserved_at_40[0x40];
8745 };
8746
8747 struct mlx5_ifc_alloc_q_counter_out_bits {
8748         u8         status[0x8];
8749         u8         reserved_at_8[0x18];
8750
8751         u8         syndrome[0x20];
8752
8753         u8         reserved_at_40[0x18];
8754         u8         counter_set_id[0x8];
8755
8756         u8         reserved_at_60[0x20];
8757 };
8758
8759 struct mlx5_ifc_alloc_q_counter_in_bits {
8760         u8         opcode[0x10];
8761         u8         uid[0x10];
8762
8763         u8         reserved_at_20[0x10];
8764         u8         op_mod[0x10];
8765
8766         u8         reserved_at_40[0x40];
8767 };
8768
8769 struct mlx5_ifc_alloc_pd_out_bits {
8770         u8         status[0x8];
8771         u8         reserved_at_8[0x18];
8772
8773         u8         syndrome[0x20];
8774
8775         u8         reserved_at_40[0x8];
8776         u8         pd[0x18];
8777
8778         u8         reserved_at_60[0x20];
8779 };
8780
8781 struct mlx5_ifc_alloc_pd_in_bits {
8782         u8         opcode[0x10];
8783         u8         uid[0x10];
8784
8785         u8         reserved_at_20[0x10];
8786         u8         op_mod[0x10];
8787
8788         u8         reserved_at_40[0x40];
8789 };
8790
8791 struct mlx5_ifc_alloc_flow_counter_out_bits {
8792         u8         status[0x8];
8793         u8         reserved_at_8[0x18];
8794
8795         u8         syndrome[0x20];
8796
8797         u8         flow_counter_id[0x20];
8798
8799         u8         reserved_at_60[0x20];
8800 };
8801
8802 struct mlx5_ifc_alloc_flow_counter_in_bits {
8803         u8         opcode[0x10];
8804         u8         reserved_at_10[0x10];
8805
8806         u8         reserved_at_20[0x10];
8807         u8         op_mod[0x10];
8808
8809         u8         reserved_at_40[0x38];
8810         u8         flow_counter_bulk[0x8];
8811 };
8812
8813 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8814         u8         status[0x8];
8815         u8         reserved_at_8[0x18];
8816
8817         u8         syndrome[0x20];
8818
8819         u8         reserved_at_40[0x40];
8820 };
8821
8822 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8823         u8         opcode[0x10];
8824         u8         reserved_at_10[0x10];
8825
8826         u8         reserved_at_20[0x10];
8827         u8         op_mod[0x10];
8828
8829         u8         reserved_at_40[0x20];
8830
8831         u8         reserved_at_60[0x10];
8832         u8         vxlan_udp_port[0x10];
8833 };
8834
8835 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8836         u8         status[0x8];
8837         u8         reserved_at_8[0x18];
8838
8839         u8         syndrome[0x20];
8840
8841         u8         reserved_at_40[0x40];
8842 };
8843
8844 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8845         u8         rate_limit[0x20];
8846
8847         u8         burst_upper_bound[0x20];
8848
8849         u8         reserved_at_40[0x10];
8850         u8         typical_packet_size[0x10];
8851
8852         u8         reserved_at_60[0x120];
8853 };
8854
8855 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8856         u8         opcode[0x10];
8857         u8         uid[0x10];
8858
8859         u8         reserved_at_20[0x10];
8860         u8         op_mod[0x10];
8861
8862         u8         reserved_at_40[0x10];
8863         u8         rate_limit_index[0x10];
8864
8865         u8         reserved_at_60[0x20];
8866
8867         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8868 };
8869
8870 struct mlx5_ifc_access_register_out_bits {
8871         u8         status[0x8];
8872         u8         reserved_at_8[0x18];
8873
8874         u8         syndrome[0x20];
8875
8876         u8         reserved_at_40[0x40];
8877
8878         u8         register_data[][0x20];
8879 };
8880
8881 enum {
8882         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8883         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8884 };
8885
8886 struct mlx5_ifc_access_register_in_bits {
8887         u8         opcode[0x10];
8888         u8         reserved_at_10[0x10];
8889
8890         u8         reserved_at_20[0x10];
8891         u8         op_mod[0x10];
8892
8893         u8         reserved_at_40[0x10];
8894         u8         register_id[0x10];
8895
8896         u8         argument[0x20];
8897
8898         u8         register_data[][0x20];
8899 };
8900
8901 struct mlx5_ifc_sltp_reg_bits {
8902         u8         status[0x4];
8903         u8         version[0x4];
8904         u8         local_port[0x8];
8905         u8         pnat[0x2];
8906         u8         reserved_at_12[0x2];
8907         u8         lane[0x4];
8908         u8         reserved_at_18[0x8];
8909
8910         u8         reserved_at_20[0x20];
8911
8912         u8         reserved_at_40[0x7];
8913         u8         polarity[0x1];
8914         u8         ob_tap0[0x8];
8915         u8         ob_tap1[0x8];
8916         u8         ob_tap2[0x8];
8917
8918         u8         reserved_at_60[0xc];
8919         u8         ob_preemp_mode[0x4];
8920         u8         ob_reg[0x8];
8921         u8         ob_bias[0x8];
8922
8923         u8         reserved_at_80[0x20];
8924 };
8925
8926 struct mlx5_ifc_slrg_reg_bits {
8927         u8         status[0x4];
8928         u8         version[0x4];
8929         u8         local_port[0x8];
8930         u8         pnat[0x2];
8931         u8         reserved_at_12[0x2];
8932         u8         lane[0x4];
8933         u8         reserved_at_18[0x8];
8934
8935         u8         time_to_link_up[0x10];
8936         u8         reserved_at_30[0xc];
8937         u8         grade_lane_speed[0x4];
8938
8939         u8         grade_version[0x8];
8940         u8         grade[0x18];
8941
8942         u8         reserved_at_60[0x4];
8943         u8         height_grade_type[0x4];
8944         u8         height_grade[0x18];
8945
8946         u8         height_dz[0x10];
8947         u8         height_dv[0x10];
8948
8949         u8         reserved_at_a0[0x10];
8950         u8         height_sigma[0x10];
8951
8952         u8         reserved_at_c0[0x20];
8953
8954         u8         reserved_at_e0[0x4];
8955         u8         phase_grade_type[0x4];
8956         u8         phase_grade[0x18];
8957
8958         u8         reserved_at_100[0x8];
8959         u8         phase_eo_pos[0x8];
8960         u8         reserved_at_110[0x8];
8961         u8         phase_eo_neg[0x8];
8962
8963         u8         ffe_set_tested[0x10];
8964         u8         test_errors_per_lane[0x10];
8965 };
8966
8967 struct mlx5_ifc_pvlc_reg_bits {
8968         u8         reserved_at_0[0x8];
8969         u8         local_port[0x8];
8970         u8         reserved_at_10[0x10];
8971
8972         u8         reserved_at_20[0x1c];
8973         u8         vl_hw_cap[0x4];
8974
8975         u8         reserved_at_40[0x1c];
8976         u8         vl_admin[0x4];
8977
8978         u8         reserved_at_60[0x1c];
8979         u8         vl_operational[0x4];
8980 };
8981
8982 struct mlx5_ifc_pude_reg_bits {
8983         u8         swid[0x8];
8984         u8         local_port[0x8];
8985         u8         reserved_at_10[0x4];
8986         u8         admin_status[0x4];
8987         u8         reserved_at_18[0x4];
8988         u8         oper_status[0x4];
8989
8990         u8         reserved_at_20[0x60];
8991 };
8992
8993 struct mlx5_ifc_ptys_reg_bits {
8994         u8         reserved_at_0[0x1];
8995         u8         an_disable_admin[0x1];
8996         u8         an_disable_cap[0x1];
8997         u8         reserved_at_3[0x5];
8998         u8         local_port[0x8];
8999         u8         reserved_at_10[0xd];
9000         u8         proto_mask[0x3];
9001
9002         u8         an_status[0x4];
9003         u8         reserved_at_24[0xc];
9004         u8         data_rate_oper[0x10];
9005
9006         u8         ext_eth_proto_capability[0x20];
9007
9008         u8         eth_proto_capability[0x20];
9009
9010         u8         ib_link_width_capability[0x10];
9011         u8         ib_proto_capability[0x10];
9012
9013         u8         ext_eth_proto_admin[0x20];
9014
9015         u8         eth_proto_admin[0x20];
9016
9017         u8         ib_link_width_admin[0x10];
9018         u8         ib_proto_admin[0x10];
9019
9020         u8         ext_eth_proto_oper[0x20];
9021
9022         u8         eth_proto_oper[0x20];
9023
9024         u8         ib_link_width_oper[0x10];
9025         u8         ib_proto_oper[0x10];
9026
9027         u8         reserved_at_160[0x1c];
9028         u8         connector_type[0x4];
9029
9030         u8         eth_proto_lp_advertise[0x20];
9031
9032         u8         reserved_at_1a0[0x60];
9033 };
9034
9035 struct mlx5_ifc_mlcr_reg_bits {
9036         u8         reserved_at_0[0x8];
9037         u8         local_port[0x8];
9038         u8         reserved_at_10[0x20];
9039
9040         u8         beacon_duration[0x10];
9041         u8         reserved_at_40[0x10];
9042
9043         u8         beacon_remain[0x10];
9044 };
9045
9046 struct mlx5_ifc_ptas_reg_bits {
9047         u8         reserved_at_0[0x20];
9048
9049         u8         algorithm_options[0x10];
9050         u8         reserved_at_30[0x4];
9051         u8         repetitions_mode[0x4];
9052         u8         num_of_repetitions[0x8];
9053
9054         u8         grade_version[0x8];
9055         u8         height_grade_type[0x4];
9056         u8         phase_grade_type[0x4];
9057         u8         height_grade_weight[0x8];
9058         u8         phase_grade_weight[0x8];
9059
9060         u8         gisim_measure_bits[0x10];
9061         u8         adaptive_tap_measure_bits[0x10];
9062
9063         u8         ber_bath_high_error_threshold[0x10];
9064         u8         ber_bath_mid_error_threshold[0x10];
9065
9066         u8         ber_bath_low_error_threshold[0x10];
9067         u8         one_ratio_high_threshold[0x10];
9068
9069         u8         one_ratio_high_mid_threshold[0x10];
9070         u8         one_ratio_low_mid_threshold[0x10];
9071
9072         u8         one_ratio_low_threshold[0x10];
9073         u8         ndeo_error_threshold[0x10];
9074
9075         u8         mixer_offset_step_size[0x10];
9076         u8         reserved_at_110[0x8];
9077         u8         mix90_phase_for_voltage_bath[0x8];
9078
9079         u8         mixer_offset_start[0x10];
9080         u8         mixer_offset_end[0x10];
9081
9082         u8         reserved_at_140[0x15];
9083         u8         ber_test_time[0xb];
9084 };
9085
9086 struct mlx5_ifc_pspa_reg_bits {
9087         u8         swid[0x8];
9088         u8         local_port[0x8];
9089         u8         sub_port[0x8];
9090         u8         reserved_at_18[0x8];
9091
9092         u8         reserved_at_20[0x20];
9093 };
9094
9095 struct mlx5_ifc_pqdr_reg_bits {
9096         u8         reserved_at_0[0x8];
9097         u8         local_port[0x8];
9098         u8         reserved_at_10[0x5];
9099         u8         prio[0x3];
9100         u8         reserved_at_18[0x6];
9101         u8         mode[0x2];
9102
9103         u8         reserved_at_20[0x20];
9104
9105         u8         reserved_at_40[0x10];
9106         u8         min_threshold[0x10];
9107
9108         u8         reserved_at_60[0x10];
9109         u8         max_threshold[0x10];
9110
9111         u8         reserved_at_80[0x10];
9112         u8         mark_probability_denominator[0x10];
9113
9114         u8         reserved_at_a0[0x60];
9115 };
9116
9117 struct mlx5_ifc_ppsc_reg_bits {
9118         u8         reserved_at_0[0x8];
9119         u8         local_port[0x8];
9120         u8         reserved_at_10[0x10];
9121
9122         u8         reserved_at_20[0x60];
9123
9124         u8         reserved_at_80[0x1c];
9125         u8         wrps_admin[0x4];
9126
9127         u8         reserved_at_a0[0x1c];
9128         u8         wrps_status[0x4];
9129
9130         u8         reserved_at_c0[0x8];
9131         u8         up_threshold[0x8];
9132         u8         reserved_at_d0[0x8];
9133         u8         down_threshold[0x8];
9134
9135         u8         reserved_at_e0[0x20];
9136
9137         u8         reserved_at_100[0x1c];
9138         u8         srps_admin[0x4];
9139
9140         u8         reserved_at_120[0x1c];
9141         u8         srps_status[0x4];
9142
9143         u8         reserved_at_140[0x40];
9144 };
9145
9146 struct mlx5_ifc_pplr_reg_bits {
9147         u8         reserved_at_0[0x8];
9148         u8         local_port[0x8];
9149         u8         reserved_at_10[0x10];
9150
9151         u8         reserved_at_20[0x8];
9152         u8         lb_cap[0x8];
9153         u8         reserved_at_30[0x8];
9154         u8         lb_en[0x8];
9155 };
9156
9157 struct mlx5_ifc_pplm_reg_bits {
9158         u8         reserved_at_0[0x8];
9159         u8         local_port[0x8];
9160         u8         reserved_at_10[0x10];
9161
9162         u8         reserved_at_20[0x20];
9163
9164         u8         port_profile_mode[0x8];
9165         u8         static_port_profile[0x8];
9166         u8         active_port_profile[0x8];
9167         u8         reserved_at_58[0x8];
9168
9169         u8         retransmission_active[0x8];
9170         u8         fec_mode_active[0x18];
9171
9172         u8         rs_fec_correction_bypass_cap[0x4];
9173         u8         reserved_at_84[0x8];
9174         u8         fec_override_cap_56g[0x4];
9175         u8         fec_override_cap_100g[0x4];
9176         u8         fec_override_cap_50g[0x4];
9177         u8         fec_override_cap_25g[0x4];
9178         u8         fec_override_cap_10g_40g[0x4];
9179
9180         u8         rs_fec_correction_bypass_admin[0x4];
9181         u8         reserved_at_a4[0x8];
9182         u8         fec_override_admin_56g[0x4];
9183         u8         fec_override_admin_100g[0x4];
9184         u8         fec_override_admin_50g[0x4];
9185         u8         fec_override_admin_25g[0x4];
9186         u8         fec_override_admin_10g_40g[0x4];
9187
9188         u8         fec_override_cap_400g_8x[0x10];
9189         u8         fec_override_cap_200g_4x[0x10];
9190
9191         u8         fec_override_cap_100g_2x[0x10];
9192         u8         fec_override_cap_50g_1x[0x10];
9193
9194         u8         fec_override_admin_400g_8x[0x10];
9195         u8         fec_override_admin_200g_4x[0x10];
9196
9197         u8         fec_override_admin_100g_2x[0x10];
9198         u8         fec_override_admin_50g_1x[0x10];
9199
9200         u8         reserved_at_140[0x140];
9201 };
9202
9203 struct mlx5_ifc_ppcnt_reg_bits {
9204         u8         swid[0x8];
9205         u8         local_port[0x8];
9206         u8         pnat[0x2];
9207         u8         reserved_at_12[0x8];
9208         u8         grp[0x6];
9209
9210         u8         clr[0x1];
9211         u8         reserved_at_21[0x1c];
9212         u8         prio_tc[0x3];
9213
9214         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9215 };
9216
9217 struct mlx5_ifc_mpein_reg_bits {
9218         u8         reserved_at_0[0x2];
9219         u8         depth[0x6];
9220         u8         pcie_index[0x8];
9221         u8         node[0x8];
9222         u8         reserved_at_18[0x8];
9223
9224         u8         capability_mask[0x20];
9225
9226         u8         reserved_at_40[0x8];
9227         u8         link_width_enabled[0x8];
9228         u8         link_speed_enabled[0x10];
9229
9230         u8         lane0_physical_position[0x8];
9231         u8         link_width_active[0x8];
9232         u8         link_speed_active[0x10];
9233
9234         u8         num_of_pfs[0x10];
9235         u8         num_of_vfs[0x10];
9236
9237         u8         bdf0[0x10];
9238         u8         reserved_at_b0[0x10];
9239
9240         u8         max_read_request_size[0x4];
9241         u8         max_payload_size[0x4];
9242         u8         reserved_at_c8[0x5];
9243         u8         pwr_status[0x3];
9244         u8         port_type[0x4];
9245         u8         reserved_at_d4[0xb];
9246         u8         lane_reversal[0x1];
9247
9248         u8         reserved_at_e0[0x14];
9249         u8         pci_power[0xc];
9250
9251         u8         reserved_at_100[0x20];
9252
9253         u8         device_status[0x10];
9254         u8         port_state[0x8];
9255         u8         reserved_at_138[0x8];
9256
9257         u8         reserved_at_140[0x10];
9258         u8         receiver_detect_result[0x10];
9259
9260         u8         reserved_at_160[0x20];
9261 };
9262
9263 struct mlx5_ifc_mpcnt_reg_bits {
9264         u8         reserved_at_0[0x8];
9265         u8         pcie_index[0x8];
9266         u8         reserved_at_10[0xa];
9267         u8         grp[0x6];
9268
9269         u8         clr[0x1];
9270         u8         reserved_at_21[0x1f];
9271
9272         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9273 };
9274
9275 struct mlx5_ifc_ppad_reg_bits {
9276         u8         reserved_at_0[0x3];
9277         u8         single_mac[0x1];
9278         u8         reserved_at_4[0x4];
9279         u8         local_port[0x8];
9280         u8         mac_47_32[0x10];
9281
9282         u8         mac_31_0[0x20];
9283
9284         u8         reserved_at_40[0x40];
9285 };
9286
9287 struct mlx5_ifc_pmtu_reg_bits {
9288         u8         reserved_at_0[0x8];
9289         u8         local_port[0x8];
9290         u8         reserved_at_10[0x10];
9291
9292         u8         max_mtu[0x10];
9293         u8         reserved_at_30[0x10];
9294
9295         u8         admin_mtu[0x10];
9296         u8         reserved_at_50[0x10];
9297
9298         u8         oper_mtu[0x10];
9299         u8         reserved_at_70[0x10];
9300 };
9301
9302 struct mlx5_ifc_pmpr_reg_bits {
9303         u8         reserved_at_0[0x8];
9304         u8         module[0x8];
9305         u8         reserved_at_10[0x10];
9306
9307         u8         reserved_at_20[0x18];
9308         u8         attenuation_5g[0x8];
9309
9310         u8         reserved_at_40[0x18];
9311         u8         attenuation_7g[0x8];
9312
9313         u8         reserved_at_60[0x18];
9314         u8         attenuation_12g[0x8];
9315 };
9316
9317 struct mlx5_ifc_pmpe_reg_bits {
9318         u8         reserved_at_0[0x8];
9319         u8         module[0x8];
9320         u8         reserved_at_10[0xc];
9321         u8         module_status[0x4];
9322
9323         u8         reserved_at_20[0x60];
9324 };
9325
9326 struct mlx5_ifc_pmpc_reg_bits {
9327         u8         module_state_updated[32][0x8];
9328 };
9329
9330 struct mlx5_ifc_pmlpn_reg_bits {
9331         u8         reserved_at_0[0x4];
9332         u8         mlpn_status[0x4];
9333         u8         local_port[0x8];
9334         u8         reserved_at_10[0x10];
9335
9336         u8         e[0x1];
9337         u8         reserved_at_21[0x1f];
9338 };
9339
9340 struct mlx5_ifc_pmlp_reg_bits {
9341         u8         rxtx[0x1];
9342         u8         reserved_at_1[0x7];
9343         u8         local_port[0x8];
9344         u8         reserved_at_10[0x8];
9345         u8         width[0x8];
9346
9347         u8         lane0_module_mapping[0x20];
9348
9349         u8         lane1_module_mapping[0x20];
9350
9351         u8         lane2_module_mapping[0x20];
9352
9353         u8         lane3_module_mapping[0x20];
9354
9355         u8         reserved_at_a0[0x160];
9356 };
9357
9358 struct mlx5_ifc_pmaos_reg_bits {
9359         u8         reserved_at_0[0x8];
9360         u8         module[0x8];
9361         u8         reserved_at_10[0x4];
9362         u8         admin_status[0x4];
9363         u8         reserved_at_18[0x4];
9364         u8         oper_status[0x4];
9365
9366         u8         ase[0x1];
9367         u8         ee[0x1];
9368         u8         reserved_at_22[0x1c];
9369         u8         e[0x2];
9370
9371         u8         reserved_at_40[0x40];
9372 };
9373
9374 struct mlx5_ifc_plpc_reg_bits {
9375         u8         reserved_at_0[0x4];
9376         u8         profile_id[0xc];
9377         u8         reserved_at_10[0x4];
9378         u8         proto_mask[0x4];
9379         u8         reserved_at_18[0x8];
9380
9381         u8         reserved_at_20[0x10];
9382         u8         lane_speed[0x10];
9383
9384         u8         reserved_at_40[0x17];
9385         u8         lpbf[0x1];
9386         u8         fec_mode_policy[0x8];
9387
9388         u8         retransmission_capability[0x8];
9389         u8         fec_mode_capability[0x18];
9390
9391         u8         retransmission_support_admin[0x8];
9392         u8         fec_mode_support_admin[0x18];
9393
9394         u8         retransmission_request_admin[0x8];
9395         u8         fec_mode_request_admin[0x18];
9396
9397         u8         reserved_at_c0[0x80];
9398 };
9399
9400 struct mlx5_ifc_plib_reg_bits {
9401         u8         reserved_at_0[0x8];
9402         u8         local_port[0x8];
9403         u8         reserved_at_10[0x8];
9404         u8         ib_port[0x8];
9405
9406         u8         reserved_at_20[0x60];
9407 };
9408
9409 struct mlx5_ifc_plbf_reg_bits {
9410         u8         reserved_at_0[0x8];
9411         u8         local_port[0x8];
9412         u8         reserved_at_10[0xd];
9413         u8         lbf_mode[0x3];
9414
9415         u8         reserved_at_20[0x20];
9416 };
9417
9418 struct mlx5_ifc_pipg_reg_bits {
9419         u8         reserved_at_0[0x8];
9420         u8         local_port[0x8];
9421         u8         reserved_at_10[0x10];
9422
9423         u8         dic[0x1];
9424         u8         reserved_at_21[0x19];
9425         u8         ipg[0x4];
9426         u8         reserved_at_3e[0x2];
9427 };
9428
9429 struct mlx5_ifc_pifr_reg_bits {
9430         u8         reserved_at_0[0x8];
9431         u8         local_port[0x8];
9432         u8         reserved_at_10[0x10];
9433
9434         u8         reserved_at_20[0xe0];
9435
9436         u8         port_filter[8][0x20];
9437
9438         u8         port_filter_update_en[8][0x20];
9439 };
9440
9441 struct mlx5_ifc_pfcc_reg_bits {
9442         u8         reserved_at_0[0x8];
9443         u8         local_port[0x8];
9444         u8         reserved_at_10[0xb];
9445         u8         ppan_mask_n[0x1];
9446         u8         minor_stall_mask[0x1];
9447         u8         critical_stall_mask[0x1];
9448         u8         reserved_at_1e[0x2];
9449
9450         u8         ppan[0x4];
9451         u8         reserved_at_24[0x4];
9452         u8         prio_mask_tx[0x8];
9453         u8         reserved_at_30[0x8];
9454         u8         prio_mask_rx[0x8];
9455
9456         u8         pptx[0x1];
9457         u8         aptx[0x1];
9458         u8         pptx_mask_n[0x1];
9459         u8         reserved_at_43[0x5];
9460         u8         pfctx[0x8];
9461         u8         reserved_at_50[0x10];
9462
9463         u8         pprx[0x1];
9464         u8         aprx[0x1];
9465         u8         pprx_mask_n[0x1];
9466         u8         reserved_at_63[0x5];
9467         u8         pfcrx[0x8];
9468         u8         reserved_at_70[0x10];
9469
9470         u8         device_stall_minor_watermark[0x10];
9471         u8         device_stall_critical_watermark[0x10];
9472
9473         u8         reserved_at_a0[0x60];
9474 };
9475
9476 struct mlx5_ifc_pelc_reg_bits {
9477         u8         op[0x4];
9478         u8         reserved_at_4[0x4];
9479         u8         local_port[0x8];
9480         u8         reserved_at_10[0x10];
9481
9482         u8         op_admin[0x8];
9483         u8         op_capability[0x8];
9484         u8         op_request[0x8];
9485         u8         op_active[0x8];
9486
9487         u8         admin[0x40];
9488
9489         u8         capability[0x40];
9490
9491         u8         request[0x40];
9492
9493         u8         active[0x40];
9494
9495         u8         reserved_at_140[0x80];
9496 };
9497
9498 struct mlx5_ifc_peir_reg_bits {
9499         u8         reserved_at_0[0x8];
9500         u8         local_port[0x8];
9501         u8         reserved_at_10[0x10];
9502
9503         u8         reserved_at_20[0xc];
9504         u8         error_count[0x4];
9505         u8         reserved_at_30[0x10];
9506
9507         u8         reserved_at_40[0xc];
9508         u8         lane[0x4];
9509         u8         reserved_at_50[0x8];
9510         u8         error_type[0x8];
9511 };
9512
9513 struct mlx5_ifc_mpegc_reg_bits {
9514         u8         reserved_at_0[0x30];
9515         u8         field_select[0x10];
9516
9517         u8         tx_overflow_sense[0x1];
9518         u8         mark_cqe[0x1];
9519         u8         mark_cnp[0x1];
9520         u8         reserved_at_43[0x1b];
9521         u8         tx_lossy_overflow_oper[0x2];
9522
9523         u8         reserved_at_60[0x100];
9524 };
9525
9526 enum {
9527         MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9528         MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9529         MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9530 };
9531
9532 struct mlx5_ifc_mtutc_reg_bits {
9533         u8         reserved_at_0[0x1c];
9534         u8         operation[0x4];
9535
9536         u8         freq_adjustment[0x20];
9537
9538         u8         reserved_at_40[0x40];
9539
9540         u8         utc_sec[0x20];
9541
9542         u8         reserved_at_a0[0x2];
9543         u8         utc_nsec[0x1e];
9544
9545         u8         time_adjustment[0x20];
9546 };
9547
9548 struct mlx5_ifc_pcam_enhanced_features_bits {
9549         u8         reserved_at_0[0x68];
9550         u8         fec_50G_per_lane_in_pplm[0x1];
9551         u8         reserved_at_69[0x4];
9552         u8         rx_icrc_encapsulated_counter[0x1];
9553         u8         reserved_at_6e[0x4];
9554         u8         ptys_extended_ethernet[0x1];
9555         u8         reserved_at_73[0x3];
9556         u8         pfcc_mask[0x1];
9557         u8         reserved_at_77[0x3];
9558         u8         per_lane_error_counters[0x1];
9559         u8         rx_buffer_fullness_counters[0x1];
9560         u8         ptys_connector_type[0x1];
9561         u8         reserved_at_7d[0x1];
9562         u8         ppcnt_discard_group[0x1];
9563         u8         ppcnt_statistical_group[0x1];
9564 };
9565
9566 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9567         u8         port_access_reg_cap_mask_127_to_96[0x20];
9568         u8         port_access_reg_cap_mask_95_to_64[0x20];
9569
9570         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9571         u8         pplm[0x1];
9572         u8         port_access_reg_cap_mask_34_to_32[0x3];
9573
9574         u8         port_access_reg_cap_mask_31_to_13[0x13];
9575         u8         pbmc[0x1];
9576         u8         pptb[0x1];
9577         u8         port_access_reg_cap_mask_10_to_09[0x2];
9578         u8         ppcnt[0x1];
9579         u8         port_access_reg_cap_mask_07_to_00[0x8];
9580 };
9581
9582 struct mlx5_ifc_pcam_reg_bits {
9583         u8         reserved_at_0[0x8];
9584         u8         feature_group[0x8];
9585         u8         reserved_at_10[0x8];
9586         u8         access_reg_group[0x8];
9587
9588         u8         reserved_at_20[0x20];
9589
9590         union {
9591                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9592                 u8         reserved_at_0[0x80];
9593         } port_access_reg_cap_mask;
9594
9595         u8         reserved_at_c0[0x80];
9596
9597         union {
9598                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9599                 u8         reserved_at_0[0x80];
9600         } feature_cap_mask;
9601
9602         u8         reserved_at_1c0[0xc0];
9603 };
9604
9605 struct mlx5_ifc_mcam_enhanced_features_bits {
9606         u8         reserved_at_0[0x6b];
9607         u8         ptpcyc2realtime_modify[0x1];
9608         u8         reserved_at_6c[0x2];
9609         u8         pci_status_and_power[0x1];
9610         u8         reserved_at_6f[0x5];
9611         u8         mark_tx_action_cnp[0x1];
9612         u8         mark_tx_action_cqe[0x1];
9613         u8         dynamic_tx_overflow[0x1];
9614         u8         reserved_at_77[0x4];
9615         u8         pcie_outbound_stalled[0x1];
9616         u8         tx_overflow_buffer_pkt[0x1];
9617         u8         mtpps_enh_out_per_adj[0x1];
9618         u8         mtpps_fs[0x1];
9619         u8         pcie_performance_group[0x1];
9620 };
9621
9622 struct mlx5_ifc_mcam_access_reg_bits {
9623         u8         reserved_at_0[0x1c];
9624         u8         mcda[0x1];
9625         u8         mcc[0x1];
9626         u8         mcqi[0x1];
9627         u8         mcqs[0x1];
9628
9629         u8         regs_95_to_87[0x9];
9630         u8         mpegc[0x1];
9631         u8         mtutc[0x1];
9632         u8         regs_84_to_68[0x11];
9633         u8         tracer_registers[0x4];
9634
9635         u8         regs_63_to_32[0x20];
9636         u8         regs_31_to_0[0x20];
9637 };
9638
9639 struct mlx5_ifc_mcam_access_reg_bits1 {
9640         u8         regs_127_to_96[0x20];
9641
9642         u8         regs_95_to_64[0x20];
9643
9644         u8         regs_63_to_32[0x20];
9645
9646         u8         regs_31_to_0[0x20];
9647 };
9648
9649 struct mlx5_ifc_mcam_access_reg_bits2 {
9650         u8         regs_127_to_99[0x1d];
9651         u8         mirc[0x1];
9652         u8         regs_97_to_96[0x2];
9653
9654         u8         regs_95_to_64[0x20];
9655
9656         u8         regs_63_to_32[0x20];
9657
9658         u8         regs_31_to_0[0x20];
9659 };
9660
9661 struct mlx5_ifc_mcam_reg_bits {
9662         u8         reserved_at_0[0x8];
9663         u8         feature_group[0x8];
9664         u8         reserved_at_10[0x8];
9665         u8         access_reg_group[0x8];
9666
9667         u8         reserved_at_20[0x20];
9668
9669         union {
9670                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9671                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9672                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9673                 u8         reserved_at_0[0x80];
9674         } mng_access_reg_cap_mask;
9675
9676         u8         reserved_at_c0[0x80];
9677
9678         union {
9679                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9680                 u8         reserved_at_0[0x80];
9681         } mng_feature_cap_mask;
9682
9683         u8         reserved_at_1c0[0x80];
9684 };
9685
9686 struct mlx5_ifc_qcam_access_reg_cap_mask {
9687         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9688         u8         qpdpm[0x1];
9689         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9690         u8         qdpm[0x1];
9691         u8         qpts[0x1];
9692         u8         qcap[0x1];
9693         u8         qcam_access_reg_cap_mask_0[0x1];
9694 };
9695
9696 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9697         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9698         u8         qpts_trust_both[0x1];
9699 };
9700
9701 struct mlx5_ifc_qcam_reg_bits {
9702         u8         reserved_at_0[0x8];
9703         u8         feature_group[0x8];
9704         u8         reserved_at_10[0x8];
9705         u8         access_reg_group[0x8];
9706         u8         reserved_at_20[0x20];
9707
9708         union {
9709                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9710                 u8  reserved_at_0[0x80];
9711         } qos_access_reg_cap_mask;
9712
9713         u8         reserved_at_c0[0x80];
9714
9715         union {
9716                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9717                 u8  reserved_at_0[0x80];
9718         } qos_feature_cap_mask;
9719
9720         u8         reserved_at_1c0[0x80];
9721 };
9722
9723 struct mlx5_ifc_core_dump_reg_bits {
9724         u8         reserved_at_0[0x18];
9725         u8         core_dump_type[0x8];
9726
9727         u8         reserved_at_20[0x30];
9728         u8         vhca_id[0x10];
9729
9730         u8         reserved_at_60[0x8];
9731         u8         qpn[0x18];
9732         u8         reserved_at_80[0x180];
9733 };
9734
9735 struct mlx5_ifc_pcap_reg_bits {
9736         u8         reserved_at_0[0x8];
9737         u8         local_port[0x8];
9738         u8         reserved_at_10[0x10];
9739
9740         u8         port_capability_mask[4][0x20];
9741 };
9742
9743 struct mlx5_ifc_paos_reg_bits {
9744         u8         swid[0x8];
9745         u8         local_port[0x8];
9746         u8         reserved_at_10[0x4];
9747         u8         admin_status[0x4];
9748         u8         reserved_at_18[0x4];
9749         u8         oper_status[0x4];
9750
9751         u8         ase[0x1];
9752         u8         ee[0x1];
9753         u8         reserved_at_22[0x1c];
9754         u8         e[0x2];
9755
9756         u8         reserved_at_40[0x40];
9757 };
9758
9759 struct mlx5_ifc_pamp_reg_bits {
9760         u8         reserved_at_0[0x8];
9761         u8         opamp_group[0x8];
9762         u8         reserved_at_10[0xc];
9763         u8         opamp_group_type[0x4];
9764
9765         u8         start_index[0x10];
9766         u8         reserved_at_30[0x4];
9767         u8         num_of_indices[0xc];
9768
9769         u8         index_data[18][0x10];
9770 };
9771
9772 struct mlx5_ifc_pcmr_reg_bits {
9773         u8         reserved_at_0[0x8];
9774         u8         local_port[0x8];
9775         u8         reserved_at_10[0x10];
9776
9777         u8         entropy_force_cap[0x1];
9778         u8         entropy_calc_cap[0x1];
9779         u8         entropy_gre_calc_cap[0x1];
9780         u8         reserved_at_23[0xf];
9781         u8         rx_ts_over_crc_cap[0x1];
9782         u8         reserved_at_33[0xb];
9783         u8         fcs_cap[0x1];
9784         u8         reserved_at_3f[0x1];
9785
9786         u8         entropy_force[0x1];
9787         u8         entropy_calc[0x1];
9788         u8         entropy_gre_calc[0x1];
9789         u8         reserved_at_43[0xf];
9790         u8         rx_ts_over_crc[0x1];
9791         u8         reserved_at_53[0xb];
9792         u8         fcs_chk[0x1];
9793         u8         reserved_at_5f[0x1];
9794 };
9795
9796 struct mlx5_ifc_lane_2_module_mapping_bits {
9797         u8         reserved_at_0[0x6];
9798         u8         rx_lane[0x2];
9799         u8         reserved_at_8[0x6];
9800         u8         tx_lane[0x2];
9801         u8         reserved_at_10[0x8];
9802         u8         module[0x8];
9803 };
9804
9805 struct mlx5_ifc_bufferx_reg_bits {
9806         u8         reserved_at_0[0x6];
9807         u8         lossy[0x1];
9808         u8         epsb[0x1];
9809         u8         reserved_at_8[0xc];
9810         u8         size[0xc];
9811
9812         u8         xoff_threshold[0x10];
9813         u8         xon_threshold[0x10];
9814 };
9815
9816 struct mlx5_ifc_set_node_in_bits {
9817         u8         node_description[64][0x8];
9818 };
9819
9820 struct mlx5_ifc_register_power_settings_bits {
9821         u8         reserved_at_0[0x18];
9822         u8         power_settings_level[0x8];
9823
9824         u8         reserved_at_20[0x60];
9825 };
9826
9827 struct mlx5_ifc_register_host_endianness_bits {
9828         u8         he[0x1];
9829         u8         reserved_at_1[0x1f];
9830
9831         u8         reserved_at_20[0x60];
9832 };
9833
9834 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9835         u8         reserved_at_0[0x20];
9836
9837         u8         mkey[0x20];
9838
9839         u8         addressh_63_32[0x20];
9840
9841         u8         addressl_31_0[0x20];
9842 };
9843
9844 struct mlx5_ifc_ud_adrs_vector_bits {
9845         u8         dc_key[0x40];
9846
9847         u8         ext[0x1];
9848         u8         reserved_at_41[0x7];
9849         u8         destination_qp_dct[0x18];
9850
9851         u8         static_rate[0x4];
9852         u8         sl_eth_prio[0x4];
9853         u8         fl[0x1];
9854         u8         mlid[0x7];
9855         u8         rlid_udp_sport[0x10];
9856
9857         u8         reserved_at_80[0x20];
9858
9859         u8         rmac_47_16[0x20];
9860
9861         u8         rmac_15_0[0x10];
9862         u8         tclass[0x8];
9863         u8         hop_limit[0x8];
9864
9865         u8         reserved_at_e0[0x1];
9866         u8         grh[0x1];
9867         u8         reserved_at_e2[0x2];
9868         u8         src_addr_index[0x8];
9869         u8         flow_label[0x14];
9870
9871         u8         rgid_rip[16][0x8];
9872 };
9873
9874 struct mlx5_ifc_pages_req_event_bits {
9875         u8         reserved_at_0[0x10];
9876         u8         function_id[0x10];
9877
9878         u8         num_pages[0x20];
9879
9880         u8         reserved_at_40[0xa0];
9881 };
9882
9883 struct mlx5_ifc_eqe_bits {
9884         u8         reserved_at_0[0x8];
9885         u8         event_type[0x8];
9886         u8         reserved_at_10[0x8];
9887         u8         event_sub_type[0x8];
9888
9889         u8         reserved_at_20[0xe0];
9890
9891         union mlx5_ifc_event_auto_bits event_data;
9892
9893         u8         reserved_at_1e0[0x10];
9894         u8         signature[0x8];
9895         u8         reserved_at_1f8[0x7];
9896         u8         owner[0x1];
9897 };
9898
9899 enum {
9900         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9901 };
9902
9903 struct mlx5_ifc_cmd_queue_entry_bits {
9904         u8         type[0x8];
9905         u8         reserved_at_8[0x18];
9906
9907         u8         input_length[0x20];
9908
9909         u8         input_mailbox_pointer_63_32[0x20];
9910
9911         u8         input_mailbox_pointer_31_9[0x17];
9912         u8         reserved_at_77[0x9];
9913
9914         u8         command_input_inline_data[16][0x8];
9915
9916         u8         command_output_inline_data[16][0x8];
9917
9918         u8         output_mailbox_pointer_63_32[0x20];
9919
9920         u8         output_mailbox_pointer_31_9[0x17];
9921         u8         reserved_at_1b7[0x9];
9922
9923         u8         output_length[0x20];
9924
9925         u8         token[0x8];
9926         u8         signature[0x8];
9927         u8         reserved_at_1f0[0x8];
9928         u8         status[0x7];
9929         u8         ownership[0x1];
9930 };
9931
9932 struct mlx5_ifc_cmd_out_bits {
9933         u8         status[0x8];
9934         u8         reserved_at_8[0x18];
9935
9936         u8         syndrome[0x20];
9937
9938         u8         command_output[0x20];
9939 };
9940
9941 struct mlx5_ifc_cmd_in_bits {
9942         u8         opcode[0x10];
9943         u8         reserved_at_10[0x10];
9944
9945         u8         reserved_at_20[0x10];
9946         u8         op_mod[0x10];
9947
9948         u8         command[][0x20];
9949 };
9950
9951 struct mlx5_ifc_cmd_if_box_bits {
9952         u8         mailbox_data[512][0x8];
9953
9954         u8         reserved_at_1000[0x180];
9955
9956         u8         next_pointer_63_32[0x20];
9957
9958         u8         next_pointer_31_10[0x16];
9959         u8         reserved_at_11b6[0xa];
9960
9961         u8         block_number[0x20];
9962
9963         u8         reserved_at_11e0[0x8];
9964         u8         token[0x8];
9965         u8         ctrl_signature[0x8];
9966         u8         signature[0x8];
9967 };
9968
9969 struct mlx5_ifc_mtt_bits {
9970         u8         ptag_63_32[0x20];
9971
9972         u8         ptag_31_8[0x18];
9973         u8         reserved_at_38[0x6];
9974         u8         wr_en[0x1];
9975         u8         rd_en[0x1];
9976 };
9977
9978 struct mlx5_ifc_query_wol_rol_out_bits {
9979         u8         status[0x8];
9980         u8         reserved_at_8[0x18];
9981
9982         u8         syndrome[0x20];
9983
9984         u8         reserved_at_40[0x10];
9985         u8         rol_mode[0x8];
9986         u8         wol_mode[0x8];
9987
9988         u8         reserved_at_60[0x20];
9989 };
9990
9991 struct mlx5_ifc_query_wol_rol_in_bits {
9992         u8         opcode[0x10];
9993         u8         reserved_at_10[0x10];
9994
9995         u8         reserved_at_20[0x10];
9996         u8         op_mod[0x10];
9997
9998         u8         reserved_at_40[0x40];
9999 };
10000
10001 struct mlx5_ifc_set_wol_rol_out_bits {
10002         u8         status[0x8];
10003         u8         reserved_at_8[0x18];
10004
10005         u8         syndrome[0x20];
10006
10007         u8         reserved_at_40[0x40];
10008 };
10009
10010 struct mlx5_ifc_set_wol_rol_in_bits {
10011         u8         opcode[0x10];
10012         u8         reserved_at_10[0x10];
10013
10014         u8         reserved_at_20[0x10];
10015         u8         op_mod[0x10];
10016
10017         u8         rol_mode_valid[0x1];
10018         u8         wol_mode_valid[0x1];
10019         u8         reserved_at_42[0xe];
10020         u8         rol_mode[0x8];
10021         u8         wol_mode[0x8];
10022
10023         u8         reserved_at_60[0x20];
10024 };
10025
10026 enum {
10027         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10028         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10029         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10030 };
10031
10032 enum {
10033         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10034         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10035         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10036 };
10037
10038 enum {
10039         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10040         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10041         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10042         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10043         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10044         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10045         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10046         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10047         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10048         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10049         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10050 };
10051
10052 struct mlx5_ifc_initial_seg_bits {
10053         u8         fw_rev_minor[0x10];
10054         u8         fw_rev_major[0x10];
10055
10056         u8         cmd_interface_rev[0x10];
10057         u8         fw_rev_subminor[0x10];
10058
10059         u8         reserved_at_40[0x40];
10060
10061         u8         cmdq_phy_addr_63_32[0x20];
10062
10063         u8         cmdq_phy_addr_31_12[0x14];
10064         u8         reserved_at_b4[0x2];
10065         u8         nic_interface[0x2];
10066         u8         log_cmdq_size[0x4];
10067         u8         log_cmdq_stride[0x4];
10068
10069         u8         command_doorbell_vector[0x20];
10070
10071         u8         reserved_at_e0[0xf00];
10072
10073         u8         initializing[0x1];
10074         u8         reserved_at_fe1[0x4];
10075         u8         nic_interface_supported[0x3];
10076         u8         embedded_cpu[0x1];
10077         u8         reserved_at_fe9[0x17];
10078
10079         struct mlx5_ifc_health_buffer_bits health_buffer;
10080
10081         u8         no_dram_nic_offset[0x20];
10082
10083         u8         reserved_at_1220[0x6e40];
10084
10085         u8         reserved_at_8060[0x1f];
10086         u8         clear_int[0x1];
10087
10088         u8         health_syndrome[0x8];
10089         u8         health_counter[0x18];
10090
10091         u8         reserved_at_80a0[0x17fc0];
10092 };
10093
10094 struct mlx5_ifc_mtpps_reg_bits {
10095         u8         reserved_at_0[0xc];
10096         u8         cap_number_of_pps_pins[0x4];
10097         u8         reserved_at_10[0x4];
10098         u8         cap_max_num_of_pps_in_pins[0x4];
10099         u8         reserved_at_18[0x4];
10100         u8         cap_max_num_of_pps_out_pins[0x4];
10101
10102         u8         reserved_at_20[0x24];
10103         u8         cap_pin_3_mode[0x4];
10104         u8         reserved_at_48[0x4];
10105         u8         cap_pin_2_mode[0x4];
10106         u8         reserved_at_50[0x4];
10107         u8         cap_pin_1_mode[0x4];
10108         u8         reserved_at_58[0x4];
10109         u8         cap_pin_0_mode[0x4];
10110
10111         u8         reserved_at_60[0x4];
10112         u8         cap_pin_7_mode[0x4];
10113         u8         reserved_at_68[0x4];
10114         u8         cap_pin_6_mode[0x4];
10115         u8         reserved_at_70[0x4];
10116         u8         cap_pin_5_mode[0x4];
10117         u8         reserved_at_78[0x4];
10118         u8         cap_pin_4_mode[0x4];
10119
10120         u8         field_select[0x20];
10121         u8         reserved_at_a0[0x60];
10122
10123         u8         enable[0x1];
10124         u8         reserved_at_101[0xb];
10125         u8         pattern[0x4];
10126         u8         reserved_at_110[0x4];
10127         u8         pin_mode[0x4];
10128         u8         pin[0x8];
10129
10130         u8         reserved_at_120[0x20];
10131
10132         u8         time_stamp[0x40];
10133
10134         u8         out_pulse_duration[0x10];
10135         u8         out_periodic_adjustment[0x10];
10136         u8         enhanced_out_periodic_adjustment[0x20];
10137
10138         u8         reserved_at_1c0[0x20];
10139 };
10140
10141 struct mlx5_ifc_mtppse_reg_bits {
10142         u8         reserved_at_0[0x18];
10143         u8         pin[0x8];
10144         u8         event_arm[0x1];
10145         u8         reserved_at_21[0x1b];
10146         u8         event_generation_mode[0x4];
10147         u8         reserved_at_40[0x40];
10148 };
10149
10150 struct mlx5_ifc_mcqs_reg_bits {
10151         u8         last_index_flag[0x1];
10152         u8         reserved_at_1[0x7];
10153         u8         fw_device[0x8];
10154         u8         component_index[0x10];
10155
10156         u8         reserved_at_20[0x10];
10157         u8         identifier[0x10];
10158
10159         u8         reserved_at_40[0x17];
10160         u8         component_status[0x5];
10161         u8         component_update_state[0x4];
10162
10163         u8         last_update_state_changer_type[0x4];
10164         u8         last_update_state_changer_host_id[0x4];
10165         u8         reserved_at_68[0x18];
10166 };
10167
10168 struct mlx5_ifc_mcqi_cap_bits {
10169         u8         supported_info_bitmask[0x20];
10170
10171         u8         component_size[0x20];
10172
10173         u8         max_component_size[0x20];
10174
10175         u8         log_mcda_word_size[0x4];
10176         u8         reserved_at_64[0xc];
10177         u8         mcda_max_write_size[0x10];
10178
10179         u8         rd_en[0x1];
10180         u8         reserved_at_81[0x1];
10181         u8         match_chip_id[0x1];
10182         u8         match_psid[0x1];
10183         u8         check_user_timestamp[0x1];
10184         u8         match_base_guid_mac[0x1];
10185         u8         reserved_at_86[0x1a];
10186 };
10187
10188 struct mlx5_ifc_mcqi_version_bits {
10189         u8         reserved_at_0[0x2];
10190         u8         build_time_valid[0x1];
10191         u8         user_defined_time_valid[0x1];
10192         u8         reserved_at_4[0x14];
10193         u8         version_string_length[0x8];
10194
10195         u8         version[0x20];
10196
10197         u8         build_time[0x40];
10198
10199         u8         user_defined_time[0x40];
10200
10201         u8         build_tool_version[0x20];
10202
10203         u8         reserved_at_e0[0x20];
10204
10205         u8         version_string[92][0x8];
10206 };
10207
10208 struct mlx5_ifc_mcqi_activation_method_bits {
10209         u8         pending_server_ac_power_cycle[0x1];
10210         u8         pending_server_dc_power_cycle[0x1];
10211         u8         pending_server_reboot[0x1];
10212         u8         pending_fw_reset[0x1];
10213         u8         auto_activate[0x1];
10214         u8         all_hosts_sync[0x1];
10215         u8         device_hw_reset[0x1];
10216         u8         reserved_at_7[0x19];
10217 };
10218
10219 union mlx5_ifc_mcqi_reg_data_bits {
10220         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10221         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10222         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10223 };
10224
10225 struct mlx5_ifc_mcqi_reg_bits {
10226         u8         read_pending_component[0x1];
10227         u8         reserved_at_1[0xf];
10228         u8         component_index[0x10];
10229
10230         u8         reserved_at_20[0x20];
10231
10232         u8         reserved_at_40[0x1b];
10233         u8         info_type[0x5];
10234
10235         u8         info_size[0x20];
10236
10237         u8         offset[0x20];
10238
10239         u8         reserved_at_a0[0x10];
10240         u8         data_size[0x10];
10241
10242         union mlx5_ifc_mcqi_reg_data_bits data[];
10243 };
10244
10245 struct mlx5_ifc_mcc_reg_bits {
10246         u8         reserved_at_0[0x4];
10247         u8         time_elapsed_since_last_cmd[0xc];
10248         u8         reserved_at_10[0x8];
10249         u8         instruction[0x8];
10250
10251         u8         reserved_at_20[0x10];
10252         u8         component_index[0x10];
10253
10254         u8         reserved_at_40[0x8];
10255         u8         update_handle[0x18];
10256
10257         u8         handle_owner_type[0x4];
10258         u8         handle_owner_host_id[0x4];
10259         u8         reserved_at_68[0x1];
10260         u8         control_progress[0x7];
10261         u8         error_code[0x8];
10262         u8         reserved_at_78[0x4];
10263         u8         control_state[0x4];
10264
10265         u8         component_size[0x20];
10266
10267         u8         reserved_at_a0[0x60];
10268 };
10269
10270 struct mlx5_ifc_mcda_reg_bits {
10271         u8         reserved_at_0[0x8];
10272         u8         update_handle[0x18];
10273
10274         u8         offset[0x20];
10275
10276         u8         reserved_at_40[0x10];
10277         u8         size[0x10];
10278
10279         u8         reserved_at_60[0x20];
10280
10281         u8         data[][0x20];
10282 };
10283
10284 enum {
10285         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10286         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10287 };
10288
10289 enum {
10290         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10291         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10292         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10293 };
10294
10295 struct mlx5_ifc_mfrl_reg_bits {
10296         u8         reserved_at_0[0x20];
10297
10298         u8         reserved_at_20[0x2];
10299         u8         pci_sync_for_fw_update_start[0x1];
10300         u8         pci_sync_for_fw_update_resp[0x2];
10301         u8         rst_type_sel[0x3];
10302         u8         reserved_at_28[0x8];
10303         u8         reset_type[0x8];
10304         u8         reset_level[0x8];
10305 };
10306
10307 struct mlx5_ifc_mirc_reg_bits {
10308         u8         reserved_at_0[0x18];
10309         u8         status_code[0x8];
10310
10311         u8         reserved_at_20[0x20];
10312 };
10313
10314 struct mlx5_ifc_pddr_monitor_opcode_bits {
10315         u8         reserved_at_0[0x10];
10316         u8         monitor_opcode[0x10];
10317 };
10318
10319 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10320         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10321         u8         reserved_at_0[0x20];
10322 };
10323
10324 enum {
10325         /* Monitor opcodes */
10326         MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10327 };
10328
10329 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10330         u8         reserved_at_0[0x10];
10331         u8         group_opcode[0x10];
10332
10333         union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10334
10335         u8         reserved_at_40[0x20];
10336
10337         u8         status_message[59][0x20];
10338 };
10339
10340 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10341         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10342         u8         reserved_at_0[0x7c0];
10343 };
10344
10345 enum {
10346         MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10347 };
10348
10349 struct mlx5_ifc_pddr_reg_bits {
10350         u8         reserved_at_0[0x8];
10351         u8         local_port[0x8];
10352         u8         pnat[0x2];
10353         u8         reserved_at_12[0xe];
10354
10355         u8         reserved_at_20[0x18];
10356         u8         page_select[0x8];
10357
10358         union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10359 };
10360
10361 union mlx5_ifc_ports_control_registers_document_bits {
10362         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10363         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10364         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10365         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10366         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10367         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10368         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10369         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10370         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10371         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10372         struct mlx5_ifc_pamp_reg_bits pamp_reg;
10373         struct mlx5_ifc_paos_reg_bits paos_reg;
10374         struct mlx5_ifc_pcap_reg_bits pcap_reg;
10375         struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10376         struct mlx5_ifc_pddr_reg_bits pddr_reg;
10377         struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10378         struct mlx5_ifc_peir_reg_bits peir_reg;
10379         struct mlx5_ifc_pelc_reg_bits pelc_reg;
10380         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10381         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10382         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10383         struct mlx5_ifc_pifr_reg_bits pifr_reg;
10384         struct mlx5_ifc_pipg_reg_bits pipg_reg;
10385         struct mlx5_ifc_plbf_reg_bits plbf_reg;
10386         struct mlx5_ifc_plib_reg_bits plib_reg;
10387         struct mlx5_ifc_plpc_reg_bits plpc_reg;
10388         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10389         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10390         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10391         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10392         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10393         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10394         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10395         struct mlx5_ifc_ppad_reg_bits ppad_reg;
10396         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10397         struct mlx5_ifc_mpein_reg_bits mpein_reg;
10398         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10399         struct mlx5_ifc_pplm_reg_bits pplm_reg;
10400         struct mlx5_ifc_pplr_reg_bits pplr_reg;
10401         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10402         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10403         struct mlx5_ifc_pspa_reg_bits pspa_reg;
10404         struct mlx5_ifc_ptas_reg_bits ptas_reg;
10405         struct mlx5_ifc_ptys_reg_bits ptys_reg;
10406         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10407         struct mlx5_ifc_pude_reg_bits pude_reg;
10408         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10409         struct mlx5_ifc_slrg_reg_bits slrg_reg;
10410         struct mlx5_ifc_sltp_reg_bits sltp_reg;
10411         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10412         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10413         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10414         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10415         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10416         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10417         struct mlx5_ifc_mcc_reg_bits mcc_reg;
10418         struct mlx5_ifc_mcda_reg_bits mcda_reg;
10419         struct mlx5_ifc_mirc_reg_bits mirc_reg;
10420         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10421         struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10422         u8         reserved_at_0[0x60e0];
10423 };
10424
10425 union mlx5_ifc_debug_enhancements_document_bits {
10426         struct mlx5_ifc_health_buffer_bits health_buffer;
10427         u8         reserved_at_0[0x200];
10428 };
10429
10430 union mlx5_ifc_uplink_pci_interface_document_bits {
10431         struct mlx5_ifc_initial_seg_bits initial_seg;
10432         u8         reserved_at_0[0x20060];
10433 };
10434
10435 struct mlx5_ifc_set_flow_table_root_out_bits {
10436         u8         status[0x8];
10437         u8         reserved_at_8[0x18];
10438
10439         u8         syndrome[0x20];
10440
10441         u8         reserved_at_40[0x40];
10442 };
10443
10444 struct mlx5_ifc_set_flow_table_root_in_bits {
10445         u8         opcode[0x10];
10446         u8         reserved_at_10[0x10];
10447
10448         u8         reserved_at_20[0x10];
10449         u8         op_mod[0x10];
10450
10451         u8         other_vport[0x1];
10452         u8         reserved_at_41[0xf];
10453         u8         vport_number[0x10];
10454
10455         u8         reserved_at_60[0x20];
10456
10457         u8         table_type[0x8];
10458         u8         reserved_at_88[0x7];
10459         u8         table_of_other_vport[0x1];
10460         u8         table_vport_number[0x10];
10461
10462         u8         reserved_at_a0[0x8];
10463         u8         table_id[0x18];
10464
10465         u8         reserved_at_c0[0x8];
10466         u8         underlay_qpn[0x18];
10467         u8         table_eswitch_owner_vhca_id_valid[0x1];
10468         u8         reserved_at_e1[0xf];
10469         u8         table_eswitch_owner_vhca_id[0x10];
10470         u8         reserved_at_100[0x100];
10471 };
10472
10473 enum {
10474         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10475         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10476 };
10477
10478 struct mlx5_ifc_modify_flow_table_out_bits {
10479         u8         status[0x8];
10480         u8         reserved_at_8[0x18];
10481
10482         u8         syndrome[0x20];
10483
10484         u8         reserved_at_40[0x40];
10485 };
10486
10487 struct mlx5_ifc_modify_flow_table_in_bits {
10488         u8         opcode[0x10];
10489         u8         reserved_at_10[0x10];
10490
10491         u8         reserved_at_20[0x10];
10492         u8         op_mod[0x10];
10493
10494         u8         other_vport[0x1];
10495         u8         reserved_at_41[0xf];
10496         u8         vport_number[0x10];
10497
10498         u8         reserved_at_60[0x10];
10499         u8         modify_field_select[0x10];
10500
10501         u8         table_type[0x8];
10502         u8         reserved_at_88[0x18];
10503
10504         u8         reserved_at_a0[0x8];
10505         u8         table_id[0x18];
10506
10507         struct mlx5_ifc_flow_table_context_bits flow_table_context;
10508 };
10509
10510 struct mlx5_ifc_ets_tcn_config_reg_bits {
10511         u8         g[0x1];
10512         u8         b[0x1];
10513         u8         r[0x1];
10514         u8         reserved_at_3[0x9];
10515         u8         group[0x4];
10516         u8         reserved_at_10[0x9];
10517         u8         bw_allocation[0x7];
10518
10519         u8         reserved_at_20[0xc];
10520         u8         max_bw_units[0x4];
10521         u8         reserved_at_30[0x8];
10522         u8         max_bw_value[0x8];
10523 };
10524
10525 struct mlx5_ifc_ets_global_config_reg_bits {
10526         u8         reserved_at_0[0x2];
10527         u8         r[0x1];
10528         u8         reserved_at_3[0x1d];
10529
10530         u8         reserved_at_20[0xc];
10531         u8         max_bw_units[0x4];
10532         u8         reserved_at_30[0x8];
10533         u8         max_bw_value[0x8];
10534 };
10535
10536 struct mlx5_ifc_qetc_reg_bits {
10537         u8                                         reserved_at_0[0x8];
10538         u8                                         port_number[0x8];
10539         u8                                         reserved_at_10[0x30];
10540
10541         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10542         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10543 };
10544
10545 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10546         u8         e[0x1];
10547         u8         reserved_at_01[0x0b];
10548         u8         prio[0x04];
10549 };
10550
10551 struct mlx5_ifc_qpdpm_reg_bits {
10552         u8                                     reserved_at_0[0x8];
10553         u8                                     local_port[0x8];
10554         u8                                     reserved_at_10[0x10];
10555         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10556 };
10557
10558 struct mlx5_ifc_qpts_reg_bits {
10559         u8         reserved_at_0[0x8];
10560         u8         local_port[0x8];
10561         u8         reserved_at_10[0x2d];
10562         u8         trust_state[0x3];
10563 };
10564
10565 struct mlx5_ifc_pptb_reg_bits {
10566         u8         reserved_at_0[0x2];
10567         u8         mm[0x2];
10568         u8         reserved_at_4[0x4];
10569         u8         local_port[0x8];
10570         u8         reserved_at_10[0x6];
10571         u8         cm[0x1];
10572         u8         um[0x1];
10573         u8         pm[0x8];
10574
10575         u8         prio_x_buff[0x20];
10576
10577         u8         pm_msb[0x8];
10578         u8         reserved_at_48[0x10];
10579         u8         ctrl_buff[0x4];
10580         u8         untagged_buff[0x4];
10581 };
10582
10583 struct mlx5_ifc_sbcam_reg_bits {
10584         u8         reserved_at_0[0x8];
10585         u8         feature_group[0x8];
10586         u8         reserved_at_10[0x8];
10587         u8         access_reg_group[0x8];
10588
10589         u8         reserved_at_20[0x20];
10590
10591         u8         sb_access_reg_cap_mask[4][0x20];
10592
10593         u8         reserved_at_c0[0x80];
10594
10595         u8         sb_feature_cap_mask[4][0x20];
10596
10597         u8         reserved_at_1c0[0x40];
10598
10599         u8         cap_total_buffer_size[0x20];
10600
10601         u8         cap_cell_size[0x10];
10602         u8         cap_max_pg_buffers[0x8];
10603         u8         cap_num_pool_supported[0x8];
10604
10605         u8         reserved_at_240[0x8];
10606         u8         cap_sbsr_stat_size[0x8];
10607         u8         cap_max_tclass_data[0x8];
10608         u8         cap_max_cpu_ingress_tclass_sb[0x8];
10609 };
10610
10611 struct mlx5_ifc_pbmc_reg_bits {
10612         u8         reserved_at_0[0x8];
10613         u8         local_port[0x8];
10614         u8         reserved_at_10[0x10];
10615
10616         u8         xoff_timer_value[0x10];
10617         u8         xoff_refresh[0x10];
10618
10619         u8         reserved_at_40[0x9];
10620         u8         fullness_threshold[0x7];
10621         u8         port_buffer_size[0x10];
10622
10623         struct mlx5_ifc_bufferx_reg_bits buffer[10];
10624
10625         u8         reserved_at_2e0[0x80];
10626 };
10627
10628 struct mlx5_ifc_qtct_reg_bits {
10629         u8         reserved_at_0[0x8];
10630         u8         port_number[0x8];
10631         u8         reserved_at_10[0xd];
10632         u8         prio[0x3];
10633
10634         u8         reserved_at_20[0x1d];
10635         u8         tclass[0x3];
10636 };
10637
10638 struct mlx5_ifc_mcia_reg_bits {
10639         u8         l[0x1];
10640         u8         reserved_at_1[0x7];
10641         u8         module[0x8];
10642         u8         reserved_at_10[0x8];
10643         u8         status[0x8];
10644
10645         u8         i2c_device_address[0x8];
10646         u8         page_number[0x8];
10647         u8         device_address[0x10];
10648
10649         u8         reserved_at_40[0x10];
10650         u8         size[0x10];
10651
10652         u8         reserved_at_60[0x20];
10653
10654         u8         dword_0[0x20];
10655         u8         dword_1[0x20];
10656         u8         dword_2[0x20];
10657         u8         dword_3[0x20];
10658         u8         dword_4[0x20];
10659         u8         dword_5[0x20];
10660         u8         dword_6[0x20];
10661         u8         dword_7[0x20];
10662         u8         dword_8[0x20];
10663         u8         dword_9[0x20];
10664         u8         dword_10[0x20];
10665         u8         dword_11[0x20];
10666 };
10667
10668 struct mlx5_ifc_dcbx_param_bits {
10669         u8         dcbx_cee_cap[0x1];
10670         u8         dcbx_ieee_cap[0x1];
10671         u8         dcbx_standby_cap[0x1];
10672         u8         reserved_at_3[0x5];
10673         u8         port_number[0x8];
10674         u8         reserved_at_10[0xa];
10675         u8         max_application_table_size[6];
10676         u8         reserved_at_20[0x15];
10677         u8         version_oper[0x3];
10678         u8         reserved_at_38[5];
10679         u8         version_admin[0x3];
10680         u8         willing_admin[0x1];
10681         u8         reserved_at_41[0x3];
10682         u8         pfc_cap_oper[0x4];
10683         u8         reserved_at_48[0x4];
10684         u8         pfc_cap_admin[0x4];
10685         u8         reserved_at_50[0x4];
10686         u8         num_of_tc_oper[0x4];
10687         u8         reserved_at_58[0x4];
10688         u8         num_of_tc_admin[0x4];
10689         u8         remote_willing[0x1];
10690         u8         reserved_at_61[3];
10691         u8         remote_pfc_cap[4];
10692         u8         reserved_at_68[0x14];
10693         u8         remote_num_of_tc[0x4];
10694         u8         reserved_at_80[0x18];
10695         u8         error[0x8];
10696         u8         reserved_at_a0[0x160];
10697 };
10698
10699 enum {
10700         MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10701         MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT,
10702 };
10703
10704 struct mlx5_ifc_lagc_bits {
10705         u8         fdb_selection_mode[0x1];
10706         u8         reserved_at_1[0x14];
10707         u8         port_select_mode[0x3];
10708         u8         reserved_at_18[0x5];
10709         u8         lag_state[0x3];
10710
10711         u8         reserved_at_20[0x14];
10712         u8         tx_remap_affinity_2[0x4];
10713         u8         reserved_at_38[0x4];
10714         u8         tx_remap_affinity_1[0x4];
10715 };
10716
10717 struct mlx5_ifc_create_lag_out_bits {
10718         u8         status[0x8];
10719         u8         reserved_at_8[0x18];
10720
10721         u8         syndrome[0x20];
10722
10723         u8         reserved_at_40[0x40];
10724 };
10725
10726 struct mlx5_ifc_create_lag_in_bits {
10727         u8         opcode[0x10];
10728         u8         reserved_at_10[0x10];
10729
10730         u8         reserved_at_20[0x10];
10731         u8         op_mod[0x10];
10732
10733         struct mlx5_ifc_lagc_bits ctx;
10734 };
10735
10736 struct mlx5_ifc_modify_lag_out_bits {
10737         u8         status[0x8];
10738         u8         reserved_at_8[0x18];
10739
10740         u8         syndrome[0x20];
10741
10742         u8         reserved_at_40[0x40];
10743 };
10744
10745 struct mlx5_ifc_modify_lag_in_bits {
10746         u8         opcode[0x10];
10747         u8         reserved_at_10[0x10];
10748
10749         u8         reserved_at_20[0x10];
10750         u8         op_mod[0x10];
10751
10752         u8         reserved_at_40[0x20];
10753         u8         field_select[0x20];
10754
10755         struct mlx5_ifc_lagc_bits ctx;
10756 };
10757
10758 struct mlx5_ifc_query_lag_out_bits {
10759         u8         status[0x8];
10760         u8         reserved_at_8[0x18];
10761
10762         u8         syndrome[0x20];
10763
10764         struct mlx5_ifc_lagc_bits ctx;
10765 };
10766
10767 struct mlx5_ifc_query_lag_in_bits {
10768         u8         opcode[0x10];
10769         u8         reserved_at_10[0x10];
10770
10771         u8         reserved_at_20[0x10];
10772         u8         op_mod[0x10];
10773
10774         u8         reserved_at_40[0x40];
10775 };
10776
10777 struct mlx5_ifc_destroy_lag_out_bits {
10778         u8         status[0x8];
10779         u8         reserved_at_8[0x18];
10780
10781         u8         syndrome[0x20];
10782
10783         u8         reserved_at_40[0x40];
10784 };
10785
10786 struct mlx5_ifc_destroy_lag_in_bits {
10787         u8         opcode[0x10];
10788         u8         reserved_at_10[0x10];
10789
10790         u8         reserved_at_20[0x10];
10791         u8         op_mod[0x10];
10792
10793         u8         reserved_at_40[0x40];
10794 };
10795
10796 struct mlx5_ifc_create_vport_lag_out_bits {
10797         u8         status[0x8];
10798         u8         reserved_at_8[0x18];
10799
10800         u8         syndrome[0x20];
10801
10802         u8         reserved_at_40[0x40];
10803 };
10804
10805 struct mlx5_ifc_create_vport_lag_in_bits {
10806         u8         opcode[0x10];
10807         u8         reserved_at_10[0x10];
10808
10809         u8         reserved_at_20[0x10];
10810         u8         op_mod[0x10];
10811
10812         u8         reserved_at_40[0x40];
10813 };
10814
10815 struct mlx5_ifc_destroy_vport_lag_out_bits {
10816         u8         status[0x8];
10817         u8         reserved_at_8[0x18];
10818
10819         u8         syndrome[0x20];
10820
10821         u8         reserved_at_40[0x40];
10822 };
10823
10824 struct mlx5_ifc_destroy_vport_lag_in_bits {
10825         u8         opcode[0x10];
10826         u8         reserved_at_10[0x10];
10827
10828         u8         reserved_at_20[0x10];
10829         u8         op_mod[0x10];
10830
10831         u8         reserved_at_40[0x40];
10832 };
10833
10834 enum {
10835         MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
10836         MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
10837 };
10838
10839 struct mlx5_ifc_modify_memic_in_bits {
10840         u8         opcode[0x10];
10841         u8         uid[0x10];
10842
10843         u8         reserved_at_20[0x10];
10844         u8         op_mod[0x10];
10845
10846         u8         reserved_at_40[0x20];
10847
10848         u8         reserved_at_60[0x18];
10849         u8         memic_operation_type[0x8];
10850
10851         u8         memic_start_addr[0x40];
10852
10853         u8         reserved_at_c0[0x140];
10854 };
10855
10856 struct mlx5_ifc_modify_memic_out_bits {
10857         u8         status[0x8];
10858         u8         reserved_at_8[0x18];
10859
10860         u8         syndrome[0x20];
10861
10862         u8         reserved_at_40[0x40];
10863
10864         u8         memic_operation_addr[0x40];
10865
10866         u8         reserved_at_c0[0x140];
10867 };
10868
10869 struct mlx5_ifc_alloc_memic_in_bits {
10870         u8         opcode[0x10];
10871         u8         reserved_at_10[0x10];
10872
10873         u8         reserved_at_20[0x10];
10874         u8         op_mod[0x10];
10875
10876         u8         reserved_at_30[0x20];
10877
10878         u8         reserved_at_40[0x18];
10879         u8         log_memic_addr_alignment[0x8];
10880
10881         u8         range_start_addr[0x40];
10882
10883         u8         range_size[0x20];
10884
10885         u8         memic_size[0x20];
10886 };
10887
10888 struct mlx5_ifc_alloc_memic_out_bits {
10889         u8         status[0x8];
10890         u8         reserved_at_8[0x18];
10891
10892         u8         syndrome[0x20];
10893
10894         u8         memic_start_addr[0x40];
10895 };
10896
10897 struct mlx5_ifc_dealloc_memic_in_bits {
10898         u8         opcode[0x10];
10899         u8         reserved_at_10[0x10];
10900
10901         u8         reserved_at_20[0x10];
10902         u8         op_mod[0x10];
10903
10904         u8         reserved_at_40[0x40];
10905
10906         u8         memic_start_addr[0x40];
10907
10908         u8         memic_size[0x20];
10909
10910         u8         reserved_at_e0[0x20];
10911 };
10912
10913 struct mlx5_ifc_dealloc_memic_out_bits {
10914         u8         status[0x8];
10915         u8         reserved_at_8[0x18];
10916
10917         u8         syndrome[0x20];
10918
10919         u8         reserved_at_40[0x40];
10920 };
10921
10922 struct mlx5_ifc_umem_bits {
10923         u8         reserved_at_0[0x80];
10924
10925         u8         reserved_at_80[0x1b];
10926         u8         log_page_size[0x5];
10927
10928         u8         page_offset[0x20];
10929
10930         u8         num_of_mtt[0x40];
10931
10932         struct mlx5_ifc_mtt_bits  mtt[];
10933 };
10934
10935 struct mlx5_ifc_uctx_bits {
10936         u8         cap[0x20];
10937
10938         u8         reserved_at_20[0x160];
10939 };
10940
10941 struct mlx5_ifc_sw_icm_bits {
10942         u8         modify_field_select[0x40];
10943
10944         u8         reserved_at_40[0x18];
10945         u8         log_sw_icm_size[0x8];
10946
10947         u8         reserved_at_60[0x20];
10948
10949         u8         sw_icm_start_addr[0x40];
10950
10951         u8         reserved_at_c0[0x140];
10952 };
10953
10954 struct mlx5_ifc_geneve_tlv_option_bits {
10955         u8         modify_field_select[0x40];
10956
10957         u8         reserved_at_40[0x18];
10958         u8         geneve_option_fte_index[0x8];
10959
10960         u8         option_class[0x10];
10961         u8         option_type[0x8];
10962         u8         reserved_at_78[0x3];
10963         u8         option_data_length[0x5];
10964
10965         u8         reserved_at_80[0x180];
10966 };
10967
10968 struct mlx5_ifc_create_umem_in_bits {
10969         u8         opcode[0x10];
10970         u8         uid[0x10];
10971
10972         u8         reserved_at_20[0x10];
10973         u8         op_mod[0x10];
10974
10975         u8         reserved_at_40[0x40];
10976
10977         struct mlx5_ifc_umem_bits  umem;
10978 };
10979
10980 struct mlx5_ifc_create_umem_out_bits {
10981         u8         status[0x8];
10982         u8         reserved_at_8[0x18];
10983
10984         u8         syndrome[0x20];
10985
10986         u8         reserved_at_40[0x8];
10987         u8         umem_id[0x18];
10988
10989         u8         reserved_at_60[0x20];
10990 };
10991
10992 struct mlx5_ifc_destroy_umem_in_bits {
10993         u8        opcode[0x10];
10994         u8        uid[0x10];
10995
10996         u8        reserved_at_20[0x10];
10997         u8        op_mod[0x10];
10998
10999         u8        reserved_at_40[0x8];
11000         u8        umem_id[0x18];
11001
11002         u8        reserved_at_60[0x20];
11003 };
11004
11005 struct mlx5_ifc_destroy_umem_out_bits {
11006         u8        status[0x8];
11007         u8        reserved_at_8[0x18];
11008
11009         u8        syndrome[0x20];
11010
11011         u8        reserved_at_40[0x40];
11012 };
11013
11014 struct mlx5_ifc_create_uctx_in_bits {
11015         u8         opcode[0x10];
11016         u8         reserved_at_10[0x10];
11017
11018         u8         reserved_at_20[0x10];
11019         u8         op_mod[0x10];
11020
11021         u8         reserved_at_40[0x40];
11022
11023         struct mlx5_ifc_uctx_bits  uctx;
11024 };
11025
11026 struct mlx5_ifc_create_uctx_out_bits {
11027         u8         status[0x8];
11028         u8         reserved_at_8[0x18];
11029
11030         u8         syndrome[0x20];
11031
11032         u8         reserved_at_40[0x10];
11033         u8         uid[0x10];
11034
11035         u8         reserved_at_60[0x20];
11036 };
11037
11038 struct mlx5_ifc_destroy_uctx_in_bits {
11039         u8         opcode[0x10];
11040         u8         reserved_at_10[0x10];
11041
11042         u8         reserved_at_20[0x10];
11043         u8         op_mod[0x10];
11044
11045         u8         reserved_at_40[0x10];
11046         u8         uid[0x10];
11047
11048         u8         reserved_at_60[0x20];
11049 };
11050
11051 struct mlx5_ifc_destroy_uctx_out_bits {
11052         u8         status[0x8];
11053         u8         reserved_at_8[0x18];
11054
11055         u8         syndrome[0x20];
11056
11057         u8          reserved_at_40[0x40];
11058 };
11059
11060 struct mlx5_ifc_create_sw_icm_in_bits {
11061         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11062         struct mlx5_ifc_sw_icm_bits                   sw_icm;
11063 };
11064
11065 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11066         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11067         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11068 };
11069
11070 struct mlx5_ifc_mtrc_string_db_param_bits {
11071         u8         string_db_base_address[0x20];
11072
11073         u8         reserved_at_20[0x8];
11074         u8         string_db_size[0x18];
11075 };
11076
11077 struct mlx5_ifc_mtrc_cap_bits {
11078         u8         trace_owner[0x1];
11079         u8         trace_to_memory[0x1];
11080         u8         reserved_at_2[0x4];
11081         u8         trc_ver[0x2];
11082         u8         reserved_at_8[0x14];
11083         u8         num_string_db[0x4];
11084
11085         u8         first_string_trace[0x8];
11086         u8         num_string_trace[0x8];
11087         u8         reserved_at_30[0x28];
11088
11089         u8         log_max_trace_buffer_size[0x8];
11090
11091         u8         reserved_at_60[0x20];
11092
11093         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11094
11095         u8         reserved_at_280[0x180];
11096 };
11097
11098 struct mlx5_ifc_mtrc_conf_bits {
11099         u8         reserved_at_0[0x1c];
11100         u8         trace_mode[0x4];
11101         u8         reserved_at_20[0x18];
11102         u8         log_trace_buffer_size[0x8];
11103         u8         trace_mkey[0x20];
11104         u8         reserved_at_60[0x3a0];
11105 };
11106
11107 struct mlx5_ifc_mtrc_stdb_bits {
11108         u8         string_db_index[0x4];
11109         u8         reserved_at_4[0x4];
11110         u8         read_size[0x18];
11111         u8         start_offset[0x20];
11112         u8         string_db_data[];
11113 };
11114
11115 struct mlx5_ifc_mtrc_ctrl_bits {
11116         u8         trace_status[0x2];
11117         u8         reserved_at_2[0x2];
11118         u8         arm_event[0x1];
11119         u8         reserved_at_5[0xb];
11120         u8         modify_field_select[0x10];
11121         u8         reserved_at_20[0x2b];
11122         u8         current_timestamp52_32[0x15];
11123         u8         current_timestamp31_0[0x20];
11124         u8         reserved_at_80[0x180];
11125 };
11126
11127 struct mlx5_ifc_host_params_context_bits {
11128         u8         host_number[0x8];
11129         u8         reserved_at_8[0x7];
11130         u8         host_pf_disabled[0x1];
11131         u8         host_num_of_vfs[0x10];
11132
11133         u8         host_total_vfs[0x10];
11134         u8         host_pci_bus[0x10];
11135
11136         u8         reserved_at_40[0x10];
11137         u8         host_pci_device[0x10];
11138
11139         u8         reserved_at_60[0x10];
11140         u8         host_pci_function[0x10];
11141
11142         u8         reserved_at_80[0x180];
11143 };
11144
11145 struct mlx5_ifc_query_esw_functions_in_bits {
11146         u8         opcode[0x10];
11147         u8         reserved_at_10[0x10];
11148
11149         u8         reserved_at_20[0x10];
11150         u8         op_mod[0x10];
11151
11152         u8         reserved_at_40[0x40];
11153 };
11154
11155 struct mlx5_ifc_query_esw_functions_out_bits {
11156         u8         status[0x8];
11157         u8         reserved_at_8[0x18];
11158
11159         u8         syndrome[0x20];
11160
11161         u8         reserved_at_40[0x40];
11162
11163         struct mlx5_ifc_host_params_context_bits host_params_context;
11164
11165         u8         reserved_at_280[0x180];
11166         u8         host_sf_enable[][0x40];
11167 };
11168
11169 struct mlx5_ifc_sf_partition_bits {
11170         u8         reserved_at_0[0x10];
11171         u8         log_num_sf[0x8];
11172         u8         log_sf_bar_size[0x8];
11173 };
11174
11175 struct mlx5_ifc_query_sf_partitions_out_bits {
11176         u8         status[0x8];
11177         u8         reserved_at_8[0x18];
11178
11179         u8         syndrome[0x20];
11180
11181         u8         reserved_at_40[0x18];
11182         u8         num_sf_partitions[0x8];
11183
11184         u8         reserved_at_60[0x20];
11185
11186         struct mlx5_ifc_sf_partition_bits sf_partition[];
11187 };
11188
11189 struct mlx5_ifc_query_sf_partitions_in_bits {
11190         u8         opcode[0x10];
11191         u8         reserved_at_10[0x10];
11192
11193         u8         reserved_at_20[0x10];
11194         u8         op_mod[0x10];
11195
11196         u8         reserved_at_40[0x40];
11197 };
11198
11199 struct mlx5_ifc_dealloc_sf_out_bits {
11200         u8         status[0x8];
11201         u8         reserved_at_8[0x18];
11202
11203         u8         syndrome[0x20];
11204
11205         u8         reserved_at_40[0x40];
11206 };
11207
11208 struct mlx5_ifc_dealloc_sf_in_bits {
11209         u8         opcode[0x10];
11210         u8         reserved_at_10[0x10];
11211
11212         u8         reserved_at_20[0x10];
11213         u8         op_mod[0x10];
11214
11215         u8         reserved_at_40[0x10];
11216         u8         function_id[0x10];
11217
11218         u8         reserved_at_60[0x20];
11219 };
11220
11221 struct mlx5_ifc_alloc_sf_out_bits {
11222         u8         status[0x8];
11223         u8         reserved_at_8[0x18];
11224
11225         u8         syndrome[0x20];
11226
11227         u8         reserved_at_40[0x40];
11228 };
11229
11230 struct mlx5_ifc_alloc_sf_in_bits {
11231         u8         opcode[0x10];
11232         u8         reserved_at_10[0x10];
11233
11234         u8         reserved_at_20[0x10];
11235         u8         op_mod[0x10];
11236
11237         u8         reserved_at_40[0x10];
11238         u8         function_id[0x10];
11239
11240         u8         reserved_at_60[0x20];
11241 };
11242
11243 struct mlx5_ifc_affiliated_event_header_bits {
11244         u8         reserved_at_0[0x10];
11245         u8         obj_type[0x10];
11246
11247         u8         obj_id[0x20];
11248 };
11249
11250 enum {
11251         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11252         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11253         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11254 };
11255
11256 enum {
11257         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11258         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11259         MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11260 };
11261
11262 enum {
11263         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11264         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
11265         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
11266 };
11267
11268 struct mlx5_ifc_ipsec_obj_bits {
11269         u8         modify_field_select[0x40];
11270         u8         full_offload[0x1];
11271         u8         reserved_at_41[0x1];
11272         u8         esn_en[0x1];
11273         u8         esn_overlap[0x1];
11274         u8         reserved_at_44[0x2];
11275         u8         icv_length[0x2];
11276         u8         reserved_at_48[0x4];
11277         u8         aso_return_reg[0x4];
11278         u8         reserved_at_50[0x10];
11279
11280         u8         esn_msb[0x20];
11281
11282         u8         reserved_at_80[0x8];
11283         u8         dekn[0x18];
11284
11285         u8         salt[0x20];
11286
11287         u8         implicit_iv[0x40];
11288
11289         u8         reserved_at_100[0x700];
11290 };
11291
11292 struct mlx5_ifc_create_ipsec_obj_in_bits {
11293         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11294         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11295 };
11296
11297 enum {
11298         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11299         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11300 };
11301
11302 struct mlx5_ifc_query_ipsec_obj_out_bits {
11303         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11304         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11305 };
11306
11307 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11308         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11309         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11310 };
11311
11312 struct mlx5_ifc_encryption_key_obj_bits {
11313         u8         modify_field_select[0x40];
11314
11315         u8         reserved_at_40[0x14];
11316         u8         key_size[0x4];
11317         u8         reserved_at_58[0x4];
11318         u8         key_type[0x4];
11319
11320         u8         reserved_at_60[0x8];
11321         u8         pd[0x18];
11322
11323         u8         reserved_at_80[0x180];
11324         u8         key[8][0x20];
11325
11326         u8         reserved_at_300[0x500];
11327 };
11328
11329 struct mlx5_ifc_create_encryption_key_in_bits {
11330         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11331         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11332 };
11333
11334 struct mlx5_ifc_sampler_obj_bits {
11335         u8         modify_field_select[0x40];
11336
11337         u8         table_type[0x8];
11338         u8         level[0x8];
11339         u8         reserved_at_50[0xf];
11340         u8         ignore_flow_level[0x1];
11341
11342         u8         sample_ratio[0x20];
11343
11344         u8         reserved_at_80[0x8];
11345         u8         sample_table_id[0x18];
11346
11347         u8         reserved_at_a0[0x8];
11348         u8         default_table_id[0x18];
11349
11350         u8         sw_steering_icm_address_rx[0x40];
11351         u8         sw_steering_icm_address_tx[0x40];
11352
11353         u8         reserved_at_140[0xa0];
11354 };
11355
11356 struct mlx5_ifc_create_sampler_obj_in_bits {
11357         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11358         struct mlx5_ifc_sampler_obj_bits sampler_object;
11359 };
11360
11361 struct mlx5_ifc_query_sampler_obj_out_bits {
11362         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11363         struct mlx5_ifc_sampler_obj_bits sampler_object;
11364 };
11365
11366 enum {
11367         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11368         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11369 };
11370
11371 enum {
11372         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11373         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11374 };
11375
11376 struct mlx5_ifc_tls_static_params_bits {
11377         u8         const_2[0x2];
11378         u8         tls_version[0x4];
11379         u8         const_1[0x2];
11380         u8         reserved_at_8[0x14];
11381         u8         encryption_standard[0x4];
11382
11383         u8         reserved_at_20[0x20];
11384
11385         u8         initial_record_number[0x40];
11386
11387         u8         resync_tcp_sn[0x20];
11388
11389         u8         gcm_iv[0x20];
11390
11391         u8         implicit_iv[0x40];
11392
11393         u8         reserved_at_100[0x8];
11394         u8         dek_index[0x18];
11395
11396         u8         reserved_at_120[0xe0];
11397 };
11398
11399 struct mlx5_ifc_tls_progress_params_bits {
11400         u8         next_record_tcp_sn[0x20];
11401
11402         u8         hw_resync_tcp_sn[0x20];
11403
11404         u8         record_tracker_state[0x2];
11405         u8         auth_state[0x2];
11406         u8         reserved_at_44[0x4];
11407         u8         hw_offset_record_number[0x18];
11408 };
11409
11410 enum {
11411         MLX5_MTT_PERM_READ      = 1 << 0,
11412         MLX5_MTT_PERM_WRITE     = 1 << 1,
11413         MLX5_MTT_PERM_RW        = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11414 };
11415
11416 #endif /* MLX5_IFC_H */