include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  91 };
  92
  93 enum {
  94         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  95         MLX5_OBJ_TYPE_MKEY = 0xff01,
  96         MLX5_OBJ_TYPE_QP = 0xff02,
  97         MLX5_OBJ_TYPE_PSV = 0xff03,
  98         MLX5_OBJ_TYPE_RMP = 0xff04,
  99         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 100         MLX5_OBJ_TYPE_RQ = 0xff06,
 101         MLX5_OBJ_TYPE_SQ = 0xff07,
 102         MLX5_OBJ_TYPE_TIR = 0xff08,
 103         MLX5_OBJ_TYPE_TIS = 0xff09,
 104         MLX5_OBJ_TYPE_DCT = 0xff0a,
 105         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 106         MLX5_OBJ_TYPE_RQT = 0xff0e,
 107         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 108         MLX5_OBJ_TYPE_CQ = 0xff10,
 109 };
 110
 111 enum {
 112         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 113         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 114         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 115         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 116         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 117         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 118         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 119         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 120         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 121         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 122         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 123         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 124         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 125         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 126         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 127         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 128         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 129         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 130         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 131         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 132         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 133         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 134         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 135         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 136         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 137         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 138         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 139         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 140         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 141         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 142         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 143         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 144         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 145         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 146         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 147         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 148         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 149         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 150         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 151         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 152         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 153         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 154         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 155         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 156         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 157         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 158         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 159         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 160         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 161         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 162         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 163         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 164         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 165         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 166         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 167         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 168         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 169         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 170         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 171         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 172         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 173         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 174         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 175         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 176         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 177         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 178         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 179         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 180         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 181         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 182         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 183         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 184         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 185         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 186         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 188         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 189         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 191         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 192         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 193         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 194         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 195         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 196         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 197         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 198         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 199         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 200         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 201         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 202         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 203         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 204         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 205         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 206         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 207         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 208         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 209         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 210         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 211         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 212         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 213         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 214         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 215         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 216         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 217         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 218         MLX5_CMD_OP_NOP                           = 0x80d,
 219         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 220         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 221         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 222         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 223         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 224         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 225         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 226         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 227         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 228         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 229         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 230         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 231         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 232         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 233         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 234         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 235         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 236         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 237         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 238         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 239         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 240         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 241         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 242         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 243         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 244         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 245         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 246         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 247         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 248         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 249         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 250         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 251         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 252         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 253         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 254         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 255         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 256         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 257         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 258         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 259         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 260         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 261         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 262         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 263         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 264         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 265         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 266         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 267         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 268         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 269         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 270         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 271         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 272         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 273         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 274         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 275         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 276         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 277         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 278         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 279         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 280         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 281         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 282         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 283         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 284         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 285         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 286         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 287         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 288         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 289         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 290         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 291         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 292         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 293         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 294         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 295         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 296         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 297         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 298         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 299         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 300         MLX5_CMD_OP_MAX
 301 };
 302
 303 /* Valid range for general commands that don't work over an object */
 304 enum {
 305         MLX5_CMD_OP_GENERAL_START = 0xb00,
 306         MLX5_CMD_OP_GENERAL_END = 0xd00,
 307 };
 308
 309 struct mlx5_ifc_flow_table_fields_supported_bits {
 310         u8         outer_dmac[0x1];
 311         u8         outer_smac[0x1];
 312         u8         outer_ether_type[0x1];
 313         u8         outer_ip_version[0x1];
 314         u8         outer_first_prio[0x1];
 315         u8         outer_first_cfi[0x1];
 316         u8         outer_first_vid[0x1];
 317         u8         outer_ipv4_ttl[0x1];
 318         u8         outer_second_prio[0x1];
 319         u8         outer_second_cfi[0x1];
 320         u8         outer_second_vid[0x1];
 321         u8         reserved_at_b[0x1];
 322         u8         outer_sip[0x1];
 323         u8         outer_dip[0x1];
 324         u8         outer_frag[0x1];
 325         u8         outer_ip_protocol[0x1];
 326         u8         outer_ip_ecn[0x1];
 327         u8         outer_ip_dscp[0x1];
 328         u8         outer_udp_sport[0x1];
 329         u8         outer_udp_dport[0x1];
 330         u8         outer_tcp_sport[0x1];
 331         u8         outer_tcp_dport[0x1];
 332         u8         outer_tcp_flags[0x1];
 333         u8         outer_gre_protocol[0x1];
 334         u8         outer_gre_key[0x1];
 335         u8         outer_vxlan_vni[0x1];
 336         u8         outer_geneve_vni[0x1];
 337         u8         outer_geneve_oam[0x1];
 338         u8         outer_geneve_protocol_type[0x1];
 339         u8         outer_geneve_opt_len[0x1];
 340         u8         reserved_at_1e[0x1];
 341         u8         source_eswitch_port[0x1];
 342
 343         u8         inner_dmac[0x1];
 344         u8         inner_smac[0x1];
 345         u8         inner_ether_type[0x1];
 346         u8         inner_ip_version[0x1];
 347         u8         inner_first_prio[0x1];
 348         u8         inner_first_cfi[0x1];
 349         u8         inner_first_vid[0x1];
 350         u8         reserved_at_27[0x1];
 351         u8         inner_second_prio[0x1];
 352         u8         inner_second_cfi[0x1];
 353         u8         inner_second_vid[0x1];
 354         u8         reserved_at_2b[0x1];
 355         u8         inner_sip[0x1];
 356         u8         inner_dip[0x1];
 357         u8         inner_frag[0x1];
 358         u8         inner_ip_protocol[0x1];
 359         u8         inner_ip_ecn[0x1];
 360         u8         inner_ip_dscp[0x1];
 361         u8         inner_udp_sport[0x1];
 362         u8         inner_udp_dport[0x1];
 363         u8         inner_tcp_sport[0x1];
 364         u8         inner_tcp_dport[0x1];
 365         u8         inner_tcp_flags[0x1];
 366         u8         reserved_at_37[0x9];
 367
 368         u8         geneve_tlv_option_0_data[0x1];
 369         u8         reserved_at_41[0x4];
 370         u8         outer_first_mpls_over_udp[0x4];
 371         u8         outer_first_mpls_over_gre[0x4];
 372         u8         inner_first_mpls[0x4];
 373         u8         outer_first_mpls[0x4];
 374         u8         reserved_at_55[0x2];
 375         u8         outer_esp_spi[0x1];
 376         u8         reserved_at_58[0x2];
 377         u8         bth_dst_qp[0x1];
 378         u8         reserved_at_5b[0x5];
 379
 380         u8         reserved_at_60[0x18];
 381         u8         metadata_reg_c_7[0x1];
 382         u8         metadata_reg_c_6[0x1];
 383         u8         metadata_reg_c_5[0x1];
 384         u8         metadata_reg_c_4[0x1];
 385         u8         metadata_reg_c_3[0x1];
 386         u8         metadata_reg_c_2[0x1];
 387         u8         metadata_reg_c_1[0x1];
 388         u8         metadata_reg_c_0[0x1];
 389 };
 390
 391 struct mlx5_ifc_flow_table_prop_layout_bits {
 392         u8         ft_support[0x1];
 393         u8         reserved_at_1[0x1];
 394         u8         flow_counter[0x1];
 395         u8         flow_modify_en[0x1];
 396         u8         modify_root[0x1];
 397         u8         identified_miss_table_mode[0x1];
 398         u8         flow_table_modify[0x1];
 399         u8         reformat[0x1];
 400         u8         decap[0x1];
 401         u8         reserved_at_9[0x1];
 402         u8         pop_vlan[0x1];
 403         u8         push_vlan[0x1];
 404         u8         reserved_at_c[0x1];
 405         u8         pop_vlan_2[0x1];
 406         u8         push_vlan_2[0x1];
 407         u8         reformat_and_vlan_action[0x1];
 408         u8         reserved_at_10[0x1];
 409         u8         sw_owner[0x1];
 410         u8         reformat_l3_tunnel_to_l2[0x1];
 411         u8         reformat_l2_to_l3_tunnel[0x1];
 412         u8         reformat_and_modify_action[0x1];
 413         u8         ignore_flow_level[0x1];
 414         u8         reserved_at_16[0x1];
 415         u8         table_miss_action_domain[0x1];
 416         u8         termination_table[0x1];
 417         u8         reformat_and_fwd_to_table[0x1];
 418         u8         reserved_at_1a[0x6];
 419         u8         termination_table_raw_traffic[0x1];
 420         u8         reserved_at_21[0x1];
 421         u8         log_max_ft_size[0x6];
 422         u8         log_max_modify_header_context[0x8];
 423         u8         max_modify_header_actions[0x8];
 424         u8         max_ft_level[0x8];
 425
 426         u8         reserved_at_40[0x20];
 427
 428         u8         reserved_at_60[0x18];
 429         u8         log_max_ft_num[0x8];
 430
 431         u8         reserved_at_80[0x18];
 432         u8         log_max_destination[0x8];
 433
 434         u8         log_max_flow_counter[0x8];
 435         u8         reserved_at_a8[0x10];
 436         u8         log_max_flow[0x8];
 437
 438         u8         reserved_at_c0[0x40];
 439
 440         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 441
 442         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 443 };
 444
 445 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 446         u8         send[0x1];
 447         u8         receive[0x1];
 448         u8         write[0x1];
 449         u8         read[0x1];
 450         u8         atomic[0x1];
 451         u8         srq_receive[0x1];
 452         u8         reserved_at_6[0x1a];
 453 };
 454
 455 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 456         u8         smac_47_16[0x20];
 457
 458         u8         smac_15_0[0x10];
 459         u8         ethertype[0x10];
 460
 461         u8         dmac_47_16[0x20];
 462
 463         u8         dmac_15_0[0x10];
 464         u8         first_prio[0x3];
 465         u8         first_cfi[0x1];
 466         u8         first_vid[0xc];
 467
 468         u8         ip_protocol[0x8];
 469         u8         ip_dscp[0x6];
 470         u8         ip_ecn[0x2];
 471         u8         cvlan_tag[0x1];
 472         u8         svlan_tag[0x1];
 473         u8         frag[0x1];
 474         u8         ip_version[0x4];
 475         u8         tcp_flags[0x9];
 476
 477         u8         tcp_sport[0x10];
 478         u8         tcp_dport[0x10];
 479
 480         u8         reserved_at_c0[0x18];
 481         u8         ttl_hoplimit[0x8];
 482
 483         u8         udp_sport[0x10];
 484         u8         udp_dport[0x10];
 485
 486         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 487
 488         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 489 };
 490
 491 struct mlx5_ifc_nvgre_key_bits {
 492         u8 hi[0x18];
 493         u8 lo[0x8];
 494 };
 495
 496 union mlx5_ifc_gre_key_bits {
 497         struct mlx5_ifc_nvgre_key_bits nvgre;
 498         u8 key[0x20];
 499 };
 500
 501 struct mlx5_ifc_fte_match_set_misc_bits {
 502         u8         gre_c_present[0x1];
 503         u8         reserved_at_1[0x1];
 504         u8         gre_k_present[0x1];
 505         u8         gre_s_present[0x1];
 506         u8         source_vhca_port[0x4];
 507         u8         source_sqn[0x18];
 508
 509         u8         source_eswitch_owner_vhca_id[0x10];
 510         u8         source_port[0x10];
 511
 512         u8         outer_second_prio[0x3];
 513         u8         outer_second_cfi[0x1];
 514         u8         outer_second_vid[0xc];
 515         u8         inner_second_prio[0x3];
 516         u8         inner_second_cfi[0x1];
 517         u8         inner_second_vid[0xc];
 518
 519         u8         outer_second_cvlan_tag[0x1];
 520         u8         inner_second_cvlan_tag[0x1];
 521         u8         outer_second_svlan_tag[0x1];
 522         u8         inner_second_svlan_tag[0x1];
 523         u8         reserved_at_64[0xc];
 524         u8         gre_protocol[0x10];
 525
 526         union mlx5_ifc_gre_key_bits gre_key;
 527
 528         u8         vxlan_vni[0x18];
 529         u8         reserved_at_b8[0x8];
 530
 531         u8         geneve_vni[0x18];
 532         u8         reserved_at_d8[0x7];
 533         u8         geneve_oam[0x1];
 534
 535         u8         reserved_at_e0[0xc];
 536         u8         outer_ipv6_flow_label[0x14];
 537
 538         u8         reserved_at_100[0xc];
 539         u8         inner_ipv6_flow_label[0x14];
 540
 541         u8         reserved_at_120[0xa];
 542         u8         geneve_opt_len[0x6];
 543         u8         geneve_protocol_type[0x10];
 544
 545         u8         reserved_at_140[0x8];
 546         u8         bth_dst_qp[0x18];
 547         u8         reserved_at_160[0x20];
 548         u8         outer_esp_spi[0x20];
 549         u8         reserved_at_1a0[0x60];
 550 };
 551
 552 struct mlx5_ifc_fte_match_mpls_bits {
 553         u8         mpls_label[0x14];
 554         u8         mpls_exp[0x3];
 555         u8         mpls_s_bos[0x1];
 556         u8         mpls_ttl[0x8];
 557 };
 558
 559 struct mlx5_ifc_fte_match_set_misc2_bits {
 560         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 561
 562         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 563
 564         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 565
 566         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 567
 568         u8         metadata_reg_c_7[0x20];
 569
 570         u8         metadata_reg_c_6[0x20];
 571
 572         u8         metadata_reg_c_5[0x20];
 573
 574         u8         metadata_reg_c_4[0x20];
 575
 576         u8         metadata_reg_c_3[0x20];
 577
 578         u8         metadata_reg_c_2[0x20];
 579
 580         u8         metadata_reg_c_1[0x20];
 581
 582         u8         metadata_reg_c_0[0x20];
 583
 584         u8         metadata_reg_a[0x20];
 585
 586         u8         metadata_reg_b[0x20];
 587
 588         u8         reserved_at_1c0[0x40];
 589 };
 590
 591 struct mlx5_ifc_fte_match_set_misc3_bits {
 592         u8         inner_tcp_seq_num[0x20];
 593
 594         u8         outer_tcp_seq_num[0x20];
 595
 596         u8         inner_tcp_ack_num[0x20];
 597
 598         u8         outer_tcp_ack_num[0x20];
 599
 600         u8         reserved_at_80[0x8];
 601         u8         outer_vxlan_gpe_vni[0x18];
 602
 603         u8         outer_vxlan_gpe_next_protocol[0x8];
 604         u8         outer_vxlan_gpe_flags[0x8];
 605         u8         reserved_at_b0[0x10];
 606
 607         u8         icmp_header_data[0x20];
 608
 609         u8         icmpv6_header_data[0x20];
 610
 611         u8         icmp_type[0x8];
 612         u8         icmp_code[0x8];
 613         u8         icmpv6_type[0x8];
 614         u8         icmpv6_code[0x8];
 615
 616         u8         geneve_tlv_option_0_data[0x20];
 617
 618         u8         reserved_at_140[0xc0];
 619 };
 620
 621 struct mlx5_ifc_cmd_pas_bits {
 622         u8         pa_h[0x20];
 623
 624         u8         pa_l[0x14];
 625         u8         reserved_at_34[0xc];
 626 };
 627
 628 struct mlx5_ifc_uint64_bits {
 629         u8         hi[0x20];
 630
 631         u8         lo[0x20];
 632 };
 633
 634 enum {
 635         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 636         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 637         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 638         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 639         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 640         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 641         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 642         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 643         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 644         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 645 };
 646
 647 struct mlx5_ifc_ads_bits {
 648         u8         fl[0x1];
 649         u8         free_ar[0x1];
 650         u8         reserved_at_2[0xe];
 651         u8         pkey_index[0x10];
 652
 653         u8         reserved_at_20[0x8];
 654         u8         grh[0x1];
 655         u8         mlid[0x7];
 656         u8         rlid[0x10];
 657
 658         u8         ack_timeout[0x5];
 659         u8         reserved_at_45[0x3];
 660         u8         src_addr_index[0x8];
 661         u8         reserved_at_50[0x4];
 662         u8         stat_rate[0x4];
 663         u8         hop_limit[0x8];
 664
 665         u8         reserved_at_60[0x4];
 666         u8         tclass[0x8];
 667         u8         flow_label[0x14];
 668
 669         u8         rgid_rip[16][0x8];
 670
 671         u8         reserved_at_100[0x4];
 672         u8         f_dscp[0x1];
 673         u8         f_ecn[0x1];
 674         u8         reserved_at_106[0x1];
 675         u8         f_eth_prio[0x1];
 676         u8         ecn[0x2];
 677         u8         dscp[0x6];
 678         u8         udp_sport[0x10];
 679
 680         u8         dei_cfi[0x1];
 681         u8         eth_prio[0x3];
 682         u8         sl[0x4];
 683         u8         vhca_port_num[0x8];
 684         u8         rmac_47_32[0x10];
 685
 686         u8         rmac_31_0[0x20];
 687 };
 688
 689 struct mlx5_ifc_flow_table_nic_cap_bits {
 690         u8         nic_rx_multi_path_tirs[0x1];
 691         u8         nic_rx_multi_path_tirs_fts[0x1];
 692         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 693         u8         reserved_at_3[0x4];
 694         u8         sw_owner_reformat_supported[0x1];
 695         u8         reserved_at_8[0x18];
 696
 697         u8         encap_general_header[0x1];
 698         u8         reserved_at_21[0xa];
 699         u8         log_max_packet_reformat_context[0x5];
 700         u8         reserved_at_30[0x6];
 701         u8         max_encap_header_size[0xa];
 702         u8         reserved_at_40[0x1c0];
 703
 704         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 705
 706         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 707
 708         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 709
 710         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 711
 712         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 713
 714         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 715
 716         u8         reserved_at_e00[0x1200];
 717
 718         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 719
 720         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 721
 722         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 723
 724         u8         reserved_at_20c0[0x5f40];
 725 };
 726
 727 enum {
 728         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 729         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 730         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 731         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 732         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 733         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 734         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 735         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 736 };
 737
 738 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 739         u8      fdb_to_vport_reg_c_id[0x8];
 740         u8      reserved_at_8[0xd];
 741         u8      fdb_modify_header_fwd_to_table[0x1];
 742         u8      reserved_at_16[0x1];
 743         u8      flow_source[0x1];
 744         u8      reserved_at_18[0x2];
 745         u8      multi_fdb_encap[0x1];
 746         u8      egress_acl_forward_to_vport[0x1];
 747         u8      fdb_multi_path_to_table[0x1];
 748         u8      reserved_at_1d[0x3];
 749
 750         u8      reserved_at_20[0x1e0];
 751
 752         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 753
 754         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 755
 756         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 757
 758         u8      reserved_at_800[0x1000];
 759
 760         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 761
 762         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 763
 764         u8      sw_steering_uplink_icm_address_rx[0x40];
 765
 766         u8      sw_steering_uplink_icm_address_tx[0x40];
 767
 768         u8      reserved_at_1900[0x6700];
 769 };
 770
 771 enum {
 772         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 773         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 774 };
 775
 776 struct mlx5_ifc_e_switch_cap_bits {
 777         u8         vport_svlan_strip[0x1];
 778         u8         vport_cvlan_strip[0x1];
 779         u8         vport_svlan_insert[0x1];
 780         u8         vport_cvlan_insert_if_not_exist[0x1];
 781         u8         vport_cvlan_insert_overwrite[0x1];
 782         u8         reserved_at_5[0x3];
 783         u8         esw_uplink_ingress_acl[0x1];
 784         u8         reserved_at_9[0x10];
 785         u8         esw_functions_changed[0x1];
 786         u8         reserved_at_1a[0x1];
 787         u8         ecpf_vport_exists[0x1];
 788         u8         counter_eswitch_affinity[0x1];
 789         u8         merged_eswitch[0x1];
 790         u8         nic_vport_node_guid_modify[0x1];
 791         u8         nic_vport_port_guid_modify[0x1];
 792
 793         u8         vxlan_encap_decap[0x1];
 794         u8         nvgre_encap_decap[0x1];
 795         u8         reserved_at_22[0x1];
 796         u8         log_max_fdb_encap_uplink[0x5];
 797         u8         reserved_at_21[0x3];
 798         u8         log_max_packet_reformat_context[0x5];
 799         u8         reserved_2b[0x6];
 800         u8         max_encap_header_size[0xa];
 801
 802         u8         reserved_at_40[0xb];
 803         u8         log_max_esw_sf[0x5];
 804         u8         esw_sf_base_id[0x10];
 805
 806         u8         reserved_at_60[0x7a0];
 807
 808 };
 809
 810 struct mlx5_ifc_qos_cap_bits {
 811         u8         packet_pacing[0x1];
 812         u8         esw_scheduling[0x1];
 813         u8         esw_bw_share[0x1];
 814         u8         esw_rate_limit[0x1];
 815         u8         reserved_at_4[0x1];
 816         u8         packet_pacing_burst_bound[0x1];
 817         u8         packet_pacing_typical_size[0x1];
 818         u8         reserved_at_7[0x4];
 819         u8         packet_pacing_uid[0x1];
 820         u8         reserved_at_c[0x14];
 821
 822         u8         reserved_at_20[0x20];
 823
 824         u8         packet_pacing_max_rate[0x20];
 825
 826         u8         packet_pacing_min_rate[0x20];
 827
 828         u8         reserved_at_80[0x10];
 829         u8         packet_pacing_rate_table_size[0x10];
 830
 831         u8         esw_element_type[0x10];
 832         u8         esw_tsar_type[0x10];
 833
 834         u8         reserved_at_c0[0x10];
 835         u8         max_qos_para_vport[0x10];
 836
 837         u8         max_tsar_bw_share[0x20];
 838
 839         u8         reserved_at_100[0x700];
 840 };
 841
 842 struct mlx5_ifc_debug_cap_bits {
 843         u8         core_dump_general[0x1];
 844         u8         core_dump_qp[0x1];
 845         u8         reserved_at_2[0x7];
 846         u8         resource_dump[0x1];
 847         u8         reserved_at_a[0x16];
 848
 849         u8         reserved_at_20[0x2];
 850         u8         stall_detect[0x1];
 851         u8         reserved_at_23[0x1d];
 852
 853         u8         reserved_at_40[0x7c0];
 854 };
 855
 856 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 857         u8         csum_cap[0x1];
 858         u8         vlan_cap[0x1];
 859         u8         lro_cap[0x1];
 860         u8         lro_psh_flag[0x1];
 861         u8         lro_time_stamp[0x1];
 862         u8         reserved_at_5[0x2];
 863         u8         wqe_vlan_insert[0x1];
 864         u8         self_lb_en_modifiable[0x1];
 865         u8         reserved_at_9[0x2];
 866         u8         max_lso_cap[0x5];
 867         u8         multi_pkt_send_wqe[0x2];
 868         u8         wqe_inline_mode[0x2];
 869         u8         rss_ind_tbl_cap[0x4];
 870         u8         reg_umr_sq[0x1];
 871         u8         scatter_fcs[0x1];
 872         u8         enhanced_multi_pkt_send_wqe[0x1];
 873         u8         tunnel_lso_const_out_ip_id[0x1];
 874         u8         reserved_at_1c[0x2];
 875         u8         tunnel_stateless_gre[0x1];
 876         u8         tunnel_stateless_vxlan[0x1];
 877
 878         u8         swp[0x1];
 879         u8         swp_csum[0x1];
 880         u8         swp_lso[0x1];
 881         u8         cqe_checksum_full[0x1];
 882         u8         tunnel_stateless_geneve_tx[0x1];
 883         u8         tunnel_stateless_mpls_over_udp[0x1];
 884         u8         tunnel_stateless_mpls_over_gre[0x1];
 885         u8         tunnel_stateless_vxlan_gpe[0x1];
 886         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 887         u8         tunnel_stateless_ip_over_ip[0x1];
 888         u8         reserved_at_2a[0x6];
 889         u8         max_vxlan_udp_ports[0x8];
 890         u8         reserved_at_38[0x6];
 891         u8         max_geneve_opt_len[0x1];
 892         u8         tunnel_stateless_geneve_rx[0x1];
 893
 894         u8         reserved_at_40[0x10];
 895         u8         lro_min_mss_size[0x10];
 896
 897         u8         reserved_at_60[0x120];
 898
 899         u8         lro_timer_supported_periods[4][0x20];
 900
 901         u8         reserved_at_200[0x600];
 902 };
 903
 904 struct mlx5_ifc_roce_cap_bits {
 905         u8         roce_apm[0x1];
 906         u8         reserved_at_1[0x1f];
 907
 908         u8         reserved_at_20[0x60];
 909
 910         u8         reserved_at_80[0xc];
 911         u8         l3_type[0x4];
 912         u8         reserved_at_90[0x8];
 913         u8         roce_version[0x8];
 914
 915         u8         reserved_at_a0[0x10];
 916         u8         r_roce_dest_udp_port[0x10];
 917
 918         u8         r_roce_max_src_udp_port[0x10];
 919         u8         r_roce_min_src_udp_port[0x10];
 920
 921         u8         reserved_at_e0[0x10];
 922         u8         roce_address_table_size[0x10];
 923
 924         u8         reserved_at_100[0x700];
 925 };
 926
 927 struct mlx5_ifc_sync_steering_in_bits {
 928         u8         opcode[0x10];
 929         u8         uid[0x10];
 930
 931         u8         reserved_at_20[0x10];
 932         u8         op_mod[0x10];
 933
 934         u8         reserved_at_40[0xc0];
 935 };
 936
 937 struct mlx5_ifc_sync_steering_out_bits {
 938         u8         status[0x8];
 939         u8         reserved_at_8[0x18];
 940
 941         u8         syndrome[0x20];
 942
 943         u8         reserved_at_40[0x40];
 944 };
 945
 946 struct mlx5_ifc_device_mem_cap_bits {
 947         u8         memic[0x1];
 948         u8         reserved_at_1[0x1f];
 949
 950         u8         reserved_at_20[0xb];
 951         u8         log_min_memic_alloc_size[0x5];
 952         u8         reserved_at_30[0x8];
 953         u8         log_max_memic_addr_alignment[0x8];
 954
 955         u8         memic_bar_start_addr[0x40];
 956
 957         u8         memic_bar_size[0x20];
 958
 959         u8         max_memic_size[0x20];
 960
 961         u8         steering_sw_icm_start_address[0x40];
 962
 963         u8         reserved_at_100[0x8];
 964         u8         log_header_modify_sw_icm_size[0x8];
 965         u8         reserved_at_110[0x2];
 966         u8         log_sw_icm_alloc_granularity[0x6];
 967         u8         log_steering_sw_icm_size[0x8];
 968
 969         u8         reserved_at_120[0x20];
 970
 971         u8         header_modify_sw_icm_start_address[0x40];
 972
 973         u8         reserved_at_180[0x680];
 974 };
 975
 976 struct mlx5_ifc_device_event_cap_bits {
 977         u8         user_affiliated_events[4][0x40];
 978
 979         u8         user_unaffiliated_events[4][0x40];
 980 };
 981
 982 struct mlx5_ifc_device_virtio_emulation_cap_bits {
 983         u8         reserved_at_0[0x20];
 984
 985         u8         reserved_at_20[0x13];
 986         u8         log_doorbell_stride[0x5];
 987         u8         reserved_at_38[0x3];
 988         u8         log_doorbell_bar_size[0x5];
 989
 990         u8         doorbell_bar_offset[0x40];
 991
 992         u8         reserved_at_80[0x780];
 993 };
 994
 995 enum {
 996         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 997         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 998         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 999         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1000         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1001         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1002         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1003         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1004         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1005 };
1006
1007 enum {
1008         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1009         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1010         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1011         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1012         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1013         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1014         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1015         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1016         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1017 };
1018
1019 struct mlx5_ifc_atomic_caps_bits {
1020         u8         reserved_at_0[0x40];
1021
1022         u8         atomic_req_8B_endianness_mode[0x2];
1023         u8         reserved_at_42[0x4];
1024         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1025
1026         u8         reserved_at_47[0x19];
1027
1028         u8         reserved_at_60[0x20];
1029
1030         u8         reserved_at_80[0x10];
1031         u8         atomic_operations[0x10];
1032
1033         u8         reserved_at_a0[0x10];
1034         u8         atomic_size_qp[0x10];
1035
1036         u8         reserved_at_c0[0x10];
1037         u8         atomic_size_dc[0x10];
1038
1039         u8         reserved_at_e0[0x720];
1040 };
1041
1042 struct mlx5_ifc_odp_cap_bits {
1043         u8         reserved_at_0[0x40];
1044
1045         u8         sig[0x1];
1046         u8         reserved_at_41[0x1f];
1047
1048         u8         reserved_at_60[0x20];
1049
1050         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1051
1052         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1053
1054         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1055
1056         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1057
1058         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1059
1060         u8         reserved_at_120[0x6E0];
1061 };
1062
1063 struct mlx5_ifc_calc_op {
1064         u8        reserved_at_0[0x10];
1065         u8        reserved_at_10[0x9];
1066         u8        op_swap_endianness[0x1];
1067         u8        op_min[0x1];
1068         u8        op_xor[0x1];
1069         u8        op_or[0x1];
1070         u8        op_and[0x1];
1071         u8        op_max[0x1];
1072         u8        op_add[0x1];
1073 };
1074
1075 struct mlx5_ifc_vector_calc_cap_bits {
1076         u8         calc_matrix[0x1];
1077         u8         reserved_at_1[0x1f];
1078         u8         reserved_at_20[0x8];
1079         u8         max_vec_count[0x8];
1080         u8         reserved_at_30[0xd];
1081         u8         max_chunk_size[0x3];
1082         struct mlx5_ifc_calc_op calc0;
1083         struct mlx5_ifc_calc_op calc1;
1084         struct mlx5_ifc_calc_op calc2;
1085         struct mlx5_ifc_calc_op calc3;
1086
1087         u8         reserved_at_c0[0x720];
1088 };
1089
1090 struct mlx5_ifc_tls_cap_bits {
1091         u8         tls_1_2_aes_gcm_128[0x1];
1092         u8         tls_1_3_aes_gcm_128[0x1];
1093         u8         tls_1_2_aes_gcm_256[0x1];
1094         u8         tls_1_3_aes_gcm_256[0x1];
1095         u8         reserved_at_4[0x1c];
1096
1097         u8         reserved_at_20[0x7e0];
1098 };
1099
1100 enum {
1101         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1102         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1103         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1104         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1105 };
1106
1107 enum {
1108         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1109         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1110 };
1111
1112 enum {
1113         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1114         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1115         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1116         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1117         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1118 };
1119
1120 enum {
1121         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1122         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1123         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1124         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1125         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1126         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1127 };
1128
1129 enum {
1130         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1131         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1132 };
1133
1134 enum {
1135         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1136         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1137         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1138 };
1139
1140 enum {
1141         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1142         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1143 };
1144
1145 enum {
1146         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1147         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1148         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1149 };
1150
1151 enum {
1152         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1153         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1154         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1155         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1156 };
1157
1158 enum {
1159         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1160         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1161 };
1162
1163 #define MLX5_FC_BULK_SIZE_FACTOR 128
1164
1165 enum mlx5_fc_bulk_alloc_bitmask {
1166         MLX5_FC_BULK_128   = (1 << 0),
1167         MLX5_FC_BULK_256   = (1 << 1),
1168         MLX5_FC_BULK_512   = (1 << 2),
1169         MLX5_FC_BULK_1024  = (1 << 3),
1170         MLX5_FC_BULK_2048  = (1 << 4),
1171         MLX5_FC_BULK_4096  = (1 << 5),
1172         MLX5_FC_BULK_8192  = (1 << 6),
1173         MLX5_FC_BULK_16384 = (1 << 7),
1174 };
1175
1176 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1177
1178 struct mlx5_ifc_cmd_hca_cap_bits {
1179         u8         reserved_at_0[0x30];
1180         u8         vhca_id[0x10];
1181
1182         u8         reserved_at_40[0x40];
1183
1184         u8         log_max_srq_sz[0x8];
1185         u8         log_max_qp_sz[0x8];
1186         u8         event_cap[0x1];
1187         u8         reserved_at_91[0x7];
1188         u8         prio_tag_required[0x1];
1189         u8         reserved_at_99[0x2];
1190         u8         log_max_qp[0x5];
1191
1192         u8         reserved_at_a0[0xb];
1193         u8         log_max_srq[0x5];
1194         u8         reserved_at_b0[0x10];
1195
1196         u8         max_sgl_for_optimized_performance[0x8];
1197         u8         log_max_cq_sz[0x8];
1198         u8         reserved_at_d0[0xb];
1199         u8         log_max_cq[0x5];
1200
1201         u8         log_max_eq_sz[0x8];
1202         u8         relaxed_ordering_write[0x1];
1203         u8         relaxed_ordering_read[0x1];
1204         u8         log_max_mkey[0x6];
1205         u8         reserved_at_f0[0x8];
1206         u8         dump_fill_mkey[0x1];
1207         u8         reserved_at_f9[0x2];
1208         u8         fast_teardown[0x1];
1209         u8         log_max_eq[0x4];
1210
1211         u8         max_indirection[0x8];
1212         u8         fixed_buffer_size[0x1];
1213         u8         log_max_mrw_sz[0x7];
1214         u8         force_teardown[0x1];
1215         u8         reserved_at_111[0x1];
1216         u8         log_max_bsf_list_size[0x6];
1217         u8         umr_extended_translation_offset[0x1];
1218         u8         null_mkey[0x1];
1219         u8         log_max_klm_list_size[0x6];
1220
1221         u8         reserved_at_120[0xa];
1222         u8         log_max_ra_req_dc[0x6];
1223         u8         reserved_at_130[0xa];
1224         u8         log_max_ra_res_dc[0x6];
1225
1226         u8         reserved_at_140[0x9];
1227         u8         roce_accl[0x1];
1228         u8         log_max_ra_req_qp[0x6];
1229         u8         reserved_at_150[0xa];
1230         u8         log_max_ra_res_qp[0x6];
1231
1232         u8         end_pad[0x1];
1233         u8         cc_query_allowed[0x1];
1234         u8         cc_modify_allowed[0x1];
1235         u8         start_pad[0x1];
1236         u8         cache_line_128byte[0x1];
1237         u8         reserved_at_165[0x4];
1238         u8         rts2rts_qp_counters_set_id[0x1];
1239         u8         reserved_at_16a[0x2];
1240         u8         vnic_env_int_rq_oob[0x1];
1241         u8         sbcam_reg[0x1];
1242         u8         reserved_at_16e[0x1];
1243         u8         qcam_reg[0x1];
1244         u8         gid_table_size[0x10];
1245
1246         u8         out_of_seq_cnt[0x1];
1247         u8         vport_counters[0x1];
1248         u8         retransmission_q_counters[0x1];
1249         u8         debug[0x1];
1250         u8         modify_rq_counter_set_id[0x1];
1251         u8         rq_delay_drop[0x1];
1252         u8         max_qp_cnt[0xa];
1253         u8         pkey_table_size[0x10];
1254
1255         u8         vport_group_manager[0x1];
1256         u8         vhca_group_manager[0x1];
1257         u8         ib_virt[0x1];
1258         u8         eth_virt[0x1];
1259         u8         vnic_env_queue_counters[0x1];
1260         u8         ets[0x1];
1261         u8         nic_flow_table[0x1];
1262         u8         eswitch_manager[0x1];
1263         u8         device_memory[0x1];
1264         u8         mcam_reg[0x1];
1265         u8         pcam_reg[0x1];
1266         u8         local_ca_ack_delay[0x5];
1267         u8         port_module_event[0x1];
1268         u8         enhanced_error_q_counters[0x1];
1269         u8         ports_check[0x1];
1270         u8         reserved_at_1b3[0x1];
1271         u8         disable_link_up[0x1];
1272         u8         beacon_led[0x1];
1273         u8         port_type[0x2];
1274         u8         num_ports[0x8];
1275
1276         u8         reserved_at_1c0[0x1];
1277         u8         pps[0x1];
1278         u8         pps_modify[0x1];
1279         u8         log_max_msg[0x5];
1280         u8         reserved_at_1c8[0x4];
1281         u8         max_tc[0x4];
1282         u8         temp_warn_event[0x1];
1283         u8         dcbx[0x1];
1284         u8         general_notification_event[0x1];
1285         u8         reserved_at_1d3[0x2];
1286         u8         fpga[0x1];
1287         u8         rol_s[0x1];
1288         u8         rol_g[0x1];
1289         u8         reserved_at_1d8[0x1];
1290         u8         wol_s[0x1];
1291         u8         wol_g[0x1];
1292         u8         wol_a[0x1];
1293         u8         wol_b[0x1];
1294         u8         wol_m[0x1];
1295         u8         wol_u[0x1];
1296         u8         wol_p[0x1];
1297
1298         u8         stat_rate_support[0x10];
1299         u8         reserved_at_1f0[0xc];
1300         u8         cqe_version[0x4];
1301
1302         u8         compact_address_vector[0x1];
1303         u8         striding_rq[0x1];
1304         u8         reserved_at_202[0x1];
1305         u8         ipoib_enhanced_offloads[0x1];
1306         u8         ipoib_basic_offloads[0x1];
1307         u8         reserved_at_205[0x1];
1308         u8         repeated_block_disabled[0x1];
1309         u8         umr_modify_entity_size_disabled[0x1];
1310         u8         umr_modify_atomic_disabled[0x1];
1311         u8         umr_indirect_mkey_disabled[0x1];
1312         u8         umr_fence[0x2];
1313         u8         dc_req_scat_data_cqe[0x1];
1314         u8         reserved_at_20d[0x2];
1315         u8         drain_sigerr[0x1];
1316         u8         cmdif_checksum[0x2];
1317         u8         sigerr_cqe[0x1];
1318         u8         reserved_at_213[0x1];
1319         u8         wq_signature[0x1];
1320         u8         sctr_data_cqe[0x1];
1321         u8         reserved_at_216[0x1];
1322         u8         sho[0x1];
1323         u8         tph[0x1];
1324         u8         rf[0x1];
1325         u8         dct[0x1];
1326         u8         qos[0x1];
1327         u8         eth_net_offloads[0x1];
1328         u8         roce[0x1];
1329         u8         atomic[0x1];
1330         u8         reserved_at_21f[0x1];
1331
1332         u8         cq_oi[0x1];
1333         u8         cq_resize[0x1];
1334         u8         cq_moderation[0x1];
1335         u8         reserved_at_223[0x3];
1336         u8         cq_eq_remap[0x1];
1337         u8         pg[0x1];
1338         u8         block_lb_mc[0x1];
1339         u8         reserved_at_229[0x1];
1340         u8         scqe_break_moderation[0x1];
1341         u8         cq_period_start_from_cqe[0x1];
1342         u8         cd[0x1];
1343         u8         reserved_at_22d[0x1];
1344         u8         apm[0x1];
1345         u8         vector_calc[0x1];
1346         u8         umr_ptr_rlky[0x1];
1347         u8         imaicl[0x1];
1348         u8         qp_packet_based[0x1];
1349         u8         reserved_at_233[0x3];
1350         u8         qkv[0x1];
1351         u8         pkv[0x1];
1352         u8         set_deth_sqpn[0x1];
1353         u8         reserved_at_239[0x3];
1354         u8         xrc[0x1];
1355         u8         ud[0x1];
1356         u8         uc[0x1];
1357         u8         rc[0x1];
1358
1359         u8         uar_4k[0x1];
1360         u8         reserved_at_241[0x9];
1361         u8         uar_sz[0x6];
1362         u8         reserved_at_250[0x8];
1363         u8         log_pg_sz[0x8];
1364
1365         u8         bf[0x1];
1366         u8         driver_version[0x1];
1367         u8         pad_tx_eth_packet[0x1];
1368         u8         reserved_at_263[0x8];
1369         u8         log_bf_reg_size[0x5];
1370
1371         u8         reserved_at_270[0x8];
1372         u8         lag_tx_port_affinity[0x1];
1373         u8         reserved_at_279[0x2];
1374         u8         lag_master[0x1];
1375         u8         num_lag_ports[0x4];
1376
1377         u8         reserved_at_280[0x10];
1378         u8         max_wqe_sz_sq[0x10];
1379
1380         u8         reserved_at_2a0[0x10];
1381         u8         max_wqe_sz_rq[0x10];
1382
1383         u8         max_flow_counter_31_16[0x10];
1384         u8         max_wqe_sz_sq_dc[0x10];
1385
1386         u8         reserved_at_2e0[0x7];
1387         u8         max_qp_mcg[0x19];
1388
1389         u8         reserved_at_300[0x10];
1390         u8         flow_counter_bulk_alloc[0x8];
1391         u8         log_max_mcg[0x8];
1392
1393         u8         reserved_at_320[0x3];
1394         u8         log_max_transport_domain[0x5];
1395         u8         reserved_at_328[0x3];
1396         u8         log_max_pd[0x5];
1397         u8         reserved_at_330[0xb];
1398         u8         log_max_xrcd[0x5];
1399
1400         u8         nic_receive_steering_discard[0x1];
1401         u8         receive_discard_vport_down[0x1];
1402         u8         transmit_discard_vport_down[0x1];
1403         u8         reserved_at_343[0x5];
1404         u8         log_max_flow_counter_bulk[0x8];
1405         u8         max_flow_counter_15_0[0x10];
1406
1407
1408         u8         reserved_at_360[0x3];
1409         u8         log_max_rq[0x5];
1410         u8         reserved_at_368[0x3];
1411         u8         log_max_sq[0x5];
1412         u8         reserved_at_370[0x3];
1413         u8         log_max_tir[0x5];
1414         u8         reserved_at_378[0x3];
1415         u8         log_max_tis[0x5];
1416
1417         u8         basic_cyclic_rcv_wqe[0x1];
1418         u8         reserved_at_381[0x2];
1419         u8         log_max_rmp[0x5];
1420         u8         reserved_at_388[0x3];
1421         u8         log_max_rqt[0x5];
1422         u8         reserved_at_390[0x3];
1423         u8         log_max_rqt_size[0x5];
1424         u8         reserved_at_398[0x3];
1425         u8         log_max_tis_per_sq[0x5];
1426
1427         u8         ext_stride_num_range[0x1];
1428         u8         reserved_at_3a1[0x2];
1429         u8         log_max_stride_sz_rq[0x5];
1430         u8         reserved_at_3a8[0x3];
1431         u8         log_min_stride_sz_rq[0x5];
1432         u8         reserved_at_3b0[0x3];
1433         u8         log_max_stride_sz_sq[0x5];
1434         u8         reserved_at_3b8[0x3];
1435         u8         log_min_stride_sz_sq[0x5];
1436
1437         u8         hairpin[0x1];
1438         u8         reserved_at_3c1[0x2];
1439         u8         log_max_hairpin_queues[0x5];
1440         u8         reserved_at_3c8[0x3];
1441         u8         log_max_hairpin_wq_data_sz[0x5];
1442         u8         reserved_at_3d0[0x3];
1443         u8         log_max_hairpin_num_packets[0x5];
1444         u8         reserved_at_3d8[0x3];
1445         u8         log_max_wq_sz[0x5];
1446
1447         u8         nic_vport_change_event[0x1];
1448         u8         disable_local_lb_uc[0x1];
1449         u8         disable_local_lb_mc[0x1];
1450         u8         log_min_hairpin_wq_data_sz[0x5];
1451         u8         reserved_at_3e8[0x3];
1452         u8         log_max_vlan_list[0x5];
1453         u8         reserved_at_3f0[0x3];
1454         u8         log_max_current_mc_list[0x5];
1455         u8         reserved_at_3f8[0x3];
1456         u8         log_max_current_uc_list[0x5];
1457
1458         u8         general_obj_types[0x40];
1459
1460         u8         reserved_at_440[0x20];
1461
1462         u8         reserved_at_460[0x3];
1463         u8         log_max_uctx[0x5];
1464         u8         reserved_at_468[0x3];
1465         u8         log_max_umem[0x5];
1466         u8         max_num_eqs[0x10];
1467
1468         u8         reserved_at_480[0x1];
1469         u8         tls_tx[0x1];
1470         u8         reserved_at_482[0x1];
1471         u8         log_max_l2_table[0x5];
1472         u8         reserved_at_488[0x8];
1473         u8         log_uar_page_sz[0x10];
1474
1475         u8         reserved_at_4a0[0x20];
1476         u8         device_frequency_mhz[0x20];
1477         u8         device_frequency_khz[0x20];
1478
1479         u8         reserved_at_500[0x20];
1480         u8         num_of_uars_per_page[0x20];
1481
1482         u8         flex_parser_protocols[0x20];
1483
1484         u8         max_geneve_tlv_options[0x8];
1485         u8         reserved_at_568[0x3];
1486         u8         max_geneve_tlv_option_data_len[0x5];
1487         u8         reserved_at_570[0x10];
1488
1489         u8         reserved_at_580[0x33];
1490         u8         log_max_dek[0x5];
1491         u8         reserved_at_5b8[0x4];
1492         u8         mini_cqe_resp_stride_index[0x1];
1493         u8         cqe_128_always[0x1];
1494         u8         cqe_compression_128[0x1];
1495         u8         cqe_compression[0x1];
1496
1497         u8         cqe_compression_timeout[0x10];
1498         u8         cqe_compression_max_num[0x10];
1499
1500         u8         reserved_at_5e0[0x10];
1501         u8         tag_matching[0x1];
1502         u8         rndv_offload_rc[0x1];
1503         u8         rndv_offload_dc[0x1];
1504         u8         log_tag_matching_list_sz[0x5];
1505         u8         reserved_at_5f8[0x3];
1506         u8         log_max_xrq[0x5];
1507
1508         u8         affiliate_nic_vport_criteria[0x8];
1509         u8         native_port_num[0x8];
1510         u8         num_vhca_ports[0x8];
1511         u8         reserved_at_618[0x6];
1512         u8         sw_owner_id[0x1];
1513         u8         reserved_at_61f[0x1];
1514
1515         u8         max_num_of_monitor_counters[0x10];
1516         u8         num_ppcnt_monitor_counters[0x10];
1517
1518         u8         reserved_at_640[0x10];
1519         u8         num_q_monitor_counters[0x10];
1520
1521         u8         reserved_at_660[0x20];
1522
1523         u8         sf[0x1];
1524         u8         sf_set_partition[0x1];
1525         u8         reserved_at_682[0x1];
1526         u8         log_max_sf[0x5];
1527         u8         reserved_at_688[0x8];
1528         u8         log_min_sf_size[0x8];
1529         u8         max_num_sf_partitions[0x8];
1530
1531         u8         uctx_cap[0x20];
1532
1533         u8         reserved_at_6c0[0x4];
1534         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1535         u8         flex_parser_id_icmp_dw1[0x4];
1536         u8         flex_parser_id_icmp_dw0[0x4];
1537         u8         flex_parser_id_icmpv6_dw1[0x4];
1538         u8         flex_parser_id_icmpv6_dw0[0x4];
1539         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1540         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1541
1542         u8         reserved_at_6e0[0x10];
1543         u8         sf_base_id[0x10];
1544
1545         u8         reserved_at_700[0x80];
1546         u8         vhca_tunnel_commands[0x40];
1547         u8         reserved_at_7c0[0x40];
1548 };
1549
1550 enum mlx5_flow_destination_type {
1551         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1552         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1553         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1554
1555         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1556         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1557         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1558 };
1559
1560 enum mlx5_flow_table_miss_action {
1561         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1562         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1563         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1564 };
1565
1566 struct mlx5_ifc_dest_format_struct_bits {
1567         u8         destination_type[0x8];
1568         u8         destination_id[0x18];
1569
1570         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1571         u8         packet_reformat[0x1];
1572         u8         reserved_at_22[0xe];
1573         u8         destination_eswitch_owner_vhca_id[0x10];
1574 };
1575
1576 struct mlx5_ifc_flow_counter_list_bits {
1577         u8         flow_counter_id[0x20];
1578
1579         u8         reserved_at_20[0x20];
1580 };
1581
1582 struct mlx5_ifc_extended_dest_format_bits {
1583         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1584
1585         u8         packet_reformat_id[0x20];
1586
1587         u8         reserved_at_60[0x20];
1588 };
1589
1590 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1591         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1592         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1593 };
1594
1595 struct mlx5_ifc_fte_match_param_bits {
1596         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1597
1598         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1599
1600         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1601
1602         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1603
1604         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1605
1606         u8         reserved_at_a00[0x600];
1607 };
1608
1609 enum {
1610         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1611         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1612         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1613         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1614         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1615 };
1616
1617 struct mlx5_ifc_rx_hash_field_select_bits {
1618         u8         l3_prot_type[0x1];
1619         u8         l4_prot_type[0x1];
1620         u8         selected_fields[0x1e];
1621 };
1622
1623 enum {
1624         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1625         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1626 };
1627
1628 enum {
1629         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1630         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1631 };
1632
1633 struct mlx5_ifc_wq_bits {
1634         u8         wq_type[0x4];
1635         u8         wq_signature[0x1];
1636         u8         end_padding_mode[0x2];
1637         u8         cd_slave[0x1];
1638         u8         reserved_at_8[0x18];
1639
1640         u8         hds_skip_first_sge[0x1];
1641         u8         log2_hds_buf_size[0x3];
1642         u8         reserved_at_24[0x7];
1643         u8         page_offset[0x5];
1644         u8         lwm[0x10];
1645
1646         u8         reserved_at_40[0x8];
1647         u8         pd[0x18];
1648
1649         u8         reserved_at_60[0x8];
1650         u8         uar_page[0x18];
1651
1652         u8         dbr_addr[0x40];
1653
1654         u8         hw_counter[0x20];
1655
1656         u8         sw_counter[0x20];
1657
1658         u8         reserved_at_100[0xc];
1659         u8         log_wq_stride[0x4];
1660         u8         reserved_at_110[0x3];
1661         u8         log_wq_pg_sz[0x5];
1662         u8         reserved_at_118[0x3];
1663         u8         log_wq_sz[0x5];
1664
1665         u8         dbr_umem_valid[0x1];
1666         u8         wq_umem_valid[0x1];
1667         u8         reserved_at_122[0x1];
1668         u8         log_hairpin_num_packets[0x5];
1669         u8         reserved_at_128[0x3];
1670         u8         log_hairpin_data_sz[0x5];
1671
1672         u8         reserved_at_130[0x4];
1673         u8         log_wqe_num_of_strides[0x4];
1674         u8         two_byte_shift_en[0x1];
1675         u8         reserved_at_139[0x4];
1676         u8         log_wqe_stride_size[0x3];
1677
1678         u8         reserved_at_140[0x4c0];
1679
1680         struct mlx5_ifc_cmd_pas_bits pas[0];
1681 };
1682
1683 struct mlx5_ifc_rq_num_bits {
1684         u8         reserved_at_0[0x8];
1685         u8         rq_num[0x18];
1686 };
1687
1688 struct mlx5_ifc_mac_address_layout_bits {
1689         u8         reserved_at_0[0x10];
1690         u8         mac_addr_47_32[0x10];
1691
1692         u8         mac_addr_31_0[0x20];
1693 };
1694
1695 struct mlx5_ifc_vlan_layout_bits {
1696         u8         reserved_at_0[0x14];
1697         u8         vlan[0x0c];
1698
1699         u8         reserved_at_20[0x20];
1700 };
1701
1702 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1703         u8         reserved_at_0[0xa0];
1704
1705         u8         min_time_between_cnps[0x20];
1706
1707         u8         reserved_at_c0[0x12];
1708         u8         cnp_dscp[0x6];
1709         u8         reserved_at_d8[0x4];
1710         u8         cnp_prio_mode[0x1];
1711         u8         cnp_802p_prio[0x3];
1712
1713         u8         reserved_at_e0[0x720];
1714 };
1715
1716 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1717         u8         reserved_at_0[0x60];
1718
1719         u8         reserved_at_60[0x4];
1720         u8         clamp_tgt_rate[0x1];
1721         u8         reserved_at_65[0x3];
1722         u8         clamp_tgt_rate_after_time_inc[0x1];
1723         u8         reserved_at_69[0x17];
1724
1725         u8         reserved_at_80[0x20];
1726
1727         u8         rpg_time_reset[0x20];
1728
1729         u8         rpg_byte_reset[0x20];
1730
1731         u8         rpg_threshold[0x20];
1732
1733         u8         rpg_max_rate[0x20];
1734
1735         u8         rpg_ai_rate[0x20];
1736
1737         u8         rpg_hai_rate[0x20];
1738
1739         u8         rpg_gd[0x20];
1740
1741         u8         rpg_min_dec_fac[0x20];
1742
1743         u8         rpg_min_rate[0x20];
1744
1745         u8         reserved_at_1c0[0xe0];
1746
1747         u8         rate_to_set_on_first_cnp[0x20];
1748
1749         u8         dce_tcp_g[0x20];
1750
1751         u8         dce_tcp_rtt[0x20];
1752
1753         u8         rate_reduce_monitor_period[0x20];
1754
1755         u8         reserved_at_320[0x20];
1756
1757         u8         initial_alpha_value[0x20];
1758
1759         u8         reserved_at_360[0x4a0];
1760 };
1761
1762 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1763         u8         reserved_at_0[0x80];
1764
1765         u8         rppp_max_rps[0x20];
1766
1767         u8         rpg_time_reset[0x20];
1768
1769         u8         rpg_byte_reset[0x20];
1770
1771         u8         rpg_threshold[0x20];
1772
1773         u8         rpg_max_rate[0x20];
1774
1775         u8         rpg_ai_rate[0x20];
1776
1777         u8         rpg_hai_rate[0x20];
1778
1779         u8         rpg_gd[0x20];
1780
1781         u8         rpg_min_dec_fac[0x20];
1782
1783         u8         rpg_min_rate[0x20];
1784
1785         u8         reserved_at_1c0[0x640];
1786 };
1787
1788 enum {
1789         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1790         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1791         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1792 };
1793
1794 struct mlx5_ifc_resize_field_select_bits {
1795         u8         resize_field_select[0x20];
1796 };
1797
1798 struct mlx5_ifc_resource_dump_bits {
1799         u8         more_dump[0x1];
1800         u8         inline_dump[0x1];
1801         u8         reserved_at_2[0xa];
1802         u8         seq_num[0x4];
1803         u8         segment_type[0x10];
1804
1805         u8         reserved_at_20[0x10];
1806         u8         vhca_id[0x10];
1807
1808         u8         index1[0x20];
1809
1810         u8         index2[0x20];
1811
1812         u8         num_of_obj1[0x10];
1813         u8         num_of_obj2[0x10];
1814
1815         u8         reserved_at_a0[0x20];
1816
1817         u8         device_opaque[0x40];
1818
1819         u8         mkey[0x20];
1820
1821         u8         size[0x20];
1822
1823         u8         address[0x40];
1824
1825         u8         inline_data[52][0x20];
1826 };
1827
1828 struct mlx5_ifc_resource_dump_menu_record_bits {
1829         u8         reserved_at_0[0x4];
1830         u8         num_of_obj2_supports_active[0x1];
1831         u8         num_of_obj2_supports_all[0x1];
1832         u8         must_have_num_of_obj2[0x1];
1833         u8         support_num_of_obj2[0x1];
1834         u8         num_of_obj1_supports_active[0x1];
1835         u8         num_of_obj1_supports_all[0x1];
1836         u8         must_have_num_of_obj1[0x1];
1837         u8         support_num_of_obj1[0x1];
1838         u8         must_have_index2[0x1];
1839         u8         support_index2[0x1];
1840         u8         must_have_index1[0x1];
1841         u8         support_index1[0x1];
1842         u8         segment_type[0x10];
1843
1844         u8         segment_name[4][0x20];
1845
1846         u8         index1_name[4][0x20];
1847
1848         u8         index2_name[4][0x20];
1849 };
1850
1851 struct mlx5_ifc_resource_dump_segment_header_bits {
1852         u8         length_dw[0x10];
1853         u8         segment_type[0x10];
1854 };
1855
1856 struct mlx5_ifc_resource_dump_command_segment_bits {
1857         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1858
1859         u8         segment_called[0x10];
1860         u8         vhca_id[0x10];
1861
1862         u8         index1[0x20];
1863
1864         u8         index2[0x20];
1865
1866         u8         num_of_obj1[0x10];
1867         u8         num_of_obj2[0x10];
1868 };
1869
1870 struct mlx5_ifc_resource_dump_error_segment_bits {
1871         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1872
1873         u8         reserved_at_20[0x10];
1874         u8         syndrome_id[0x10];
1875
1876         u8         reserved_at_40[0x40];
1877
1878         u8         error[8][0x20];
1879 };
1880
1881 struct mlx5_ifc_resource_dump_info_segment_bits {
1882         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1883
1884         u8         reserved_at_20[0x18];
1885         u8         dump_version[0x8];
1886
1887         u8         hw_version[0x20];
1888
1889         u8         fw_version[0x20];
1890 };
1891
1892 struct mlx5_ifc_resource_dump_menu_segment_bits {
1893         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1894
1895         u8         reserved_at_20[0x10];
1896         u8         num_of_records[0x10];
1897
1898         struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1899 };
1900
1901 struct mlx5_ifc_resource_dump_resource_segment_bits {
1902         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1903
1904         u8         reserved_at_20[0x20];
1905
1906         u8         index1[0x20];
1907
1908         u8         index2[0x20];
1909
1910         u8         payload[0][0x20];
1911 };
1912
1913 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1914         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1915 };
1916
1917 struct mlx5_ifc_menu_resource_dump_response_bits {
1918         struct mlx5_ifc_resource_dump_info_segment_bits info;
1919         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1920         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1921         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1922 };
1923
1924 enum {
1925         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1926         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1927         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1928         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1929 };
1930
1931 struct mlx5_ifc_modify_field_select_bits {
1932         u8         modify_field_select[0x20];
1933 };
1934
1935 struct mlx5_ifc_field_select_r_roce_np_bits {
1936         u8         field_select_r_roce_np[0x20];
1937 };
1938
1939 struct mlx5_ifc_field_select_r_roce_rp_bits {
1940         u8         field_select_r_roce_rp[0x20];
1941 };
1942
1943 enum {
1944         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1945         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1946         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1947         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1948         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1949         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1950         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1951         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1952         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1953         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1954 };
1955
1956 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1957         u8         field_select_8021qaurp[0x20];
1958 };
1959
1960 struct mlx5_ifc_phys_layer_cntrs_bits {
1961         u8         time_since_last_clear_high[0x20];
1962
1963         u8         time_since_last_clear_low[0x20];
1964
1965         u8         symbol_errors_high[0x20];
1966
1967         u8         symbol_errors_low[0x20];
1968
1969         u8         sync_headers_errors_high[0x20];
1970
1971         u8         sync_headers_errors_low[0x20];
1972
1973         u8         edpl_bip_errors_lane0_high[0x20];
1974
1975         u8         edpl_bip_errors_lane0_low[0x20];
1976
1977         u8         edpl_bip_errors_lane1_high[0x20];
1978
1979         u8         edpl_bip_errors_lane1_low[0x20];
1980
1981         u8         edpl_bip_errors_lane2_high[0x20];
1982
1983         u8         edpl_bip_errors_lane2_low[0x20];
1984
1985         u8         edpl_bip_errors_lane3_high[0x20];
1986
1987         u8         edpl_bip_errors_lane3_low[0x20];
1988
1989         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1990
1991         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1992
1993         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1994
1995         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1996
1997         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1998
1999         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2000
2001         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2002
2003         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2004
2005         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2006
2007         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2008
2009         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2010
2011         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2012
2013         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2014
2015         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2016
2017         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2018
2019         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2020
2021         u8         rs_fec_corrected_blocks_high[0x20];
2022
2023         u8         rs_fec_corrected_blocks_low[0x20];
2024
2025         u8         rs_fec_uncorrectable_blocks_high[0x20];
2026
2027         u8         rs_fec_uncorrectable_blocks_low[0x20];
2028
2029         u8         rs_fec_no_errors_blocks_high[0x20];
2030
2031         u8         rs_fec_no_errors_blocks_low[0x20];
2032
2033         u8         rs_fec_single_error_blocks_high[0x20];
2034
2035         u8         rs_fec_single_error_blocks_low[0x20];
2036
2037         u8         rs_fec_corrected_symbols_total_high[0x20];
2038
2039         u8         rs_fec_corrected_symbols_total_low[0x20];
2040
2041         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2042
2043         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2044
2045         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2046
2047         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2048
2049         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2050
2051         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2052
2053         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2054
2055         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2056
2057         u8         link_down_events[0x20];
2058
2059         u8         successful_recovery_events[0x20];
2060
2061         u8         reserved_at_640[0x180];
2062 };
2063
2064 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2065         u8         time_since_last_clear_high[0x20];
2066
2067         u8         time_since_last_clear_low[0x20];
2068
2069         u8         phy_received_bits_high[0x20];
2070
2071         u8         phy_received_bits_low[0x20];
2072
2073         u8         phy_symbol_errors_high[0x20];
2074
2075         u8         phy_symbol_errors_low[0x20];
2076
2077         u8         phy_corrected_bits_high[0x20];
2078
2079         u8         phy_corrected_bits_low[0x20];
2080
2081         u8         phy_corrected_bits_lane0_high[0x20];
2082
2083         u8         phy_corrected_bits_lane0_low[0x20];
2084
2085         u8         phy_corrected_bits_lane1_high[0x20];
2086
2087         u8         phy_corrected_bits_lane1_low[0x20];
2088
2089         u8         phy_corrected_bits_lane2_high[0x20];
2090
2091         u8         phy_corrected_bits_lane2_low[0x20];
2092
2093         u8         phy_corrected_bits_lane3_high[0x20];
2094
2095         u8         phy_corrected_bits_lane3_low[0x20];
2096
2097         u8         reserved_at_200[0x5c0];
2098 };
2099
2100 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2101         u8         symbol_error_counter[0x10];
2102
2103         u8         link_error_recovery_counter[0x8];
2104
2105         u8         link_downed_counter[0x8];
2106
2107         u8         port_rcv_errors[0x10];
2108
2109         u8         port_rcv_remote_physical_errors[0x10];
2110
2111         u8         port_rcv_switch_relay_errors[0x10];
2112
2113         u8         port_xmit_discards[0x10];
2114
2115         u8         port_xmit_constraint_errors[0x8];
2116
2117         u8         port_rcv_constraint_errors[0x8];
2118
2119         u8         reserved_at_70[0x8];
2120
2121         u8         link_overrun_errors[0x8];
2122
2123         u8         reserved_at_80[0x10];
2124
2125         u8         vl_15_dropped[0x10];
2126
2127         u8         reserved_at_a0[0x80];
2128
2129         u8         port_xmit_wait[0x20];
2130 };
2131
2132 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2133         u8         transmit_queue_high[0x20];
2134
2135         u8         transmit_queue_low[0x20];
2136
2137         u8         no_buffer_discard_uc_high[0x20];
2138
2139         u8         no_buffer_discard_uc_low[0x20];
2140
2141         u8         reserved_at_80[0x740];
2142 };
2143
2144 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2145         u8         wred_discard_high[0x20];
2146
2147         u8         wred_discard_low[0x20];
2148
2149         u8         ecn_marked_tc_high[0x20];
2150
2151         u8         ecn_marked_tc_low[0x20];
2152
2153         u8         reserved_at_80[0x740];
2154 };
2155
2156 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2157         u8         rx_octets_high[0x20];
2158
2159         u8         rx_octets_low[0x20];
2160
2161         u8         reserved_at_40[0xc0];
2162
2163         u8         rx_frames_high[0x20];
2164
2165         u8         rx_frames_low[0x20];
2166
2167         u8         tx_octets_high[0x20];
2168
2169         u8         tx_octets_low[0x20];
2170
2171         u8         reserved_at_180[0xc0];
2172
2173         u8         tx_frames_high[0x20];
2174
2175         u8         tx_frames_low[0x20];
2176
2177         u8         rx_pause_high[0x20];
2178
2179         u8         rx_pause_low[0x20];
2180
2181         u8         rx_pause_duration_high[0x20];
2182
2183         u8         rx_pause_duration_low[0x20];
2184
2185         u8         tx_pause_high[0x20];
2186
2187         u8         tx_pause_low[0x20];
2188
2189         u8         tx_pause_duration_high[0x20];
2190
2191         u8         tx_pause_duration_low[0x20];
2192
2193         u8         rx_pause_transition_high[0x20];
2194
2195         u8         rx_pause_transition_low[0x20];
2196
2197         u8         rx_discards_high[0x20];
2198
2199         u8         rx_discards_low[0x20];
2200
2201         u8         device_stall_minor_watermark_cnt_high[0x20];
2202
2203         u8         device_stall_minor_watermark_cnt_low[0x20];
2204
2205         u8         device_stall_critical_watermark_cnt_high[0x20];
2206
2207         u8         device_stall_critical_watermark_cnt_low[0x20];
2208
2209         u8         reserved_at_480[0x340];
2210 };
2211
2212 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2213         u8         port_transmit_wait_high[0x20];
2214
2215         u8         port_transmit_wait_low[0x20];
2216
2217         u8         reserved_at_40[0x100];
2218
2219         u8         rx_buffer_almost_full_high[0x20];
2220
2221         u8         rx_buffer_almost_full_low[0x20];
2222
2223         u8         rx_buffer_full_high[0x20];
2224
2225         u8         rx_buffer_full_low[0x20];
2226
2227         u8         rx_icrc_encapsulated_high[0x20];
2228
2229         u8         rx_icrc_encapsulated_low[0x20];
2230
2231         u8         reserved_at_200[0x5c0];
2232 };
2233
2234 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2235         u8         dot3stats_alignment_errors_high[0x20];
2236
2237         u8         dot3stats_alignment_errors_low[0x20];
2238
2239         u8         dot3stats_fcs_errors_high[0x20];
2240
2241         u8         dot3stats_fcs_errors_low[0x20];
2242
2243         u8         dot3stats_single_collision_frames_high[0x20];
2244
2245         u8         dot3stats_single_collision_frames_low[0x20];
2246
2247         u8         dot3stats_multiple_collision_frames_high[0x20];
2248
2249         u8         dot3stats_multiple_collision_frames_low[0x20];
2250
2251         u8         dot3stats_sqe_test_errors_high[0x20];
2252
2253         u8         dot3stats_sqe_test_errors_low[0x20];
2254
2255         u8         dot3stats_deferred_transmissions_high[0x20];
2256
2257         u8         dot3stats_deferred_transmissions_low[0x20];
2258
2259         u8         dot3stats_late_collisions_high[0x20];
2260
2261         u8         dot3stats_late_collisions_low[0x20];
2262
2263         u8         dot3stats_excessive_collisions_high[0x20];
2264
2265         u8         dot3stats_excessive_collisions_low[0x20];
2266
2267         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2268
2269         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2270
2271         u8         dot3stats_carrier_sense_errors_high[0x20];
2272
2273         u8         dot3stats_carrier_sense_errors_low[0x20];
2274
2275         u8         dot3stats_frame_too_longs_high[0x20];
2276
2277         u8         dot3stats_frame_too_longs_low[0x20];
2278
2279         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2280
2281         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2282
2283         u8         dot3stats_symbol_errors_high[0x20];
2284
2285         u8         dot3stats_symbol_errors_low[0x20];
2286
2287         u8         dot3control_in_unknown_opcodes_high[0x20];
2288
2289         u8         dot3control_in_unknown_opcodes_low[0x20];
2290
2291         u8         dot3in_pause_frames_high[0x20];
2292
2293         u8         dot3in_pause_frames_low[0x20];
2294
2295         u8         dot3out_pause_frames_high[0x20];
2296
2297         u8         dot3out_pause_frames_low[0x20];
2298
2299         u8         reserved_at_400[0x3c0];
2300 };
2301
2302 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2303         u8         ether_stats_drop_events_high[0x20];
2304
2305         u8         ether_stats_drop_events_low[0x20];
2306
2307         u8         ether_stats_octets_high[0x20];
2308
2309         u8         ether_stats_octets_low[0x20];
2310
2311         u8         ether_stats_pkts_high[0x20];
2312
2313         u8         ether_stats_pkts_low[0x20];
2314
2315         u8         ether_stats_broadcast_pkts_high[0x20];
2316
2317         u8         ether_stats_broadcast_pkts_low[0x20];
2318
2319         u8         ether_stats_multicast_pkts_high[0x20];
2320
2321         u8         ether_stats_multicast_pkts_low[0x20];
2322
2323         u8         ether_stats_crc_align_errors_high[0x20];
2324
2325         u8         ether_stats_crc_align_errors_low[0x20];
2326
2327         u8         ether_stats_undersize_pkts_high[0x20];
2328
2329         u8         ether_stats_undersize_pkts_low[0x20];
2330
2331         u8         ether_stats_oversize_pkts_high[0x20];
2332
2333         u8         ether_stats_oversize_pkts_low[0x20];
2334
2335         u8         ether_stats_fragments_high[0x20];
2336
2337         u8         ether_stats_fragments_low[0x20];
2338
2339         u8         ether_stats_jabbers_high[0x20];
2340
2341         u8         ether_stats_jabbers_low[0x20];
2342
2343         u8         ether_stats_collisions_high[0x20];
2344
2345         u8         ether_stats_collisions_low[0x20];
2346
2347         u8         ether_stats_pkts64octets_high[0x20];
2348
2349         u8         ether_stats_pkts64octets_low[0x20];
2350
2351         u8         ether_stats_pkts65to127octets_high[0x20];
2352
2353         u8         ether_stats_pkts65to127octets_low[0x20];
2354
2355         u8         ether_stats_pkts128to255octets_high[0x20];
2356
2357         u8         ether_stats_pkts128to255octets_low[0x20];
2358
2359         u8         ether_stats_pkts256to511octets_high[0x20];
2360
2361         u8         ether_stats_pkts256to511octets_low[0x20];
2362
2363         u8         ether_stats_pkts512to1023octets_high[0x20];
2364
2365         u8         ether_stats_pkts512to1023octets_low[0x20];
2366
2367         u8         ether_stats_pkts1024to1518octets_high[0x20];
2368
2369         u8         ether_stats_pkts1024to1518octets_low[0x20];
2370
2371         u8         ether_stats_pkts1519to2047octets_high[0x20];
2372
2373         u8         ether_stats_pkts1519to2047octets_low[0x20];
2374
2375         u8         ether_stats_pkts2048to4095octets_high[0x20];
2376
2377         u8         ether_stats_pkts2048to4095octets_low[0x20];
2378
2379         u8         ether_stats_pkts4096to8191octets_high[0x20];
2380
2381         u8         ether_stats_pkts4096to8191octets_low[0x20];
2382
2383         u8         ether_stats_pkts8192to10239octets_high[0x20];
2384
2385         u8         ether_stats_pkts8192to10239octets_low[0x20];
2386
2387         u8         reserved_at_540[0x280];
2388 };
2389
2390 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2391         u8         if_in_octets_high[0x20];
2392
2393         u8         if_in_octets_low[0x20];
2394
2395         u8         if_in_ucast_pkts_high[0x20];
2396
2397         u8         if_in_ucast_pkts_low[0x20];
2398
2399         u8         if_in_discards_high[0x20];
2400
2401         u8         if_in_discards_low[0x20];
2402
2403         u8         if_in_errors_high[0x20];
2404
2405         u8         if_in_errors_low[0x20];
2406
2407         u8         if_in_unknown_protos_high[0x20];
2408
2409         u8         if_in_unknown_protos_low[0x20];
2410
2411         u8         if_out_octets_high[0x20];
2412
2413         u8         if_out_octets_low[0x20];
2414
2415         u8         if_out_ucast_pkts_high[0x20];
2416
2417         u8         if_out_ucast_pkts_low[0x20];
2418
2419         u8         if_out_discards_high[0x20];
2420
2421         u8         if_out_discards_low[0x20];
2422
2423         u8         if_out_errors_high[0x20];
2424
2425         u8         if_out_errors_low[0x20];
2426
2427         u8         if_in_multicast_pkts_high[0x20];
2428
2429         u8         if_in_multicast_pkts_low[0x20];
2430
2431         u8         if_in_broadcast_pkts_high[0x20];
2432
2433         u8         if_in_broadcast_pkts_low[0x20];
2434
2435         u8         if_out_multicast_pkts_high[0x20];
2436
2437         u8         if_out_multicast_pkts_low[0x20];
2438
2439         u8         if_out_broadcast_pkts_high[0x20];
2440
2441         u8         if_out_broadcast_pkts_low[0x20];
2442
2443         u8         reserved_at_340[0x480];
2444 };
2445
2446 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2447         u8         a_frames_transmitted_ok_high[0x20];
2448
2449         u8         a_frames_transmitted_ok_low[0x20];
2450
2451         u8         a_frames_received_ok_high[0x20];
2452
2453         u8         a_frames_received_ok_low[0x20];
2454
2455         u8         a_frame_check_sequence_errors_high[0x20];
2456
2457         u8         a_frame_check_sequence_errors_low[0x20];
2458
2459         u8         a_alignment_errors_high[0x20];
2460
2461         u8         a_alignment_errors_low[0x20];
2462
2463         u8         a_octets_transmitted_ok_high[0x20];
2464
2465         u8         a_octets_transmitted_ok_low[0x20];
2466
2467         u8         a_octets_received_ok_high[0x20];
2468
2469         u8         a_octets_received_ok_low[0x20];
2470
2471         u8         a_multicast_frames_xmitted_ok_high[0x20];
2472
2473         u8         a_multicast_frames_xmitted_ok_low[0x20];
2474
2475         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2476
2477         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2478
2479         u8         a_multicast_frames_received_ok_high[0x20];
2480
2481         u8         a_multicast_frames_received_ok_low[0x20];
2482
2483         u8         a_broadcast_frames_received_ok_high[0x20];
2484
2485         u8         a_broadcast_frames_received_ok_low[0x20];
2486
2487         u8         a_in_range_length_errors_high[0x20];
2488
2489         u8         a_in_range_length_errors_low[0x20];
2490
2491         u8         a_out_of_range_length_field_high[0x20];
2492
2493         u8         a_out_of_range_length_field_low[0x20];
2494
2495         u8         a_frame_too_long_errors_high[0x20];
2496
2497         u8         a_frame_too_long_errors_low[0x20];
2498
2499         u8         a_symbol_error_during_carrier_high[0x20];
2500
2501         u8         a_symbol_error_during_carrier_low[0x20];
2502
2503         u8         a_mac_control_frames_transmitted_high[0x20];
2504
2505         u8         a_mac_control_frames_transmitted_low[0x20];
2506
2507         u8         a_mac_control_frames_received_high[0x20];
2508
2509         u8         a_mac_control_frames_received_low[0x20];
2510
2511         u8         a_unsupported_opcodes_received_high[0x20];
2512
2513         u8         a_unsupported_opcodes_received_low[0x20];
2514
2515         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2516
2517         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2518
2519         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2520
2521         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2522
2523         u8         reserved_at_4c0[0x300];
2524 };
2525
2526 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2527         u8         life_time_counter_high[0x20];
2528
2529         u8         life_time_counter_low[0x20];
2530
2531         u8         rx_errors[0x20];
2532
2533         u8         tx_errors[0x20];
2534
2535         u8         l0_to_recovery_eieos[0x20];
2536
2537         u8         l0_to_recovery_ts[0x20];
2538
2539         u8         l0_to_recovery_framing[0x20];
2540
2541         u8         l0_to_recovery_retrain[0x20];
2542
2543         u8         crc_error_dllp[0x20];
2544
2545         u8         crc_error_tlp[0x20];
2546
2547         u8         tx_overflow_buffer_pkt_high[0x20];
2548
2549         u8         tx_overflow_buffer_pkt_low[0x20];
2550
2551         u8         outbound_stalled_reads[0x20];
2552
2553         u8         outbound_stalled_writes[0x20];
2554
2555         u8         outbound_stalled_reads_events[0x20];
2556
2557         u8         outbound_stalled_writes_events[0x20];
2558
2559         u8         reserved_at_200[0x5c0];
2560 };
2561
2562 struct mlx5_ifc_cmd_inter_comp_event_bits {
2563         u8         command_completion_vector[0x20];
2564
2565         u8         reserved_at_20[0xc0];
2566 };
2567
2568 struct mlx5_ifc_stall_vl_event_bits {
2569         u8         reserved_at_0[0x18];
2570         u8         port_num[0x1];
2571         u8         reserved_at_19[0x3];
2572         u8         vl[0x4];
2573
2574         u8         reserved_at_20[0xa0];
2575 };
2576
2577 struct mlx5_ifc_db_bf_congestion_event_bits {
2578         u8         event_subtype[0x8];
2579         u8         reserved_at_8[0x8];
2580         u8         congestion_level[0x8];
2581         u8         reserved_at_18[0x8];
2582
2583         u8         reserved_at_20[0xa0];
2584 };
2585
2586 struct mlx5_ifc_gpio_event_bits {
2587         u8         reserved_at_0[0x60];
2588
2589         u8         gpio_event_hi[0x20];
2590
2591         u8         gpio_event_lo[0x20];
2592
2593         u8         reserved_at_a0[0x40];
2594 };
2595
2596 struct mlx5_ifc_port_state_change_event_bits {
2597         u8         reserved_at_0[0x40];
2598
2599         u8         port_num[0x4];
2600         u8         reserved_at_44[0x1c];
2601
2602         u8         reserved_at_60[0x80];
2603 };
2604
2605 struct mlx5_ifc_dropped_packet_logged_bits {
2606         u8         reserved_at_0[0xe0];
2607 };
2608
2609 enum {
2610         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2611         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2612 };
2613
2614 struct mlx5_ifc_cq_error_bits {
2615         u8         reserved_at_0[0x8];
2616         u8         cqn[0x18];
2617
2618         u8         reserved_at_20[0x20];
2619
2620         u8         reserved_at_40[0x18];
2621         u8         syndrome[0x8];
2622
2623         u8         reserved_at_60[0x80];
2624 };
2625
2626 struct mlx5_ifc_rdma_page_fault_event_bits {
2627         u8         bytes_committed[0x20];
2628
2629         u8         r_key[0x20];
2630
2631         u8         reserved_at_40[0x10];
2632         u8         packet_len[0x10];
2633
2634         u8         rdma_op_len[0x20];
2635
2636         u8         rdma_va[0x40];
2637
2638         u8         reserved_at_c0[0x5];
2639         u8         rdma[0x1];
2640         u8         write[0x1];
2641         u8         requestor[0x1];
2642         u8         qp_number[0x18];
2643 };
2644
2645 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2646         u8         bytes_committed[0x20];
2647
2648         u8         reserved_at_20[0x10];
2649         u8         wqe_index[0x10];
2650
2651         u8         reserved_at_40[0x10];
2652         u8         len[0x10];
2653
2654         u8         reserved_at_60[0x60];
2655
2656         u8         reserved_at_c0[0x5];
2657         u8         rdma[0x1];
2658         u8         write_read[0x1];
2659         u8         requestor[0x1];
2660         u8         qpn[0x18];
2661 };
2662
2663 struct mlx5_ifc_qp_events_bits {
2664         u8         reserved_at_0[0xa0];
2665
2666         u8         type[0x8];
2667         u8         reserved_at_a8[0x18];
2668
2669         u8         reserved_at_c0[0x8];
2670         u8         qpn_rqn_sqn[0x18];
2671 };
2672
2673 struct mlx5_ifc_dct_events_bits {
2674         u8         reserved_at_0[0xc0];
2675
2676         u8         reserved_at_c0[0x8];
2677         u8         dct_number[0x18];
2678 };
2679
2680 struct mlx5_ifc_comp_event_bits {
2681         u8         reserved_at_0[0xc0];
2682
2683         u8         reserved_at_c0[0x8];
2684         u8         cq_number[0x18];
2685 };
2686
2687 enum {
2688         MLX5_QPC_STATE_RST        = 0x0,
2689         MLX5_QPC_STATE_INIT       = 0x1,
2690         MLX5_QPC_STATE_RTR        = 0x2,
2691         MLX5_QPC_STATE_RTS        = 0x3,
2692         MLX5_QPC_STATE_SQER       = 0x4,
2693         MLX5_QPC_STATE_ERR        = 0x6,
2694         MLX5_QPC_STATE_SQD        = 0x7,
2695         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2696 };
2697
2698 enum {
2699         MLX5_QPC_ST_RC            = 0x0,
2700         MLX5_QPC_ST_UC            = 0x1,
2701         MLX5_QPC_ST_UD            = 0x2,
2702         MLX5_QPC_ST_XRC           = 0x3,
2703         MLX5_QPC_ST_DCI           = 0x5,
2704         MLX5_QPC_ST_QP0           = 0x7,
2705         MLX5_QPC_ST_QP1           = 0x8,
2706         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2707         MLX5_QPC_ST_REG_UMR       = 0xc,
2708 };
2709
2710 enum {
2711         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2712         MLX5_QPC_PM_STATE_REARM     = 0x1,
2713         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2714         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2715 };
2716
2717 enum {
2718         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2719 };
2720
2721 enum {
2722         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2723         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2724 };
2725
2726 enum {
2727         MLX5_QPC_MTU_256_BYTES        = 0x1,
2728         MLX5_QPC_MTU_512_BYTES        = 0x2,
2729         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2730         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2731         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2732         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2733 };
2734
2735 enum {
2736         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2737         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2738         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2739         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2740         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2741         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2742         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2743         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2744 };
2745
2746 enum {
2747         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2748         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2749         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2750 };
2751
2752 enum {
2753         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2754         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2755         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2756 };
2757
2758 struct mlx5_ifc_qpc_bits {
2759         u8         state[0x4];
2760         u8         lag_tx_port_affinity[0x4];
2761         u8         st[0x8];
2762         u8         reserved_at_10[0x3];
2763         u8         pm_state[0x2];
2764         u8         reserved_at_15[0x1];
2765         u8         req_e2e_credit_mode[0x2];
2766         u8         offload_type[0x4];
2767         u8         end_padding_mode[0x2];
2768         u8         reserved_at_1e[0x2];
2769
2770         u8         wq_signature[0x1];
2771         u8         block_lb_mc[0x1];
2772         u8         atomic_like_write_en[0x1];
2773         u8         latency_sensitive[0x1];
2774         u8         reserved_at_24[0x1];
2775         u8         drain_sigerr[0x1];
2776         u8         reserved_at_26[0x2];
2777         u8         pd[0x18];
2778
2779         u8         mtu[0x3];
2780         u8         log_msg_max[0x5];
2781         u8         reserved_at_48[0x1];
2782         u8         log_rq_size[0x4];
2783         u8         log_rq_stride[0x3];
2784         u8         no_sq[0x1];
2785         u8         log_sq_size[0x4];
2786         u8         reserved_at_55[0x6];
2787         u8         rlky[0x1];
2788         u8         ulp_stateless_offload_mode[0x4];
2789
2790         u8         counter_set_id[0x8];
2791         u8         uar_page[0x18];
2792
2793         u8         reserved_at_80[0x8];
2794         u8         user_index[0x18];
2795
2796         u8         reserved_at_a0[0x3];
2797         u8         log_page_size[0x5];
2798         u8         remote_qpn[0x18];
2799
2800         struct mlx5_ifc_ads_bits primary_address_path;
2801
2802         struct mlx5_ifc_ads_bits secondary_address_path;
2803
2804         u8         log_ack_req_freq[0x4];
2805         u8         reserved_at_384[0x4];
2806         u8         log_sra_max[0x3];
2807         u8         reserved_at_38b[0x2];
2808         u8         retry_count[0x3];
2809         u8         rnr_retry[0x3];
2810         u8         reserved_at_393[0x1];
2811         u8         fre[0x1];
2812         u8         cur_rnr_retry[0x3];
2813         u8         cur_retry_count[0x3];
2814         u8         reserved_at_39b[0x5];
2815
2816         u8         reserved_at_3a0[0x20];
2817
2818         u8         reserved_at_3c0[0x8];
2819         u8         next_send_psn[0x18];
2820
2821         u8         reserved_at_3e0[0x8];
2822         u8         cqn_snd[0x18];
2823
2824         u8         reserved_at_400[0x8];
2825         u8         deth_sqpn[0x18];
2826
2827         u8         reserved_at_420[0x20];
2828
2829         u8         reserved_at_440[0x8];
2830         u8         last_acked_psn[0x18];
2831
2832         u8         reserved_at_460[0x8];
2833         u8         ssn[0x18];
2834
2835         u8         reserved_at_480[0x8];
2836         u8         log_rra_max[0x3];
2837         u8         reserved_at_48b[0x1];
2838         u8         atomic_mode[0x4];
2839         u8         rre[0x1];
2840         u8         rwe[0x1];
2841         u8         rae[0x1];
2842         u8         reserved_at_493[0x1];
2843         u8         page_offset[0x6];
2844         u8         reserved_at_49a[0x3];
2845         u8         cd_slave_receive[0x1];
2846         u8         cd_slave_send[0x1];
2847         u8         cd_master[0x1];
2848
2849         u8         reserved_at_4a0[0x3];
2850         u8         min_rnr_nak[0x5];
2851         u8         next_rcv_psn[0x18];
2852
2853         u8         reserved_at_4c0[0x8];
2854         u8         xrcd[0x18];
2855
2856         u8         reserved_at_4e0[0x8];
2857         u8         cqn_rcv[0x18];
2858
2859         u8         dbr_addr[0x40];
2860
2861         u8         q_key[0x20];
2862
2863         u8         reserved_at_560[0x5];
2864         u8         rq_type[0x3];
2865         u8         srqn_rmpn_xrqn[0x18];
2866
2867         u8         reserved_at_580[0x8];
2868         u8         rmsn[0x18];
2869
2870         u8         hw_sq_wqebb_counter[0x10];
2871         u8         sw_sq_wqebb_counter[0x10];
2872
2873         u8         hw_rq_counter[0x20];
2874
2875         u8         sw_rq_counter[0x20];
2876
2877         u8         reserved_at_600[0x20];
2878
2879         u8         reserved_at_620[0xf];
2880         u8         cgs[0x1];
2881         u8         cs_req[0x8];
2882         u8         cs_res[0x8];
2883
2884         u8         dc_access_key[0x40];
2885
2886         u8         reserved_at_680[0x3];
2887         u8         dbr_umem_valid[0x1];
2888
2889         u8         reserved_at_684[0xbc];
2890 };
2891
2892 struct mlx5_ifc_roce_addr_layout_bits {
2893         u8         source_l3_address[16][0x8];
2894
2895         u8         reserved_at_80[0x3];
2896         u8         vlan_valid[0x1];
2897         u8         vlan_id[0xc];
2898         u8         source_mac_47_32[0x10];
2899
2900         u8         source_mac_31_0[0x20];
2901
2902         u8         reserved_at_c0[0x14];
2903         u8         roce_l3_type[0x4];
2904         u8         roce_version[0x8];
2905
2906         u8         reserved_at_e0[0x20];
2907 };
2908
2909 union mlx5_ifc_hca_cap_union_bits {
2910         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2911         struct mlx5_ifc_odp_cap_bits odp_cap;
2912         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2913         struct mlx5_ifc_roce_cap_bits roce_cap;
2914         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2915         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2916         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2917         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2918         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2919         struct mlx5_ifc_qos_cap_bits qos_cap;
2920         struct mlx5_ifc_debug_cap_bits debug_cap;
2921         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2922         struct mlx5_ifc_tls_cap_bits tls_cap;
2923         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2924         struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2925         u8         reserved_at_0[0x8000];
2926 };
2927
2928 enum {
2929         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2930         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2931         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2932         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2933         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2934         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2935         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2936         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2937         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2938         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2939         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2940 };
2941
2942 enum {
2943         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2944         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2945         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2946 };
2947
2948 struct mlx5_ifc_vlan_bits {
2949         u8         ethtype[0x10];
2950         u8         prio[0x3];
2951         u8         cfi[0x1];
2952         u8         vid[0xc];
2953 };
2954
2955 struct mlx5_ifc_flow_context_bits {
2956         struct mlx5_ifc_vlan_bits push_vlan;
2957
2958         u8         group_id[0x20];
2959
2960         u8         reserved_at_40[0x8];
2961         u8         flow_tag[0x18];
2962
2963         u8         reserved_at_60[0x10];
2964         u8         action[0x10];
2965
2966         u8         extended_destination[0x1];
2967         u8         reserved_at_81[0x1];
2968         u8         flow_source[0x2];
2969         u8         reserved_at_84[0x4];
2970         u8         destination_list_size[0x18];
2971
2972         u8         reserved_at_a0[0x8];
2973         u8         flow_counter_list_size[0x18];
2974
2975         u8         packet_reformat_id[0x20];
2976
2977         u8         modify_header_id[0x20];
2978
2979         struct mlx5_ifc_vlan_bits push_vlan_2;
2980
2981         u8         reserved_at_120[0xe0];
2982
2983         struct mlx5_ifc_fte_match_param_bits match_value;
2984
2985         u8         reserved_at_1200[0x600];
2986
2987         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2988 };
2989
2990 enum {
2991         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2992         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2993 };
2994
2995 struct mlx5_ifc_xrc_srqc_bits {
2996         u8         state[0x4];
2997         u8         log_xrc_srq_size[0x4];
2998         u8         reserved_at_8[0x18];
2999
3000         u8         wq_signature[0x1];
3001         u8         cont_srq[0x1];
3002         u8         reserved_at_22[0x1];
3003         u8         rlky[0x1];
3004         u8         basic_cyclic_rcv_wqe[0x1];
3005         u8         log_rq_stride[0x3];
3006         u8         xrcd[0x18];
3007
3008         u8         page_offset[0x6];
3009         u8         reserved_at_46[0x1];
3010         u8         dbr_umem_valid[0x1];
3011         u8         cqn[0x18];
3012
3013         u8         reserved_at_60[0x20];
3014
3015         u8         user_index_equal_xrc_srqn[0x1];
3016         u8         reserved_at_81[0x1];
3017         u8         log_page_size[0x6];
3018         u8         user_index[0x18];
3019
3020         u8         reserved_at_a0[0x20];
3021
3022         u8         reserved_at_c0[0x8];
3023         u8         pd[0x18];
3024
3025         u8         lwm[0x10];
3026         u8         wqe_cnt[0x10];
3027
3028         u8         reserved_at_100[0x40];
3029
3030         u8         db_record_addr_h[0x20];
3031
3032         u8         db_record_addr_l[0x1e];
3033         u8         reserved_at_17e[0x2];
3034
3035         u8         reserved_at_180[0x80];
3036 };
3037
3038 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3039         u8         counter_error_queues[0x20];
3040
3041         u8         total_error_queues[0x20];
3042
3043         u8         send_queue_priority_update_flow[0x20];
3044
3045         u8         reserved_at_60[0x20];
3046
3047         u8         nic_receive_steering_discard[0x40];
3048
3049         u8         receive_discard_vport_down[0x40];
3050
3051         u8         transmit_discard_vport_down[0x40];
3052
3053         u8         reserved_at_140[0xa0];
3054
3055         u8         internal_rq_out_of_buffer[0x20];
3056
3057         u8         reserved_at_200[0xe00];
3058 };
3059
3060 struct mlx5_ifc_traffic_counter_bits {
3061         u8         packets[0x40];
3062
3063         u8         octets[0x40];
3064 };
3065
3066 struct mlx5_ifc_tisc_bits {
3067         u8         strict_lag_tx_port_affinity[0x1];
3068         u8         tls_en[0x1];
3069         u8         reserved_at_2[0x2];
3070         u8         lag_tx_port_affinity[0x04];
3071
3072         u8         reserved_at_8[0x4];
3073         u8         prio[0x4];
3074         u8         reserved_at_10[0x10];
3075
3076         u8         reserved_at_20[0x100];
3077
3078         u8         reserved_at_120[0x8];
3079         u8         transport_domain[0x18];
3080
3081         u8         reserved_at_140[0x8];
3082         u8         underlay_qpn[0x18];
3083
3084         u8         reserved_at_160[0x8];
3085         u8         pd[0x18];
3086
3087         u8         reserved_at_180[0x380];
3088 };
3089
3090 enum {
3091         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3092         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3093 };
3094
3095 enum {
3096         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3097         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3098 };
3099
3100 enum {
3101         MLX5_RX_HASH_FN_NONE           = 0x0,
3102         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3103         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3104 };
3105
3106 enum {
3107         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3108         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3109 };
3110
3111 struct mlx5_ifc_tirc_bits {
3112         u8         reserved_at_0[0x20];
3113
3114         u8         disp_type[0x4];
3115         u8         reserved_at_24[0x1c];
3116
3117         u8         reserved_at_40[0x40];
3118
3119         u8         reserved_at_80[0x4];
3120         u8         lro_timeout_period_usecs[0x10];
3121         u8         lro_enable_mask[0x4];
3122         u8         lro_max_ip_payload_size[0x8];
3123
3124         u8         reserved_at_a0[0x40];
3125
3126         u8         reserved_at_e0[0x8];
3127         u8         inline_rqn[0x18];
3128
3129         u8         rx_hash_symmetric[0x1];
3130         u8         reserved_at_101[0x1];
3131         u8         tunneled_offload_en[0x1];
3132         u8         reserved_at_103[0x5];
3133         u8         indirect_table[0x18];
3134
3135         u8         rx_hash_fn[0x4];
3136         u8         reserved_at_124[0x2];
3137         u8         self_lb_block[0x2];
3138         u8         transport_domain[0x18];
3139
3140         u8         rx_hash_toeplitz_key[10][0x20];
3141
3142         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3143
3144         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3145
3146         u8         reserved_at_2c0[0x4c0];
3147 };
3148
3149 enum {
3150         MLX5_SRQC_STATE_GOOD   = 0x0,
3151         MLX5_SRQC_STATE_ERROR  = 0x1,
3152 };
3153
3154 struct mlx5_ifc_srqc_bits {
3155         u8         state[0x4];
3156         u8         log_srq_size[0x4];
3157         u8         reserved_at_8[0x18];
3158
3159         u8         wq_signature[0x1];
3160         u8         cont_srq[0x1];
3161         u8         reserved_at_22[0x1];
3162         u8         rlky[0x1];
3163         u8         reserved_at_24[0x1];
3164         u8         log_rq_stride[0x3];
3165         u8         xrcd[0x18];
3166
3167         u8         page_offset[0x6];
3168         u8         reserved_at_46[0x2];
3169         u8         cqn[0x18];
3170
3171         u8         reserved_at_60[0x20];
3172
3173         u8         reserved_at_80[0x2];
3174         u8         log_page_size[0x6];
3175         u8         reserved_at_88[0x18];
3176
3177         u8         reserved_at_a0[0x20];
3178
3179         u8         reserved_at_c0[0x8];
3180         u8         pd[0x18];
3181
3182         u8         lwm[0x10];
3183         u8         wqe_cnt[0x10];
3184
3185         u8         reserved_at_100[0x40];
3186
3187         u8         dbr_addr[0x40];
3188
3189         u8         reserved_at_180[0x80];
3190 };
3191
3192 enum {
3193         MLX5_SQC_STATE_RST  = 0x0,
3194         MLX5_SQC_STATE_RDY  = 0x1,
3195         MLX5_SQC_STATE_ERR  = 0x3,
3196 };
3197
3198 struct mlx5_ifc_sqc_bits {
3199         u8         rlky[0x1];
3200         u8         cd_master[0x1];
3201         u8         fre[0x1];
3202         u8         flush_in_error_en[0x1];
3203         u8         allow_multi_pkt_send_wqe[0x1];
3204         u8         min_wqe_inline_mode[0x3];
3205         u8         state[0x4];
3206         u8         reg_umr[0x1];
3207         u8         allow_swp[0x1];
3208         u8         hairpin[0x1];
3209         u8         reserved_at_f[0x11];
3210
3211         u8         reserved_at_20[0x8];
3212         u8         user_index[0x18];
3213
3214         u8         reserved_at_40[0x8];
3215         u8         cqn[0x18];
3216
3217         u8         reserved_at_60[0x8];
3218         u8         hairpin_peer_rq[0x18];
3219
3220         u8         reserved_at_80[0x10];
3221         u8         hairpin_peer_vhca[0x10];
3222
3223         u8         reserved_at_a0[0x50];
3224
3225         u8         packet_pacing_rate_limit_index[0x10];
3226         u8         tis_lst_sz[0x10];
3227         u8         reserved_at_110[0x10];
3228
3229         u8         reserved_at_120[0x40];
3230
3231         u8         reserved_at_160[0x8];
3232         u8         tis_num_0[0x18];
3233
3234         struct mlx5_ifc_wq_bits wq;
3235 };
3236
3237 enum {
3238         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3239         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3240         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3241         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3242 };
3243
3244 enum {
3245         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3246         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3247         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3248         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3249 };
3250
3251 struct mlx5_ifc_scheduling_context_bits {
3252         u8         element_type[0x8];
3253         u8         reserved_at_8[0x18];
3254
3255         u8         element_attributes[0x20];
3256
3257         u8         parent_element_id[0x20];
3258
3259         u8         reserved_at_60[0x40];
3260
3261         u8         bw_share[0x20];
3262
3263         u8         max_average_bw[0x20];
3264
3265         u8         reserved_at_e0[0x120];
3266 };
3267
3268 struct mlx5_ifc_rqtc_bits {
3269         u8         reserved_at_0[0xa0];
3270
3271         u8         reserved_at_a0[0x10];
3272         u8         rqt_max_size[0x10];
3273
3274         u8         reserved_at_c0[0x10];
3275         u8         rqt_actual_size[0x10];
3276
3277         u8         reserved_at_e0[0x6a0];
3278
3279         struct mlx5_ifc_rq_num_bits rq_num[0];
3280 };
3281
3282 enum {
3283         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3284         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3285 };
3286
3287 enum {
3288         MLX5_RQC_STATE_RST  = 0x0,
3289         MLX5_RQC_STATE_RDY  = 0x1,
3290         MLX5_RQC_STATE_ERR  = 0x3,
3291 };
3292
3293 struct mlx5_ifc_rqc_bits {
3294         u8         rlky[0x1];
3295         u8         delay_drop_en[0x1];
3296         u8         scatter_fcs[0x1];
3297         u8         vsd[0x1];
3298         u8         mem_rq_type[0x4];
3299         u8         state[0x4];
3300         u8         reserved_at_c[0x1];
3301         u8         flush_in_error_en[0x1];
3302         u8         hairpin[0x1];
3303         u8         reserved_at_f[0x11];
3304
3305         u8         reserved_at_20[0x8];
3306         u8         user_index[0x18];
3307
3308         u8         reserved_at_40[0x8];
3309         u8         cqn[0x18];
3310
3311         u8         counter_set_id[0x8];
3312         u8         reserved_at_68[0x18];
3313
3314         u8         reserved_at_80[0x8];
3315         u8         rmpn[0x18];
3316
3317         u8         reserved_at_a0[0x8];
3318         u8         hairpin_peer_sq[0x18];
3319
3320         u8         reserved_at_c0[0x10];
3321         u8         hairpin_peer_vhca[0x10];
3322
3323         u8         reserved_at_e0[0xa0];
3324
3325         struct mlx5_ifc_wq_bits wq;
3326 };
3327
3328 enum {
3329         MLX5_RMPC_STATE_RDY  = 0x1,
3330         MLX5_RMPC_STATE_ERR  = 0x3,
3331 };
3332
3333 struct mlx5_ifc_rmpc_bits {
3334         u8         reserved_at_0[0x8];
3335         u8         state[0x4];
3336         u8         reserved_at_c[0x14];
3337
3338         u8         basic_cyclic_rcv_wqe[0x1];
3339         u8         reserved_at_21[0x1f];
3340
3341         u8         reserved_at_40[0x140];
3342
3343         struct mlx5_ifc_wq_bits wq;
3344 };
3345
3346 struct mlx5_ifc_nic_vport_context_bits {
3347         u8         reserved_at_0[0x5];
3348         u8         min_wqe_inline_mode[0x3];
3349         u8         reserved_at_8[0x15];
3350         u8         disable_mc_local_lb[0x1];
3351         u8         disable_uc_local_lb[0x1];
3352         u8         roce_en[0x1];
3353
3354         u8         arm_change_event[0x1];
3355         u8         reserved_at_21[0x1a];
3356         u8         event_on_mtu[0x1];
3357         u8         event_on_promisc_change[0x1];
3358         u8         event_on_vlan_change[0x1];
3359         u8         event_on_mc_address_change[0x1];
3360         u8         event_on_uc_address_change[0x1];
3361
3362         u8         reserved_at_40[0xc];
3363
3364         u8         affiliation_criteria[0x4];
3365         u8         affiliated_vhca_id[0x10];
3366
3367         u8         reserved_at_60[0xd0];
3368
3369         u8         mtu[0x10];
3370
3371         u8         system_image_guid[0x40];
3372         u8         port_guid[0x40];
3373         u8         node_guid[0x40];
3374
3375         u8         reserved_at_200[0x140];
3376         u8         qkey_violation_counter[0x10];
3377         u8         reserved_at_350[0x430];
3378
3379         u8         promisc_uc[0x1];
3380         u8         promisc_mc[0x1];
3381         u8         promisc_all[0x1];
3382         u8         reserved_at_783[0x2];
3383         u8         allowed_list_type[0x3];
3384         u8         reserved_at_788[0xc];
3385         u8         allowed_list_size[0xc];
3386
3387         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3388
3389         u8         reserved_at_7e0[0x20];
3390
3391         u8         current_uc_mac_address[0][0x40];
3392 };
3393
3394 enum {
3395         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3396         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3397         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3398         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3399         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3400         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3401 };
3402
3403 struct mlx5_ifc_mkc_bits {
3404         u8         reserved_at_0[0x1];
3405         u8         free[0x1];
3406         u8         reserved_at_2[0x1];
3407         u8         access_mode_4_2[0x3];
3408         u8         reserved_at_6[0x7];
3409         u8         relaxed_ordering_write[0x1];
3410         u8         reserved_at_e[0x1];
3411         u8         small_fence_on_rdma_read_response[0x1];
3412         u8         umr_en[0x1];
3413         u8         a[0x1];
3414         u8         rw[0x1];
3415         u8         rr[0x1];
3416         u8         lw[0x1];
3417         u8         lr[0x1];
3418         u8         access_mode_1_0[0x2];
3419         u8         reserved_at_18[0x8];
3420
3421         u8         qpn[0x18];
3422         u8         mkey_7_0[0x8];
3423
3424         u8         reserved_at_40[0x20];
3425
3426         u8         length64[0x1];
3427         u8         bsf_en[0x1];
3428         u8         sync_umr[0x1];
3429         u8         reserved_at_63[0x2];
3430         u8         expected_sigerr_count[0x1];
3431         u8         reserved_at_66[0x1];
3432         u8         en_rinval[0x1];
3433         u8         pd[0x18];
3434
3435         u8         start_addr[0x40];
3436
3437         u8         len[0x40];
3438
3439         u8         bsf_octword_size[0x20];
3440
3441         u8         reserved_at_120[0x80];
3442
3443         u8         translations_octword_size[0x20];
3444
3445         u8         reserved_at_1c0[0x19];
3446         u8         relaxed_ordering_read[0x1];
3447         u8         reserved_at_1d9[0x1];
3448         u8         log_page_size[0x5];
3449
3450         u8         reserved_at_1e0[0x20];
3451 };
3452
3453 struct mlx5_ifc_pkey_bits {
3454         u8         reserved_at_0[0x10];
3455         u8         pkey[0x10];
3456 };
3457
3458 struct mlx5_ifc_array128_auto_bits {
3459         u8         array128_auto[16][0x8];
3460 };
3461
3462 struct mlx5_ifc_hca_vport_context_bits {
3463         u8         field_select[0x20];
3464
3465         u8         reserved_at_20[0xe0];
3466
3467         u8         sm_virt_aware[0x1];
3468         u8         has_smi[0x1];
3469         u8         has_raw[0x1];
3470         u8         grh_required[0x1];
3471         u8         reserved_at_104[0xc];
3472         u8         port_physical_state[0x4];
3473         u8         vport_state_policy[0x4];
3474         u8         port_state[0x4];
3475         u8         vport_state[0x4];
3476
3477         u8         reserved_at_120[0x20];
3478
3479         u8         system_image_guid[0x40];
3480
3481         u8         port_guid[0x40];
3482
3483         u8         node_guid[0x40];
3484
3485         u8         cap_mask1[0x20];
3486
3487         u8         cap_mask1_field_select[0x20];
3488
3489         u8         cap_mask2[0x20];
3490
3491         u8         cap_mask2_field_select[0x20];
3492
3493         u8         reserved_at_280[0x80];
3494
3495         u8         lid[0x10];
3496         u8         reserved_at_310[0x4];
3497         u8         init_type_reply[0x4];
3498         u8         lmc[0x3];
3499         u8         subnet_timeout[0x5];
3500
3501         u8         sm_lid[0x10];
3502         u8         sm_sl[0x4];
3503         u8         reserved_at_334[0xc];
3504
3505         u8         qkey_violation_counter[0x10];
3506         u8         pkey_violation_counter[0x10];
3507
3508         u8         reserved_at_360[0xca0];
3509 };
3510
3511 struct mlx5_ifc_esw_vport_context_bits {
3512         u8         fdb_to_vport_reg_c[0x1];
3513         u8         reserved_at_1[0x2];
3514         u8         vport_svlan_strip[0x1];
3515         u8         vport_cvlan_strip[0x1];
3516         u8         vport_svlan_insert[0x1];
3517         u8         vport_cvlan_insert[0x2];
3518         u8         fdb_to_vport_reg_c_id[0x8];
3519         u8         reserved_at_10[0x10];
3520
3521         u8         reserved_at_20[0x20];
3522
3523         u8         svlan_cfi[0x1];
3524         u8         svlan_pcp[0x3];
3525         u8         svlan_id[0xc];
3526         u8         cvlan_cfi[0x1];
3527         u8         cvlan_pcp[0x3];
3528         u8         cvlan_id[0xc];
3529
3530         u8         reserved_at_60[0x720];
3531
3532         u8         sw_steering_vport_icm_address_rx[0x40];
3533
3534         u8         sw_steering_vport_icm_address_tx[0x40];
3535 };
3536
3537 enum {
3538         MLX5_EQC_STATUS_OK                = 0x0,
3539         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3540 };
3541
3542 enum {
3543         MLX5_EQC_ST_ARMED  = 0x9,
3544         MLX5_EQC_ST_FIRED  = 0xa,
3545 };
3546
3547 struct mlx5_ifc_eqc_bits {
3548         u8         status[0x4];
3549         u8         reserved_at_4[0x9];
3550         u8         ec[0x1];
3551         u8         oi[0x1];
3552         u8         reserved_at_f[0x5];
3553         u8         st[0x4];
3554         u8         reserved_at_18[0x8];
3555
3556         u8         reserved_at_20[0x20];
3557
3558         u8         reserved_at_40[0x14];
3559         u8         page_offset[0x6];
3560         u8         reserved_at_5a[0x6];
3561
3562         u8         reserved_at_60[0x3];
3563         u8         log_eq_size[0x5];
3564         u8         uar_page[0x18];
3565
3566         u8         reserved_at_80[0x20];
3567
3568         u8         reserved_at_a0[0x18];
3569         u8         intr[0x8];
3570
3571         u8         reserved_at_c0[0x3];
3572         u8         log_page_size[0x5];
3573         u8         reserved_at_c8[0x18];
3574
3575         u8         reserved_at_e0[0x60];
3576
3577         u8         reserved_at_140[0x8];
3578         u8         consumer_counter[0x18];
3579
3580         u8         reserved_at_160[0x8];
3581         u8         producer_counter[0x18];
3582
3583         u8         reserved_at_180[0x80];
3584 };
3585
3586 enum {
3587         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3588         MLX5_DCTC_STATE_DRAINING  = 0x1,
3589         MLX5_DCTC_STATE_DRAINED   = 0x2,
3590 };
3591
3592 enum {
3593         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3594         MLX5_DCTC_CS_RES_NA         = 0x1,
3595         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3596 };
3597
3598 enum {
3599         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3600         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3601         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3602         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3603         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3604 };
3605
3606 struct mlx5_ifc_dctc_bits {
3607         u8         reserved_at_0[0x4];
3608         u8         state[0x4];
3609         u8         reserved_at_8[0x18];
3610
3611         u8         reserved_at_20[0x8];
3612         u8         user_index[0x18];
3613
3614         u8         reserved_at_40[0x8];
3615         u8         cqn[0x18];
3616
3617         u8         counter_set_id[0x8];
3618         u8         atomic_mode[0x4];
3619         u8         rre[0x1];
3620         u8         rwe[0x1];
3621         u8         rae[0x1];
3622         u8         atomic_like_write_en[0x1];
3623         u8         latency_sensitive[0x1];
3624         u8         rlky[0x1];
3625         u8         free_ar[0x1];
3626         u8         reserved_at_73[0xd];
3627
3628         u8         reserved_at_80[0x8];
3629         u8         cs_res[0x8];
3630         u8         reserved_at_90[0x3];
3631         u8         min_rnr_nak[0x5];
3632         u8         reserved_at_98[0x8];
3633
3634         u8         reserved_at_a0[0x8];
3635         u8         srqn_xrqn[0x18];
3636
3637         u8         reserved_at_c0[0x8];
3638         u8         pd[0x18];
3639
3640         u8         tclass[0x8];
3641         u8         reserved_at_e8[0x4];
3642         u8         flow_label[0x14];
3643
3644         u8         dc_access_key[0x40];
3645
3646         u8         reserved_at_140[0x5];
3647         u8         mtu[0x3];
3648         u8         port[0x8];
3649         u8         pkey_index[0x10];
3650
3651         u8         reserved_at_160[0x8];
3652         u8         my_addr_index[0x8];
3653         u8         reserved_at_170[0x8];
3654         u8         hop_limit[0x8];
3655
3656         u8         dc_access_key_violation_count[0x20];
3657
3658         u8         reserved_at_1a0[0x14];
3659         u8         dei_cfi[0x1];
3660         u8         eth_prio[0x3];
3661         u8         ecn[0x2];
3662         u8         dscp[0x6];
3663
3664         u8         reserved_at_1c0[0x40];
3665 };
3666
3667 enum {
3668         MLX5_CQC_STATUS_OK             = 0x0,
3669         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3670         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3671 };
3672
3673 enum {
3674         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3675         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3676 };
3677
3678 enum {
3679         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3680         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3681         MLX5_CQC_ST_FIRED                                 = 0xa,
3682 };
3683
3684 enum {
3685         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3686         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3687         MLX5_CQ_PERIOD_NUM_MODES
3688 };
3689
3690 struct mlx5_ifc_cqc_bits {
3691         u8         status[0x4];
3692         u8         reserved_at_4[0x2];
3693         u8         dbr_umem_valid[0x1];
3694         u8         reserved_at_7[0x1];
3695         u8         cqe_sz[0x3];
3696         u8         cc[0x1];
3697         u8         reserved_at_c[0x1];
3698         u8         scqe_break_moderation_en[0x1];
3699         u8         oi[0x1];
3700         u8         cq_period_mode[0x2];
3701         u8         cqe_comp_en[0x1];
3702         u8         mini_cqe_res_format[0x2];
3703         u8         st[0x4];
3704         u8         reserved_at_18[0x8];
3705
3706         u8         reserved_at_20[0x20];
3707
3708         u8         reserved_at_40[0x14];
3709         u8         page_offset[0x6];
3710         u8         reserved_at_5a[0x6];
3711
3712         u8         reserved_at_60[0x3];
3713         u8         log_cq_size[0x5];
3714         u8         uar_page[0x18];
3715
3716         u8         reserved_at_80[0x4];
3717         u8         cq_period[0xc];
3718         u8         cq_max_count[0x10];
3719
3720         u8         reserved_at_a0[0x18];
3721         u8         c_eqn[0x8];
3722
3723         u8         reserved_at_c0[0x3];
3724         u8         log_page_size[0x5];
3725         u8         reserved_at_c8[0x18];
3726
3727         u8         reserved_at_e0[0x20];
3728
3729         u8         reserved_at_100[0x8];
3730         u8         last_notified_index[0x18];
3731
3732         u8         reserved_at_120[0x8];
3733         u8         last_solicit_index[0x18];
3734
3735         u8         reserved_at_140[0x8];
3736         u8         consumer_counter[0x18];
3737
3738         u8         reserved_at_160[0x8];
3739         u8         producer_counter[0x18];
3740
3741         u8         reserved_at_180[0x40];
3742
3743         u8         dbr_addr[0x40];
3744 };
3745
3746 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3747         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3748         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3749         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3750         u8         reserved_at_0[0x800];
3751 };
3752
3753 struct mlx5_ifc_query_adapter_param_block_bits {
3754         u8         reserved_at_0[0xc0];
3755
3756         u8         reserved_at_c0[0x8];
3757         u8         ieee_vendor_id[0x18];
3758
3759         u8         reserved_at_e0[0x10];
3760         u8         vsd_vendor_id[0x10];
3761
3762         u8         vsd[208][0x8];
3763
3764         u8         vsd_contd_psid[16][0x8];
3765 };
3766
3767 enum {
3768         MLX5_XRQC_STATE_GOOD   = 0x0,
3769         MLX5_XRQC_STATE_ERROR  = 0x1,
3770 };
3771
3772 enum {
3773         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3774         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3775 };
3776
3777 enum {
3778         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3779 };
3780
3781 struct mlx5_ifc_tag_matching_topology_context_bits {
3782         u8         log_matching_list_sz[0x4];
3783         u8         reserved_at_4[0xc];
3784         u8         append_next_index[0x10];
3785
3786         u8         sw_phase_cnt[0x10];
3787         u8         hw_phase_cnt[0x10];
3788
3789         u8         reserved_at_40[0x40];
3790 };
3791
3792 struct mlx5_ifc_xrqc_bits {
3793         u8         state[0x4];
3794         u8         rlkey[0x1];
3795         u8         reserved_at_5[0xf];
3796         u8         topology[0x4];
3797         u8         reserved_at_18[0x4];
3798         u8         offload[0x4];
3799
3800         u8         reserved_at_20[0x8];
3801         u8         user_index[0x18];
3802
3803         u8         reserved_at_40[0x8];
3804         u8         cqn[0x18];
3805
3806         u8         reserved_at_60[0xa0];
3807
3808         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3809
3810         u8         reserved_at_180[0x280];
3811
3812         struct mlx5_ifc_wq_bits wq;
3813 };
3814
3815 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3816         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3817         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3818         u8         reserved_at_0[0x20];
3819 };
3820
3821 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3822         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3823         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3824         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3825         u8         reserved_at_0[0x20];
3826 };
3827
3828 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3829         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3830         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3831         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3832         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3833         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3834         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3835         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3836         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3837         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3838         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3839         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3840         u8         reserved_at_0[0x7c0];
3841 };
3842
3843 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3844         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3845         u8         reserved_at_0[0x7c0];
3846 };
3847
3848 union mlx5_ifc_event_auto_bits {
3849         struct mlx5_ifc_comp_event_bits comp_event;
3850         struct mlx5_ifc_dct_events_bits dct_events;
3851         struct mlx5_ifc_qp_events_bits qp_events;
3852         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3853         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3854         struct mlx5_ifc_cq_error_bits cq_error;
3855         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3856         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3857         struct mlx5_ifc_gpio_event_bits gpio_event;
3858         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3859         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3860         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3861         u8         reserved_at_0[0xe0];
3862 };
3863
3864 struct mlx5_ifc_health_buffer_bits {
3865         u8         reserved_at_0[0x100];
3866
3867         u8         assert_existptr[0x20];
3868
3869         u8         assert_callra[0x20];
3870
3871         u8         reserved_at_140[0x40];
3872
3873         u8         fw_version[0x20];
3874
3875         u8         hw_id[0x20];
3876
3877         u8         reserved_at_1c0[0x20];
3878
3879         u8         irisc_index[0x8];
3880         u8         synd[0x8];
3881         u8         ext_synd[0x10];
3882 };
3883
3884 struct mlx5_ifc_register_loopback_control_bits {
3885         u8         no_lb[0x1];
3886         u8         reserved_at_1[0x7];
3887         u8         port[0x8];
3888         u8         reserved_at_10[0x10];
3889
3890         u8         reserved_at_20[0x60];
3891 };
3892
3893 struct mlx5_ifc_vport_tc_element_bits {
3894         u8         traffic_class[0x4];
3895         u8         reserved_at_4[0xc];
3896         u8         vport_number[0x10];
3897 };
3898
3899 struct mlx5_ifc_vport_element_bits {
3900         u8         reserved_at_0[0x10];
3901         u8         vport_number[0x10];
3902 };
3903
3904 enum {
3905         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3906         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3907         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3908 };
3909
3910 struct mlx5_ifc_tsar_element_bits {
3911         u8         reserved_at_0[0x8];
3912         u8         tsar_type[0x8];
3913         u8         reserved_at_10[0x10];
3914 };
3915
3916 enum {
3917         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3918         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3919 };
3920
3921 struct mlx5_ifc_teardown_hca_out_bits {
3922         u8         status[0x8];
3923         u8         reserved_at_8[0x18];
3924
3925         u8         syndrome[0x20];
3926
3927         u8         reserved_at_40[0x3f];
3928
3929         u8         state[0x1];
3930 };
3931
3932 enum {
3933         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3934         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3935         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3936 };
3937
3938 struct mlx5_ifc_teardown_hca_in_bits {
3939         u8         opcode[0x10];
3940         u8         reserved_at_10[0x10];
3941
3942         u8         reserved_at_20[0x10];
3943         u8         op_mod[0x10];
3944
3945         u8         reserved_at_40[0x10];
3946         u8         profile[0x10];
3947
3948         u8         reserved_at_60[0x20];
3949 };
3950
3951 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3952         u8         status[0x8];
3953         u8         reserved_at_8[0x18];
3954
3955         u8         syndrome[0x20];
3956
3957         u8         reserved_at_40[0x40];
3958 };
3959
3960 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3961         u8         opcode[0x10];
3962         u8         uid[0x10];
3963
3964         u8         reserved_at_20[0x10];
3965         u8         op_mod[0x10];
3966
3967         u8         reserved_at_40[0x8];
3968         u8         qpn[0x18];
3969
3970         u8         reserved_at_60[0x20];
3971
3972         u8         opt_param_mask[0x20];
3973
3974         u8         reserved_at_a0[0x20];
3975
3976         struct mlx5_ifc_qpc_bits qpc;
3977
3978         u8         reserved_at_800[0x80];
3979 };
3980
3981 struct mlx5_ifc_sqd2rts_qp_out_bits {
3982         u8         status[0x8];
3983         u8         reserved_at_8[0x18];
3984
3985         u8         syndrome[0x20];
3986
3987         u8         reserved_at_40[0x40];
3988 };
3989
3990 struct mlx5_ifc_sqd2rts_qp_in_bits {
3991         u8         opcode[0x10];
3992         u8         uid[0x10];
3993
3994         u8         reserved_at_20[0x10];
3995         u8         op_mod[0x10];
3996
3997         u8         reserved_at_40[0x8];
3998         u8         qpn[0x18];
3999
4000         u8         reserved_at_60[0x20];
4001
4002         u8         opt_param_mask[0x20];
4003
4004         u8         reserved_at_a0[0x20];
4005
4006         struct mlx5_ifc_qpc_bits qpc;
4007
4008         u8         reserved_at_800[0x80];
4009 };
4010
4011 struct mlx5_ifc_set_roce_address_out_bits {
4012         u8         status[0x8];
4013         u8         reserved_at_8[0x18];
4014
4015         u8         syndrome[0x20];
4016
4017         u8         reserved_at_40[0x40];
4018 };
4019
4020 struct mlx5_ifc_set_roce_address_in_bits {
4021         u8         opcode[0x10];
4022         u8         reserved_at_10[0x10];
4023
4024         u8         reserved_at_20[0x10];
4025         u8         op_mod[0x10];
4026
4027         u8         roce_address_index[0x10];
4028         u8         reserved_at_50[0xc];
4029         u8         vhca_port_num[0x4];
4030
4031         u8         reserved_at_60[0x20];
4032
4033         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4034 };
4035
4036 struct mlx5_ifc_set_mad_demux_out_bits {
4037         u8         status[0x8];
4038         u8         reserved_at_8[0x18];
4039
4040         u8         syndrome[0x20];
4041
4042         u8         reserved_at_40[0x40];
4043 };
4044
4045 enum {
4046         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4047         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4048 };
4049
4050 struct mlx5_ifc_set_mad_demux_in_bits {
4051         u8         opcode[0x10];
4052         u8         reserved_at_10[0x10];
4053
4054         u8         reserved_at_20[0x10];
4055         u8         op_mod[0x10];
4056
4057         u8         reserved_at_40[0x20];
4058
4059         u8         reserved_at_60[0x6];
4060         u8         demux_mode[0x2];
4061         u8         reserved_at_68[0x18];
4062 };
4063
4064 struct mlx5_ifc_set_l2_table_entry_out_bits {
4065         u8         status[0x8];
4066         u8         reserved_at_8[0x18];
4067
4068         u8         syndrome[0x20];
4069
4070         u8         reserved_at_40[0x40];
4071 };
4072
4073 struct mlx5_ifc_set_l2_table_entry_in_bits {
4074         u8         opcode[0x10];
4075         u8         reserved_at_10[0x10];
4076
4077         u8         reserved_at_20[0x10];
4078         u8         op_mod[0x10];
4079
4080         u8         reserved_at_40[0x60];
4081
4082         u8         reserved_at_a0[0x8];
4083         u8         table_index[0x18];
4084
4085         u8         reserved_at_c0[0x20];
4086
4087         u8         reserved_at_e0[0x13];
4088         u8         vlan_valid[0x1];
4089         u8         vlan[0xc];
4090
4091         struct mlx5_ifc_mac_address_layout_bits mac_address;
4092
4093         u8         reserved_at_140[0xc0];
4094 };
4095
4096 struct mlx5_ifc_set_issi_out_bits {
4097         u8         status[0x8];
4098         u8         reserved_at_8[0x18];
4099
4100         u8         syndrome[0x20];
4101
4102         u8         reserved_at_40[0x40];
4103 };
4104
4105 struct mlx5_ifc_set_issi_in_bits {
4106         u8         opcode[0x10];
4107         u8         reserved_at_10[0x10];
4108
4109         u8         reserved_at_20[0x10];
4110         u8         op_mod[0x10];
4111
4112         u8         reserved_at_40[0x10];
4113         u8         current_issi[0x10];
4114
4115         u8         reserved_at_60[0x20];
4116 };
4117
4118 struct mlx5_ifc_set_hca_cap_out_bits {
4119         u8         status[0x8];
4120         u8         reserved_at_8[0x18];
4121
4122         u8         syndrome[0x20];
4123
4124         u8         reserved_at_40[0x40];
4125 };
4126
4127 struct mlx5_ifc_set_hca_cap_in_bits {
4128         u8         opcode[0x10];
4129         u8         reserved_at_10[0x10];
4130
4131         u8         reserved_at_20[0x10];
4132         u8         op_mod[0x10];
4133
4134         u8         reserved_at_40[0x40];
4135
4136         union mlx5_ifc_hca_cap_union_bits capability;
4137 };
4138
4139 enum {
4140         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4141         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4142         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4143         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
4144 };
4145
4146 struct mlx5_ifc_set_fte_out_bits {
4147         u8         status[0x8];
4148         u8         reserved_at_8[0x18];
4149
4150         u8         syndrome[0x20];
4151
4152         u8         reserved_at_40[0x40];
4153 };
4154
4155 struct mlx5_ifc_set_fte_in_bits {
4156         u8         opcode[0x10];
4157         u8         reserved_at_10[0x10];
4158
4159         u8         reserved_at_20[0x10];
4160         u8         op_mod[0x10];
4161
4162         u8         other_vport[0x1];
4163         u8         reserved_at_41[0xf];
4164         u8         vport_number[0x10];
4165
4166         u8         reserved_at_60[0x20];
4167
4168         u8         table_type[0x8];
4169         u8         reserved_at_88[0x18];
4170
4171         u8         reserved_at_a0[0x8];
4172         u8         table_id[0x18];
4173
4174         u8         ignore_flow_level[0x1];
4175         u8         reserved_at_c1[0x17];
4176         u8         modify_enable_mask[0x8];
4177
4178         u8         reserved_at_e0[0x20];
4179
4180         u8         flow_index[0x20];
4181
4182         u8         reserved_at_120[0xe0];
4183
4184         struct mlx5_ifc_flow_context_bits flow_context;
4185 };
4186
4187 struct mlx5_ifc_rts2rts_qp_out_bits {
4188         u8         status[0x8];
4189         u8         reserved_at_8[0x18];
4190
4191         u8         syndrome[0x20];
4192
4193         u8         reserved_at_40[0x40];
4194 };
4195
4196 struct mlx5_ifc_rts2rts_qp_in_bits {
4197         u8         opcode[0x10];
4198         u8         uid[0x10];
4199
4200         u8         reserved_at_20[0x10];
4201         u8         op_mod[0x10];
4202
4203         u8         reserved_at_40[0x8];
4204         u8         qpn[0x18];
4205
4206         u8         reserved_at_60[0x20];
4207
4208         u8         opt_param_mask[0x20];
4209
4210         u8         reserved_at_a0[0x20];
4211
4212         struct mlx5_ifc_qpc_bits qpc;
4213
4214         u8         reserved_at_800[0x80];
4215 };
4216
4217 struct mlx5_ifc_rtr2rts_qp_out_bits {
4218         u8         status[0x8];
4219         u8         reserved_at_8[0x18];
4220
4221         u8         syndrome[0x20];
4222
4223         u8         reserved_at_40[0x40];
4224 };
4225
4226 struct mlx5_ifc_rtr2rts_qp_in_bits {
4227         u8         opcode[0x10];
4228         u8         uid[0x10];
4229
4230         u8         reserved_at_20[0x10];
4231         u8         op_mod[0x10];
4232
4233         u8         reserved_at_40[0x8];
4234         u8         qpn[0x18];
4235
4236         u8         reserved_at_60[0x20];
4237
4238         u8         opt_param_mask[0x20];
4239
4240         u8         reserved_at_a0[0x20];
4241
4242         struct mlx5_ifc_qpc_bits qpc;
4243
4244         u8         reserved_at_800[0x80];
4245 };
4246
4247 struct mlx5_ifc_rst2init_qp_out_bits {
4248         u8         status[0x8];
4249         u8         reserved_at_8[0x18];
4250
4251         u8         syndrome[0x20];
4252
4253         u8         reserved_at_40[0x40];
4254 };
4255
4256 struct mlx5_ifc_rst2init_qp_in_bits {
4257         u8         opcode[0x10];
4258         u8         uid[0x10];
4259
4260         u8         reserved_at_20[0x10];
4261         u8         op_mod[0x10];
4262
4263         u8         reserved_at_40[0x8];
4264         u8         qpn[0x18];
4265
4266         u8         reserved_at_60[0x20];
4267
4268         u8         opt_param_mask[0x20];
4269
4270         u8         reserved_at_a0[0x20];
4271
4272         struct mlx5_ifc_qpc_bits qpc;
4273
4274         u8         reserved_at_800[0x80];
4275 };
4276
4277 struct mlx5_ifc_query_xrq_out_bits {
4278         u8         status[0x8];
4279         u8         reserved_at_8[0x18];
4280
4281         u8         syndrome[0x20];
4282
4283         u8         reserved_at_40[0x40];
4284
4285         struct mlx5_ifc_xrqc_bits xrq_context;
4286 };
4287
4288 struct mlx5_ifc_query_xrq_in_bits {
4289         u8         opcode[0x10];
4290         u8         reserved_at_10[0x10];
4291
4292         u8         reserved_at_20[0x10];
4293         u8         op_mod[0x10];
4294
4295         u8         reserved_at_40[0x8];
4296         u8         xrqn[0x18];
4297
4298         u8         reserved_at_60[0x20];
4299 };
4300
4301 struct mlx5_ifc_query_xrc_srq_out_bits {
4302         u8         status[0x8];
4303         u8         reserved_at_8[0x18];
4304
4305         u8         syndrome[0x20];
4306
4307         u8         reserved_at_40[0x40];
4308
4309         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4310
4311         u8         reserved_at_280[0x600];
4312
4313         u8         pas[0][0x40];
4314 };
4315
4316 struct mlx5_ifc_query_xrc_srq_in_bits {
4317         u8         opcode[0x10];
4318         u8         reserved_at_10[0x10];
4319
4320         u8         reserved_at_20[0x10];
4321         u8         op_mod[0x10];
4322
4323         u8         reserved_at_40[0x8];
4324         u8         xrc_srqn[0x18];
4325
4326         u8         reserved_at_60[0x20];
4327 };
4328
4329 enum {
4330         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4331         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4332 };
4333
4334 struct mlx5_ifc_query_vport_state_out_bits {
4335         u8         status[0x8];
4336         u8         reserved_at_8[0x18];
4337
4338         u8         syndrome[0x20];
4339
4340         u8         reserved_at_40[0x20];
4341
4342         u8         reserved_at_60[0x18];
4343         u8         admin_state[0x4];
4344         u8         state[0x4];
4345 };
4346
4347 enum {
4348         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4349         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4350 };
4351
4352 struct mlx5_ifc_arm_monitor_counter_in_bits {
4353         u8         opcode[0x10];
4354         u8         uid[0x10];
4355
4356         u8         reserved_at_20[0x10];
4357         u8         op_mod[0x10];
4358
4359         u8         reserved_at_40[0x20];
4360
4361         u8         reserved_at_60[0x20];
4362 };
4363
4364 struct mlx5_ifc_arm_monitor_counter_out_bits {
4365         u8         status[0x8];
4366         u8         reserved_at_8[0x18];
4367
4368         u8         syndrome[0x20];
4369
4370         u8         reserved_at_40[0x40];
4371 };
4372
4373 enum {
4374         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4375         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4376 };
4377
4378 enum mlx5_monitor_counter_ppcnt {
4379         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4380         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4381         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4382         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4383         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4384         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4385 };
4386
4387 enum {
4388         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4389 };
4390
4391 struct mlx5_ifc_monitor_counter_output_bits {
4392         u8         reserved_at_0[0x4];
4393         u8         type[0x4];
4394         u8         reserved_at_8[0x8];
4395         u8         counter[0x10];
4396
4397         u8         counter_group_id[0x20];
4398 };
4399
4400 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4401 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4402 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4403                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4404
4405 struct mlx5_ifc_set_monitor_counter_in_bits {
4406         u8         opcode[0x10];
4407         u8         uid[0x10];
4408
4409         u8         reserved_at_20[0x10];
4410         u8         op_mod[0x10];
4411
4412         u8         reserved_at_40[0x10];
4413         u8         num_of_counters[0x10];
4414
4415         u8         reserved_at_60[0x20];
4416
4417         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4418 };
4419
4420 struct mlx5_ifc_set_monitor_counter_out_bits {
4421         u8         status[0x8];
4422         u8         reserved_at_8[0x18];
4423
4424         u8         syndrome[0x20];
4425
4426         u8         reserved_at_40[0x40];
4427 };
4428
4429 struct mlx5_ifc_query_vport_state_in_bits {
4430         u8         opcode[0x10];
4431         u8         reserved_at_10[0x10];
4432
4433         u8         reserved_at_20[0x10];
4434         u8         op_mod[0x10];
4435
4436         u8         other_vport[0x1];
4437         u8         reserved_at_41[0xf];
4438         u8         vport_number[0x10];
4439
4440         u8         reserved_at_60[0x20];
4441 };
4442
4443 struct mlx5_ifc_query_vnic_env_out_bits {
4444         u8         status[0x8];
4445         u8         reserved_at_8[0x18];
4446
4447         u8         syndrome[0x20];
4448
4449         u8         reserved_at_40[0x40];
4450
4451         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4452 };
4453
4454 enum {
4455         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4456 };
4457
4458 struct mlx5_ifc_query_vnic_env_in_bits {
4459         u8         opcode[0x10];
4460         u8         reserved_at_10[0x10];
4461
4462         u8         reserved_at_20[0x10];
4463         u8         op_mod[0x10];
4464
4465         u8         other_vport[0x1];
4466         u8         reserved_at_41[0xf];
4467         u8         vport_number[0x10];
4468
4469         u8         reserved_at_60[0x20];
4470 };
4471
4472 struct mlx5_ifc_query_vport_counter_out_bits {
4473         u8         status[0x8];
4474         u8         reserved_at_8[0x18];
4475
4476         u8         syndrome[0x20];
4477
4478         u8         reserved_at_40[0x40];
4479
4480         struct mlx5_ifc_traffic_counter_bits received_errors;
4481
4482         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4483
4484         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4485
4486         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4487
4488         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4489
4490         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4491
4492         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4493
4494         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4495
4496         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4497
4498         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4499
4500         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4501
4502         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4503
4504         u8         reserved_at_680[0xa00];
4505 };
4506
4507 enum {
4508         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4509 };
4510
4511 struct mlx5_ifc_query_vport_counter_in_bits {
4512         u8         opcode[0x10];
4513         u8         reserved_at_10[0x10];
4514
4515         u8         reserved_at_20[0x10];
4516         u8         op_mod[0x10];
4517
4518         u8         other_vport[0x1];
4519         u8         reserved_at_41[0xb];
4520         u8         port_num[0x4];
4521         u8         vport_number[0x10];
4522
4523         u8         reserved_at_60[0x60];
4524
4525         u8         clear[0x1];
4526         u8         reserved_at_c1[0x1f];
4527
4528         u8         reserved_at_e0[0x20];
4529 };
4530
4531 struct mlx5_ifc_query_tis_out_bits {
4532         u8         status[0x8];
4533         u8         reserved_at_8[0x18];
4534
4535         u8         syndrome[0x20];
4536
4537         u8         reserved_at_40[0x40];
4538
4539         struct mlx5_ifc_tisc_bits tis_context;
4540 };
4541
4542 struct mlx5_ifc_query_tis_in_bits {
4543         u8         opcode[0x10];
4544         u8         reserved_at_10[0x10];
4545
4546         u8         reserved_at_20[0x10];
4547         u8         op_mod[0x10];
4548
4549         u8         reserved_at_40[0x8];
4550         u8         tisn[0x18];
4551
4552         u8         reserved_at_60[0x20];
4553 };
4554
4555 struct mlx5_ifc_query_tir_out_bits {
4556         u8         status[0x8];
4557         u8         reserved_at_8[0x18];
4558
4559         u8         syndrome[0x20];
4560
4561         u8         reserved_at_40[0xc0];
4562
4563         struct mlx5_ifc_tirc_bits tir_context;
4564 };
4565
4566 struct mlx5_ifc_query_tir_in_bits {
4567         u8         opcode[0x10];
4568         u8         reserved_at_10[0x10];
4569
4570         u8         reserved_at_20[0x10];
4571         u8         op_mod[0x10];
4572
4573         u8         reserved_at_40[0x8];
4574         u8         tirn[0x18];
4575
4576         u8         reserved_at_60[0x20];
4577 };
4578
4579 struct mlx5_ifc_query_srq_out_bits {
4580         u8         status[0x8];
4581         u8         reserved_at_8[0x18];
4582
4583         u8         syndrome[0x20];
4584
4585         u8         reserved_at_40[0x40];
4586
4587         struct mlx5_ifc_srqc_bits srq_context_entry;
4588
4589         u8         reserved_at_280[0x600];
4590
4591         u8         pas[0][0x40];
4592 };
4593
4594 struct mlx5_ifc_query_srq_in_bits {
4595         u8         opcode[0x10];
4596         u8         reserved_at_10[0x10];
4597
4598         u8         reserved_at_20[0x10];
4599         u8         op_mod[0x10];
4600
4601         u8         reserved_at_40[0x8];
4602         u8         srqn[0x18];
4603
4604         u8         reserved_at_60[0x20];
4605 };
4606
4607 struct mlx5_ifc_query_sq_out_bits {
4608         u8         status[0x8];
4609         u8         reserved_at_8[0x18];
4610
4611         u8         syndrome[0x20];
4612
4613         u8         reserved_at_40[0xc0];
4614
4615         struct mlx5_ifc_sqc_bits sq_context;
4616 };
4617
4618 struct mlx5_ifc_query_sq_in_bits {
4619         u8         opcode[0x10];
4620         u8         reserved_at_10[0x10];
4621
4622         u8         reserved_at_20[0x10];
4623         u8         op_mod[0x10];
4624
4625         u8         reserved_at_40[0x8];
4626         u8         sqn[0x18];
4627
4628         u8         reserved_at_60[0x20];
4629 };
4630
4631 struct mlx5_ifc_query_special_contexts_out_bits {
4632         u8         status[0x8];
4633         u8         reserved_at_8[0x18];
4634
4635         u8         syndrome[0x20];
4636
4637         u8         dump_fill_mkey[0x20];
4638
4639         u8         resd_lkey[0x20];
4640
4641         u8         null_mkey[0x20];
4642
4643         u8         reserved_at_a0[0x60];
4644 };
4645
4646 struct mlx5_ifc_query_special_contexts_in_bits {
4647         u8         opcode[0x10];
4648         u8         reserved_at_10[0x10];
4649
4650         u8         reserved_at_20[0x10];
4651         u8         op_mod[0x10];
4652
4653         u8         reserved_at_40[0x40];
4654 };
4655
4656 struct mlx5_ifc_query_scheduling_element_out_bits {
4657         u8         opcode[0x10];
4658         u8         reserved_at_10[0x10];
4659
4660         u8         reserved_at_20[0x10];
4661         u8         op_mod[0x10];
4662
4663         u8         reserved_at_40[0xc0];
4664
4665         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4666
4667         u8         reserved_at_300[0x100];
4668 };
4669
4670 enum {
4671         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4672 };
4673
4674 struct mlx5_ifc_query_scheduling_element_in_bits {
4675         u8         opcode[0x10];
4676         u8         reserved_at_10[0x10];
4677
4678         u8         reserved_at_20[0x10];
4679         u8         op_mod[0x10];
4680
4681         u8         scheduling_hierarchy[0x8];
4682         u8         reserved_at_48[0x18];
4683
4684         u8         scheduling_element_id[0x20];
4685
4686         u8         reserved_at_80[0x180];
4687 };
4688
4689 struct mlx5_ifc_query_rqt_out_bits {
4690         u8         status[0x8];
4691         u8         reserved_at_8[0x18];
4692
4693         u8         syndrome[0x20];
4694
4695         u8         reserved_at_40[0xc0];
4696
4697         struct mlx5_ifc_rqtc_bits rqt_context;
4698 };
4699
4700 struct mlx5_ifc_query_rqt_in_bits {
4701         u8         opcode[0x10];
4702         u8         reserved_at_10[0x10];
4703
4704         u8         reserved_at_20[0x10];
4705         u8         op_mod[0x10];
4706
4707         u8         reserved_at_40[0x8];
4708         u8         rqtn[0x18];
4709
4710         u8         reserved_at_60[0x20];
4711 };
4712
4713 struct mlx5_ifc_query_rq_out_bits {
4714         u8         status[0x8];
4715         u8         reserved_at_8[0x18];
4716
4717         u8         syndrome[0x20];
4718
4719         u8         reserved_at_40[0xc0];
4720
4721         struct mlx5_ifc_rqc_bits rq_context;
4722 };
4723
4724 struct mlx5_ifc_query_rq_in_bits {
4725         u8         opcode[0x10];
4726         u8         reserved_at_10[0x10];
4727
4728         u8         reserved_at_20[0x10];
4729         u8         op_mod[0x10];
4730
4731         u8         reserved_at_40[0x8];
4732         u8         rqn[0x18];
4733
4734         u8         reserved_at_60[0x20];
4735 };
4736
4737 struct mlx5_ifc_query_roce_address_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x40];
4744
4745         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4746 };
4747
4748 struct mlx5_ifc_query_roce_address_in_bits {
4749         u8         opcode[0x10];
4750         u8         reserved_at_10[0x10];
4751
4752         u8         reserved_at_20[0x10];
4753         u8         op_mod[0x10];
4754
4755         u8         roce_address_index[0x10];
4756         u8         reserved_at_50[0xc];
4757         u8         vhca_port_num[0x4];
4758
4759         u8         reserved_at_60[0x20];
4760 };
4761
4762 struct mlx5_ifc_query_rmp_out_bits {
4763         u8         status[0x8];
4764         u8         reserved_at_8[0x18];
4765
4766         u8         syndrome[0x20];
4767
4768         u8         reserved_at_40[0xc0];
4769
4770         struct mlx5_ifc_rmpc_bits rmp_context;
4771 };
4772
4773 struct mlx5_ifc_query_rmp_in_bits {
4774         u8         opcode[0x10];
4775         u8         reserved_at_10[0x10];
4776
4777         u8         reserved_at_20[0x10];
4778         u8         op_mod[0x10];
4779
4780         u8         reserved_at_40[0x8];
4781         u8         rmpn[0x18];
4782
4783         u8         reserved_at_60[0x20];
4784 };
4785
4786 struct mlx5_ifc_query_qp_out_bits {
4787         u8         status[0x8];
4788         u8         reserved_at_8[0x18];
4789
4790         u8         syndrome[0x20];
4791
4792         u8         reserved_at_40[0x40];
4793
4794         u8         opt_param_mask[0x20];
4795
4796         u8         reserved_at_a0[0x20];
4797
4798         struct mlx5_ifc_qpc_bits qpc;
4799
4800         u8         reserved_at_800[0x80];
4801
4802         u8         pas[0][0x40];
4803 };
4804
4805 struct mlx5_ifc_query_qp_in_bits {
4806         u8         opcode[0x10];
4807         u8         reserved_at_10[0x10];
4808
4809         u8         reserved_at_20[0x10];
4810         u8         op_mod[0x10];
4811
4812         u8         reserved_at_40[0x8];
4813         u8         qpn[0x18];
4814
4815         u8         reserved_at_60[0x20];
4816 };
4817
4818 struct mlx5_ifc_query_q_counter_out_bits {
4819         u8         status[0x8];
4820         u8         reserved_at_8[0x18];
4821
4822         u8         syndrome[0x20];
4823
4824         u8         reserved_at_40[0x40];
4825
4826         u8         rx_write_requests[0x20];
4827
4828         u8         reserved_at_a0[0x20];
4829
4830         u8         rx_read_requests[0x20];
4831
4832         u8         reserved_at_e0[0x20];
4833
4834         u8         rx_atomic_requests[0x20];
4835
4836         u8         reserved_at_120[0x20];
4837
4838         u8         rx_dct_connect[0x20];
4839
4840         u8         reserved_at_160[0x20];
4841
4842         u8         out_of_buffer[0x20];
4843
4844         u8         reserved_at_1a0[0x20];
4845
4846         u8         out_of_sequence[0x20];
4847
4848         u8         reserved_at_1e0[0x20];
4849
4850         u8         duplicate_request[0x20];
4851
4852         u8         reserved_at_220[0x20];
4853
4854         u8         rnr_nak_retry_err[0x20];
4855
4856         u8         reserved_at_260[0x20];
4857
4858         u8         packet_seq_err[0x20];
4859
4860         u8         reserved_at_2a0[0x20];
4861
4862         u8         implied_nak_seq_err[0x20];
4863
4864         u8         reserved_at_2e0[0x20];
4865
4866         u8         local_ack_timeout_err[0x20];
4867
4868         u8         reserved_at_320[0xa0];
4869
4870         u8         resp_local_length_error[0x20];
4871
4872         u8         req_local_length_error[0x20];
4873
4874         u8         resp_local_qp_error[0x20];
4875
4876         u8         local_operation_error[0x20];
4877
4878         u8         resp_local_protection[0x20];
4879
4880         u8         req_local_protection[0x20];
4881
4882         u8         resp_cqe_error[0x20];
4883
4884         u8         req_cqe_error[0x20];
4885
4886         u8         req_mw_binding[0x20];
4887
4888         u8         req_bad_response[0x20];
4889
4890         u8         req_remote_invalid_request[0x20];
4891
4892         u8         resp_remote_invalid_request[0x20];
4893
4894         u8         req_remote_access_errors[0x20];
4895
4896         u8         resp_remote_access_errors[0x20];
4897
4898         u8         req_remote_operation_errors[0x20];
4899
4900         u8         req_transport_retries_exceeded[0x20];
4901
4902         u8         cq_overflow[0x20];
4903
4904         u8         resp_cqe_flush_error[0x20];
4905
4906         u8         req_cqe_flush_error[0x20];
4907
4908         u8         reserved_at_620[0x20];
4909
4910         u8         roce_adp_retrans[0x20];
4911
4912         u8         roce_adp_retrans_to[0x20];
4913
4914         u8         roce_slow_restart[0x20];
4915
4916         u8         roce_slow_restart_cnps[0x20];
4917
4918         u8         roce_slow_restart_trans[0x20];
4919
4920         u8         reserved_at_6e0[0x120];
4921 };
4922
4923 struct mlx5_ifc_query_q_counter_in_bits {
4924         u8         opcode[0x10];
4925         u8         reserved_at_10[0x10];
4926
4927         u8         reserved_at_20[0x10];
4928         u8         op_mod[0x10];
4929
4930         u8         reserved_at_40[0x80];
4931
4932         u8         clear[0x1];
4933         u8         reserved_at_c1[0x1f];
4934
4935         u8         reserved_at_e0[0x18];
4936         u8         counter_set_id[0x8];
4937 };
4938
4939 struct mlx5_ifc_query_pages_out_bits {
4940         u8         status[0x8];
4941         u8         reserved_at_8[0x18];
4942
4943         u8         syndrome[0x20];
4944
4945         u8         embedded_cpu_function[0x1];
4946         u8         reserved_at_41[0xf];
4947         u8         function_id[0x10];
4948
4949         u8         num_pages[0x20];
4950 };
4951
4952 enum {
4953         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4954         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4955         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4956 };
4957
4958 struct mlx5_ifc_query_pages_in_bits {
4959         u8         opcode[0x10];
4960         u8         reserved_at_10[0x10];
4961
4962         u8         reserved_at_20[0x10];
4963         u8         op_mod[0x10];
4964
4965         u8         embedded_cpu_function[0x1];
4966         u8         reserved_at_41[0xf];
4967         u8         function_id[0x10];
4968
4969         u8         reserved_at_60[0x20];
4970 };
4971
4972 struct mlx5_ifc_query_nic_vport_context_out_bits {
4973         u8         status[0x8];
4974         u8         reserved_at_8[0x18];
4975
4976         u8         syndrome[0x20];
4977
4978         u8         reserved_at_40[0x40];
4979
4980         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4981 };
4982
4983 struct mlx5_ifc_query_nic_vport_context_in_bits {
4984         u8         opcode[0x10];
4985         u8         reserved_at_10[0x10];
4986
4987         u8         reserved_at_20[0x10];
4988         u8         op_mod[0x10];
4989
4990         u8         other_vport[0x1];
4991         u8         reserved_at_41[0xf];
4992         u8         vport_number[0x10];
4993
4994         u8         reserved_at_60[0x5];
4995         u8         allowed_list_type[0x3];
4996         u8         reserved_at_68[0x18];
4997 };
4998
4999 struct mlx5_ifc_query_mkey_out_bits {
5000         u8         status[0x8];
5001         u8         reserved_at_8[0x18];
5002
5003         u8         syndrome[0x20];
5004
5005         u8         reserved_at_40[0x40];
5006
5007         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5008
5009         u8         reserved_at_280[0x600];
5010
5011         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5012
5013         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5014 };
5015
5016 struct mlx5_ifc_query_mkey_in_bits {
5017         u8         opcode[0x10];
5018         u8         reserved_at_10[0x10];
5019
5020         u8         reserved_at_20[0x10];
5021         u8         op_mod[0x10];
5022
5023         u8         reserved_at_40[0x8];
5024         u8         mkey_index[0x18];
5025
5026         u8         pg_access[0x1];
5027         u8         reserved_at_61[0x1f];
5028 };
5029
5030 struct mlx5_ifc_query_mad_demux_out_bits {
5031         u8         status[0x8];
5032         u8         reserved_at_8[0x18];
5033
5034         u8         syndrome[0x20];
5035
5036         u8         reserved_at_40[0x40];
5037
5038         u8         mad_dumux_parameters_block[0x20];
5039 };
5040
5041 struct mlx5_ifc_query_mad_demux_in_bits {
5042         u8         opcode[0x10];
5043         u8         reserved_at_10[0x10];
5044
5045         u8         reserved_at_20[0x10];
5046         u8         op_mod[0x10];
5047
5048         u8         reserved_at_40[0x40];
5049 };
5050
5051 struct mlx5_ifc_query_l2_table_entry_out_bits {
5052         u8         status[0x8];
5053         u8         reserved_at_8[0x18];
5054
5055         u8         syndrome[0x20];
5056
5057         u8         reserved_at_40[0xa0];
5058
5059         u8         reserved_at_e0[0x13];
5060         u8         vlan_valid[0x1];
5061         u8         vlan[0xc];
5062
5063         struct mlx5_ifc_mac_address_layout_bits mac_address;
5064
5065         u8         reserved_at_140[0xc0];
5066 };
5067
5068 struct mlx5_ifc_query_l2_table_entry_in_bits {
5069         u8         opcode[0x10];
5070         u8         reserved_at_10[0x10];
5071
5072         u8         reserved_at_20[0x10];
5073         u8         op_mod[0x10];
5074
5075         u8         reserved_at_40[0x60];
5076
5077         u8         reserved_at_a0[0x8];
5078         u8         table_index[0x18];
5079
5080         u8         reserved_at_c0[0x140];
5081 };
5082
5083 struct mlx5_ifc_query_issi_out_bits {
5084         u8         status[0x8];
5085         u8         reserved_at_8[0x18];
5086
5087         u8         syndrome[0x20];
5088
5089         u8         reserved_at_40[0x10];
5090         u8         current_issi[0x10];
5091
5092         u8         reserved_at_60[0xa0];
5093
5094         u8         reserved_at_100[76][0x8];
5095         u8         supported_issi_dw0[0x20];
5096 };
5097
5098 struct mlx5_ifc_query_issi_in_bits {
5099         u8         opcode[0x10];
5100         u8         reserved_at_10[0x10];
5101
5102         u8         reserved_at_20[0x10];
5103         u8         op_mod[0x10];
5104
5105         u8         reserved_at_40[0x40];
5106 };
5107
5108 struct mlx5_ifc_set_driver_version_out_bits {
5109         u8         status[0x8];
5110         u8         reserved_0[0x18];
5111
5112         u8         syndrome[0x20];
5113         u8         reserved_1[0x40];
5114 };
5115
5116 struct mlx5_ifc_set_driver_version_in_bits {
5117         u8         opcode[0x10];
5118         u8         reserved_0[0x10];
5119
5120         u8         reserved_1[0x10];
5121         u8         op_mod[0x10];
5122
5123         u8         reserved_2[0x40];
5124         u8         driver_version[64][0x8];
5125 };
5126
5127 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5128         u8         status[0x8];
5129         u8         reserved_at_8[0x18];
5130
5131         u8         syndrome[0x20];
5132
5133         u8         reserved_at_40[0x40];
5134
5135         struct mlx5_ifc_pkey_bits pkey[0];
5136 };
5137
5138 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5139         u8         opcode[0x10];
5140         u8         reserved_at_10[0x10];
5141
5142         u8         reserved_at_20[0x10];
5143         u8         op_mod[0x10];
5144
5145         u8         other_vport[0x1];
5146         u8         reserved_at_41[0xb];
5147         u8         port_num[0x4];
5148         u8         vport_number[0x10];
5149
5150         u8         reserved_at_60[0x10];
5151         u8         pkey_index[0x10];
5152 };
5153
5154 enum {
5155         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5156         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5157         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5158 };
5159
5160 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5161         u8         status[0x8];
5162         u8         reserved_at_8[0x18];
5163
5164         u8         syndrome[0x20];
5165
5166         u8         reserved_at_40[0x20];
5167
5168         u8         gids_num[0x10];
5169         u8         reserved_at_70[0x10];
5170
5171         struct mlx5_ifc_array128_auto_bits gid[0];
5172 };
5173
5174 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5175         u8         opcode[0x10];
5176         u8         reserved_at_10[0x10];
5177
5178         u8         reserved_at_20[0x10];
5179         u8         op_mod[0x10];
5180
5181         u8         other_vport[0x1];
5182         u8         reserved_at_41[0xb];
5183         u8         port_num[0x4];
5184         u8         vport_number[0x10];
5185
5186         u8         reserved_at_60[0x10];
5187         u8         gid_index[0x10];
5188 };
5189
5190 struct mlx5_ifc_query_hca_vport_context_out_bits {
5191         u8         status[0x8];
5192         u8         reserved_at_8[0x18];
5193
5194         u8         syndrome[0x20];
5195
5196         u8         reserved_at_40[0x40];
5197
5198         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5199 };
5200
5201 struct mlx5_ifc_query_hca_vport_context_in_bits {
5202         u8         opcode[0x10];
5203         u8         reserved_at_10[0x10];
5204
5205         u8         reserved_at_20[0x10];
5206         u8         op_mod[0x10];
5207
5208         u8         other_vport[0x1];
5209         u8         reserved_at_41[0xb];
5210         u8         port_num[0x4];
5211         u8         vport_number[0x10];
5212
5213         u8         reserved_at_60[0x20];
5214 };
5215
5216 struct mlx5_ifc_query_hca_cap_out_bits {
5217         u8         status[0x8];
5218         u8         reserved_at_8[0x18];
5219
5220         u8         syndrome[0x20];
5221
5222         u8         reserved_at_40[0x40];
5223
5224         union mlx5_ifc_hca_cap_union_bits capability;
5225 };
5226
5227 struct mlx5_ifc_query_hca_cap_in_bits {
5228         u8         opcode[0x10];
5229         u8         reserved_at_10[0x10];
5230
5231         u8         reserved_at_20[0x10];
5232         u8         op_mod[0x10];
5233
5234         u8         other_function[0x1];
5235         u8         reserved_at_41[0xf];
5236         u8         function_id[0x10];
5237
5238         u8         reserved_at_60[0x20];
5239 };
5240
5241 struct mlx5_ifc_other_hca_cap_bits {
5242         u8         roce[0x1];
5243         u8         reserved_at_1[0x27f];
5244 };
5245
5246 struct mlx5_ifc_query_other_hca_cap_out_bits {
5247         u8         status[0x8];
5248         u8         reserved_at_8[0x18];
5249
5250         u8         syndrome[0x20];
5251
5252         u8         reserved_at_40[0x40];
5253
5254         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5255 };
5256
5257 struct mlx5_ifc_query_other_hca_cap_in_bits {
5258         u8         opcode[0x10];
5259         u8         reserved_at_10[0x10];
5260
5261         u8         reserved_at_20[0x10];
5262         u8         op_mod[0x10];
5263
5264         u8         reserved_at_40[0x10];
5265         u8         function_id[0x10];
5266
5267         u8         reserved_at_60[0x20];
5268 };
5269
5270 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5271         u8         status[0x8];
5272         u8         reserved_at_8[0x18];
5273
5274         u8         syndrome[0x20];
5275
5276         u8         reserved_at_40[0x40];
5277 };
5278
5279 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5280         u8         opcode[0x10];
5281         u8         reserved_at_10[0x10];
5282
5283         u8         reserved_at_20[0x10];
5284         u8         op_mod[0x10];
5285
5286         u8         reserved_at_40[0x10];
5287         u8         function_id[0x10];
5288         u8         field_select[0x20];
5289
5290         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5291 };
5292
5293 struct mlx5_ifc_flow_table_context_bits {
5294         u8         reformat_en[0x1];
5295         u8         decap_en[0x1];
5296         u8         sw_owner[0x1];
5297         u8         termination_table[0x1];
5298         u8         table_miss_action[0x4];
5299         u8         level[0x8];
5300         u8         reserved_at_10[0x8];
5301         u8         log_size[0x8];
5302
5303         u8         reserved_at_20[0x8];
5304         u8         table_miss_id[0x18];
5305
5306         u8         reserved_at_40[0x8];
5307         u8         lag_master_next_table_id[0x18];
5308
5309         u8         reserved_at_60[0x60];
5310
5311         u8         sw_owner_icm_root_1[0x40];
5312
5313         u8         sw_owner_icm_root_0[0x40];
5314
5315 };
5316
5317 struct mlx5_ifc_query_flow_table_out_bits {
5318         u8         status[0x8];
5319         u8         reserved_at_8[0x18];
5320
5321         u8         syndrome[0x20];
5322
5323         u8         reserved_at_40[0x80];
5324
5325         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5326 };
5327
5328 struct mlx5_ifc_query_flow_table_in_bits {
5329         u8         opcode[0x10];
5330         u8         reserved_at_10[0x10];
5331
5332         u8         reserved_at_20[0x10];
5333         u8         op_mod[0x10];
5334
5335         u8         reserved_at_40[0x40];
5336
5337         u8         table_type[0x8];
5338         u8         reserved_at_88[0x18];
5339
5340         u8         reserved_at_a0[0x8];
5341         u8         table_id[0x18];
5342
5343         u8         reserved_at_c0[0x140];
5344 };
5345
5346 struct mlx5_ifc_query_fte_out_bits {
5347         u8         status[0x8];
5348         u8         reserved_at_8[0x18];
5349
5350         u8         syndrome[0x20];
5351
5352         u8         reserved_at_40[0x1c0];
5353
5354         struct mlx5_ifc_flow_context_bits flow_context;
5355 };
5356
5357 struct mlx5_ifc_query_fte_in_bits {
5358         u8         opcode[0x10];
5359         u8         reserved_at_10[0x10];
5360
5361         u8         reserved_at_20[0x10];
5362         u8         op_mod[0x10];
5363
5364         u8         reserved_at_40[0x40];
5365
5366         u8         table_type[0x8];
5367         u8         reserved_at_88[0x18];
5368
5369         u8         reserved_at_a0[0x8];
5370         u8         table_id[0x18];
5371
5372         u8         reserved_at_c0[0x40];
5373
5374         u8         flow_index[0x20];
5375
5376         u8         reserved_at_120[0xe0];
5377 };
5378
5379 enum {
5380         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5381         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5382         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5383         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5384         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5385 };
5386
5387 struct mlx5_ifc_query_flow_group_out_bits {
5388         u8         status[0x8];
5389         u8         reserved_at_8[0x18];
5390
5391         u8         syndrome[0x20];
5392
5393         u8         reserved_at_40[0xa0];
5394
5395         u8         start_flow_index[0x20];
5396
5397         u8         reserved_at_100[0x20];
5398
5399         u8         end_flow_index[0x20];
5400
5401         u8         reserved_at_140[0xa0];
5402
5403         u8         reserved_at_1e0[0x18];
5404         u8         match_criteria_enable[0x8];
5405
5406         struct mlx5_ifc_fte_match_param_bits match_criteria;
5407
5408         u8         reserved_at_1200[0xe00];
5409 };
5410
5411 struct mlx5_ifc_query_flow_group_in_bits {
5412         u8         opcode[0x10];
5413         u8         reserved_at_10[0x10];
5414
5415         u8         reserved_at_20[0x10];
5416         u8         op_mod[0x10];
5417
5418         u8         reserved_at_40[0x40];
5419
5420         u8         table_type[0x8];
5421         u8         reserved_at_88[0x18];
5422
5423         u8         reserved_at_a0[0x8];
5424         u8         table_id[0x18];
5425
5426         u8         group_id[0x20];
5427
5428         u8         reserved_at_e0[0x120];
5429 };
5430
5431 struct mlx5_ifc_query_flow_counter_out_bits {
5432         u8         status[0x8];
5433         u8         reserved_at_8[0x18];
5434
5435         u8         syndrome[0x20];
5436
5437         u8         reserved_at_40[0x40];
5438
5439         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5440 };
5441
5442 struct mlx5_ifc_query_flow_counter_in_bits {
5443         u8         opcode[0x10];
5444         u8         reserved_at_10[0x10];
5445
5446         u8         reserved_at_20[0x10];
5447         u8         op_mod[0x10];
5448
5449         u8         reserved_at_40[0x80];
5450
5451         u8         clear[0x1];
5452         u8         reserved_at_c1[0xf];
5453         u8         num_of_counters[0x10];
5454
5455         u8         flow_counter_id[0x20];
5456 };
5457
5458 struct mlx5_ifc_query_esw_vport_context_out_bits {
5459         u8         status[0x8];
5460         u8         reserved_at_8[0x18];
5461
5462         u8         syndrome[0x20];
5463
5464         u8         reserved_at_40[0x40];
5465
5466         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5467 };
5468
5469 struct mlx5_ifc_query_esw_vport_context_in_bits {
5470         u8         opcode[0x10];
5471         u8         reserved_at_10[0x10];
5472
5473         u8         reserved_at_20[0x10];
5474         u8         op_mod[0x10];
5475
5476         u8         other_vport[0x1];
5477         u8         reserved_at_41[0xf];
5478         u8         vport_number[0x10];
5479
5480         u8         reserved_at_60[0x20];
5481 };
5482
5483 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5484         u8         status[0x8];
5485         u8         reserved_at_8[0x18];
5486
5487         u8         syndrome[0x20];
5488
5489         u8         reserved_at_40[0x40];
5490 };
5491
5492 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5493         u8         reserved_at_0[0x1b];
5494         u8         fdb_to_vport_reg_c_id[0x1];
5495         u8         vport_cvlan_insert[0x1];
5496         u8         vport_svlan_insert[0x1];
5497         u8         vport_cvlan_strip[0x1];
5498         u8         vport_svlan_strip[0x1];
5499 };
5500
5501 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5502         u8         opcode[0x10];
5503         u8         reserved_at_10[0x10];
5504
5505         u8         reserved_at_20[0x10];
5506         u8         op_mod[0x10];
5507
5508         u8         other_vport[0x1];
5509         u8         reserved_at_41[0xf];
5510         u8         vport_number[0x10];
5511
5512         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5513
5514         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5515 };
5516
5517 struct mlx5_ifc_query_eq_out_bits {
5518         u8         status[0x8];
5519         u8         reserved_at_8[0x18];
5520
5521         u8         syndrome[0x20];
5522
5523         u8         reserved_at_40[0x40];
5524
5525         struct mlx5_ifc_eqc_bits eq_context_entry;
5526
5527         u8         reserved_at_280[0x40];
5528
5529         u8         event_bitmask[0x40];
5530
5531         u8         reserved_at_300[0x580];
5532
5533         u8         pas[0][0x40];
5534 };
5535
5536 struct mlx5_ifc_query_eq_in_bits {
5537         u8         opcode[0x10];
5538         u8         reserved_at_10[0x10];
5539
5540         u8         reserved_at_20[0x10];
5541         u8         op_mod[0x10];
5542
5543         u8         reserved_at_40[0x18];
5544         u8         eq_number[0x8];
5545
5546         u8         reserved_at_60[0x20];
5547 };
5548
5549 struct mlx5_ifc_packet_reformat_context_in_bits {
5550         u8         reserved_at_0[0x5];
5551         u8         reformat_type[0x3];
5552         u8         reserved_at_8[0xe];
5553         u8         reformat_data_size[0xa];
5554
5555         u8         reserved_at_20[0x10];
5556         u8         reformat_data[2][0x8];
5557
5558         u8         more_reformat_data[0][0x8];
5559 };
5560
5561 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5562         u8         status[0x8];
5563         u8         reserved_at_8[0x18];
5564
5565         u8         syndrome[0x20];
5566
5567         u8         reserved_at_40[0xa0];
5568
5569         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5570 };
5571
5572 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5573         u8         opcode[0x10];
5574         u8         reserved_at_10[0x10];
5575
5576         u8         reserved_at_20[0x10];
5577         u8         op_mod[0x10];
5578
5579         u8         packet_reformat_id[0x20];
5580
5581         u8         reserved_at_60[0xa0];
5582 };
5583
5584 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5585         u8         status[0x8];
5586         u8         reserved_at_8[0x18];
5587
5588         u8         syndrome[0x20];
5589
5590         u8         packet_reformat_id[0x20];
5591
5592         u8         reserved_at_60[0x20];
5593 };
5594
5595 enum mlx5_reformat_ctx_type {
5596         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5597         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5598         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5599         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5600         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5601 };
5602
5603 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5604         u8         opcode[0x10];
5605         u8         reserved_at_10[0x10];
5606
5607         u8         reserved_at_20[0x10];
5608         u8         op_mod[0x10];
5609
5610         u8         reserved_at_40[0xa0];
5611
5612         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5613 };
5614
5615 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5616         u8         status[0x8];
5617         u8         reserved_at_8[0x18];
5618
5619         u8         syndrome[0x20];
5620
5621         u8         reserved_at_40[0x40];
5622 };
5623
5624 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5625         u8         opcode[0x10];
5626         u8         reserved_at_10[0x10];
5627
5628         u8         reserved_20[0x10];
5629         u8         op_mod[0x10];
5630
5631         u8         packet_reformat_id[0x20];
5632
5633         u8         reserved_60[0x20];
5634 };
5635
5636 struct mlx5_ifc_set_action_in_bits {
5637         u8         action_type[0x4];
5638         u8         field[0xc];
5639         u8         reserved_at_10[0x3];
5640         u8         offset[0x5];
5641         u8         reserved_at_18[0x3];
5642         u8         length[0x5];
5643
5644         u8         data[0x20];
5645 };
5646
5647 struct mlx5_ifc_add_action_in_bits {
5648         u8         action_type[0x4];
5649         u8         field[0xc];
5650         u8         reserved_at_10[0x10];
5651
5652         u8         data[0x20];
5653 };
5654
5655 struct mlx5_ifc_copy_action_in_bits {
5656         u8         action_type[0x4];
5657         u8         src_field[0xc];
5658         u8         reserved_at_10[0x3];
5659         u8         src_offset[0x5];
5660         u8         reserved_at_18[0x3];
5661         u8         length[0x5];
5662
5663         u8         reserved_at_20[0x4];
5664         u8         dst_field[0xc];
5665         u8         reserved_at_30[0x3];
5666         u8         dst_offset[0x5];
5667         u8         reserved_at_38[0x8];
5668 };
5669
5670 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5671         struct mlx5_ifc_set_action_in_bits set_action_in;
5672         struct mlx5_ifc_add_action_in_bits add_action_in;
5673         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5674         u8         reserved_at_0[0x40];
5675 };
5676
5677 enum {
5678         MLX5_ACTION_TYPE_SET   = 0x1,
5679         MLX5_ACTION_TYPE_ADD   = 0x2,
5680         MLX5_ACTION_TYPE_COPY  = 0x3,
5681 };
5682
5683 enum {
5684         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5685         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5686         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5687         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5688         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5689         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5690         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5691         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5692         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5693         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5694         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5695         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5696         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5697         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5698         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5699         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5700         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5701         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5702         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5703         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5704         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5705         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5706         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5707         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5708         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5709         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5710         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5711         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5712         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5713         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5714         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5715         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5716         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5717         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5718         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5719         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5720 };
5721
5722 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5723         u8         status[0x8];
5724         u8         reserved_at_8[0x18];
5725
5726         u8         syndrome[0x20];
5727
5728         u8         modify_header_id[0x20];
5729
5730         u8         reserved_at_60[0x20];
5731 };
5732
5733 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5734         u8         opcode[0x10];
5735         u8         reserved_at_10[0x10];
5736
5737         u8         reserved_at_20[0x10];
5738         u8         op_mod[0x10];
5739
5740         u8         reserved_at_40[0x20];
5741
5742         u8         table_type[0x8];
5743         u8         reserved_at_68[0x10];
5744         u8         num_of_actions[0x8];
5745
5746         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5747 };
5748
5749 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5750         u8         status[0x8];
5751         u8         reserved_at_8[0x18];
5752
5753         u8         syndrome[0x20];
5754
5755         u8         reserved_at_40[0x40];
5756 };
5757
5758 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5759         u8         opcode[0x10];
5760         u8         reserved_at_10[0x10];
5761
5762         u8         reserved_at_20[0x10];
5763         u8         op_mod[0x10];
5764
5765         u8         modify_header_id[0x20];
5766
5767         u8         reserved_at_60[0x20];
5768 };
5769
5770 struct mlx5_ifc_query_dct_out_bits {
5771         u8         status[0x8];
5772         u8         reserved_at_8[0x18];
5773
5774         u8         syndrome[0x20];
5775
5776         u8         reserved_at_40[0x40];
5777
5778         struct mlx5_ifc_dctc_bits dct_context_entry;
5779
5780         u8         reserved_at_280[0x180];
5781 };
5782
5783 struct mlx5_ifc_query_dct_in_bits {
5784         u8         opcode[0x10];
5785         u8         reserved_at_10[0x10];
5786
5787         u8         reserved_at_20[0x10];
5788         u8         op_mod[0x10];
5789
5790         u8         reserved_at_40[0x8];
5791         u8         dctn[0x18];
5792
5793         u8         reserved_at_60[0x20];
5794 };
5795
5796 struct mlx5_ifc_query_cq_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_at_8[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_at_40[0x40];
5803
5804         struct mlx5_ifc_cqc_bits cq_context;
5805
5806         u8         reserved_at_280[0x600];
5807
5808         u8         pas[0][0x40];
5809 };
5810
5811 struct mlx5_ifc_query_cq_in_bits {
5812         u8         opcode[0x10];
5813         u8         reserved_at_10[0x10];
5814
5815         u8         reserved_at_20[0x10];
5816         u8         op_mod[0x10];
5817
5818         u8         reserved_at_40[0x8];
5819         u8         cqn[0x18];
5820
5821         u8         reserved_at_60[0x20];
5822 };
5823
5824 struct mlx5_ifc_query_cong_status_out_bits {
5825         u8         status[0x8];
5826         u8         reserved_at_8[0x18];
5827
5828         u8         syndrome[0x20];
5829
5830         u8         reserved_at_40[0x20];
5831
5832         u8         enable[0x1];
5833         u8         tag_enable[0x1];
5834         u8         reserved_at_62[0x1e];
5835 };
5836
5837 struct mlx5_ifc_query_cong_status_in_bits {
5838         u8         opcode[0x10];
5839         u8         reserved_at_10[0x10];
5840
5841         u8         reserved_at_20[0x10];
5842         u8         op_mod[0x10];
5843
5844         u8         reserved_at_40[0x18];
5845         u8         priority[0x4];
5846         u8         cong_protocol[0x4];
5847
5848         u8         reserved_at_60[0x20];
5849 };
5850
5851 struct mlx5_ifc_query_cong_statistics_out_bits {
5852         u8         status[0x8];
5853         u8         reserved_at_8[0x18];
5854
5855         u8         syndrome[0x20];
5856
5857         u8         reserved_at_40[0x40];
5858
5859         u8         rp_cur_flows[0x20];
5860
5861         u8         sum_flows[0x20];
5862
5863         u8         rp_cnp_ignored_high[0x20];
5864
5865         u8         rp_cnp_ignored_low[0x20];
5866
5867         u8         rp_cnp_handled_high[0x20];
5868
5869         u8         rp_cnp_handled_low[0x20];
5870
5871         u8         reserved_at_140[0x100];
5872
5873         u8         time_stamp_high[0x20];
5874
5875         u8         time_stamp_low[0x20];
5876
5877         u8         accumulators_period[0x20];
5878
5879         u8         np_ecn_marked_roce_packets_high[0x20];
5880
5881         u8         np_ecn_marked_roce_packets_low[0x20];
5882
5883         u8         np_cnp_sent_high[0x20];
5884
5885         u8         np_cnp_sent_low[0x20];
5886
5887         u8         reserved_at_320[0x560];
5888 };
5889
5890 struct mlx5_ifc_query_cong_statistics_in_bits {
5891         u8         opcode[0x10];
5892         u8         reserved_at_10[0x10];
5893
5894         u8         reserved_at_20[0x10];
5895         u8         op_mod[0x10];
5896
5897         u8         clear[0x1];
5898         u8         reserved_at_41[0x1f];
5899
5900         u8         reserved_at_60[0x20];
5901 };
5902
5903 struct mlx5_ifc_query_cong_params_out_bits {
5904         u8         status[0x8];
5905         u8         reserved_at_8[0x18];
5906
5907         u8         syndrome[0x20];
5908
5909         u8         reserved_at_40[0x40];
5910
5911         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5912 };
5913
5914 struct mlx5_ifc_query_cong_params_in_bits {
5915         u8         opcode[0x10];
5916         u8         reserved_at_10[0x10];
5917
5918         u8         reserved_at_20[0x10];
5919         u8         op_mod[0x10];
5920
5921         u8         reserved_at_40[0x1c];
5922         u8         cong_protocol[0x4];
5923
5924         u8         reserved_at_60[0x20];
5925 };
5926
5927 struct mlx5_ifc_query_adapter_out_bits {
5928         u8         status[0x8];
5929         u8         reserved_at_8[0x18];
5930
5931         u8         syndrome[0x20];
5932
5933         u8         reserved_at_40[0x40];
5934
5935         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5936 };
5937
5938 struct mlx5_ifc_query_adapter_in_bits {
5939         u8         opcode[0x10];
5940         u8         reserved_at_10[0x10];
5941
5942         u8         reserved_at_20[0x10];
5943         u8         op_mod[0x10];
5944
5945         u8         reserved_at_40[0x40];
5946 };
5947
5948 struct mlx5_ifc_qp_2rst_out_bits {
5949         u8         status[0x8];
5950         u8         reserved_at_8[0x18];
5951
5952         u8         syndrome[0x20];
5953
5954         u8         reserved_at_40[0x40];
5955 };
5956
5957 struct mlx5_ifc_qp_2rst_in_bits {
5958         u8         opcode[0x10];
5959         u8         uid[0x10];
5960
5961         u8         reserved_at_20[0x10];
5962         u8         op_mod[0x10];
5963
5964         u8         reserved_at_40[0x8];
5965         u8         qpn[0x18];
5966
5967         u8         reserved_at_60[0x20];
5968 };
5969
5970 struct mlx5_ifc_qp_2err_out_bits {
5971         u8         status[0x8];
5972         u8         reserved_at_8[0x18];
5973
5974         u8         syndrome[0x20];
5975
5976         u8         reserved_at_40[0x40];
5977 };
5978
5979 struct mlx5_ifc_qp_2err_in_bits {
5980         u8         opcode[0x10];
5981         u8         uid[0x10];
5982
5983         u8         reserved_at_20[0x10];
5984         u8         op_mod[0x10];
5985
5986         u8         reserved_at_40[0x8];
5987         u8         qpn[0x18];
5988
5989         u8         reserved_at_60[0x20];
5990 };
5991
5992 struct mlx5_ifc_page_fault_resume_out_bits {
5993         u8         status[0x8];
5994         u8         reserved_at_8[0x18];
5995
5996         u8         syndrome[0x20];
5997
5998         u8         reserved_at_40[0x40];
5999 };
6000
6001 struct mlx5_ifc_page_fault_resume_in_bits {
6002         u8         opcode[0x10];
6003         u8         reserved_at_10[0x10];
6004
6005         u8         reserved_at_20[0x10];
6006         u8         op_mod[0x10];
6007
6008         u8         error[0x1];
6009         u8         reserved_at_41[0x4];
6010         u8         page_fault_type[0x3];
6011         u8         wq_number[0x18];
6012
6013         u8         reserved_at_60[0x8];
6014         u8         token[0x18];
6015 };
6016
6017 struct mlx5_ifc_nop_out_bits {
6018         u8         status[0x8];
6019         u8         reserved_at_8[0x18];
6020
6021         u8         syndrome[0x20];
6022
6023         u8         reserved_at_40[0x40];
6024 };
6025
6026 struct mlx5_ifc_nop_in_bits {
6027         u8         opcode[0x10];
6028         u8         reserved_at_10[0x10];
6029
6030         u8         reserved_at_20[0x10];
6031         u8         op_mod[0x10];
6032
6033         u8         reserved_at_40[0x40];
6034 };
6035
6036 struct mlx5_ifc_modify_vport_state_out_bits {
6037         u8         status[0x8];
6038         u8         reserved_at_8[0x18];
6039
6040         u8         syndrome[0x20];
6041
6042         u8         reserved_at_40[0x40];
6043 };
6044
6045 struct mlx5_ifc_modify_vport_state_in_bits {
6046         u8         opcode[0x10];
6047         u8         reserved_at_10[0x10];
6048
6049         u8         reserved_at_20[0x10];
6050         u8         op_mod[0x10];
6051
6052         u8         other_vport[0x1];
6053         u8         reserved_at_41[0xf];
6054         u8         vport_number[0x10];
6055
6056         u8         reserved_at_60[0x18];
6057         u8         admin_state[0x4];
6058         u8         reserved_at_7c[0x4];
6059 };
6060
6061 struct mlx5_ifc_modify_tis_out_bits {
6062         u8         status[0x8];
6063         u8         reserved_at_8[0x18];
6064
6065         u8         syndrome[0x20];
6066
6067         u8         reserved_at_40[0x40];
6068 };
6069
6070 struct mlx5_ifc_modify_tis_bitmask_bits {
6071         u8         reserved_at_0[0x20];
6072
6073         u8         reserved_at_20[0x1d];
6074         u8         lag_tx_port_affinity[0x1];
6075         u8         strict_lag_tx_port_affinity[0x1];
6076         u8         prio[0x1];
6077 };
6078
6079 struct mlx5_ifc_modify_tis_in_bits {
6080         u8         opcode[0x10];
6081         u8         uid[0x10];
6082
6083         u8         reserved_at_20[0x10];
6084         u8         op_mod[0x10];
6085
6086         u8         reserved_at_40[0x8];
6087         u8         tisn[0x18];
6088
6089         u8         reserved_at_60[0x20];
6090
6091         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6092
6093         u8         reserved_at_c0[0x40];
6094
6095         struct mlx5_ifc_tisc_bits ctx;
6096 };
6097
6098 struct mlx5_ifc_modify_tir_bitmask_bits {
6099         u8         reserved_at_0[0x20];
6100
6101         u8         reserved_at_20[0x1b];
6102         u8         self_lb_en[0x1];
6103         u8         reserved_at_3c[0x1];
6104         u8         hash[0x1];
6105         u8         reserved_at_3e[0x1];
6106         u8         lro[0x1];
6107 };
6108
6109 struct mlx5_ifc_modify_tir_out_bits {
6110         u8         status[0x8];
6111         u8         reserved_at_8[0x18];
6112
6113         u8         syndrome[0x20];
6114
6115         u8         reserved_at_40[0x40];
6116 };
6117
6118 struct mlx5_ifc_modify_tir_in_bits {
6119         u8         opcode[0x10];
6120         u8         uid[0x10];
6121
6122         u8         reserved_at_20[0x10];
6123         u8         op_mod[0x10];
6124
6125         u8         reserved_at_40[0x8];
6126         u8         tirn[0x18];
6127
6128         u8         reserved_at_60[0x20];
6129
6130         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6131
6132         u8         reserved_at_c0[0x40];
6133
6134         struct mlx5_ifc_tirc_bits ctx;
6135 };
6136
6137 struct mlx5_ifc_modify_sq_out_bits {
6138         u8         status[0x8];
6139         u8         reserved_at_8[0x18];
6140
6141         u8         syndrome[0x20];
6142
6143         u8         reserved_at_40[0x40];
6144 };
6145
6146 struct mlx5_ifc_modify_sq_in_bits {
6147         u8         opcode[0x10];
6148         u8         uid[0x10];
6149
6150         u8         reserved_at_20[0x10];
6151         u8         op_mod[0x10];
6152
6153         u8         sq_state[0x4];
6154         u8         reserved_at_44[0x4];
6155         u8         sqn[0x18];
6156
6157         u8         reserved_at_60[0x20];
6158
6159         u8         modify_bitmask[0x40];
6160
6161         u8         reserved_at_c0[0x40];
6162
6163         struct mlx5_ifc_sqc_bits ctx;
6164 };
6165
6166 struct mlx5_ifc_modify_scheduling_element_out_bits {
6167         u8         status[0x8];
6168         u8         reserved_at_8[0x18];
6169
6170         u8         syndrome[0x20];
6171
6172         u8         reserved_at_40[0x1c0];
6173 };
6174
6175 enum {
6176         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6177         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6178 };
6179
6180 struct mlx5_ifc_modify_scheduling_element_in_bits {
6181         u8         opcode[0x10];
6182         u8         reserved_at_10[0x10];
6183
6184         u8         reserved_at_20[0x10];
6185         u8         op_mod[0x10];
6186
6187         u8         scheduling_hierarchy[0x8];
6188         u8         reserved_at_48[0x18];
6189
6190         u8         scheduling_element_id[0x20];
6191
6192         u8         reserved_at_80[0x20];
6193
6194         u8         modify_bitmask[0x20];
6195
6196         u8         reserved_at_c0[0x40];
6197
6198         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6199
6200         u8         reserved_at_300[0x100];
6201 };
6202
6203 struct mlx5_ifc_modify_rqt_out_bits {
6204         u8         status[0x8];
6205         u8         reserved_at_8[0x18];
6206
6207         u8         syndrome[0x20];
6208
6209         u8         reserved_at_40[0x40];
6210 };
6211
6212 struct mlx5_ifc_rqt_bitmask_bits {
6213         u8         reserved_at_0[0x20];
6214
6215         u8         reserved_at_20[0x1f];
6216         u8         rqn_list[0x1];
6217 };
6218
6219 struct mlx5_ifc_modify_rqt_in_bits {
6220         u8         opcode[0x10];
6221         u8         uid[0x10];
6222
6223         u8         reserved_at_20[0x10];
6224         u8         op_mod[0x10];
6225
6226         u8         reserved_at_40[0x8];
6227         u8         rqtn[0x18];
6228
6229         u8         reserved_at_60[0x20];
6230
6231         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6232
6233         u8         reserved_at_c0[0x40];
6234
6235         struct mlx5_ifc_rqtc_bits ctx;
6236 };
6237
6238 struct mlx5_ifc_modify_rq_out_bits {
6239         u8         status[0x8];
6240         u8         reserved_at_8[0x18];
6241
6242         u8         syndrome[0x20];
6243
6244         u8         reserved_at_40[0x40];
6245 };
6246
6247 enum {
6248         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6249         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6250         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6251 };
6252
6253 struct mlx5_ifc_modify_rq_in_bits {
6254         u8         opcode[0x10];
6255         u8         uid[0x10];
6256
6257         u8         reserved_at_20[0x10];
6258         u8         op_mod[0x10];
6259
6260         u8         rq_state[0x4];
6261         u8         reserved_at_44[0x4];
6262         u8         rqn[0x18];
6263
6264         u8         reserved_at_60[0x20];
6265
6266         u8         modify_bitmask[0x40];
6267
6268         u8         reserved_at_c0[0x40];
6269
6270         struct mlx5_ifc_rqc_bits ctx;
6271 };
6272
6273 struct mlx5_ifc_modify_rmp_out_bits {
6274         u8         status[0x8];
6275         u8         reserved_at_8[0x18];
6276
6277         u8         syndrome[0x20];
6278
6279         u8         reserved_at_40[0x40];
6280 };
6281
6282 struct mlx5_ifc_rmp_bitmask_bits {
6283         u8         reserved_at_0[0x20];
6284
6285         u8         reserved_at_20[0x1f];
6286         u8         lwm[0x1];
6287 };
6288
6289 struct mlx5_ifc_modify_rmp_in_bits {
6290         u8         opcode[0x10];
6291         u8         uid[0x10];
6292
6293         u8         reserved_at_20[0x10];
6294         u8         op_mod[0x10];
6295
6296         u8         rmp_state[0x4];
6297         u8         reserved_at_44[0x4];
6298         u8         rmpn[0x18];
6299
6300         u8         reserved_at_60[0x20];
6301
6302         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6303
6304         u8         reserved_at_c0[0x40];
6305
6306         struct mlx5_ifc_rmpc_bits ctx;
6307 };
6308
6309 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6310         u8         status[0x8];
6311         u8         reserved_at_8[0x18];
6312
6313         u8         syndrome[0x20];
6314
6315         u8         reserved_at_40[0x40];
6316 };
6317
6318 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6319         u8         reserved_at_0[0x12];
6320         u8         affiliation[0x1];
6321         u8         reserved_at_13[0x1];
6322         u8         disable_uc_local_lb[0x1];
6323         u8         disable_mc_local_lb[0x1];
6324         u8         node_guid[0x1];
6325         u8         port_guid[0x1];
6326         u8         min_inline[0x1];
6327         u8         mtu[0x1];
6328         u8         change_event[0x1];
6329         u8         promisc[0x1];
6330         u8         permanent_address[0x1];
6331         u8         addresses_list[0x1];
6332         u8         roce_en[0x1];
6333         u8         reserved_at_1f[0x1];
6334 };
6335
6336 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6337         u8         opcode[0x10];
6338         u8         reserved_at_10[0x10];
6339
6340         u8         reserved_at_20[0x10];
6341         u8         op_mod[0x10];
6342
6343         u8         other_vport[0x1];
6344         u8         reserved_at_41[0xf];
6345         u8         vport_number[0x10];
6346
6347         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6348
6349         u8         reserved_at_80[0x780];
6350
6351         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6352 };
6353
6354 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6355         u8         status[0x8];
6356         u8         reserved_at_8[0x18];
6357
6358         u8         syndrome[0x20];
6359
6360         u8         reserved_at_40[0x40];
6361 };
6362
6363 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6364         u8         opcode[0x10];
6365         u8         reserved_at_10[0x10];
6366
6367         u8         reserved_at_20[0x10];
6368         u8         op_mod[0x10];
6369
6370         u8         other_vport[0x1];
6371         u8         reserved_at_41[0xb];
6372         u8         port_num[0x4];
6373         u8         vport_number[0x10];
6374
6375         u8         reserved_at_60[0x20];
6376
6377         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6378 };
6379
6380 struct mlx5_ifc_modify_cq_out_bits {
6381         u8         status[0x8];
6382         u8         reserved_at_8[0x18];
6383
6384         u8         syndrome[0x20];
6385
6386         u8         reserved_at_40[0x40];
6387 };
6388
6389 enum {
6390         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6391         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6392 };
6393
6394 struct mlx5_ifc_modify_cq_in_bits {
6395         u8         opcode[0x10];
6396         u8         uid[0x10];
6397
6398         u8         reserved_at_20[0x10];
6399         u8         op_mod[0x10];
6400
6401         u8         reserved_at_40[0x8];
6402         u8         cqn[0x18];
6403
6404         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6405
6406         struct mlx5_ifc_cqc_bits cq_context;
6407
6408         u8         reserved_at_280[0x60];
6409
6410         u8         cq_umem_valid[0x1];
6411         u8         reserved_at_2e1[0x1f];
6412
6413         u8         reserved_at_300[0x580];
6414
6415         u8         pas[0][0x40];
6416 };
6417
6418 struct mlx5_ifc_modify_cong_status_out_bits {
6419         u8         status[0x8];
6420         u8         reserved_at_8[0x18];
6421
6422         u8         syndrome[0x20];
6423
6424         u8         reserved_at_40[0x40];
6425 };
6426
6427 struct mlx5_ifc_modify_cong_status_in_bits {
6428         u8         opcode[0x10];
6429         u8         reserved_at_10[0x10];
6430
6431         u8         reserved_at_20[0x10];
6432         u8         op_mod[0x10];
6433
6434         u8         reserved_at_40[0x18];
6435         u8         priority[0x4];
6436         u8         cong_protocol[0x4];
6437
6438         u8         enable[0x1];
6439         u8         tag_enable[0x1];
6440         u8         reserved_at_62[0x1e];
6441 };
6442
6443 struct mlx5_ifc_modify_cong_params_out_bits {
6444         u8         status[0x8];
6445         u8         reserved_at_8[0x18];
6446
6447         u8         syndrome[0x20];
6448
6449         u8         reserved_at_40[0x40];
6450 };
6451
6452 struct mlx5_ifc_modify_cong_params_in_bits {
6453         u8         opcode[0x10];
6454         u8         reserved_at_10[0x10];
6455
6456         u8         reserved_at_20[0x10];
6457         u8         op_mod[0x10];
6458
6459         u8         reserved_at_40[0x1c];
6460         u8         cong_protocol[0x4];
6461
6462         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6463
6464         u8         reserved_at_80[0x80];
6465
6466         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6467 };
6468
6469 struct mlx5_ifc_manage_pages_out_bits {
6470         u8         status[0x8];
6471         u8         reserved_at_8[0x18];
6472
6473         u8         syndrome[0x20];
6474
6475         u8         output_num_entries[0x20];
6476
6477         u8         reserved_at_60[0x20];
6478
6479         u8         pas[0][0x40];
6480 };
6481
6482 enum {
6483         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6484         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6485         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6486 };
6487
6488 struct mlx5_ifc_manage_pages_in_bits {
6489         u8         opcode[0x10];
6490         u8         reserved_at_10[0x10];
6491
6492         u8         reserved_at_20[0x10];
6493         u8         op_mod[0x10];
6494
6495         u8         embedded_cpu_function[0x1];
6496         u8         reserved_at_41[0xf];
6497         u8         function_id[0x10];
6498
6499         u8         input_num_entries[0x20];
6500
6501         u8         pas[0][0x40];
6502 };
6503
6504 struct mlx5_ifc_mad_ifc_out_bits {
6505         u8         status[0x8];
6506         u8         reserved_at_8[0x18];
6507
6508         u8         syndrome[0x20];
6509
6510         u8         reserved_at_40[0x40];
6511
6512         u8         response_mad_packet[256][0x8];
6513 };
6514
6515 struct mlx5_ifc_mad_ifc_in_bits {
6516         u8         opcode[0x10];
6517         u8         reserved_at_10[0x10];
6518
6519         u8         reserved_at_20[0x10];
6520         u8         op_mod[0x10];
6521
6522         u8         remote_lid[0x10];
6523         u8         reserved_at_50[0x8];
6524         u8         port[0x8];
6525
6526         u8         reserved_at_60[0x20];
6527
6528         u8         mad[256][0x8];
6529 };
6530
6531 struct mlx5_ifc_init_hca_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x40];
6538 };
6539
6540 struct mlx5_ifc_init_hca_in_bits {
6541         u8         opcode[0x10];
6542         u8         reserved_at_10[0x10];
6543
6544         u8         reserved_at_20[0x10];
6545         u8         op_mod[0x10];
6546
6547         u8         reserved_at_40[0x40];
6548         u8         sw_owner_id[4][0x20];
6549 };
6550
6551 struct mlx5_ifc_init2rtr_qp_out_bits {
6552         u8         status[0x8];
6553         u8         reserved_at_8[0x18];
6554
6555         u8         syndrome[0x20];
6556
6557         u8         reserved_at_40[0x40];
6558 };
6559
6560 struct mlx5_ifc_init2rtr_qp_in_bits {
6561         u8         opcode[0x10];
6562         u8         uid[0x10];
6563
6564         u8         reserved_at_20[0x10];
6565         u8         op_mod[0x10];
6566
6567         u8         reserved_at_40[0x8];
6568         u8         qpn[0x18];
6569
6570         u8         reserved_at_60[0x20];
6571
6572         u8         opt_param_mask[0x20];
6573
6574         u8         reserved_at_a0[0x20];
6575
6576         struct mlx5_ifc_qpc_bits qpc;
6577
6578         u8         reserved_at_800[0x80];
6579 };
6580
6581 struct mlx5_ifc_init2init_qp_out_bits {
6582         u8         status[0x8];
6583         u8         reserved_at_8[0x18];
6584
6585         u8         syndrome[0x20];
6586
6587         u8         reserved_at_40[0x40];
6588 };
6589
6590 struct mlx5_ifc_init2init_qp_in_bits {
6591         u8         opcode[0x10];
6592         u8         uid[0x10];
6593
6594         u8         reserved_at_20[0x10];
6595         u8         op_mod[0x10];
6596
6597         u8         reserved_at_40[0x8];
6598         u8         qpn[0x18];
6599
6600         u8         reserved_at_60[0x20];
6601
6602         u8         opt_param_mask[0x20];
6603
6604         u8         reserved_at_a0[0x20];
6605
6606         struct mlx5_ifc_qpc_bits qpc;
6607
6608         u8         reserved_at_800[0x80];
6609 };
6610
6611 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6612         u8         status[0x8];
6613         u8         reserved_at_8[0x18];
6614
6615         u8         syndrome[0x20];
6616
6617         u8         reserved_at_40[0x40];
6618
6619         u8         packet_headers_log[128][0x8];
6620
6621         u8         packet_syndrome[64][0x8];
6622 };
6623
6624 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6625         u8         opcode[0x10];
6626         u8         reserved_at_10[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x40];
6632 };
6633
6634 struct mlx5_ifc_gen_eqe_in_bits {
6635         u8         opcode[0x10];
6636         u8         reserved_at_10[0x10];
6637
6638         u8         reserved_at_20[0x10];
6639         u8         op_mod[0x10];
6640
6641         u8         reserved_at_40[0x18];
6642         u8         eq_number[0x8];
6643
6644         u8         reserved_at_60[0x20];
6645
6646         u8         eqe[64][0x8];
6647 };
6648
6649 struct mlx5_ifc_gen_eq_out_bits {
6650         u8         status[0x8];
6651         u8         reserved_at_8[0x18];
6652
6653         u8         syndrome[0x20];
6654
6655         u8         reserved_at_40[0x40];
6656 };
6657
6658 struct mlx5_ifc_enable_hca_out_bits {
6659         u8         status[0x8];
6660         u8         reserved_at_8[0x18];
6661
6662         u8         syndrome[0x20];
6663
6664         u8         reserved_at_40[0x20];
6665 };
6666
6667 struct mlx5_ifc_enable_hca_in_bits {
6668         u8         opcode[0x10];
6669         u8         reserved_at_10[0x10];
6670
6671         u8         reserved_at_20[0x10];
6672         u8         op_mod[0x10];
6673
6674         u8         embedded_cpu_function[0x1];
6675         u8         reserved_at_41[0xf];
6676         u8         function_id[0x10];
6677
6678         u8         reserved_at_60[0x20];
6679 };
6680
6681 struct mlx5_ifc_drain_dct_out_bits {
6682         u8         status[0x8];
6683         u8         reserved_at_8[0x18];
6684
6685         u8         syndrome[0x20];
6686
6687         u8         reserved_at_40[0x40];
6688 };
6689
6690 struct mlx5_ifc_drain_dct_in_bits {
6691         u8         opcode[0x10];
6692         u8         uid[0x10];
6693
6694         u8         reserved_at_20[0x10];
6695         u8         op_mod[0x10];
6696
6697         u8         reserved_at_40[0x8];
6698         u8         dctn[0x18];
6699
6700         u8         reserved_at_60[0x20];
6701 };
6702
6703 struct mlx5_ifc_disable_hca_out_bits {
6704         u8         status[0x8];
6705         u8         reserved_at_8[0x18];
6706
6707         u8         syndrome[0x20];
6708
6709         u8         reserved_at_40[0x20];
6710 };
6711
6712 struct mlx5_ifc_disable_hca_in_bits {
6713         u8         opcode[0x10];
6714         u8         reserved_at_10[0x10];
6715
6716         u8         reserved_at_20[0x10];
6717         u8         op_mod[0x10];
6718
6719         u8         embedded_cpu_function[0x1];
6720         u8         reserved_at_41[0xf];
6721         u8         function_id[0x10];
6722
6723         u8         reserved_at_60[0x20];
6724 };
6725
6726 struct mlx5_ifc_detach_from_mcg_out_bits {
6727         u8         status[0x8];
6728         u8         reserved_at_8[0x18];
6729
6730         u8         syndrome[0x20];
6731
6732         u8         reserved_at_40[0x40];
6733 };
6734
6735 struct mlx5_ifc_detach_from_mcg_in_bits {
6736         u8         opcode[0x10];
6737         u8         uid[0x10];
6738
6739         u8         reserved_at_20[0x10];
6740         u8         op_mod[0x10];
6741
6742         u8         reserved_at_40[0x8];
6743         u8         qpn[0x18];
6744
6745         u8         reserved_at_60[0x20];
6746
6747         u8         multicast_gid[16][0x8];
6748 };
6749
6750 struct mlx5_ifc_destroy_xrq_out_bits {
6751         u8         status[0x8];
6752         u8         reserved_at_8[0x18];
6753
6754         u8         syndrome[0x20];
6755
6756         u8         reserved_at_40[0x40];
6757 };
6758
6759 struct mlx5_ifc_destroy_xrq_in_bits {
6760         u8         opcode[0x10];
6761         u8         uid[0x10];
6762
6763         u8         reserved_at_20[0x10];
6764         u8         op_mod[0x10];
6765
6766         u8         reserved_at_40[0x8];
6767         u8         xrqn[0x18];
6768
6769         u8         reserved_at_60[0x20];
6770 };
6771
6772 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6773         u8         status[0x8];
6774         u8         reserved_at_8[0x18];
6775
6776         u8         syndrome[0x20];
6777
6778         u8         reserved_at_40[0x40];
6779 };
6780
6781 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6782         u8         opcode[0x10];
6783         u8         uid[0x10];
6784
6785         u8         reserved_at_20[0x10];
6786         u8         op_mod[0x10];
6787
6788         u8         reserved_at_40[0x8];
6789         u8         xrc_srqn[0x18];
6790
6791         u8         reserved_at_60[0x20];
6792 };
6793
6794 struct mlx5_ifc_destroy_tis_out_bits {
6795         u8         status[0x8];
6796         u8         reserved_at_8[0x18];
6797
6798         u8         syndrome[0x20];
6799
6800         u8         reserved_at_40[0x40];
6801 };
6802
6803 struct mlx5_ifc_destroy_tis_in_bits {
6804         u8         opcode[0x10];
6805         u8         uid[0x10];
6806
6807         u8         reserved_at_20[0x10];
6808         u8         op_mod[0x10];
6809
6810         u8         reserved_at_40[0x8];
6811         u8         tisn[0x18];
6812
6813         u8         reserved_at_60[0x20];
6814 };
6815
6816 struct mlx5_ifc_destroy_tir_out_bits {
6817         u8         status[0x8];
6818         u8         reserved_at_8[0x18];
6819
6820         u8         syndrome[0x20];
6821
6822         u8         reserved_at_40[0x40];
6823 };
6824
6825 struct mlx5_ifc_destroy_tir_in_bits {
6826         u8         opcode[0x10];
6827         u8         uid[0x10];
6828
6829         u8         reserved_at_20[0x10];
6830         u8         op_mod[0x10];
6831
6832         u8         reserved_at_40[0x8];
6833         u8         tirn[0x18];
6834
6835         u8         reserved_at_60[0x20];
6836 };
6837
6838 struct mlx5_ifc_destroy_srq_out_bits {
6839         u8         status[0x8];
6840         u8         reserved_at_8[0x18];
6841
6842         u8         syndrome[0x20];
6843
6844         u8         reserved_at_40[0x40];
6845 };
6846
6847 struct mlx5_ifc_destroy_srq_in_bits {
6848         u8         opcode[0x10];
6849         u8         uid[0x10];
6850
6851         u8         reserved_at_20[0x10];
6852         u8         op_mod[0x10];
6853
6854         u8         reserved_at_40[0x8];
6855         u8         srqn[0x18];
6856
6857         u8         reserved_at_60[0x20];
6858 };
6859
6860 struct mlx5_ifc_destroy_sq_out_bits {
6861         u8         status[0x8];
6862         u8         reserved_at_8[0x18];
6863
6864         u8         syndrome[0x20];
6865
6866         u8         reserved_at_40[0x40];
6867 };
6868
6869 struct mlx5_ifc_destroy_sq_in_bits {
6870         u8         opcode[0x10];
6871         u8         uid[0x10];
6872
6873         u8         reserved_at_20[0x10];
6874         u8         op_mod[0x10];
6875
6876         u8         reserved_at_40[0x8];
6877         u8         sqn[0x18];
6878
6879         u8         reserved_at_60[0x20];
6880 };
6881
6882 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6883         u8         status[0x8];
6884         u8         reserved_at_8[0x18];
6885
6886         u8         syndrome[0x20];
6887
6888         u8         reserved_at_40[0x1c0];
6889 };
6890
6891 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6892         u8         opcode[0x10];
6893         u8         reserved_at_10[0x10];
6894
6895         u8         reserved_at_20[0x10];
6896         u8         op_mod[0x10];
6897
6898         u8         scheduling_hierarchy[0x8];
6899         u8         reserved_at_48[0x18];
6900
6901         u8         scheduling_element_id[0x20];
6902
6903         u8         reserved_at_80[0x180];
6904 };
6905
6906 struct mlx5_ifc_destroy_rqt_out_bits {
6907         u8         status[0x8];
6908         u8         reserved_at_8[0x18];
6909
6910         u8         syndrome[0x20];
6911
6912         u8         reserved_at_40[0x40];
6913 };
6914
6915 struct mlx5_ifc_destroy_rqt_in_bits {
6916         u8         opcode[0x10];
6917         u8         uid[0x10];
6918
6919         u8         reserved_at_20[0x10];
6920         u8         op_mod[0x10];
6921
6922         u8         reserved_at_40[0x8];
6923         u8         rqtn[0x18];
6924
6925         u8         reserved_at_60[0x20];
6926 };
6927
6928 struct mlx5_ifc_destroy_rq_out_bits {
6929         u8         status[0x8];
6930         u8         reserved_at_8[0x18];
6931
6932         u8         syndrome[0x20];
6933
6934         u8         reserved_at_40[0x40];
6935 };
6936
6937 struct mlx5_ifc_destroy_rq_in_bits {
6938         u8         opcode[0x10];
6939         u8         uid[0x10];
6940
6941         u8         reserved_at_20[0x10];
6942         u8         op_mod[0x10];
6943
6944         u8         reserved_at_40[0x8];
6945         u8         rqn[0x18];
6946
6947         u8         reserved_at_60[0x20];
6948 };
6949
6950 struct mlx5_ifc_set_delay_drop_params_in_bits {
6951         u8         opcode[0x10];
6952         u8         reserved_at_10[0x10];
6953
6954         u8         reserved_at_20[0x10];
6955         u8         op_mod[0x10];
6956
6957         u8         reserved_at_40[0x20];
6958
6959         u8         reserved_at_60[0x10];
6960         u8         delay_drop_timeout[0x10];
6961 };
6962
6963 struct mlx5_ifc_set_delay_drop_params_out_bits {
6964         u8         status[0x8];
6965         u8         reserved_at_8[0x18];
6966
6967         u8         syndrome[0x20];
6968
6969         u8         reserved_at_40[0x40];
6970 };
6971
6972 struct mlx5_ifc_destroy_rmp_out_bits {
6973         u8         status[0x8];
6974         u8         reserved_at_8[0x18];
6975
6976         u8         syndrome[0x20];
6977
6978         u8         reserved_at_40[0x40];
6979 };
6980
6981 struct mlx5_ifc_destroy_rmp_in_bits {
6982         u8         opcode[0x10];
6983         u8         uid[0x10];
6984
6985         u8         reserved_at_20[0x10];
6986         u8         op_mod[0x10];
6987
6988         u8         reserved_at_40[0x8];
6989         u8         rmpn[0x18];
6990
6991         u8         reserved_at_60[0x20];
6992 };
6993
6994 struct mlx5_ifc_destroy_qp_out_bits {
6995         u8         status[0x8];
6996         u8         reserved_at_8[0x18];
6997
6998         u8         syndrome[0x20];
6999
7000         u8         reserved_at_40[0x40];
7001 };
7002
7003 struct mlx5_ifc_destroy_qp_in_bits {
7004         u8         opcode[0x10];
7005         u8         uid[0x10];
7006
7007         u8         reserved_at_20[0x10];
7008         u8         op_mod[0x10];
7009
7010         u8         reserved_at_40[0x8];
7011         u8         qpn[0x18];
7012
7013         u8         reserved_at_60[0x20];
7014 };
7015
7016 struct mlx5_ifc_destroy_psv_out_bits {
7017         u8         status[0x8];
7018         u8         reserved_at_8[0x18];
7019
7020         u8         syndrome[0x20];
7021
7022         u8         reserved_at_40[0x40];
7023 };
7024
7025 struct mlx5_ifc_destroy_psv_in_bits {
7026         u8         opcode[0x10];
7027         u8         reserved_at_10[0x10];
7028
7029         u8         reserved_at_20[0x10];
7030         u8         op_mod[0x10];
7031
7032         u8         reserved_at_40[0x8];
7033         u8         psvn[0x18];
7034
7035         u8         reserved_at_60[0x20];
7036 };
7037
7038 struct mlx5_ifc_destroy_mkey_out_bits {
7039         u8         status[0x8];
7040         u8         reserved_at_8[0x18];
7041
7042         u8         syndrome[0x20];
7043
7044         u8         reserved_at_40[0x40];
7045 };
7046
7047 struct mlx5_ifc_destroy_mkey_in_bits {
7048         u8         opcode[0x10];
7049         u8         reserved_at_10[0x10];
7050
7051         u8         reserved_at_20[0x10];
7052         u8         op_mod[0x10];
7053
7054         u8         reserved_at_40[0x8];
7055         u8         mkey_index[0x18];
7056
7057         u8         reserved_at_60[0x20];
7058 };
7059
7060 struct mlx5_ifc_destroy_flow_table_out_bits {
7061         u8         status[0x8];
7062         u8         reserved_at_8[0x18];
7063
7064         u8         syndrome[0x20];
7065
7066         u8         reserved_at_40[0x40];
7067 };
7068
7069 struct mlx5_ifc_destroy_flow_table_in_bits {
7070         u8         opcode[0x10];
7071         u8         reserved_at_10[0x10];
7072
7073         u8         reserved_at_20[0x10];
7074         u8         op_mod[0x10];
7075
7076         u8         other_vport[0x1];
7077         u8         reserved_at_41[0xf];
7078         u8         vport_number[0x10];
7079
7080         u8         reserved_at_60[0x20];
7081
7082         u8         table_type[0x8];
7083         u8         reserved_at_88[0x18];
7084
7085         u8         reserved_at_a0[0x8];
7086         u8         table_id[0x18];
7087
7088         u8         reserved_at_c0[0x140];
7089 };
7090
7091 struct mlx5_ifc_destroy_flow_group_out_bits {
7092         u8         status[0x8];
7093         u8         reserved_at_8[0x18];
7094
7095         u8         syndrome[0x20];
7096
7097         u8         reserved_at_40[0x40];
7098 };
7099
7100 struct mlx5_ifc_destroy_flow_group_in_bits {
7101         u8         opcode[0x10];
7102         u8         reserved_at_10[0x10];
7103
7104         u8         reserved_at_20[0x10];
7105         u8         op_mod[0x10];
7106
7107         u8         other_vport[0x1];
7108         u8         reserved_at_41[0xf];
7109         u8         vport_number[0x10];
7110
7111         u8         reserved_at_60[0x20];
7112
7113         u8         table_type[0x8];
7114         u8         reserved_at_88[0x18];
7115
7116         u8         reserved_at_a0[0x8];
7117         u8         table_id[0x18];
7118
7119         u8         group_id[0x20];
7120
7121         u8         reserved_at_e0[0x120];
7122 };
7123
7124 struct mlx5_ifc_destroy_eq_out_bits {
7125         u8         status[0x8];
7126         u8         reserved_at_8[0x18];
7127
7128         u8         syndrome[0x20];
7129
7130         u8         reserved_at_40[0x40];
7131 };
7132
7133 struct mlx5_ifc_destroy_eq_in_bits {
7134         u8         opcode[0x10];
7135         u8         reserved_at_10[0x10];
7136
7137         u8         reserved_at_20[0x10];
7138         u8         op_mod[0x10];
7139
7140         u8         reserved_at_40[0x18];
7141         u8         eq_number[0x8];
7142
7143         u8         reserved_at_60[0x20];
7144 };
7145
7146 struct mlx5_ifc_destroy_dct_out_bits {
7147         u8         status[0x8];
7148         u8         reserved_at_8[0x18];
7149
7150         u8         syndrome[0x20];
7151
7152         u8         reserved_at_40[0x40];
7153 };
7154
7155 struct mlx5_ifc_destroy_dct_in_bits {
7156         u8         opcode[0x10];
7157         u8         uid[0x10];
7158
7159         u8         reserved_at_20[0x10];
7160         u8         op_mod[0x10];
7161
7162         u8         reserved_at_40[0x8];
7163         u8         dctn[0x18];
7164
7165         u8         reserved_at_60[0x20];
7166 };
7167
7168 struct mlx5_ifc_destroy_cq_out_bits {
7169         u8         status[0x8];
7170         u8         reserved_at_8[0x18];
7171
7172         u8         syndrome[0x20];
7173
7174         u8         reserved_at_40[0x40];
7175 };
7176
7177 struct mlx5_ifc_destroy_cq_in_bits {
7178         u8         opcode[0x10];
7179         u8         uid[0x10];
7180
7181         u8         reserved_at_20[0x10];
7182         u8         op_mod[0x10];
7183
7184         u8         reserved_at_40[0x8];
7185         u8         cqn[0x18];
7186
7187         u8         reserved_at_60[0x20];
7188 };
7189
7190 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7191         u8         status[0x8];
7192         u8         reserved_at_8[0x18];
7193
7194         u8         syndrome[0x20];
7195
7196         u8         reserved_at_40[0x40];
7197 };
7198
7199 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7200         u8         opcode[0x10];
7201         u8         reserved_at_10[0x10];
7202
7203         u8         reserved_at_20[0x10];
7204         u8         op_mod[0x10];
7205
7206         u8         reserved_at_40[0x20];
7207
7208         u8         reserved_at_60[0x10];
7209         u8         vxlan_udp_port[0x10];
7210 };
7211
7212 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7213         u8         status[0x8];
7214         u8         reserved_at_8[0x18];
7215
7216         u8         syndrome[0x20];
7217
7218         u8         reserved_at_40[0x40];
7219 };
7220
7221 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7222         u8         opcode[0x10];
7223         u8         reserved_at_10[0x10];
7224
7225         u8         reserved_at_20[0x10];
7226         u8         op_mod[0x10];
7227
7228         u8         reserved_at_40[0x60];
7229
7230         u8         reserved_at_a0[0x8];
7231         u8         table_index[0x18];
7232
7233         u8         reserved_at_c0[0x140];
7234 };
7235
7236 struct mlx5_ifc_delete_fte_out_bits {
7237         u8         status[0x8];
7238         u8         reserved_at_8[0x18];
7239
7240         u8         syndrome[0x20];
7241
7242         u8         reserved_at_40[0x40];
7243 };
7244
7245 struct mlx5_ifc_delete_fte_in_bits {
7246         u8         opcode[0x10];
7247         u8         reserved_at_10[0x10];
7248
7249         u8         reserved_at_20[0x10];
7250         u8         op_mod[0x10];
7251
7252         u8         other_vport[0x1];
7253         u8         reserved_at_41[0xf];
7254         u8         vport_number[0x10];
7255
7256         u8         reserved_at_60[0x20];
7257
7258         u8         table_type[0x8];
7259         u8         reserved_at_88[0x18];
7260
7261         u8         reserved_at_a0[0x8];
7262         u8         table_id[0x18];
7263
7264         u8         reserved_at_c0[0x40];
7265
7266         u8         flow_index[0x20];
7267
7268         u8         reserved_at_120[0xe0];
7269 };
7270
7271 struct mlx5_ifc_dealloc_xrcd_out_bits {
7272         u8         status[0x8];
7273         u8         reserved_at_8[0x18];
7274
7275         u8         syndrome[0x20];
7276
7277         u8         reserved_at_40[0x40];
7278 };
7279
7280 struct mlx5_ifc_dealloc_xrcd_in_bits {
7281         u8         opcode[0x10];
7282         u8         uid[0x10];
7283
7284         u8         reserved_at_20[0x10];
7285         u8         op_mod[0x10];
7286
7287         u8         reserved_at_40[0x8];
7288         u8         xrcd[0x18];
7289
7290         u8         reserved_at_60[0x20];
7291 };
7292
7293 struct mlx5_ifc_dealloc_uar_out_bits {
7294         u8         status[0x8];
7295         u8         reserved_at_8[0x18];
7296
7297         u8         syndrome[0x20];
7298
7299         u8         reserved_at_40[0x40];
7300 };
7301
7302 struct mlx5_ifc_dealloc_uar_in_bits {
7303         u8         opcode[0x10];
7304         u8         reserved_at_10[0x10];
7305
7306         u8         reserved_at_20[0x10];
7307         u8         op_mod[0x10];
7308
7309         u8         reserved_at_40[0x8];
7310         u8         uar[0x18];
7311
7312         u8         reserved_at_60[0x20];
7313 };
7314
7315 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7316         u8         status[0x8];
7317         u8         reserved_at_8[0x18];
7318
7319         u8         syndrome[0x20];
7320
7321         u8         reserved_at_40[0x40];
7322 };
7323
7324 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7325         u8         opcode[0x10];
7326         u8         uid[0x10];
7327
7328         u8         reserved_at_20[0x10];
7329         u8         op_mod[0x10];
7330
7331         u8         reserved_at_40[0x8];
7332         u8         transport_domain[0x18];
7333
7334         u8         reserved_at_60[0x20];
7335 };
7336
7337 struct mlx5_ifc_dealloc_q_counter_out_bits {
7338         u8         status[0x8];
7339         u8         reserved_at_8[0x18];
7340
7341         u8         syndrome[0x20];
7342
7343         u8         reserved_at_40[0x40];
7344 };
7345
7346 struct mlx5_ifc_dealloc_q_counter_in_bits {
7347         u8         opcode[0x10];
7348         u8         reserved_at_10[0x10];
7349
7350         u8         reserved_at_20[0x10];
7351         u8         op_mod[0x10];
7352
7353         u8         reserved_at_40[0x18];
7354         u8         counter_set_id[0x8];
7355
7356         u8         reserved_at_60[0x20];
7357 };
7358
7359 struct mlx5_ifc_dealloc_pd_out_bits {
7360         u8         status[0x8];
7361         u8         reserved_at_8[0x18];
7362
7363         u8         syndrome[0x20];
7364
7365         u8         reserved_at_40[0x40];
7366 };
7367
7368 struct mlx5_ifc_dealloc_pd_in_bits {
7369         u8         opcode[0x10];
7370         u8         uid[0x10];
7371
7372         u8         reserved_at_20[0x10];
7373         u8         op_mod[0x10];
7374
7375         u8         reserved_at_40[0x8];
7376         u8         pd[0x18];
7377
7378         u8         reserved_at_60[0x20];
7379 };
7380
7381 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7382         u8         status[0x8];
7383         u8         reserved_at_8[0x18];
7384
7385         u8         syndrome[0x20];
7386
7387         u8         reserved_at_40[0x40];
7388 };
7389
7390 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7391         u8         opcode[0x10];
7392         u8         reserved_at_10[0x10];
7393
7394         u8         reserved_at_20[0x10];
7395         u8         op_mod[0x10];
7396
7397         u8         flow_counter_id[0x20];
7398
7399         u8         reserved_at_60[0x20];
7400 };
7401
7402 struct mlx5_ifc_create_xrq_out_bits {
7403         u8         status[0x8];
7404         u8         reserved_at_8[0x18];
7405
7406         u8         syndrome[0x20];
7407
7408         u8         reserved_at_40[0x8];
7409         u8         xrqn[0x18];
7410
7411         u8         reserved_at_60[0x20];
7412 };
7413
7414 struct mlx5_ifc_create_xrq_in_bits {
7415         u8         opcode[0x10];
7416         u8         uid[0x10];
7417
7418         u8         reserved_at_20[0x10];
7419         u8         op_mod[0x10];
7420
7421         u8         reserved_at_40[0x40];
7422
7423         struct mlx5_ifc_xrqc_bits xrq_context;
7424 };
7425
7426 struct mlx5_ifc_create_xrc_srq_out_bits {
7427         u8         status[0x8];
7428         u8         reserved_at_8[0x18];
7429
7430         u8         syndrome[0x20];
7431
7432         u8         reserved_at_40[0x8];
7433         u8         xrc_srqn[0x18];
7434
7435         u8         reserved_at_60[0x20];
7436 };
7437
7438 struct mlx5_ifc_create_xrc_srq_in_bits {
7439         u8         opcode[0x10];
7440         u8         uid[0x10];
7441
7442         u8         reserved_at_20[0x10];
7443         u8         op_mod[0x10];
7444
7445         u8         reserved_at_40[0x40];
7446
7447         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7448
7449         u8         reserved_at_280[0x60];
7450
7451         u8         xrc_srq_umem_valid[0x1];
7452         u8         reserved_at_2e1[0x1f];
7453
7454         u8         reserved_at_300[0x580];
7455
7456         u8         pas[0][0x40];
7457 };
7458
7459 struct mlx5_ifc_create_tis_out_bits {
7460         u8         status[0x8];
7461         u8         reserved_at_8[0x18];
7462
7463         u8         syndrome[0x20];
7464
7465         u8         reserved_at_40[0x8];
7466         u8         tisn[0x18];
7467
7468         u8         reserved_at_60[0x20];
7469 };
7470
7471 struct mlx5_ifc_create_tis_in_bits {
7472         u8         opcode[0x10];
7473         u8         uid[0x10];
7474
7475         u8         reserved_at_20[0x10];
7476         u8         op_mod[0x10];
7477
7478         u8         reserved_at_40[0xc0];
7479
7480         struct mlx5_ifc_tisc_bits ctx;
7481 };
7482
7483 struct mlx5_ifc_create_tir_out_bits {
7484         u8         status[0x8];
7485         u8         icm_address_63_40[0x18];
7486
7487         u8         syndrome[0x20];
7488
7489         u8         icm_address_39_32[0x8];
7490         u8         tirn[0x18];
7491
7492         u8         icm_address_31_0[0x20];
7493 };
7494
7495 struct mlx5_ifc_create_tir_in_bits {
7496         u8         opcode[0x10];
7497         u8         uid[0x10];
7498
7499         u8         reserved_at_20[0x10];
7500         u8         op_mod[0x10];
7501
7502         u8         reserved_at_40[0xc0];
7503
7504         struct mlx5_ifc_tirc_bits ctx;
7505 };
7506
7507 struct mlx5_ifc_create_srq_out_bits {
7508         u8         status[0x8];
7509         u8         reserved_at_8[0x18];
7510
7511         u8         syndrome[0x20];
7512
7513         u8         reserved_at_40[0x8];
7514         u8         srqn[0x18];
7515
7516         u8         reserved_at_60[0x20];
7517 };
7518
7519 struct mlx5_ifc_create_srq_in_bits {
7520         u8         opcode[0x10];
7521         u8         uid[0x10];
7522
7523         u8         reserved_at_20[0x10];
7524         u8         op_mod[0x10];
7525
7526         u8         reserved_at_40[0x40];
7527
7528         struct mlx5_ifc_srqc_bits srq_context_entry;
7529
7530         u8         reserved_at_280[0x600];
7531
7532         u8         pas[0][0x40];
7533 };
7534
7535 struct mlx5_ifc_create_sq_out_bits {
7536         u8         status[0x8];
7537         u8         reserved_at_8[0x18];
7538
7539         u8         syndrome[0x20];
7540
7541         u8         reserved_at_40[0x8];
7542         u8         sqn[0x18];
7543
7544         u8         reserved_at_60[0x20];
7545 };
7546
7547 struct mlx5_ifc_create_sq_in_bits {
7548         u8         opcode[0x10];
7549         u8         uid[0x10];
7550
7551         u8         reserved_at_20[0x10];
7552         u8         op_mod[0x10];
7553
7554         u8         reserved_at_40[0xc0];
7555
7556         struct mlx5_ifc_sqc_bits ctx;
7557 };
7558
7559 struct mlx5_ifc_create_scheduling_element_out_bits {
7560         u8         status[0x8];
7561         u8         reserved_at_8[0x18];
7562
7563         u8         syndrome[0x20];
7564
7565         u8         reserved_at_40[0x40];
7566
7567         u8         scheduling_element_id[0x20];
7568
7569         u8         reserved_at_a0[0x160];
7570 };
7571
7572 struct mlx5_ifc_create_scheduling_element_in_bits {
7573         u8         opcode[0x10];
7574         u8         reserved_at_10[0x10];
7575
7576         u8         reserved_at_20[0x10];
7577         u8         op_mod[0x10];
7578
7579         u8         scheduling_hierarchy[0x8];
7580         u8         reserved_at_48[0x18];
7581
7582         u8         reserved_at_60[0xa0];
7583
7584         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7585
7586         u8         reserved_at_300[0x100];
7587 };
7588
7589 struct mlx5_ifc_create_rqt_out_bits {
7590         u8         status[0x8];
7591         u8         reserved_at_8[0x18];
7592
7593         u8         syndrome[0x20];
7594
7595         u8         reserved_at_40[0x8];
7596         u8         rqtn[0x18];
7597
7598         u8         reserved_at_60[0x20];
7599 };
7600
7601 struct mlx5_ifc_create_rqt_in_bits {
7602         u8         opcode[0x10];
7603         u8         uid[0x10];
7604
7605         u8         reserved_at_20[0x10];
7606         u8         op_mod[0x10];
7607
7608         u8         reserved_at_40[0xc0];
7609
7610         struct mlx5_ifc_rqtc_bits rqt_context;
7611 };
7612
7613 struct mlx5_ifc_create_rq_out_bits {
7614         u8         status[0x8];
7615         u8         reserved_at_8[0x18];
7616
7617         u8         syndrome[0x20];
7618
7619         u8         reserved_at_40[0x8];
7620         u8         rqn[0x18];
7621
7622         u8         reserved_at_60[0x20];
7623 };
7624
7625 struct mlx5_ifc_create_rq_in_bits {
7626         u8         opcode[0x10];
7627         u8         uid[0x10];
7628
7629         u8         reserved_at_20[0x10];
7630         u8         op_mod[0x10];
7631
7632         u8         reserved_at_40[0xc0];
7633
7634         struct mlx5_ifc_rqc_bits ctx;
7635 };
7636
7637 struct mlx5_ifc_create_rmp_out_bits {
7638         u8         status[0x8];
7639         u8         reserved_at_8[0x18];
7640
7641         u8         syndrome[0x20];
7642
7643         u8         reserved_at_40[0x8];
7644         u8         rmpn[0x18];
7645
7646         u8         reserved_at_60[0x20];
7647 };
7648
7649 struct mlx5_ifc_create_rmp_in_bits {
7650         u8         opcode[0x10];
7651         u8         uid[0x10];
7652
7653         u8         reserved_at_20[0x10];
7654         u8         op_mod[0x10];
7655
7656         u8         reserved_at_40[0xc0];
7657
7658         struct mlx5_ifc_rmpc_bits ctx;
7659 };
7660
7661 struct mlx5_ifc_create_qp_out_bits {
7662         u8         status[0x8];
7663         u8         reserved_at_8[0x18];
7664
7665         u8         syndrome[0x20];
7666
7667         u8         reserved_at_40[0x8];
7668         u8         qpn[0x18];
7669
7670         u8         reserved_at_60[0x20];
7671 };
7672
7673 struct mlx5_ifc_create_qp_in_bits {
7674         u8         opcode[0x10];
7675         u8         uid[0x10];
7676
7677         u8         reserved_at_20[0x10];
7678         u8         op_mod[0x10];
7679
7680         u8         reserved_at_40[0x40];
7681
7682         u8         opt_param_mask[0x20];
7683
7684         u8         reserved_at_a0[0x20];
7685
7686         struct mlx5_ifc_qpc_bits qpc;
7687
7688         u8         reserved_at_800[0x60];
7689
7690         u8         wq_umem_valid[0x1];
7691         u8         reserved_at_861[0x1f];
7692
7693         u8         pas[0][0x40];
7694 };
7695
7696 struct mlx5_ifc_create_psv_out_bits {
7697         u8         status[0x8];
7698         u8         reserved_at_8[0x18];
7699
7700         u8         syndrome[0x20];
7701
7702         u8         reserved_at_40[0x40];
7703
7704         u8         reserved_at_80[0x8];
7705         u8         psv0_index[0x18];
7706
7707         u8         reserved_at_a0[0x8];
7708         u8         psv1_index[0x18];
7709
7710         u8         reserved_at_c0[0x8];
7711         u8         psv2_index[0x18];
7712
7713         u8         reserved_at_e0[0x8];
7714         u8         psv3_index[0x18];
7715 };
7716
7717 struct mlx5_ifc_create_psv_in_bits {
7718         u8         opcode[0x10];
7719         u8         reserved_at_10[0x10];
7720
7721         u8         reserved_at_20[0x10];
7722         u8         op_mod[0x10];
7723
7724         u8         num_psv[0x4];
7725         u8         reserved_at_44[0x4];
7726         u8         pd[0x18];
7727
7728         u8         reserved_at_60[0x20];
7729 };
7730
7731 struct mlx5_ifc_create_mkey_out_bits {
7732         u8         status[0x8];
7733         u8         reserved_at_8[0x18];
7734
7735         u8         syndrome[0x20];
7736
7737         u8         reserved_at_40[0x8];
7738         u8         mkey_index[0x18];
7739
7740         u8         reserved_at_60[0x20];
7741 };
7742
7743 struct mlx5_ifc_create_mkey_in_bits {
7744         u8         opcode[0x10];
7745         u8         reserved_at_10[0x10];
7746
7747         u8         reserved_at_20[0x10];
7748         u8         op_mod[0x10];
7749
7750         u8         reserved_at_40[0x20];
7751
7752         u8         pg_access[0x1];
7753         u8         mkey_umem_valid[0x1];
7754         u8         reserved_at_62[0x1e];
7755
7756         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7757
7758         u8         reserved_at_280[0x80];
7759
7760         u8         translations_octword_actual_size[0x20];
7761
7762         u8         reserved_at_320[0x560];
7763
7764         u8         klm_pas_mtt[0][0x20];
7765 };
7766
7767 enum {
7768         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7769         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7770         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7771         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7772         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7773         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7774         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7775 };
7776
7777 struct mlx5_ifc_create_flow_table_out_bits {
7778         u8         status[0x8];
7779         u8         icm_address_63_40[0x18];
7780
7781         u8         syndrome[0x20];
7782
7783         u8         icm_address_39_32[0x8];
7784         u8         table_id[0x18];
7785
7786         u8         icm_address_31_0[0x20];
7787 };
7788
7789 struct mlx5_ifc_create_flow_table_in_bits {
7790         u8         opcode[0x10];
7791         u8         reserved_at_10[0x10];
7792
7793         u8         reserved_at_20[0x10];
7794         u8         op_mod[0x10];
7795
7796         u8         other_vport[0x1];
7797         u8         reserved_at_41[0xf];
7798         u8         vport_number[0x10];
7799
7800         u8         reserved_at_60[0x20];
7801
7802         u8         table_type[0x8];
7803         u8         reserved_at_88[0x18];
7804
7805         u8         reserved_at_a0[0x20];
7806
7807         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7808 };
7809
7810 struct mlx5_ifc_create_flow_group_out_bits {
7811         u8         status[0x8];
7812         u8         reserved_at_8[0x18];
7813
7814         u8         syndrome[0x20];
7815
7816         u8         reserved_at_40[0x8];
7817         u8         group_id[0x18];
7818
7819         u8         reserved_at_60[0x20];
7820 };
7821
7822 enum {
7823         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7824         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7825         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7826         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7827 };
7828
7829 struct mlx5_ifc_create_flow_group_in_bits {
7830         u8         opcode[0x10];
7831         u8         reserved_at_10[0x10];
7832
7833         u8         reserved_at_20[0x10];
7834         u8         op_mod[0x10];
7835
7836         u8         other_vport[0x1];
7837         u8         reserved_at_41[0xf];
7838         u8         vport_number[0x10];
7839
7840         u8         reserved_at_60[0x20];
7841
7842         u8         table_type[0x8];
7843         u8         reserved_at_88[0x18];
7844
7845         u8         reserved_at_a0[0x8];
7846         u8         table_id[0x18];
7847
7848         u8         source_eswitch_owner_vhca_id_valid[0x1];
7849
7850         u8         reserved_at_c1[0x1f];
7851
7852         u8         start_flow_index[0x20];
7853
7854         u8         reserved_at_100[0x20];
7855
7856         u8         end_flow_index[0x20];
7857
7858         u8         reserved_at_140[0xa0];
7859
7860         u8         reserved_at_1e0[0x18];
7861         u8         match_criteria_enable[0x8];
7862
7863         struct mlx5_ifc_fte_match_param_bits match_criteria;
7864
7865         u8         reserved_at_1200[0xe00];
7866 };
7867
7868 struct mlx5_ifc_create_eq_out_bits {
7869         u8         status[0x8];
7870         u8         reserved_at_8[0x18];
7871
7872         u8         syndrome[0x20];
7873
7874         u8         reserved_at_40[0x18];
7875         u8         eq_number[0x8];
7876
7877         u8         reserved_at_60[0x20];
7878 };
7879
7880 struct mlx5_ifc_create_eq_in_bits {
7881         u8         opcode[0x10];
7882         u8         uid[0x10];
7883
7884         u8         reserved_at_20[0x10];
7885         u8         op_mod[0x10];
7886
7887         u8         reserved_at_40[0x40];
7888
7889         struct mlx5_ifc_eqc_bits eq_context_entry;
7890
7891         u8         reserved_at_280[0x40];
7892
7893         u8         event_bitmask[4][0x40];
7894
7895         u8         reserved_at_3c0[0x4c0];
7896
7897         u8         pas[0][0x40];
7898 };
7899
7900 struct mlx5_ifc_create_dct_out_bits {
7901         u8         status[0x8];
7902         u8         reserved_at_8[0x18];
7903
7904         u8         syndrome[0x20];
7905
7906         u8         reserved_at_40[0x8];
7907         u8         dctn[0x18];
7908
7909         u8         reserved_at_60[0x20];
7910 };
7911
7912 struct mlx5_ifc_create_dct_in_bits {
7913         u8         opcode[0x10];
7914         u8         uid[0x10];
7915
7916         u8         reserved_at_20[0x10];
7917         u8         op_mod[0x10];
7918
7919         u8         reserved_at_40[0x40];
7920
7921         struct mlx5_ifc_dctc_bits dct_context_entry;
7922
7923         u8         reserved_at_280[0x180];
7924 };
7925
7926 struct mlx5_ifc_create_cq_out_bits {
7927         u8         status[0x8];
7928         u8         reserved_at_8[0x18];
7929
7930         u8         syndrome[0x20];
7931
7932         u8         reserved_at_40[0x8];
7933         u8         cqn[0x18];
7934
7935         u8         reserved_at_60[0x20];
7936 };
7937
7938 struct mlx5_ifc_create_cq_in_bits {
7939         u8         opcode[0x10];
7940         u8         uid[0x10];
7941
7942         u8         reserved_at_20[0x10];
7943         u8         op_mod[0x10];
7944
7945         u8         reserved_at_40[0x40];
7946
7947         struct mlx5_ifc_cqc_bits cq_context;
7948
7949         u8         reserved_at_280[0x60];
7950
7951         u8         cq_umem_valid[0x1];
7952         u8         reserved_at_2e1[0x59f];
7953
7954         u8         pas[0][0x40];
7955 };
7956
7957 struct mlx5_ifc_config_int_moderation_out_bits {
7958         u8         status[0x8];
7959         u8         reserved_at_8[0x18];
7960
7961         u8         syndrome[0x20];
7962
7963         u8         reserved_at_40[0x4];
7964         u8         min_delay[0xc];
7965         u8         int_vector[0x10];
7966
7967         u8         reserved_at_60[0x20];
7968 };
7969
7970 enum {
7971         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7972         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7973 };
7974
7975 struct mlx5_ifc_config_int_moderation_in_bits {
7976         u8         opcode[0x10];
7977         u8         reserved_at_10[0x10];
7978
7979         u8         reserved_at_20[0x10];
7980         u8         op_mod[0x10];
7981
7982         u8         reserved_at_40[0x4];
7983         u8         min_delay[0xc];
7984         u8         int_vector[0x10];
7985
7986         u8         reserved_at_60[0x20];
7987 };
7988
7989 struct mlx5_ifc_attach_to_mcg_out_bits {
7990         u8         status[0x8];
7991         u8         reserved_at_8[0x18];
7992
7993         u8         syndrome[0x20];
7994
7995         u8         reserved_at_40[0x40];
7996 };
7997
7998 struct mlx5_ifc_attach_to_mcg_in_bits {
7999         u8         opcode[0x10];
8000         u8         uid[0x10];
8001
8002         u8         reserved_at_20[0x10];
8003         u8         op_mod[0x10];
8004
8005         u8         reserved_at_40[0x8];
8006         u8         qpn[0x18];
8007
8008         u8         reserved_at_60[0x20];
8009
8010         u8         multicast_gid[16][0x8];
8011 };
8012
8013 struct mlx5_ifc_arm_xrq_out_bits {
8014         u8         status[0x8];
8015         u8         reserved_at_8[0x18];
8016
8017         u8         syndrome[0x20];
8018
8019         u8         reserved_at_40[0x40];
8020 };
8021
8022 struct mlx5_ifc_arm_xrq_in_bits {
8023         u8         opcode[0x10];
8024         u8         reserved_at_10[0x10];
8025
8026         u8         reserved_at_20[0x10];
8027         u8         op_mod[0x10];
8028
8029         u8         reserved_at_40[0x8];
8030         u8         xrqn[0x18];
8031
8032         u8         reserved_at_60[0x10];
8033         u8         lwm[0x10];
8034 };
8035
8036 struct mlx5_ifc_arm_xrc_srq_out_bits {
8037         u8         status[0x8];
8038         u8         reserved_at_8[0x18];
8039
8040         u8         syndrome[0x20];
8041
8042         u8         reserved_at_40[0x40];
8043 };
8044
8045 enum {
8046         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8047 };
8048
8049 struct mlx5_ifc_arm_xrc_srq_in_bits {
8050         u8         opcode[0x10];
8051         u8         uid[0x10];
8052
8053         u8         reserved_at_20[0x10];
8054         u8         op_mod[0x10];
8055
8056         u8         reserved_at_40[0x8];
8057         u8         xrc_srqn[0x18];
8058
8059         u8         reserved_at_60[0x10];
8060         u8         lwm[0x10];
8061 };
8062
8063 struct mlx5_ifc_arm_rq_out_bits {
8064         u8         status[0x8];
8065         u8         reserved_at_8[0x18];
8066
8067         u8         syndrome[0x20];
8068
8069         u8         reserved_at_40[0x40];
8070 };
8071
8072 enum {
8073         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8074         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8075 };
8076
8077 struct mlx5_ifc_arm_rq_in_bits {
8078         u8         opcode[0x10];
8079         u8         uid[0x10];
8080
8081         u8         reserved_at_20[0x10];
8082         u8         op_mod[0x10];
8083
8084         u8         reserved_at_40[0x8];
8085         u8         srq_number[0x18];
8086
8087         u8         reserved_at_60[0x10];
8088         u8         lwm[0x10];
8089 };
8090
8091 struct mlx5_ifc_arm_dct_out_bits {
8092         u8         status[0x8];
8093         u8         reserved_at_8[0x18];
8094
8095         u8         syndrome[0x20];
8096
8097         u8         reserved_at_40[0x40];
8098 };
8099
8100 struct mlx5_ifc_arm_dct_in_bits {
8101         u8         opcode[0x10];
8102         u8         reserved_at_10[0x10];
8103
8104         u8         reserved_at_20[0x10];
8105         u8         op_mod[0x10];
8106
8107         u8         reserved_at_40[0x8];
8108         u8         dct_number[0x18];
8109
8110         u8         reserved_at_60[0x20];
8111 };
8112
8113 struct mlx5_ifc_alloc_xrcd_out_bits {
8114         u8         status[0x8];
8115         u8         reserved_at_8[0x18];
8116
8117         u8         syndrome[0x20];
8118
8119         u8         reserved_at_40[0x8];
8120         u8         xrcd[0x18];
8121
8122         u8         reserved_at_60[0x20];
8123 };
8124
8125 struct mlx5_ifc_alloc_xrcd_in_bits {
8126         u8         opcode[0x10];
8127         u8         uid[0x10];
8128
8129         u8         reserved_at_20[0x10];
8130         u8         op_mod[0x10];
8131
8132         u8         reserved_at_40[0x40];
8133 };
8134
8135 struct mlx5_ifc_alloc_uar_out_bits {
8136         u8         status[0x8];
8137         u8         reserved_at_8[0x18];
8138
8139         u8         syndrome[0x20];
8140
8141         u8         reserved_at_40[0x8];
8142         u8         uar[0x18];
8143
8144         u8         reserved_at_60[0x20];
8145 };
8146
8147 struct mlx5_ifc_alloc_uar_in_bits {
8148         u8         opcode[0x10];
8149         u8         reserved_at_10[0x10];
8150
8151         u8         reserved_at_20[0x10];
8152         u8         op_mod[0x10];
8153
8154         u8         reserved_at_40[0x40];
8155 };
8156
8157 struct mlx5_ifc_alloc_transport_domain_out_bits {
8158         u8         status[0x8];
8159         u8         reserved_at_8[0x18];
8160
8161         u8         syndrome[0x20];
8162
8163         u8         reserved_at_40[0x8];
8164         u8         transport_domain[0x18];
8165
8166         u8         reserved_at_60[0x20];
8167 };
8168
8169 struct mlx5_ifc_alloc_transport_domain_in_bits {
8170         u8         opcode[0x10];
8171         u8         uid[0x10];
8172
8173         u8         reserved_at_20[0x10];
8174         u8         op_mod[0x10];
8175
8176         u8         reserved_at_40[0x40];
8177 };
8178
8179 struct mlx5_ifc_alloc_q_counter_out_bits {
8180         u8         status[0x8];
8181         u8         reserved_at_8[0x18];
8182
8183         u8         syndrome[0x20];
8184
8185         u8         reserved_at_40[0x18];
8186         u8         counter_set_id[0x8];
8187
8188         u8         reserved_at_60[0x20];
8189 };
8190
8191 struct mlx5_ifc_alloc_q_counter_in_bits {
8192         u8         opcode[0x10];
8193         u8         uid[0x10];
8194
8195         u8         reserved_at_20[0x10];
8196         u8         op_mod[0x10];
8197
8198         u8         reserved_at_40[0x40];
8199 };
8200
8201 struct mlx5_ifc_alloc_pd_out_bits {
8202         u8         status[0x8];
8203         u8         reserved_at_8[0x18];
8204
8205         u8         syndrome[0x20];
8206
8207         u8         reserved_at_40[0x8];
8208         u8         pd[0x18];
8209
8210         u8         reserved_at_60[0x20];
8211 };
8212
8213 struct mlx5_ifc_alloc_pd_in_bits {
8214         u8         opcode[0x10];
8215         u8         uid[0x10];
8216
8217         u8         reserved_at_20[0x10];
8218         u8         op_mod[0x10];
8219
8220         u8         reserved_at_40[0x40];
8221 };
8222
8223 struct mlx5_ifc_alloc_flow_counter_out_bits {
8224         u8         status[0x8];
8225         u8         reserved_at_8[0x18];
8226
8227         u8         syndrome[0x20];
8228
8229         u8         flow_counter_id[0x20];
8230
8231         u8         reserved_at_60[0x20];
8232 };
8233
8234 struct mlx5_ifc_alloc_flow_counter_in_bits {
8235         u8         opcode[0x10];
8236         u8         reserved_at_10[0x10];
8237
8238         u8         reserved_at_20[0x10];
8239         u8         op_mod[0x10];
8240
8241         u8         reserved_at_40[0x38];
8242         u8         flow_counter_bulk[0x8];
8243 };
8244
8245 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8246         u8         status[0x8];
8247         u8         reserved_at_8[0x18];
8248
8249         u8         syndrome[0x20];
8250
8251         u8         reserved_at_40[0x40];
8252 };
8253
8254 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8255         u8         opcode[0x10];
8256         u8         reserved_at_10[0x10];
8257
8258         u8         reserved_at_20[0x10];
8259         u8         op_mod[0x10];
8260
8261         u8         reserved_at_40[0x20];
8262
8263         u8         reserved_at_60[0x10];
8264         u8         vxlan_udp_port[0x10];
8265 };
8266
8267 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8268         u8         status[0x8];
8269         u8         reserved_at_8[0x18];
8270
8271         u8         syndrome[0x20];
8272
8273         u8         reserved_at_40[0x40];
8274 };
8275
8276 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8277         u8         rate_limit[0x20];
8278
8279         u8         burst_upper_bound[0x20];
8280
8281         u8         reserved_at_40[0x10];
8282         u8         typical_packet_size[0x10];
8283
8284         u8         reserved_at_60[0x120];
8285 };
8286
8287 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8288         u8         opcode[0x10];
8289         u8         uid[0x10];
8290
8291         u8         reserved_at_20[0x10];
8292         u8         op_mod[0x10];
8293
8294         u8         reserved_at_40[0x10];
8295         u8         rate_limit_index[0x10];
8296
8297         u8         reserved_at_60[0x20];
8298
8299         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8300 };
8301
8302 struct mlx5_ifc_access_register_out_bits {
8303         u8         status[0x8];
8304         u8         reserved_at_8[0x18];
8305
8306         u8         syndrome[0x20];
8307
8308         u8         reserved_at_40[0x40];
8309
8310         u8         register_data[0][0x20];
8311 };
8312
8313 enum {
8314         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8315         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8316 };
8317
8318 struct mlx5_ifc_access_register_in_bits {
8319         u8         opcode[0x10];
8320         u8         reserved_at_10[0x10];
8321
8322         u8         reserved_at_20[0x10];
8323         u8         op_mod[0x10];
8324
8325         u8         reserved_at_40[0x10];
8326         u8         register_id[0x10];
8327
8328         u8         argument[0x20];
8329
8330         u8         register_data[0][0x20];
8331 };
8332
8333 struct mlx5_ifc_sltp_reg_bits {
8334         u8         status[0x4];
8335         u8         version[0x4];
8336         u8         local_port[0x8];
8337         u8         pnat[0x2];
8338         u8         reserved_at_12[0x2];
8339         u8         lane[0x4];
8340         u8         reserved_at_18[0x8];
8341
8342         u8         reserved_at_20[0x20];
8343
8344         u8         reserved_at_40[0x7];
8345         u8         polarity[0x1];
8346         u8         ob_tap0[0x8];
8347         u8         ob_tap1[0x8];
8348         u8         ob_tap2[0x8];
8349
8350         u8         reserved_at_60[0xc];
8351         u8         ob_preemp_mode[0x4];
8352         u8         ob_reg[0x8];
8353         u8         ob_bias[0x8];
8354
8355         u8         reserved_at_80[0x20];
8356 };
8357
8358 struct mlx5_ifc_slrg_reg_bits {
8359         u8         status[0x4];
8360         u8         version[0x4];
8361         u8         local_port[0x8];
8362         u8         pnat[0x2];
8363         u8         reserved_at_12[0x2];
8364         u8         lane[0x4];
8365         u8         reserved_at_18[0x8];
8366
8367         u8         time_to_link_up[0x10];
8368         u8         reserved_at_30[0xc];
8369         u8         grade_lane_speed[0x4];
8370
8371         u8         grade_version[0x8];
8372         u8         grade[0x18];
8373
8374         u8         reserved_at_60[0x4];
8375         u8         height_grade_type[0x4];
8376         u8         height_grade[0x18];
8377
8378         u8         height_dz[0x10];
8379         u8         height_dv[0x10];
8380
8381         u8         reserved_at_a0[0x10];
8382         u8         height_sigma[0x10];
8383
8384         u8         reserved_at_c0[0x20];
8385
8386         u8         reserved_at_e0[0x4];
8387         u8         phase_grade_type[0x4];
8388         u8         phase_grade[0x18];
8389
8390         u8         reserved_at_100[0x8];
8391         u8         phase_eo_pos[0x8];
8392         u8         reserved_at_110[0x8];
8393         u8         phase_eo_neg[0x8];
8394
8395         u8         ffe_set_tested[0x10];
8396         u8         test_errors_per_lane[0x10];
8397 };
8398
8399 struct mlx5_ifc_pvlc_reg_bits {
8400         u8         reserved_at_0[0x8];
8401         u8         local_port[0x8];
8402         u8         reserved_at_10[0x10];
8403
8404         u8         reserved_at_20[0x1c];
8405         u8         vl_hw_cap[0x4];
8406
8407         u8         reserved_at_40[0x1c];
8408         u8         vl_admin[0x4];
8409
8410         u8         reserved_at_60[0x1c];
8411         u8         vl_operational[0x4];
8412 };
8413
8414 struct mlx5_ifc_pude_reg_bits {
8415         u8         swid[0x8];
8416         u8         local_port[0x8];
8417         u8         reserved_at_10[0x4];
8418         u8         admin_status[0x4];
8419         u8         reserved_at_18[0x4];
8420         u8         oper_status[0x4];
8421
8422         u8         reserved_at_20[0x60];
8423 };
8424
8425 struct mlx5_ifc_ptys_reg_bits {
8426         u8         reserved_at_0[0x1];
8427         u8         an_disable_admin[0x1];
8428         u8         an_disable_cap[0x1];
8429         u8         reserved_at_3[0x5];
8430         u8         local_port[0x8];
8431         u8         reserved_at_10[0xd];
8432         u8         proto_mask[0x3];
8433
8434         u8         an_status[0x4];
8435         u8         reserved_at_24[0xc];
8436         u8         data_rate_oper[0x10];
8437
8438         u8         ext_eth_proto_capability[0x20];
8439
8440         u8         eth_proto_capability[0x20];
8441
8442         u8         ib_link_width_capability[0x10];
8443         u8         ib_proto_capability[0x10];
8444
8445         u8         ext_eth_proto_admin[0x20];
8446
8447         u8         eth_proto_admin[0x20];
8448
8449         u8         ib_link_width_admin[0x10];
8450         u8         ib_proto_admin[0x10];
8451
8452         u8         ext_eth_proto_oper[0x20];
8453
8454         u8         eth_proto_oper[0x20];
8455
8456         u8         ib_link_width_oper[0x10];
8457         u8         ib_proto_oper[0x10];
8458
8459         u8         reserved_at_160[0x1c];
8460         u8         connector_type[0x4];
8461
8462         u8         eth_proto_lp_advertise[0x20];
8463
8464         u8         reserved_at_1a0[0x60];
8465 };
8466
8467 struct mlx5_ifc_mlcr_reg_bits {
8468         u8         reserved_at_0[0x8];
8469         u8         local_port[0x8];
8470         u8         reserved_at_10[0x20];
8471
8472         u8         beacon_duration[0x10];
8473         u8         reserved_at_40[0x10];
8474
8475         u8         beacon_remain[0x10];
8476 };
8477
8478 struct mlx5_ifc_ptas_reg_bits {
8479         u8         reserved_at_0[0x20];
8480
8481         u8         algorithm_options[0x10];
8482         u8         reserved_at_30[0x4];
8483         u8         repetitions_mode[0x4];
8484         u8         num_of_repetitions[0x8];
8485
8486         u8         grade_version[0x8];
8487         u8         height_grade_type[0x4];
8488         u8         phase_grade_type[0x4];
8489         u8         height_grade_weight[0x8];
8490         u8         phase_grade_weight[0x8];
8491
8492         u8         gisim_measure_bits[0x10];
8493         u8         adaptive_tap_measure_bits[0x10];
8494
8495         u8         ber_bath_high_error_threshold[0x10];
8496         u8         ber_bath_mid_error_threshold[0x10];
8497
8498         u8         ber_bath_low_error_threshold[0x10];
8499         u8         one_ratio_high_threshold[0x10];
8500
8501         u8         one_ratio_high_mid_threshold[0x10];
8502         u8         one_ratio_low_mid_threshold[0x10];
8503
8504         u8         one_ratio_low_threshold[0x10];
8505         u8         ndeo_error_threshold[0x10];
8506
8507         u8         mixer_offset_step_size[0x10];
8508         u8         reserved_at_110[0x8];
8509         u8         mix90_phase_for_voltage_bath[0x8];
8510
8511         u8         mixer_offset_start[0x10];
8512         u8         mixer_offset_end[0x10];
8513
8514         u8         reserved_at_140[0x15];
8515         u8         ber_test_time[0xb];
8516 };
8517
8518 struct mlx5_ifc_pspa_reg_bits {
8519         u8         swid[0x8];
8520         u8         local_port[0x8];
8521         u8         sub_port[0x8];
8522         u8         reserved_at_18[0x8];
8523
8524         u8         reserved_at_20[0x20];
8525 };
8526
8527 struct mlx5_ifc_pqdr_reg_bits {
8528         u8         reserved_at_0[0x8];
8529         u8         local_port[0x8];
8530         u8         reserved_at_10[0x5];
8531         u8         prio[0x3];
8532         u8         reserved_at_18[0x6];
8533         u8         mode[0x2];
8534
8535         u8         reserved_at_20[0x20];
8536
8537         u8         reserved_at_40[0x10];
8538         u8         min_threshold[0x10];
8539
8540         u8         reserved_at_60[0x10];
8541         u8         max_threshold[0x10];
8542
8543         u8         reserved_at_80[0x10];
8544         u8         mark_probability_denominator[0x10];
8545
8546         u8         reserved_at_a0[0x60];
8547 };
8548
8549 struct mlx5_ifc_ppsc_reg_bits {
8550         u8         reserved_at_0[0x8];
8551         u8         local_port[0x8];
8552         u8         reserved_at_10[0x10];
8553
8554         u8         reserved_at_20[0x60];
8555
8556         u8         reserved_at_80[0x1c];
8557         u8         wrps_admin[0x4];
8558
8559         u8         reserved_at_a0[0x1c];
8560         u8         wrps_status[0x4];
8561
8562         u8         reserved_at_c0[0x8];
8563         u8         up_threshold[0x8];
8564         u8         reserved_at_d0[0x8];
8565         u8         down_threshold[0x8];
8566
8567         u8         reserved_at_e0[0x20];
8568
8569         u8         reserved_at_100[0x1c];
8570         u8         srps_admin[0x4];
8571
8572         u8         reserved_at_120[0x1c];
8573         u8         srps_status[0x4];
8574
8575         u8         reserved_at_140[0x40];
8576 };
8577
8578 struct mlx5_ifc_pplr_reg_bits {
8579         u8         reserved_at_0[0x8];
8580         u8         local_port[0x8];
8581         u8         reserved_at_10[0x10];
8582
8583         u8         reserved_at_20[0x8];
8584         u8         lb_cap[0x8];
8585         u8         reserved_at_30[0x8];
8586         u8         lb_en[0x8];
8587 };
8588
8589 struct mlx5_ifc_pplm_reg_bits {
8590         u8         reserved_at_0[0x8];
8591         u8         local_port[0x8];
8592         u8         reserved_at_10[0x10];
8593
8594         u8         reserved_at_20[0x20];
8595
8596         u8         port_profile_mode[0x8];
8597         u8         static_port_profile[0x8];
8598         u8         active_port_profile[0x8];
8599         u8         reserved_at_58[0x8];
8600
8601         u8         retransmission_active[0x8];
8602         u8         fec_mode_active[0x18];
8603
8604         u8         rs_fec_correction_bypass_cap[0x4];
8605         u8         reserved_at_84[0x8];
8606         u8         fec_override_cap_56g[0x4];
8607         u8         fec_override_cap_100g[0x4];
8608         u8         fec_override_cap_50g[0x4];
8609         u8         fec_override_cap_25g[0x4];
8610         u8         fec_override_cap_10g_40g[0x4];
8611
8612         u8         rs_fec_correction_bypass_admin[0x4];
8613         u8         reserved_at_a4[0x8];
8614         u8         fec_override_admin_56g[0x4];
8615         u8         fec_override_admin_100g[0x4];
8616         u8         fec_override_admin_50g[0x4];
8617         u8         fec_override_admin_25g[0x4];
8618         u8         fec_override_admin_10g_40g[0x4];
8619
8620         u8         fec_override_cap_400g_8x[0x10];
8621         u8         fec_override_cap_200g_4x[0x10];
8622
8623         u8         fec_override_cap_100g_2x[0x10];
8624         u8         fec_override_cap_50g_1x[0x10];
8625
8626         u8         fec_override_admin_400g_8x[0x10];
8627         u8         fec_override_admin_200g_4x[0x10];
8628
8629         u8         fec_override_admin_100g_2x[0x10];
8630         u8         fec_override_admin_50g_1x[0x10];
8631 };
8632
8633 struct mlx5_ifc_ppcnt_reg_bits {
8634         u8         swid[0x8];
8635         u8         local_port[0x8];
8636         u8         pnat[0x2];
8637         u8         reserved_at_12[0x8];
8638         u8         grp[0x6];
8639
8640         u8         clr[0x1];
8641         u8         reserved_at_21[0x1c];
8642         u8         prio_tc[0x3];
8643
8644         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8645 };
8646
8647 struct mlx5_ifc_mpein_reg_bits {
8648         u8         reserved_at_0[0x2];
8649         u8         depth[0x6];
8650         u8         pcie_index[0x8];
8651         u8         node[0x8];
8652         u8         reserved_at_18[0x8];
8653
8654         u8         capability_mask[0x20];
8655
8656         u8         reserved_at_40[0x8];
8657         u8         link_width_enabled[0x8];
8658         u8         link_speed_enabled[0x10];
8659
8660         u8         lane0_physical_position[0x8];
8661         u8         link_width_active[0x8];
8662         u8         link_speed_active[0x10];
8663
8664         u8         num_of_pfs[0x10];
8665         u8         num_of_vfs[0x10];
8666
8667         u8         bdf0[0x10];
8668         u8         reserved_at_b0[0x10];
8669
8670         u8         max_read_request_size[0x4];
8671         u8         max_payload_size[0x4];
8672         u8         reserved_at_c8[0x5];
8673         u8         pwr_status[0x3];
8674         u8         port_type[0x4];
8675         u8         reserved_at_d4[0xb];
8676         u8         lane_reversal[0x1];
8677
8678         u8         reserved_at_e0[0x14];
8679         u8         pci_power[0xc];
8680
8681         u8         reserved_at_100[0x20];
8682
8683         u8         device_status[0x10];
8684         u8         port_state[0x8];
8685         u8         reserved_at_138[0x8];
8686
8687         u8         reserved_at_140[0x10];
8688         u8         receiver_detect_result[0x10];
8689
8690         u8         reserved_at_160[0x20];
8691 };
8692
8693 struct mlx5_ifc_mpcnt_reg_bits {
8694         u8         reserved_at_0[0x8];
8695         u8         pcie_index[0x8];
8696         u8         reserved_at_10[0xa];
8697         u8         grp[0x6];
8698
8699         u8         clr[0x1];
8700         u8         reserved_at_21[0x1f];
8701
8702         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8703 };
8704
8705 struct mlx5_ifc_ppad_reg_bits {
8706         u8         reserved_at_0[0x3];
8707         u8         single_mac[0x1];
8708         u8         reserved_at_4[0x4];
8709         u8         local_port[0x8];
8710         u8         mac_47_32[0x10];
8711
8712         u8         mac_31_0[0x20];
8713
8714         u8         reserved_at_40[0x40];
8715 };
8716
8717 struct mlx5_ifc_pmtu_reg_bits {
8718         u8         reserved_at_0[0x8];
8719         u8         local_port[0x8];
8720         u8         reserved_at_10[0x10];
8721
8722         u8         max_mtu[0x10];
8723         u8         reserved_at_30[0x10];
8724
8725         u8         admin_mtu[0x10];
8726         u8         reserved_at_50[0x10];
8727
8728         u8         oper_mtu[0x10];
8729         u8         reserved_at_70[0x10];
8730 };
8731
8732 struct mlx5_ifc_pmpr_reg_bits {
8733         u8         reserved_at_0[0x8];
8734         u8         module[0x8];
8735         u8         reserved_at_10[0x10];
8736
8737         u8         reserved_at_20[0x18];
8738         u8         attenuation_5g[0x8];
8739
8740         u8         reserved_at_40[0x18];
8741         u8         attenuation_7g[0x8];
8742
8743         u8         reserved_at_60[0x18];
8744         u8         attenuation_12g[0x8];
8745 };
8746
8747 struct mlx5_ifc_pmpe_reg_bits {
8748         u8         reserved_at_0[0x8];
8749         u8         module[0x8];
8750         u8         reserved_at_10[0xc];
8751         u8         module_status[0x4];
8752
8753         u8         reserved_at_20[0x60];
8754 };
8755
8756 struct mlx5_ifc_pmpc_reg_bits {
8757         u8         module_state_updated[32][0x8];
8758 };
8759
8760 struct mlx5_ifc_pmlpn_reg_bits {
8761         u8         reserved_at_0[0x4];
8762         u8         mlpn_status[0x4];
8763         u8         local_port[0x8];
8764         u8         reserved_at_10[0x10];
8765
8766         u8         e[0x1];
8767         u8         reserved_at_21[0x1f];
8768 };
8769
8770 struct mlx5_ifc_pmlp_reg_bits {
8771         u8         rxtx[0x1];
8772         u8         reserved_at_1[0x7];
8773         u8         local_port[0x8];
8774         u8         reserved_at_10[0x8];
8775         u8         width[0x8];
8776
8777         u8         lane0_module_mapping[0x20];
8778
8779         u8         lane1_module_mapping[0x20];
8780
8781         u8         lane2_module_mapping[0x20];
8782
8783         u8         lane3_module_mapping[0x20];
8784
8785         u8         reserved_at_a0[0x160];
8786 };
8787
8788 struct mlx5_ifc_pmaos_reg_bits {
8789         u8         reserved_at_0[0x8];
8790         u8         module[0x8];
8791         u8         reserved_at_10[0x4];
8792         u8         admin_status[0x4];
8793         u8         reserved_at_18[0x4];
8794         u8         oper_status[0x4];
8795
8796         u8         ase[0x1];
8797         u8         ee[0x1];
8798         u8         reserved_at_22[0x1c];
8799         u8         e[0x2];
8800
8801         u8         reserved_at_40[0x40];
8802 };
8803
8804 struct mlx5_ifc_plpc_reg_bits {
8805         u8         reserved_at_0[0x4];
8806         u8         profile_id[0xc];
8807         u8         reserved_at_10[0x4];
8808         u8         proto_mask[0x4];
8809         u8         reserved_at_18[0x8];
8810
8811         u8         reserved_at_20[0x10];
8812         u8         lane_speed[0x10];
8813
8814         u8         reserved_at_40[0x17];
8815         u8         lpbf[0x1];
8816         u8         fec_mode_policy[0x8];
8817
8818         u8         retransmission_capability[0x8];
8819         u8         fec_mode_capability[0x18];
8820
8821         u8         retransmission_support_admin[0x8];
8822         u8         fec_mode_support_admin[0x18];
8823
8824         u8         retransmission_request_admin[0x8];
8825         u8         fec_mode_request_admin[0x18];
8826
8827         u8         reserved_at_c0[0x80];
8828 };
8829
8830 struct mlx5_ifc_plib_reg_bits {
8831         u8         reserved_at_0[0x8];
8832         u8         local_port[0x8];
8833         u8         reserved_at_10[0x8];
8834         u8         ib_port[0x8];
8835
8836         u8         reserved_at_20[0x60];
8837 };
8838
8839 struct mlx5_ifc_plbf_reg_bits {
8840         u8         reserved_at_0[0x8];
8841         u8         local_port[0x8];
8842         u8         reserved_at_10[0xd];
8843         u8         lbf_mode[0x3];
8844
8845         u8         reserved_at_20[0x20];
8846 };
8847
8848 struct mlx5_ifc_pipg_reg_bits {
8849         u8         reserved_at_0[0x8];
8850         u8         local_port[0x8];
8851         u8         reserved_at_10[0x10];
8852
8853         u8         dic[0x1];
8854         u8         reserved_at_21[0x19];
8855         u8         ipg[0x4];
8856         u8         reserved_at_3e[0x2];
8857 };
8858
8859 struct mlx5_ifc_pifr_reg_bits {
8860         u8         reserved_at_0[0x8];
8861         u8         local_port[0x8];
8862         u8         reserved_at_10[0x10];
8863
8864         u8         reserved_at_20[0xe0];
8865
8866         u8         port_filter[8][0x20];
8867
8868         u8         port_filter_update_en[8][0x20];
8869 };
8870
8871 struct mlx5_ifc_pfcc_reg_bits {
8872         u8         reserved_at_0[0x8];
8873         u8         local_port[0x8];
8874         u8         reserved_at_10[0xb];
8875         u8         ppan_mask_n[0x1];
8876         u8         minor_stall_mask[0x1];
8877         u8         critical_stall_mask[0x1];
8878         u8         reserved_at_1e[0x2];
8879
8880         u8         ppan[0x4];
8881         u8         reserved_at_24[0x4];
8882         u8         prio_mask_tx[0x8];
8883         u8         reserved_at_30[0x8];
8884         u8         prio_mask_rx[0x8];
8885
8886         u8         pptx[0x1];
8887         u8         aptx[0x1];
8888         u8         pptx_mask_n[0x1];
8889         u8         reserved_at_43[0x5];
8890         u8         pfctx[0x8];
8891         u8         reserved_at_50[0x10];
8892
8893         u8         pprx[0x1];
8894         u8         aprx[0x1];
8895         u8         pprx_mask_n[0x1];
8896         u8         reserved_at_63[0x5];
8897         u8         pfcrx[0x8];
8898         u8         reserved_at_70[0x10];
8899
8900         u8         device_stall_minor_watermark[0x10];
8901         u8         device_stall_critical_watermark[0x10];
8902
8903         u8         reserved_at_a0[0x60];
8904 };
8905
8906 struct mlx5_ifc_pelc_reg_bits {
8907         u8         op[0x4];
8908         u8         reserved_at_4[0x4];
8909         u8         local_port[0x8];
8910         u8         reserved_at_10[0x10];
8911
8912         u8         op_admin[0x8];
8913         u8         op_capability[0x8];
8914         u8         op_request[0x8];
8915         u8         op_active[0x8];
8916
8917         u8         admin[0x40];
8918
8919         u8         capability[0x40];
8920
8921         u8         request[0x40];
8922
8923         u8         active[0x40];
8924
8925         u8         reserved_at_140[0x80];
8926 };
8927
8928 struct mlx5_ifc_peir_reg_bits {
8929         u8         reserved_at_0[0x8];
8930         u8         local_port[0x8];
8931         u8         reserved_at_10[0x10];
8932
8933         u8         reserved_at_20[0xc];
8934         u8         error_count[0x4];
8935         u8         reserved_at_30[0x10];
8936
8937         u8         reserved_at_40[0xc];
8938         u8         lane[0x4];
8939         u8         reserved_at_50[0x8];
8940         u8         error_type[0x8];
8941 };
8942
8943 struct mlx5_ifc_mpegc_reg_bits {
8944         u8         reserved_at_0[0x30];
8945         u8         field_select[0x10];
8946
8947         u8         tx_overflow_sense[0x1];
8948         u8         mark_cqe[0x1];
8949         u8         mark_cnp[0x1];
8950         u8         reserved_at_43[0x1b];
8951         u8         tx_lossy_overflow_oper[0x2];
8952
8953         u8         reserved_at_60[0x100];
8954 };
8955
8956 struct mlx5_ifc_pcam_enhanced_features_bits {
8957         u8         reserved_at_0[0x68];
8958         u8         fec_50G_per_lane_in_pplm[0x1];
8959         u8         reserved_at_69[0x4];
8960         u8         rx_icrc_encapsulated_counter[0x1];
8961         u8         reserved_at_6e[0x4];
8962         u8         ptys_extended_ethernet[0x1];
8963         u8         reserved_at_73[0x3];
8964         u8         pfcc_mask[0x1];
8965         u8         reserved_at_77[0x3];
8966         u8         per_lane_error_counters[0x1];
8967         u8         rx_buffer_fullness_counters[0x1];
8968         u8         ptys_connector_type[0x1];
8969         u8         reserved_at_7d[0x1];
8970         u8         ppcnt_discard_group[0x1];
8971         u8         ppcnt_statistical_group[0x1];
8972 };
8973
8974 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8975         u8         port_access_reg_cap_mask_127_to_96[0x20];
8976         u8         port_access_reg_cap_mask_95_to_64[0x20];
8977
8978         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8979         u8         pplm[0x1];
8980         u8         port_access_reg_cap_mask_34_to_32[0x3];
8981
8982         u8         port_access_reg_cap_mask_31_to_13[0x13];
8983         u8         pbmc[0x1];
8984         u8         pptb[0x1];
8985         u8         port_access_reg_cap_mask_10_to_09[0x2];
8986         u8         ppcnt[0x1];
8987         u8         port_access_reg_cap_mask_07_to_00[0x8];
8988 };
8989
8990 struct mlx5_ifc_pcam_reg_bits {
8991         u8         reserved_at_0[0x8];
8992         u8         feature_group[0x8];
8993         u8         reserved_at_10[0x8];
8994         u8         access_reg_group[0x8];
8995
8996         u8         reserved_at_20[0x20];
8997
8998         union {
8999                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9000                 u8         reserved_at_0[0x80];
9001         } port_access_reg_cap_mask;
9002
9003         u8         reserved_at_c0[0x80];
9004
9005         union {
9006                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9007                 u8         reserved_at_0[0x80];
9008         } feature_cap_mask;
9009
9010         u8         reserved_at_1c0[0xc0];
9011 };
9012
9013 struct mlx5_ifc_mcam_enhanced_features_bits {
9014         u8         reserved_at_0[0x6e];
9015         u8         pci_status_and_power[0x1];
9016         u8         reserved_at_6f[0x5];
9017         u8         mark_tx_action_cnp[0x1];
9018         u8         mark_tx_action_cqe[0x1];
9019         u8         dynamic_tx_overflow[0x1];
9020         u8         reserved_at_77[0x4];
9021         u8         pcie_outbound_stalled[0x1];
9022         u8         tx_overflow_buffer_pkt[0x1];
9023         u8         mtpps_enh_out_per_adj[0x1];
9024         u8         mtpps_fs[0x1];
9025         u8         pcie_performance_group[0x1];
9026 };
9027
9028 struct mlx5_ifc_mcam_access_reg_bits {
9029         u8         reserved_at_0[0x1c];
9030         u8         mcda[0x1];
9031         u8         mcc[0x1];
9032         u8         mcqi[0x1];
9033         u8         mcqs[0x1];
9034
9035         u8         regs_95_to_87[0x9];
9036         u8         mpegc[0x1];
9037         u8         regs_85_to_68[0x12];
9038         u8         tracer_registers[0x4];
9039
9040         u8         regs_63_to_32[0x20];
9041         u8         regs_31_to_0[0x20];
9042 };
9043
9044 struct mlx5_ifc_mcam_access_reg_bits1 {
9045         u8         regs_127_to_96[0x20];
9046
9047         u8         regs_95_to_64[0x20];
9048
9049         u8         regs_63_to_32[0x20];
9050
9051         u8         regs_31_to_0[0x20];
9052 };
9053
9054 struct mlx5_ifc_mcam_access_reg_bits2 {
9055         u8         regs_127_to_99[0x1d];
9056         u8         mirc[0x1];
9057         u8         regs_97_to_96[0x2];
9058
9059         u8         regs_95_to_64[0x20];
9060
9061         u8         regs_63_to_32[0x20];
9062
9063         u8         regs_31_to_0[0x20];
9064 };
9065
9066 struct mlx5_ifc_mcam_reg_bits {
9067         u8         reserved_at_0[0x8];
9068         u8         feature_group[0x8];
9069         u8         reserved_at_10[0x8];
9070         u8         access_reg_group[0x8];
9071
9072         u8         reserved_at_20[0x20];
9073
9074         union {
9075                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9076                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9077                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9078                 u8         reserved_at_0[0x80];
9079         } mng_access_reg_cap_mask;
9080
9081         u8         reserved_at_c0[0x80];
9082
9083         union {
9084                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9085                 u8         reserved_at_0[0x80];
9086         } mng_feature_cap_mask;
9087
9088         u8         reserved_at_1c0[0x80];
9089 };
9090
9091 struct mlx5_ifc_qcam_access_reg_cap_mask {
9092         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9093         u8         qpdpm[0x1];
9094         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9095         u8         qdpm[0x1];
9096         u8         qpts[0x1];
9097         u8         qcap[0x1];
9098         u8         qcam_access_reg_cap_mask_0[0x1];
9099 };
9100
9101 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9102         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9103         u8         qpts_trust_both[0x1];
9104 };
9105
9106 struct mlx5_ifc_qcam_reg_bits {
9107         u8         reserved_at_0[0x8];
9108         u8         feature_group[0x8];
9109         u8         reserved_at_10[0x8];
9110         u8         access_reg_group[0x8];
9111         u8         reserved_at_20[0x20];
9112
9113         union {
9114                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9115                 u8  reserved_at_0[0x80];
9116         } qos_access_reg_cap_mask;
9117
9118         u8         reserved_at_c0[0x80];
9119
9120         union {
9121                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9122                 u8  reserved_at_0[0x80];
9123         } qos_feature_cap_mask;
9124
9125         u8         reserved_at_1c0[0x80];
9126 };
9127
9128 struct mlx5_ifc_core_dump_reg_bits {
9129         u8         reserved_at_0[0x18];
9130         u8         core_dump_type[0x8];
9131
9132         u8         reserved_at_20[0x30];
9133         u8         vhca_id[0x10];
9134
9135         u8         reserved_at_60[0x8];
9136         u8         qpn[0x18];
9137         u8         reserved_at_80[0x180];
9138 };
9139
9140 struct mlx5_ifc_pcap_reg_bits {
9141         u8         reserved_at_0[0x8];
9142         u8         local_port[0x8];
9143         u8         reserved_at_10[0x10];
9144
9145         u8         port_capability_mask[4][0x20];
9146 };
9147
9148 struct mlx5_ifc_paos_reg_bits {
9149         u8         swid[0x8];
9150         u8         local_port[0x8];
9151         u8         reserved_at_10[0x4];
9152         u8         admin_status[0x4];
9153         u8         reserved_at_18[0x4];
9154         u8         oper_status[0x4];
9155
9156         u8         ase[0x1];
9157         u8         ee[0x1];
9158         u8         reserved_at_22[0x1c];
9159         u8         e[0x2];
9160
9161         u8         reserved_at_40[0x40];
9162 };
9163
9164 struct mlx5_ifc_pamp_reg_bits {
9165         u8         reserved_at_0[0x8];
9166         u8         opamp_group[0x8];
9167         u8         reserved_at_10[0xc];
9168         u8         opamp_group_type[0x4];
9169
9170         u8         start_index[0x10];
9171         u8         reserved_at_30[0x4];
9172         u8         num_of_indices[0xc];
9173
9174         u8         index_data[18][0x10];
9175 };
9176
9177 struct mlx5_ifc_pcmr_reg_bits {
9178         u8         reserved_at_0[0x8];
9179         u8         local_port[0x8];
9180         u8         reserved_at_10[0x10];
9181         u8         entropy_force_cap[0x1];
9182         u8         entropy_calc_cap[0x1];
9183         u8         entropy_gre_calc_cap[0x1];
9184         u8         reserved_at_23[0x1b];
9185         u8         fcs_cap[0x1];
9186         u8         reserved_at_3f[0x1];
9187         u8         entropy_force[0x1];
9188         u8         entropy_calc[0x1];
9189         u8         entropy_gre_calc[0x1];
9190         u8         reserved_at_43[0x1b];
9191         u8         fcs_chk[0x1];
9192         u8         reserved_at_5f[0x1];
9193 };
9194
9195 struct mlx5_ifc_lane_2_module_mapping_bits {
9196         u8         reserved_at_0[0x6];
9197         u8         rx_lane[0x2];
9198         u8         reserved_at_8[0x6];
9199         u8         tx_lane[0x2];
9200         u8         reserved_at_10[0x8];
9201         u8         module[0x8];
9202 };
9203
9204 struct mlx5_ifc_bufferx_reg_bits {
9205         u8         reserved_at_0[0x6];
9206         u8         lossy[0x1];
9207         u8         epsb[0x1];
9208         u8         reserved_at_8[0xc];
9209         u8         size[0xc];
9210
9211         u8         xoff_threshold[0x10];
9212         u8         xon_threshold[0x10];
9213 };
9214
9215 struct mlx5_ifc_set_node_in_bits {
9216         u8         node_description[64][0x8];
9217 };
9218
9219 struct mlx5_ifc_register_power_settings_bits {
9220         u8         reserved_at_0[0x18];
9221         u8         power_settings_level[0x8];
9222
9223         u8         reserved_at_20[0x60];
9224 };
9225
9226 struct mlx5_ifc_register_host_endianness_bits {
9227         u8         he[0x1];
9228         u8         reserved_at_1[0x1f];
9229
9230         u8         reserved_at_20[0x60];
9231 };
9232
9233 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9234         u8         reserved_at_0[0x20];
9235
9236         u8         mkey[0x20];
9237
9238         u8         addressh_63_32[0x20];
9239
9240         u8         addressl_31_0[0x20];
9241 };
9242
9243 struct mlx5_ifc_ud_adrs_vector_bits {
9244         u8         dc_key[0x40];
9245
9246         u8         ext[0x1];
9247         u8         reserved_at_41[0x7];
9248         u8         destination_qp_dct[0x18];
9249
9250         u8         static_rate[0x4];
9251         u8         sl_eth_prio[0x4];
9252         u8         fl[0x1];
9253         u8         mlid[0x7];
9254         u8         rlid_udp_sport[0x10];
9255
9256         u8         reserved_at_80[0x20];
9257
9258         u8         rmac_47_16[0x20];
9259
9260         u8         rmac_15_0[0x10];
9261         u8         tclass[0x8];
9262         u8         hop_limit[0x8];
9263
9264         u8         reserved_at_e0[0x1];
9265         u8         grh[0x1];
9266         u8         reserved_at_e2[0x2];
9267         u8         src_addr_index[0x8];
9268         u8         flow_label[0x14];
9269
9270         u8         rgid_rip[16][0x8];
9271 };
9272
9273 struct mlx5_ifc_pages_req_event_bits {
9274         u8         reserved_at_0[0x10];
9275         u8         function_id[0x10];
9276
9277         u8         num_pages[0x20];
9278
9279         u8         reserved_at_40[0xa0];
9280 };
9281
9282 struct mlx5_ifc_eqe_bits {
9283         u8         reserved_at_0[0x8];
9284         u8         event_type[0x8];
9285         u8         reserved_at_10[0x8];
9286         u8         event_sub_type[0x8];
9287
9288         u8         reserved_at_20[0xe0];
9289
9290         union mlx5_ifc_event_auto_bits event_data;
9291
9292         u8         reserved_at_1e0[0x10];
9293         u8         signature[0x8];
9294         u8         reserved_at_1f8[0x7];
9295         u8         owner[0x1];
9296 };
9297
9298 enum {
9299         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9300 };
9301
9302 struct mlx5_ifc_cmd_queue_entry_bits {
9303         u8         type[0x8];
9304         u8         reserved_at_8[0x18];
9305
9306         u8         input_length[0x20];
9307
9308         u8         input_mailbox_pointer_63_32[0x20];
9309
9310         u8         input_mailbox_pointer_31_9[0x17];
9311         u8         reserved_at_77[0x9];
9312
9313         u8         command_input_inline_data[16][0x8];
9314
9315         u8         command_output_inline_data[16][0x8];
9316
9317         u8         output_mailbox_pointer_63_32[0x20];
9318
9319         u8         output_mailbox_pointer_31_9[0x17];
9320         u8         reserved_at_1b7[0x9];
9321
9322         u8         output_length[0x20];
9323
9324         u8         token[0x8];
9325         u8         signature[0x8];
9326         u8         reserved_at_1f0[0x8];
9327         u8         status[0x7];
9328         u8         ownership[0x1];
9329 };
9330
9331 struct mlx5_ifc_cmd_out_bits {
9332         u8         status[0x8];
9333         u8         reserved_at_8[0x18];
9334
9335         u8         syndrome[0x20];
9336
9337         u8         command_output[0x20];
9338 };
9339
9340 struct mlx5_ifc_cmd_in_bits {
9341         u8         opcode[0x10];
9342         u8         reserved_at_10[0x10];
9343
9344         u8         reserved_at_20[0x10];
9345         u8         op_mod[0x10];
9346
9347         u8         command[0][0x20];
9348 };
9349
9350 struct mlx5_ifc_cmd_if_box_bits {
9351         u8         mailbox_data[512][0x8];
9352
9353         u8         reserved_at_1000[0x180];
9354
9355         u8         next_pointer_63_32[0x20];
9356
9357         u8         next_pointer_31_10[0x16];
9358         u8         reserved_at_11b6[0xa];
9359
9360         u8         block_number[0x20];
9361
9362         u8         reserved_at_11e0[0x8];
9363         u8         token[0x8];
9364         u8         ctrl_signature[0x8];
9365         u8         signature[0x8];
9366 };
9367
9368 struct mlx5_ifc_mtt_bits {
9369         u8         ptag_63_32[0x20];
9370
9371         u8         ptag_31_8[0x18];
9372         u8         reserved_at_38[0x6];
9373         u8         wr_en[0x1];
9374         u8         rd_en[0x1];
9375 };
9376
9377 struct mlx5_ifc_query_wol_rol_out_bits {
9378         u8         status[0x8];
9379         u8         reserved_at_8[0x18];
9380
9381         u8         syndrome[0x20];
9382
9383         u8         reserved_at_40[0x10];
9384         u8         rol_mode[0x8];
9385         u8         wol_mode[0x8];
9386
9387         u8         reserved_at_60[0x20];
9388 };
9389
9390 struct mlx5_ifc_query_wol_rol_in_bits {
9391         u8         opcode[0x10];
9392         u8         reserved_at_10[0x10];
9393
9394         u8         reserved_at_20[0x10];
9395         u8         op_mod[0x10];
9396
9397         u8         reserved_at_40[0x40];
9398 };
9399
9400 struct mlx5_ifc_set_wol_rol_out_bits {
9401         u8         status[0x8];
9402         u8         reserved_at_8[0x18];
9403
9404         u8         syndrome[0x20];
9405
9406         u8         reserved_at_40[0x40];
9407 };
9408
9409 struct mlx5_ifc_set_wol_rol_in_bits {
9410         u8         opcode[0x10];
9411         u8         reserved_at_10[0x10];
9412
9413         u8         reserved_at_20[0x10];
9414         u8         op_mod[0x10];
9415
9416         u8         rol_mode_valid[0x1];
9417         u8         wol_mode_valid[0x1];
9418         u8         reserved_at_42[0xe];
9419         u8         rol_mode[0x8];
9420         u8         wol_mode[0x8];
9421
9422         u8         reserved_at_60[0x20];
9423 };
9424
9425 enum {
9426         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9427         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9428         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9429 };
9430
9431 enum {
9432         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9433         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9434         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9435 };
9436
9437 enum {
9438         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9439         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9440         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9441         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9442         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9443         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9444         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9445         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9446         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9447         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9448         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9449 };
9450
9451 struct mlx5_ifc_initial_seg_bits {
9452         u8         fw_rev_minor[0x10];
9453         u8         fw_rev_major[0x10];
9454
9455         u8         cmd_interface_rev[0x10];
9456         u8         fw_rev_subminor[0x10];
9457
9458         u8         reserved_at_40[0x40];
9459
9460         u8         cmdq_phy_addr_63_32[0x20];
9461
9462         u8         cmdq_phy_addr_31_12[0x14];
9463         u8         reserved_at_b4[0x2];
9464         u8         nic_interface[0x2];
9465         u8         log_cmdq_size[0x4];
9466         u8         log_cmdq_stride[0x4];
9467
9468         u8         command_doorbell_vector[0x20];
9469
9470         u8         reserved_at_e0[0xf00];
9471
9472         u8         initializing[0x1];
9473         u8         reserved_at_fe1[0x4];
9474         u8         nic_interface_supported[0x3];
9475         u8         embedded_cpu[0x1];
9476         u8         reserved_at_fe9[0x17];
9477
9478         struct mlx5_ifc_health_buffer_bits health_buffer;
9479
9480         u8         no_dram_nic_offset[0x20];
9481
9482         u8         reserved_at_1220[0x6e40];
9483
9484         u8         reserved_at_8060[0x1f];
9485         u8         clear_int[0x1];
9486
9487         u8         health_syndrome[0x8];
9488         u8         health_counter[0x18];
9489
9490         u8         reserved_at_80a0[0x17fc0];
9491 };
9492
9493 struct mlx5_ifc_mtpps_reg_bits {
9494         u8         reserved_at_0[0xc];
9495         u8         cap_number_of_pps_pins[0x4];
9496         u8         reserved_at_10[0x4];
9497         u8         cap_max_num_of_pps_in_pins[0x4];
9498         u8         reserved_at_18[0x4];
9499         u8         cap_max_num_of_pps_out_pins[0x4];
9500
9501         u8         reserved_at_20[0x24];
9502         u8         cap_pin_3_mode[0x4];
9503         u8         reserved_at_48[0x4];
9504         u8         cap_pin_2_mode[0x4];
9505         u8         reserved_at_50[0x4];
9506         u8         cap_pin_1_mode[0x4];
9507         u8         reserved_at_58[0x4];
9508         u8         cap_pin_0_mode[0x4];
9509
9510         u8         reserved_at_60[0x4];
9511         u8         cap_pin_7_mode[0x4];
9512         u8         reserved_at_68[0x4];
9513         u8         cap_pin_6_mode[0x4];
9514         u8         reserved_at_70[0x4];
9515         u8         cap_pin_5_mode[0x4];
9516         u8         reserved_at_78[0x4];
9517         u8         cap_pin_4_mode[0x4];
9518
9519         u8         field_select[0x20];
9520         u8         reserved_at_a0[0x60];
9521
9522         u8         enable[0x1];
9523         u8         reserved_at_101[0xb];
9524         u8         pattern[0x4];
9525         u8         reserved_at_110[0x4];
9526         u8         pin_mode[0x4];
9527         u8         pin[0x8];
9528
9529         u8         reserved_at_120[0x20];
9530
9531         u8         time_stamp[0x40];
9532
9533         u8         out_pulse_duration[0x10];
9534         u8         out_periodic_adjustment[0x10];
9535         u8         enhanced_out_periodic_adjustment[0x20];
9536
9537         u8         reserved_at_1c0[0x20];
9538 };
9539
9540 struct mlx5_ifc_mtppse_reg_bits {
9541         u8         reserved_at_0[0x18];
9542         u8         pin[0x8];
9543         u8         event_arm[0x1];
9544         u8         reserved_at_21[0x1b];
9545         u8         event_generation_mode[0x4];
9546         u8         reserved_at_40[0x40];
9547 };
9548
9549 struct mlx5_ifc_mcqs_reg_bits {
9550         u8         last_index_flag[0x1];
9551         u8         reserved_at_1[0x7];
9552         u8         fw_device[0x8];
9553         u8         component_index[0x10];
9554
9555         u8         reserved_at_20[0x10];
9556         u8         identifier[0x10];
9557
9558         u8         reserved_at_40[0x17];
9559         u8         component_status[0x5];
9560         u8         component_update_state[0x4];
9561
9562         u8         last_update_state_changer_type[0x4];
9563         u8         last_update_state_changer_host_id[0x4];
9564         u8         reserved_at_68[0x18];
9565 };
9566
9567 struct mlx5_ifc_mcqi_cap_bits {
9568         u8         supported_info_bitmask[0x20];
9569
9570         u8         component_size[0x20];
9571
9572         u8         max_component_size[0x20];
9573
9574         u8         log_mcda_word_size[0x4];
9575         u8         reserved_at_64[0xc];
9576         u8         mcda_max_write_size[0x10];
9577
9578         u8         rd_en[0x1];
9579         u8         reserved_at_81[0x1];
9580         u8         match_chip_id[0x1];
9581         u8         match_psid[0x1];
9582         u8         check_user_timestamp[0x1];
9583         u8         match_base_guid_mac[0x1];
9584         u8         reserved_at_86[0x1a];
9585 };
9586
9587 struct mlx5_ifc_mcqi_version_bits {
9588         u8         reserved_at_0[0x2];
9589         u8         build_time_valid[0x1];
9590         u8         user_defined_time_valid[0x1];
9591         u8         reserved_at_4[0x14];
9592         u8         version_string_length[0x8];
9593
9594         u8         version[0x20];
9595
9596         u8         build_time[0x40];
9597
9598         u8         user_defined_time[0x40];
9599
9600         u8         build_tool_version[0x20];
9601
9602         u8         reserved_at_e0[0x20];
9603
9604         u8         version_string[92][0x8];
9605 };
9606
9607 struct mlx5_ifc_mcqi_activation_method_bits {
9608         u8         pending_server_ac_power_cycle[0x1];
9609         u8         pending_server_dc_power_cycle[0x1];
9610         u8         pending_server_reboot[0x1];
9611         u8         pending_fw_reset[0x1];
9612         u8         auto_activate[0x1];
9613         u8         all_hosts_sync[0x1];
9614         u8         device_hw_reset[0x1];
9615         u8         reserved_at_7[0x19];
9616 };
9617
9618 union mlx5_ifc_mcqi_reg_data_bits {
9619         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9620         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9621         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9622 };
9623
9624 struct mlx5_ifc_mcqi_reg_bits {
9625         u8         read_pending_component[0x1];
9626         u8         reserved_at_1[0xf];
9627         u8         component_index[0x10];
9628
9629         u8         reserved_at_20[0x20];
9630
9631         u8         reserved_at_40[0x1b];
9632         u8         info_type[0x5];
9633
9634         u8         info_size[0x20];
9635
9636         u8         offset[0x20];
9637
9638         u8         reserved_at_a0[0x10];
9639         u8         data_size[0x10];
9640
9641         union mlx5_ifc_mcqi_reg_data_bits data[0];
9642 };
9643
9644 struct mlx5_ifc_mcc_reg_bits {
9645         u8         reserved_at_0[0x4];
9646         u8         time_elapsed_since_last_cmd[0xc];
9647         u8         reserved_at_10[0x8];
9648         u8         instruction[0x8];
9649
9650         u8         reserved_at_20[0x10];
9651         u8         component_index[0x10];
9652
9653         u8         reserved_at_40[0x8];
9654         u8         update_handle[0x18];
9655
9656         u8         handle_owner_type[0x4];
9657         u8         handle_owner_host_id[0x4];
9658         u8         reserved_at_68[0x1];
9659         u8         control_progress[0x7];
9660         u8         error_code[0x8];
9661         u8         reserved_at_78[0x4];
9662         u8         control_state[0x4];
9663
9664         u8         component_size[0x20];
9665
9666         u8         reserved_at_a0[0x60];
9667 };
9668
9669 struct mlx5_ifc_mcda_reg_bits {
9670         u8         reserved_at_0[0x8];
9671         u8         update_handle[0x18];
9672
9673         u8         offset[0x20];
9674
9675         u8         reserved_at_40[0x10];
9676         u8         size[0x10];
9677
9678         u8         reserved_at_60[0x20];
9679
9680         u8         data[0][0x20];
9681 };
9682
9683 struct mlx5_ifc_mirc_reg_bits {
9684         u8         reserved_at_0[0x18];
9685         u8         status_code[0x8];
9686
9687         u8         reserved_at_20[0x20];
9688 };
9689
9690 union mlx5_ifc_ports_control_registers_document_bits {
9691         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9692         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9693         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9694         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9695         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9696         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9697         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9698         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9699         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9700         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9701         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9702         struct mlx5_ifc_paos_reg_bits paos_reg;
9703         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9704         struct mlx5_ifc_peir_reg_bits peir_reg;
9705         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9706         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9707         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9708         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9709         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9710         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9711         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9712         struct mlx5_ifc_plib_reg_bits plib_reg;
9713         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9714         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9715         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9716         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9717         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9718         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9719         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9720         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9721         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9722         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9723         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9724         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9725         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9726         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9727         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9728         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9729         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9730         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9731         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9732         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9733         struct mlx5_ifc_pude_reg_bits pude_reg;
9734         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9735         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9736         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9737         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9738         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9739         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9740         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9741         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9742         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9743         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9744         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9745         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9746         u8         reserved_at_0[0x60e0];
9747 };
9748
9749 union mlx5_ifc_debug_enhancements_document_bits {
9750         struct mlx5_ifc_health_buffer_bits health_buffer;
9751         u8         reserved_at_0[0x200];
9752 };
9753
9754 union mlx5_ifc_uplink_pci_interface_document_bits {
9755         struct mlx5_ifc_initial_seg_bits initial_seg;
9756         u8         reserved_at_0[0x20060];
9757 };
9758
9759 struct mlx5_ifc_set_flow_table_root_out_bits {
9760         u8         status[0x8];
9761         u8         reserved_at_8[0x18];
9762
9763         u8         syndrome[0x20];
9764
9765         u8         reserved_at_40[0x40];
9766 };
9767
9768 struct mlx5_ifc_set_flow_table_root_in_bits {
9769         u8         opcode[0x10];
9770         u8         reserved_at_10[0x10];
9771
9772         u8         reserved_at_20[0x10];
9773         u8         op_mod[0x10];
9774
9775         u8         other_vport[0x1];
9776         u8         reserved_at_41[0xf];
9777         u8         vport_number[0x10];
9778
9779         u8         reserved_at_60[0x20];
9780
9781         u8         table_type[0x8];
9782         u8         reserved_at_88[0x18];
9783
9784         u8         reserved_at_a0[0x8];
9785         u8         table_id[0x18];
9786
9787         u8         reserved_at_c0[0x8];
9788         u8         underlay_qpn[0x18];
9789         u8         reserved_at_e0[0x120];
9790 };
9791
9792 enum {
9793         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9794         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9795 };
9796
9797 struct mlx5_ifc_modify_flow_table_out_bits {
9798         u8         status[0x8];
9799         u8         reserved_at_8[0x18];
9800
9801         u8         syndrome[0x20];
9802
9803         u8         reserved_at_40[0x40];
9804 };
9805
9806 struct mlx5_ifc_modify_flow_table_in_bits {
9807         u8         opcode[0x10];
9808         u8         reserved_at_10[0x10];
9809
9810         u8         reserved_at_20[0x10];
9811         u8         op_mod[0x10];
9812
9813         u8         other_vport[0x1];
9814         u8         reserved_at_41[0xf];
9815         u8         vport_number[0x10];
9816
9817         u8         reserved_at_60[0x10];
9818         u8         modify_field_select[0x10];
9819
9820         u8         table_type[0x8];
9821         u8         reserved_at_88[0x18];
9822
9823         u8         reserved_at_a0[0x8];
9824         u8         table_id[0x18];
9825
9826         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9827 };
9828
9829 struct mlx5_ifc_ets_tcn_config_reg_bits {
9830         u8         g[0x1];
9831         u8         b[0x1];
9832         u8         r[0x1];
9833         u8         reserved_at_3[0x9];
9834         u8         group[0x4];
9835         u8         reserved_at_10[0x9];
9836         u8         bw_allocation[0x7];
9837
9838         u8         reserved_at_20[0xc];
9839         u8         max_bw_units[0x4];
9840         u8         reserved_at_30[0x8];
9841         u8         max_bw_value[0x8];
9842 };
9843
9844 struct mlx5_ifc_ets_global_config_reg_bits {
9845         u8         reserved_at_0[0x2];
9846         u8         r[0x1];
9847         u8         reserved_at_3[0x1d];
9848
9849         u8         reserved_at_20[0xc];
9850         u8         max_bw_units[0x4];
9851         u8         reserved_at_30[0x8];
9852         u8         max_bw_value[0x8];
9853 };
9854
9855 struct mlx5_ifc_qetc_reg_bits {
9856         u8                                         reserved_at_0[0x8];
9857         u8                                         port_number[0x8];
9858         u8                                         reserved_at_10[0x30];
9859
9860         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9861         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9862 };
9863
9864 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9865         u8         e[0x1];
9866         u8         reserved_at_01[0x0b];
9867         u8         prio[0x04];
9868 };
9869
9870 struct mlx5_ifc_qpdpm_reg_bits {
9871         u8                                     reserved_at_0[0x8];
9872         u8                                     local_port[0x8];
9873         u8                                     reserved_at_10[0x10];
9874         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9875 };
9876
9877 struct mlx5_ifc_qpts_reg_bits {
9878         u8         reserved_at_0[0x8];
9879         u8         local_port[0x8];
9880         u8         reserved_at_10[0x2d];
9881         u8         trust_state[0x3];
9882 };
9883
9884 struct mlx5_ifc_pptb_reg_bits {
9885         u8         reserved_at_0[0x2];
9886         u8         mm[0x2];
9887         u8         reserved_at_4[0x4];
9888         u8         local_port[0x8];
9889         u8         reserved_at_10[0x6];
9890         u8         cm[0x1];
9891         u8         um[0x1];
9892         u8         pm[0x8];
9893
9894         u8         prio_x_buff[0x20];
9895
9896         u8         pm_msb[0x8];
9897         u8         reserved_at_48[0x10];
9898         u8         ctrl_buff[0x4];
9899         u8         untagged_buff[0x4];
9900 };
9901
9902 struct mlx5_ifc_pbmc_reg_bits {
9903         u8         reserved_at_0[0x8];
9904         u8         local_port[0x8];
9905         u8         reserved_at_10[0x10];
9906
9907         u8         xoff_timer_value[0x10];
9908         u8         xoff_refresh[0x10];
9909
9910         u8         reserved_at_40[0x9];
9911         u8         fullness_threshold[0x7];
9912         u8         port_buffer_size[0x10];
9913
9914         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9915
9916         u8         reserved_at_2e0[0x40];
9917 };
9918
9919 struct mlx5_ifc_qtct_reg_bits {
9920         u8         reserved_at_0[0x8];
9921         u8         port_number[0x8];
9922         u8         reserved_at_10[0xd];
9923         u8         prio[0x3];
9924
9925         u8         reserved_at_20[0x1d];
9926         u8         tclass[0x3];
9927 };
9928
9929 struct mlx5_ifc_mcia_reg_bits {
9930         u8         l[0x1];
9931         u8         reserved_at_1[0x7];
9932         u8         module[0x8];
9933         u8         reserved_at_10[0x8];
9934         u8         status[0x8];
9935
9936         u8         i2c_device_address[0x8];
9937         u8         page_number[0x8];
9938         u8         device_address[0x10];
9939
9940         u8         reserved_at_40[0x10];
9941         u8         size[0x10];
9942
9943         u8         reserved_at_60[0x20];
9944
9945         u8         dword_0[0x20];
9946         u8         dword_1[0x20];
9947         u8         dword_2[0x20];
9948         u8         dword_3[0x20];
9949         u8         dword_4[0x20];
9950         u8         dword_5[0x20];
9951         u8         dword_6[0x20];
9952         u8         dword_7[0x20];
9953         u8         dword_8[0x20];
9954         u8         dword_9[0x20];
9955         u8         dword_10[0x20];
9956         u8         dword_11[0x20];
9957 };
9958
9959 struct mlx5_ifc_dcbx_param_bits {
9960         u8         dcbx_cee_cap[0x1];
9961         u8         dcbx_ieee_cap[0x1];
9962         u8         dcbx_standby_cap[0x1];
9963         u8         reserved_at_3[0x5];
9964         u8         port_number[0x8];
9965         u8         reserved_at_10[0xa];
9966         u8         max_application_table_size[6];
9967         u8         reserved_at_20[0x15];
9968         u8         version_oper[0x3];
9969         u8         reserved_at_38[5];
9970         u8         version_admin[0x3];
9971         u8         willing_admin[0x1];
9972         u8         reserved_at_41[0x3];
9973         u8         pfc_cap_oper[0x4];
9974         u8         reserved_at_48[0x4];
9975         u8         pfc_cap_admin[0x4];
9976         u8         reserved_at_50[0x4];
9977         u8         num_of_tc_oper[0x4];
9978         u8         reserved_at_58[0x4];
9979         u8         num_of_tc_admin[0x4];
9980         u8         remote_willing[0x1];
9981         u8         reserved_at_61[3];
9982         u8         remote_pfc_cap[4];
9983         u8         reserved_at_68[0x14];
9984         u8         remote_num_of_tc[0x4];
9985         u8         reserved_at_80[0x18];
9986         u8         error[0x8];
9987         u8         reserved_at_a0[0x160];
9988 };
9989
9990 struct mlx5_ifc_lagc_bits {
9991         u8         reserved_at_0[0x1d];
9992         u8         lag_state[0x3];
9993
9994         u8         reserved_at_20[0x14];
9995         u8         tx_remap_affinity_2[0x4];
9996         u8         reserved_at_38[0x4];
9997         u8         tx_remap_affinity_1[0x4];
9998 };
9999
10000 struct mlx5_ifc_create_lag_out_bits {
10001         u8         status[0x8];
10002         u8         reserved_at_8[0x18];
10003
10004         u8         syndrome[0x20];
10005
10006         u8         reserved_at_40[0x40];
10007 };
10008
10009 struct mlx5_ifc_create_lag_in_bits {
10010         u8         opcode[0x10];
10011         u8         reserved_at_10[0x10];
10012
10013         u8         reserved_at_20[0x10];
10014         u8         op_mod[0x10];
10015
10016         struct mlx5_ifc_lagc_bits ctx;
10017 };
10018
10019 struct mlx5_ifc_modify_lag_out_bits {
10020         u8         status[0x8];
10021         u8         reserved_at_8[0x18];
10022
10023         u8         syndrome[0x20];
10024
10025         u8         reserved_at_40[0x40];
10026 };
10027
10028 struct mlx5_ifc_modify_lag_in_bits {
10029         u8         opcode[0x10];
10030         u8         reserved_at_10[0x10];
10031
10032         u8         reserved_at_20[0x10];
10033         u8         op_mod[0x10];
10034
10035         u8         reserved_at_40[0x20];
10036         u8         field_select[0x20];
10037
10038         struct mlx5_ifc_lagc_bits ctx;
10039 };
10040
10041 struct mlx5_ifc_query_lag_out_bits {
10042         u8         status[0x8];
10043         u8         reserved_at_8[0x18];
10044
10045         u8         syndrome[0x20];
10046
10047         struct mlx5_ifc_lagc_bits ctx;
10048 };
10049
10050 struct mlx5_ifc_query_lag_in_bits {
10051         u8         opcode[0x10];
10052         u8         reserved_at_10[0x10];
10053
10054         u8         reserved_at_20[0x10];
10055         u8         op_mod[0x10];
10056
10057         u8         reserved_at_40[0x40];
10058 };
10059
10060 struct mlx5_ifc_destroy_lag_out_bits {
10061         u8         status[0x8];
10062         u8         reserved_at_8[0x18];
10063
10064         u8         syndrome[0x20];
10065
10066         u8         reserved_at_40[0x40];
10067 };
10068
10069 struct mlx5_ifc_destroy_lag_in_bits {
10070         u8         opcode[0x10];
10071         u8         reserved_at_10[0x10];
10072
10073         u8         reserved_at_20[0x10];
10074         u8         op_mod[0x10];
10075
10076         u8         reserved_at_40[0x40];
10077 };
10078
10079 struct mlx5_ifc_create_vport_lag_out_bits {
10080         u8         status[0x8];
10081         u8         reserved_at_8[0x18];
10082
10083         u8         syndrome[0x20];
10084
10085         u8         reserved_at_40[0x40];
10086 };
10087
10088 struct mlx5_ifc_create_vport_lag_in_bits {
10089         u8         opcode[0x10];
10090         u8         reserved_at_10[0x10];
10091
10092         u8         reserved_at_20[0x10];
10093         u8         op_mod[0x10];
10094
10095         u8         reserved_at_40[0x40];
10096 };
10097
10098 struct mlx5_ifc_destroy_vport_lag_out_bits {
10099         u8         status[0x8];
10100         u8         reserved_at_8[0x18];
10101
10102         u8         syndrome[0x20];
10103
10104         u8         reserved_at_40[0x40];
10105 };
10106
10107 struct mlx5_ifc_destroy_vport_lag_in_bits {
10108         u8         opcode[0x10];
10109         u8         reserved_at_10[0x10];
10110
10111         u8         reserved_at_20[0x10];
10112         u8         op_mod[0x10];
10113
10114         u8         reserved_at_40[0x40];
10115 };
10116
10117 struct mlx5_ifc_alloc_memic_in_bits {
10118         u8         opcode[0x10];
10119         u8         reserved_at_10[0x10];
10120
10121         u8         reserved_at_20[0x10];
10122         u8         op_mod[0x10];
10123
10124         u8         reserved_at_30[0x20];
10125
10126         u8         reserved_at_40[0x18];
10127         u8         log_memic_addr_alignment[0x8];
10128
10129         u8         range_start_addr[0x40];
10130
10131         u8         range_size[0x20];
10132
10133         u8         memic_size[0x20];
10134 };
10135
10136 struct mlx5_ifc_alloc_memic_out_bits {
10137         u8         status[0x8];
10138         u8         reserved_at_8[0x18];
10139
10140         u8         syndrome[0x20];
10141
10142         u8         memic_start_addr[0x40];
10143 };
10144
10145 struct mlx5_ifc_dealloc_memic_in_bits {
10146         u8         opcode[0x10];
10147         u8         reserved_at_10[0x10];
10148
10149         u8         reserved_at_20[0x10];
10150         u8         op_mod[0x10];
10151
10152         u8         reserved_at_40[0x40];
10153
10154         u8         memic_start_addr[0x40];
10155
10156         u8         memic_size[0x20];
10157
10158         u8         reserved_at_e0[0x20];
10159 };
10160
10161 struct mlx5_ifc_dealloc_memic_out_bits {
10162         u8         status[0x8];
10163         u8         reserved_at_8[0x18];
10164
10165         u8         syndrome[0x20];
10166
10167         u8         reserved_at_40[0x40];
10168 };
10169
10170 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10171         u8         opcode[0x10];
10172         u8         uid[0x10];
10173
10174         u8         vhca_tunnel_id[0x10];
10175         u8         obj_type[0x10];
10176
10177         u8         obj_id[0x20];
10178
10179         u8         reserved_at_60[0x20];
10180 };
10181
10182 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10183         u8         status[0x8];
10184         u8         reserved_at_8[0x18];
10185
10186         u8         syndrome[0x20];
10187
10188         u8         obj_id[0x20];
10189
10190         u8         reserved_at_60[0x20];
10191 };
10192
10193 struct mlx5_ifc_umem_bits {
10194         u8         reserved_at_0[0x80];
10195
10196         u8         reserved_at_80[0x1b];
10197         u8         log_page_size[0x5];
10198
10199         u8         page_offset[0x20];
10200
10201         u8         num_of_mtt[0x40];
10202
10203         struct mlx5_ifc_mtt_bits  mtt[0];
10204 };
10205
10206 struct mlx5_ifc_uctx_bits {
10207         u8         cap[0x20];
10208
10209         u8         reserved_at_20[0x160];
10210 };
10211
10212 struct mlx5_ifc_sw_icm_bits {
10213         u8         modify_field_select[0x40];
10214
10215         u8         reserved_at_40[0x18];
10216         u8         log_sw_icm_size[0x8];
10217
10218         u8         reserved_at_60[0x20];
10219
10220         u8         sw_icm_start_addr[0x40];
10221
10222         u8         reserved_at_c0[0x140];
10223 };
10224
10225 struct mlx5_ifc_geneve_tlv_option_bits {
10226         u8         modify_field_select[0x40];
10227
10228         u8         reserved_at_40[0x18];
10229         u8         geneve_option_fte_index[0x8];
10230
10231         u8         option_class[0x10];
10232         u8         option_type[0x8];
10233         u8         reserved_at_78[0x3];
10234         u8         option_data_length[0x5];
10235
10236         u8         reserved_at_80[0x180];
10237 };
10238
10239 struct mlx5_ifc_create_umem_in_bits {
10240         u8         opcode[0x10];
10241         u8         uid[0x10];
10242
10243         u8         reserved_at_20[0x10];
10244         u8         op_mod[0x10];
10245
10246         u8         reserved_at_40[0x40];
10247
10248         struct mlx5_ifc_umem_bits  umem;
10249 };
10250
10251 struct mlx5_ifc_create_uctx_in_bits {
10252         u8         opcode[0x10];
10253         u8         reserved_at_10[0x10];
10254
10255         u8         reserved_at_20[0x10];
10256         u8         op_mod[0x10];
10257
10258         u8         reserved_at_40[0x40];
10259
10260         struct mlx5_ifc_uctx_bits  uctx;
10261 };
10262
10263 struct mlx5_ifc_destroy_uctx_in_bits {
10264         u8         opcode[0x10];
10265         u8         reserved_at_10[0x10];
10266
10267         u8         reserved_at_20[0x10];
10268         u8         op_mod[0x10];
10269
10270         u8         reserved_at_40[0x10];
10271         u8         uid[0x10];
10272
10273         u8         reserved_at_60[0x20];
10274 };
10275
10276 struct mlx5_ifc_create_sw_icm_in_bits {
10277         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10278         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10279 };
10280
10281 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10282         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10283         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10284 };
10285
10286 struct mlx5_ifc_mtrc_string_db_param_bits {
10287         u8         string_db_base_address[0x20];
10288
10289         u8         reserved_at_20[0x8];
10290         u8         string_db_size[0x18];
10291 };
10292
10293 struct mlx5_ifc_mtrc_cap_bits {
10294         u8         trace_owner[0x1];
10295         u8         trace_to_memory[0x1];
10296         u8         reserved_at_2[0x4];
10297         u8         trc_ver[0x2];
10298         u8         reserved_at_8[0x14];
10299         u8         num_string_db[0x4];
10300
10301         u8         first_string_trace[0x8];
10302         u8         num_string_trace[0x8];
10303         u8         reserved_at_30[0x28];
10304
10305         u8         log_max_trace_buffer_size[0x8];
10306
10307         u8         reserved_at_60[0x20];
10308
10309         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10310
10311         u8         reserved_at_280[0x180];
10312 };
10313
10314 struct mlx5_ifc_mtrc_conf_bits {
10315         u8         reserved_at_0[0x1c];
10316         u8         trace_mode[0x4];
10317         u8         reserved_at_20[0x18];
10318         u8         log_trace_buffer_size[0x8];
10319         u8         trace_mkey[0x20];
10320         u8         reserved_at_60[0x3a0];
10321 };
10322
10323 struct mlx5_ifc_mtrc_stdb_bits {
10324         u8         string_db_index[0x4];
10325         u8         reserved_at_4[0x4];
10326         u8         read_size[0x18];
10327         u8         start_offset[0x20];
10328         u8         string_db_data[0];
10329 };
10330
10331 struct mlx5_ifc_mtrc_ctrl_bits {
10332         u8         trace_status[0x2];
10333         u8         reserved_at_2[0x2];
10334         u8         arm_event[0x1];
10335         u8         reserved_at_5[0xb];
10336         u8         modify_field_select[0x10];
10337         u8         reserved_at_20[0x2b];
10338         u8         current_timestamp52_32[0x15];
10339         u8         current_timestamp31_0[0x20];
10340         u8         reserved_at_80[0x180];
10341 };
10342
10343 struct mlx5_ifc_host_params_context_bits {
10344         u8         host_number[0x8];
10345         u8         reserved_at_8[0x7];
10346         u8         host_pf_disabled[0x1];
10347         u8         host_num_of_vfs[0x10];
10348
10349         u8         host_total_vfs[0x10];
10350         u8         host_pci_bus[0x10];
10351
10352         u8         reserved_at_40[0x10];
10353         u8         host_pci_device[0x10];
10354
10355         u8         reserved_at_60[0x10];
10356         u8         host_pci_function[0x10];
10357
10358         u8         reserved_at_80[0x180];
10359 };
10360
10361 struct mlx5_ifc_query_esw_functions_in_bits {
10362         u8         opcode[0x10];
10363         u8         reserved_at_10[0x10];
10364
10365         u8         reserved_at_20[0x10];
10366         u8         op_mod[0x10];
10367
10368         u8         reserved_at_40[0x40];
10369 };
10370
10371 struct mlx5_ifc_query_esw_functions_out_bits {
10372         u8         status[0x8];
10373         u8         reserved_at_8[0x18];
10374
10375         u8         syndrome[0x20];
10376
10377         u8         reserved_at_40[0x40];
10378
10379         struct mlx5_ifc_host_params_context_bits host_params_context;
10380
10381         u8         reserved_at_280[0x180];
10382         u8         host_sf_enable[0][0x40];
10383 };
10384
10385 struct mlx5_ifc_sf_partition_bits {
10386         u8         reserved_at_0[0x10];
10387         u8         log_num_sf[0x8];
10388         u8         log_sf_bar_size[0x8];
10389 };
10390
10391 struct mlx5_ifc_query_sf_partitions_out_bits {
10392         u8         status[0x8];
10393         u8         reserved_at_8[0x18];
10394
10395         u8         syndrome[0x20];
10396
10397         u8         reserved_at_40[0x18];
10398         u8         num_sf_partitions[0x8];
10399
10400         u8         reserved_at_60[0x20];
10401
10402         struct mlx5_ifc_sf_partition_bits sf_partition[0];
10403 };
10404
10405 struct mlx5_ifc_query_sf_partitions_in_bits {
10406         u8         opcode[0x10];
10407         u8         reserved_at_10[0x10];
10408
10409         u8         reserved_at_20[0x10];
10410         u8         op_mod[0x10];
10411
10412         u8         reserved_at_40[0x40];
10413 };
10414
10415 struct mlx5_ifc_dealloc_sf_out_bits {
10416         u8         status[0x8];
10417         u8         reserved_at_8[0x18];
10418
10419         u8         syndrome[0x20];
10420
10421         u8         reserved_at_40[0x40];
10422 };
10423
10424 struct mlx5_ifc_dealloc_sf_in_bits {
10425         u8         opcode[0x10];
10426         u8         reserved_at_10[0x10];
10427
10428         u8         reserved_at_20[0x10];
10429         u8         op_mod[0x10];
10430
10431         u8         reserved_at_40[0x10];
10432         u8         function_id[0x10];
10433
10434         u8         reserved_at_60[0x20];
10435 };
10436
10437 struct mlx5_ifc_alloc_sf_out_bits {
10438         u8         status[0x8];
10439         u8         reserved_at_8[0x18];
10440
10441         u8         syndrome[0x20];
10442
10443         u8         reserved_at_40[0x40];
10444 };
10445
10446 struct mlx5_ifc_alloc_sf_in_bits {
10447         u8         opcode[0x10];
10448         u8         reserved_at_10[0x10];
10449
10450         u8         reserved_at_20[0x10];
10451         u8         op_mod[0x10];
10452
10453         u8         reserved_at_40[0x10];
10454         u8         function_id[0x10];
10455
10456         u8         reserved_at_60[0x20];
10457 };
10458
10459 struct mlx5_ifc_affiliated_event_header_bits {
10460         u8         reserved_at_0[0x10];
10461         u8         obj_type[0x10];
10462
10463         u8         obj_id[0x20];
10464 };
10465
10466 enum {
10467         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10468 };
10469
10470 enum {
10471         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10472 };
10473
10474 struct mlx5_ifc_encryption_key_obj_bits {
10475         u8         modify_field_select[0x40];
10476
10477         u8         reserved_at_40[0x14];
10478         u8         key_size[0x4];
10479         u8         reserved_at_58[0x4];
10480         u8         key_type[0x4];
10481
10482         u8         reserved_at_60[0x8];
10483         u8         pd[0x18];
10484
10485         u8         reserved_at_80[0x180];
10486         u8         key[8][0x20];
10487
10488         u8         reserved_at_300[0x500];
10489 };
10490
10491 struct mlx5_ifc_create_encryption_key_in_bits {
10492         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10493         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10494 };
10495
10496 enum {
10497         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10498         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10499 };
10500
10501 enum {
10502         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10503         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10504 };
10505
10506 struct mlx5_ifc_tls_static_params_bits {
10507         u8         const_2[0x2];
10508         u8         tls_version[0x4];
10509         u8         const_1[0x2];
10510         u8         reserved_at_8[0x14];
10511         u8         encryption_standard[0x4];
10512
10513         u8         reserved_at_20[0x20];
10514
10515         u8         initial_record_number[0x40];
10516
10517         u8         resync_tcp_sn[0x20];
10518
10519         u8         gcm_iv[0x20];
10520
10521         u8         implicit_iv[0x40];
10522
10523         u8         reserved_at_100[0x8];
10524         u8         dek_index[0x18];
10525
10526         u8         reserved_at_120[0xe0];
10527 };
10528
10529 struct mlx5_ifc_tls_progress_params_bits {
10530         u8         reserved_at_0[0x8];
10531         u8         tisn[0x18];
10532
10533         u8         next_record_tcp_sn[0x20];
10534
10535         u8         hw_resync_tcp_sn[0x20];
10536
10537         u8         record_tracker_state[0x2];
10538         u8         auth_state[0x2];
10539         u8         reserved_at_64[0x4];
10540         u8         hw_offset_record_number[0x18];
10541 };
10542
10543 #endif /* MLX5_IFC_H */