include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 204         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 205         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 206         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 207         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 208         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 209         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 210         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 211         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 212         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 213         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 214         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 215         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 216         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 217         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 218         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 219         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 220         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 221         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 222         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 223         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 224         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 225         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 226         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 227         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 228         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 229         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 230         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 231         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 232         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 233         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 234         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 235         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 236         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 237         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 238         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 239         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 240         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 241         MLX5_CMD_OP_MAX
 242 };
 243
 244 struct mlx5_ifc_flow_table_fields_supported_bits {
 245         u8         outer_dmac[0x1];
 246         u8         outer_smac[0x1];
 247         u8         outer_ether_type[0x1];
 248         u8         outer_ip_version[0x1];
 249         u8         outer_first_prio[0x1];
 250         u8         outer_first_cfi[0x1];
 251         u8         outer_first_vid[0x1];
 252         u8         outer_ipv4_ttl[0x1];
 253         u8         outer_second_prio[0x1];
 254         u8         outer_second_cfi[0x1];
 255         u8         outer_second_vid[0x1];
 256         u8         reserved_at_b[0x1];
 257         u8         outer_sip[0x1];
 258         u8         outer_dip[0x1];
 259         u8         outer_frag[0x1];
 260         u8         outer_ip_protocol[0x1];
 261         u8         outer_ip_ecn[0x1];
 262         u8         outer_ip_dscp[0x1];
 263         u8         outer_udp_sport[0x1];
 264         u8         outer_udp_dport[0x1];
 265         u8         outer_tcp_sport[0x1];
 266         u8         outer_tcp_dport[0x1];
 267         u8         outer_tcp_flags[0x1];
 268         u8         outer_gre_protocol[0x1];
 269         u8         outer_gre_key[0x1];
 270         u8         outer_vxlan_vni[0x1];
 271         u8         reserved_at_1a[0x5];
 272         u8         source_eswitch_port[0x1];
 273
 274         u8         inner_dmac[0x1];
 275         u8         inner_smac[0x1];
 276         u8         inner_ether_type[0x1];
 277         u8         inner_ip_version[0x1];
 278         u8         inner_first_prio[0x1];
 279         u8         inner_first_cfi[0x1];
 280         u8         inner_first_vid[0x1];
 281         u8         reserved_at_27[0x1];
 282         u8         inner_second_prio[0x1];
 283         u8         inner_second_cfi[0x1];
 284         u8         inner_second_vid[0x1];
 285         u8         reserved_at_2b[0x1];
 286         u8         inner_sip[0x1];
 287         u8         inner_dip[0x1];
 288         u8         inner_frag[0x1];
 289         u8         inner_ip_protocol[0x1];
 290         u8         inner_ip_ecn[0x1];
 291         u8         inner_ip_dscp[0x1];
 292         u8         inner_udp_sport[0x1];
 293         u8         inner_udp_dport[0x1];
 294         u8         inner_tcp_sport[0x1];
 295         u8         inner_tcp_dport[0x1];
 296         u8         inner_tcp_flags[0x1];
 297         u8         reserved_at_37[0x9];
 298         u8         reserved_at_40[0x1a];
 299         u8         bth_dst_qp[0x1];
 300
 301         u8         reserved_at_5b[0x25];
 302 };
 303
 304 struct mlx5_ifc_flow_table_prop_layout_bits {
 305         u8         ft_support[0x1];
 306         u8         reserved_at_1[0x1];
 307         u8         flow_counter[0x1];
 308         u8         flow_modify_en[0x1];
 309         u8         modify_root[0x1];
 310         u8         identified_miss_table_mode[0x1];
 311         u8         flow_table_modify[0x1];
 312         u8         encap[0x1];
 313         u8         decap[0x1];
 314         u8         reserved_at_9[0x17];
 315
 316         u8         reserved_at_20[0x2];
 317         u8         log_max_ft_size[0x6];
 318         u8         log_max_modify_header_context[0x8];
 319         u8         max_modify_header_actions[0x8];
 320         u8         max_ft_level[0x8];
 321
 322         u8         reserved_at_40[0x20];
 323
 324         u8         reserved_at_60[0x18];
 325         u8         log_max_ft_num[0x8];
 326
 327         u8         reserved_at_80[0x18];
 328         u8         log_max_destination[0x8];
 329
 330         u8         log_max_flow_counter[0x8];
 331         u8         reserved_at_a8[0x10];
 332         u8         log_max_flow[0x8];
 333
 334         u8         reserved_at_c0[0x40];
 335
 336         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 337
 338         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 339 };
 340
 341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 342         u8         send[0x1];
 343         u8         receive[0x1];
 344         u8         write[0x1];
 345         u8         read[0x1];
 346         u8         atomic[0x1];
 347         u8         srq_receive[0x1];
 348         u8         reserved_at_6[0x1a];
 349 };
 350
 351 struct mlx5_ifc_ipv4_layout_bits {
 352         u8         reserved_at_0[0x60];
 353
 354         u8         ipv4[0x20];
 355 };
 356
 357 struct mlx5_ifc_ipv6_layout_bits {
 358         u8         ipv6[16][0x8];
 359 };
 360
 361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 362         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 363         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 364         u8         reserved_at_0[0x80];
 365 };
 366
 367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 368         u8         smac_47_16[0x20];
 369
 370         u8         smac_15_0[0x10];
 371         u8         ethertype[0x10];
 372
 373         u8         dmac_47_16[0x20];
 374
 375         u8         dmac_15_0[0x10];
 376         u8         first_prio[0x3];
 377         u8         first_cfi[0x1];
 378         u8         first_vid[0xc];
 379
 380         u8         ip_protocol[0x8];
 381         u8         ip_dscp[0x6];
 382         u8         ip_ecn[0x2];
 383         u8         cvlan_tag[0x1];
 384         u8         svlan_tag[0x1];
 385         u8         frag[0x1];
 386         u8         ip_version[0x4];
 387         u8         tcp_flags[0x9];
 388
 389         u8         tcp_sport[0x10];
 390         u8         tcp_dport[0x10];
 391
 392         u8         reserved_at_c0[0x18];
 393         u8         ttl_hoplimit[0x8];
 394
 395         u8         udp_sport[0x10];
 396         u8         udp_dport[0x10];
 397
 398         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 399
 400         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 401 };
 402
 403 struct mlx5_ifc_fte_match_set_misc_bits {
 404         u8         reserved_at_0[0x8];
 405         u8         source_sqn[0x18];
 406
 407         u8         reserved_at_20[0x10];
 408         u8         source_port[0x10];
 409
 410         u8         outer_second_prio[0x3];
 411         u8         outer_second_cfi[0x1];
 412         u8         outer_second_vid[0xc];
 413         u8         inner_second_prio[0x3];
 414         u8         inner_second_cfi[0x1];
 415         u8         inner_second_vid[0xc];
 416
 417         u8         outer_second_cvlan_tag[0x1];
 418         u8         inner_second_cvlan_tag[0x1];
 419         u8         outer_second_svlan_tag[0x1];
 420         u8         inner_second_svlan_tag[0x1];
 421         u8         reserved_at_64[0xc];
 422         u8         gre_protocol[0x10];
 423
 424         u8         gre_key_h[0x18];
 425         u8         gre_key_l[0x8];
 426
 427         u8         vxlan_vni[0x18];
 428         u8         reserved_at_b8[0x8];
 429
 430         u8         reserved_at_c0[0x20];
 431
 432         u8         reserved_at_e0[0xc];
 433         u8         outer_ipv6_flow_label[0x14];
 434
 435         u8         reserved_at_100[0xc];
 436         u8         inner_ipv6_flow_label[0x14];
 437
 438         u8         reserved_at_120[0x28];
 439         u8         bth_dst_qp[0x18];
 440         u8         reserved_at_160[0xa0];
 441 };
 442
 443 struct mlx5_ifc_cmd_pas_bits {
 444         u8         pa_h[0x20];
 445
 446         u8         pa_l[0x14];
 447         u8         reserved_at_34[0xc];
 448 };
 449
 450 struct mlx5_ifc_uint64_bits {
 451         u8         hi[0x20];
 452
 453         u8         lo[0x20];
 454 };
 455
 456 enum {
 457         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 458         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 459         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 460         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 461         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 462         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 463         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 464         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 465         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 466         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 467 };
 468
 469 struct mlx5_ifc_ads_bits {
 470         u8         fl[0x1];
 471         u8         free_ar[0x1];
 472         u8         reserved_at_2[0xe];
 473         u8         pkey_index[0x10];
 474
 475         u8         reserved_at_20[0x8];
 476         u8         grh[0x1];
 477         u8         mlid[0x7];
 478         u8         rlid[0x10];
 479
 480         u8         ack_timeout[0x5];
 481         u8         reserved_at_45[0x3];
 482         u8         src_addr_index[0x8];
 483         u8         reserved_at_50[0x4];
 484         u8         stat_rate[0x4];
 485         u8         hop_limit[0x8];
 486
 487         u8         reserved_at_60[0x4];
 488         u8         tclass[0x8];
 489         u8         flow_label[0x14];
 490
 491         u8         rgid_rip[16][0x8];
 492
 493         u8         reserved_at_100[0x4];
 494         u8         f_dscp[0x1];
 495         u8         f_ecn[0x1];
 496         u8         reserved_at_106[0x1];
 497         u8         f_eth_prio[0x1];
 498         u8         ecn[0x2];
 499         u8         dscp[0x6];
 500         u8         udp_sport[0x10];
 501
 502         u8         dei_cfi[0x1];
 503         u8         eth_prio[0x3];
 504         u8         sl[0x4];
 505         u8         port[0x8];
 506         u8         rmac_47_32[0x10];
 507
 508         u8         rmac_31_0[0x20];
 509 };
 510
 511 struct mlx5_ifc_flow_table_nic_cap_bits {
 512         u8         nic_rx_multi_path_tirs[0x1];
 513         u8         nic_rx_multi_path_tirs_fts[0x1];
 514         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 515         u8         reserved_at_3[0x1fd];
 516
 517         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 518
 519         u8         reserved_at_400[0x200];
 520
 521         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 522
 523         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 524
 525         u8         reserved_at_a00[0x200];
 526
 527         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 528
 529         u8         reserved_at_e00[0x7200];
 530 };
 531
 532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 533         u8     reserved_at_0[0x200];
 534
 535         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 536
 537         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 538
 539         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 540
 541         u8      reserved_at_800[0x7800];
 542 };
 543
 544 struct mlx5_ifc_e_switch_cap_bits {
 545         u8         vport_svlan_strip[0x1];
 546         u8         vport_cvlan_strip[0x1];
 547         u8         vport_svlan_insert[0x1];
 548         u8         vport_cvlan_insert_if_not_exist[0x1];
 549         u8         vport_cvlan_insert_overwrite[0x1];
 550         u8         reserved_at_5[0x19];
 551         u8         nic_vport_node_guid_modify[0x1];
 552         u8         nic_vport_port_guid_modify[0x1];
 553
 554         u8         vxlan_encap_decap[0x1];
 555         u8         nvgre_encap_decap[0x1];
 556         u8         reserved_at_22[0x9];
 557         u8         log_max_encap_headers[0x5];
 558         u8         reserved_2b[0x6];
 559         u8         max_encap_header_size[0xa];
 560
 561         u8         reserved_40[0x7c0];
 562
 563 };
 564
 565 struct mlx5_ifc_qos_cap_bits {
 566         u8         packet_pacing[0x1];
 567         u8         esw_scheduling[0x1];
 568         u8         esw_bw_share[0x1];
 569         u8         esw_rate_limit[0x1];
 570         u8         reserved_at_4[0x1c];
 571
 572         u8         reserved_at_20[0x20];
 573
 574         u8         packet_pacing_max_rate[0x20];
 575
 576         u8         packet_pacing_min_rate[0x20];
 577
 578         u8         reserved_at_80[0x10];
 579         u8         packet_pacing_rate_table_size[0x10];
 580
 581         u8         esw_element_type[0x10];
 582         u8         esw_tsar_type[0x10];
 583
 584         u8         reserved_at_c0[0x10];
 585         u8         max_qos_para_vport[0x10];
 586
 587         u8         max_tsar_bw_share[0x20];
 588
 589         u8         reserved_at_100[0x700];
 590 };
 591
 592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 593         u8         csum_cap[0x1];
 594         u8         vlan_cap[0x1];
 595         u8         lro_cap[0x1];
 596         u8         lro_psh_flag[0x1];
 597         u8         lro_time_stamp[0x1];
 598         u8         reserved_at_5[0x2];
 599         u8         wqe_vlan_insert[0x1];
 600         u8         self_lb_en_modifiable[0x1];
 601         u8         reserved_at_9[0x2];
 602         u8         max_lso_cap[0x5];
 603         u8         multi_pkt_send_wqe[0x2];
 604         u8         wqe_inline_mode[0x2];
 605         u8         rss_ind_tbl_cap[0x4];
 606         u8         reg_umr_sq[0x1];
 607         u8         scatter_fcs[0x1];
 608         u8         enhanced_multi_pkt_send_wqe[0x1];
 609         u8         tunnel_lso_const_out_ip_id[0x1];
 610         u8         reserved_at_1c[0x2];
 611         u8         tunnel_stateless_gre[0x1];
 612         u8         tunnel_stateless_vxlan[0x1];
 613
 614         u8         swp[0x1];
 615         u8         swp_csum[0x1];
 616         u8         swp_lso[0x1];
 617         u8         reserved_at_23[0x1d];
 618
 619         u8         reserved_at_40[0x10];
 620         u8         lro_min_mss_size[0x10];
 621
 622         u8         reserved_at_60[0x120];
 623
 624         u8         lro_timer_supported_periods[4][0x20];
 625
 626         u8         reserved_at_200[0x600];
 627 };
 628
 629 struct mlx5_ifc_roce_cap_bits {
 630         u8         roce_apm[0x1];
 631         u8         reserved_at_1[0x1f];
 632
 633         u8         reserved_at_20[0x60];
 634
 635         u8         reserved_at_80[0xc];
 636         u8         l3_type[0x4];
 637         u8         reserved_at_90[0x8];
 638         u8         roce_version[0x8];
 639
 640         u8         reserved_at_a0[0x10];
 641         u8         r_roce_dest_udp_port[0x10];
 642
 643         u8         r_roce_max_src_udp_port[0x10];
 644         u8         r_roce_min_src_udp_port[0x10];
 645
 646         u8         reserved_at_e0[0x10];
 647         u8         roce_address_table_size[0x10];
 648
 649         u8         reserved_at_100[0x700];
 650 };
 651
 652 enum {
 653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 660         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 661         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 662 };
 663
 664 enum {
 665         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 666         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 667         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 668         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 669         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 670         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 671         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 672         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 673         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 674 };
 675
 676 struct mlx5_ifc_atomic_caps_bits {
 677         u8         reserved_at_0[0x40];
 678
 679         u8         atomic_req_8B_endianness_mode[0x2];
 680         u8         reserved_at_42[0x4];
 681         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 682
 683         u8         reserved_at_47[0x19];
 684
 685         u8         reserved_at_60[0x20];
 686
 687         u8         reserved_at_80[0x10];
 688         u8         atomic_operations[0x10];
 689
 690         u8         reserved_at_a0[0x10];
 691         u8         atomic_size_qp[0x10];
 692
 693         u8         reserved_at_c0[0x10];
 694         u8         atomic_size_dc[0x10];
 695
 696         u8         reserved_at_e0[0x720];
 697 };
 698
 699 struct mlx5_ifc_odp_cap_bits {
 700         u8         reserved_at_0[0x40];
 701
 702         u8         sig[0x1];
 703         u8         reserved_at_41[0x1f];
 704
 705         u8         reserved_at_60[0x20];
 706
 707         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 708
 709         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 710
 711         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 712
 713         u8         reserved_at_e0[0x720];
 714 };
 715
 716 struct mlx5_ifc_calc_op {
 717         u8        reserved_at_0[0x10];
 718         u8        reserved_at_10[0x9];
 719         u8        op_swap_endianness[0x1];
 720         u8        op_min[0x1];
 721         u8        op_xor[0x1];
 722         u8        op_or[0x1];
 723         u8        op_and[0x1];
 724         u8        op_max[0x1];
 725         u8        op_add[0x1];
 726 };
 727
 728 struct mlx5_ifc_vector_calc_cap_bits {
 729         u8         calc_matrix[0x1];
 730         u8         reserved_at_1[0x1f];
 731         u8         reserved_at_20[0x8];
 732         u8         max_vec_count[0x8];
 733         u8         reserved_at_30[0xd];
 734         u8         max_chunk_size[0x3];
 735         struct mlx5_ifc_calc_op calc0;
 736         struct mlx5_ifc_calc_op calc1;
 737         struct mlx5_ifc_calc_op calc2;
 738         struct mlx5_ifc_calc_op calc3;
 739
 740         u8         reserved_at_e0[0x720];
 741 };
 742
 743 enum {
 744         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 745         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 746         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 747 };
 748
 749 enum {
 750         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 751         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 752 };
 753
 754 enum {
 755         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 756         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 757         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 758         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 759         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 760 };
 761
 762 enum {
 763         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 764         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 765         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 766         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 767         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 768         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 769 };
 770
 771 enum {
 772         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 773         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 774 };
 775
 776 enum {
 777         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 778         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 779         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 780 };
 781
 782 enum {
 783         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 784         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 785 };
 786
 787 enum {
 788         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 789         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 790         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 791 };
 792
 793 struct mlx5_ifc_cmd_hca_cap_bits {
 794         u8         reserved_at_0[0x80];
 795
 796         u8         log_max_srq_sz[0x8];
 797         u8         log_max_qp_sz[0x8];
 798         u8         reserved_at_90[0xb];
 799         u8         log_max_qp[0x5];
 800
 801         u8         reserved_at_a0[0xb];
 802         u8         log_max_srq[0x5];
 803         u8         reserved_at_b0[0x10];
 804
 805         u8         reserved_at_c0[0x8];
 806         u8         log_max_cq_sz[0x8];
 807         u8         reserved_at_d0[0xb];
 808         u8         log_max_cq[0x5];
 809
 810         u8         log_max_eq_sz[0x8];
 811         u8         reserved_at_e8[0x2];
 812         u8         log_max_mkey[0x6];
 813         u8         reserved_at_f0[0xc];
 814         u8         log_max_eq[0x4];
 815
 816         u8         max_indirection[0x8];
 817         u8         fixed_buffer_size[0x1];
 818         u8         log_max_mrw_sz[0x7];
 819         u8         force_teardown[0x1];
 820         u8         reserved_at_111[0x1];
 821         u8         log_max_bsf_list_size[0x6];
 822         u8         umr_extended_translation_offset[0x1];
 823         u8         null_mkey[0x1];
 824         u8         log_max_klm_list_size[0x6];
 825
 826         u8         reserved_at_120[0xa];
 827         u8         log_max_ra_req_dc[0x6];
 828         u8         reserved_at_130[0xa];
 829         u8         log_max_ra_res_dc[0x6];
 830
 831         u8         reserved_at_140[0xa];
 832         u8         log_max_ra_req_qp[0x6];
 833         u8         reserved_at_150[0xa];
 834         u8         log_max_ra_res_qp[0x6];
 835
 836         u8         end_pad[0x1];
 837         u8         cc_query_allowed[0x1];
 838         u8         cc_modify_allowed[0x1];
 839         u8         start_pad[0x1];
 840         u8         cache_line_128byte[0x1];
 841         u8         reserved_at_165[0xb];
 842         u8         gid_table_size[0x10];
 843
 844         u8         out_of_seq_cnt[0x1];
 845         u8         vport_counters[0x1];
 846         u8         retransmission_q_counters[0x1];
 847         u8         reserved_at_183[0x1];
 848         u8         modify_rq_counter_set_id[0x1];
 849         u8         rq_delay_drop[0x1];
 850         u8         max_qp_cnt[0xa];
 851         u8         pkey_table_size[0x10];
 852
 853         u8         vport_group_manager[0x1];
 854         u8         vhca_group_manager[0x1];
 855         u8         ib_virt[0x1];
 856         u8         eth_virt[0x1];
 857         u8         reserved_at_1a4[0x1];
 858         u8         ets[0x1];
 859         u8         nic_flow_table[0x1];
 860         u8         eswitch_flow_table[0x1];
 861         u8         early_vf_enable[0x1];
 862         u8         mcam_reg[0x1];
 863         u8         pcam_reg[0x1];
 864         u8         local_ca_ack_delay[0x5];
 865         u8         port_module_event[0x1];
 866         u8         enhanced_error_q_counters[0x1];
 867         u8         ports_check[0x1];
 868         u8         reserved_at_1b3[0x1];
 869         u8         disable_link_up[0x1];
 870         u8         beacon_led[0x1];
 871         u8         port_type[0x2];
 872         u8         num_ports[0x8];
 873
 874         u8         reserved_at_1c0[0x1];
 875         u8         pps[0x1];
 876         u8         pps_modify[0x1];
 877         u8         log_max_msg[0x5];
 878         u8         reserved_at_1c8[0x4];
 879         u8         max_tc[0x4];
 880         u8         reserved_at_1d0[0x1];
 881         u8         dcbx[0x1];
 882         u8         general_notification_event[0x1];
 883         u8         reserved_at_1d3[0x2];
 884         u8         fpga[0x1];
 885         u8         rol_s[0x1];
 886         u8         rol_g[0x1];
 887         u8         reserved_at_1d8[0x1];
 888         u8         wol_s[0x1];
 889         u8         wol_g[0x1];
 890         u8         wol_a[0x1];
 891         u8         wol_b[0x1];
 892         u8         wol_m[0x1];
 893         u8         wol_u[0x1];
 894         u8         wol_p[0x1];
 895
 896         u8         stat_rate_support[0x10];
 897         u8         reserved_at_1f0[0xc];
 898         u8         cqe_version[0x4];
 899
 900         u8         compact_address_vector[0x1];
 901         u8         striding_rq[0x1];
 902         u8         reserved_at_202[0x1];
 903         u8         ipoib_enhanced_offloads[0x1];
 904         u8         ipoib_basic_offloads[0x1];
 905         u8         reserved_at_205[0x5];
 906         u8         umr_fence[0x2];
 907         u8         reserved_at_20c[0x3];
 908         u8         drain_sigerr[0x1];
 909         u8         cmdif_checksum[0x2];
 910         u8         sigerr_cqe[0x1];
 911         u8         reserved_at_213[0x1];
 912         u8         wq_signature[0x1];
 913         u8         sctr_data_cqe[0x1];
 914         u8         reserved_at_216[0x1];
 915         u8         sho[0x1];
 916         u8         tph[0x1];
 917         u8         rf[0x1];
 918         u8         dct[0x1];
 919         u8         qos[0x1];
 920         u8         eth_net_offloads[0x1];
 921         u8         roce[0x1];
 922         u8         atomic[0x1];
 923         u8         reserved_at_21f[0x1];
 924
 925         u8         cq_oi[0x1];
 926         u8         cq_resize[0x1];
 927         u8         cq_moderation[0x1];
 928         u8         reserved_at_223[0x3];
 929         u8         cq_eq_remap[0x1];
 930         u8         pg[0x1];
 931         u8         block_lb_mc[0x1];
 932         u8         reserved_at_229[0x1];
 933         u8         scqe_break_moderation[0x1];
 934         u8         cq_period_start_from_cqe[0x1];
 935         u8         cd[0x1];
 936         u8         reserved_at_22d[0x1];
 937         u8         apm[0x1];
 938         u8         vector_calc[0x1];
 939         u8         umr_ptr_rlky[0x1];
 940         u8         imaicl[0x1];
 941         u8         reserved_at_232[0x4];
 942         u8         qkv[0x1];
 943         u8         pkv[0x1];
 944         u8         set_deth_sqpn[0x1];
 945         u8         reserved_at_239[0x3];
 946         u8         xrc[0x1];
 947         u8         ud[0x1];
 948         u8         uc[0x1];
 949         u8         rc[0x1];
 950
 951         u8         uar_4k[0x1];
 952         u8         reserved_at_241[0x9];
 953         u8         uar_sz[0x6];
 954         u8         reserved_at_250[0x8];
 955         u8         log_pg_sz[0x8];
 956
 957         u8         bf[0x1];
 958         u8         driver_version[0x1];
 959         u8         pad_tx_eth_packet[0x1];
 960         u8         reserved_at_263[0x8];
 961         u8         log_bf_reg_size[0x5];
 962
 963         u8         reserved_at_270[0xb];
 964         u8         lag_master[0x1];
 965         u8         num_lag_ports[0x4];
 966
 967         u8         reserved_at_280[0x10];
 968         u8         max_wqe_sz_sq[0x10];
 969
 970         u8         reserved_at_2a0[0x10];
 971         u8         max_wqe_sz_rq[0x10];
 972
 973         u8         max_flow_counter_31_16[0x10];
 974         u8         max_wqe_sz_sq_dc[0x10];
 975
 976         u8         reserved_at_2e0[0x7];
 977         u8         max_qp_mcg[0x19];
 978
 979         u8         reserved_at_300[0x18];
 980         u8         log_max_mcg[0x8];
 981
 982         u8         reserved_at_320[0x3];
 983         u8         log_max_transport_domain[0x5];
 984         u8         reserved_at_328[0x3];
 985         u8         log_max_pd[0x5];
 986         u8         reserved_at_330[0xb];
 987         u8         log_max_xrcd[0x5];
 988
 989         u8         reserved_at_340[0x8];
 990         u8         log_max_flow_counter_bulk[0x8];
 991         u8         max_flow_counter_15_0[0x10];
 992
 993
 994         u8         reserved_at_360[0x3];
 995         u8         log_max_rq[0x5];
 996         u8         reserved_at_368[0x3];
 997         u8         log_max_sq[0x5];
 998         u8         reserved_at_370[0x3];
 999         u8         log_max_tir[0x5];
1000         u8         reserved_at_378[0x3];
1001         u8         log_max_tis[0x5];
1002
1003         u8         basic_cyclic_rcv_wqe[0x1];
1004         u8         reserved_at_381[0x2];
1005         u8         log_max_rmp[0x5];
1006         u8         reserved_at_388[0x3];
1007         u8         log_max_rqt[0x5];
1008         u8         reserved_at_390[0x3];
1009         u8         log_max_rqt_size[0x5];
1010         u8         reserved_at_398[0x3];
1011         u8         log_max_tis_per_sq[0x5];
1012
1013         u8         reserved_at_3a0[0x3];
1014         u8         log_max_stride_sz_rq[0x5];
1015         u8         reserved_at_3a8[0x3];
1016         u8         log_min_stride_sz_rq[0x5];
1017         u8         reserved_at_3b0[0x3];
1018         u8         log_max_stride_sz_sq[0x5];
1019         u8         reserved_at_3b8[0x3];
1020         u8         log_min_stride_sz_sq[0x5];
1021
1022         u8         reserved_at_3c0[0x1b];
1023         u8         log_max_wq_sz[0x5];
1024
1025         u8         nic_vport_change_event[0x1];
1026         u8         disable_local_lb[0x1];
1027         u8         reserved_at_3e2[0x9];
1028         u8         log_max_vlan_list[0x5];
1029         u8         reserved_at_3f0[0x3];
1030         u8         log_max_current_mc_list[0x5];
1031         u8         reserved_at_3f8[0x3];
1032         u8         log_max_current_uc_list[0x5];
1033
1034         u8         reserved_at_400[0x80];
1035
1036         u8         reserved_at_480[0x3];
1037         u8         log_max_l2_table[0x5];
1038         u8         reserved_at_488[0x8];
1039         u8         log_uar_page_sz[0x10];
1040
1041         u8         reserved_at_4a0[0x20];
1042         u8         device_frequency_mhz[0x20];
1043         u8         device_frequency_khz[0x20];
1044
1045         u8         reserved_at_500[0x20];
1046         u8         num_of_uars_per_page[0x20];
1047         u8         reserved_at_540[0x40];
1048
1049         u8         reserved_at_580[0x3f];
1050         u8         cqe_compression[0x1];
1051
1052         u8         cqe_compression_timeout[0x10];
1053         u8         cqe_compression_max_num[0x10];
1054
1055         u8         reserved_at_5e0[0x10];
1056         u8         tag_matching[0x1];
1057         u8         rndv_offload_rc[0x1];
1058         u8         rndv_offload_dc[0x1];
1059         u8         log_tag_matching_list_sz[0x5];
1060         u8         reserved_at_5f8[0x3];
1061         u8         log_max_xrq[0x5];
1062
1063         u8         reserved_at_600[0x200];
1064 };
1065
1066 enum mlx5_flow_destination_type {
1067         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1068         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1069         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1070
1071         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1072 };
1073
1074 struct mlx5_ifc_dest_format_struct_bits {
1075         u8         destination_type[0x8];
1076         u8         destination_id[0x18];
1077
1078         u8         reserved_at_20[0x20];
1079 };
1080
1081 struct mlx5_ifc_flow_counter_list_bits {
1082         u8         flow_counter_id[0x20];
1083
1084         u8         reserved_at_20[0x20];
1085 };
1086
1087 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1088         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1089         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1090         u8         reserved_at_0[0x40];
1091 };
1092
1093 struct mlx5_ifc_fte_match_param_bits {
1094         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1095
1096         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1097
1098         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1099
1100         u8         reserved_at_600[0xa00];
1101 };
1102
1103 enum {
1104         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1105         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1106         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1107         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1108         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1109 };
1110
1111 struct mlx5_ifc_rx_hash_field_select_bits {
1112         u8         l3_prot_type[0x1];
1113         u8         l4_prot_type[0x1];
1114         u8         selected_fields[0x1e];
1115 };
1116
1117 enum {
1118         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1119         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1120 };
1121
1122 enum {
1123         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1124         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1125 };
1126
1127 struct mlx5_ifc_wq_bits {
1128         u8         wq_type[0x4];
1129         u8         wq_signature[0x1];
1130         u8         end_padding_mode[0x2];
1131         u8         cd_slave[0x1];
1132         u8         reserved_at_8[0x18];
1133
1134         u8         hds_skip_first_sge[0x1];
1135         u8         log2_hds_buf_size[0x3];
1136         u8         reserved_at_24[0x7];
1137         u8         page_offset[0x5];
1138         u8         lwm[0x10];
1139
1140         u8         reserved_at_40[0x8];
1141         u8         pd[0x18];
1142
1143         u8         reserved_at_60[0x8];
1144         u8         uar_page[0x18];
1145
1146         u8         dbr_addr[0x40];
1147
1148         u8         hw_counter[0x20];
1149
1150         u8         sw_counter[0x20];
1151
1152         u8         reserved_at_100[0xc];
1153         u8         log_wq_stride[0x4];
1154         u8         reserved_at_110[0x3];
1155         u8         log_wq_pg_sz[0x5];
1156         u8         reserved_at_118[0x3];
1157         u8         log_wq_sz[0x5];
1158
1159         u8         reserved_at_120[0x15];
1160         u8         log_wqe_num_of_strides[0x3];
1161         u8         two_byte_shift_en[0x1];
1162         u8         reserved_at_139[0x4];
1163         u8         log_wqe_stride_size[0x3];
1164
1165         u8         reserved_at_140[0x4c0];
1166
1167         struct mlx5_ifc_cmd_pas_bits pas[0];
1168 };
1169
1170 struct mlx5_ifc_rq_num_bits {
1171         u8         reserved_at_0[0x8];
1172         u8         rq_num[0x18];
1173 };
1174
1175 struct mlx5_ifc_mac_address_layout_bits {
1176         u8         reserved_at_0[0x10];
1177         u8         mac_addr_47_32[0x10];
1178
1179         u8         mac_addr_31_0[0x20];
1180 };
1181
1182 struct mlx5_ifc_vlan_layout_bits {
1183         u8         reserved_at_0[0x14];
1184         u8         vlan[0x0c];
1185
1186         u8         reserved_at_20[0x20];
1187 };
1188
1189 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1190         u8         reserved_at_0[0xa0];
1191
1192         u8         min_time_between_cnps[0x20];
1193
1194         u8         reserved_at_c0[0x12];
1195         u8         cnp_dscp[0x6];
1196         u8         reserved_at_d8[0x4];
1197         u8         cnp_prio_mode[0x1];
1198         u8         cnp_802p_prio[0x3];
1199
1200         u8         reserved_at_e0[0x720];
1201 };
1202
1203 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1204         u8         reserved_at_0[0x60];
1205
1206         u8         reserved_at_60[0x4];
1207         u8         clamp_tgt_rate[0x1];
1208         u8         reserved_at_65[0x3];
1209         u8         clamp_tgt_rate_after_time_inc[0x1];
1210         u8         reserved_at_69[0x17];
1211
1212         u8         reserved_at_80[0x20];
1213
1214         u8         rpg_time_reset[0x20];
1215
1216         u8         rpg_byte_reset[0x20];
1217
1218         u8         rpg_threshold[0x20];
1219
1220         u8         rpg_max_rate[0x20];
1221
1222         u8         rpg_ai_rate[0x20];
1223
1224         u8         rpg_hai_rate[0x20];
1225
1226         u8         rpg_gd[0x20];
1227
1228         u8         rpg_min_dec_fac[0x20];
1229
1230         u8         rpg_min_rate[0x20];
1231
1232         u8         reserved_at_1c0[0xe0];
1233
1234         u8         rate_to_set_on_first_cnp[0x20];
1235
1236         u8         dce_tcp_g[0x20];
1237
1238         u8         dce_tcp_rtt[0x20];
1239
1240         u8         rate_reduce_monitor_period[0x20];
1241
1242         u8         reserved_at_320[0x20];
1243
1244         u8         initial_alpha_value[0x20];
1245
1246         u8         reserved_at_360[0x4a0];
1247 };
1248
1249 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1250         u8         reserved_at_0[0x80];
1251
1252         u8         rppp_max_rps[0x20];
1253
1254         u8         rpg_time_reset[0x20];
1255
1256         u8         rpg_byte_reset[0x20];
1257
1258         u8         rpg_threshold[0x20];
1259
1260         u8         rpg_max_rate[0x20];
1261
1262         u8         rpg_ai_rate[0x20];
1263
1264         u8         rpg_hai_rate[0x20];
1265
1266         u8         rpg_gd[0x20];
1267
1268         u8         rpg_min_dec_fac[0x20];
1269
1270         u8         rpg_min_rate[0x20];
1271
1272         u8         reserved_at_1c0[0x640];
1273 };
1274
1275 enum {
1276         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1277         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1278         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1279 };
1280
1281 struct mlx5_ifc_resize_field_select_bits {
1282         u8         resize_field_select[0x20];
1283 };
1284
1285 enum {
1286         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1287         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1288         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1289         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1290 };
1291
1292 struct mlx5_ifc_modify_field_select_bits {
1293         u8         modify_field_select[0x20];
1294 };
1295
1296 struct mlx5_ifc_field_select_r_roce_np_bits {
1297         u8         field_select_r_roce_np[0x20];
1298 };
1299
1300 struct mlx5_ifc_field_select_r_roce_rp_bits {
1301         u8         field_select_r_roce_rp[0x20];
1302 };
1303
1304 enum {
1305         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1306         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1307         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1308         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1309         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1310         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1311         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1312         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1313         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1314         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1315 };
1316
1317 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1318         u8         field_select_8021qaurp[0x20];
1319 };
1320
1321 struct mlx5_ifc_phys_layer_cntrs_bits {
1322         u8         time_since_last_clear_high[0x20];
1323
1324         u8         time_since_last_clear_low[0x20];
1325
1326         u8         symbol_errors_high[0x20];
1327
1328         u8         symbol_errors_low[0x20];
1329
1330         u8         sync_headers_errors_high[0x20];
1331
1332         u8         sync_headers_errors_low[0x20];
1333
1334         u8         edpl_bip_errors_lane0_high[0x20];
1335
1336         u8         edpl_bip_errors_lane0_low[0x20];
1337
1338         u8         edpl_bip_errors_lane1_high[0x20];
1339
1340         u8         edpl_bip_errors_lane1_low[0x20];
1341
1342         u8         edpl_bip_errors_lane2_high[0x20];
1343
1344         u8         edpl_bip_errors_lane2_low[0x20];
1345
1346         u8         edpl_bip_errors_lane3_high[0x20];
1347
1348         u8         edpl_bip_errors_lane3_low[0x20];
1349
1350         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1351
1352         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1353
1354         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1355
1356         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1357
1358         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1359
1360         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1361
1362         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1363
1364         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1365
1366         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1367
1368         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1369
1370         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1371
1372         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1373
1374         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1375
1376         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1377
1378         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1379
1380         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1381
1382         u8         rs_fec_corrected_blocks_high[0x20];
1383
1384         u8         rs_fec_corrected_blocks_low[0x20];
1385
1386         u8         rs_fec_uncorrectable_blocks_high[0x20];
1387
1388         u8         rs_fec_uncorrectable_blocks_low[0x20];
1389
1390         u8         rs_fec_no_errors_blocks_high[0x20];
1391
1392         u8         rs_fec_no_errors_blocks_low[0x20];
1393
1394         u8         rs_fec_single_error_blocks_high[0x20];
1395
1396         u8         rs_fec_single_error_blocks_low[0x20];
1397
1398         u8         rs_fec_corrected_symbols_total_high[0x20];
1399
1400         u8         rs_fec_corrected_symbols_total_low[0x20];
1401
1402         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1403
1404         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1405
1406         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1407
1408         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1409
1410         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1411
1412         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1413
1414         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1415
1416         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1417
1418         u8         link_down_events[0x20];
1419
1420         u8         successful_recovery_events[0x20];
1421
1422         u8         reserved_at_640[0x180];
1423 };
1424
1425 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1426         u8         time_since_last_clear_high[0x20];
1427
1428         u8         time_since_last_clear_low[0x20];
1429
1430         u8         phy_received_bits_high[0x20];
1431
1432         u8         phy_received_bits_low[0x20];
1433
1434         u8         phy_symbol_errors_high[0x20];
1435
1436         u8         phy_symbol_errors_low[0x20];
1437
1438         u8         phy_corrected_bits_high[0x20];
1439
1440         u8         phy_corrected_bits_low[0x20];
1441
1442         u8         phy_corrected_bits_lane0_high[0x20];
1443
1444         u8         phy_corrected_bits_lane0_low[0x20];
1445
1446         u8         phy_corrected_bits_lane1_high[0x20];
1447
1448         u8         phy_corrected_bits_lane1_low[0x20];
1449
1450         u8         phy_corrected_bits_lane2_high[0x20];
1451
1452         u8         phy_corrected_bits_lane2_low[0x20];
1453
1454         u8         phy_corrected_bits_lane3_high[0x20];
1455
1456         u8         phy_corrected_bits_lane3_low[0x20];
1457
1458         u8         reserved_at_200[0x5c0];
1459 };
1460
1461 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1462         u8         symbol_error_counter[0x10];
1463
1464         u8         link_error_recovery_counter[0x8];
1465
1466         u8         link_downed_counter[0x8];
1467
1468         u8         port_rcv_errors[0x10];
1469
1470         u8         port_rcv_remote_physical_errors[0x10];
1471
1472         u8         port_rcv_switch_relay_errors[0x10];
1473
1474         u8         port_xmit_discards[0x10];
1475
1476         u8         port_xmit_constraint_errors[0x8];
1477
1478         u8         port_rcv_constraint_errors[0x8];
1479
1480         u8         reserved_at_70[0x8];
1481
1482         u8         link_overrun_errors[0x8];
1483
1484         u8         reserved_at_80[0x10];
1485
1486         u8         vl_15_dropped[0x10];
1487
1488         u8         reserved_at_a0[0x80];
1489
1490         u8         port_xmit_wait[0x20];
1491 };
1492
1493 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1494         u8         transmit_queue_high[0x20];
1495
1496         u8         transmit_queue_low[0x20];
1497
1498         u8         reserved_at_40[0x780];
1499 };
1500
1501 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1502         u8         rx_octets_high[0x20];
1503
1504         u8         rx_octets_low[0x20];
1505
1506         u8         reserved_at_40[0xc0];
1507
1508         u8         rx_frames_high[0x20];
1509
1510         u8         rx_frames_low[0x20];
1511
1512         u8         tx_octets_high[0x20];
1513
1514         u8         tx_octets_low[0x20];
1515
1516         u8         reserved_at_180[0xc0];
1517
1518         u8         tx_frames_high[0x20];
1519
1520         u8         tx_frames_low[0x20];
1521
1522         u8         rx_pause_high[0x20];
1523
1524         u8         rx_pause_low[0x20];
1525
1526         u8         rx_pause_duration_high[0x20];
1527
1528         u8         rx_pause_duration_low[0x20];
1529
1530         u8         tx_pause_high[0x20];
1531
1532         u8         tx_pause_low[0x20];
1533
1534         u8         tx_pause_duration_high[0x20];
1535
1536         u8         tx_pause_duration_low[0x20];
1537
1538         u8         rx_pause_transition_high[0x20];
1539
1540         u8         rx_pause_transition_low[0x20];
1541
1542         u8         reserved_at_3c0[0x400];
1543 };
1544
1545 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1546         u8         port_transmit_wait_high[0x20];
1547
1548         u8         port_transmit_wait_low[0x20];
1549
1550         u8         reserved_at_40[0x100];
1551
1552         u8         rx_buffer_almost_full_high[0x20];
1553
1554         u8         rx_buffer_almost_full_low[0x20];
1555
1556         u8         rx_buffer_full_high[0x20];
1557
1558         u8         rx_buffer_full_low[0x20];
1559
1560         u8         reserved_at_1c0[0x600];
1561 };
1562
1563 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1564         u8         dot3stats_alignment_errors_high[0x20];
1565
1566         u8         dot3stats_alignment_errors_low[0x20];
1567
1568         u8         dot3stats_fcs_errors_high[0x20];
1569
1570         u8         dot3stats_fcs_errors_low[0x20];
1571
1572         u8         dot3stats_single_collision_frames_high[0x20];
1573
1574         u8         dot3stats_single_collision_frames_low[0x20];
1575
1576         u8         dot3stats_multiple_collision_frames_high[0x20];
1577
1578         u8         dot3stats_multiple_collision_frames_low[0x20];
1579
1580         u8         dot3stats_sqe_test_errors_high[0x20];
1581
1582         u8         dot3stats_sqe_test_errors_low[0x20];
1583
1584         u8         dot3stats_deferred_transmissions_high[0x20];
1585
1586         u8         dot3stats_deferred_transmissions_low[0x20];
1587
1588         u8         dot3stats_late_collisions_high[0x20];
1589
1590         u8         dot3stats_late_collisions_low[0x20];
1591
1592         u8         dot3stats_excessive_collisions_high[0x20];
1593
1594         u8         dot3stats_excessive_collisions_low[0x20];
1595
1596         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1597
1598         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1599
1600         u8         dot3stats_carrier_sense_errors_high[0x20];
1601
1602         u8         dot3stats_carrier_sense_errors_low[0x20];
1603
1604         u8         dot3stats_frame_too_longs_high[0x20];
1605
1606         u8         dot3stats_frame_too_longs_low[0x20];
1607
1608         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1609
1610         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1611
1612         u8         dot3stats_symbol_errors_high[0x20];
1613
1614         u8         dot3stats_symbol_errors_low[0x20];
1615
1616         u8         dot3control_in_unknown_opcodes_high[0x20];
1617
1618         u8         dot3control_in_unknown_opcodes_low[0x20];
1619
1620         u8         dot3in_pause_frames_high[0x20];
1621
1622         u8         dot3in_pause_frames_low[0x20];
1623
1624         u8         dot3out_pause_frames_high[0x20];
1625
1626         u8         dot3out_pause_frames_low[0x20];
1627
1628         u8         reserved_at_400[0x3c0];
1629 };
1630
1631 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1632         u8         ether_stats_drop_events_high[0x20];
1633
1634         u8         ether_stats_drop_events_low[0x20];
1635
1636         u8         ether_stats_octets_high[0x20];
1637
1638         u8         ether_stats_octets_low[0x20];
1639
1640         u8         ether_stats_pkts_high[0x20];
1641
1642         u8         ether_stats_pkts_low[0x20];
1643
1644         u8         ether_stats_broadcast_pkts_high[0x20];
1645
1646         u8         ether_stats_broadcast_pkts_low[0x20];
1647
1648         u8         ether_stats_multicast_pkts_high[0x20];
1649
1650         u8         ether_stats_multicast_pkts_low[0x20];
1651
1652         u8         ether_stats_crc_align_errors_high[0x20];
1653
1654         u8         ether_stats_crc_align_errors_low[0x20];
1655
1656         u8         ether_stats_undersize_pkts_high[0x20];
1657
1658         u8         ether_stats_undersize_pkts_low[0x20];
1659
1660         u8         ether_stats_oversize_pkts_high[0x20];
1661
1662         u8         ether_stats_oversize_pkts_low[0x20];
1663
1664         u8         ether_stats_fragments_high[0x20];
1665
1666         u8         ether_stats_fragments_low[0x20];
1667
1668         u8         ether_stats_jabbers_high[0x20];
1669
1670         u8         ether_stats_jabbers_low[0x20];
1671
1672         u8         ether_stats_collisions_high[0x20];
1673
1674         u8         ether_stats_collisions_low[0x20];
1675
1676         u8         ether_stats_pkts64octets_high[0x20];
1677
1678         u8         ether_stats_pkts64octets_low[0x20];
1679
1680         u8         ether_stats_pkts65to127octets_high[0x20];
1681
1682         u8         ether_stats_pkts65to127octets_low[0x20];
1683
1684         u8         ether_stats_pkts128to255octets_high[0x20];
1685
1686         u8         ether_stats_pkts128to255octets_low[0x20];
1687
1688         u8         ether_stats_pkts256to511octets_high[0x20];
1689
1690         u8         ether_stats_pkts256to511octets_low[0x20];
1691
1692         u8         ether_stats_pkts512to1023octets_high[0x20];
1693
1694         u8         ether_stats_pkts512to1023octets_low[0x20];
1695
1696         u8         ether_stats_pkts1024to1518octets_high[0x20];
1697
1698         u8         ether_stats_pkts1024to1518octets_low[0x20];
1699
1700         u8         ether_stats_pkts1519to2047octets_high[0x20];
1701
1702         u8         ether_stats_pkts1519to2047octets_low[0x20];
1703
1704         u8         ether_stats_pkts2048to4095octets_high[0x20];
1705
1706         u8         ether_stats_pkts2048to4095octets_low[0x20];
1707
1708         u8         ether_stats_pkts4096to8191octets_high[0x20];
1709
1710         u8         ether_stats_pkts4096to8191octets_low[0x20];
1711
1712         u8         ether_stats_pkts8192to10239octets_high[0x20];
1713
1714         u8         ether_stats_pkts8192to10239octets_low[0x20];
1715
1716         u8         reserved_at_540[0x280];
1717 };
1718
1719 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1720         u8         if_in_octets_high[0x20];
1721
1722         u8         if_in_octets_low[0x20];
1723
1724         u8         if_in_ucast_pkts_high[0x20];
1725
1726         u8         if_in_ucast_pkts_low[0x20];
1727
1728         u8         if_in_discards_high[0x20];
1729
1730         u8         if_in_discards_low[0x20];
1731
1732         u8         if_in_errors_high[0x20];
1733
1734         u8         if_in_errors_low[0x20];
1735
1736         u8         if_in_unknown_protos_high[0x20];
1737
1738         u8         if_in_unknown_protos_low[0x20];
1739
1740         u8         if_out_octets_high[0x20];
1741
1742         u8         if_out_octets_low[0x20];
1743
1744         u8         if_out_ucast_pkts_high[0x20];
1745
1746         u8         if_out_ucast_pkts_low[0x20];
1747
1748         u8         if_out_discards_high[0x20];
1749
1750         u8         if_out_discards_low[0x20];
1751
1752         u8         if_out_errors_high[0x20];
1753
1754         u8         if_out_errors_low[0x20];
1755
1756         u8         if_in_multicast_pkts_high[0x20];
1757
1758         u8         if_in_multicast_pkts_low[0x20];
1759
1760         u8         if_in_broadcast_pkts_high[0x20];
1761
1762         u8         if_in_broadcast_pkts_low[0x20];
1763
1764         u8         if_out_multicast_pkts_high[0x20];
1765
1766         u8         if_out_multicast_pkts_low[0x20];
1767
1768         u8         if_out_broadcast_pkts_high[0x20];
1769
1770         u8         if_out_broadcast_pkts_low[0x20];
1771
1772         u8         reserved_at_340[0x480];
1773 };
1774
1775 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1776         u8         a_frames_transmitted_ok_high[0x20];
1777
1778         u8         a_frames_transmitted_ok_low[0x20];
1779
1780         u8         a_frames_received_ok_high[0x20];
1781
1782         u8         a_frames_received_ok_low[0x20];
1783
1784         u8         a_frame_check_sequence_errors_high[0x20];
1785
1786         u8         a_frame_check_sequence_errors_low[0x20];
1787
1788         u8         a_alignment_errors_high[0x20];
1789
1790         u8         a_alignment_errors_low[0x20];
1791
1792         u8         a_octets_transmitted_ok_high[0x20];
1793
1794         u8         a_octets_transmitted_ok_low[0x20];
1795
1796         u8         a_octets_received_ok_high[0x20];
1797
1798         u8         a_octets_received_ok_low[0x20];
1799
1800         u8         a_multicast_frames_xmitted_ok_high[0x20];
1801
1802         u8         a_multicast_frames_xmitted_ok_low[0x20];
1803
1804         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1805
1806         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1807
1808         u8         a_multicast_frames_received_ok_high[0x20];
1809
1810         u8         a_multicast_frames_received_ok_low[0x20];
1811
1812         u8         a_broadcast_frames_received_ok_high[0x20];
1813
1814         u8         a_broadcast_frames_received_ok_low[0x20];
1815
1816         u8         a_in_range_length_errors_high[0x20];
1817
1818         u8         a_in_range_length_errors_low[0x20];
1819
1820         u8         a_out_of_range_length_field_high[0x20];
1821
1822         u8         a_out_of_range_length_field_low[0x20];
1823
1824         u8         a_frame_too_long_errors_high[0x20];
1825
1826         u8         a_frame_too_long_errors_low[0x20];
1827
1828         u8         a_symbol_error_during_carrier_high[0x20];
1829
1830         u8         a_symbol_error_during_carrier_low[0x20];
1831
1832         u8         a_mac_control_frames_transmitted_high[0x20];
1833
1834         u8         a_mac_control_frames_transmitted_low[0x20];
1835
1836         u8         a_mac_control_frames_received_high[0x20];
1837
1838         u8         a_mac_control_frames_received_low[0x20];
1839
1840         u8         a_unsupported_opcodes_received_high[0x20];
1841
1842         u8         a_unsupported_opcodes_received_low[0x20];
1843
1844         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1845
1846         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1847
1848         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1849
1850         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1851
1852         u8         reserved_at_4c0[0x300];
1853 };
1854
1855 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1856         u8         life_time_counter_high[0x20];
1857
1858         u8         life_time_counter_low[0x20];
1859
1860         u8         rx_errors[0x20];
1861
1862         u8         tx_errors[0x20];
1863
1864         u8         l0_to_recovery_eieos[0x20];
1865
1866         u8         l0_to_recovery_ts[0x20];
1867
1868         u8         l0_to_recovery_framing[0x20];
1869
1870         u8         l0_to_recovery_retrain[0x20];
1871
1872         u8         crc_error_dllp[0x20];
1873
1874         u8         crc_error_tlp[0x20];
1875
1876         u8         tx_overflow_buffer_pkt_high[0x20];
1877
1878         u8         tx_overflow_buffer_pkt_low[0x20];
1879
1880         u8         outbound_stalled_reads[0x20];
1881
1882         u8         outbound_stalled_writes[0x20];
1883
1884         u8         outbound_stalled_reads_events[0x20];
1885
1886         u8         outbound_stalled_writes_events[0x20];
1887
1888         u8         reserved_at_200[0x5c0];
1889 };
1890
1891 struct mlx5_ifc_cmd_inter_comp_event_bits {
1892         u8         command_completion_vector[0x20];
1893
1894         u8         reserved_at_20[0xc0];
1895 };
1896
1897 struct mlx5_ifc_stall_vl_event_bits {
1898         u8         reserved_at_0[0x18];
1899         u8         port_num[0x1];
1900         u8         reserved_at_19[0x3];
1901         u8         vl[0x4];
1902
1903         u8         reserved_at_20[0xa0];
1904 };
1905
1906 struct mlx5_ifc_db_bf_congestion_event_bits {
1907         u8         event_subtype[0x8];
1908         u8         reserved_at_8[0x8];
1909         u8         congestion_level[0x8];
1910         u8         reserved_at_18[0x8];
1911
1912         u8         reserved_at_20[0xa0];
1913 };
1914
1915 struct mlx5_ifc_gpio_event_bits {
1916         u8         reserved_at_0[0x60];
1917
1918         u8         gpio_event_hi[0x20];
1919
1920         u8         gpio_event_lo[0x20];
1921
1922         u8         reserved_at_a0[0x40];
1923 };
1924
1925 struct mlx5_ifc_port_state_change_event_bits {
1926         u8         reserved_at_0[0x40];
1927
1928         u8         port_num[0x4];
1929         u8         reserved_at_44[0x1c];
1930
1931         u8         reserved_at_60[0x80];
1932 };
1933
1934 struct mlx5_ifc_dropped_packet_logged_bits {
1935         u8         reserved_at_0[0xe0];
1936 };
1937
1938 enum {
1939         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1940         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1941 };
1942
1943 struct mlx5_ifc_cq_error_bits {
1944         u8         reserved_at_0[0x8];
1945         u8         cqn[0x18];
1946
1947         u8         reserved_at_20[0x20];
1948
1949         u8         reserved_at_40[0x18];
1950         u8         syndrome[0x8];
1951
1952         u8         reserved_at_60[0x80];
1953 };
1954
1955 struct mlx5_ifc_rdma_page_fault_event_bits {
1956         u8         bytes_committed[0x20];
1957
1958         u8         r_key[0x20];
1959
1960         u8         reserved_at_40[0x10];
1961         u8         packet_len[0x10];
1962
1963         u8         rdma_op_len[0x20];
1964
1965         u8         rdma_va[0x40];
1966
1967         u8         reserved_at_c0[0x5];
1968         u8         rdma[0x1];
1969         u8         write[0x1];
1970         u8         requestor[0x1];
1971         u8         qp_number[0x18];
1972 };
1973
1974 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1975         u8         bytes_committed[0x20];
1976
1977         u8         reserved_at_20[0x10];
1978         u8         wqe_index[0x10];
1979
1980         u8         reserved_at_40[0x10];
1981         u8         len[0x10];
1982
1983         u8         reserved_at_60[0x60];
1984
1985         u8         reserved_at_c0[0x5];
1986         u8         rdma[0x1];
1987         u8         write_read[0x1];
1988         u8         requestor[0x1];
1989         u8         qpn[0x18];
1990 };
1991
1992 struct mlx5_ifc_qp_events_bits {
1993         u8         reserved_at_0[0xa0];
1994
1995         u8         type[0x8];
1996         u8         reserved_at_a8[0x18];
1997
1998         u8         reserved_at_c0[0x8];
1999         u8         qpn_rqn_sqn[0x18];
2000 };
2001
2002 struct mlx5_ifc_dct_events_bits {
2003         u8         reserved_at_0[0xc0];
2004
2005         u8         reserved_at_c0[0x8];
2006         u8         dct_number[0x18];
2007 };
2008
2009 struct mlx5_ifc_comp_event_bits {
2010         u8         reserved_at_0[0xc0];
2011
2012         u8         reserved_at_c0[0x8];
2013         u8         cq_number[0x18];
2014 };
2015
2016 enum {
2017         MLX5_QPC_STATE_RST        = 0x0,
2018         MLX5_QPC_STATE_INIT       = 0x1,
2019         MLX5_QPC_STATE_RTR        = 0x2,
2020         MLX5_QPC_STATE_RTS        = 0x3,
2021         MLX5_QPC_STATE_SQER       = 0x4,
2022         MLX5_QPC_STATE_ERR        = 0x6,
2023         MLX5_QPC_STATE_SQD        = 0x7,
2024         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2025 };
2026
2027 enum {
2028         MLX5_QPC_ST_RC            = 0x0,
2029         MLX5_QPC_ST_UC            = 0x1,
2030         MLX5_QPC_ST_UD            = 0x2,
2031         MLX5_QPC_ST_XRC           = 0x3,
2032         MLX5_QPC_ST_DCI           = 0x5,
2033         MLX5_QPC_ST_QP0           = 0x7,
2034         MLX5_QPC_ST_QP1           = 0x8,
2035         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2036         MLX5_QPC_ST_REG_UMR       = 0xc,
2037 };
2038
2039 enum {
2040         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2041         MLX5_QPC_PM_STATE_REARM     = 0x1,
2042         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2043         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2044 };
2045
2046 enum {
2047         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2048 };
2049
2050 enum {
2051         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2052         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2053 };
2054
2055 enum {
2056         MLX5_QPC_MTU_256_BYTES        = 0x1,
2057         MLX5_QPC_MTU_512_BYTES        = 0x2,
2058         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2059         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2060         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2061         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2062 };
2063
2064 enum {
2065         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2066         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2067         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2068         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2069         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2070         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2071         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2072         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2073 };
2074
2075 enum {
2076         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2077         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2078         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2079 };
2080
2081 enum {
2082         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2083         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2084         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2085 };
2086
2087 struct mlx5_ifc_qpc_bits {
2088         u8         state[0x4];
2089         u8         lag_tx_port_affinity[0x4];
2090         u8         st[0x8];
2091         u8         reserved_at_10[0x3];
2092         u8         pm_state[0x2];
2093         u8         reserved_at_15[0x3];
2094         u8         offload_type[0x4];
2095         u8         end_padding_mode[0x2];
2096         u8         reserved_at_1e[0x2];
2097
2098         u8         wq_signature[0x1];
2099         u8         block_lb_mc[0x1];
2100         u8         atomic_like_write_en[0x1];
2101         u8         latency_sensitive[0x1];
2102         u8         reserved_at_24[0x1];
2103         u8         drain_sigerr[0x1];
2104         u8         reserved_at_26[0x2];
2105         u8         pd[0x18];
2106
2107         u8         mtu[0x3];
2108         u8         log_msg_max[0x5];
2109         u8         reserved_at_48[0x1];
2110         u8         log_rq_size[0x4];
2111         u8         log_rq_stride[0x3];
2112         u8         no_sq[0x1];
2113         u8         log_sq_size[0x4];
2114         u8         reserved_at_55[0x6];
2115         u8         rlky[0x1];
2116         u8         ulp_stateless_offload_mode[0x4];
2117
2118         u8         counter_set_id[0x8];
2119         u8         uar_page[0x18];
2120
2121         u8         reserved_at_80[0x8];
2122         u8         user_index[0x18];
2123
2124         u8         reserved_at_a0[0x3];
2125         u8         log_page_size[0x5];
2126         u8         remote_qpn[0x18];
2127
2128         struct mlx5_ifc_ads_bits primary_address_path;
2129
2130         struct mlx5_ifc_ads_bits secondary_address_path;
2131
2132         u8         log_ack_req_freq[0x4];
2133         u8         reserved_at_384[0x4];
2134         u8         log_sra_max[0x3];
2135         u8         reserved_at_38b[0x2];
2136         u8         retry_count[0x3];
2137         u8         rnr_retry[0x3];
2138         u8         reserved_at_393[0x1];
2139         u8         fre[0x1];
2140         u8         cur_rnr_retry[0x3];
2141         u8         cur_retry_count[0x3];
2142         u8         reserved_at_39b[0x5];
2143
2144         u8         reserved_at_3a0[0x20];
2145
2146         u8         reserved_at_3c0[0x8];
2147         u8         next_send_psn[0x18];
2148
2149         u8         reserved_at_3e0[0x8];
2150         u8         cqn_snd[0x18];
2151
2152         u8         reserved_at_400[0x8];
2153         u8         deth_sqpn[0x18];
2154
2155         u8         reserved_at_420[0x20];
2156
2157         u8         reserved_at_440[0x8];
2158         u8         last_acked_psn[0x18];
2159
2160         u8         reserved_at_460[0x8];
2161         u8         ssn[0x18];
2162
2163         u8         reserved_at_480[0x8];
2164         u8         log_rra_max[0x3];
2165         u8         reserved_at_48b[0x1];
2166         u8         atomic_mode[0x4];
2167         u8         rre[0x1];
2168         u8         rwe[0x1];
2169         u8         rae[0x1];
2170         u8         reserved_at_493[0x1];
2171         u8         page_offset[0x6];
2172         u8         reserved_at_49a[0x3];
2173         u8         cd_slave_receive[0x1];
2174         u8         cd_slave_send[0x1];
2175         u8         cd_master[0x1];
2176
2177         u8         reserved_at_4a0[0x3];
2178         u8         min_rnr_nak[0x5];
2179         u8         next_rcv_psn[0x18];
2180
2181         u8         reserved_at_4c0[0x8];
2182         u8         xrcd[0x18];
2183
2184         u8         reserved_at_4e0[0x8];
2185         u8         cqn_rcv[0x18];
2186
2187         u8         dbr_addr[0x40];
2188
2189         u8         q_key[0x20];
2190
2191         u8         reserved_at_560[0x5];
2192         u8         rq_type[0x3];
2193         u8         srqn_rmpn_xrqn[0x18];
2194
2195         u8         reserved_at_580[0x8];
2196         u8         rmsn[0x18];
2197
2198         u8         hw_sq_wqebb_counter[0x10];
2199         u8         sw_sq_wqebb_counter[0x10];
2200
2201         u8         hw_rq_counter[0x20];
2202
2203         u8         sw_rq_counter[0x20];
2204
2205         u8         reserved_at_600[0x20];
2206
2207         u8         reserved_at_620[0xf];
2208         u8         cgs[0x1];
2209         u8         cs_req[0x8];
2210         u8         cs_res[0x8];
2211
2212         u8         dc_access_key[0x40];
2213
2214         u8         reserved_at_680[0xc0];
2215 };
2216
2217 struct mlx5_ifc_roce_addr_layout_bits {
2218         u8         source_l3_address[16][0x8];
2219
2220         u8         reserved_at_80[0x3];
2221         u8         vlan_valid[0x1];
2222         u8         vlan_id[0xc];
2223         u8         source_mac_47_32[0x10];
2224
2225         u8         source_mac_31_0[0x20];
2226
2227         u8         reserved_at_c0[0x14];
2228         u8         roce_l3_type[0x4];
2229         u8         roce_version[0x8];
2230
2231         u8         reserved_at_e0[0x20];
2232 };
2233
2234 union mlx5_ifc_hca_cap_union_bits {
2235         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2236         struct mlx5_ifc_odp_cap_bits odp_cap;
2237         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2238         struct mlx5_ifc_roce_cap_bits roce_cap;
2239         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2240         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2241         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2242         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2243         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2244         struct mlx5_ifc_qos_cap_bits qos_cap;
2245         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2246         u8         reserved_at_0[0x8000];
2247 };
2248
2249 enum {
2250         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2251         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2252         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2253         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2254         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2255         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2256         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2257 };
2258
2259 struct mlx5_ifc_flow_context_bits {
2260         u8         reserved_at_0[0x20];
2261
2262         u8         group_id[0x20];
2263
2264         u8         reserved_at_40[0x8];
2265         u8         flow_tag[0x18];
2266
2267         u8         reserved_at_60[0x10];
2268         u8         action[0x10];
2269
2270         u8         reserved_at_80[0x8];
2271         u8         destination_list_size[0x18];
2272
2273         u8         reserved_at_a0[0x8];
2274         u8         flow_counter_list_size[0x18];
2275
2276         u8         encap_id[0x20];
2277
2278         u8         modify_header_id[0x20];
2279
2280         u8         reserved_at_100[0x100];
2281
2282         struct mlx5_ifc_fte_match_param_bits match_value;
2283
2284         u8         reserved_at_1200[0x600];
2285
2286         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2287 };
2288
2289 enum {
2290         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2291         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2292 };
2293
2294 struct mlx5_ifc_xrc_srqc_bits {
2295         u8         state[0x4];
2296         u8         log_xrc_srq_size[0x4];
2297         u8         reserved_at_8[0x18];
2298
2299         u8         wq_signature[0x1];
2300         u8         cont_srq[0x1];
2301         u8         reserved_at_22[0x1];
2302         u8         rlky[0x1];
2303         u8         basic_cyclic_rcv_wqe[0x1];
2304         u8         log_rq_stride[0x3];
2305         u8         xrcd[0x18];
2306
2307         u8         page_offset[0x6];
2308         u8         reserved_at_46[0x2];
2309         u8         cqn[0x18];
2310
2311         u8         reserved_at_60[0x20];
2312
2313         u8         user_index_equal_xrc_srqn[0x1];
2314         u8         reserved_at_81[0x1];
2315         u8         log_page_size[0x6];
2316         u8         user_index[0x18];
2317
2318         u8         reserved_at_a0[0x20];
2319
2320         u8         reserved_at_c0[0x8];
2321         u8         pd[0x18];
2322
2323         u8         lwm[0x10];
2324         u8         wqe_cnt[0x10];
2325
2326         u8         reserved_at_100[0x40];
2327
2328         u8         db_record_addr_h[0x20];
2329
2330         u8         db_record_addr_l[0x1e];
2331         u8         reserved_at_17e[0x2];
2332
2333         u8         reserved_at_180[0x80];
2334 };
2335
2336 struct mlx5_ifc_traffic_counter_bits {
2337         u8         packets[0x40];
2338
2339         u8         octets[0x40];
2340 };
2341
2342 struct mlx5_ifc_tisc_bits {
2343         u8         strict_lag_tx_port_affinity[0x1];
2344         u8         reserved_at_1[0x3];
2345         u8         lag_tx_port_affinity[0x04];
2346
2347         u8         reserved_at_8[0x4];
2348         u8         prio[0x4];
2349         u8         reserved_at_10[0x10];
2350
2351         u8         reserved_at_20[0x100];
2352
2353         u8         reserved_at_120[0x8];
2354         u8         transport_domain[0x18];
2355
2356         u8         reserved_at_140[0x8];
2357         u8         underlay_qpn[0x18];
2358         u8         reserved_at_160[0x3a0];
2359 };
2360
2361 enum {
2362         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2363         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2364 };
2365
2366 enum {
2367         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2368         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2369 };
2370
2371 enum {
2372         MLX5_RX_HASH_FN_NONE           = 0x0,
2373         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2374         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2375 };
2376
2377 enum {
2378         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2379         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2380 };
2381
2382 struct mlx5_ifc_tirc_bits {
2383         u8         reserved_at_0[0x20];
2384
2385         u8         disp_type[0x4];
2386         u8         reserved_at_24[0x1c];
2387
2388         u8         reserved_at_40[0x40];
2389
2390         u8         reserved_at_80[0x4];
2391         u8         lro_timeout_period_usecs[0x10];
2392         u8         lro_enable_mask[0x4];
2393         u8         lro_max_ip_payload_size[0x8];
2394
2395         u8         reserved_at_a0[0x40];
2396
2397         u8         reserved_at_e0[0x8];
2398         u8         inline_rqn[0x18];
2399
2400         u8         rx_hash_symmetric[0x1];
2401         u8         reserved_at_101[0x1];
2402         u8         tunneled_offload_en[0x1];
2403         u8         reserved_at_103[0x5];
2404         u8         indirect_table[0x18];
2405
2406         u8         rx_hash_fn[0x4];
2407         u8         reserved_at_124[0x2];
2408         u8         self_lb_block[0x2];
2409         u8         transport_domain[0x18];
2410
2411         u8         rx_hash_toeplitz_key[10][0x20];
2412
2413         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2414
2415         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2416
2417         u8         reserved_at_2c0[0x4c0];
2418 };
2419
2420 enum {
2421         MLX5_SRQC_STATE_GOOD   = 0x0,
2422         MLX5_SRQC_STATE_ERROR  = 0x1,
2423 };
2424
2425 struct mlx5_ifc_srqc_bits {
2426         u8         state[0x4];
2427         u8         log_srq_size[0x4];
2428         u8         reserved_at_8[0x18];
2429
2430         u8         wq_signature[0x1];
2431         u8         cont_srq[0x1];
2432         u8         reserved_at_22[0x1];
2433         u8         rlky[0x1];
2434         u8         reserved_at_24[0x1];
2435         u8         log_rq_stride[0x3];
2436         u8         xrcd[0x18];
2437
2438         u8         page_offset[0x6];
2439         u8         reserved_at_46[0x2];
2440         u8         cqn[0x18];
2441
2442         u8         reserved_at_60[0x20];
2443
2444         u8         reserved_at_80[0x2];
2445         u8         log_page_size[0x6];
2446         u8         reserved_at_88[0x18];
2447
2448         u8         reserved_at_a0[0x20];
2449
2450         u8         reserved_at_c0[0x8];
2451         u8         pd[0x18];
2452
2453         u8         lwm[0x10];
2454         u8         wqe_cnt[0x10];
2455
2456         u8         reserved_at_100[0x40];
2457
2458         u8         dbr_addr[0x40];
2459
2460         u8         reserved_at_180[0x80];
2461 };
2462
2463 enum {
2464         MLX5_SQC_STATE_RST  = 0x0,
2465         MLX5_SQC_STATE_RDY  = 0x1,
2466         MLX5_SQC_STATE_ERR  = 0x3,
2467 };
2468
2469 struct mlx5_ifc_sqc_bits {
2470         u8         rlky[0x1];
2471         u8         cd_master[0x1];
2472         u8         fre[0x1];
2473         u8         flush_in_error_en[0x1];
2474         u8         allow_multi_pkt_send_wqe[0x1];
2475         u8         min_wqe_inline_mode[0x3];
2476         u8         state[0x4];
2477         u8         reg_umr[0x1];
2478         u8         allow_swp[0x1];
2479         u8         reserved_at_e[0x12];
2480
2481         u8         reserved_at_20[0x8];
2482         u8         user_index[0x18];
2483
2484         u8         reserved_at_40[0x8];
2485         u8         cqn[0x18];
2486
2487         u8         reserved_at_60[0x90];
2488
2489         u8         packet_pacing_rate_limit_index[0x10];
2490         u8         tis_lst_sz[0x10];
2491         u8         reserved_at_110[0x10];
2492
2493         u8         reserved_at_120[0x40];
2494
2495         u8         reserved_at_160[0x8];
2496         u8         tis_num_0[0x18];
2497
2498         struct mlx5_ifc_wq_bits wq;
2499 };
2500
2501 enum {
2502         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2503         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2504         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2505         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2506 };
2507
2508 struct mlx5_ifc_scheduling_context_bits {
2509         u8         element_type[0x8];
2510         u8         reserved_at_8[0x18];
2511
2512         u8         element_attributes[0x20];
2513
2514         u8         parent_element_id[0x20];
2515
2516         u8         reserved_at_60[0x40];
2517
2518         u8         bw_share[0x20];
2519
2520         u8         max_average_bw[0x20];
2521
2522         u8         reserved_at_e0[0x120];
2523 };
2524
2525 struct mlx5_ifc_rqtc_bits {
2526         u8         reserved_at_0[0xa0];
2527
2528         u8         reserved_at_a0[0x10];
2529         u8         rqt_max_size[0x10];
2530
2531         u8         reserved_at_c0[0x10];
2532         u8         rqt_actual_size[0x10];
2533
2534         u8         reserved_at_e0[0x6a0];
2535
2536         struct mlx5_ifc_rq_num_bits rq_num[0];
2537 };
2538
2539 enum {
2540         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2541         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2542 };
2543
2544 enum {
2545         MLX5_RQC_STATE_RST  = 0x0,
2546         MLX5_RQC_STATE_RDY  = 0x1,
2547         MLX5_RQC_STATE_ERR  = 0x3,
2548 };
2549
2550 struct mlx5_ifc_rqc_bits {
2551         u8         rlky[0x1];
2552         u8         delay_drop_en[0x1];
2553         u8         scatter_fcs[0x1];
2554         u8         vsd[0x1];
2555         u8         mem_rq_type[0x4];
2556         u8         state[0x4];
2557         u8         reserved_at_c[0x1];
2558         u8         flush_in_error_en[0x1];
2559         u8         reserved_at_e[0x12];
2560
2561         u8         reserved_at_20[0x8];
2562         u8         user_index[0x18];
2563
2564         u8         reserved_at_40[0x8];
2565         u8         cqn[0x18];
2566
2567         u8         counter_set_id[0x8];
2568         u8         reserved_at_68[0x18];
2569
2570         u8         reserved_at_80[0x8];
2571         u8         rmpn[0x18];
2572
2573         u8         reserved_at_a0[0xe0];
2574
2575         struct mlx5_ifc_wq_bits wq;
2576 };
2577
2578 enum {
2579         MLX5_RMPC_STATE_RDY  = 0x1,
2580         MLX5_RMPC_STATE_ERR  = 0x3,
2581 };
2582
2583 struct mlx5_ifc_rmpc_bits {
2584         u8         reserved_at_0[0x8];
2585         u8         state[0x4];
2586         u8         reserved_at_c[0x14];
2587
2588         u8         basic_cyclic_rcv_wqe[0x1];
2589         u8         reserved_at_21[0x1f];
2590
2591         u8         reserved_at_40[0x140];
2592
2593         struct mlx5_ifc_wq_bits wq;
2594 };
2595
2596 struct mlx5_ifc_nic_vport_context_bits {
2597         u8         reserved_at_0[0x5];
2598         u8         min_wqe_inline_mode[0x3];
2599         u8         reserved_at_8[0x15];
2600         u8         disable_mc_local_lb[0x1];
2601         u8         disable_uc_local_lb[0x1];
2602         u8         roce_en[0x1];
2603
2604         u8         arm_change_event[0x1];
2605         u8         reserved_at_21[0x1a];
2606         u8         event_on_mtu[0x1];
2607         u8         event_on_promisc_change[0x1];
2608         u8         event_on_vlan_change[0x1];
2609         u8         event_on_mc_address_change[0x1];
2610         u8         event_on_uc_address_change[0x1];
2611
2612         u8         reserved_at_40[0xf0];
2613
2614         u8         mtu[0x10];
2615
2616         u8         system_image_guid[0x40];
2617         u8         port_guid[0x40];
2618         u8         node_guid[0x40];
2619
2620         u8         reserved_at_200[0x140];
2621         u8         qkey_violation_counter[0x10];
2622         u8         reserved_at_350[0x430];
2623
2624         u8         promisc_uc[0x1];
2625         u8         promisc_mc[0x1];
2626         u8         promisc_all[0x1];
2627         u8         reserved_at_783[0x2];
2628         u8         allowed_list_type[0x3];
2629         u8         reserved_at_788[0xc];
2630         u8         allowed_list_size[0xc];
2631
2632         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2633
2634         u8         reserved_at_7e0[0x20];
2635
2636         u8         current_uc_mac_address[0][0x40];
2637 };
2638
2639 enum {
2640         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2641         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2642         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2643         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2644 };
2645
2646 struct mlx5_ifc_mkc_bits {
2647         u8         reserved_at_0[0x1];
2648         u8         free[0x1];
2649         u8         reserved_at_2[0xd];
2650         u8         small_fence_on_rdma_read_response[0x1];
2651         u8         umr_en[0x1];
2652         u8         a[0x1];
2653         u8         rw[0x1];
2654         u8         rr[0x1];
2655         u8         lw[0x1];
2656         u8         lr[0x1];
2657         u8         access_mode[0x2];
2658         u8         reserved_at_18[0x8];
2659
2660         u8         qpn[0x18];
2661         u8         mkey_7_0[0x8];
2662
2663         u8         reserved_at_40[0x20];
2664
2665         u8         length64[0x1];
2666         u8         bsf_en[0x1];
2667         u8         sync_umr[0x1];
2668         u8         reserved_at_63[0x2];
2669         u8         expected_sigerr_count[0x1];
2670         u8         reserved_at_66[0x1];
2671         u8         en_rinval[0x1];
2672         u8         pd[0x18];
2673
2674         u8         start_addr[0x40];
2675
2676         u8         len[0x40];
2677
2678         u8         bsf_octword_size[0x20];
2679
2680         u8         reserved_at_120[0x80];
2681
2682         u8         translations_octword_size[0x20];
2683
2684         u8         reserved_at_1c0[0x1b];
2685         u8         log_page_size[0x5];
2686
2687         u8         reserved_at_1e0[0x20];
2688 };
2689
2690 struct mlx5_ifc_pkey_bits {
2691         u8         reserved_at_0[0x10];
2692         u8         pkey[0x10];
2693 };
2694
2695 struct mlx5_ifc_array128_auto_bits {
2696         u8         array128_auto[16][0x8];
2697 };
2698
2699 struct mlx5_ifc_hca_vport_context_bits {
2700         u8         field_select[0x20];
2701
2702         u8         reserved_at_20[0xe0];
2703
2704         u8         sm_virt_aware[0x1];
2705         u8         has_smi[0x1];
2706         u8         has_raw[0x1];
2707         u8         grh_required[0x1];
2708         u8         reserved_at_104[0xc];
2709         u8         port_physical_state[0x4];
2710         u8         vport_state_policy[0x4];
2711         u8         port_state[0x4];
2712         u8         vport_state[0x4];
2713
2714         u8         reserved_at_120[0x20];
2715
2716         u8         system_image_guid[0x40];
2717
2718         u8         port_guid[0x40];
2719
2720         u8         node_guid[0x40];
2721
2722         u8         cap_mask1[0x20];
2723
2724         u8         cap_mask1_field_select[0x20];
2725
2726         u8         cap_mask2[0x20];
2727
2728         u8         cap_mask2_field_select[0x20];
2729
2730         u8         reserved_at_280[0x80];
2731
2732         u8         lid[0x10];
2733         u8         reserved_at_310[0x4];
2734         u8         init_type_reply[0x4];
2735         u8         lmc[0x3];
2736         u8         subnet_timeout[0x5];
2737
2738         u8         sm_lid[0x10];
2739         u8         sm_sl[0x4];
2740         u8         reserved_at_334[0xc];
2741
2742         u8         qkey_violation_counter[0x10];
2743         u8         pkey_violation_counter[0x10];
2744
2745         u8         reserved_at_360[0xca0];
2746 };
2747
2748 struct mlx5_ifc_esw_vport_context_bits {
2749         u8         reserved_at_0[0x3];
2750         u8         vport_svlan_strip[0x1];
2751         u8         vport_cvlan_strip[0x1];
2752         u8         vport_svlan_insert[0x1];
2753         u8         vport_cvlan_insert[0x2];
2754         u8         reserved_at_8[0x18];
2755
2756         u8         reserved_at_20[0x20];
2757
2758         u8         svlan_cfi[0x1];
2759         u8         svlan_pcp[0x3];
2760         u8         svlan_id[0xc];
2761         u8         cvlan_cfi[0x1];
2762         u8         cvlan_pcp[0x3];
2763         u8         cvlan_id[0xc];
2764
2765         u8         reserved_at_60[0x7a0];
2766 };
2767
2768 enum {
2769         MLX5_EQC_STATUS_OK                = 0x0,
2770         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2771 };
2772
2773 enum {
2774         MLX5_EQC_ST_ARMED  = 0x9,
2775         MLX5_EQC_ST_FIRED  = 0xa,
2776 };
2777
2778 struct mlx5_ifc_eqc_bits {
2779         u8         status[0x4];
2780         u8         reserved_at_4[0x9];
2781         u8         ec[0x1];
2782         u8         oi[0x1];
2783         u8         reserved_at_f[0x5];
2784         u8         st[0x4];
2785         u8         reserved_at_18[0x8];
2786
2787         u8         reserved_at_20[0x20];
2788
2789         u8         reserved_at_40[0x14];
2790         u8         page_offset[0x6];
2791         u8         reserved_at_5a[0x6];
2792
2793         u8         reserved_at_60[0x3];
2794         u8         log_eq_size[0x5];
2795         u8         uar_page[0x18];
2796
2797         u8         reserved_at_80[0x20];
2798
2799         u8         reserved_at_a0[0x18];
2800         u8         intr[0x8];
2801
2802         u8         reserved_at_c0[0x3];
2803         u8         log_page_size[0x5];
2804         u8         reserved_at_c8[0x18];
2805
2806         u8         reserved_at_e0[0x60];
2807
2808         u8         reserved_at_140[0x8];
2809         u8         consumer_counter[0x18];
2810
2811         u8         reserved_at_160[0x8];
2812         u8         producer_counter[0x18];
2813
2814         u8         reserved_at_180[0x80];
2815 };
2816
2817 enum {
2818         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2819         MLX5_DCTC_STATE_DRAINING  = 0x1,
2820         MLX5_DCTC_STATE_DRAINED   = 0x2,
2821 };
2822
2823 enum {
2824         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2825         MLX5_DCTC_CS_RES_NA         = 0x1,
2826         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2827 };
2828
2829 enum {
2830         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2831         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2832         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2833         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2834         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2835 };
2836
2837 struct mlx5_ifc_dctc_bits {
2838         u8         reserved_at_0[0x4];
2839         u8         state[0x4];
2840         u8         reserved_at_8[0x18];
2841
2842         u8         reserved_at_20[0x8];
2843         u8         user_index[0x18];
2844
2845         u8         reserved_at_40[0x8];
2846         u8         cqn[0x18];
2847
2848         u8         counter_set_id[0x8];
2849         u8         atomic_mode[0x4];
2850         u8         rre[0x1];
2851         u8         rwe[0x1];
2852         u8         rae[0x1];
2853         u8         atomic_like_write_en[0x1];
2854         u8         latency_sensitive[0x1];
2855         u8         rlky[0x1];
2856         u8         free_ar[0x1];
2857         u8         reserved_at_73[0xd];
2858
2859         u8         reserved_at_80[0x8];
2860         u8         cs_res[0x8];
2861         u8         reserved_at_90[0x3];
2862         u8         min_rnr_nak[0x5];
2863         u8         reserved_at_98[0x8];
2864
2865         u8         reserved_at_a0[0x8];
2866         u8         srqn_xrqn[0x18];
2867
2868         u8         reserved_at_c0[0x8];
2869         u8         pd[0x18];
2870
2871         u8         tclass[0x8];
2872         u8         reserved_at_e8[0x4];
2873         u8         flow_label[0x14];
2874
2875         u8         dc_access_key[0x40];
2876
2877         u8         reserved_at_140[0x5];
2878         u8         mtu[0x3];
2879         u8         port[0x8];
2880         u8         pkey_index[0x10];
2881
2882         u8         reserved_at_160[0x8];
2883         u8         my_addr_index[0x8];
2884         u8         reserved_at_170[0x8];
2885         u8         hop_limit[0x8];
2886
2887         u8         dc_access_key_violation_count[0x20];
2888
2889         u8         reserved_at_1a0[0x14];
2890         u8         dei_cfi[0x1];
2891         u8         eth_prio[0x3];
2892         u8         ecn[0x2];
2893         u8         dscp[0x6];
2894
2895         u8         reserved_at_1c0[0x40];
2896 };
2897
2898 enum {
2899         MLX5_CQC_STATUS_OK             = 0x0,
2900         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2901         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2902 };
2903
2904 enum {
2905         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2906         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2907 };
2908
2909 enum {
2910         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2911         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2912         MLX5_CQC_ST_FIRED                                 = 0xa,
2913 };
2914
2915 enum {
2916         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2917         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2918         MLX5_CQ_PERIOD_NUM_MODES
2919 };
2920
2921 struct mlx5_ifc_cqc_bits {
2922         u8         status[0x4];
2923         u8         reserved_at_4[0x4];
2924         u8         cqe_sz[0x3];
2925         u8         cc[0x1];
2926         u8         reserved_at_c[0x1];
2927         u8         scqe_break_moderation_en[0x1];
2928         u8         oi[0x1];
2929         u8         cq_period_mode[0x2];
2930         u8         cqe_comp_en[0x1];
2931         u8         mini_cqe_res_format[0x2];
2932         u8         st[0x4];
2933         u8         reserved_at_18[0x8];
2934
2935         u8         reserved_at_20[0x20];
2936
2937         u8         reserved_at_40[0x14];
2938         u8         page_offset[0x6];
2939         u8         reserved_at_5a[0x6];
2940
2941         u8         reserved_at_60[0x3];
2942         u8         log_cq_size[0x5];
2943         u8         uar_page[0x18];
2944
2945         u8         reserved_at_80[0x4];
2946         u8         cq_period[0xc];
2947         u8         cq_max_count[0x10];
2948
2949         u8         reserved_at_a0[0x18];
2950         u8         c_eqn[0x8];
2951
2952         u8         reserved_at_c0[0x3];
2953         u8         log_page_size[0x5];
2954         u8         reserved_at_c8[0x18];
2955
2956         u8         reserved_at_e0[0x20];
2957
2958         u8         reserved_at_100[0x8];
2959         u8         last_notified_index[0x18];
2960
2961         u8         reserved_at_120[0x8];
2962         u8         last_solicit_index[0x18];
2963
2964         u8         reserved_at_140[0x8];
2965         u8         consumer_counter[0x18];
2966
2967         u8         reserved_at_160[0x8];
2968         u8         producer_counter[0x18];
2969
2970         u8         reserved_at_180[0x40];
2971
2972         u8         dbr_addr[0x40];
2973 };
2974
2975 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2976         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2977         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2978         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2979         u8         reserved_at_0[0x800];
2980 };
2981
2982 struct mlx5_ifc_query_adapter_param_block_bits {
2983         u8         reserved_at_0[0xc0];
2984
2985         u8         reserved_at_c0[0x8];
2986         u8         ieee_vendor_id[0x18];
2987
2988         u8         reserved_at_e0[0x10];
2989         u8         vsd_vendor_id[0x10];
2990
2991         u8         vsd[208][0x8];
2992
2993         u8         vsd_contd_psid[16][0x8];
2994 };
2995
2996 enum {
2997         MLX5_XRQC_STATE_GOOD   = 0x0,
2998         MLX5_XRQC_STATE_ERROR  = 0x1,
2999 };
3000
3001 enum {
3002         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3003         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3004 };
3005
3006 enum {
3007         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3008 };
3009
3010 struct mlx5_ifc_tag_matching_topology_context_bits {
3011         u8         log_matching_list_sz[0x4];
3012         u8         reserved_at_4[0xc];
3013         u8         append_next_index[0x10];
3014
3015         u8         sw_phase_cnt[0x10];
3016         u8         hw_phase_cnt[0x10];
3017
3018         u8         reserved_at_40[0x40];
3019 };
3020
3021 struct mlx5_ifc_xrqc_bits {
3022         u8         state[0x4];
3023         u8         rlkey[0x1];
3024         u8         reserved_at_5[0xf];
3025         u8         topology[0x4];
3026         u8         reserved_at_18[0x4];
3027         u8         offload[0x4];
3028
3029         u8         reserved_at_20[0x8];
3030         u8         user_index[0x18];
3031
3032         u8         reserved_at_40[0x8];
3033         u8         cqn[0x18];
3034
3035         u8         reserved_at_60[0xa0];
3036
3037         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3038
3039         u8         reserved_at_180[0x280];
3040
3041         struct mlx5_ifc_wq_bits wq;
3042 };
3043
3044 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3045         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3046         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3047         u8         reserved_at_0[0x20];
3048 };
3049
3050 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3051         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3052         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3053         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3054         u8         reserved_at_0[0x20];
3055 };
3056
3057 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3058         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3059         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3060         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3061         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3062         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3063         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3064         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3065         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3066         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3067         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3068         u8         reserved_at_0[0x7c0];
3069 };
3070
3071 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3072         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3073         u8         reserved_at_0[0x7c0];
3074 };
3075
3076 union mlx5_ifc_event_auto_bits {
3077         struct mlx5_ifc_comp_event_bits comp_event;
3078         struct mlx5_ifc_dct_events_bits dct_events;
3079         struct mlx5_ifc_qp_events_bits qp_events;
3080         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3081         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3082         struct mlx5_ifc_cq_error_bits cq_error;
3083         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3084         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3085         struct mlx5_ifc_gpio_event_bits gpio_event;
3086         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3087         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3088         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3089         u8         reserved_at_0[0xe0];
3090 };
3091
3092 struct mlx5_ifc_health_buffer_bits {
3093         u8         reserved_at_0[0x100];
3094
3095         u8         assert_existptr[0x20];
3096
3097         u8         assert_callra[0x20];
3098
3099         u8         reserved_at_140[0x40];
3100
3101         u8         fw_version[0x20];
3102
3103         u8         hw_id[0x20];
3104
3105         u8         reserved_at_1c0[0x20];
3106
3107         u8         irisc_index[0x8];
3108         u8         synd[0x8];
3109         u8         ext_synd[0x10];
3110 };
3111
3112 struct mlx5_ifc_register_loopback_control_bits {
3113         u8         no_lb[0x1];
3114         u8         reserved_at_1[0x7];
3115         u8         port[0x8];
3116         u8         reserved_at_10[0x10];
3117
3118         u8         reserved_at_20[0x60];
3119 };
3120
3121 struct mlx5_ifc_vport_tc_element_bits {
3122         u8         traffic_class[0x4];
3123         u8         reserved_at_4[0xc];
3124         u8         vport_number[0x10];
3125 };
3126
3127 struct mlx5_ifc_vport_element_bits {
3128         u8         reserved_at_0[0x10];
3129         u8         vport_number[0x10];
3130 };
3131
3132 enum {
3133         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3134         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3135         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3136 };
3137
3138 struct mlx5_ifc_tsar_element_bits {
3139         u8         reserved_at_0[0x8];
3140         u8         tsar_type[0x8];
3141         u8         reserved_at_10[0x10];
3142 };
3143
3144 enum {
3145         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3146         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3147 };
3148
3149 struct mlx5_ifc_teardown_hca_out_bits {
3150         u8         status[0x8];
3151         u8         reserved_at_8[0x18];
3152
3153         u8         syndrome[0x20];
3154
3155         u8         reserved_at_40[0x3f];
3156
3157         u8         force_state[0x1];
3158 };
3159
3160 enum {
3161         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3162         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3163 };
3164
3165 struct mlx5_ifc_teardown_hca_in_bits {
3166         u8         opcode[0x10];
3167         u8         reserved_at_10[0x10];
3168
3169         u8         reserved_at_20[0x10];
3170         u8         op_mod[0x10];
3171
3172         u8         reserved_at_40[0x10];
3173         u8         profile[0x10];
3174
3175         u8         reserved_at_60[0x20];
3176 };
3177
3178 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3179         u8         status[0x8];
3180         u8         reserved_at_8[0x18];
3181
3182         u8         syndrome[0x20];
3183
3184         u8         reserved_at_40[0x40];
3185 };
3186
3187 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3188         u8         opcode[0x10];
3189         u8         reserved_at_10[0x10];
3190
3191         u8         reserved_at_20[0x10];
3192         u8         op_mod[0x10];
3193
3194         u8         reserved_at_40[0x8];
3195         u8         qpn[0x18];
3196
3197         u8         reserved_at_60[0x20];
3198
3199         u8         opt_param_mask[0x20];
3200
3201         u8         reserved_at_a0[0x20];
3202
3203         struct mlx5_ifc_qpc_bits qpc;
3204
3205         u8         reserved_at_800[0x80];
3206 };
3207
3208 struct mlx5_ifc_sqd2rts_qp_out_bits {
3209         u8         status[0x8];
3210         u8         reserved_at_8[0x18];
3211
3212         u8         syndrome[0x20];
3213
3214         u8         reserved_at_40[0x40];
3215 };
3216
3217 struct mlx5_ifc_sqd2rts_qp_in_bits {
3218         u8         opcode[0x10];
3219         u8         reserved_at_10[0x10];
3220
3221         u8         reserved_at_20[0x10];
3222         u8         op_mod[0x10];
3223
3224         u8         reserved_at_40[0x8];
3225         u8         qpn[0x18];
3226
3227         u8         reserved_at_60[0x20];
3228
3229         u8         opt_param_mask[0x20];
3230
3231         u8         reserved_at_a0[0x20];
3232
3233         struct mlx5_ifc_qpc_bits qpc;
3234
3235         u8         reserved_at_800[0x80];
3236 };
3237
3238 struct mlx5_ifc_set_roce_address_out_bits {
3239         u8         status[0x8];
3240         u8         reserved_at_8[0x18];
3241
3242         u8         syndrome[0x20];
3243
3244         u8         reserved_at_40[0x40];
3245 };
3246
3247 struct mlx5_ifc_set_roce_address_in_bits {
3248         u8         opcode[0x10];
3249         u8         reserved_at_10[0x10];
3250
3251         u8         reserved_at_20[0x10];
3252         u8         op_mod[0x10];
3253
3254         u8         roce_address_index[0x10];
3255         u8         reserved_at_50[0x10];
3256
3257         u8         reserved_at_60[0x20];
3258
3259         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3260 };
3261
3262 struct mlx5_ifc_set_mad_demux_out_bits {
3263         u8         status[0x8];
3264         u8         reserved_at_8[0x18];
3265
3266         u8         syndrome[0x20];
3267
3268         u8         reserved_at_40[0x40];
3269 };
3270
3271 enum {
3272         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3273         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3274 };
3275
3276 struct mlx5_ifc_set_mad_demux_in_bits {
3277         u8         opcode[0x10];
3278         u8         reserved_at_10[0x10];
3279
3280         u8         reserved_at_20[0x10];
3281         u8         op_mod[0x10];
3282
3283         u8         reserved_at_40[0x20];
3284
3285         u8         reserved_at_60[0x6];
3286         u8         demux_mode[0x2];
3287         u8         reserved_at_68[0x18];
3288 };
3289
3290 struct mlx5_ifc_set_l2_table_entry_out_bits {
3291         u8         status[0x8];
3292         u8         reserved_at_8[0x18];
3293
3294         u8         syndrome[0x20];
3295
3296         u8         reserved_at_40[0x40];
3297 };
3298
3299 struct mlx5_ifc_set_l2_table_entry_in_bits {
3300         u8         opcode[0x10];
3301         u8         reserved_at_10[0x10];
3302
3303         u8         reserved_at_20[0x10];
3304         u8         op_mod[0x10];
3305
3306         u8         reserved_at_40[0x60];
3307
3308         u8         reserved_at_a0[0x8];
3309         u8         table_index[0x18];
3310
3311         u8         reserved_at_c0[0x20];
3312
3313         u8         reserved_at_e0[0x13];
3314         u8         vlan_valid[0x1];
3315         u8         vlan[0xc];
3316
3317         struct mlx5_ifc_mac_address_layout_bits mac_address;
3318
3319         u8         reserved_at_140[0xc0];
3320 };
3321
3322 struct mlx5_ifc_set_issi_out_bits {
3323         u8         status[0x8];
3324         u8         reserved_at_8[0x18];
3325
3326         u8         syndrome[0x20];
3327
3328         u8         reserved_at_40[0x40];
3329 };
3330
3331 struct mlx5_ifc_set_issi_in_bits {
3332         u8         opcode[0x10];
3333         u8         reserved_at_10[0x10];
3334
3335         u8         reserved_at_20[0x10];
3336         u8         op_mod[0x10];
3337
3338         u8         reserved_at_40[0x10];
3339         u8         current_issi[0x10];
3340
3341         u8         reserved_at_60[0x20];
3342 };
3343
3344 struct mlx5_ifc_set_hca_cap_out_bits {
3345         u8         status[0x8];
3346         u8         reserved_at_8[0x18];
3347
3348         u8         syndrome[0x20];
3349
3350         u8         reserved_at_40[0x40];
3351 };
3352
3353 struct mlx5_ifc_set_hca_cap_in_bits {
3354         u8         opcode[0x10];
3355         u8         reserved_at_10[0x10];
3356
3357         u8         reserved_at_20[0x10];
3358         u8         op_mod[0x10];
3359
3360         u8         reserved_at_40[0x40];
3361
3362         union mlx5_ifc_hca_cap_union_bits capability;
3363 };
3364
3365 enum {
3366         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3367         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3368         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3369         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3370 };
3371
3372 struct mlx5_ifc_set_fte_out_bits {
3373         u8         status[0x8];
3374         u8         reserved_at_8[0x18];
3375
3376         u8         syndrome[0x20];
3377
3378         u8         reserved_at_40[0x40];
3379 };
3380
3381 struct mlx5_ifc_set_fte_in_bits {
3382         u8         opcode[0x10];
3383         u8         reserved_at_10[0x10];
3384
3385         u8         reserved_at_20[0x10];
3386         u8         op_mod[0x10];
3387
3388         u8         other_vport[0x1];
3389         u8         reserved_at_41[0xf];
3390         u8         vport_number[0x10];
3391
3392         u8         reserved_at_60[0x20];
3393
3394         u8         table_type[0x8];
3395         u8         reserved_at_88[0x18];
3396
3397         u8         reserved_at_a0[0x8];
3398         u8         table_id[0x18];
3399
3400         u8         reserved_at_c0[0x18];
3401         u8         modify_enable_mask[0x8];
3402
3403         u8         reserved_at_e0[0x20];
3404
3405         u8         flow_index[0x20];
3406
3407         u8         reserved_at_120[0xe0];
3408
3409         struct mlx5_ifc_flow_context_bits flow_context;
3410 };
3411
3412 struct mlx5_ifc_rts2rts_qp_out_bits {
3413         u8         status[0x8];
3414         u8         reserved_at_8[0x18];
3415
3416         u8         syndrome[0x20];
3417
3418         u8         reserved_at_40[0x40];
3419 };
3420
3421 struct mlx5_ifc_rts2rts_qp_in_bits {
3422         u8         opcode[0x10];
3423         u8         reserved_at_10[0x10];
3424
3425         u8         reserved_at_20[0x10];
3426         u8         op_mod[0x10];
3427
3428         u8         reserved_at_40[0x8];
3429         u8         qpn[0x18];
3430
3431         u8         reserved_at_60[0x20];
3432
3433         u8         opt_param_mask[0x20];
3434
3435         u8         reserved_at_a0[0x20];
3436
3437         struct mlx5_ifc_qpc_bits qpc;
3438
3439         u8         reserved_at_800[0x80];
3440 };
3441
3442 struct mlx5_ifc_rtr2rts_qp_out_bits {
3443         u8         status[0x8];
3444         u8         reserved_at_8[0x18];
3445
3446         u8         syndrome[0x20];
3447
3448         u8         reserved_at_40[0x40];
3449 };
3450
3451 struct mlx5_ifc_rtr2rts_qp_in_bits {
3452         u8         opcode[0x10];
3453         u8         reserved_at_10[0x10];
3454
3455         u8         reserved_at_20[0x10];
3456         u8         op_mod[0x10];
3457
3458         u8         reserved_at_40[0x8];
3459         u8         qpn[0x18];
3460
3461         u8         reserved_at_60[0x20];
3462
3463         u8         opt_param_mask[0x20];
3464
3465         u8         reserved_at_a0[0x20];
3466
3467         struct mlx5_ifc_qpc_bits qpc;
3468
3469         u8         reserved_at_800[0x80];
3470 };
3471
3472 struct mlx5_ifc_rst2init_qp_out_bits {
3473         u8         status[0x8];
3474         u8         reserved_at_8[0x18];
3475
3476         u8         syndrome[0x20];
3477
3478         u8         reserved_at_40[0x40];
3479 };
3480
3481 struct mlx5_ifc_rst2init_qp_in_bits {
3482         u8         opcode[0x10];
3483         u8         reserved_at_10[0x10];
3484
3485         u8         reserved_at_20[0x10];
3486         u8         op_mod[0x10];
3487
3488         u8         reserved_at_40[0x8];
3489         u8         qpn[0x18];
3490
3491         u8         reserved_at_60[0x20];
3492
3493         u8         opt_param_mask[0x20];
3494
3495         u8         reserved_at_a0[0x20];
3496
3497         struct mlx5_ifc_qpc_bits qpc;
3498
3499         u8         reserved_at_800[0x80];
3500 };
3501
3502 struct mlx5_ifc_query_xrq_out_bits {
3503         u8         status[0x8];
3504         u8         reserved_at_8[0x18];
3505
3506         u8         syndrome[0x20];
3507
3508         u8         reserved_at_40[0x40];
3509
3510         struct mlx5_ifc_xrqc_bits xrq_context;
3511 };
3512
3513 struct mlx5_ifc_query_xrq_in_bits {
3514         u8         opcode[0x10];
3515         u8         reserved_at_10[0x10];
3516
3517         u8         reserved_at_20[0x10];
3518         u8         op_mod[0x10];
3519
3520         u8         reserved_at_40[0x8];
3521         u8         xrqn[0x18];
3522
3523         u8         reserved_at_60[0x20];
3524 };
3525
3526 struct mlx5_ifc_query_xrc_srq_out_bits {
3527         u8         status[0x8];
3528         u8         reserved_at_8[0x18];
3529
3530         u8         syndrome[0x20];
3531
3532         u8         reserved_at_40[0x40];
3533
3534         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3535
3536         u8         reserved_at_280[0x600];
3537
3538         u8         pas[0][0x40];
3539 };
3540
3541 struct mlx5_ifc_query_xrc_srq_in_bits {
3542         u8         opcode[0x10];
3543         u8         reserved_at_10[0x10];
3544
3545         u8         reserved_at_20[0x10];
3546         u8         op_mod[0x10];
3547
3548         u8         reserved_at_40[0x8];
3549         u8         xrc_srqn[0x18];
3550
3551         u8         reserved_at_60[0x20];
3552 };
3553
3554 enum {
3555         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3556         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3557 };
3558
3559 struct mlx5_ifc_query_vport_state_out_bits {
3560         u8         status[0x8];
3561         u8         reserved_at_8[0x18];
3562
3563         u8         syndrome[0x20];
3564
3565         u8         reserved_at_40[0x20];
3566
3567         u8         reserved_at_60[0x18];
3568         u8         admin_state[0x4];
3569         u8         state[0x4];
3570 };
3571
3572 enum {
3573         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3574         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3575 };
3576
3577 struct mlx5_ifc_query_vport_state_in_bits {
3578         u8         opcode[0x10];
3579         u8         reserved_at_10[0x10];
3580
3581         u8         reserved_at_20[0x10];
3582         u8         op_mod[0x10];
3583
3584         u8         other_vport[0x1];
3585         u8         reserved_at_41[0xf];
3586         u8         vport_number[0x10];
3587
3588         u8         reserved_at_60[0x20];
3589 };
3590
3591 struct mlx5_ifc_query_vport_counter_out_bits {
3592         u8         status[0x8];
3593         u8         reserved_at_8[0x18];
3594
3595         u8         syndrome[0x20];
3596
3597         u8         reserved_at_40[0x40];
3598
3599         struct mlx5_ifc_traffic_counter_bits received_errors;
3600
3601         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3602
3603         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3604
3605         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3606
3607         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3608
3609         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3610
3611         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3612
3613         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3614
3615         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3616
3617         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3618
3619         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3620
3621         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3622
3623         u8         reserved_at_680[0xa00];
3624 };
3625
3626 enum {
3627         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3628 };
3629
3630 struct mlx5_ifc_query_vport_counter_in_bits {
3631         u8         opcode[0x10];
3632         u8         reserved_at_10[0x10];
3633
3634         u8         reserved_at_20[0x10];
3635         u8         op_mod[0x10];
3636
3637         u8         other_vport[0x1];
3638         u8         reserved_at_41[0xb];
3639         u8         port_num[0x4];
3640         u8         vport_number[0x10];
3641
3642         u8         reserved_at_60[0x60];
3643
3644         u8         clear[0x1];
3645         u8         reserved_at_c1[0x1f];
3646
3647         u8         reserved_at_e0[0x20];
3648 };
3649
3650 struct mlx5_ifc_query_tis_out_bits {
3651         u8         status[0x8];
3652         u8         reserved_at_8[0x18];
3653
3654         u8         syndrome[0x20];
3655
3656         u8         reserved_at_40[0x40];
3657
3658         struct mlx5_ifc_tisc_bits tis_context;
3659 };
3660
3661 struct mlx5_ifc_query_tis_in_bits {
3662         u8         opcode[0x10];
3663         u8         reserved_at_10[0x10];
3664
3665         u8         reserved_at_20[0x10];
3666         u8         op_mod[0x10];
3667
3668         u8         reserved_at_40[0x8];
3669         u8         tisn[0x18];
3670
3671         u8         reserved_at_60[0x20];
3672 };
3673
3674 struct mlx5_ifc_query_tir_out_bits {
3675         u8         status[0x8];
3676         u8         reserved_at_8[0x18];
3677
3678         u8         syndrome[0x20];
3679
3680         u8         reserved_at_40[0xc0];
3681
3682         struct mlx5_ifc_tirc_bits tir_context;
3683 };
3684
3685 struct mlx5_ifc_query_tir_in_bits {
3686         u8         opcode[0x10];
3687         u8         reserved_at_10[0x10];
3688
3689         u8         reserved_at_20[0x10];
3690         u8         op_mod[0x10];
3691
3692         u8         reserved_at_40[0x8];
3693         u8         tirn[0x18];
3694
3695         u8         reserved_at_60[0x20];
3696 };
3697
3698 struct mlx5_ifc_query_srq_out_bits {
3699         u8         status[0x8];
3700         u8         reserved_at_8[0x18];
3701
3702         u8         syndrome[0x20];
3703
3704         u8         reserved_at_40[0x40];
3705
3706         struct mlx5_ifc_srqc_bits srq_context_entry;
3707
3708         u8         reserved_at_280[0x600];
3709
3710         u8         pas[0][0x40];
3711 };
3712
3713 struct mlx5_ifc_query_srq_in_bits {
3714         u8         opcode[0x10];
3715         u8         reserved_at_10[0x10];
3716
3717         u8         reserved_at_20[0x10];
3718         u8         op_mod[0x10];
3719
3720         u8         reserved_at_40[0x8];
3721         u8         srqn[0x18];
3722
3723         u8         reserved_at_60[0x20];
3724 };
3725
3726 struct mlx5_ifc_query_sq_out_bits {
3727         u8         status[0x8];
3728         u8         reserved_at_8[0x18];
3729
3730         u8         syndrome[0x20];
3731
3732         u8         reserved_at_40[0xc0];
3733
3734         struct mlx5_ifc_sqc_bits sq_context;
3735 };
3736
3737 struct mlx5_ifc_query_sq_in_bits {
3738         u8         opcode[0x10];
3739         u8         reserved_at_10[0x10];
3740
3741         u8         reserved_at_20[0x10];
3742         u8         op_mod[0x10];
3743
3744         u8         reserved_at_40[0x8];
3745         u8         sqn[0x18];
3746
3747         u8         reserved_at_60[0x20];
3748 };
3749
3750 struct mlx5_ifc_query_special_contexts_out_bits {
3751         u8         status[0x8];
3752         u8         reserved_at_8[0x18];
3753
3754         u8         syndrome[0x20];
3755
3756         u8         dump_fill_mkey[0x20];
3757
3758         u8         resd_lkey[0x20];
3759
3760         u8         null_mkey[0x20];
3761
3762         u8         reserved_at_a0[0x60];
3763 };
3764
3765 struct mlx5_ifc_query_special_contexts_in_bits {
3766         u8         opcode[0x10];
3767         u8         reserved_at_10[0x10];
3768
3769         u8         reserved_at_20[0x10];
3770         u8         op_mod[0x10];
3771
3772         u8         reserved_at_40[0x40];
3773 };
3774
3775 struct mlx5_ifc_query_scheduling_element_out_bits {
3776         u8         opcode[0x10];
3777         u8         reserved_at_10[0x10];
3778
3779         u8         reserved_at_20[0x10];
3780         u8         op_mod[0x10];
3781
3782         u8         reserved_at_40[0xc0];
3783
3784         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3785
3786         u8         reserved_at_300[0x100];
3787 };
3788
3789 enum {
3790         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3791 };
3792
3793 struct mlx5_ifc_query_scheduling_element_in_bits {
3794         u8         opcode[0x10];
3795         u8         reserved_at_10[0x10];
3796
3797         u8         reserved_at_20[0x10];
3798         u8         op_mod[0x10];
3799
3800         u8         scheduling_hierarchy[0x8];
3801         u8         reserved_at_48[0x18];
3802
3803         u8         scheduling_element_id[0x20];
3804
3805         u8         reserved_at_80[0x180];
3806 };
3807
3808 struct mlx5_ifc_query_rqt_out_bits {
3809         u8         status[0x8];
3810         u8         reserved_at_8[0x18];
3811
3812         u8         syndrome[0x20];
3813
3814         u8         reserved_at_40[0xc0];
3815
3816         struct mlx5_ifc_rqtc_bits rqt_context;
3817 };
3818
3819 struct mlx5_ifc_query_rqt_in_bits {
3820         u8         opcode[0x10];
3821         u8         reserved_at_10[0x10];
3822
3823         u8         reserved_at_20[0x10];
3824         u8         op_mod[0x10];
3825
3826         u8         reserved_at_40[0x8];
3827         u8         rqtn[0x18];
3828
3829         u8         reserved_at_60[0x20];
3830 };
3831
3832 struct mlx5_ifc_query_rq_out_bits {
3833         u8         status[0x8];
3834         u8         reserved_at_8[0x18];
3835
3836         u8         syndrome[0x20];
3837
3838         u8         reserved_at_40[0xc0];
3839
3840         struct mlx5_ifc_rqc_bits rq_context;
3841 };
3842
3843 struct mlx5_ifc_query_rq_in_bits {
3844         u8         opcode[0x10];
3845         u8         reserved_at_10[0x10];
3846
3847         u8         reserved_at_20[0x10];
3848         u8         op_mod[0x10];
3849
3850         u8         reserved_at_40[0x8];
3851         u8         rqn[0x18];
3852
3853         u8         reserved_at_60[0x20];
3854 };
3855
3856 struct mlx5_ifc_query_roce_address_out_bits {
3857         u8         status[0x8];
3858         u8         reserved_at_8[0x18];
3859
3860         u8         syndrome[0x20];
3861
3862         u8         reserved_at_40[0x40];
3863
3864         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3865 };
3866
3867 struct mlx5_ifc_query_roce_address_in_bits {
3868         u8         opcode[0x10];
3869         u8         reserved_at_10[0x10];
3870
3871         u8         reserved_at_20[0x10];
3872         u8         op_mod[0x10];
3873
3874         u8         roce_address_index[0x10];
3875         u8         reserved_at_50[0x10];
3876
3877         u8         reserved_at_60[0x20];
3878 };
3879
3880 struct mlx5_ifc_query_rmp_out_bits {
3881         u8         status[0x8];
3882         u8         reserved_at_8[0x18];
3883
3884         u8         syndrome[0x20];
3885
3886         u8         reserved_at_40[0xc0];
3887
3888         struct mlx5_ifc_rmpc_bits rmp_context;
3889 };
3890
3891 struct mlx5_ifc_query_rmp_in_bits {
3892         u8         opcode[0x10];
3893         u8         reserved_at_10[0x10];
3894
3895         u8         reserved_at_20[0x10];
3896         u8         op_mod[0x10];
3897
3898         u8         reserved_at_40[0x8];
3899         u8         rmpn[0x18];
3900
3901         u8         reserved_at_60[0x20];
3902 };
3903
3904 struct mlx5_ifc_query_qp_out_bits {
3905         u8         status[0x8];
3906         u8         reserved_at_8[0x18];
3907
3908         u8         syndrome[0x20];
3909
3910         u8         reserved_at_40[0x40];
3911
3912         u8         opt_param_mask[0x20];
3913
3914         u8         reserved_at_a0[0x20];
3915
3916         struct mlx5_ifc_qpc_bits qpc;
3917
3918         u8         reserved_at_800[0x80];
3919
3920         u8         pas[0][0x40];
3921 };
3922
3923 struct mlx5_ifc_query_qp_in_bits {
3924         u8         opcode[0x10];
3925         u8         reserved_at_10[0x10];
3926
3927         u8         reserved_at_20[0x10];
3928         u8         op_mod[0x10];
3929
3930         u8         reserved_at_40[0x8];
3931         u8         qpn[0x18];
3932
3933         u8         reserved_at_60[0x20];
3934 };
3935
3936 struct mlx5_ifc_query_q_counter_out_bits {
3937         u8         status[0x8];
3938         u8         reserved_at_8[0x18];
3939
3940         u8         syndrome[0x20];
3941
3942         u8         reserved_at_40[0x40];
3943
3944         u8         rx_write_requests[0x20];
3945
3946         u8         reserved_at_a0[0x20];
3947
3948         u8         rx_read_requests[0x20];
3949
3950         u8         reserved_at_e0[0x20];
3951
3952         u8         rx_atomic_requests[0x20];
3953
3954         u8         reserved_at_120[0x20];
3955
3956         u8         rx_dct_connect[0x20];
3957
3958         u8         reserved_at_160[0x20];
3959
3960         u8         out_of_buffer[0x20];
3961
3962         u8         reserved_at_1a0[0x20];
3963
3964         u8         out_of_sequence[0x20];
3965
3966         u8         reserved_at_1e0[0x20];
3967
3968         u8         duplicate_request[0x20];
3969
3970         u8         reserved_at_220[0x20];
3971
3972         u8         rnr_nak_retry_err[0x20];
3973
3974         u8         reserved_at_260[0x20];
3975
3976         u8         packet_seq_err[0x20];
3977
3978         u8         reserved_at_2a0[0x20];
3979
3980         u8         implied_nak_seq_err[0x20];
3981
3982         u8         reserved_at_2e0[0x20];
3983
3984         u8         local_ack_timeout_err[0x20];
3985
3986         u8         reserved_at_320[0xa0];
3987
3988         u8         resp_local_length_error[0x20];
3989
3990         u8         req_local_length_error[0x20];
3991
3992         u8         resp_local_qp_error[0x20];
3993
3994         u8         local_operation_error[0x20];
3995
3996         u8         resp_local_protection[0x20];
3997
3998         u8         req_local_protection[0x20];
3999
4000         u8         resp_cqe_error[0x20];
4001
4002         u8         req_cqe_error[0x20];
4003
4004         u8         req_mw_binding[0x20];
4005
4006         u8         req_bad_response[0x20];
4007
4008         u8         req_remote_invalid_request[0x20];
4009
4010         u8         resp_remote_invalid_request[0x20];
4011
4012         u8         req_remote_access_errors[0x20];
4013
4014         u8         resp_remote_access_errors[0x20];
4015
4016         u8         req_remote_operation_errors[0x20];
4017
4018         u8         req_transport_retries_exceeded[0x20];
4019
4020         u8         cq_overflow[0x20];
4021
4022         u8         resp_cqe_flush_error[0x20];
4023
4024         u8         req_cqe_flush_error[0x20];
4025
4026         u8         reserved_at_620[0x1e0];
4027 };
4028
4029 struct mlx5_ifc_query_q_counter_in_bits {
4030         u8         opcode[0x10];
4031         u8         reserved_at_10[0x10];
4032
4033         u8         reserved_at_20[0x10];
4034         u8         op_mod[0x10];
4035
4036         u8         reserved_at_40[0x80];
4037
4038         u8         clear[0x1];
4039         u8         reserved_at_c1[0x1f];
4040
4041         u8         reserved_at_e0[0x18];
4042         u8         counter_set_id[0x8];
4043 };
4044
4045 struct mlx5_ifc_query_pages_out_bits {
4046         u8         status[0x8];
4047         u8         reserved_at_8[0x18];
4048
4049         u8         syndrome[0x20];
4050
4051         u8         reserved_at_40[0x10];
4052         u8         function_id[0x10];
4053
4054         u8         num_pages[0x20];
4055 };
4056
4057 enum {
4058         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4059         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4060         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4061 };
4062
4063 struct mlx5_ifc_query_pages_in_bits {
4064         u8         opcode[0x10];
4065         u8         reserved_at_10[0x10];
4066
4067         u8         reserved_at_20[0x10];
4068         u8         op_mod[0x10];
4069
4070         u8         reserved_at_40[0x10];
4071         u8         function_id[0x10];
4072
4073         u8         reserved_at_60[0x20];
4074 };
4075
4076 struct mlx5_ifc_query_nic_vport_context_out_bits {
4077         u8         status[0x8];
4078         u8         reserved_at_8[0x18];
4079
4080         u8         syndrome[0x20];
4081
4082         u8         reserved_at_40[0x40];
4083
4084         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4085 };
4086
4087 struct mlx5_ifc_query_nic_vport_context_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_at_10[0x10];
4090
4091         u8         reserved_at_20[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         other_vport[0x1];
4095         u8         reserved_at_41[0xf];
4096         u8         vport_number[0x10];
4097
4098         u8         reserved_at_60[0x5];
4099         u8         allowed_list_type[0x3];
4100         u8         reserved_at_68[0x18];
4101 };
4102
4103 struct mlx5_ifc_query_mkey_out_bits {
4104         u8         status[0x8];
4105         u8         reserved_at_8[0x18];
4106
4107         u8         syndrome[0x20];
4108
4109         u8         reserved_at_40[0x40];
4110
4111         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4112
4113         u8         reserved_at_280[0x600];
4114
4115         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4116
4117         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4118 };
4119
4120 struct mlx5_ifc_query_mkey_in_bits {
4121         u8         opcode[0x10];
4122         u8         reserved_at_10[0x10];
4123
4124         u8         reserved_at_20[0x10];
4125         u8         op_mod[0x10];
4126
4127         u8         reserved_at_40[0x8];
4128         u8         mkey_index[0x18];
4129
4130         u8         pg_access[0x1];
4131         u8         reserved_at_61[0x1f];
4132 };
4133
4134 struct mlx5_ifc_query_mad_demux_out_bits {
4135         u8         status[0x8];
4136         u8         reserved_at_8[0x18];
4137
4138         u8         syndrome[0x20];
4139
4140         u8         reserved_at_40[0x40];
4141
4142         u8         mad_dumux_parameters_block[0x20];
4143 };
4144
4145 struct mlx5_ifc_query_mad_demux_in_bits {
4146         u8         opcode[0x10];
4147         u8         reserved_at_10[0x10];
4148
4149         u8         reserved_at_20[0x10];
4150         u8         op_mod[0x10];
4151
4152         u8         reserved_at_40[0x40];
4153 };
4154
4155 struct mlx5_ifc_query_l2_table_entry_out_bits {
4156         u8         status[0x8];
4157         u8         reserved_at_8[0x18];
4158
4159         u8         syndrome[0x20];
4160
4161         u8         reserved_at_40[0xa0];
4162
4163         u8         reserved_at_e0[0x13];
4164         u8         vlan_valid[0x1];
4165         u8         vlan[0xc];
4166
4167         struct mlx5_ifc_mac_address_layout_bits mac_address;
4168
4169         u8         reserved_at_140[0xc0];
4170 };
4171
4172 struct mlx5_ifc_query_l2_table_entry_in_bits {
4173         u8         opcode[0x10];
4174         u8         reserved_at_10[0x10];
4175
4176         u8         reserved_at_20[0x10];
4177         u8         op_mod[0x10];
4178
4179         u8         reserved_at_40[0x60];
4180
4181         u8         reserved_at_a0[0x8];
4182         u8         table_index[0x18];
4183
4184         u8         reserved_at_c0[0x140];
4185 };
4186
4187 struct mlx5_ifc_query_issi_out_bits {
4188         u8         status[0x8];
4189         u8         reserved_at_8[0x18];
4190
4191         u8         syndrome[0x20];
4192
4193         u8         reserved_at_40[0x10];
4194         u8         current_issi[0x10];
4195
4196         u8         reserved_at_60[0xa0];
4197
4198         u8         reserved_at_100[76][0x8];
4199         u8         supported_issi_dw0[0x20];
4200 };
4201
4202 struct mlx5_ifc_query_issi_in_bits {
4203         u8         opcode[0x10];
4204         u8         reserved_at_10[0x10];
4205
4206         u8         reserved_at_20[0x10];
4207         u8         op_mod[0x10];
4208
4209         u8         reserved_at_40[0x40];
4210 };
4211
4212 struct mlx5_ifc_set_driver_version_out_bits {
4213         u8         status[0x8];
4214         u8         reserved_0[0x18];
4215
4216         u8         syndrome[0x20];
4217         u8         reserved_1[0x40];
4218 };
4219
4220 struct mlx5_ifc_set_driver_version_in_bits {
4221         u8         opcode[0x10];
4222         u8         reserved_0[0x10];
4223
4224         u8         reserved_1[0x10];
4225         u8         op_mod[0x10];
4226
4227         u8         reserved_2[0x40];
4228         u8         driver_version[64][0x8];
4229 };
4230
4231 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4232         u8         status[0x8];
4233         u8         reserved_at_8[0x18];
4234
4235         u8         syndrome[0x20];
4236
4237         u8         reserved_at_40[0x40];
4238
4239         struct mlx5_ifc_pkey_bits pkey[0];
4240 };
4241
4242 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4243         u8         opcode[0x10];
4244         u8         reserved_at_10[0x10];
4245
4246         u8         reserved_at_20[0x10];
4247         u8         op_mod[0x10];
4248
4249         u8         other_vport[0x1];
4250         u8         reserved_at_41[0xb];
4251         u8         port_num[0x4];
4252         u8         vport_number[0x10];
4253
4254         u8         reserved_at_60[0x10];
4255         u8         pkey_index[0x10];
4256 };
4257
4258 enum {
4259         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4260         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4261         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4262 };
4263
4264 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4265         u8         status[0x8];
4266         u8         reserved_at_8[0x18];
4267
4268         u8         syndrome[0x20];
4269
4270         u8         reserved_at_40[0x20];
4271
4272         u8         gids_num[0x10];
4273         u8         reserved_at_70[0x10];
4274
4275         struct mlx5_ifc_array128_auto_bits gid[0];
4276 };
4277
4278 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4279         u8         opcode[0x10];
4280         u8         reserved_at_10[0x10];
4281
4282         u8         reserved_at_20[0x10];
4283         u8         op_mod[0x10];
4284
4285         u8         other_vport[0x1];
4286         u8         reserved_at_41[0xb];
4287         u8         port_num[0x4];
4288         u8         vport_number[0x10];
4289
4290         u8         reserved_at_60[0x10];
4291         u8         gid_index[0x10];
4292 };
4293
4294 struct mlx5_ifc_query_hca_vport_context_out_bits {
4295         u8         status[0x8];
4296         u8         reserved_at_8[0x18];
4297
4298         u8         syndrome[0x20];
4299
4300         u8         reserved_at_40[0x40];
4301
4302         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4303 };
4304
4305 struct mlx5_ifc_query_hca_vport_context_in_bits {
4306         u8         opcode[0x10];
4307         u8         reserved_at_10[0x10];
4308
4309         u8         reserved_at_20[0x10];
4310         u8         op_mod[0x10];
4311
4312         u8         other_vport[0x1];
4313         u8         reserved_at_41[0xb];
4314         u8         port_num[0x4];
4315         u8         vport_number[0x10];
4316
4317         u8         reserved_at_60[0x20];
4318 };
4319
4320 struct mlx5_ifc_query_hca_cap_out_bits {
4321         u8         status[0x8];
4322         u8         reserved_at_8[0x18];
4323
4324         u8         syndrome[0x20];
4325
4326         u8         reserved_at_40[0x40];
4327
4328         union mlx5_ifc_hca_cap_union_bits capability;
4329 };
4330
4331 struct mlx5_ifc_query_hca_cap_in_bits {
4332         u8         opcode[0x10];
4333         u8         reserved_at_10[0x10];
4334
4335         u8         reserved_at_20[0x10];
4336         u8         op_mod[0x10];
4337
4338         u8         reserved_at_40[0x40];
4339 };
4340
4341 struct mlx5_ifc_query_flow_table_out_bits {
4342         u8         status[0x8];
4343         u8         reserved_at_8[0x18];
4344
4345         u8         syndrome[0x20];
4346
4347         u8         reserved_at_40[0x80];
4348
4349         u8         reserved_at_c0[0x8];
4350         u8         level[0x8];
4351         u8         reserved_at_d0[0x8];
4352         u8         log_size[0x8];
4353
4354         u8         reserved_at_e0[0x120];
4355 };
4356
4357 struct mlx5_ifc_query_flow_table_in_bits {
4358         u8         opcode[0x10];
4359         u8         reserved_at_10[0x10];
4360
4361         u8         reserved_at_20[0x10];
4362         u8         op_mod[0x10];
4363
4364         u8         reserved_at_40[0x40];
4365
4366         u8         table_type[0x8];
4367         u8         reserved_at_88[0x18];
4368
4369         u8         reserved_at_a0[0x8];
4370         u8         table_id[0x18];
4371
4372         u8         reserved_at_c0[0x140];
4373 };
4374
4375 struct mlx5_ifc_query_fte_out_bits {
4376         u8         status[0x8];
4377         u8         reserved_at_8[0x18];
4378
4379         u8         syndrome[0x20];
4380
4381         u8         reserved_at_40[0x1c0];
4382
4383         struct mlx5_ifc_flow_context_bits flow_context;
4384 };
4385
4386 struct mlx5_ifc_query_fte_in_bits {
4387         u8         opcode[0x10];
4388         u8         reserved_at_10[0x10];
4389
4390         u8         reserved_at_20[0x10];
4391         u8         op_mod[0x10];
4392
4393         u8         reserved_at_40[0x40];
4394
4395         u8         table_type[0x8];
4396         u8         reserved_at_88[0x18];
4397
4398         u8         reserved_at_a0[0x8];
4399         u8         table_id[0x18];
4400
4401         u8         reserved_at_c0[0x40];
4402
4403         u8         flow_index[0x20];
4404
4405         u8         reserved_at_120[0xe0];
4406 };
4407
4408 enum {
4409         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4410         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4411         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4412 };
4413
4414 struct mlx5_ifc_query_flow_group_out_bits {
4415         u8         status[0x8];
4416         u8         reserved_at_8[0x18];
4417
4418         u8         syndrome[0x20];
4419
4420         u8         reserved_at_40[0xa0];
4421
4422         u8         start_flow_index[0x20];
4423
4424         u8         reserved_at_100[0x20];
4425
4426         u8         end_flow_index[0x20];
4427
4428         u8         reserved_at_140[0xa0];
4429
4430         u8         reserved_at_1e0[0x18];
4431         u8         match_criteria_enable[0x8];
4432
4433         struct mlx5_ifc_fte_match_param_bits match_criteria;
4434
4435         u8         reserved_at_1200[0xe00];
4436 };
4437
4438 struct mlx5_ifc_query_flow_group_in_bits {
4439         u8         opcode[0x10];
4440         u8         reserved_at_10[0x10];
4441
4442         u8         reserved_at_20[0x10];
4443         u8         op_mod[0x10];
4444
4445         u8         reserved_at_40[0x40];
4446
4447         u8         table_type[0x8];
4448         u8         reserved_at_88[0x18];
4449
4450         u8         reserved_at_a0[0x8];
4451         u8         table_id[0x18];
4452
4453         u8         group_id[0x20];
4454
4455         u8         reserved_at_e0[0x120];
4456 };
4457
4458 struct mlx5_ifc_query_flow_counter_out_bits {
4459         u8         status[0x8];
4460         u8         reserved_at_8[0x18];
4461
4462         u8         syndrome[0x20];
4463
4464         u8         reserved_at_40[0x40];
4465
4466         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4467 };
4468
4469 struct mlx5_ifc_query_flow_counter_in_bits {
4470         u8         opcode[0x10];
4471         u8         reserved_at_10[0x10];
4472
4473         u8         reserved_at_20[0x10];
4474         u8         op_mod[0x10];
4475
4476         u8         reserved_at_40[0x80];
4477
4478         u8         clear[0x1];
4479         u8         reserved_at_c1[0xf];
4480         u8         num_of_counters[0x10];
4481
4482         u8         flow_counter_id[0x20];
4483 };
4484
4485 struct mlx5_ifc_query_esw_vport_context_out_bits {
4486         u8         status[0x8];
4487         u8         reserved_at_8[0x18];
4488
4489         u8         syndrome[0x20];
4490
4491         u8         reserved_at_40[0x40];
4492
4493         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4494 };
4495
4496 struct mlx5_ifc_query_esw_vport_context_in_bits {
4497         u8         opcode[0x10];
4498         u8         reserved_at_10[0x10];
4499
4500         u8         reserved_at_20[0x10];
4501         u8         op_mod[0x10];
4502
4503         u8         other_vport[0x1];
4504         u8         reserved_at_41[0xf];
4505         u8         vport_number[0x10];
4506
4507         u8         reserved_at_60[0x20];
4508 };
4509
4510 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4511         u8         status[0x8];
4512         u8         reserved_at_8[0x18];
4513
4514         u8         syndrome[0x20];
4515
4516         u8         reserved_at_40[0x40];
4517 };
4518
4519 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4520         u8         reserved_at_0[0x1c];
4521         u8         vport_cvlan_insert[0x1];
4522         u8         vport_svlan_insert[0x1];
4523         u8         vport_cvlan_strip[0x1];
4524         u8         vport_svlan_strip[0x1];
4525 };
4526
4527 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4528         u8         opcode[0x10];
4529         u8         reserved_at_10[0x10];
4530
4531         u8         reserved_at_20[0x10];
4532         u8         op_mod[0x10];
4533
4534         u8         other_vport[0x1];
4535         u8         reserved_at_41[0xf];
4536         u8         vport_number[0x10];
4537
4538         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4539
4540         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4541 };
4542
4543 struct mlx5_ifc_query_eq_out_bits {
4544         u8         status[0x8];
4545         u8         reserved_at_8[0x18];
4546
4547         u8         syndrome[0x20];
4548
4549         u8         reserved_at_40[0x40];
4550
4551         struct mlx5_ifc_eqc_bits eq_context_entry;
4552
4553         u8         reserved_at_280[0x40];
4554
4555         u8         event_bitmask[0x40];
4556
4557         u8         reserved_at_300[0x580];
4558
4559         u8         pas[0][0x40];
4560 };
4561
4562 struct mlx5_ifc_query_eq_in_bits {
4563         u8         opcode[0x10];
4564         u8         reserved_at_10[0x10];
4565
4566         u8         reserved_at_20[0x10];
4567         u8         op_mod[0x10];
4568
4569         u8         reserved_at_40[0x18];
4570         u8         eq_number[0x8];
4571
4572         u8         reserved_at_60[0x20];
4573 };
4574
4575 struct mlx5_ifc_encap_header_in_bits {
4576         u8         reserved_at_0[0x5];
4577         u8         header_type[0x3];
4578         u8         reserved_at_8[0xe];
4579         u8         encap_header_size[0xa];
4580
4581         u8         reserved_at_20[0x10];
4582         u8         encap_header[2][0x8];
4583
4584         u8         more_encap_header[0][0x8];
4585 };
4586
4587 struct mlx5_ifc_query_encap_header_out_bits {
4588         u8         status[0x8];
4589         u8         reserved_at_8[0x18];
4590
4591         u8         syndrome[0x20];
4592
4593         u8         reserved_at_40[0xa0];
4594
4595         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4596 };
4597
4598 struct mlx5_ifc_query_encap_header_in_bits {
4599         u8         opcode[0x10];
4600         u8         reserved_at_10[0x10];
4601
4602         u8         reserved_at_20[0x10];
4603         u8         op_mod[0x10];
4604
4605         u8         encap_id[0x20];
4606
4607         u8         reserved_at_60[0xa0];
4608 };
4609
4610 struct mlx5_ifc_alloc_encap_header_out_bits {
4611         u8         status[0x8];
4612         u8         reserved_at_8[0x18];
4613
4614         u8         syndrome[0x20];
4615
4616         u8         encap_id[0x20];
4617
4618         u8         reserved_at_60[0x20];
4619 };
4620
4621 struct mlx5_ifc_alloc_encap_header_in_bits {
4622         u8         opcode[0x10];
4623         u8         reserved_at_10[0x10];
4624
4625         u8         reserved_at_20[0x10];
4626         u8         op_mod[0x10];
4627
4628         u8         reserved_at_40[0xa0];
4629
4630         struct mlx5_ifc_encap_header_in_bits encap_header;
4631 };
4632
4633 struct mlx5_ifc_dealloc_encap_header_out_bits {
4634         u8         status[0x8];
4635         u8         reserved_at_8[0x18];
4636
4637         u8         syndrome[0x20];
4638
4639         u8         reserved_at_40[0x40];
4640 };
4641
4642 struct mlx5_ifc_dealloc_encap_header_in_bits {
4643         u8         opcode[0x10];
4644         u8         reserved_at_10[0x10];
4645
4646         u8         reserved_20[0x10];
4647         u8         op_mod[0x10];
4648
4649         u8         encap_id[0x20];
4650
4651         u8         reserved_60[0x20];
4652 };
4653
4654 struct mlx5_ifc_set_action_in_bits {
4655         u8         action_type[0x4];
4656         u8         field[0xc];
4657         u8         reserved_at_10[0x3];
4658         u8         offset[0x5];
4659         u8         reserved_at_18[0x3];
4660         u8         length[0x5];
4661
4662         u8         data[0x20];
4663 };
4664
4665 struct mlx5_ifc_add_action_in_bits {
4666         u8         action_type[0x4];
4667         u8         field[0xc];
4668         u8         reserved_at_10[0x10];
4669
4670         u8         data[0x20];
4671 };
4672
4673 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4674         struct mlx5_ifc_set_action_in_bits set_action_in;
4675         struct mlx5_ifc_add_action_in_bits add_action_in;
4676         u8         reserved_at_0[0x40];
4677 };
4678
4679 enum {
4680         MLX5_ACTION_TYPE_SET   = 0x1,
4681         MLX5_ACTION_TYPE_ADD   = 0x2,
4682 };
4683
4684 enum {
4685         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4686         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4687         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4688         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4689         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4690         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4691         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4692         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4693         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4694         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4695         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4696         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4697         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4698         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4699         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4700         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4701         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4702         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4703         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4704         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4705         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4706         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4707         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4708 };
4709
4710 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4711         u8         status[0x8];
4712         u8         reserved_at_8[0x18];
4713
4714         u8         syndrome[0x20];
4715
4716         u8         modify_header_id[0x20];
4717
4718         u8         reserved_at_60[0x20];
4719 };
4720
4721 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4722         u8         opcode[0x10];
4723         u8         reserved_at_10[0x10];
4724
4725         u8         reserved_at_20[0x10];
4726         u8         op_mod[0x10];
4727
4728         u8         reserved_at_40[0x20];
4729
4730         u8         table_type[0x8];
4731         u8         reserved_at_68[0x10];
4732         u8         num_of_actions[0x8];
4733
4734         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4735 };
4736
4737 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4738         u8         status[0x8];
4739         u8         reserved_at_8[0x18];
4740
4741         u8         syndrome[0x20];
4742
4743         u8         reserved_at_40[0x40];
4744 };
4745
4746 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4747         u8         opcode[0x10];
4748         u8         reserved_at_10[0x10];
4749
4750         u8         reserved_at_20[0x10];
4751         u8         op_mod[0x10];
4752
4753         u8         modify_header_id[0x20];
4754
4755         u8         reserved_at_60[0x20];
4756 };
4757
4758 struct mlx5_ifc_query_dct_out_bits {
4759         u8         status[0x8];
4760         u8         reserved_at_8[0x18];
4761
4762         u8         syndrome[0x20];
4763
4764         u8         reserved_at_40[0x40];
4765
4766         struct mlx5_ifc_dctc_bits dct_context_entry;
4767
4768         u8         reserved_at_280[0x180];
4769 };
4770
4771 struct mlx5_ifc_query_dct_in_bits {
4772         u8         opcode[0x10];
4773         u8         reserved_at_10[0x10];
4774
4775         u8         reserved_at_20[0x10];
4776         u8         op_mod[0x10];
4777
4778         u8         reserved_at_40[0x8];
4779         u8         dctn[0x18];
4780
4781         u8         reserved_at_60[0x20];
4782 };
4783
4784 struct mlx5_ifc_query_cq_out_bits {
4785         u8         status[0x8];
4786         u8         reserved_at_8[0x18];
4787
4788         u8         syndrome[0x20];
4789
4790         u8         reserved_at_40[0x40];
4791
4792         struct mlx5_ifc_cqc_bits cq_context;
4793
4794         u8         reserved_at_280[0x600];
4795
4796         u8         pas[0][0x40];
4797 };
4798
4799 struct mlx5_ifc_query_cq_in_bits {
4800         u8         opcode[0x10];
4801         u8         reserved_at_10[0x10];
4802
4803         u8         reserved_at_20[0x10];
4804         u8         op_mod[0x10];
4805
4806         u8         reserved_at_40[0x8];
4807         u8         cqn[0x18];
4808
4809         u8         reserved_at_60[0x20];
4810 };
4811
4812 struct mlx5_ifc_query_cong_status_out_bits {
4813         u8         status[0x8];
4814         u8         reserved_at_8[0x18];
4815
4816         u8         syndrome[0x20];
4817
4818         u8         reserved_at_40[0x20];
4819
4820         u8         enable[0x1];
4821         u8         tag_enable[0x1];
4822         u8         reserved_at_62[0x1e];
4823 };
4824
4825 struct mlx5_ifc_query_cong_status_in_bits {
4826         u8         opcode[0x10];
4827         u8         reserved_at_10[0x10];
4828
4829         u8         reserved_at_20[0x10];
4830         u8         op_mod[0x10];
4831
4832         u8         reserved_at_40[0x18];
4833         u8         priority[0x4];
4834         u8         cong_protocol[0x4];
4835
4836         u8         reserved_at_60[0x20];
4837 };
4838
4839 struct mlx5_ifc_query_cong_statistics_out_bits {
4840         u8         status[0x8];
4841         u8         reserved_at_8[0x18];
4842
4843         u8         syndrome[0x20];
4844
4845         u8         reserved_at_40[0x40];
4846
4847         u8         rp_cur_flows[0x20];
4848
4849         u8         sum_flows[0x20];
4850
4851         u8         rp_cnp_ignored_high[0x20];
4852
4853         u8         rp_cnp_ignored_low[0x20];
4854
4855         u8         rp_cnp_handled_high[0x20];
4856
4857         u8         rp_cnp_handled_low[0x20];
4858
4859         u8         reserved_at_140[0x100];
4860
4861         u8         time_stamp_high[0x20];
4862
4863         u8         time_stamp_low[0x20];
4864
4865         u8         accumulators_period[0x20];
4866
4867         u8         np_ecn_marked_roce_packets_high[0x20];
4868
4869         u8         np_ecn_marked_roce_packets_low[0x20];
4870
4871         u8         np_cnp_sent_high[0x20];
4872
4873         u8         np_cnp_sent_low[0x20];
4874
4875         u8         reserved_at_320[0x560];
4876 };
4877
4878 struct mlx5_ifc_query_cong_statistics_in_bits {
4879         u8         opcode[0x10];
4880         u8         reserved_at_10[0x10];
4881
4882         u8         reserved_at_20[0x10];
4883         u8         op_mod[0x10];
4884
4885         u8         clear[0x1];
4886         u8         reserved_at_41[0x1f];
4887
4888         u8         reserved_at_60[0x20];
4889 };
4890
4891 struct mlx5_ifc_query_cong_params_out_bits {
4892         u8         status[0x8];
4893         u8         reserved_at_8[0x18];
4894
4895         u8         syndrome[0x20];
4896
4897         u8         reserved_at_40[0x40];
4898
4899         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4900 };
4901
4902 struct mlx5_ifc_query_cong_params_in_bits {
4903         u8         opcode[0x10];
4904         u8         reserved_at_10[0x10];
4905
4906         u8         reserved_at_20[0x10];
4907         u8         op_mod[0x10];
4908
4909         u8         reserved_at_40[0x1c];
4910         u8         cong_protocol[0x4];
4911
4912         u8         reserved_at_60[0x20];
4913 };
4914
4915 struct mlx5_ifc_query_adapter_out_bits {
4916         u8         status[0x8];
4917         u8         reserved_at_8[0x18];
4918
4919         u8         syndrome[0x20];
4920
4921         u8         reserved_at_40[0x40];
4922
4923         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4924 };
4925
4926 struct mlx5_ifc_query_adapter_in_bits {
4927         u8         opcode[0x10];
4928         u8         reserved_at_10[0x10];
4929
4930         u8         reserved_at_20[0x10];
4931         u8         op_mod[0x10];
4932
4933         u8         reserved_at_40[0x40];
4934 };
4935
4936 struct mlx5_ifc_qp_2rst_out_bits {
4937         u8         status[0x8];
4938         u8         reserved_at_8[0x18];
4939
4940         u8         syndrome[0x20];
4941
4942         u8         reserved_at_40[0x40];
4943 };
4944
4945 struct mlx5_ifc_qp_2rst_in_bits {
4946         u8         opcode[0x10];
4947         u8         reserved_at_10[0x10];
4948
4949         u8         reserved_at_20[0x10];
4950         u8         op_mod[0x10];
4951
4952         u8         reserved_at_40[0x8];
4953         u8         qpn[0x18];
4954
4955         u8         reserved_at_60[0x20];
4956 };
4957
4958 struct mlx5_ifc_qp_2err_out_bits {
4959         u8         status[0x8];
4960         u8         reserved_at_8[0x18];
4961
4962         u8         syndrome[0x20];
4963
4964         u8         reserved_at_40[0x40];
4965 };
4966
4967 struct mlx5_ifc_qp_2err_in_bits {
4968         u8         opcode[0x10];
4969         u8         reserved_at_10[0x10];
4970
4971         u8         reserved_at_20[0x10];
4972         u8         op_mod[0x10];
4973
4974         u8         reserved_at_40[0x8];
4975         u8         qpn[0x18];
4976
4977         u8         reserved_at_60[0x20];
4978 };
4979
4980 struct mlx5_ifc_page_fault_resume_out_bits {
4981         u8         status[0x8];
4982         u8         reserved_at_8[0x18];
4983
4984         u8         syndrome[0x20];
4985
4986         u8         reserved_at_40[0x40];
4987 };
4988
4989 struct mlx5_ifc_page_fault_resume_in_bits {
4990         u8         opcode[0x10];
4991         u8         reserved_at_10[0x10];
4992
4993         u8         reserved_at_20[0x10];
4994         u8         op_mod[0x10];
4995
4996         u8         error[0x1];
4997         u8         reserved_at_41[0x4];
4998         u8         page_fault_type[0x3];
4999         u8         wq_number[0x18];
5000
5001         u8         reserved_at_60[0x8];
5002         u8         token[0x18];
5003 };
5004
5005 struct mlx5_ifc_nop_out_bits {
5006         u8         status[0x8];
5007         u8         reserved_at_8[0x18];
5008
5009         u8         syndrome[0x20];
5010
5011         u8         reserved_at_40[0x40];
5012 };
5013
5014 struct mlx5_ifc_nop_in_bits {
5015         u8         opcode[0x10];
5016         u8         reserved_at_10[0x10];
5017
5018         u8         reserved_at_20[0x10];
5019         u8         op_mod[0x10];
5020
5021         u8         reserved_at_40[0x40];
5022 };
5023
5024 struct mlx5_ifc_modify_vport_state_out_bits {
5025         u8         status[0x8];
5026         u8         reserved_at_8[0x18];
5027
5028         u8         syndrome[0x20];
5029
5030         u8         reserved_at_40[0x40];
5031 };
5032
5033 struct mlx5_ifc_modify_vport_state_in_bits {
5034         u8         opcode[0x10];
5035         u8         reserved_at_10[0x10];
5036
5037         u8         reserved_at_20[0x10];
5038         u8         op_mod[0x10];
5039
5040         u8         other_vport[0x1];
5041         u8         reserved_at_41[0xf];
5042         u8         vport_number[0x10];
5043
5044         u8         reserved_at_60[0x18];
5045         u8         admin_state[0x4];
5046         u8         reserved_at_7c[0x4];
5047 };
5048
5049 struct mlx5_ifc_modify_tis_out_bits {
5050         u8         status[0x8];
5051         u8         reserved_at_8[0x18];
5052
5053         u8         syndrome[0x20];
5054
5055         u8         reserved_at_40[0x40];
5056 };
5057
5058 struct mlx5_ifc_modify_tis_bitmask_bits {
5059         u8         reserved_at_0[0x20];
5060
5061         u8         reserved_at_20[0x1d];
5062         u8         lag_tx_port_affinity[0x1];
5063         u8         strict_lag_tx_port_affinity[0x1];
5064         u8         prio[0x1];
5065 };
5066
5067 struct mlx5_ifc_modify_tis_in_bits {
5068         u8         opcode[0x10];
5069         u8         reserved_at_10[0x10];
5070
5071         u8         reserved_at_20[0x10];
5072         u8         op_mod[0x10];
5073
5074         u8         reserved_at_40[0x8];
5075         u8         tisn[0x18];
5076
5077         u8         reserved_at_60[0x20];
5078
5079         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5080
5081         u8         reserved_at_c0[0x40];
5082
5083         struct mlx5_ifc_tisc_bits ctx;
5084 };
5085
5086 struct mlx5_ifc_modify_tir_bitmask_bits {
5087         u8         reserved_at_0[0x20];
5088
5089         u8         reserved_at_20[0x1b];
5090         u8         self_lb_en[0x1];
5091         u8         reserved_at_3c[0x1];
5092         u8         hash[0x1];
5093         u8         reserved_at_3e[0x1];
5094         u8         lro[0x1];
5095 };
5096
5097 struct mlx5_ifc_modify_tir_out_bits {
5098         u8         status[0x8];
5099         u8         reserved_at_8[0x18];
5100
5101         u8         syndrome[0x20];
5102
5103         u8         reserved_at_40[0x40];
5104 };
5105
5106 struct mlx5_ifc_modify_tir_in_bits {
5107         u8         opcode[0x10];
5108         u8         reserved_at_10[0x10];
5109
5110         u8         reserved_at_20[0x10];
5111         u8         op_mod[0x10];
5112
5113         u8         reserved_at_40[0x8];
5114         u8         tirn[0x18];
5115
5116         u8         reserved_at_60[0x20];
5117
5118         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5119
5120         u8         reserved_at_c0[0x40];
5121
5122         struct mlx5_ifc_tirc_bits ctx;
5123 };
5124
5125 struct mlx5_ifc_modify_sq_out_bits {
5126         u8         status[0x8];
5127         u8         reserved_at_8[0x18];
5128
5129         u8         syndrome[0x20];
5130
5131         u8         reserved_at_40[0x40];
5132 };
5133
5134 struct mlx5_ifc_modify_sq_in_bits {
5135         u8         opcode[0x10];
5136         u8         reserved_at_10[0x10];
5137
5138         u8         reserved_at_20[0x10];
5139         u8         op_mod[0x10];
5140
5141         u8         sq_state[0x4];
5142         u8         reserved_at_44[0x4];
5143         u8         sqn[0x18];
5144
5145         u8         reserved_at_60[0x20];
5146
5147         u8         modify_bitmask[0x40];
5148
5149         u8         reserved_at_c0[0x40];
5150
5151         struct mlx5_ifc_sqc_bits ctx;
5152 };
5153
5154 struct mlx5_ifc_modify_scheduling_element_out_bits {
5155         u8         status[0x8];
5156         u8         reserved_at_8[0x18];
5157
5158         u8         syndrome[0x20];
5159
5160         u8         reserved_at_40[0x1c0];
5161 };
5162
5163 enum {
5164         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5165         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5166 };
5167
5168 struct mlx5_ifc_modify_scheduling_element_in_bits {
5169         u8         opcode[0x10];
5170         u8         reserved_at_10[0x10];
5171
5172         u8         reserved_at_20[0x10];
5173         u8         op_mod[0x10];
5174
5175         u8         scheduling_hierarchy[0x8];
5176         u8         reserved_at_48[0x18];
5177
5178         u8         scheduling_element_id[0x20];
5179
5180         u8         reserved_at_80[0x20];
5181
5182         u8         modify_bitmask[0x20];
5183
5184         u8         reserved_at_c0[0x40];
5185
5186         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5187
5188         u8         reserved_at_300[0x100];
5189 };
5190
5191 struct mlx5_ifc_modify_rqt_out_bits {
5192         u8         status[0x8];
5193         u8         reserved_at_8[0x18];
5194
5195         u8         syndrome[0x20];
5196
5197         u8         reserved_at_40[0x40];
5198 };
5199
5200 struct mlx5_ifc_rqt_bitmask_bits {
5201         u8         reserved_at_0[0x20];
5202
5203         u8         reserved_at_20[0x1f];
5204         u8         rqn_list[0x1];
5205 };
5206
5207 struct mlx5_ifc_modify_rqt_in_bits {
5208         u8         opcode[0x10];
5209         u8         reserved_at_10[0x10];
5210
5211         u8         reserved_at_20[0x10];
5212         u8         op_mod[0x10];
5213
5214         u8         reserved_at_40[0x8];
5215         u8         rqtn[0x18];
5216
5217         u8         reserved_at_60[0x20];
5218
5219         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5220
5221         u8         reserved_at_c0[0x40];
5222
5223         struct mlx5_ifc_rqtc_bits ctx;
5224 };
5225
5226 struct mlx5_ifc_modify_rq_out_bits {
5227         u8         status[0x8];
5228         u8         reserved_at_8[0x18];
5229
5230         u8         syndrome[0x20];
5231
5232         u8         reserved_at_40[0x40];
5233 };
5234
5235 enum {
5236         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5237         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5238         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5239 };
5240
5241 struct mlx5_ifc_modify_rq_in_bits {
5242         u8         opcode[0x10];
5243         u8         reserved_at_10[0x10];
5244
5245         u8         reserved_at_20[0x10];
5246         u8         op_mod[0x10];
5247
5248         u8         rq_state[0x4];
5249         u8         reserved_at_44[0x4];
5250         u8         rqn[0x18];
5251
5252         u8         reserved_at_60[0x20];
5253
5254         u8         modify_bitmask[0x40];
5255
5256         u8         reserved_at_c0[0x40];
5257
5258         struct mlx5_ifc_rqc_bits ctx;
5259 };
5260
5261 struct mlx5_ifc_modify_rmp_out_bits {
5262         u8         status[0x8];
5263         u8         reserved_at_8[0x18];
5264
5265         u8         syndrome[0x20];
5266
5267         u8         reserved_at_40[0x40];
5268 };
5269
5270 struct mlx5_ifc_rmp_bitmask_bits {
5271         u8         reserved_at_0[0x20];
5272
5273         u8         reserved_at_20[0x1f];
5274         u8         lwm[0x1];
5275 };
5276
5277 struct mlx5_ifc_modify_rmp_in_bits {
5278         u8         opcode[0x10];
5279         u8         reserved_at_10[0x10];
5280
5281         u8         reserved_at_20[0x10];
5282         u8         op_mod[0x10];
5283
5284         u8         rmp_state[0x4];
5285         u8         reserved_at_44[0x4];
5286         u8         rmpn[0x18];
5287
5288         u8         reserved_at_60[0x20];
5289
5290         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5291
5292         u8         reserved_at_c0[0x40];
5293
5294         struct mlx5_ifc_rmpc_bits ctx;
5295 };
5296
5297 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5298         u8         status[0x8];
5299         u8         reserved_at_8[0x18];
5300
5301         u8         syndrome[0x20];
5302
5303         u8         reserved_at_40[0x40];
5304 };
5305
5306 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5307         u8         reserved_at_0[0x14];
5308         u8         disable_uc_local_lb[0x1];
5309         u8         disable_mc_local_lb[0x1];
5310         u8         node_guid[0x1];
5311         u8         port_guid[0x1];
5312         u8         min_inline[0x1];
5313         u8         mtu[0x1];
5314         u8         change_event[0x1];
5315         u8         promisc[0x1];
5316         u8         permanent_address[0x1];
5317         u8         addresses_list[0x1];
5318         u8         roce_en[0x1];
5319         u8         reserved_at_1f[0x1];
5320 };
5321
5322 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5323         u8         opcode[0x10];
5324         u8         reserved_at_10[0x10];
5325
5326         u8         reserved_at_20[0x10];
5327         u8         op_mod[0x10];
5328
5329         u8         other_vport[0x1];
5330         u8         reserved_at_41[0xf];
5331         u8         vport_number[0x10];
5332
5333         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5334
5335         u8         reserved_at_80[0x780];
5336
5337         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5338 };
5339
5340 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5341         u8         status[0x8];
5342         u8         reserved_at_8[0x18];
5343
5344         u8         syndrome[0x20];
5345
5346         u8         reserved_at_40[0x40];
5347 };
5348
5349 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5350         u8         opcode[0x10];
5351         u8         reserved_at_10[0x10];
5352
5353         u8         reserved_at_20[0x10];
5354         u8         op_mod[0x10];
5355
5356         u8         other_vport[0x1];
5357         u8         reserved_at_41[0xb];
5358         u8         port_num[0x4];
5359         u8         vport_number[0x10];
5360
5361         u8         reserved_at_60[0x20];
5362
5363         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5364 };
5365
5366 struct mlx5_ifc_modify_cq_out_bits {
5367         u8         status[0x8];
5368         u8         reserved_at_8[0x18];
5369
5370         u8         syndrome[0x20];
5371
5372         u8         reserved_at_40[0x40];
5373 };
5374
5375 enum {
5376         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5377         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5378 };
5379
5380 struct mlx5_ifc_modify_cq_in_bits {
5381         u8         opcode[0x10];
5382         u8         reserved_at_10[0x10];
5383
5384         u8         reserved_at_20[0x10];
5385         u8         op_mod[0x10];
5386
5387         u8         reserved_at_40[0x8];
5388         u8         cqn[0x18];
5389
5390         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5391
5392         struct mlx5_ifc_cqc_bits cq_context;
5393
5394         u8         reserved_at_280[0x600];
5395
5396         u8         pas[0][0x40];
5397 };
5398
5399 struct mlx5_ifc_modify_cong_status_out_bits {
5400         u8         status[0x8];
5401         u8         reserved_at_8[0x18];
5402
5403         u8         syndrome[0x20];
5404
5405         u8         reserved_at_40[0x40];
5406 };
5407
5408 struct mlx5_ifc_modify_cong_status_in_bits {
5409         u8         opcode[0x10];
5410         u8         reserved_at_10[0x10];
5411
5412         u8         reserved_at_20[0x10];
5413         u8         op_mod[0x10];
5414
5415         u8         reserved_at_40[0x18];
5416         u8         priority[0x4];
5417         u8         cong_protocol[0x4];
5418
5419         u8         enable[0x1];
5420         u8         tag_enable[0x1];
5421         u8         reserved_at_62[0x1e];
5422 };
5423
5424 struct mlx5_ifc_modify_cong_params_out_bits {
5425         u8         status[0x8];
5426         u8         reserved_at_8[0x18];
5427
5428         u8         syndrome[0x20];
5429
5430         u8         reserved_at_40[0x40];
5431 };
5432
5433 struct mlx5_ifc_modify_cong_params_in_bits {
5434         u8         opcode[0x10];
5435         u8         reserved_at_10[0x10];
5436
5437         u8         reserved_at_20[0x10];
5438         u8         op_mod[0x10];
5439
5440         u8         reserved_at_40[0x1c];
5441         u8         cong_protocol[0x4];
5442
5443         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5444
5445         u8         reserved_at_80[0x80];
5446
5447         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5448 };
5449
5450 struct mlx5_ifc_manage_pages_out_bits {
5451         u8         status[0x8];
5452         u8         reserved_at_8[0x18];
5453
5454         u8         syndrome[0x20];
5455
5456         u8         output_num_entries[0x20];
5457
5458         u8         reserved_at_60[0x20];
5459
5460         u8         pas[0][0x40];
5461 };
5462
5463 enum {
5464         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5465         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5466         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5467 };
5468
5469 struct mlx5_ifc_manage_pages_in_bits {
5470         u8         opcode[0x10];
5471         u8         reserved_at_10[0x10];
5472
5473         u8         reserved_at_20[0x10];
5474         u8         op_mod[0x10];
5475
5476         u8         reserved_at_40[0x10];
5477         u8         function_id[0x10];
5478
5479         u8         input_num_entries[0x20];
5480
5481         u8         pas[0][0x40];
5482 };
5483
5484 struct mlx5_ifc_mad_ifc_out_bits {
5485         u8         status[0x8];
5486         u8         reserved_at_8[0x18];
5487
5488         u8         syndrome[0x20];
5489
5490         u8         reserved_at_40[0x40];
5491
5492         u8         response_mad_packet[256][0x8];
5493 };
5494
5495 struct mlx5_ifc_mad_ifc_in_bits {
5496         u8         opcode[0x10];
5497         u8         reserved_at_10[0x10];
5498
5499         u8         reserved_at_20[0x10];
5500         u8         op_mod[0x10];
5501
5502         u8         remote_lid[0x10];
5503         u8         reserved_at_50[0x8];
5504         u8         port[0x8];
5505
5506         u8         reserved_at_60[0x20];
5507
5508         u8         mad[256][0x8];
5509 };
5510
5511 struct mlx5_ifc_init_hca_out_bits {
5512         u8         status[0x8];
5513         u8         reserved_at_8[0x18];
5514
5515         u8         syndrome[0x20];
5516
5517         u8         reserved_at_40[0x40];
5518 };
5519
5520 struct mlx5_ifc_init_hca_in_bits {
5521         u8         opcode[0x10];
5522         u8         reserved_at_10[0x10];
5523
5524         u8         reserved_at_20[0x10];
5525         u8         op_mod[0x10];
5526
5527         u8         reserved_at_40[0x40];
5528 };
5529
5530 struct mlx5_ifc_init2rtr_qp_out_bits {
5531         u8         status[0x8];
5532         u8         reserved_at_8[0x18];
5533
5534         u8         syndrome[0x20];
5535
5536         u8         reserved_at_40[0x40];
5537 };
5538
5539 struct mlx5_ifc_init2rtr_qp_in_bits {
5540         u8         opcode[0x10];
5541         u8         reserved_at_10[0x10];
5542
5543         u8         reserved_at_20[0x10];
5544         u8         op_mod[0x10];
5545
5546         u8         reserved_at_40[0x8];
5547         u8         qpn[0x18];
5548
5549         u8         reserved_at_60[0x20];
5550
5551         u8         opt_param_mask[0x20];
5552
5553         u8         reserved_at_a0[0x20];
5554
5555         struct mlx5_ifc_qpc_bits qpc;
5556
5557         u8         reserved_at_800[0x80];
5558 };
5559
5560 struct mlx5_ifc_init2init_qp_out_bits {
5561         u8         status[0x8];
5562         u8         reserved_at_8[0x18];
5563
5564         u8         syndrome[0x20];
5565
5566         u8         reserved_at_40[0x40];
5567 };
5568
5569 struct mlx5_ifc_init2init_qp_in_bits {
5570         u8         opcode[0x10];
5571         u8         reserved_at_10[0x10];
5572
5573         u8         reserved_at_20[0x10];
5574         u8         op_mod[0x10];
5575
5576         u8         reserved_at_40[0x8];
5577         u8         qpn[0x18];
5578
5579         u8         reserved_at_60[0x20];
5580
5581         u8         opt_param_mask[0x20];
5582
5583         u8         reserved_at_a0[0x20];
5584
5585         struct mlx5_ifc_qpc_bits qpc;
5586
5587         u8         reserved_at_800[0x80];
5588 };
5589
5590 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5591         u8         status[0x8];
5592         u8         reserved_at_8[0x18];
5593
5594         u8         syndrome[0x20];
5595
5596         u8         reserved_at_40[0x40];
5597
5598         u8         packet_headers_log[128][0x8];
5599
5600         u8         packet_syndrome[64][0x8];
5601 };
5602
5603 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5604         u8         opcode[0x10];
5605         u8         reserved_at_10[0x10];
5606
5607         u8         reserved_at_20[0x10];
5608         u8         op_mod[0x10];
5609
5610         u8         reserved_at_40[0x40];
5611 };
5612
5613 struct mlx5_ifc_gen_eqe_in_bits {
5614         u8         opcode[0x10];
5615         u8         reserved_at_10[0x10];
5616
5617         u8         reserved_at_20[0x10];
5618         u8         op_mod[0x10];
5619
5620         u8         reserved_at_40[0x18];
5621         u8         eq_number[0x8];
5622
5623         u8         reserved_at_60[0x20];
5624
5625         u8         eqe[64][0x8];
5626 };
5627
5628 struct mlx5_ifc_gen_eq_out_bits {
5629         u8         status[0x8];
5630         u8         reserved_at_8[0x18];
5631
5632         u8         syndrome[0x20];
5633
5634         u8         reserved_at_40[0x40];
5635 };
5636
5637 struct mlx5_ifc_enable_hca_out_bits {
5638         u8         status[0x8];
5639         u8         reserved_at_8[0x18];
5640
5641         u8         syndrome[0x20];
5642
5643         u8         reserved_at_40[0x20];
5644 };
5645
5646 struct mlx5_ifc_enable_hca_in_bits {
5647         u8         opcode[0x10];
5648         u8         reserved_at_10[0x10];
5649
5650         u8         reserved_at_20[0x10];
5651         u8         op_mod[0x10];
5652
5653         u8         reserved_at_40[0x10];
5654         u8         function_id[0x10];
5655
5656         u8         reserved_at_60[0x20];
5657 };
5658
5659 struct mlx5_ifc_drain_dct_out_bits {
5660         u8         status[0x8];
5661         u8         reserved_at_8[0x18];
5662
5663         u8         syndrome[0x20];
5664
5665         u8         reserved_at_40[0x40];
5666 };
5667
5668 struct mlx5_ifc_drain_dct_in_bits {
5669         u8         opcode[0x10];
5670         u8         reserved_at_10[0x10];
5671
5672         u8         reserved_at_20[0x10];
5673         u8         op_mod[0x10];
5674
5675         u8         reserved_at_40[0x8];
5676         u8         dctn[0x18];
5677
5678         u8         reserved_at_60[0x20];
5679 };
5680
5681 struct mlx5_ifc_disable_hca_out_bits {
5682         u8         status[0x8];
5683         u8         reserved_at_8[0x18];
5684
5685         u8         syndrome[0x20];
5686
5687         u8         reserved_at_40[0x20];
5688 };
5689
5690 struct mlx5_ifc_disable_hca_in_bits {
5691         u8         opcode[0x10];
5692         u8         reserved_at_10[0x10];
5693
5694         u8         reserved_at_20[0x10];
5695         u8         op_mod[0x10];
5696
5697         u8         reserved_at_40[0x10];
5698         u8         function_id[0x10];
5699
5700         u8         reserved_at_60[0x20];
5701 };
5702
5703 struct mlx5_ifc_detach_from_mcg_out_bits {
5704         u8         status[0x8];
5705         u8         reserved_at_8[0x18];
5706
5707         u8         syndrome[0x20];
5708
5709         u8         reserved_at_40[0x40];
5710 };
5711
5712 struct mlx5_ifc_detach_from_mcg_in_bits {
5713         u8         opcode[0x10];
5714         u8         reserved_at_10[0x10];
5715
5716         u8         reserved_at_20[0x10];
5717         u8         op_mod[0x10];
5718
5719         u8         reserved_at_40[0x8];
5720         u8         qpn[0x18];
5721
5722         u8         reserved_at_60[0x20];
5723
5724         u8         multicast_gid[16][0x8];
5725 };
5726
5727 struct mlx5_ifc_destroy_xrq_out_bits {
5728         u8         status[0x8];
5729         u8         reserved_at_8[0x18];
5730
5731         u8         syndrome[0x20];
5732
5733         u8         reserved_at_40[0x40];
5734 };
5735
5736 struct mlx5_ifc_destroy_xrq_in_bits {
5737         u8         opcode[0x10];
5738         u8         reserved_at_10[0x10];
5739
5740         u8         reserved_at_20[0x10];
5741         u8         op_mod[0x10];
5742
5743         u8         reserved_at_40[0x8];
5744         u8         xrqn[0x18];
5745
5746         u8         reserved_at_60[0x20];
5747 };
5748
5749 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5750         u8         status[0x8];
5751         u8         reserved_at_8[0x18];
5752
5753         u8         syndrome[0x20];
5754
5755         u8         reserved_at_40[0x40];
5756 };
5757
5758 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5759         u8         opcode[0x10];
5760         u8         reserved_at_10[0x10];
5761
5762         u8         reserved_at_20[0x10];
5763         u8         op_mod[0x10];
5764
5765         u8         reserved_at_40[0x8];
5766         u8         xrc_srqn[0x18];
5767
5768         u8         reserved_at_60[0x20];
5769 };
5770
5771 struct mlx5_ifc_destroy_tis_out_bits {
5772         u8         status[0x8];
5773         u8         reserved_at_8[0x18];
5774
5775         u8         syndrome[0x20];
5776
5777         u8         reserved_at_40[0x40];
5778 };
5779
5780 struct mlx5_ifc_destroy_tis_in_bits {
5781         u8         opcode[0x10];
5782         u8         reserved_at_10[0x10];
5783
5784         u8         reserved_at_20[0x10];
5785         u8         op_mod[0x10];
5786
5787         u8         reserved_at_40[0x8];
5788         u8         tisn[0x18];
5789
5790         u8         reserved_at_60[0x20];
5791 };
5792
5793 struct mlx5_ifc_destroy_tir_out_bits {
5794         u8         status[0x8];
5795         u8         reserved_at_8[0x18];
5796
5797         u8         syndrome[0x20];
5798
5799         u8         reserved_at_40[0x40];
5800 };
5801
5802 struct mlx5_ifc_destroy_tir_in_bits {
5803         u8         opcode[0x10];
5804         u8         reserved_at_10[0x10];
5805
5806         u8         reserved_at_20[0x10];
5807         u8         op_mod[0x10];
5808
5809         u8         reserved_at_40[0x8];
5810         u8         tirn[0x18];
5811
5812         u8         reserved_at_60[0x20];
5813 };
5814
5815 struct mlx5_ifc_destroy_srq_out_bits {
5816         u8         status[0x8];
5817         u8         reserved_at_8[0x18];
5818
5819         u8         syndrome[0x20];
5820
5821         u8         reserved_at_40[0x40];
5822 };
5823
5824 struct mlx5_ifc_destroy_srq_in_bits {
5825         u8         opcode[0x10];
5826         u8         reserved_at_10[0x10];
5827
5828         u8         reserved_at_20[0x10];
5829         u8         op_mod[0x10];
5830
5831         u8         reserved_at_40[0x8];
5832         u8         srqn[0x18];
5833
5834         u8         reserved_at_60[0x20];
5835 };
5836
5837 struct mlx5_ifc_destroy_sq_out_bits {
5838         u8         status[0x8];
5839         u8         reserved_at_8[0x18];
5840
5841         u8         syndrome[0x20];
5842
5843         u8         reserved_at_40[0x40];
5844 };
5845
5846 struct mlx5_ifc_destroy_sq_in_bits {
5847         u8         opcode[0x10];
5848         u8         reserved_at_10[0x10];
5849
5850         u8         reserved_at_20[0x10];
5851         u8         op_mod[0x10];
5852
5853         u8         reserved_at_40[0x8];
5854         u8         sqn[0x18];
5855
5856         u8         reserved_at_60[0x20];
5857 };
5858
5859 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5860         u8         status[0x8];
5861         u8         reserved_at_8[0x18];
5862
5863         u8         syndrome[0x20];
5864
5865         u8         reserved_at_40[0x1c0];
5866 };
5867
5868 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5869         u8         opcode[0x10];
5870         u8         reserved_at_10[0x10];
5871
5872         u8         reserved_at_20[0x10];
5873         u8         op_mod[0x10];
5874
5875         u8         scheduling_hierarchy[0x8];
5876         u8         reserved_at_48[0x18];
5877
5878         u8         scheduling_element_id[0x20];
5879
5880         u8         reserved_at_80[0x180];
5881 };
5882
5883 struct mlx5_ifc_destroy_rqt_out_bits {
5884         u8         status[0x8];
5885         u8         reserved_at_8[0x18];
5886
5887         u8         syndrome[0x20];
5888
5889         u8         reserved_at_40[0x40];
5890 };
5891
5892 struct mlx5_ifc_destroy_rqt_in_bits {
5893         u8         opcode[0x10];
5894         u8         reserved_at_10[0x10];
5895
5896         u8         reserved_at_20[0x10];
5897         u8         op_mod[0x10];
5898
5899         u8         reserved_at_40[0x8];
5900         u8         rqtn[0x18];
5901
5902         u8         reserved_at_60[0x20];
5903 };
5904
5905 struct mlx5_ifc_destroy_rq_out_bits {
5906         u8         status[0x8];
5907         u8         reserved_at_8[0x18];
5908
5909         u8         syndrome[0x20];
5910
5911         u8         reserved_at_40[0x40];
5912 };
5913
5914 struct mlx5_ifc_destroy_rq_in_bits {
5915         u8         opcode[0x10];
5916         u8         reserved_at_10[0x10];
5917
5918         u8         reserved_at_20[0x10];
5919         u8         op_mod[0x10];
5920
5921         u8         reserved_at_40[0x8];
5922         u8         rqn[0x18];
5923
5924         u8         reserved_at_60[0x20];
5925 };
5926
5927 struct mlx5_ifc_set_delay_drop_params_in_bits {
5928         u8         opcode[0x10];
5929         u8         reserved_at_10[0x10];
5930
5931         u8         reserved_at_20[0x10];
5932         u8         op_mod[0x10];
5933
5934         u8         reserved_at_40[0x20];
5935
5936         u8         reserved_at_60[0x10];
5937         u8         delay_drop_timeout[0x10];
5938 };
5939
5940 struct mlx5_ifc_set_delay_drop_params_out_bits {
5941         u8         status[0x8];
5942         u8         reserved_at_8[0x18];
5943
5944         u8         syndrome[0x20];
5945
5946         u8         reserved_at_40[0x40];
5947 };
5948
5949 struct mlx5_ifc_destroy_rmp_out_bits {
5950         u8         status[0x8];
5951         u8         reserved_at_8[0x18];
5952
5953         u8         syndrome[0x20];
5954
5955         u8         reserved_at_40[0x40];
5956 };
5957
5958 struct mlx5_ifc_destroy_rmp_in_bits {
5959         u8         opcode[0x10];
5960         u8         reserved_at_10[0x10];
5961
5962         u8         reserved_at_20[0x10];
5963         u8         op_mod[0x10];
5964
5965         u8         reserved_at_40[0x8];
5966         u8         rmpn[0x18];
5967
5968         u8         reserved_at_60[0x20];
5969 };
5970
5971 struct mlx5_ifc_destroy_qp_out_bits {
5972         u8         status[0x8];
5973         u8         reserved_at_8[0x18];
5974
5975         u8         syndrome[0x20];
5976
5977         u8         reserved_at_40[0x40];
5978 };
5979
5980 struct mlx5_ifc_destroy_qp_in_bits {
5981         u8         opcode[0x10];
5982         u8         reserved_at_10[0x10];
5983
5984         u8         reserved_at_20[0x10];
5985         u8         op_mod[0x10];
5986
5987         u8         reserved_at_40[0x8];
5988         u8         qpn[0x18];
5989
5990         u8         reserved_at_60[0x20];
5991 };
5992
5993 struct mlx5_ifc_destroy_psv_out_bits {
5994         u8         status[0x8];
5995         u8         reserved_at_8[0x18];
5996
5997         u8         syndrome[0x20];
5998
5999         u8         reserved_at_40[0x40];
6000 };
6001
6002 struct mlx5_ifc_destroy_psv_in_bits {
6003         u8         opcode[0x10];
6004         u8         reserved_at_10[0x10];
6005
6006         u8         reserved_at_20[0x10];
6007         u8         op_mod[0x10];
6008
6009         u8         reserved_at_40[0x8];
6010         u8         psvn[0x18];
6011
6012         u8         reserved_at_60[0x20];
6013 };
6014
6015 struct mlx5_ifc_destroy_mkey_out_bits {
6016         u8         status[0x8];
6017         u8         reserved_at_8[0x18];
6018
6019         u8         syndrome[0x20];
6020
6021         u8         reserved_at_40[0x40];
6022 };
6023
6024 struct mlx5_ifc_destroy_mkey_in_bits {
6025         u8         opcode[0x10];
6026         u8         reserved_at_10[0x10];
6027
6028         u8         reserved_at_20[0x10];
6029         u8         op_mod[0x10];
6030
6031         u8         reserved_at_40[0x8];
6032         u8         mkey_index[0x18];
6033
6034         u8         reserved_at_60[0x20];
6035 };
6036
6037 struct mlx5_ifc_destroy_flow_table_out_bits {
6038         u8         status[0x8];
6039         u8         reserved_at_8[0x18];
6040
6041         u8         syndrome[0x20];
6042
6043         u8         reserved_at_40[0x40];
6044 };
6045
6046 struct mlx5_ifc_destroy_flow_table_in_bits {
6047         u8         opcode[0x10];
6048         u8         reserved_at_10[0x10];
6049
6050         u8         reserved_at_20[0x10];
6051         u8         op_mod[0x10];
6052
6053         u8         other_vport[0x1];
6054         u8         reserved_at_41[0xf];
6055         u8         vport_number[0x10];
6056
6057         u8         reserved_at_60[0x20];
6058
6059         u8         table_type[0x8];
6060         u8         reserved_at_88[0x18];
6061
6062         u8         reserved_at_a0[0x8];
6063         u8         table_id[0x18];
6064
6065         u8         reserved_at_c0[0x140];
6066 };
6067
6068 struct mlx5_ifc_destroy_flow_group_out_bits {
6069         u8         status[0x8];
6070         u8         reserved_at_8[0x18];
6071
6072         u8         syndrome[0x20];
6073
6074         u8         reserved_at_40[0x40];
6075 };
6076
6077 struct mlx5_ifc_destroy_flow_group_in_bits {
6078         u8         opcode[0x10];
6079         u8         reserved_at_10[0x10];
6080
6081         u8         reserved_at_20[0x10];
6082         u8         op_mod[0x10];
6083
6084         u8         other_vport[0x1];
6085         u8         reserved_at_41[0xf];
6086         u8         vport_number[0x10];
6087
6088         u8         reserved_at_60[0x20];
6089
6090         u8         table_type[0x8];
6091         u8         reserved_at_88[0x18];
6092
6093         u8         reserved_at_a0[0x8];
6094         u8         table_id[0x18];
6095
6096         u8         group_id[0x20];
6097
6098         u8         reserved_at_e0[0x120];
6099 };
6100
6101 struct mlx5_ifc_destroy_eq_out_bits {
6102         u8         status[0x8];
6103         u8         reserved_at_8[0x18];
6104
6105         u8         syndrome[0x20];
6106
6107         u8         reserved_at_40[0x40];
6108 };
6109
6110 struct mlx5_ifc_destroy_eq_in_bits {
6111         u8         opcode[0x10];
6112         u8         reserved_at_10[0x10];
6113
6114         u8         reserved_at_20[0x10];
6115         u8         op_mod[0x10];
6116
6117         u8         reserved_at_40[0x18];
6118         u8         eq_number[0x8];
6119
6120         u8         reserved_at_60[0x20];
6121 };
6122
6123 struct mlx5_ifc_destroy_dct_out_bits {
6124         u8         status[0x8];
6125         u8         reserved_at_8[0x18];
6126
6127         u8         syndrome[0x20];
6128
6129         u8         reserved_at_40[0x40];
6130 };
6131
6132 struct mlx5_ifc_destroy_dct_in_bits {
6133         u8         opcode[0x10];
6134         u8         reserved_at_10[0x10];
6135
6136         u8         reserved_at_20[0x10];
6137         u8         op_mod[0x10];
6138
6139         u8         reserved_at_40[0x8];
6140         u8         dctn[0x18];
6141
6142         u8         reserved_at_60[0x20];
6143 };
6144
6145 struct mlx5_ifc_destroy_cq_out_bits {
6146         u8         status[0x8];
6147         u8         reserved_at_8[0x18];
6148
6149         u8         syndrome[0x20];
6150
6151         u8         reserved_at_40[0x40];
6152 };
6153
6154 struct mlx5_ifc_destroy_cq_in_bits {
6155         u8         opcode[0x10];
6156         u8         reserved_at_10[0x10];
6157
6158         u8         reserved_at_20[0x10];
6159         u8         op_mod[0x10];
6160
6161         u8         reserved_at_40[0x8];
6162         u8         cqn[0x18];
6163
6164         u8         reserved_at_60[0x20];
6165 };
6166
6167 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6168         u8         status[0x8];
6169         u8         reserved_at_8[0x18];
6170
6171         u8         syndrome[0x20];
6172
6173         u8         reserved_at_40[0x40];
6174 };
6175
6176 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6177         u8         opcode[0x10];
6178         u8         reserved_at_10[0x10];
6179
6180         u8         reserved_at_20[0x10];
6181         u8         op_mod[0x10];
6182
6183         u8         reserved_at_40[0x20];
6184
6185         u8         reserved_at_60[0x10];
6186         u8         vxlan_udp_port[0x10];
6187 };
6188
6189 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6190         u8         status[0x8];
6191         u8         reserved_at_8[0x18];
6192
6193         u8         syndrome[0x20];
6194
6195         u8         reserved_at_40[0x40];
6196 };
6197
6198 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6199         u8         opcode[0x10];
6200         u8         reserved_at_10[0x10];
6201
6202         u8         reserved_at_20[0x10];
6203         u8         op_mod[0x10];
6204
6205         u8         reserved_at_40[0x60];
6206
6207         u8         reserved_at_a0[0x8];
6208         u8         table_index[0x18];
6209
6210         u8         reserved_at_c0[0x140];
6211 };
6212
6213 struct mlx5_ifc_delete_fte_out_bits {
6214         u8         status[0x8];
6215         u8         reserved_at_8[0x18];
6216
6217         u8         syndrome[0x20];
6218
6219         u8         reserved_at_40[0x40];
6220 };
6221
6222 struct mlx5_ifc_delete_fte_in_bits {
6223         u8         opcode[0x10];
6224         u8         reserved_at_10[0x10];
6225
6226         u8         reserved_at_20[0x10];
6227         u8         op_mod[0x10];
6228
6229         u8         other_vport[0x1];
6230         u8         reserved_at_41[0xf];
6231         u8         vport_number[0x10];
6232
6233         u8         reserved_at_60[0x20];
6234
6235         u8         table_type[0x8];
6236         u8         reserved_at_88[0x18];
6237
6238         u8         reserved_at_a0[0x8];
6239         u8         table_id[0x18];
6240
6241         u8         reserved_at_c0[0x40];
6242
6243         u8         flow_index[0x20];
6244
6245         u8         reserved_at_120[0xe0];
6246 };
6247
6248 struct mlx5_ifc_dealloc_xrcd_out_bits {
6249         u8         status[0x8];
6250         u8         reserved_at_8[0x18];
6251
6252         u8         syndrome[0x20];
6253
6254         u8         reserved_at_40[0x40];
6255 };
6256
6257 struct mlx5_ifc_dealloc_xrcd_in_bits {
6258         u8         opcode[0x10];
6259         u8         reserved_at_10[0x10];
6260
6261         u8         reserved_at_20[0x10];
6262         u8         op_mod[0x10];
6263
6264         u8         reserved_at_40[0x8];
6265         u8         xrcd[0x18];
6266
6267         u8         reserved_at_60[0x20];
6268 };
6269
6270 struct mlx5_ifc_dealloc_uar_out_bits {
6271         u8         status[0x8];
6272         u8         reserved_at_8[0x18];
6273
6274         u8         syndrome[0x20];
6275
6276         u8         reserved_at_40[0x40];
6277 };
6278
6279 struct mlx5_ifc_dealloc_uar_in_bits {
6280         u8         opcode[0x10];
6281         u8         reserved_at_10[0x10];
6282
6283         u8         reserved_at_20[0x10];
6284         u8         op_mod[0x10];
6285
6286         u8         reserved_at_40[0x8];
6287         u8         uar[0x18];
6288
6289         u8         reserved_at_60[0x20];
6290 };
6291
6292 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6293         u8         status[0x8];
6294         u8         reserved_at_8[0x18];
6295
6296         u8         syndrome[0x20];
6297
6298         u8         reserved_at_40[0x40];
6299 };
6300
6301 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6302         u8         opcode[0x10];
6303         u8         reserved_at_10[0x10];
6304
6305         u8         reserved_at_20[0x10];
6306         u8         op_mod[0x10];
6307
6308         u8         reserved_at_40[0x8];
6309         u8         transport_domain[0x18];
6310
6311         u8         reserved_at_60[0x20];
6312 };
6313
6314 struct mlx5_ifc_dealloc_q_counter_out_bits {
6315         u8         status[0x8];
6316         u8         reserved_at_8[0x18];
6317
6318         u8         syndrome[0x20];
6319
6320         u8         reserved_at_40[0x40];
6321 };
6322
6323 struct mlx5_ifc_dealloc_q_counter_in_bits {
6324         u8         opcode[0x10];
6325         u8         reserved_at_10[0x10];
6326
6327         u8         reserved_at_20[0x10];
6328         u8         op_mod[0x10];
6329
6330         u8         reserved_at_40[0x18];
6331         u8         counter_set_id[0x8];
6332
6333         u8         reserved_at_60[0x20];
6334 };
6335
6336 struct mlx5_ifc_dealloc_pd_out_bits {
6337         u8         status[0x8];
6338         u8         reserved_at_8[0x18];
6339
6340         u8         syndrome[0x20];
6341
6342         u8         reserved_at_40[0x40];
6343 };
6344
6345 struct mlx5_ifc_dealloc_pd_in_bits {
6346         u8         opcode[0x10];
6347         u8         reserved_at_10[0x10];
6348
6349         u8         reserved_at_20[0x10];
6350         u8         op_mod[0x10];
6351
6352         u8         reserved_at_40[0x8];
6353         u8         pd[0x18];
6354
6355         u8         reserved_at_60[0x20];
6356 };
6357
6358 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6359         u8         status[0x8];
6360         u8         reserved_at_8[0x18];
6361
6362         u8         syndrome[0x20];
6363
6364         u8         reserved_at_40[0x40];
6365 };
6366
6367 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6368         u8         opcode[0x10];
6369         u8         reserved_at_10[0x10];
6370
6371         u8         reserved_at_20[0x10];
6372         u8         op_mod[0x10];
6373
6374         u8         flow_counter_id[0x20];
6375
6376         u8         reserved_at_60[0x20];
6377 };
6378
6379 struct mlx5_ifc_create_xrq_out_bits {
6380         u8         status[0x8];
6381         u8         reserved_at_8[0x18];
6382
6383         u8         syndrome[0x20];
6384
6385         u8         reserved_at_40[0x8];
6386         u8         xrqn[0x18];
6387
6388         u8         reserved_at_60[0x20];
6389 };
6390
6391 struct mlx5_ifc_create_xrq_in_bits {
6392         u8         opcode[0x10];
6393         u8         reserved_at_10[0x10];
6394
6395         u8         reserved_at_20[0x10];
6396         u8         op_mod[0x10];
6397
6398         u8         reserved_at_40[0x40];
6399
6400         struct mlx5_ifc_xrqc_bits xrq_context;
6401 };
6402
6403 struct mlx5_ifc_create_xrc_srq_out_bits {
6404         u8         status[0x8];
6405         u8         reserved_at_8[0x18];
6406
6407         u8         syndrome[0x20];
6408
6409         u8         reserved_at_40[0x8];
6410         u8         xrc_srqn[0x18];
6411
6412         u8         reserved_at_60[0x20];
6413 };
6414
6415 struct mlx5_ifc_create_xrc_srq_in_bits {
6416         u8         opcode[0x10];
6417         u8         reserved_at_10[0x10];
6418
6419         u8         reserved_at_20[0x10];
6420         u8         op_mod[0x10];
6421
6422         u8         reserved_at_40[0x40];
6423
6424         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6425
6426         u8         reserved_at_280[0x600];
6427
6428         u8         pas[0][0x40];
6429 };
6430
6431 struct mlx5_ifc_create_tis_out_bits {
6432         u8         status[0x8];
6433         u8         reserved_at_8[0x18];
6434
6435         u8         syndrome[0x20];
6436
6437         u8         reserved_at_40[0x8];
6438         u8         tisn[0x18];
6439
6440         u8         reserved_at_60[0x20];
6441 };
6442
6443 struct mlx5_ifc_create_tis_in_bits {
6444         u8         opcode[0x10];
6445         u8         reserved_at_10[0x10];
6446
6447         u8         reserved_at_20[0x10];
6448         u8         op_mod[0x10];
6449
6450         u8         reserved_at_40[0xc0];
6451
6452         struct mlx5_ifc_tisc_bits ctx;
6453 };
6454
6455 struct mlx5_ifc_create_tir_out_bits {
6456         u8         status[0x8];
6457         u8         reserved_at_8[0x18];
6458
6459         u8         syndrome[0x20];
6460
6461         u8         reserved_at_40[0x8];
6462         u8         tirn[0x18];
6463
6464         u8         reserved_at_60[0x20];
6465 };
6466
6467 struct mlx5_ifc_create_tir_in_bits {
6468         u8         opcode[0x10];
6469         u8         reserved_at_10[0x10];
6470
6471         u8         reserved_at_20[0x10];
6472         u8         op_mod[0x10];
6473
6474         u8         reserved_at_40[0xc0];
6475
6476         struct mlx5_ifc_tirc_bits ctx;
6477 };
6478
6479 struct mlx5_ifc_create_srq_out_bits {
6480         u8         status[0x8];
6481         u8         reserved_at_8[0x18];
6482
6483         u8         syndrome[0x20];
6484
6485         u8         reserved_at_40[0x8];
6486         u8         srqn[0x18];
6487
6488         u8         reserved_at_60[0x20];
6489 };
6490
6491 struct mlx5_ifc_create_srq_in_bits {
6492         u8         opcode[0x10];
6493         u8         reserved_at_10[0x10];
6494
6495         u8         reserved_at_20[0x10];
6496         u8         op_mod[0x10];
6497
6498         u8         reserved_at_40[0x40];
6499
6500         struct mlx5_ifc_srqc_bits srq_context_entry;
6501
6502         u8         reserved_at_280[0x600];
6503
6504         u8         pas[0][0x40];
6505 };
6506
6507 struct mlx5_ifc_create_sq_out_bits {
6508         u8         status[0x8];
6509         u8         reserved_at_8[0x18];
6510
6511         u8         syndrome[0x20];
6512
6513         u8         reserved_at_40[0x8];
6514         u8         sqn[0x18];
6515
6516         u8         reserved_at_60[0x20];
6517 };
6518
6519 struct mlx5_ifc_create_sq_in_bits {
6520         u8         opcode[0x10];
6521         u8         reserved_at_10[0x10];
6522
6523         u8         reserved_at_20[0x10];
6524         u8         op_mod[0x10];
6525
6526         u8         reserved_at_40[0xc0];
6527
6528         struct mlx5_ifc_sqc_bits ctx;
6529 };
6530
6531 struct mlx5_ifc_create_scheduling_element_out_bits {
6532         u8         status[0x8];
6533         u8         reserved_at_8[0x18];
6534
6535         u8         syndrome[0x20];
6536
6537         u8         reserved_at_40[0x40];
6538
6539         u8         scheduling_element_id[0x20];
6540
6541         u8         reserved_at_a0[0x160];
6542 };
6543
6544 struct mlx5_ifc_create_scheduling_element_in_bits {
6545         u8         opcode[0x10];
6546         u8         reserved_at_10[0x10];
6547
6548         u8         reserved_at_20[0x10];
6549         u8         op_mod[0x10];
6550
6551         u8         scheduling_hierarchy[0x8];
6552         u8         reserved_at_48[0x18];
6553
6554         u8         reserved_at_60[0xa0];
6555
6556         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6557
6558         u8         reserved_at_300[0x100];
6559 };
6560
6561 struct mlx5_ifc_create_rqt_out_bits {
6562         u8         status[0x8];
6563         u8         reserved_at_8[0x18];
6564
6565         u8         syndrome[0x20];
6566
6567         u8         reserved_at_40[0x8];
6568         u8         rqtn[0x18];
6569
6570         u8         reserved_at_60[0x20];
6571 };
6572
6573 struct mlx5_ifc_create_rqt_in_bits {
6574         u8         opcode[0x10];
6575         u8         reserved_at_10[0x10];
6576
6577         u8         reserved_at_20[0x10];
6578         u8         op_mod[0x10];
6579
6580         u8         reserved_at_40[0xc0];
6581
6582         struct mlx5_ifc_rqtc_bits rqt_context;
6583 };
6584
6585 struct mlx5_ifc_create_rq_out_bits {
6586         u8         status[0x8];
6587         u8         reserved_at_8[0x18];
6588
6589         u8         syndrome[0x20];
6590
6591         u8         reserved_at_40[0x8];
6592         u8         rqn[0x18];
6593
6594         u8         reserved_at_60[0x20];
6595 };
6596
6597 struct mlx5_ifc_create_rq_in_bits {
6598         u8         opcode[0x10];
6599         u8         reserved_at_10[0x10];
6600
6601         u8         reserved_at_20[0x10];
6602         u8         op_mod[0x10];
6603
6604         u8         reserved_at_40[0xc0];
6605
6606         struct mlx5_ifc_rqc_bits ctx;
6607 };
6608
6609 struct mlx5_ifc_create_rmp_out_bits {
6610         u8         status[0x8];
6611         u8         reserved_at_8[0x18];
6612
6613         u8         syndrome[0x20];
6614
6615         u8         reserved_at_40[0x8];
6616         u8         rmpn[0x18];
6617
6618         u8         reserved_at_60[0x20];
6619 };
6620
6621 struct mlx5_ifc_create_rmp_in_bits {
6622         u8         opcode[0x10];
6623         u8         reserved_at_10[0x10];
6624
6625         u8         reserved_at_20[0x10];
6626         u8         op_mod[0x10];
6627
6628         u8         reserved_at_40[0xc0];
6629
6630         struct mlx5_ifc_rmpc_bits ctx;
6631 };
6632
6633 struct mlx5_ifc_create_qp_out_bits {
6634         u8         status[0x8];
6635         u8         reserved_at_8[0x18];
6636
6637         u8         syndrome[0x20];
6638
6639         u8         reserved_at_40[0x8];
6640         u8         qpn[0x18];
6641
6642         u8         reserved_at_60[0x20];
6643 };
6644
6645 struct mlx5_ifc_create_qp_in_bits {
6646         u8         opcode[0x10];
6647         u8         reserved_at_10[0x10];
6648
6649         u8         reserved_at_20[0x10];
6650         u8         op_mod[0x10];
6651
6652         u8         reserved_at_40[0x40];
6653
6654         u8         opt_param_mask[0x20];
6655
6656         u8         reserved_at_a0[0x20];
6657
6658         struct mlx5_ifc_qpc_bits qpc;
6659
6660         u8         reserved_at_800[0x80];
6661
6662         u8         pas[0][0x40];
6663 };
6664
6665 struct mlx5_ifc_create_psv_out_bits {
6666         u8         status[0x8];
6667         u8         reserved_at_8[0x18];
6668
6669         u8         syndrome[0x20];
6670
6671         u8         reserved_at_40[0x40];
6672
6673         u8         reserved_at_80[0x8];
6674         u8         psv0_index[0x18];
6675
6676         u8         reserved_at_a0[0x8];
6677         u8         psv1_index[0x18];
6678
6679         u8         reserved_at_c0[0x8];
6680         u8         psv2_index[0x18];
6681
6682         u8         reserved_at_e0[0x8];
6683         u8         psv3_index[0x18];
6684 };
6685
6686 struct mlx5_ifc_create_psv_in_bits {
6687         u8         opcode[0x10];
6688         u8         reserved_at_10[0x10];
6689
6690         u8         reserved_at_20[0x10];
6691         u8         op_mod[0x10];
6692
6693         u8         num_psv[0x4];
6694         u8         reserved_at_44[0x4];
6695         u8         pd[0x18];
6696
6697         u8         reserved_at_60[0x20];
6698 };
6699
6700 struct mlx5_ifc_create_mkey_out_bits {
6701         u8         status[0x8];
6702         u8         reserved_at_8[0x18];
6703
6704         u8         syndrome[0x20];
6705
6706         u8         reserved_at_40[0x8];
6707         u8         mkey_index[0x18];
6708
6709         u8         reserved_at_60[0x20];
6710 };
6711
6712 struct mlx5_ifc_create_mkey_in_bits {
6713         u8         opcode[0x10];
6714         u8         reserved_at_10[0x10];
6715
6716         u8         reserved_at_20[0x10];
6717         u8         op_mod[0x10];
6718
6719         u8         reserved_at_40[0x20];
6720
6721         u8         pg_access[0x1];
6722         u8         reserved_at_61[0x1f];
6723
6724         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6725
6726         u8         reserved_at_280[0x80];
6727
6728         u8         translations_octword_actual_size[0x20];
6729
6730         u8         reserved_at_320[0x560];
6731
6732         u8         klm_pas_mtt[0][0x20];
6733 };
6734
6735 struct mlx5_ifc_create_flow_table_out_bits {
6736         u8         status[0x8];
6737         u8         reserved_at_8[0x18];
6738
6739         u8         syndrome[0x20];
6740
6741         u8         reserved_at_40[0x8];
6742         u8         table_id[0x18];
6743
6744         u8         reserved_at_60[0x20];
6745 };
6746
6747 struct mlx5_ifc_flow_table_context_bits {
6748         u8         encap_en[0x1];
6749         u8         decap_en[0x1];
6750         u8         reserved_at_2[0x2];
6751         u8         table_miss_action[0x4];
6752         u8         level[0x8];
6753         u8         reserved_at_10[0x8];
6754         u8         log_size[0x8];
6755
6756         u8         reserved_at_20[0x8];
6757         u8         table_miss_id[0x18];
6758
6759         u8         reserved_at_40[0x8];
6760         u8         lag_master_next_table_id[0x18];
6761
6762         u8         reserved_at_60[0xe0];
6763 };
6764
6765 struct mlx5_ifc_create_flow_table_in_bits {
6766         u8         opcode[0x10];
6767         u8         reserved_at_10[0x10];
6768
6769         u8         reserved_at_20[0x10];
6770         u8         op_mod[0x10];
6771
6772         u8         other_vport[0x1];
6773         u8         reserved_at_41[0xf];
6774         u8         vport_number[0x10];
6775
6776         u8         reserved_at_60[0x20];
6777
6778         u8         table_type[0x8];
6779         u8         reserved_at_88[0x18];
6780
6781         u8         reserved_at_a0[0x20];
6782
6783         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6784 };
6785
6786 struct mlx5_ifc_create_flow_group_out_bits {
6787         u8         status[0x8];
6788         u8         reserved_at_8[0x18];
6789
6790         u8         syndrome[0x20];
6791
6792         u8         reserved_at_40[0x8];
6793         u8         group_id[0x18];
6794
6795         u8         reserved_at_60[0x20];
6796 };
6797
6798 enum {
6799         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6800         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6801         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6802 };
6803
6804 struct mlx5_ifc_create_flow_group_in_bits {
6805         u8         opcode[0x10];
6806         u8         reserved_at_10[0x10];
6807
6808         u8         reserved_at_20[0x10];
6809         u8         op_mod[0x10];
6810
6811         u8         other_vport[0x1];
6812         u8         reserved_at_41[0xf];
6813         u8         vport_number[0x10];
6814
6815         u8         reserved_at_60[0x20];
6816
6817         u8         table_type[0x8];
6818         u8         reserved_at_88[0x18];
6819
6820         u8         reserved_at_a0[0x8];
6821         u8         table_id[0x18];
6822
6823         u8         reserved_at_c0[0x20];
6824
6825         u8         start_flow_index[0x20];
6826
6827         u8         reserved_at_100[0x20];
6828
6829         u8         end_flow_index[0x20];
6830
6831         u8         reserved_at_140[0xa0];
6832
6833         u8         reserved_at_1e0[0x18];
6834         u8         match_criteria_enable[0x8];
6835
6836         struct mlx5_ifc_fte_match_param_bits match_criteria;
6837
6838         u8         reserved_at_1200[0xe00];
6839 };
6840
6841 struct mlx5_ifc_create_eq_out_bits {
6842         u8         status[0x8];
6843         u8         reserved_at_8[0x18];
6844
6845         u8         syndrome[0x20];
6846
6847         u8         reserved_at_40[0x18];
6848         u8         eq_number[0x8];
6849
6850         u8         reserved_at_60[0x20];
6851 };
6852
6853 struct mlx5_ifc_create_eq_in_bits {
6854         u8         opcode[0x10];
6855         u8         reserved_at_10[0x10];
6856
6857         u8         reserved_at_20[0x10];
6858         u8         op_mod[0x10];
6859
6860         u8         reserved_at_40[0x40];
6861
6862         struct mlx5_ifc_eqc_bits eq_context_entry;
6863
6864         u8         reserved_at_280[0x40];
6865
6866         u8         event_bitmask[0x40];
6867
6868         u8         reserved_at_300[0x580];
6869
6870         u8         pas[0][0x40];
6871 };
6872
6873 struct mlx5_ifc_create_dct_out_bits {
6874         u8         status[0x8];
6875         u8         reserved_at_8[0x18];
6876
6877         u8         syndrome[0x20];
6878
6879         u8         reserved_at_40[0x8];
6880         u8         dctn[0x18];
6881
6882         u8         reserved_at_60[0x20];
6883 };
6884
6885 struct mlx5_ifc_create_dct_in_bits {
6886         u8         opcode[0x10];
6887         u8         reserved_at_10[0x10];
6888
6889         u8         reserved_at_20[0x10];
6890         u8         op_mod[0x10];
6891
6892         u8         reserved_at_40[0x40];
6893
6894         struct mlx5_ifc_dctc_bits dct_context_entry;
6895
6896         u8         reserved_at_280[0x180];
6897 };
6898
6899 struct mlx5_ifc_create_cq_out_bits {
6900         u8         status[0x8];
6901         u8         reserved_at_8[0x18];
6902
6903         u8         syndrome[0x20];
6904
6905         u8         reserved_at_40[0x8];
6906         u8         cqn[0x18];
6907
6908         u8         reserved_at_60[0x20];
6909 };
6910
6911 struct mlx5_ifc_create_cq_in_bits {
6912         u8         opcode[0x10];
6913         u8         reserved_at_10[0x10];
6914
6915         u8         reserved_at_20[0x10];
6916         u8         op_mod[0x10];
6917
6918         u8         reserved_at_40[0x40];
6919
6920         struct mlx5_ifc_cqc_bits cq_context;
6921
6922         u8         reserved_at_280[0x600];
6923
6924         u8         pas[0][0x40];
6925 };
6926
6927 struct mlx5_ifc_config_int_moderation_out_bits {
6928         u8         status[0x8];
6929         u8         reserved_at_8[0x18];
6930
6931         u8         syndrome[0x20];
6932
6933         u8         reserved_at_40[0x4];
6934         u8         min_delay[0xc];
6935         u8         int_vector[0x10];
6936
6937         u8         reserved_at_60[0x20];
6938 };
6939
6940 enum {
6941         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6942         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6943 };
6944
6945 struct mlx5_ifc_config_int_moderation_in_bits {
6946         u8         opcode[0x10];
6947         u8         reserved_at_10[0x10];
6948
6949         u8         reserved_at_20[0x10];
6950         u8         op_mod[0x10];
6951
6952         u8         reserved_at_40[0x4];
6953         u8         min_delay[0xc];
6954         u8         int_vector[0x10];
6955
6956         u8         reserved_at_60[0x20];
6957 };
6958
6959 struct mlx5_ifc_attach_to_mcg_out_bits {
6960         u8         status[0x8];
6961         u8         reserved_at_8[0x18];
6962
6963         u8         syndrome[0x20];
6964
6965         u8         reserved_at_40[0x40];
6966 };
6967
6968 struct mlx5_ifc_attach_to_mcg_in_bits {
6969         u8         opcode[0x10];
6970         u8         reserved_at_10[0x10];
6971
6972         u8         reserved_at_20[0x10];
6973         u8         op_mod[0x10];
6974
6975         u8         reserved_at_40[0x8];
6976         u8         qpn[0x18];
6977
6978         u8         reserved_at_60[0x20];
6979
6980         u8         multicast_gid[16][0x8];
6981 };
6982
6983 struct mlx5_ifc_arm_xrq_out_bits {
6984         u8         status[0x8];
6985         u8         reserved_at_8[0x18];
6986
6987         u8         syndrome[0x20];
6988
6989         u8         reserved_at_40[0x40];
6990 };
6991
6992 struct mlx5_ifc_arm_xrq_in_bits {
6993         u8         opcode[0x10];
6994         u8         reserved_at_10[0x10];
6995
6996         u8         reserved_at_20[0x10];
6997         u8         op_mod[0x10];
6998
6999         u8         reserved_at_40[0x8];
7000         u8         xrqn[0x18];
7001
7002         u8         reserved_at_60[0x10];
7003         u8         lwm[0x10];
7004 };
7005
7006 struct mlx5_ifc_arm_xrc_srq_out_bits {
7007         u8         status[0x8];
7008         u8         reserved_at_8[0x18];
7009
7010         u8         syndrome[0x20];
7011
7012         u8         reserved_at_40[0x40];
7013 };
7014
7015 enum {
7016         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7017 };
7018
7019 struct mlx5_ifc_arm_xrc_srq_in_bits {
7020         u8         opcode[0x10];
7021         u8         reserved_at_10[0x10];
7022
7023         u8         reserved_at_20[0x10];
7024         u8         op_mod[0x10];
7025
7026         u8         reserved_at_40[0x8];
7027         u8         xrc_srqn[0x18];
7028
7029         u8         reserved_at_60[0x10];
7030         u8         lwm[0x10];
7031 };
7032
7033 struct mlx5_ifc_arm_rq_out_bits {
7034         u8         status[0x8];
7035         u8         reserved_at_8[0x18];
7036
7037         u8         syndrome[0x20];
7038
7039         u8         reserved_at_40[0x40];
7040 };
7041
7042 enum {
7043         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7044         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7045 };
7046
7047 struct mlx5_ifc_arm_rq_in_bits {
7048         u8         opcode[0x10];
7049         u8         reserved_at_10[0x10];
7050
7051         u8         reserved_at_20[0x10];
7052         u8         op_mod[0x10];
7053
7054         u8         reserved_at_40[0x8];
7055         u8         srq_number[0x18];
7056
7057         u8         reserved_at_60[0x10];
7058         u8         lwm[0x10];
7059 };
7060
7061 struct mlx5_ifc_arm_dct_out_bits {
7062         u8         status[0x8];
7063         u8         reserved_at_8[0x18];
7064
7065         u8         syndrome[0x20];
7066
7067         u8         reserved_at_40[0x40];
7068 };
7069
7070 struct mlx5_ifc_arm_dct_in_bits {
7071         u8         opcode[0x10];
7072         u8         reserved_at_10[0x10];
7073
7074         u8         reserved_at_20[0x10];
7075         u8         op_mod[0x10];
7076
7077         u8         reserved_at_40[0x8];
7078         u8         dct_number[0x18];
7079
7080         u8         reserved_at_60[0x20];
7081 };
7082
7083 struct mlx5_ifc_alloc_xrcd_out_bits {
7084         u8         status[0x8];
7085         u8         reserved_at_8[0x18];
7086
7087         u8         syndrome[0x20];
7088
7089         u8         reserved_at_40[0x8];
7090         u8         xrcd[0x18];
7091
7092         u8         reserved_at_60[0x20];
7093 };
7094
7095 struct mlx5_ifc_alloc_xrcd_in_bits {
7096         u8         opcode[0x10];
7097         u8         reserved_at_10[0x10];
7098
7099         u8         reserved_at_20[0x10];
7100         u8         op_mod[0x10];
7101
7102         u8         reserved_at_40[0x40];
7103 };
7104
7105 struct mlx5_ifc_alloc_uar_out_bits {
7106         u8         status[0x8];
7107         u8         reserved_at_8[0x18];
7108
7109         u8         syndrome[0x20];
7110
7111         u8         reserved_at_40[0x8];
7112         u8         uar[0x18];
7113
7114         u8         reserved_at_60[0x20];
7115 };
7116
7117 struct mlx5_ifc_alloc_uar_in_bits {
7118         u8         opcode[0x10];
7119         u8         reserved_at_10[0x10];
7120
7121         u8         reserved_at_20[0x10];
7122         u8         op_mod[0x10];
7123
7124         u8         reserved_at_40[0x40];
7125 };
7126
7127 struct mlx5_ifc_alloc_transport_domain_out_bits {
7128         u8         status[0x8];
7129         u8         reserved_at_8[0x18];
7130
7131         u8         syndrome[0x20];
7132
7133         u8         reserved_at_40[0x8];
7134         u8         transport_domain[0x18];
7135
7136         u8         reserved_at_60[0x20];
7137 };
7138
7139 struct mlx5_ifc_alloc_transport_domain_in_bits {
7140         u8         opcode[0x10];
7141         u8         reserved_at_10[0x10];
7142
7143         u8         reserved_at_20[0x10];
7144         u8         op_mod[0x10];
7145
7146         u8         reserved_at_40[0x40];
7147 };
7148
7149 struct mlx5_ifc_alloc_q_counter_out_bits {
7150         u8         status[0x8];
7151         u8         reserved_at_8[0x18];
7152
7153         u8         syndrome[0x20];
7154
7155         u8         reserved_at_40[0x18];
7156         u8         counter_set_id[0x8];
7157
7158         u8         reserved_at_60[0x20];
7159 };
7160
7161 struct mlx5_ifc_alloc_q_counter_in_bits {
7162         u8         opcode[0x10];
7163         u8         reserved_at_10[0x10];
7164
7165         u8         reserved_at_20[0x10];
7166         u8         op_mod[0x10];
7167
7168         u8         reserved_at_40[0x40];
7169 };
7170
7171 struct mlx5_ifc_alloc_pd_out_bits {
7172         u8         status[0x8];
7173         u8         reserved_at_8[0x18];
7174
7175         u8         syndrome[0x20];
7176
7177         u8         reserved_at_40[0x8];
7178         u8         pd[0x18];
7179
7180         u8         reserved_at_60[0x20];
7181 };
7182
7183 struct mlx5_ifc_alloc_pd_in_bits {
7184         u8         opcode[0x10];
7185         u8         reserved_at_10[0x10];
7186
7187         u8         reserved_at_20[0x10];
7188         u8         op_mod[0x10];
7189
7190         u8         reserved_at_40[0x40];
7191 };
7192
7193 struct mlx5_ifc_alloc_flow_counter_out_bits {
7194         u8         status[0x8];
7195         u8         reserved_at_8[0x18];
7196
7197         u8         syndrome[0x20];
7198
7199         u8         flow_counter_id[0x20];
7200
7201         u8         reserved_at_60[0x20];
7202 };
7203
7204 struct mlx5_ifc_alloc_flow_counter_in_bits {
7205         u8         opcode[0x10];
7206         u8         reserved_at_10[0x10];
7207
7208         u8         reserved_at_20[0x10];
7209         u8         op_mod[0x10];
7210
7211         u8         reserved_at_40[0x40];
7212 };
7213
7214 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7215         u8         status[0x8];
7216         u8         reserved_at_8[0x18];
7217
7218         u8         syndrome[0x20];
7219
7220         u8         reserved_at_40[0x40];
7221 };
7222
7223 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7224         u8         opcode[0x10];
7225         u8         reserved_at_10[0x10];
7226
7227         u8         reserved_at_20[0x10];
7228         u8         op_mod[0x10];
7229
7230         u8         reserved_at_40[0x20];
7231
7232         u8         reserved_at_60[0x10];
7233         u8         vxlan_udp_port[0x10];
7234 };
7235
7236 struct mlx5_ifc_set_rate_limit_out_bits {
7237         u8         status[0x8];
7238         u8         reserved_at_8[0x18];
7239
7240         u8         syndrome[0x20];
7241
7242         u8         reserved_at_40[0x40];
7243 };
7244
7245 struct mlx5_ifc_set_rate_limit_in_bits {
7246         u8         opcode[0x10];
7247         u8         reserved_at_10[0x10];
7248
7249         u8         reserved_at_20[0x10];
7250         u8         op_mod[0x10];
7251
7252         u8         reserved_at_40[0x10];
7253         u8         rate_limit_index[0x10];
7254
7255         u8         reserved_at_60[0x20];
7256
7257         u8         rate_limit[0x20];
7258 };
7259
7260 struct mlx5_ifc_access_register_out_bits {
7261         u8         status[0x8];
7262         u8         reserved_at_8[0x18];
7263
7264         u8         syndrome[0x20];
7265
7266         u8         reserved_at_40[0x40];
7267
7268         u8         register_data[0][0x20];
7269 };
7270
7271 enum {
7272         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7273         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7274 };
7275
7276 struct mlx5_ifc_access_register_in_bits {
7277         u8         opcode[0x10];
7278         u8         reserved_at_10[0x10];
7279
7280         u8         reserved_at_20[0x10];
7281         u8         op_mod[0x10];
7282
7283         u8         reserved_at_40[0x10];
7284         u8         register_id[0x10];
7285
7286         u8         argument[0x20];
7287
7288         u8         register_data[0][0x20];
7289 };
7290
7291 struct mlx5_ifc_sltp_reg_bits {
7292         u8         status[0x4];
7293         u8         version[0x4];
7294         u8         local_port[0x8];
7295         u8         pnat[0x2];
7296         u8         reserved_at_12[0x2];
7297         u8         lane[0x4];
7298         u8         reserved_at_18[0x8];
7299
7300         u8         reserved_at_20[0x20];
7301
7302         u8         reserved_at_40[0x7];
7303         u8         polarity[0x1];
7304         u8         ob_tap0[0x8];
7305         u8         ob_tap1[0x8];
7306         u8         ob_tap2[0x8];
7307
7308         u8         reserved_at_60[0xc];
7309         u8         ob_preemp_mode[0x4];
7310         u8         ob_reg[0x8];
7311         u8         ob_bias[0x8];
7312
7313         u8         reserved_at_80[0x20];
7314 };
7315
7316 struct mlx5_ifc_slrg_reg_bits {
7317         u8         status[0x4];
7318         u8         version[0x4];
7319         u8         local_port[0x8];
7320         u8         pnat[0x2];
7321         u8         reserved_at_12[0x2];
7322         u8         lane[0x4];
7323         u8         reserved_at_18[0x8];
7324
7325         u8         time_to_link_up[0x10];
7326         u8         reserved_at_30[0xc];
7327         u8         grade_lane_speed[0x4];
7328
7329         u8         grade_version[0x8];
7330         u8         grade[0x18];
7331
7332         u8         reserved_at_60[0x4];
7333         u8         height_grade_type[0x4];
7334         u8         height_grade[0x18];
7335
7336         u8         height_dz[0x10];
7337         u8         height_dv[0x10];
7338
7339         u8         reserved_at_a0[0x10];
7340         u8         height_sigma[0x10];
7341
7342         u8         reserved_at_c0[0x20];
7343
7344         u8         reserved_at_e0[0x4];
7345         u8         phase_grade_type[0x4];
7346         u8         phase_grade[0x18];
7347
7348         u8         reserved_at_100[0x8];
7349         u8         phase_eo_pos[0x8];
7350         u8         reserved_at_110[0x8];
7351         u8         phase_eo_neg[0x8];
7352
7353         u8         ffe_set_tested[0x10];
7354         u8         test_errors_per_lane[0x10];
7355 };
7356
7357 struct mlx5_ifc_pvlc_reg_bits {
7358         u8         reserved_at_0[0x8];
7359         u8         local_port[0x8];
7360         u8         reserved_at_10[0x10];
7361
7362         u8         reserved_at_20[0x1c];
7363         u8         vl_hw_cap[0x4];
7364
7365         u8         reserved_at_40[0x1c];
7366         u8         vl_admin[0x4];
7367
7368         u8         reserved_at_60[0x1c];
7369         u8         vl_operational[0x4];
7370 };
7371
7372 struct mlx5_ifc_pude_reg_bits {
7373         u8         swid[0x8];
7374         u8         local_port[0x8];
7375         u8         reserved_at_10[0x4];
7376         u8         admin_status[0x4];
7377         u8         reserved_at_18[0x4];
7378         u8         oper_status[0x4];
7379
7380         u8         reserved_at_20[0x60];
7381 };
7382
7383 struct mlx5_ifc_ptys_reg_bits {
7384         u8         reserved_at_0[0x1];
7385         u8         an_disable_admin[0x1];
7386         u8         an_disable_cap[0x1];
7387         u8         reserved_at_3[0x5];
7388         u8         local_port[0x8];
7389         u8         reserved_at_10[0xd];
7390         u8         proto_mask[0x3];
7391
7392         u8         an_status[0x4];
7393         u8         reserved_at_24[0x3c];
7394
7395         u8         eth_proto_capability[0x20];
7396
7397         u8         ib_link_width_capability[0x10];
7398         u8         ib_proto_capability[0x10];
7399
7400         u8         reserved_at_a0[0x20];
7401
7402         u8         eth_proto_admin[0x20];
7403
7404         u8         ib_link_width_admin[0x10];
7405         u8         ib_proto_admin[0x10];
7406
7407         u8         reserved_at_100[0x20];
7408
7409         u8         eth_proto_oper[0x20];
7410
7411         u8         ib_link_width_oper[0x10];
7412         u8         ib_proto_oper[0x10];
7413
7414         u8         reserved_at_160[0x1c];
7415         u8         connector_type[0x4];
7416
7417         u8         eth_proto_lp_advertise[0x20];
7418
7419         u8         reserved_at_1a0[0x60];
7420 };
7421
7422 struct mlx5_ifc_mlcr_reg_bits {
7423         u8         reserved_at_0[0x8];
7424         u8         local_port[0x8];
7425         u8         reserved_at_10[0x20];
7426
7427         u8         beacon_duration[0x10];
7428         u8         reserved_at_40[0x10];
7429
7430         u8         beacon_remain[0x10];
7431 };
7432
7433 struct mlx5_ifc_ptas_reg_bits {
7434         u8         reserved_at_0[0x20];
7435
7436         u8         algorithm_options[0x10];
7437         u8         reserved_at_30[0x4];
7438         u8         repetitions_mode[0x4];
7439         u8         num_of_repetitions[0x8];
7440
7441         u8         grade_version[0x8];
7442         u8         height_grade_type[0x4];
7443         u8         phase_grade_type[0x4];
7444         u8         height_grade_weight[0x8];
7445         u8         phase_grade_weight[0x8];
7446
7447         u8         gisim_measure_bits[0x10];
7448         u8         adaptive_tap_measure_bits[0x10];
7449
7450         u8         ber_bath_high_error_threshold[0x10];
7451         u8         ber_bath_mid_error_threshold[0x10];
7452
7453         u8         ber_bath_low_error_threshold[0x10];
7454         u8         one_ratio_high_threshold[0x10];
7455
7456         u8         one_ratio_high_mid_threshold[0x10];
7457         u8         one_ratio_low_mid_threshold[0x10];
7458
7459         u8         one_ratio_low_threshold[0x10];
7460         u8         ndeo_error_threshold[0x10];
7461
7462         u8         mixer_offset_step_size[0x10];
7463         u8         reserved_at_110[0x8];
7464         u8         mix90_phase_for_voltage_bath[0x8];
7465
7466         u8         mixer_offset_start[0x10];
7467         u8         mixer_offset_end[0x10];
7468
7469         u8         reserved_at_140[0x15];
7470         u8         ber_test_time[0xb];
7471 };
7472
7473 struct mlx5_ifc_pspa_reg_bits {
7474         u8         swid[0x8];
7475         u8         local_port[0x8];
7476         u8         sub_port[0x8];
7477         u8         reserved_at_18[0x8];
7478
7479         u8         reserved_at_20[0x20];
7480 };
7481
7482 struct mlx5_ifc_pqdr_reg_bits {
7483         u8         reserved_at_0[0x8];
7484         u8         local_port[0x8];
7485         u8         reserved_at_10[0x5];
7486         u8         prio[0x3];
7487         u8         reserved_at_18[0x6];
7488         u8         mode[0x2];
7489
7490         u8         reserved_at_20[0x20];
7491
7492         u8         reserved_at_40[0x10];
7493         u8         min_threshold[0x10];
7494
7495         u8         reserved_at_60[0x10];
7496         u8         max_threshold[0x10];
7497
7498         u8         reserved_at_80[0x10];
7499         u8         mark_probability_denominator[0x10];
7500
7501         u8         reserved_at_a0[0x60];
7502 };
7503
7504 struct mlx5_ifc_ppsc_reg_bits {
7505         u8         reserved_at_0[0x8];
7506         u8         local_port[0x8];
7507         u8         reserved_at_10[0x10];
7508
7509         u8         reserved_at_20[0x60];
7510
7511         u8         reserved_at_80[0x1c];
7512         u8         wrps_admin[0x4];
7513
7514         u8         reserved_at_a0[0x1c];
7515         u8         wrps_status[0x4];
7516
7517         u8         reserved_at_c0[0x8];
7518         u8         up_threshold[0x8];
7519         u8         reserved_at_d0[0x8];
7520         u8         down_threshold[0x8];
7521
7522         u8         reserved_at_e0[0x20];
7523
7524         u8         reserved_at_100[0x1c];
7525         u8         srps_admin[0x4];
7526
7527         u8         reserved_at_120[0x1c];
7528         u8         srps_status[0x4];
7529
7530         u8         reserved_at_140[0x40];
7531 };
7532
7533 struct mlx5_ifc_pplr_reg_bits {
7534         u8         reserved_at_0[0x8];
7535         u8         local_port[0x8];
7536         u8         reserved_at_10[0x10];
7537
7538         u8         reserved_at_20[0x8];
7539         u8         lb_cap[0x8];
7540         u8         reserved_at_30[0x8];
7541         u8         lb_en[0x8];
7542 };
7543
7544 struct mlx5_ifc_pplm_reg_bits {
7545         u8         reserved_at_0[0x8];
7546         u8         local_port[0x8];
7547         u8         reserved_at_10[0x10];
7548
7549         u8         reserved_at_20[0x20];
7550
7551         u8         port_profile_mode[0x8];
7552         u8         static_port_profile[0x8];
7553         u8         active_port_profile[0x8];
7554         u8         reserved_at_58[0x8];
7555
7556         u8         retransmission_active[0x8];
7557         u8         fec_mode_active[0x18];
7558
7559         u8         reserved_at_80[0x20];
7560 };
7561
7562 struct mlx5_ifc_ppcnt_reg_bits {
7563         u8         swid[0x8];
7564         u8         local_port[0x8];
7565         u8         pnat[0x2];
7566         u8         reserved_at_12[0x8];
7567         u8         grp[0x6];
7568
7569         u8         clr[0x1];
7570         u8         reserved_at_21[0x1c];
7571         u8         prio_tc[0x3];
7572
7573         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7574 };
7575
7576 struct mlx5_ifc_mpcnt_reg_bits {
7577         u8         reserved_at_0[0x8];
7578         u8         pcie_index[0x8];
7579         u8         reserved_at_10[0xa];
7580         u8         grp[0x6];
7581
7582         u8         clr[0x1];
7583         u8         reserved_at_21[0x1f];
7584
7585         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7586 };
7587
7588 struct mlx5_ifc_ppad_reg_bits {
7589         u8         reserved_at_0[0x3];
7590         u8         single_mac[0x1];
7591         u8         reserved_at_4[0x4];
7592         u8         local_port[0x8];
7593         u8         mac_47_32[0x10];
7594
7595         u8         mac_31_0[0x20];
7596
7597         u8         reserved_at_40[0x40];
7598 };
7599
7600 struct mlx5_ifc_pmtu_reg_bits {
7601         u8         reserved_at_0[0x8];
7602         u8         local_port[0x8];
7603         u8         reserved_at_10[0x10];
7604
7605         u8         max_mtu[0x10];
7606         u8         reserved_at_30[0x10];
7607
7608         u8         admin_mtu[0x10];
7609         u8         reserved_at_50[0x10];
7610
7611         u8         oper_mtu[0x10];
7612         u8         reserved_at_70[0x10];
7613 };
7614
7615 struct mlx5_ifc_pmpr_reg_bits {
7616         u8         reserved_at_0[0x8];
7617         u8         module[0x8];
7618         u8         reserved_at_10[0x10];
7619
7620         u8         reserved_at_20[0x18];
7621         u8         attenuation_5g[0x8];
7622
7623         u8         reserved_at_40[0x18];
7624         u8         attenuation_7g[0x8];
7625
7626         u8         reserved_at_60[0x18];
7627         u8         attenuation_12g[0x8];
7628 };
7629
7630 struct mlx5_ifc_pmpe_reg_bits {
7631         u8         reserved_at_0[0x8];
7632         u8         module[0x8];
7633         u8         reserved_at_10[0xc];
7634         u8         module_status[0x4];
7635
7636         u8         reserved_at_20[0x60];
7637 };
7638
7639 struct mlx5_ifc_pmpc_reg_bits {
7640         u8         module_state_updated[32][0x8];
7641 };
7642
7643 struct mlx5_ifc_pmlpn_reg_bits {
7644         u8         reserved_at_0[0x4];
7645         u8         mlpn_status[0x4];
7646         u8         local_port[0x8];
7647         u8         reserved_at_10[0x10];
7648
7649         u8         e[0x1];
7650         u8         reserved_at_21[0x1f];
7651 };
7652
7653 struct mlx5_ifc_pmlp_reg_bits {
7654         u8         rxtx[0x1];
7655         u8         reserved_at_1[0x7];
7656         u8         local_port[0x8];
7657         u8         reserved_at_10[0x8];
7658         u8         width[0x8];
7659
7660         u8         lane0_module_mapping[0x20];
7661
7662         u8         lane1_module_mapping[0x20];
7663
7664         u8         lane2_module_mapping[0x20];
7665
7666         u8         lane3_module_mapping[0x20];
7667
7668         u8         reserved_at_a0[0x160];
7669 };
7670
7671 struct mlx5_ifc_pmaos_reg_bits {
7672         u8         reserved_at_0[0x8];
7673         u8         module[0x8];
7674         u8         reserved_at_10[0x4];
7675         u8         admin_status[0x4];
7676         u8         reserved_at_18[0x4];
7677         u8         oper_status[0x4];
7678
7679         u8         ase[0x1];
7680         u8         ee[0x1];
7681         u8         reserved_at_22[0x1c];
7682         u8         e[0x2];
7683
7684         u8         reserved_at_40[0x40];
7685 };
7686
7687 struct mlx5_ifc_plpc_reg_bits {
7688         u8         reserved_at_0[0x4];
7689         u8         profile_id[0xc];
7690         u8         reserved_at_10[0x4];
7691         u8         proto_mask[0x4];
7692         u8         reserved_at_18[0x8];
7693
7694         u8         reserved_at_20[0x10];
7695         u8         lane_speed[0x10];
7696
7697         u8         reserved_at_40[0x17];
7698         u8         lpbf[0x1];
7699         u8         fec_mode_policy[0x8];
7700
7701         u8         retransmission_capability[0x8];
7702         u8         fec_mode_capability[0x18];
7703
7704         u8         retransmission_support_admin[0x8];
7705         u8         fec_mode_support_admin[0x18];
7706
7707         u8         retransmission_request_admin[0x8];
7708         u8         fec_mode_request_admin[0x18];
7709
7710         u8         reserved_at_c0[0x80];
7711 };
7712
7713 struct mlx5_ifc_plib_reg_bits {
7714         u8         reserved_at_0[0x8];
7715         u8         local_port[0x8];
7716         u8         reserved_at_10[0x8];
7717         u8         ib_port[0x8];
7718
7719         u8         reserved_at_20[0x60];
7720 };
7721
7722 struct mlx5_ifc_plbf_reg_bits {
7723         u8         reserved_at_0[0x8];
7724         u8         local_port[0x8];
7725         u8         reserved_at_10[0xd];
7726         u8         lbf_mode[0x3];
7727
7728         u8         reserved_at_20[0x20];
7729 };
7730
7731 struct mlx5_ifc_pipg_reg_bits {
7732         u8         reserved_at_0[0x8];
7733         u8         local_port[0x8];
7734         u8         reserved_at_10[0x10];
7735
7736         u8         dic[0x1];
7737         u8         reserved_at_21[0x19];
7738         u8         ipg[0x4];
7739         u8         reserved_at_3e[0x2];
7740 };
7741
7742 struct mlx5_ifc_pifr_reg_bits {
7743         u8         reserved_at_0[0x8];
7744         u8         local_port[0x8];
7745         u8         reserved_at_10[0x10];
7746
7747         u8         reserved_at_20[0xe0];
7748
7749         u8         port_filter[8][0x20];
7750
7751         u8         port_filter_update_en[8][0x20];
7752 };
7753
7754 struct mlx5_ifc_pfcc_reg_bits {
7755         u8         reserved_at_0[0x8];
7756         u8         local_port[0x8];
7757         u8         reserved_at_10[0x10];
7758
7759         u8         ppan[0x4];
7760         u8         reserved_at_24[0x4];
7761         u8         prio_mask_tx[0x8];
7762         u8         reserved_at_30[0x8];
7763         u8         prio_mask_rx[0x8];
7764
7765         u8         pptx[0x1];
7766         u8         aptx[0x1];
7767         u8         reserved_at_42[0x6];
7768         u8         pfctx[0x8];
7769         u8         reserved_at_50[0x10];
7770
7771         u8         pprx[0x1];
7772         u8         aprx[0x1];
7773         u8         reserved_at_62[0x6];
7774         u8         pfcrx[0x8];
7775         u8         reserved_at_70[0x10];
7776
7777         u8         reserved_at_80[0x80];
7778 };
7779
7780 struct mlx5_ifc_pelc_reg_bits {
7781         u8         op[0x4];
7782         u8         reserved_at_4[0x4];
7783         u8         local_port[0x8];
7784         u8         reserved_at_10[0x10];
7785
7786         u8         op_admin[0x8];
7787         u8         op_capability[0x8];
7788         u8         op_request[0x8];
7789         u8         op_active[0x8];
7790
7791         u8         admin[0x40];
7792
7793         u8         capability[0x40];
7794
7795         u8         request[0x40];
7796
7797         u8         active[0x40];
7798
7799         u8         reserved_at_140[0x80];
7800 };
7801
7802 struct mlx5_ifc_peir_reg_bits {
7803         u8         reserved_at_0[0x8];
7804         u8         local_port[0x8];
7805         u8         reserved_at_10[0x10];
7806
7807         u8         reserved_at_20[0xc];
7808         u8         error_count[0x4];
7809         u8         reserved_at_30[0x10];
7810
7811         u8         reserved_at_40[0xc];
7812         u8         lane[0x4];
7813         u8         reserved_at_50[0x8];
7814         u8         error_type[0x8];
7815 };
7816
7817 struct mlx5_ifc_pcam_enhanced_features_bits {
7818         u8         reserved_at_0[0x7b];
7819
7820         u8         rx_buffer_fullness_counters[0x1];
7821         u8         ptys_connector_type[0x1];
7822         u8         reserved_at_7d[0x1];
7823         u8         ppcnt_discard_group[0x1];
7824         u8         ppcnt_statistical_group[0x1];
7825 };
7826
7827 struct mlx5_ifc_pcam_reg_bits {
7828         u8         reserved_at_0[0x8];
7829         u8         feature_group[0x8];
7830         u8         reserved_at_10[0x8];
7831         u8         access_reg_group[0x8];
7832
7833         u8         reserved_at_20[0x20];
7834
7835         union {
7836                 u8         reserved_at_0[0x80];
7837         } port_access_reg_cap_mask;
7838
7839         u8         reserved_at_c0[0x80];
7840
7841         union {
7842                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7843                 u8         reserved_at_0[0x80];
7844         } feature_cap_mask;
7845
7846         u8         reserved_at_1c0[0xc0];
7847 };
7848
7849 struct mlx5_ifc_mcam_enhanced_features_bits {
7850         u8         reserved_at_0[0x7b];
7851         u8         pcie_outbound_stalled[0x1];
7852         u8         tx_overflow_buffer_pkt[0x1];
7853         u8         mtpps_enh_out_per_adj[0x1];
7854         u8         mtpps_fs[0x1];
7855         u8         pcie_performance_group[0x1];
7856 };
7857
7858 struct mlx5_ifc_mcam_access_reg_bits {
7859         u8         reserved_at_0[0x1c];
7860         u8         mcda[0x1];
7861         u8         mcc[0x1];
7862         u8         mcqi[0x1];
7863         u8         reserved_at_1f[0x1];
7864
7865         u8         regs_95_to_64[0x20];
7866         u8         regs_63_to_32[0x20];
7867         u8         regs_31_to_0[0x20];
7868 };
7869
7870 struct mlx5_ifc_mcam_reg_bits {
7871         u8         reserved_at_0[0x8];
7872         u8         feature_group[0x8];
7873         u8         reserved_at_10[0x8];
7874         u8         access_reg_group[0x8];
7875
7876         u8         reserved_at_20[0x20];
7877
7878         union {
7879                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7880                 u8         reserved_at_0[0x80];
7881         } mng_access_reg_cap_mask;
7882
7883         u8         reserved_at_c0[0x80];
7884
7885         union {
7886                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7887                 u8         reserved_at_0[0x80];
7888         } mng_feature_cap_mask;
7889
7890         u8         reserved_at_1c0[0x80];
7891 };
7892
7893 struct mlx5_ifc_pcap_reg_bits {
7894         u8         reserved_at_0[0x8];
7895         u8         local_port[0x8];
7896         u8         reserved_at_10[0x10];
7897
7898         u8         port_capability_mask[4][0x20];
7899 };
7900
7901 struct mlx5_ifc_paos_reg_bits {
7902         u8         swid[0x8];
7903         u8         local_port[0x8];
7904         u8         reserved_at_10[0x4];
7905         u8         admin_status[0x4];
7906         u8         reserved_at_18[0x4];
7907         u8         oper_status[0x4];
7908
7909         u8         ase[0x1];
7910         u8         ee[0x1];
7911         u8         reserved_at_22[0x1c];
7912         u8         e[0x2];
7913
7914         u8         reserved_at_40[0x40];
7915 };
7916
7917 struct mlx5_ifc_pamp_reg_bits {
7918         u8         reserved_at_0[0x8];
7919         u8         opamp_group[0x8];
7920         u8         reserved_at_10[0xc];
7921         u8         opamp_group_type[0x4];
7922
7923         u8         start_index[0x10];
7924         u8         reserved_at_30[0x4];
7925         u8         num_of_indices[0xc];
7926
7927         u8         index_data[18][0x10];
7928 };
7929
7930 struct mlx5_ifc_pcmr_reg_bits {
7931         u8         reserved_at_0[0x8];
7932         u8         local_port[0x8];
7933         u8         reserved_at_10[0x2e];
7934         u8         fcs_cap[0x1];
7935         u8         reserved_at_3f[0x1f];
7936         u8         fcs_chk[0x1];
7937         u8         reserved_at_5f[0x1];
7938 };
7939
7940 struct mlx5_ifc_lane_2_module_mapping_bits {
7941         u8         reserved_at_0[0x6];
7942         u8         rx_lane[0x2];
7943         u8         reserved_at_8[0x6];
7944         u8         tx_lane[0x2];
7945         u8         reserved_at_10[0x8];
7946         u8         module[0x8];
7947 };
7948
7949 struct mlx5_ifc_bufferx_reg_bits {
7950         u8         reserved_at_0[0x6];
7951         u8         lossy[0x1];
7952         u8         epsb[0x1];
7953         u8         reserved_at_8[0xc];
7954         u8         size[0xc];
7955
7956         u8         xoff_threshold[0x10];
7957         u8         xon_threshold[0x10];
7958 };
7959
7960 struct mlx5_ifc_set_node_in_bits {
7961         u8         node_description[64][0x8];
7962 };
7963
7964 struct mlx5_ifc_register_power_settings_bits {
7965         u8         reserved_at_0[0x18];
7966         u8         power_settings_level[0x8];
7967
7968         u8         reserved_at_20[0x60];
7969 };
7970
7971 struct mlx5_ifc_register_host_endianness_bits {
7972         u8         he[0x1];
7973         u8         reserved_at_1[0x1f];
7974
7975         u8         reserved_at_20[0x60];
7976 };
7977
7978 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7979         u8         reserved_at_0[0x20];
7980
7981         u8         mkey[0x20];
7982
7983         u8         addressh_63_32[0x20];
7984
7985         u8         addressl_31_0[0x20];
7986 };
7987
7988 struct mlx5_ifc_ud_adrs_vector_bits {
7989         u8         dc_key[0x40];
7990
7991         u8         ext[0x1];
7992         u8         reserved_at_41[0x7];
7993         u8         destination_qp_dct[0x18];
7994
7995         u8         static_rate[0x4];
7996         u8         sl_eth_prio[0x4];
7997         u8         fl[0x1];
7998         u8         mlid[0x7];
7999         u8         rlid_udp_sport[0x10];
8000
8001         u8         reserved_at_80[0x20];
8002
8003         u8         rmac_47_16[0x20];
8004
8005         u8         rmac_15_0[0x10];
8006         u8         tclass[0x8];
8007         u8         hop_limit[0x8];
8008
8009         u8         reserved_at_e0[0x1];
8010         u8         grh[0x1];
8011         u8         reserved_at_e2[0x2];
8012         u8         src_addr_index[0x8];
8013         u8         flow_label[0x14];
8014
8015         u8         rgid_rip[16][0x8];
8016 };
8017
8018 struct mlx5_ifc_pages_req_event_bits {
8019         u8         reserved_at_0[0x10];
8020         u8         function_id[0x10];
8021
8022         u8         num_pages[0x20];
8023
8024         u8         reserved_at_40[0xa0];
8025 };
8026
8027 struct mlx5_ifc_eqe_bits {
8028         u8         reserved_at_0[0x8];
8029         u8         event_type[0x8];
8030         u8         reserved_at_10[0x8];
8031         u8         event_sub_type[0x8];
8032
8033         u8         reserved_at_20[0xe0];
8034
8035         union mlx5_ifc_event_auto_bits event_data;
8036
8037         u8         reserved_at_1e0[0x10];
8038         u8         signature[0x8];
8039         u8         reserved_at_1f8[0x7];
8040         u8         owner[0x1];
8041 };
8042
8043 enum {
8044         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8045 };
8046
8047 struct mlx5_ifc_cmd_queue_entry_bits {
8048         u8         type[0x8];
8049         u8         reserved_at_8[0x18];
8050
8051         u8         input_length[0x20];
8052
8053         u8         input_mailbox_pointer_63_32[0x20];
8054
8055         u8         input_mailbox_pointer_31_9[0x17];
8056         u8         reserved_at_77[0x9];
8057
8058         u8         command_input_inline_data[16][0x8];
8059
8060         u8         command_output_inline_data[16][0x8];
8061
8062         u8         output_mailbox_pointer_63_32[0x20];
8063
8064         u8         output_mailbox_pointer_31_9[0x17];
8065         u8         reserved_at_1b7[0x9];
8066
8067         u8         output_length[0x20];
8068
8069         u8         token[0x8];
8070         u8         signature[0x8];
8071         u8         reserved_at_1f0[0x8];
8072         u8         status[0x7];
8073         u8         ownership[0x1];
8074 };
8075
8076 struct mlx5_ifc_cmd_out_bits {
8077         u8         status[0x8];
8078         u8         reserved_at_8[0x18];
8079
8080         u8         syndrome[0x20];
8081
8082         u8         command_output[0x20];
8083 };
8084
8085 struct mlx5_ifc_cmd_in_bits {
8086         u8         opcode[0x10];
8087         u8         reserved_at_10[0x10];
8088
8089         u8         reserved_at_20[0x10];
8090         u8         op_mod[0x10];
8091
8092         u8         command[0][0x20];
8093 };
8094
8095 struct mlx5_ifc_cmd_if_box_bits {
8096         u8         mailbox_data[512][0x8];
8097
8098         u8         reserved_at_1000[0x180];
8099
8100         u8         next_pointer_63_32[0x20];
8101
8102         u8         next_pointer_31_10[0x16];
8103         u8         reserved_at_11b6[0xa];
8104
8105         u8         block_number[0x20];
8106
8107         u8         reserved_at_11e0[0x8];
8108         u8         token[0x8];
8109         u8         ctrl_signature[0x8];
8110         u8         signature[0x8];
8111 };
8112
8113 struct mlx5_ifc_mtt_bits {
8114         u8         ptag_63_32[0x20];
8115
8116         u8         ptag_31_8[0x18];
8117         u8         reserved_at_38[0x6];
8118         u8         wr_en[0x1];
8119         u8         rd_en[0x1];
8120 };
8121
8122 struct mlx5_ifc_query_wol_rol_out_bits {
8123         u8         status[0x8];
8124         u8         reserved_at_8[0x18];
8125
8126         u8         syndrome[0x20];
8127
8128         u8         reserved_at_40[0x10];
8129         u8         rol_mode[0x8];
8130         u8         wol_mode[0x8];
8131
8132         u8         reserved_at_60[0x20];
8133 };
8134
8135 struct mlx5_ifc_query_wol_rol_in_bits {
8136         u8         opcode[0x10];
8137         u8         reserved_at_10[0x10];
8138
8139         u8         reserved_at_20[0x10];
8140         u8         op_mod[0x10];
8141
8142         u8         reserved_at_40[0x40];
8143 };
8144
8145 struct mlx5_ifc_set_wol_rol_out_bits {
8146         u8         status[0x8];
8147         u8         reserved_at_8[0x18];
8148
8149         u8         syndrome[0x20];
8150
8151         u8         reserved_at_40[0x40];
8152 };
8153
8154 struct mlx5_ifc_set_wol_rol_in_bits {
8155         u8         opcode[0x10];
8156         u8         reserved_at_10[0x10];
8157
8158         u8         reserved_at_20[0x10];
8159         u8         op_mod[0x10];
8160
8161         u8         rol_mode_valid[0x1];
8162         u8         wol_mode_valid[0x1];
8163         u8         reserved_at_42[0xe];
8164         u8         rol_mode[0x8];
8165         u8         wol_mode[0x8];
8166
8167         u8         reserved_at_60[0x20];
8168 };
8169
8170 enum {
8171         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8172         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8173         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8174 };
8175
8176 enum {
8177         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8178         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8179         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8180 };
8181
8182 enum {
8183         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8184         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8185         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8186         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8187         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8188         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8189         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8190         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8191         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8192         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8193         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8194 };
8195
8196 struct mlx5_ifc_initial_seg_bits {
8197         u8         fw_rev_minor[0x10];
8198         u8         fw_rev_major[0x10];
8199
8200         u8         cmd_interface_rev[0x10];
8201         u8         fw_rev_subminor[0x10];
8202
8203         u8         reserved_at_40[0x40];
8204
8205         u8         cmdq_phy_addr_63_32[0x20];
8206
8207         u8         cmdq_phy_addr_31_12[0x14];
8208         u8         reserved_at_b4[0x2];
8209         u8         nic_interface[0x2];
8210         u8         log_cmdq_size[0x4];
8211         u8         log_cmdq_stride[0x4];
8212
8213         u8         command_doorbell_vector[0x20];
8214
8215         u8         reserved_at_e0[0xf00];
8216
8217         u8         initializing[0x1];
8218         u8         reserved_at_fe1[0x4];
8219         u8         nic_interface_supported[0x3];
8220         u8         reserved_at_fe8[0x18];
8221
8222         struct mlx5_ifc_health_buffer_bits health_buffer;
8223
8224         u8         no_dram_nic_offset[0x20];
8225
8226         u8         reserved_at_1220[0x6e40];
8227
8228         u8         reserved_at_8060[0x1f];
8229         u8         clear_int[0x1];
8230
8231         u8         health_syndrome[0x8];
8232         u8         health_counter[0x18];
8233
8234         u8         reserved_at_80a0[0x17fc0];
8235 };
8236
8237 struct mlx5_ifc_mtpps_reg_bits {
8238         u8         reserved_at_0[0xc];
8239         u8         cap_number_of_pps_pins[0x4];
8240         u8         reserved_at_10[0x4];
8241         u8         cap_max_num_of_pps_in_pins[0x4];
8242         u8         reserved_at_18[0x4];
8243         u8         cap_max_num_of_pps_out_pins[0x4];
8244
8245         u8         reserved_at_20[0x24];
8246         u8         cap_pin_3_mode[0x4];
8247         u8         reserved_at_48[0x4];
8248         u8         cap_pin_2_mode[0x4];
8249         u8         reserved_at_50[0x4];
8250         u8         cap_pin_1_mode[0x4];
8251         u8         reserved_at_58[0x4];
8252         u8         cap_pin_0_mode[0x4];
8253
8254         u8         reserved_at_60[0x4];
8255         u8         cap_pin_7_mode[0x4];
8256         u8         reserved_at_68[0x4];
8257         u8         cap_pin_6_mode[0x4];
8258         u8         reserved_at_70[0x4];
8259         u8         cap_pin_5_mode[0x4];
8260         u8         reserved_at_78[0x4];
8261         u8         cap_pin_4_mode[0x4];
8262
8263         u8         field_select[0x20];
8264         u8         reserved_at_a0[0x60];
8265
8266         u8         enable[0x1];
8267         u8         reserved_at_101[0xb];
8268         u8         pattern[0x4];
8269         u8         reserved_at_110[0x4];
8270         u8         pin_mode[0x4];
8271         u8         pin[0x8];
8272
8273         u8         reserved_at_120[0x20];
8274
8275         u8         time_stamp[0x40];
8276
8277         u8         out_pulse_duration[0x10];
8278         u8         out_periodic_adjustment[0x10];
8279         u8         enhanced_out_periodic_adjustment[0x20];
8280
8281         u8         reserved_at_1c0[0x20];
8282 };
8283
8284 struct mlx5_ifc_mtppse_reg_bits {
8285         u8         reserved_at_0[0x18];
8286         u8         pin[0x8];
8287         u8         event_arm[0x1];
8288         u8         reserved_at_21[0x1b];
8289         u8         event_generation_mode[0x4];
8290         u8         reserved_at_40[0x40];
8291 };
8292
8293 struct mlx5_ifc_mcqi_cap_bits {
8294         u8         supported_info_bitmask[0x20];
8295
8296         u8         component_size[0x20];
8297
8298         u8         max_component_size[0x20];
8299
8300         u8         log_mcda_word_size[0x4];
8301         u8         reserved_at_64[0xc];
8302         u8         mcda_max_write_size[0x10];
8303
8304         u8         rd_en[0x1];
8305         u8         reserved_at_81[0x1];
8306         u8         match_chip_id[0x1];
8307         u8         match_psid[0x1];
8308         u8         check_user_timestamp[0x1];
8309         u8         match_base_guid_mac[0x1];
8310         u8         reserved_at_86[0x1a];
8311 };
8312
8313 struct mlx5_ifc_mcqi_reg_bits {
8314         u8         read_pending_component[0x1];
8315         u8         reserved_at_1[0xf];
8316         u8         component_index[0x10];
8317
8318         u8         reserved_at_20[0x20];
8319
8320         u8         reserved_at_40[0x1b];
8321         u8         info_type[0x5];
8322
8323         u8         info_size[0x20];
8324
8325         u8         offset[0x20];
8326
8327         u8         reserved_at_a0[0x10];
8328         u8         data_size[0x10];
8329
8330         u8         data[0][0x20];
8331 };
8332
8333 struct mlx5_ifc_mcc_reg_bits {
8334         u8         reserved_at_0[0x4];
8335         u8         time_elapsed_since_last_cmd[0xc];
8336         u8         reserved_at_10[0x8];
8337         u8         instruction[0x8];
8338
8339         u8         reserved_at_20[0x10];
8340         u8         component_index[0x10];
8341
8342         u8         reserved_at_40[0x8];
8343         u8         update_handle[0x18];
8344
8345         u8         handle_owner_type[0x4];
8346         u8         handle_owner_host_id[0x4];
8347         u8         reserved_at_68[0x1];
8348         u8         control_progress[0x7];
8349         u8         error_code[0x8];
8350         u8         reserved_at_78[0x4];
8351         u8         control_state[0x4];
8352
8353         u8         component_size[0x20];
8354
8355         u8         reserved_at_a0[0x60];
8356 };
8357
8358 struct mlx5_ifc_mcda_reg_bits {
8359         u8         reserved_at_0[0x8];
8360         u8         update_handle[0x18];
8361
8362         u8         offset[0x20];
8363
8364         u8         reserved_at_40[0x10];
8365         u8         size[0x10];
8366
8367         u8         reserved_at_60[0x20];
8368
8369         u8         data[0][0x20];
8370 };
8371
8372 union mlx5_ifc_ports_control_registers_document_bits {
8373         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8374         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8375         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8376         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8377         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8378         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8379         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8380         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8381         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8382         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8383         struct mlx5_ifc_paos_reg_bits paos_reg;
8384         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8385         struct mlx5_ifc_peir_reg_bits peir_reg;
8386         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8387         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8388         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8389         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8390         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8391         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8392         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8393         struct mlx5_ifc_plib_reg_bits plib_reg;
8394         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8395         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8396         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8397         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8398         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8399         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8400         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8401         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8402         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8403         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8404         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8405         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8406         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8407         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8408         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8409         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8410         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8411         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8412         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8413         struct mlx5_ifc_pude_reg_bits pude_reg;
8414         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8415         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8416         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8417         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8418         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8419         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8420         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8421         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8422         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8423         struct mlx5_ifc_mcc_reg_bits mcc_reg;
8424         struct mlx5_ifc_mcda_reg_bits mcda_reg;
8425         u8         reserved_at_0[0x60e0];
8426 };
8427
8428 union mlx5_ifc_debug_enhancements_document_bits {
8429         struct mlx5_ifc_health_buffer_bits health_buffer;
8430         u8         reserved_at_0[0x200];
8431 };
8432
8433 union mlx5_ifc_uplink_pci_interface_document_bits {
8434         struct mlx5_ifc_initial_seg_bits initial_seg;
8435         u8         reserved_at_0[0x20060];
8436 };
8437
8438 struct mlx5_ifc_set_flow_table_root_out_bits {
8439         u8         status[0x8];
8440         u8         reserved_at_8[0x18];
8441
8442         u8         syndrome[0x20];
8443
8444         u8         reserved_at_40[0x40];
8445 };
8446
8447 struct mlx5_ifc_set_flow_table_root_in_bits {
8448         u8         opcode[0x10];
8449         u8         reserved_at_10[0x10];
8450
8451         u8         reserved_at_20[0x10];
8452         u8         op_mod[0x10];
8453
8454         u8         other_vport[0x1];
8455         u8         reserved_at_41[0xf];
8456         u8         vport_number[0x10];
8457
8458         u8         reserved_at_60[0x20];
8459
8460         u8         table_type[0x8];
8461         u8         reserved_at_88[0x18];
8462
8463         u8         reserved_at_a0[0x8];
8464         u8         table_id[0x18];
8465
8466         u8         reserved_at_c0[0x8];
8467         u8         underlay_qpn[0x18];
8468         u8         reserved_at_e0[0x120];
8469 };
8470
8471 enum {
8472         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8473         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8474 };
8475
8476 struct mlx5_ifc_modify_flow_table_out_bits {
8477         u8         status[0x8];
8478         u8         reserved_at_8[0x18];
8479
8480         u8         syndrome[0x20];
8481
8482         u8         reserved_at_40[0x40];
8483 };
8484
8485 struct mlx5_ifc_modify_flow_table_in_bits {
8486         u8         opcode[0x10];
8487         u8         reserved_at_10[0x10];
8488
8489         u8         reserved_at_20[0x10];
8490         u8         op_mod[0x10];
8491
8492         u8         other_vport[0x1];
8493         u8         reserved_at_41[0xf];
8494         u8         vport_number[0x10];
8495
8496         u8         reserved_at_60[0x10];
8497         u8         modify_field_select[0x10];
8498
8499         u8         table_type[0x8];
8500         u8         reserved_at_88[0x18];
8501
8502         u8         reserved_at_a0[0x8];
8503         u8         table_id[0x18];
8504
8505         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8506 };
8507
8508 struct mlx5_ifc_ets_tcn_config_reg_bits {
8509         u8         g[0x1];
8510         u8         b[0x1];
8511         u8         r[0x1];
8512         u8         reserved_at_3[0x9];
8513         u8         group[0x4];
8514         u8         reserved_at_10[0x9];
8515         u8         bw_allocation[0x7];
8516
8517         u8         reserved_at_20[0xc];
8518         u8         max_bw_units[0x4];
8519         u8         reserved_at_30[0x8];
8520         u8         max_bw_value[0x8];
8521 };
8522
8523 struct mlx5_ifc_ets_global_config_reg_bits {
8524         u8         reserved_at_0[0x2];
8525         u8         r[0x1];
8526         u8         reserved_at_3[0x1d];
8527
8528         u8         reserved_at_20[0xc];
8529         u8         max_bw_units[0x4];
8530         u8         reserved_at_30[0x8];
8531         u8         max_bw_value[0x8];
8532 };
8533
8534 struct mlx5_ifc_qetc_reg_bits {
8535         u8                                         reserved_at_0[0x8];
8536         u8                                         port_number[0x8];
8537         u8                                         reserved_at_10[0x30];
8538
8539         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8540         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8541 };
8542
8543 struct mlx5_ifc_qtct_reg_bits {
8544         u8         reserved_at_0[0x8];
8545         u8         port_number[0x8];
8546         u8         reserved_at_10[0xd];
8547         u8         prio[0x3];
8548
8549         u8         reserved_at_20[0x1d];
8550         u8         tclass[0x3];
8551 };
8552
8553 struct mlx5_ifc_mcia_reg_bits {
8554         u8         l[0x1];
8555         u8         reserved_at_1[0x7];
8556         u8         module[0x8];
8557         u8         reserved_at_10[0x8];
8558         u8         status[0x8];
8559
8560         u8         i2c_device_address[0x8];
8561         u8         page_number[0x8];
8562         u8         device_address[0x10];
8563
8564         u8         reserved_at_40[0x10];
8565         u8         size[0x10];
8566
8567         u8         reserved_at_60[0x20];
8568
8569         u8         dword_0[0x20];
8570         u8         dword_1[0x20];
8571         u8         dword_2[0x20];
8572         u8         dword_3[0x20];
8573         u8         dword_4[0x20];
8574         u8         dword_5[0x20];
8575         u8         dword_6[0x20];
8576         u8         dword_7[0x20];
8577         u8         dword_8[0x20];
8578         u8         dword_9[0x20];
8579         u8         dword_10[0x20];
8580         u8         dword_11[0x20];
8581 };
8582
8583 struct mlx5_ifc_dcbx_param_bits {
8584         u8         dcbx_cee_cap[0x1];
8585         u8         dcbx_ieee_cap[0x1];
8586         u8         dcbx_standby_cap[0x1];
8587         u8         reserved_at_0[0x5];
8588         u8         port_number[0x8];
8589         u8         reserved_at_10[0xa];
8590         u8         max_application_table_size[6];
8591         u8         reserved_at_20[0x15];
8592         u8         version_oper[0x3];
8593         u8         reserved_at_38[5];
8594         u8         version_admin[0x3];
8595         u8         willing_admin[0x1];
8596         u8         reserved_at_41[0x3];
8597         u8         pfc_cap_oper[0x4];
8598         u8         reserved_at_48[0x4];
8599         u8         pfc_cap_admin[0x4];
8600         u8         reserved_at_50[0x4];
8601         u8         num_of_tc_oper[0x4];
8602         u8         reserved_at_58[0x4];
8603         u8         num_of_tc_admin[0x4];
8604         u8         remote_willing[0x1];
8605         u8         reserved_at_61[3];
8606         u8         remote_pfc_cap[4];
8607         u8         reserved_at_68[0x14];
8608         u8         remote_num_of_tc[0x4];
8609         u8         reserved_at_80[0x18];
8610         u8         error[0x8];
8611         u8         reserved_at_a0[0x160];
8612 };
8613
8614 struct mlx5_ifc_lagc_bits {
8615         u8         reserved_at_0[0x1d];
8616         u8         lag_state[0x3];
8617
8618         u8         reserved_at_20[0x14];
8619         u8         tx_remap_affinity_2[0x4];
8620         u8         reserved_at_38[0x4];
8621         u8         tx_remap_affinity_1[0x4];
8622 };
8623
8624 struct mlx5_ifc_create_lag_out_bits {
8625         u8         status[0x8];
8626         u8         reserved_at_8[0x18];
8627
8628         u8         syndrome[0x20];
8629
8630         u8         reserved_at_40[0x40];
8631 };
8632
8633 struct mlx5_ifc_create_lag_in_bits {
8634         u8         opcode[0x10];
8635         u8         reserved_at_10[0x10];
8636
8637         u8         reserved_at_20[0x10];
8638         u8         op_mod[0x10];
8639
8640         struct mlx5_ifc_lagc_bits ctx;
8641 };
8642
8643 struct mlx5_ifc_modify_lag_out_bits {
8644         u8         status[0x8];
8645         u8         reserved_at_8[0x18];
8646
8647         u8         syndrome[0x20];
8648
8649         u8         reserved_at_40[0x40];
8650 };
8651
8652 struct mlx5_ifc_modify_lag_in_bits {
8653         u8         opcode[0x10];
8654         u8         reserved_at_10[0x10];
8655
8656         u8         reserved_at_20[0x10];
8657         u8         op_mod[0x10];
8658
8659         u8         reserved_at_40[0x20];
8660         u8         field_select[0x20];
8661
8662         struct mlx5_ifc_lagc_bits ctx;
8663 };
8664
8665 struct mlx5_ifc_query_lag_out_bits {
8666         u8         status[0x8];
8667         u8         reserved_at_8[0x18];
8668
8669         u8         syndrome[0x20];
8670
8671         u8         reserved_at_40[0x40];
8672
8673         struct mlx5_ifc_lagc_bits ctx;
8674 };
8675
8676 struct mlx5_ifc_query_lag_in_bits {
8677         u8         opcode[0x10];
8678         u8         reserved_at_10[0x10];
8679
8680         u8         reserved_at_20[0x10];
8681         u8         op_mod[0x10];
8682
8683         u8         reserved_at_40[0x40];
8684 };
8685
8686 struct mlx5_ifc_destroy_lag_out_bits {
8687         u8         status[0x8];
8688         u8         reserved_at_8[0x18];
8689
8690         u8         syndrome[0x20];
8691
8692         u8         reserved_at_40[0x40];
8693 };
8694
8695 struct mlx5_ifc_destroy_lag_in_bits {
8696         u8         opcode[0x10];
8697         u8         reserved_at_10[0x10];
8698
8699         u8         reserved_at_20[0x10];
8700         u8         op_mod[0x10];
8701
8702         u8         reserved_at_40[0x40];
8703 };
8704
8705 struct mlx5_ifc_create_vport_lag_out_bits {
8706         u8         status[0x8];
8707         u8         reserved_at_8[0x18];
8708
8709         u8         syndrome[0x20];
8710
8711         u8         reserved_at_40[0x40];
8712 };
8713
8714 struct mlx5_ifc_create_vport_lag_in_bits {
8715         u8         opcode[0x10];
8716         u8         reserved_at_10[0x10];
8717
8718         u8         reserved_at_20[0x10];
8719         u8         op_mod[0x10];
8720
8721         u8         reserved_at_40[0x40];
8722 };
8723
8724 struct mlx5_ifc_destroy_vport_lag_out_bits {
8725         u8         status[0x8];
8726         u8         reserved_at_8[0x18];
8727
8728         u8         syndrome[0x20];
8729
8730         u8         reserved_at_40[0x40];
8731 };
8732
8733 struct mlx5_ifc_destroy_vport_lag_in_bits {
8734         u8         opcode[0x10];
8735         u8         reserved_at_10[0x10];
8736
8737         u8         reserved_at_20[0x10];
8738         u8         op_mod[0x10];
8739
8740         u8         reserved_at_40[0x40];
8741 };
8742
8743 #endif /* MLX5_IFC_H */