2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
175 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
176 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
177 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
178 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
179 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
180 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
181 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
182 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
183 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
184 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
185 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
187 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
188 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
190 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
191 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
192 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
193 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
194 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
195 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
196 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
197 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
198 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
199 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
200 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
201 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
202 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
203 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
204 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
205 MLX5_CMD_OP_ALLOC_PD = 0x800,
206 MLX5_CMD_OP_DEALLOC_PD = 0x801,
207 MLX5_CMD_OP_ALLOC_UAR = 0x802,
208 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
209 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
210 MLX5_CMD_OP_ACCESS_REG = 0x805,
211 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
212 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
213 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
214 MLX5_CMD_OP_MAD_IFC = 0x50d,
215 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
216 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
217 MLX5_CMD_OP_NOP = 0x80d,
218 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
219 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
220 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
221 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
222 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
223 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
224 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
225 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
226 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
227 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
228 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
229 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
230 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
231 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
232 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
233 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
234 MLX5_CMD_OP_CREATE_LAG = 0x840,
235 MLX5_CMD_OP_MODIFY_LAG = 0x841,
236 MLX5_CMD_OP_QUERY_LAG = 0x842,
237 MLX5_CMD_OP_DESTROY_LAG = 0x843,
238 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
239 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
240 MLX5_CMD_OP_CREATE_TIR = 0x900,
241 MLX5_CMD_OP_MODIFY_TIR = 0x901,
242 MLX5_CMD_OP_DESTROY_TIR = 0x902,
243 MLX5_CMD_OP_QUERY_TIR = 0x903,
244 MLX5_CMD_OP_CREATE_SQ = 0x904,
245 MLX5_CMD_OP_MODIFY_SQ = 0x905,
246 MLX5_CMD_OP_DESTROY_SQ = 0x906,
247 MLX5_CMD_OP_QUERY_SQ = 0x907,
248 MLX5_CMD_OP_CREATE_RQ = 0x908,
249 MLX5_CMD_OP_MODIFY_RQ = 0x909,
250 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
251 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
252 MLX5_CMD_OP_QUERY_RQ = 0x90b,
253 MLX5_CMD_OP_CREATE_RMP = 0x90c,
254 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
255 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
256 MLX5_CMD_OP_QUERY_RMP = 0x90f,
257 MLX5_CMD_OP_CREATE_TIS = 0x912,
258 MLX5_CMD_OP_MODIFY_TIS = 0x913,
259 MLX5_CMD_OP_DESTROY_TIS = 0x914,
260 MLX5_CMD_OP_QUERY_TIS = 0x915,
261 MLX5_CMD_OP_CREATE_RQT = 0x916,
262 MLX5_CMD_OP_MODIFY_RQT = 0x917,
263 MLX5_CMD_OP_DESTROY_RQT = 0x918,
264 MLX5_CMD_OP_QUERY_RQT = 0x919,
265 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
266 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
267 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
268 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
269 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
270 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
271 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
272 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
273 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
274 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
275 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
276 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
277 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
278 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
279 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
280 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
281 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
282 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
283 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
284 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
285 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
286 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
287 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
288 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
289 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
290 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
291 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
292 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
293 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
294 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
295 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
296 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
297 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 /* Valid range for general commands that don't work over an object */
303 MLX5_CMD_OP_GENERAL_START = 0xb00,
304 MLX5_CMD_OP_GENERAL_END = 0xd00,
307 struct mlx5_ifc_flow_table_fields_supported_bits {
310 u8 outer_ether_type[0x1];
311 u8 outer_ip_version[0x1];
312 u8 outer_first_prio[0x1];
313 u8 outer_first_cfi[0x1];
314 u8 outer_first_vid[0x1];
315 u8 outer_ipv4_ttl[0x1];
316 u8 outer_second_prio[0x1];
317 u8 outer_second_cfi[0x1];
318 u8 outer_second_vid[0x1];
319 u8 reserved_at_b[0x1];
323 u8 outer_ip_protocol[0x1];
324 u8 outer_ip_ecn[0x1];
325 u8 outer_ip_dscp[0x1];
326 u8 outer_udp_sport[0x1];
327 u8 outer_udp_dport[0x1];
328 u8 outer_tcp_sport[0x1];
329 u8 outer_tcp_dport[0x1];
330 u8 outer_tcp_flags[0x1];
331 u8 outer_gre_protocol[0x1];
332 u8 outer_gre_key[0x1];
333 u8 outer_vxlan_vni[0x1];
334 u8 outer_geneve_vni[0x1];
335 u8 outer_geneve_oam[0x1];
336 u8 outer_geneve_protocol_type[0x1];
337 u8 outer_geneve_opt_len[0x1];
338 u8 reserved_at_1e[0x1];
339 u8 source_eswitch_port[0x1];
343 u8 inner_ether_type[0x1];
344 u8 inner_ip_version[0x1];
345 u8 inner_first_prio[0x1];
346 u8 inner_first_cfi[0x1];
347 u8 inner_first_vid[0x1];
348 u8 reserved_at_27[0x1];
349 u8 inner_second_prio[0x1];
350 u8 inner_second_cfi[0x1];
351 u8 inner_second_vid[0x1];
352 u8 reserved_at_2b[0x1];
356 u8 inner_ip_protocol[0x1];
357 u8 inner_ip_ecn[0x1];
358 u8 inner_ip_dscp[0x1];
359 u8 inner_udp_sport[0x1];
360 u8 inner_udp_dport[0x1];
361 u8 inner_tcp_sport[0x1];
362 u8 inner_tcp_dport[0x1];
363 u8 inner_tcp_flags[0x1];
364 u8 reserved_at_37[0x9];
366 u8 geneve_tlv_option_0_data[0x1];
367 u8 reserved_at_41[0x4];
368 u8 outer_first_mpls_over_udp[0x4];
369 u8 outer_first_mpls_over_gre[0x4];
370 u8 inner_first_mpls[0x4];
371 u8 outer_first_mpls[0x4];
372 u8 reserved_at_55[0x2];
373 u8 outer_esp_spi[0x1];
374 u8 reserved_at_58[0x2];
377 u8 reserved_at_5b[0x25];
380 struct mlx5_ifc_flow_table_prop_layout_bits {
382 u8 reserved_at_1[0x1];
383 u8 flow_counter[0x1];
384 u8 flow_modify_en[0x1];
386 u8 identified_miss_table_mode[0x1];
387 u8 flow_table_modify[0x1];
390 u8 reserved_at_9[0x1];
393 u8 reserved_at_c[0x1];
396 u8 reformat_and_vlan_action[0x1];
397 u8 reserved_at_10[0x1];
399 u8 reformat_l3_tunnel_to_l2[0x1];
400 u8 reformat_l2_to_l3_tunnel[0x1];
401 u8 reformat_and_modify_action[0x1];
402 u8 reserved_at_15[0x2];
403 u8 table_miss_action_domain[0x1];
404 u8 termination_table[0x1];
405 u8 reserved_at_19[0x7];
406 u8 reserved_at_20[0x2];
407 u8 log_max_ft_size[0x6];
408 u8 log_max_modify_header_context[0x8];
409 u8 max_modify_header_actions[0x8];
410 u8 max_ft_level[0x8];
412 u8 reserved_at_40[0x20];
414 u8 reserved_at_60[0x18];
415 u8 log_max_ft_num[0x8];
417 u8 reserved_at_80[0x18];
418 u8 log_max_destination[0x8];
420 u8 log_max_flow_counter[0x8];
421 u8 reserved_at_a8[0x10];
422 u8 log_max_flow[0x8];
424 u8 reserved_at_c0[0x40];
426 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
428 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
431 struct mlx5_ifc_odp_per_transport_service_cap_bits {
438 u8 reserved_at_6[0x1a];
441 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
466 u8 reserved_at_c0[0x18];
467 u8 ttl_hoplimit[0x8];
472 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
474 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
477 struct mlx5_ifc_nvgre_key_bits {
482 union mlx5_ifc_gre_key_bits {
483 struct mlx5_ifc_nvgre_key_bits nvgre;
487 struct mlx5_ifc_fte_match_set_misc_bits {
488 u8 reserved_at_0[0x8];
491 u8 source_eswitch_owner_vhca_id[0x10];
492 u8 source_port[0x10];
494 u8 outer_second_prio[0x3];
495 u8 outer_second_cfi[0x1];
496 u8 outer_second_vid[0xc];
497 u8 inner_second_prio[0x3];
498 u8 inner_second_cfi[0x1];
499 u8 inner_second_vid[0xc];
501 u8 outer_second_cvlan_tag[0x1];
502 u8 inner_second_cvlan_tag[0x1];
503 u8 outer_second_svlan_tag[0x1];
504 u8 inner_second_svlan_tag[0x1];
505 u8 reserved_at_64[0xc];
506 u8 gre_protocol[0x10];
508 union mlx5_ifc_gre_key_bits gre_key;
511 u8 reserved_at_b8[0x8];
514 u8 reserved_at_d8[0x7];
517 u8 reserved_at_e0[0xc];
518 u8 outer_ipv6_flow_label[0x14];
520 u8 reserved_at_100[0xc];
521 u8 inner_ipv6_flow_label[0x14];
523 u8 reserved_at_120[0xa];
524 u8 geneve_opt_len[0x6];
525 u8 geneve_protocol_type[0x10];
527 u8 reserved_at_140[0x8];
529 u8 reserved_at_160[0x20];
530 u8 outer_esp_spi[0x20];
531 u8 reserved_at_1a0[0x60];
534 struct mlx5_ifc_fte_match_mpls_bits {
541 struct mlx5_ifc_fte_match_set_misc2_bits {
542 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
544 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
546 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
548 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
550 u8 metadata_reg_c_7[0x20];
552 u8 metadata_reg_c_6[0x20];
554 u8 metadata_reg_c_5[0x20];
556 u8 metadata_reg_c_4[0x20];
558 u8 metadata_reg_c_3[0x20];
560 u8 metadata_reg_c_2[0x20];
562 u8 metadata_reg_c_1[0x20];
564 u8 metadata_reg_c_0[0x20];
566 u8 metadata_reg_a[0x20];
568 u8 reserved_at_1a0[0x60];
571 struct mlx5_ifc_fte_match_set_misc3_bits {
572 u8 reserved_at_0[0x120];
573 u8 geneve_tlv_option_0_data[0x20];
574 u8 reserved_at_140[0xc0];
577 struct mlx5_ifc_cmd_pas_bits {
581 u8 reserved_at_34[0xc];
584 struct mlx5_ifc_uint64_bits {
591 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
592 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
593 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
594 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
595 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
596 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
597 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
598 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
599 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
600 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
603 struct mlx5_ifc_ads_bits {
606 u8 reserved_at_2[0xe];
609 u8 reserved_at_20[0x8];
615 u8 reserved_at_45[0x3];
616 u8 src_addr_index[0x8];
617 u8 reserved_at_50[0x4];
621 u8 reserved_at_60[0x4];
625 u8 rgid_rip[16][0x8];
627 u8 reserved_at_100[0x4];
630 u8 reserved_at_106[0x1];
639 u8 vhca_port_num[0x8];
645 struct mlx5_ifc_flow_table_nic_cap_bits {
646 u8 nic_rx_multi_path_tirs[0x1];
647 u8 nic_rx_multi_path_tirs_fts[0x1];
648 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
649 u8 reserved_at_3[0x1d];
650 u8 encap_general_header[0x1];
651 u8 reserved_at_21[0xa];
652 u8 log_max_packet_reformat_context[0x5];
653 u8 reserved_at_30[0x6];
654 u8 max_encap_header_size[0xa];
655 u8 reserved_at_40[0x1c0];
657 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
659 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
661 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
663 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
665 u8 reserved_at_a00[0x200];
667 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
669 u8 reserved_at_e00[0x7200];
673 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
674 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
675 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
676 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
677 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
678 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
679 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
680 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
683 struct mlx5_ifc_flow_table_eswitch_cap_bits {
684 u8 fdb_to_vport_reg_c_id[0x8];
685 u8 reserved_at_8[0xf];
687 u8 reserved_at_18[0x2];
688 u8 multi_fdb_encap[0x1];
689 u8 reserved_at_1b[0x1];
690 u8 fdb_multi_path_to_table[0x1];
691 u8 reserved_at_1d[0x3];
693 u8 reserved_at_20[0x1e0];
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
697 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
699 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
701 u8 reserved_at_800[0x7800];
705 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
706 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
709 struct mlx5_ifc_e_switch_cap_bits {
710 u8 vport_svlan_strip[0x1];
711 u8 vport_cvlan_strip[0x1];
712 u8 vport_svlan_insert[0x1];
713 u8 vport_cvlan_insert_if_not_exist[0x1];
714 u8 vport_cvlan_insert_overwrite[0x1];
715 u8 reserved_at_5[0x3];
716 u8 esw_uplink_ingress_acl[0x1];
717 u8 reserved_at_9[0x10];
718 u8 esw_functions_changed[0x1];
719 u8 reserved_at_1a[0x1];
720 u8 ecpf_vport_exists[0x1];
721 u8 counter_eswitch_affinity[0x1];
722 u8 merged_eswitch[0x1];
723 u8 nic_vport_node_guid_modify[0x1];
724 u8 nic_vport_port_guid_modify[0x1];
726 u8 vxlan_encap_decap[0x1];
727 u8 nvgre_encap_decap[0x1];
728 u8 reserved_at_22[0x1];
729 u8 log_max_fdb_encap_uplink[0x5];
730 u8 reserved_at_21[0x3];
731 u8 log_max_packet_reformat_context[0x5];
733 u8 max_encap_header_size[0xa];
735 u8 reserved_at_40[0xb];
736 u8 log_max_esw_sf[0x5];
737 u8 esw_sf_base_id[0x10];
739 u8 reserved_at_60[0x7a0];
743 struct mlx5_ifc_qos_cap_bits {
744 u8 packet_pacing[0x1];
745 u8 esw_scheduling[0x1];
746 u8 esw_bw_share[0x1];
747 u8 esw_rate_limit[0x1];
748 u8 reserved_at_4[0x1];
749 u8 packet_pacing_burst_bound[0x1];
750 u8 packet_pacing_typical_size[0x1];
751 u8 reserved_at_7[0x19];
753 u8 reserved_at_20[0x20];
755 u8 packet_pacing_max_rate[0x20];
757 u8 packet_pacing_min_rate[0x20];
759 u8 reserved_at_80[0x10];
760 u8 packet_pacing_rate_table_size[0x10];
762 u8 esw_element_type[0x10];
763 u8 esw_tsar_type[0x10];
765 u8 reserved_at_c0[0x10];
766 u8 max_qos_para_vport[0x10];
768 u8 max_tsar_bw_share[0x20];
770 u8 reserved_at_100[0x700];
773 struct mlx5_ifc_debug_cap_bits {
774 u8 core_dump_general[0x1];
775 u8 core_dump_qp[0x1];
776 u8 reserved_at_2[0x1e];
778 u8 reserved_at_20[0x2];
779 u8 stall_detect[0x1];
780 u8 reserved_at_23[0x1d];
782 u8 reserved_at_40[0x7c0];
785 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
789 u8 lro_psh_flag[0x1];
790 u8 lro_time_stamp[0x1];
791 u8 reserved_at_5[0x2];
792 u8 wqe_vlan_insert[0x1];
793 u8 self_lb_en_modifiable[0x1];
794 u8 reserved_at_9[0x2];
796 u8 multi_pkt_send_wqe[0x2];
797 u8 wqe_inline_mode[0x2];
798 u8 rss_ind_tbl_cap[0x4];
801 u8 enhanced_multi_pkt_send_wqe[0x1];
802 u8 tunnel_lso_const_out_ip_id[0x1];
803 u8 reserved_at_1c[0x2];
804 u8 tunnel_stateless_gre[0x1];
805 u8 tunnel_stateless_vxlan[0x1];
810 u8 cqe_checksum_full[0x1];
811 u8 reserved_at_24[0x5];
812 u8 tunnel_stateless_ip_over_ip[0x1];
813 u8 reserved_at_2a[0x6];
814 u8 max_vxlan_udp_ports[0x8];
815 u8 reserved_at_38[0x6];
816 u8 max_geneve_opt_len[0x1];
817 u8 tunnel_stateless_geneve_rx[0x1];
819 u8 reserved_at_40[0x10];
820 u8 lro_min_mss_size[0x10];
822 u8 reserved_at_60[0x120];
824 u8 lro_timer_supported_periods[4][0x20];
826 u8 reserved_at_200[0x600];
829 struct mlx5_ifc_roce_cap_bits {
831 u8 reserved_at_1[0x1f];
833 u8 reserved_at_20[0x60];
835 u8 reserved_at_80[0xc];
837 u8 reserved_at_90[0x8];
838 u8 roce_version[0x8];
840 u8 reserved_at_a0[0x10];
841 u8 r_roce_dest_udp_port[0x10];
843 u8 r_roce_max_src_udp_port[0x10];
844 u8 r_roce_min_src_udp_port[0x10];
846 u8 reserved_at_e0[0x10];
847 u8 roce_address_table_size[0x10];
849 u8 reserved_at_100[0x700];
852 struct mlx5_ifc_device_mem_cap_bits {
854 u8 reserved_at_1[0x1f];
856 u8 reserved_at_20[0xb];
857 u8 log_min_memic_alloc_size[0x5];
858 u8 reserved_at_30[0x8];
859 u8 log_max_memic_addr_alignment[0x8];
861 u8 memic_bar_start_addr[0x40];
863 u8 memic_bar_size[0x20];
865 u8 max_memic_size[0x20];
867 u8 steering_sw_icm_start_address[0x40];
869 u8 reserved_at_100[0x8];
870 u8 log_header_modify_sw_icm_size[0x8];
871 u8 reserved_at_110[0x2];
872 u8 log_sw_icm_alloc_granularity[0x6];
873 u8 log_steering_sw_icm_size[0x8];
875 u8 reserved_at_120[0x20];
877 u8 header_modify_sw_icm_start_address[0x40];
879 u8 reserved_at_180[0x680];
882 struct mlx5_ifc_device_event_cap_bits {
883 u8 user_affiliated_events[4][0x40];
885 u8 user_unaffiliated_events[4][0x40];
889 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
890 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
891 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
892 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
893 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
894 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
895 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
896 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
897 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
901 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
902 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
903 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
904 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
905 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
906 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
907 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
908 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
909 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
912 struct mlx5_ifc_atomic_caps_bits {
913 u8 reserved_at_0[0x40];
915 u8 atomic_req_8B_endianness_mode[0x2];
916 u8 reserved_at_42[0x4];
917 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
919 u8 reserved_at_47[0x19];
921 u8 reserved_at_60[0x20];
923 u8 reserved_at_80[0x10];
924 u8 atomic_operations[0x10];
926 u8 reserved_at_a0[0x10];
927 u8 atomic_size_qp[0x10];
929 u8 reserved_at_c0[0x10];
930 u8 atomic_size_dc[0x10];
932 u8 reserved_at_e0[0x720];
935 struct mlx5_ifc_odp_cap_bits {
936 u8 reserved_at_0[0x40];
939 u8 reserved_at_41[0x1f];
941 u8 reserved_at_60[0x20];
943 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
945 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
947 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
949 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
951 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
953 u8 reserved_at_120[0x6E0];
956 struct mlx5_ifc_calc_op {
957 u8 reserved_at_0[0x10];
958 u8 reserved_at_10[0x9];
959 u8 op_swap_endianness[0x1];
968 struct mlx5_ifc_vector_calc_cap_bits {
970 u8 reserved_at_1[0x1f];
971 u8 reserved_at_20[0x8];
972 u8 max_vec_count[0x8];
973 u8 reserved_at_30[0xd];
974 u8 max_chunk_size[0x3];
975 struct mlx5_ifc_calc_op calc0;
976 struct mlx5_ifc_calc_op calc1;
977 struct mlx5_ifc_calc_op calc2;
978 struct mlx5_ifc_calc_op calc3;
980 u8 reserved_at_c0[0x720];
983 struct mlx5_ifc_tls_cap_bits {
984 u8 tls_1_2_aes_gcm_128[0x1];
985 u8 tls_1_3_aes_gcm_128[0x1];
986 u8 tls_1_2_aes_gcm_256[0x1];
987 u8 tls_1_3_aes_gcm_256[0x1];
988 u8 reserved_at_4[0x1c];
990 u8 reserved_at_20[0x7e0];
994 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
995 MLX5_WQ_TYPE_CYCLIC = 0x1,
996 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
997 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1001 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1002 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1006 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1007 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1008 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1009 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1010 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1014 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1015 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1016 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1017 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1018 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1019 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1023 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1024 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1028 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1029 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1030 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1034 MLX5_CAP_PORT_TYPE_IB = 0x0,
1035 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1039 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1040 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1041 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1045 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1046 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1049 #define MLX5_FC_BULK_SIZE_FACTOR 128
1051 enum mlx5_fc_bulk_alloc_bitmask {
1052 MLX5_FC_BULK_128 = (1 << 0),
1053 MLX5_FC_BULK_256 = (1 << 1),
1054 MLX5_FC_BULK_512 = (1 << 2),
1055 MLX5_FC_BULK_1024 = (1 << 3),
1056 MLX5_FC_BULK_2048 = (1 << 4),
1057 MLX5_FC_BULK_4096 = (1 << 5),
1058 MLX5_FC_BULK_8192 = (1 << 6),
1059 MLX5_FC_BULK_16384 = (1 << 7),
1062 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1064 struct mlx5_ifc_cmd_hca_cap_bits {
1065 u8 reserved_at_0[0x30];
1068 u8 reserved_at_40[0x40];
1070 u8 log_max_srq_sz[0x8];
1071 u8 log_max_qp_sz[0x8];
1073 u8 reserved_at_91[0x7];
1074 u8 prio_tag_required[0x1];
1075 u8 reserved_at_99[0x2];
1078 u8 reserved_at_a0[0xb];
1079 u8 log_max_srq[0x5];
1080 u8 reserved_at_b0[0x10];
1082 u8 reserved_at_c0[0x8];
1083 u8 log_max_cq_sz[0x8];
1084 u8 reserved_at_d0[0xb];
1087 u8 log_max_eq_sz[0x8];
1088 u8 reserved_at_e8[0x2];
1089 u8 log_max_mkey[0x6];
1090 u8 reserved_at_f0[0x8];
1091 u8 dump_fill_mkey[0x1];
1092 u8 reserved_at_f9[0x2];
1093 u8 fast_teardown[0x1];
1096 u8 max_indirection[0x8];
1097 u8 fixed_buffer_size[0x1];
1098 u8 log_max_mrw_sz[0x7];
1099 u8 force_teardown[0x1];
1100 u8 reserved_at_111[0x1];
1101 u8 log_max_bsf_list_size[0x6];
1102 u8 umr_extended_translation_offset[0x1];
1104 u8 log_max_klm_list_size[0x6];
1106 u8 reserved_at_120[0xa];
1107 u8 log_max_ra_req_dc[0x6];
1108 u8 reserved_at_130[0xa];
1109 u8 log_max_ra_res_dc[0x6];
1111 u8 reserved_at_140[0xa];
1112 u8 log_max_ra_req_qp[0x6];
1113 u8 reserved_at_150[0xa];
1114 u8 log_max_ra_res_qp[0x6];
1117 u8 cc_query_allowed[0x1];
1118 u8 cc_modify_allowed[0x1];
1120 u8 cache_line_128byte[0x1];
1121 u8 reserved_at_165[0x4];
1122 u8 rts2rts_qp_counters_set_id[0x1];
1123 u8 reserved_at_16a[0x2];
1124 u8 vnic_env_int_rq_oob[0x1];
1125 u8 reserved_at_16d[0x2];
1127 u8 gid_table_size[0x10];
1129 u8 out_of_seq_cnt[0x1];
1130 u8 vport_counters[0x1];
1131 u8 retransmission_q_counters[0x1];
1133 u8 modify_rq_counter_set_id[0x1];
1134 u8 rq_delay_drop[0x1];
1136 u8 pkey_table_size[0x10];
1138 u8 vport_group_manager[0x1];
1139 u8 vhca_group_manager[0x1];
1142 u8 vnic_env_queue_counters[0x1];
1144 u8 nic_flow_table[0x1];
1145 u8 eswitch_manager[0x1];
1146 u8 device_memory[0x1];
1149 u8 local_ca_ack_delay[0x5];
1150 u8 port_module_event[0x1];
1151 u8 enhanced_error_q_counters[0x1];
1152 u8 ports_check[0x1];
1153 u8 reserved_at_1b3[0x1];
1154 u8 disable_link_up[0x1];
1159 u8 reserved_at_1c0[0x1];
1162 u8 log_max_msg[0x5];
1163 u8 reserved_at_1c8[0x4];
1165 u8 temp_warn_event[0x1];
1167 u8 general_notification_event[0x1];
1168 u8 reserved_at_1d3[0x2];
1172 u8 reserved_at_1d8[0x1];
1181 u8 stat_rate_support[0x10];
1182 u8 reserved_at_1f0[0xc];
1183 u8 cqe_version[0x4];
1185 u8 compact_address_vector[0x1];
1186 u8 striding_rq[0x1];
1187 u8 reserved_at_202[0x1];
1188 u8 ipoib_enhanced_offloads[0x1];
1189 u8 ipoib_basic_offloads[0x1];
1190 u8 reserved_at_205[0x1];
1191 u8 repeated_block_disabled[0x1];
1192 u8 umr_modify_entity_size_disabled[0x1];
1193 u8 umr_modify_atomic_disabled[0x1];
1194 u8 umr_indirect_mkey_disabled[0x1];
1196 u8 dc_req_scat_data_cqe[0x1];
1197 u8 reserved_at_20d[0x2];
1198 u8 drain_sigerr[0x1];
1199 u8 cmdif_checksum[0x2];
1201 u8 reserved_at_213[0x1];
1202 u8 wq_signature[0x1];
1203 u8 sctr_data_cqe[0x1];
1204 u8 reserved_at_216[0x1];
1210 u8 eth_net_offloads[0x1];
1213 u8 reserved_at_21f[0x1];
1217 u8 cq_moderation[0x1];
1218 u8 reserved_at_223[0x3];
1219 u8 cq_eq_remap[0x1];
1221 u8 block_lb_mc[0x1];
1222 u8 reserved_at_229[0x1];
1223 u8 scqe_break_moderation[0x1];
1224 u8 cq_period_start_from_cqe[0x1];
1226 u8 reserved_at_22d[0x1];
1228 u8 vector_calc[0x1];
1229 u8 umr_ptr_rlky[0x1];
1231 u8 qp_packet_based[0x1];
1232 u8 reserved_at_233[0x3];
1235 u8 set_deth_sqpn[0x1];
1236 u8 reserved_at_239[0x3];
1243 u8 reserved_at_241[0x9];
1245 u8 reserved_at_250[0x8];
1249 u8 driver_version[0x1];
1250 u8 pad_tx_eth_packet[0x1];
1251 u8 reserved_at_263[0x8];
1252 u8 log_bf_reg_size[0x5];
1254 u8 reserved_at_270[0x8];
1255 u8 lag_tx_port_affinity[0x1];
1256 u8 reserved_at_279[0x2];
1258 u8 num_lag_ports[0x4];
1260 u8 reserved_at_280[0x10];
1261 u8 max_wqe_sz_sq[0x10];
1263 u8 reserved_at_2a0[0x10];
1264 u8 max_wqe_sz_rq[0x10];
1266 u8 max_flow_counter_31_16[0x10];
1267 u8 max_wqe_sz_sq_dc[0x10];
1269 u8 reserved_at_2e0[0x7];
1270 u8 max_qp_mcg[0x19];
1272 u8 reserved_at_300[0x10];
1273 u8 flow_counter_bulk_alloc[0x8];
1274 u8 log_max_mcg[0x8];
1276 u8 reserved_at_320[0x3];
1277 u8 log_max_transport_domain[0x5];
1278 u8 reserved_at_328[0x3];
1280 u8 reserved_at_330[0xb];
1281 u8 log_max_xrcd[0x5];
1283 u8 nic_receive_steering_discard[0x1];
1284 u8 receive_discard_vport_down[0x1];
1285 u8 transmit_discard_vport_down[0x1];
1286 u8 reserved_at_343[0x5];
1287 u8 log_max_flow_counter_bulk[0x8];
1288 u8 max_flow_counter_15_0[0x10];
1291 u8 reserved_at_360[0x3];
1293 u8 reserved_at_368[0x3];
1295 u8 reserved_at_370[0x3];
1296 u8 log_max_tir[0x5];
1297 u8 reserved_at_378[0x3];
1298 u8 log_max_tis[0x5];
1300 u8 basic_cyclic_rcv_wqe[0x1];
1301 u8 reserved_at_381[0x2];
1302 u8 log_max_rmp[0x5];
1303 u8 reserved_at_388[0x3];
1304 u8 log_max_rqt[0x5];
1305 u8 reserved_at_390[0x3];
1306 u8 log_max_rqt_size[0x5];
1307 u8 reserved_at_398[0x3];
1308 u8 log_max_tis_per_sq[0x5];
1310 u8 ext_stride_num_range[0x1];
1311 u8 reserved_at_3a1[0x2];
1312 u8 log_max_stride_sz_rq[0x5];
1313 u8 reserved_at_3a8[0x3];
1314 u8 log_min_stride_sz_rq[0x5];
1315 u8 reserved_at_3b0[0x3];
1316 u8 log_max_stride_sz_sq[0x5];
1317 u8 reserved_at_3b8[0x3];
1318 u8 log_min_stride_sz_sq[0x5];
1321 u8 reserved_at_3c1[0x2];
1322 u8 log_max_hairpin_queues[0x5];
1323 u8 reserved_at_3c8[0x3];
1324 u8 log_max_hairpin_wq_data_sz[0x5];
1325 u8 reserved_at_3d0[0x3];
1326 u8 log_max_hairpin_num_packets[0x5];
1327 u8 reserved_at_3d8[0x3];
1328 u8 log_max_wq_sz[0x5];
1330 u8 nic_vport_change_event[0x1];
1331 u8 disable_local_lb_uc[0x1];
1332 u8 disable_local_lb_mc[0x1];
1333 u8 log_min_hairpin_wq_data_sz[0x5];
1334 u8 reserved_at_3e8[0x3];
1335 u8 log_max_vlan_list[0x5];
1336 u8 reserved_at_3f0[0x3];
1337 u8 log_max_current_mc_list[0x5];
1338 u8 reserved_at_3f8[0x3];
1339 u8 log_max_current_uc_list[0x5];
1341 u8 general_obj_types[0x40];
1343 u8 reserved_at_440[0x20];
1346 u8 reserved_at_461[0x2];
1347 u8 log_max_uctx[0x5];
1348 u8 reserved_at_468[0x3];
1349 u8 log_max_umem[0x5];
1350 u8 max_num_eqs[0x10];
1352 u8 reserved_at_480[0x3];
1353 u8 log_max_l2_table[0x5];
1354 u8 reserved_at_488[0x8];
1355 u8 log_uar_page_sz[0x10];
1357 u8 reserved_at_4a0[0x20];
1358 u8 device_frequency_mhz[0x20];
1359 u8 device_frequency_khz[0x20];
1361 u8 reserved_at_500[0x20];
1362 u8 num_of_uars_per_page[0x20];
1364 u8 flex_parser_protocols[0x20];
1366 u8 max_geneve_tlv_options[0x8];
1367 u8 reserved_at_568[0x3];
1368 u8 max_geneve_tlv_option_data_len[0x5];
1369 u8 reserved_at_570[0x10];
1371 u8 reserved_at_580[0x33];
1372 u8 log_max_dek[0x5];
1373 u8 reserved_at_5b8[0x4];
1374 u8 mini_cqe_resp_stride_index[0x1];
1375 u8 cqe_128_always[0x1];
1376 u8 cqe_compression_128[0x1];
1377 u8 cqe_compression[0x1];
1379 u8 cqe_compression_timeout[0x10];
1380 u8 cqe_compression_max_num[0x10];
1382 u8 reserved_at_5e0[0x10];
1383 u8 tag_matching[0x1];
1384 u8 rndv_offload_rc[0x1];
1385 u8 rndv_offload_dc[0x1];
1386 u8 log_tag_matching_list_sz[0x5];
1387 u8 reserved_at_5f8[0x3];
1388 u8 log_max_xrq[0x5];
1390 u8 affiliate_nic_vport_criteria[0x8];
1391 u8 native_port_num[0x8];
1392 u8 num_vhca_ports[0x8];
1393 u8 reserved_at_618[0x6];
1394 u8 sw_owner_id[0x1];
1395 u8 reserved_at_61f[0x1];
1397 u8 max_num_of_monitor_counters[0x10];
1398 u8 num_ppcnt_monitor_counters[0x10];
1400 u8 reserved_at_640[0x10];
1401 u8 num_q_monitor_counters[0x10];
1403 u8 reserved_at_660[0x20];
1406 u8 sf_set_partition[0x1];
1407 u8 reserved_at_682[0x1];
1409 u8 reserved_at_688[0x8];
1410 u8 log_min_sf_size[0x8];
1411 u8 max_num_sf_partitions[0x8];
1415 u8 reserved_at_6c0[0x4];
1416 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1417 u8 reserved_at_6c8[0x28];
1418 u8 sf_base_id[0x10];
1420 u8 reserved_at_700[0x80];
1421 u8 vhca_tunnel_commands[0x40];
1422 u8 reserved_at_7c0[0x40];
1425 enum mlx5_flow_destination_type {
1426 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1427 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1428 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1430 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1431 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1432 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1435 enum mlx5_flow_table_miss_action {
1436 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1437 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1438 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1441 struct mlx5_ifc_dest_format_struct_bits {
1442 u8 destination_type[0x8];
1443 u8 destination_id[0x18];
1445 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1446 u8 packet_reformat[0x1];
1447 u8 reserved_at_22[0xe];
1448 u8 destination_eswitch_owner_vhca_id[0x10];
1451 struct mlx5_ifc_flow_counter_list_bits {
1452 u8 flow_counter_id[0x20];
1454 u8 reserved_at_20[0x20];
1457 struct mlx5_ifc_extended_dest_format_bits {
1458 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1460 u8 packet_reformat_id[0x20];
1462 u8 reserved_at_60[0x20];
1465 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1466 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1467 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1468 u8 reserved_at_0[0x40];
1471 struct mlx5_ifc_fte_match_param_bits {
1472 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1474 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1476 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1478 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1480 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1482 u8 reserved_at_a00[0x600];
1486 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1487 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1488 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1489 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1490 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1493 struct mlx5_ifc_rx_hash_field_select_bits {
1494 u8 l3_prot_type[0x1];
1495 u8 l4_prot_type[0x1];
1496 u8 selected_fields[0x1e];
1500 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1501 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1505 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1506 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1509 struct mlx5_ifc_wq_bits {
1511 u8 wq_signature[0x1];
1512 u8 end_padding_mode[0x2];
1514 u8 reserved_at_8[0x18];
1516 u8 hds_skip_first_sge[0x1];
1517 u8 log2_hds_buf_size[0x3];
1518 u8 reserved_at_24[0x7];
1519 u8 page_offset[0x5];
1522 u8 reserved_at_40[0x8];
1525 u8 reserved_at_60[0x8];
1530 u8 hw_counter[0x20];
1532 u8 sw_counter[0x20];
1534 u8 reserved_at_100[0xc];
1535 u8 log_wq_stride[0x4];
1536 u8 reserved_at_110[0x3];
1537 u8 log_wq_pg_sz[0x5];
1538 u8 reserved_at_118[0x3];
1541 u8 dbr_umem_valid[0x1];
1542 u8 wq_umem_valid[0x1];
1543 u8 reserved_at_122[0x1];
1544 u8 log_hairpin_num_packets[0x5];
1545 u8 reserved_at_128[0x3];
1546 u8 log_hairpin_data_sz[0x5];
1548 u8 reserved_at_130[0x4];
1549 u8 log_wqe_num_of_strides[0x4];
1550 u8 two_byte_shift_en[0x1];
1551 u8 reserved_at_139[0x4];
1552 u8 log_wqe_stride_size[0x3];
1554 u8 reserved_at_140[0x4c0];
1556 struct mlx5_ifc_cmd_pas_bits pas[0];
1559 struct mlx5_ifc_rq_num_bits {
1560 u8 reserved_at_0[0x8];
1564 struct mlx5_ifc_mac_address_layout_bits {
1565 u8 reserved_at_0[0x10];
1566 u8 mac_addr_47_32[0x10];
1568 u8 mac_addr_31_0[0x20];
1571 struct mlx5_ifc_vlan_layout_bits {
1572 u8 reserved_at_0[0x14];
1575 u8 reserved_at_20[0x20];
1578 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1579 u8 reserved_at_0[0xa0];
1581 u8 min_time_between_cnps[0x20];
1583 u8 reserved_at_c0[0x12];
1585 u8 reserved_at_d8[0x4];
1586 u8 cnp_prio_mode[0x1];
1587 u8 cnp_802p_prio[0x3];
1589 u8 reserved_at_e0[0x720];
1592 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1593 u8 reserved_at_0[0x60];
1595 u8 reserved_at_60[0x4];
1596 u8 clamp_tgt_rate[0x1];
1597 u8 reserved_at_65[0x3];
1598 u8 clamp_tgt_rate_after_time_inc[0x1];
1599 u8 reserved_at_69[0x17];
1601 u8 reserved_at_80[0x20];
1603 u8 rpg_time_reset[0x20];
1605 u8 rpg_byte_reset[0x20];
1607 u8 rpg_threshold[0x20];
1609 u8 rpg_max_rate[0x20];
1611 u8 rpg_ai_rate[0x20];
1613 u8 rpg_hai_rate[0x20];
1617 u8 rpg_min_dec_fac[0x20];
1619 u8 rpg_min_rate[0x20];
1621 u8 reserved_at_1c0[0xe0];
1623 u8 rate_to_set_on_first_cnp[0x20];
1627 u8 dce_tcp_rtt[0x20];
1629 u8 rate_reduce_monitor_period[0x20];
1631 u8 reserved_at_320[0x20];
1633 u8 initial_alpha_value[0x20];
1635 u8 reserved_at_360[0x4a0];
1638 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1639 u8 reserved_at_0[0x80];
1641 u8 rppp_max_rps[0x20];
1643 u8 rpg_time_reset[0x20];
1645 u8 rpg_byte_reset[0x20];
1647 u8 rpg_threshold[0x20];
1649 u8 rpg_max_rate[0x20];
1651 u8 rpg_ai_rate[0x20];
1653 u8 rpg_hai_rate[0x20];
1657 u8 rpg_min_dec_fac[0x20];
1659 u8 rpg_min_rate[0x20];
1661 u8 reserved_at_1c0[0x640];
1665 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1666 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1667 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1670 struct mlx5_ifc_resize_field_select_bits {
1671 u8 resize_field_select[0x20];
1675 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1676 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1677 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1678 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1681 struct mlx5_ifc_modify_field_select_bits {
1682 u8 modify_field_select[0x20];
1685 struct mlx5_ifc_field_select_r_roce_np_bits {
1686 u8 field_select_r_roce_np[0x20];
1689 struct mlx5_ifc_field_select_r_roce_rp_bits {
1690 u8 field_select_r_roce_rp[0x20];
1694 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1695 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1696 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1697 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1698 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1699 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1700 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1701 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1702 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1703 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1706 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1707 u8 field_select_8021qaurp[0x20];
1710 struct mlx5_ifc_phys_layer_cntrs_bits {
1711 u8 time_since_last_clear_high[0x20];
1713 u8 time_since_last_clear_low[0x20];
1715 u8 symbol_errors_high[0x20];
1717 u8 symbol_errors_low[0x20];
1719 u8 sync_headers_errors_high[0x20];
1721 u8 sync_headers_errors_low[0x20];
1723 u8 edpl_bip_errors_lane0_high[0x20];
1725 u8 edpl_bip_errors_lane0_low[0x20];
1727 u8 edpl_bip_errors_lane1_high[0x20];
1729 u8 edpl_bip_errors_lane1_low[0x20];
1731 u8 edpl_bip_errors_lane2_high[0x20];
1733 u8 edpl_bip_errors_lane2_low[0x20];
1735 u8 edpl_bip_errors_lane3_high[0x20];
1737 u8 edpl_bip_errors_lane3_low[0x20];
1739 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1741 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1743 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1745 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1747 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1749 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1751 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1753 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1755 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1757 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1759 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1761 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1763 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1765 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1767 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1769 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1771 u8 rs_fec_corrected_blocks_high[0x20];
1773 u8 rs_fec_corrected_blocks_low[0x20];
1775 u8 rs_fec_uncorrectable_blocks_high[0x20];
1777 u8 rs_fec_uncorrectable_blocks_low[0x20];
1779 u8 rs_fec_no_errors_blocks_high[0x20];
1781 u8 rs_fec_no_errors_blocks_low[0x20];
1783 u8 rs_fec_single_error_blocks_high[0x20];
1785 u8 rs_fec_single_error_blocks_low[0x20];
1787 u8 rs_fec_corrected_symbols_total_high[0x20];
1789 u8 rs_fec_corrected_symbols_total_low[0x20];
1791 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1793 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1795 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1797 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1799 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1801 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1803 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1805 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1807 u8 link_down_events[0x20];
1809 u8 successful_recovery_events[0x20];
1811 u8 reserved_at_640[0x180];
1814 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1815 u8 time_since_last_clear_high[0x20];
1817 u8 time_since_last_clear_low[0x20];
1819 u8 phy_received_bits_high[0x20];
1821 u8 phy_received_bits_low[0x20];
1823 u8 phy_symbol_errors_high[0x20];
1825 u8 phy_symbol_errors_low[0x20];
1827 u8 phy_corrected_bits_high[0x20];
1829 u8 phy_corrected_bits_low[0x20];
1831 u8 phy_corrected_bits_lane0_high[0x20];
1833 u8 phy_corrected_bits_lane0_low[0x20];
1835 u8 phy_corrected_bits_lane1_high[0x20];
1837 u8 phy_corrected_bits_lane1_low[0x20];
1839 u8 phy_corrected_bits_lane2_high[0x20];
1841 u8 phy_corrected_bits_lane2_low[0x20];
1843 u8 phy_corrected_bits_lane3_high[0x20];
1845 u8 phy_corrected_bits_lane3_low[0x20];
1847 u8 reserved_at_200[0x5c0];
1850 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1851 u8 symbol_error_counter[0x10];
1853 u8 link_error_recovery_counter[0x8];
1855 u8 link_downed_counter[0x8];
1857 u8 port_rcv_errors[0x10];
1859 u8 port_rcv_remote_physical_errors[0x10];
1861 u8 port_rcv_switch_relay_errors[0x10];
1863 u8 port_xmit_discards[0x10];
1865 u8 port_xmit_constraint_errors[0x8];
1867 u8 port_rcv_constraint_errors[0x8];
1869 u8 reserved_at_70[0x8];
1871 u8 link_overrun_errors[0x8];
1873 u8 reserved_at_80[0x10];
1875 u8 vl_15_dropped[0x10];
1877 u8 reserved_at_a0[0x80];
1879 u8 port_xmit_wait[0x20];
1882 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1883 u8 transmit_queue_high[0x20];
1885 u8 transmit_queue_low[0x20];
1887 u8 reserved_at_40[0x780];
1890 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1891 u8 rx_octets_high[0x20];
1893 u8 rx_octets_low[0x20];
1895 u8 reserved_at_40[0xc0];
1897 u8 rx_frames_high[0x20];
1899 u8 rx_frames_low[0x20];
1901 u8 tx_octets_high[0x20];
1903 u8 tx_octets_low[0x20];
1905 u8 reserved_at_180[0xc0];
1907 u8 tx_frames_high[0x20];
1909 u8 tx_frames_low[0x20];
1911 u8 rx_pause_high[0x20];
1913 u8 rx_pause_low[0x20];
1915 u8 rx_pause_duration_high[0x20];
1917 u8 rx_pause_duration_low[0x20];
1919 u8 tx_pause_high[0x20];
1921 u8 tx_pause_low[0x20];
1923 u8 tx_pause_duration_high[0x20];
1925 u8 tx_pause_duration_low[0x20];
1927 u8 rx_pause_transition_high[0x20];
1929 u8 rx_pause_transition_low[0x20];
1931 u8 reserved_at_3c0[0x40];
1933 u8 device_stall_minor_watermark_cnt_high[0x20];
1935 u8 device_stall_minor_watermark_cnt_low[0x20];
1937 u8 device_stall_critical_watermark_cnt_high[0x20];
1939 u8 device_stall_critical_watermark_cnt_low[0x20];
1941 u8 reserved_at_480[0x340];
1944 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1945 u8 port_transmit_wait_high[0x20];
1947 u8 port_transmit_wait_low[0x20];
1949 u8 reserved_at_40[0x100];
1951 u8 rx_buffer_almost_full_high[0x20];
1953 u8 rx_buffer_almost_full_low[0x20];
1955 u8 rx_buffer_full_high[0x20];
1957 u8 rx_buffer_full_low[0x20];
1959 u8 rx_icrc_encapsulated_high[0x20];
1961 u8 rx_icrc_encapsulated_low[0x20];
1963 u8 reserved_at_200[0x5c0];
1966 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1967 u8 dot3stats_alignment_errors_high[0x20];
1969 u8 dot3stats_alignment_errors_low[0x20];
1971 u8 dot3stats_fcs_errors_high[0x20];
1973 u8 dot3stats_fcs_errors_low[0x20];
1975 u8 dot3stats_single_collision_frames_high[0x20];
1977 u8 dot3stats_single_collision_frames_low[0x20];
1979 u8 dot3stats_multiple_collision_frames_high[0x20];
1981 u8 dot3stats_multiple_collision_frames_low[0x20];
1983 u8 dot3stats_sqe_test_errors_high[0x20];
1985 u8 dot3stats_sqe_test_errors_low[0x20];
1987 u8 dot3stats_deferred_transmissions_high[0x20];
1989 u8 dot3stats_deferred_transmissions_low[0x20];
1991 u8 dot3stats_late_collisions_high[0x20];
1993 u8 dot3stats_late_collisions_low[0x20];
1995 u8 dot3stats_excessive_collisions_high[0x20];
1997 u8 dot3stats_excessive_collisions_low[0x20];
1999 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2001 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2003 u8 dot3stats_carrier_sense_errors_high[0x20];
2005 u8 dot3stats_carrier_sense_errors_low[0x20];
2007 u8 dot3stats_frame_too_longs_high[0x20];
2009 u8 dot3stats_frame_too_longs_low[0x20];
2011 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2013 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2015 u8 dot3stats_symbol_errors_high[0x20];
2017 u8 dot3stats_symbol_errors_low[0x20];
2019 u8 dot3control_in_unknown_opcodes_high[0x20];
2021 u8 dot3control_in_unknown_opcodes_low[0x20];
2023 u8 dot3in_pause_frames_high[0x20];
2025 u8 dot3in_pause_frames_low[0x20];
2027 u8 dot3out_pause_frames_high[0x20];
2029 u8 dot3out_pause_frames_low[0x20];
2031 u8 reserved_at_400[0x3c0];
2034 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2035 u8 ether_stats_drop_events_high[0x20];
2037 u8 ether_stats_drop_events_low[0x20];
2039 u8 ether_stats_octets_high[0x20];
2041 u8 ether_stats_octets_low[0x20];
2043 u8 ether_stats_pkts_high[0x20];
2045 u8 ether_stats_pkts_low[0x20];
2047 u8 ether_stats_broadcast_pkts_high[0x20];
2049 u8 ether_stats_broadcast_pkts_low[0x20];
2051 u8 ether_stats_multicast_pkts_high[0x20];
2053 u8 ether_stats_multicast_pkts_low[0x20];
2055 u8 ether_stats_crc_align_errors_high[0x20];
2057 u8 ether_stats_crc_align_errors_low[0x20];
2059 u8 ether_stats_undersize_pkts_high[0x20];
2061 u8 ether_stats_undersize_pkts_low[0x20];
2063 u8 ether_stats_oversize_pkts_high[0x20];
2065 u8 ether_stats_oversize_pkts_low[0x20];
2067 u8 ether_stats_fragments_high[0x20];
2069 u8 ether_stats_fragments_low[0x20];
2071 u8 ether_stats_jabbers_high[0x20];
2073 u8 ether_stats_jabbers_low[0x20];
2075 u8 ether_stats_collisions_high[0x20];
2077 u8 ether_stats_collisions_low[0x20];
2079 u8 ether_stats_pkts64octets_high[0x20];
2081 u8 ether_stats_pkts64octets_low[0x20];
2083 u8 ether_stats_pkts65to127octets_high[0x20];
2085 u8 ether_stats_pkts65to127octets_low[0x20];
2087 u8 ether_stats_pkts128to255octets_high[0x20];
2089 u8 ether_stats_pkts128to255octets_low[0x20];
2091 u8 ether_stats_pkts256to511octets_high[0x20];
2093 u8 ether_stats_pkts256to511octets_low[0x20];
2095 u8 ether_stats_pkts512to1023octets_high[0x20];
2097 u8 ether_stats_pkts512to1023octets_low[0x20];
2099 u8 ether_stats_pkts1024to1518octets_high[0x20];
2101 u8 ether_stats_pkts1024to1518octets_low[0x20];
2103 u8 ether_stats_pkts1519to2047octets_high[0x20];
2105 u8 ether_stats_pkts1519to2047octets_low[0x20];
2107 u8 ether_stats_pkts2048to4095octets_high[0x20];
2109 u8 ether_stats_pkts2048to4095octets_low[0x20];
2111 u8 ether_stats_pkts4096to8191octets_high[0x20];
2113 u8 ether_stats_pkts4096to8191octets_low[0x20];
2115 u8 ether_stats_pkts8192to10239octets_high[0x20];
2117 u8 ether_stats_pkts8192to10239octets_low[0x20];
2119 u8 reserved_at_540[0x280];
2122 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2123 u8 if_in_octets_high[0x20];
2125 u8 if_in_octets_low[0x20];
2127 u8 if_in_ucast_pkts_high[0x20];
2129 u8 if_in_ucast_pkts_low[0x20];
2131 u8 if_in_discards_high[0x20];
2133 u8 if_in_discards_low[0x20];
2135 u8 if_in_errors_high[0x20];
2137 u8 if_in_errors_low[0x20];
2139 u8 if_in_unknown_protos_high[0x20];
2141 u8 if_in_unknown_protos_low[0x20];
2143 u8 if_out_octets_high[0x20];
2145 u8 if_out_octets_low[0x20];
2147 u8 if_out_ucast_pkts_high[0x20];
2149 u8 if_out_ucast_pkts_low[0x20];
2151 u8 if_out_discards_high[0x20];
2153 u8 if_out_discards_low[0x20];
2155 u8 if_out_errors_high[0x20];
2157 u8 if_out_errors_low[0x20];
2159 u8 if_in_multicast_pkts_high[0x20];
2161 u8 if_in_multicast_pkts_low[0x20];
2163 u8 if_in_broadcast_pkts_high[0x20];
2165 u8 if_in_broadcast_pkts_low[0x20];
2167 u8 if_out_multicast_pkts_high[0x20];
2169 u8 if_out_multicast_pkts_low[0x20];
2171 u8 if_out_broadcast_pkts_high[0x20];
2173 u8 if_out_broadcast_pkts_low[0x20];
2175 u8 reserved_at_340[0x480];
2178 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2179 u8 a_frames_transmitted_ok_high[0x20];
2181 u8 a_frames_transmitted_ok_low[0x20];
2183 u8 a_frames_received_ok_high[0x20];
2185 u8 a_frames_received_ok_low[0x20];
2187 u8 a_frame_check_sequence_errors_high[0x20];
2189 u8 a_frame_check_sequence_errors_low[0x20];
2191 u8 a_alignment_errors_high[0x20];
2193 u8 a_alignment_errors_low[0x20];
2195 u8 a_octets_transmitted_ok_high[0x20];
2197 u8 a_octets_transmitted_ok_low[0x20];
2199 u8 a_octets_received_ok_high[0x20];
2201 u8 a_octets_received_ok_low[0x20];
2203 u8 a_multicast_frames_xmitted_ok_high[0x20];
2205 u8 a_multicast_frames_xmitted_ok_low[0x20];
2207 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2209 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2211 u8 a_multicast_frames_received_ok_high[0x20];
2213 u8 a_multicast_frames_received_ok_low[0x20];
2215 u8 a_broadcast_frames_received_ok_high[0x20];
2217 u8 a_broadcast_frames_received_ok_low[0x20];
2219 u8 a_in_range_length_errors_high[0x20];
2221 u8 a_in_range_length_errors_low[0x20];
2223 u8 a_out_of_range_length_field_high[0x20];
2225 u8 a_out_of_range_length_field_low[0x20];
2227 u8 a_frame_too_long_errors_high[0x20];
2229 u8 a_frame_too_long_errors_low[0x20];
2231 u8 a_symbol_error_during_carrier_high[0x20];
2233 u8 a_symbol_error_during_carrier_low[0x20];
2235 u8 a_mac_control_frames_transmitted_high[0x20];
2237 u8 a_mac_control_frames_transmitted_low[0x20];
2239 u8 a_mac_control_frames_received_high[0x20];
2241 u8 a_mac_control_frames_received_low[0x20];
2243 u8 a_unsupported_opcodes_received_high[0x20];
2245 u8 a_unsupported_opcodes_received_low[0x20];
2247 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2249 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2251 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2253 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2255 u8 reserved_at_4c0[0x300];
2258 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2259 u8 life_time_counter_high[0x20];
2261 u8 life_time_counter_low[0x20];
2267 u8 l0_to_recovery_eieos[0x20];
2269 u8 l0_to_recovery_ts[0x20];
2271 u8 l0_to_recovery_framing[0x20];
2273 u8 l0_to_recovery_retrain[0x20];
2275 u8 crc_error_dllp[0x20];
2277 u8 crc_error_tlp[0x20];
2279 u8 tx_overflow_buffer_pkt_high[0x20];
2281 u8 tx_overflow_buffer_pkt_low[0x20];
2283 u8 outbound_stalled_reads[0x20];
2285 u8 outbound_stalled_writes[0x20];
2287 u8 outbound_stalled_reads_events[0x20];
2289 u8 outbound_stalled_writes_events[0x20];
2291 u8 reserved_at_200[0x5c0];
2294 struct mlx5_ifc_cmd_inter_comp_event_bits {
2295 u8 command_completion_vector[0x20];
2297 u8 reserved_at_20[0xc0];
2300 struct mlx5_ifc_stall_vl_event_bits {
2301 u8 reserved_at_0[0x18];
2303 u8 reserved_at_19[0x3];
2306 u8 reserved_at_20[0xa0];
2309 struct mlx5_ifc_db_bf_congestion_event_bits {
2310 u8 event_subtype[0x8];
2311 u8 reserved_at_8[0x8];
2312 u8 congestion_level[0x8];
2313 u8 reserved_at_18[0x8];
2315 u8 reserved_at_20[0xa0];
2318 struct mlx5_ifc_gpio_event_bits {
2319 u8 reserved_at_0[0x60];
2321 u8 gpio_event_hi[0x20];
2323 u8 gpio_event_lo[0x20];
2325 u8 reserved_at_a0[0x40];
2328 struct mlx5_ifc_port_state_change_event_bits {
2329 u8 reserved_at_0[0x40];
2332 u8 reserved_at_44[0x1c];
2334 u8 reserved_at_60[0x80];
2337 struct mlx5_ifc_dropped_packet_logged_bits {
2338 u8 reserved_at_0[0xe0];
2342 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2343 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2346 struct mlx5_ifc_cq_error_bits {
2347 u8 reserved_at_0[0x8];
2350 u8 reserved_at_20[0x20];
2352 u8 reserved_at_40[0x18];
2355 u8 reserved_at_60[0x80];
2358 struct mlx5_ifc_rdma_page_fault_event_bits {
2359 u8 bytes_committed[0x20];
2363 u8 reserved_at_40[0x10];
2364 u8 packet_len[0x10];
2366 u8 rdma_op_len[0x20];
2370 u8 reserved_at_c0[0x5];
2377 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2378 u8 bytes_committed[0x20];
2380 u8 reserved_at_20[0x10];
2383 u8 reserved_at_40[0x10];
2386 u8 reserved_at_60[0x60];
2388 u8 reserved_at_c0[0x5];
2395 struct mlx5_ifc_qp_events_bits {
2396 u8 reserved_at_0[0xa0];
2399 u8 reserved_at_a8[0x18];
2401 u8 reserved_at_c0[0x8];
2402 u8 qpn_rqn_sqn[0x18];
2405 struct mlx5_ifc_dct_events_bits {
2406 u8 reserved_at_0[0xc0];
2408 u8 reserved_at_c0[0x8];
2409 u8 dct_number[0x18];
2412 struct mlx5_ifc_comp_event_bits {
2413 u8 reserved_at_0[0xc0];
2415 u8 reserved_at_c0[0x8];
2420 MLX5_QPC_STATE_RST = 0x0,
2421 MLX5_QPC_STATE_INIT = 0x1,
2422 MLX5_QPC_STATE_RTR = 0x2,
2423 MLX5_QPC_STATE_RTS = 0x3,
2424 MLX5_QPC_STATE_SQER = 0x4,
2425 MLX5_QPC_STATE_ERR = 0x6,
2426 MLX5_QPC_STATE_SQD = 0x7,
2427 MLX5_QPC_STATE_SUSPENDED = 0x9,
2431 MLX5_QPC_ST_RC = 0x0,
2432 MLX5_QPC_ST_UC = 0x1,
2433 MLX5_QPC_ST_UD = 0x2,
2434 MLX5_QPC_ST_XRC = 0x3,
2435 MLX5_QPC_ST_DCI = 0x5,
2436 MLX5_QPC_ST_QP0 = 0x7,
2437 MLX5_QPC_ST_QP1 = 0x8,
2438 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2439 MLX5_QPC_ST_REG_UMR = 0xc,
2443 MLX5_QPC_PM_STATE_ARMED = 0x0,
2444 MLX5_QPC_PM_STATE_REARM = 0x1,
2445 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2446 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2450 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2454 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2455 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2459 MLX5_QPC_MTU_256_BYTES = 0x1,
2460 MLX5_QPC_MTU_512_BYTES = 0x2,
2461 MLX5_QPC_MTU_1K_BYTES = 0x3,
2462 MLX5_QPC_MTU_2K_BYTES = 0x4,
2463 MLX5_QPC_MTU_4K_BYTES = 0x5,
2464 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2468 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2469 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2470 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2471 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2472 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2473 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2474 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2475 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2479 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2480 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2481 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2485 MLX5_QPC_CS_RES_DISABLE = 0x0,
2486 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2487 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2490 struct mlx5_ifc_qpc_bits {
2492 u8 lag_tx_port_affinity[0x4];
2494 u8 reserved_at_10[0x3];
2496 u8 reserved_at_15[0x1];
2497 u8 req_e2e_credit_mode[0x2];
2498 u8 offload_type[0x4];
2499 u8 end_padding_mode[0x2];
2500 u8 reserved_at_1e[0x2];
2502 u8 wq_signature[0x1];
2503 u8 block_lb_mc[0x1];
2504 u8 atomic_like_write_en[0x1];
2505 u8 latency_sensitive[0x1];
2506 u8 reserved_at_24[0x1];
2507 u8 drain_sigerr[0x1];
2508 u8 reserved_at_26[0x2];
2512 u8 log_msg_max[0x5];
2513 u8 reserved_at_48[0x1];
2514 u8 log_rq_size[0x4];
2515 u8 log_rq_stride[0x3];
2517 u8 log_sq_size[0x4];
2518 u8 reserved_at_55[0x6];
2520 u8 ulp_stateless_offload_mode[0x4];
2522 u8 counter_set_id[0x8];
2525 u8 reserved_at_80[0x8];
2526 u8 user_index[0x18];
2528 u8 reserved_at_a0[0x3];
2529 u8 log_page_size[0x5];
2530 u8 remote_qpn[0x18];
2532 struct mlx5_ifc_ads_bits primary_address_path;
2534 struct mlx5_ifc_ads_bits secondary_address_path;
2536 u8 log_ack_req_freq[0x4];
2537 u8 reserved_at_384[0x4];
2538 u8 log_sra_max[0x3];
2539 u8 reserved_at_38b[0x2];
2540 u8 retry_count[0x3];
2542 u8 reserved_at_393[0x1];
2544 u8 cur_rnr_retry[0x3];
2545 u8 cur_retry_count[0x3];
2546 u8 reserved_at_39b[0x5];
2548 u8 reserved_at_3a0[0x20];
2550 u8 reserved_at_3c0[0x8];
2551 u8 next_send_psn[0x18];
2553 u8 reserved_at_3e0[0x8];
2556 u8 reserved_at_400[0x8];
2559 u8 reserved_at_420[0x20];
2561 u8 reserved_at_440[0x8];
2562 u8 last_acked_psn[0x18];
2564 u8 reserved_at_460[0x8];
2567 u8 reserved_at_480[0x8];
2568 u8 log_rra_max[0x3];
2569 u8 reserved_at_48b[0x1];
2570 u8 atomic_mode[0x4];
2574 u8 reserved_at_493[0x1];
2575 u8 page_offset[0x6];
2576 u8 reserved_at_49a[0x3];
2577 u8 cd_slave_receive[0x1];
2578 u8 cd_slave_send[0x1];
2581 u8 reserved_at_4a0[0x3];
2582 u8 min_rnr_nak[0x5];
2583 u8 next_rcv_psn[0x18];
2585 u8 reserved_at_4c0[0x8];
2588 u8 reserved_at_4e0[0x8];
2595 u8 reserved_at_560[0x5];
2597 u8 srqn_rmpn_xrqn[0x18];
2599 u8 reserved_at_580[0x8];
2602 u8 hw_sq_wqebb_counter[0x10];
2603 u8 sw_sq_wqebb_counter[0x10];
2605 u8 hw_rq_counter[0x20];
2607 u8 sw_rq_counter[0x20];
2609 u8 reserved_at_600[0x20];
2611 u8 reserved_at_620[0xf];
2616 u8 dc_access_key[0x40];
2618 u8 reserved_at_680[0x3];
2619 u8 dbr_umem_valid[0x1];
2621 u8 reserved_at_684[0xbc];
2624 struct mlx5_ifc_roce_addr_layout_bits {
2625 u8 source_l3_address[16][0x8];
2627 u8 reserved_at_80[0x3];
2630 u8 source_mac_47_32[0x10];
2632 u8 source_mac_31_0[0x20];
2634 u8 reserved_at_c0[0x14];
2635 u8 roce_l3_type[0x4];
2636 u8 roce_version[0x8];
2638 u8 reserved_at_e0[0x20];
2641 union mlx5_ifc_hca_cap_union_bits {
2642 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2643 struct mlx5_ifc_odp_cap_bits odp_cap;
2644 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2645 struct mlx5_ifc_roce_cap_bits roce_cap;
2646 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2647 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2648 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2649 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2650 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2651 struct mlx5_ifc_qos_cap_bits qos_cap;
2652 struct mlx5_ifc_debug_cap_bits debug_cap;
2653 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2654 struct mlx5_ifc_tls_cap_bits tls_cap;
2655 u8 reserved_at_0[0x8000];
2659 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2660 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2661 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2662 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2663 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2664 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2665 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2666 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2667 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2668 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2669 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2673 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2674 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2675 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2678 struct mlx5_ifc_vlan_bits {
2685 struct mlx5_ifc_flow_context_bits {
2686 struct mlx5_ifc_vlan_bits push_vlan;
2690 u8 reserved_at_40[0x8];
2693 u8 reserved_at_60[0x10];
2696 u8 extended_destination[0x1];
2697 u8 reserved_at_81[0x1];
2698 u8 flow_source[0x2];
2699 u8 reserved_at_84[0x4];
2700 u8 destination_list_size[0x18];
2702 u8 reserved_at_a0[0x8];
2703 u8 flow_counter_list_size[0x18];
2705 u8 packet_reformat_id[0x20];
2707 u8 modify_header_id[0x20];
2709 struct mlx5_ifc_vlan_bits push_vlan_2;
2711 u8 reserved_at_120[0xe0];
2713 struct mlx5_ifc_fte_match_param_bits match_value;
2715 u8 reserved_at_1200[0x600];
2717 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2721 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2722 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2725 struct mlx5_ifc_xrc_srqc_bits {
2727 u8 log_xrc_srq_size[0x4];
2728 u8 reserved_at_8[0x18];
2730 u8 wq_signature[0x1];
2732 u8 reserved_at_22[0x1];
2734 u8 basic_cyclic_rcv_wqe[0x1];
2735 u8 log_rq_stride[0x3];
2738 u8 page_offset[0x6];
2739 u8 reserved_at_46[0x1];
2740 u8 dbr_umem_valid[0x1];
2743 u8 reserved_at_60[0x20];
2745 u8 user_index_equal_xrc_srqn[0x1];
2746 u8 reserved_at_81[0x1];
2747 u8 log_page_size[0x6];
2748 u8 user_index[0x18];
2750 u8 reserved_at_a0[0x20];
2752 u8 reserved_at_c0[0x8];
2758 u8 reserved_at_100[0x40];
2760 u8 db_record_addr_h[0x20];
2762 u8 db_record_addr_l[0x1e];
2763 u8 reserved_at_17e[0x2];
2765 u8 reserved_at_180[0x80];
2768 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2769 u8 counter_error_queues[0x20];
2771 u8 total_error_queues[0x20];
2773 u8 send_queue_priority_update_flow[0x20];
2775 u8 reserved_at_60[0x20];
2777 u8 nic_receive_steering_discard[0x40];
2779 u8 receive_discard_vport_down[0x40];
2781 u8 transmit_discard_vport_down[0x40];
2783 u8 reserved_at_140[0xa0];
2785 u8 internal_rq_out_of_buffer[0x20];
2787 u8 reserved_at_200[0xe00];
2790 struct mlx5_ifc_traffic_counter_bits {
2796 struct mlx5_ifc_tisc_bits {
2797 u8 strict_lag_tx_port_affinity[0x1];
2799 u8 reserved_at_2[0x2];
2800 u8 lag_tx_port_affinity[0x04];
2802 u8 reserved_at_8[0x4];
2804 u8 reserved_at_10[0x10];
2806 u8 reserved_at_20[0x100];
2808 u8 reserved_at_120[0x8];
2809 u8 transport_domain[0x18];
2811 u8 reserved_at_140[0x8];
2812 u8 underlay_qpn[0x18];
2814 u8 reserved_at_160[0x8];
2817 u8 reserved_at_180[0x380];
2821 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2822 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2826 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2827 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2831 MLX5_RX_HASH_FN_NONE = 0x0,
2832 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2833 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2837 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2838 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2841 struct mlx5_ifc_tirc_bits {
2842 u8 reserved_at_0[0x20];
2845 u8 reserved_at_24[0x1c];
2847 u8 reserved_at_40[0x40];
2849 u8 reserved_at_80[0x4];
2850 u8 lro_timeout_period_usecs[0x10];
2851 u8 lro_enable_mask[0x4];
2852 u8 lro_max_ip_payload_size[0x8];
2854 u8 reserved_at_a0[0x40];
2856 u8 reserved_at_e0[0x8];
2857 u8 inline_rqn[0x18];
2859 u8 rx_hash_symmetric[0x1];
2860 u8 reserved_at_101[0x1];
2861 u8 tunneled_offload_en[0x1];
2862 u8 reserved_at_103[0x5];
2863 u8 indirect_table[0x18];
2866 u8 reserved_at_124[0x2];
2867 u8 self_lb_block[0x2];
2868 u8 transport_domain[0x18];
2870 u8 rx_hash_toeplitz_key[10][0x20];
2872 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2874 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2876 u8 reserved_at_2c0[0x4c0];
2880 MLX5_SRQC_STATE_GOOD = 0x0,
2881 MLX5_SRQC_STATE_ERROR = 0x1,
2884 struct mlx5_ifc_srqc_bits {
2886 u8 log_srq_size[0x4];
2887 u8 reserved_at_8[0x18];
2889 u8 wq_signature[0x1];
2891 u8 reserved_at_22[0x1];
2893 u8 reserved_at_24[0x1];
2894 u8 log_rq_stride[0x3];
2897 u8 page_offset[0x6];
2898 u8 reserved_at_46[0x2];
2901 u8 reserved_at_60[0x20];
2903 u8 reserved_at_80[0x2];
2904 u8 log_page_size[0x6];
2905 u8 reserved_at_88[0x18];
2907 u8 reserved_at_a0[0x20];
2909 u8 reserved_at_c0[0x8];
2915 u8 reserved_at_100[0x40];
2919 u8 reserved_at_180[0x80];
2923 MLX5_SQC_STATE_RST = 0x0,
2924 MLX5_SQC_STATE_RDY = 0x1,
2925 MLX5_SQC_STATE_ERR = 0x3,
2928 struct mlx5_ifc_sqc_bits {
2932 u8 flush_in_error_en[0x1];
2933 u8 allow_multi_pkt_send_wqe[0x1];
2934 u8 min_wqe_inline_mode[0x3];
2939 u8 reserved_at_f[0x11];
2941 u8 reserved_at_20[0x8];
2942 u8 user_index[0x18];
2944 u8 reserved_at_40[0x8];
2947 u8 reserved_at_60[0x8];
2948 u8 hairpin_peer_rq[0x18];
2950 u8 reserved_at_80[0x10];
2951 u8 hairpin_peer_vhca[0x10];
2953 u8 reserved_at_a0[0x50];
2955 u8 packet_pacing_rate_limit_index[0x10];
2956 u8 tis_lst_sz[0x10];
2957 u8 reserved_at_110[0x10];
2959 u8 reserved_at_120[0x40];
2961 u8 reserved_at_160[0x8];
2964 struct mlx5_ifc_wq_bits wq;
2968 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2969 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2970 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2971 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2975 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
2976 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
2977 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
2978 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
2981 struct mlx5_ifc_scheduling_context_bits {
2982 u8 element_type[0x8];
2983 u8 reserved_at_8[0x18];
2985 u8 element_attributes[0x20];
2987 u8 parent_element_id[0x20];
2989 u8 reserved_at_60[0x40];
2993 u8 max_average_bw[0x20];
2995 u8 reserved_at_e0[0x120];
2998 struct mlx5_ifc_rqtc_bits {
2999 u8 reserved_at_0[0xa0];
3001 u8 reserved_at_a0[0x10];
3002 u8 rqt_max_size[0x10];
3004 u8 reserved_at_c0[0x10];
3005 u8 rqt_actual_size[0x10];
3007 u8 reserved_at_e0[0x6a0];
3009 struct mlx5_ifc_rq_num_bits rq_num[0];
3013 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3014 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3018 MLX5_RQC_STATE_RST = 0x0,
3019 MLX5_RQC_STATE_RDY = 0x1,
3020 MLX5_RQC_STATE_ERR = 0x3,
3023 struct mlx5_ifc_rqc_bits {
3025 u8 delay_drop_en[0x1];
3026 u8 scatter_fcs[0x1];
3028 u8 mem_rq_type[0x4];
3030 u8 reserved_at_c[0x1];
3031 u8 flush_in_error_en[0x1];
3033 u8 reserved_at_f[0x11];
3035 u8 reserved_at_20[0x8];
3036 u8 user_index[0x18];
3038 u8 reserved_at_40[0x8];
3041 u8 counter_set_id[0x8];
3042 u8 reserved_at_68[0x18];
3044 u8 reserved_at_80[0x8];
3047 u8 reserved_at_a0[0x8];
3048 u8 hairpin_peer_sq[0x18];
3050 u8 reserved_at_c0[0x10];
3051 u8 hairpin_peer_vhca[0x10];
3053 u8 reserved_at_e0[0xa0];
3055 struct mlx5_ifc_wq_bits wq;
3059 MLX5_RMPC_STATE_RDY = 0x1,
3060 MLX5_RMPC_STATE_ERR = 0x3,
3063 struct mlx5_ifc_rmpc_bits {
3064 u8 reserved_at_0[0x8];
3066 u8 reserved_at_c[0x14];
3068 u8 basic_cyclic_rcv_wqe[0x1];
3069 u8 reserved_at_21[0x1f];
3071 u8 reserved_at_40[0x140];
3073 struct mlx5_ifc_wq_bits wq;
3076 struct mlx5_ifc_nic_vport_context_bits {
3077 u8 reserved_at_0[0x5];
3078 u8 min_wqe_inline_mode[0x3];
3079 u8 reserved_at_8[0x15];
3080 u8 disable_mc_local_lb[0x1];
3081 u8 disable_uc_local_lb[0x1];
3084 u8 arm_change_event[0x1];
3085 u8 reserved_at_21[0x1a];
3086 u8 event_on_mtu[0x1];
3087 u8 event_on_promisc_change[0x1];
3088 u8 event_on_vlan_change[0x1];
3089 u8 event_on_mc_address_change[0x1];
3090 u8 event_on_uc_address_change[0x1];
3092 u8 reserved_at_40[0xc];
3094 u8 affiliation_criteria[0x4];
3095 u8 affiliated_vhca_id[0x10];
3097 u8 reserved_at_60[0xd0];
3101 u8 system_image_guid[0x40];
3105 u8 reserved_at_200[0x140];
3106 u8 qkey_violation_counter[0x10];
3107 u8 reserved_at_350[0x430];
3111 u8 promisc_all[0x1];
3112 u8 reserved_at_783[0x2];
3113 u8 allowed_list_type[0x3];
3114 u8 reserved_at_788[0xc];
3115 u8 allowed_list_size[0xc];
3117 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3119 u8 reserved_at_7e0[0x20];
3121 u8 current_uc_mac_address[0][0x40];
3125 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3126 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3127 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3128 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3129 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3130 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3133 struct mlx5_ifc_mkc_bits {
3134 u8 reserved_at_0[0x1];
3136 u8 reserved_at_2[0x1];
3137 u8 access_mode_4_2[0x3];
3138 u8 reserved_at_6[0x7];
3139 u8 relaxed_ordering_write[0x1];
3140 u8 reserved_at_e[0x1];
3141 u8 small_fence_on_rdma_read_response[0x1];
3148 u8 access_mode_1_0[0x2];
3149 u8 reserved_at_18[0x8];
3154 u8 reserved_at_40[0x20];
3159 u8 reserved_at_63[0x2];
3160 u8 expected_sigerr_count[0x1];
3161 u8 reserved_at_66[0x1];
3165 u8 start_addr[0x40];
3169 u8 bsf_octword_size[0x20];
3171 u8 reserved_at_120[0x80];
3173 u8 translations_octword_size[0x20];
3175 u8 reserved_at_1c0[0x1b];
3176 u8 log_page_size[0x5];
3178 u8 reserved_at_1e0[0x20];
3181 struct mlx5_ifc_pkey_bits {
3182 u8 reserved_at_0[0x10];
3186 struct mlx5_ifc_array128_auto_bits {
3187 u8 array128_auto[16][0x8];
3190 struct mlx5_ifc_hca_vport_context_bits {
3191 u8 field_select[0x20];
3193 u8 reserved_at_20[0xe0];
3195 u8 sm_virt_aware[0x1];
3198 u8 grh_required[0x1];
3199 u8 reserved_at_104[0xc];
3200 u8 port_physical_state[0x4];
3201 u8 vport_state_policy[0x4];
3203 u8 vport_state[0x4];
3205 u8 reserved_at_120[0x20];
3207 u8 system_image_guid[0x40];
3215 u8 cap_mask1_field_select[0x20];
3219 u8 cap_mask2_field_select[0x20];
3221 u8 reserved_at_280[0x80];
3224 u8 reserved_at_310[0x4];
3225 u8 init_type_reply[0x4];
3227 u8 subnet_timeout[0x5];
3231 u8 reserved_at_334[0xc];
3233 u8 qkey_violation_counter[0x10];
3234 u8 pkey_violation_counter[0x10];
3236 u8 reserved_at_360[0xca0];
3239 struct mlx5_ifc_esw_vport_context_bits {
3240 u8 fdb_to_vport_reg_c[0x1];
3241 u8 reserved_at_1[0x2];
3242 u8 vport_svlan_strip[0x1];
3243 u8 vport_cvlan_strip[0x1];
3244 u8 vport_svlan_insert[0x1];
3245 u8 vport_cvlan_insert[0x2];
3246 u8 fdb_to_vport_reg_c_id[0x8];
3247 u8 reserved_at_10[0x10];
3249 u8 reserved_at_20[0x20];
3258 u8 reserved_at_60[0x7a0];
3262 MLX5_EQC_STATUS_OK = 0x0,
3263 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3267 MLX5_EQC_ST_ARMED = 0x9,
3268 MLX5_EQC_ST_FIRED = 0xa,
3271 struct mlx5_ifc_eqc_bits {
3273 u8 reserved_at_4[0x9];
3276 u8 reserved_at_f[0x5];
3278 u8 reserved_at_18[0x8];
3280 u8 reserved_at_20[0x20];
3282 u8 reserved_at_40[0x14];
3283 u8 page_offset[0x6];
3284 u8 reserved_at_5a[0x6];
3286 u8 reserved_at_60[0x3];
3287 u8 log_eq_size[0x5];
3290 u8 reserved_at_80[0x20];
3292 u8 reserved_at_a0[0x18];
3295 u8 reserved_at_c0[0x3];
3296 u8 log_page_size[0x5];
3297 u8 reserved_at_c8[0x18];
3299 u8 reserved_at_e0[0x60];
3301 u8 reserved_at_140[0x8];
3302 u8 consumer_counter[0x18];
3304 u8 reserved_at_160[0x8];
3305 u8 producer_counter[0x18];
3307 u8 reserved_at_180[0x80];
3311 MLX5_DCTC_STATE_ACTIVE = 0x0,
3312 MLX5_DCTC_STATE_DRAINING = 0x1,
3313 MLX5_DCTC_STATE_DRAINED = 0x2,
3317 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3318 MLX5_DCTC_CS_RES_NA = 0x1,
3319 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3323 MLX5_DCTC_MTU_256_BYTES = 0x1,
3324 MLX5_DCTC_MTU_512_BYTES = 0x2,
3325 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3326 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3327 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3330 struct mlx5_ifc_dctc_bits {
3331 u8 reserved_at_0[0x4];
3333 u8 reserved_at_8[0x18];
3335 u8 reserved_at_20[0x8];
3336 u8 user_index[0x18];
3338 u8 reserved_at_40[0x8];
3341 u8 counter_set_id[0x8];
3342 u8 atomic_mode[0x4];
3346 u8 atomic_like_write_en[0x1];
3347 u8 latency_sensitive[0x1];
3350 u8 reserved_at_73[0xd];
3352 u8 reserved_at_80[0x8];
3354 u8 reserved_at_90[0x3];
3355 u8 min_rnr_nak[0x5];
3356 u8 reserved_at_98[0x8];
3358 u8 reserved_at_a0[0x8];
3361 u8 reserved_at_c0[0x8];
3365 u8 reserved_at_e8[0x4];
3366 u8 flow_label[0x14];
3368 u8 dc_access_key[0x40];
3370 u8 reserved_at_140[0x5];
3373 u8 pkey_index[0x10];
3375 u8 reserved_at_160[0x8];
3376 u8 my_addr_index[0x8];
3377 u8 reserved_at_170[0x8];
3380 u8 dc_access_key_violation_count[0x20];
3382 u8 reserved_at_1a0[0x14];
3388 u8 reserved_at_1c0[0x40];
3392 MLX5_CQC_STATUS_OK = 0x0,
3393 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3394 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3398 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3399 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3403 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3404 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3405 MLX5_CQC_ST_FIRED = 0xa,
3409 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3410 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3411 MLX5_CQ_PERIOD_NUM_MODES
3414 struct mlx5_ifc_cqc_bits {
3416 u8 reserved_at_4[0x2];
3417 u8 dbr_umem_valid[0x1];
3418 u8 reserved_at_7[0x1];
3421 u8 reserved_at_c[0x1];
3422 u8 scqe_break_moderation_en[0x1];
3424 u8 cq_period_mode[0x2];
3425 u8 cqe_comp_en[0x1];
3426 u8 mini_cqe_res_format[0x2];
3428 u8 reserved_at_18[0x8];
3430 u8 reserved_at_20[0x20];
3432 u8 reserved_at_40[0x14];
3433 u8 page_offset[0x6];
3434 u8 reserved_at_5a[0x6];
3436 u8 reserved_at_60[0x3];
3437 u8 log_cq_size[0x5];
3440 u8 reserved_at_80[0x4];
3442 u8 cq_max_count[0x10];
3444 u8 reserved_at_a0[0x18];
3447 u8 reserved_at_c0[0x3];
3448 u8 log_page_size[0x5];
3449 u8 reserved_at_c8[0x18];
3451 u8 reserved_at_e0[0x20];
3453 u8 reserved_at_100[0x8];
3454 u8 last_notified_index[0x18];
3456 u8 reserved_at_120[0x8];
3457 u8 last_solicit_index[0x18];
3459 u8 reserved_at_140[0x8];
3460 u8 consumer_counter[0x18];
3462 u8 reserved_at_160[0x8];
3463 u8 producer_counter[0x18];
3465 u8 reserved_at_180[0x40];
3470 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3471 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3472 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3473 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3474 u8 reserved_at_0[0x800];
3477 struct mlx5_ifc_query_adapter_param_block_bits {
3478 u8 reserved_at_0[0xc0];
3480 u8 reserved_at_c0[0x8];
3481 u8 ieee_vendor_id[0x18];
3483 u8 reserved_at_e0[0x10];
3484 u8 vsd_vendor_id[0x10];
3488 u8 vsd_contd_psid[16][0x8];
3492 MLX5_XRQC_STATE_GOOD = 0x0,
3493 MLX5_XRQC_STATE_ERROR = 0x1,
3497 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3498 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3502 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3505 struct mlx5_ifc_tag_matching_topology_context_bits {
3506 u8 log_matching_list_sz[0x4];
3507 u8 reserved_at_4[0xc];
3508 u8 append_next_index[0x10];
3510 u8 sw_phase_cnt[0x10];
3511 u8 hw_phase_cnt[0x10];
3513 u8 reserved_at_40[0x40];
3516 struct mlx5_ifc_xrqc_bits {
3519 u8 reserved_at_5[0xf];
3521 u8 reserved_at_18[0x4];
3524 u8 reserved_at_20[0x8];
3525 u8 user_index[0x18];
3527 u8 reserved_at_40[0x8];
3530 u8 reserved_at_60[0xa0];
3532 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3534 u8 reserved_at_180[0x280];
3536 struct mlx5_ifc_wq_bits wq;
3539 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3540 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3541 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3542 u8 reserved_at_0[0x20];
3545 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3546 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3547 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3548 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3549 u8 reserved_at_0[0x20];
3552 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3553 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3554 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3555 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3556 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3557 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3558 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3559 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3560 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3561 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3562 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3563 u8 reserved_at_0[0x7c0];
3566 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3567 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3568 u8 reserved_at_0[0x7c0];
3571 union mlx5_ifc_event_auto_bits {
3572 struct mlx5_ifc_comp_event_bits comp_event;
3573 struct mlx5_ifc_dct_events_bits dct_events;
3574 struct mlx5_ifc_qp_events_bits qp_events;
3575 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3576 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3577 struct mlx5_ifc_cq_error_bits cq_error;
3578 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3579 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3580 struct mlx5_ifc_gpio_event_bits gpio_event;
3581 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3582 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3583 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3584 u8 reserved_at_0[0xe0];
3587 struct mlx5_ifc_health_buffer_bits {
3588 u8 reserved_at_0[0x100];
3590 u8 assert_existptr[0x20];
3592 u8 assert_callra[0x20];
3594 u8 reserved_at_140[0x40];
3596 u8 fw_version[0x20];
3600 u8 reserved_at_1c0[0x20];
3602 u8 irisc_index[0x8];
3607 struct mlx5_ifc_register_loopback_control_bits {
3609 u8 reserved_at_1[0x7];
3611 u8 reserved_at_10[0x10];
3613 u8 reserved_at_20[0x60];
3616 struct mlx5_ifc_vport_tc_element_bits {
3617 u8 traffic_class[0x4];
3618 u8 reserved_at_4[0xc];
3619 u8 vport_number[0x10];
3622 struct mlx5_ifc_vport_element_bits {
3623 u8 reserved_at_0[0x10];
3624 u8 vport_number[0x10];
3628 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3629 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3630 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3633 struct mlx5_ifc_tsar_element_bits {
3634 u8 reserved_at_0[0x8];
3636 u8 reserved_at_10[0x10];
3640 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3641 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3644 struct mlx5_ifc_teardown_hca_out_bits {
3646 u8 reserved_at_8[0x18];
3650 u8 reserved_at_40[0x3f];
3656 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3657 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3658 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3661 struct mlx5_ifc_teardown_hca_in_bits {
3663 u8 reserved_at_10[0x10];
3665 u8 reserved_at_20[0x10];
3668 u8 reserved_at_40[0x10];
3671 u8 reserved_at_60[0x20];
3674 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3676 u8 reserved_at_8[0x18];
3680 u8 reserved_at_40[0x40];
3683 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3687 u8 reserved_at_20[0x10];
3690 u8 reserved_at_40[0x8];
3693 u8 reserved_at_60[0x20];
3695 u8 opt_param_mask[0x20];
3697 u8 reserved_at_a0[0x20];
3699 struct mlx5_ifc_qpc_bits qpc;
3701 u8 reserved_at_800[0x80];
3704 struct mlx5_ifc_sqd2rts_qp_out_bits {
3706 u8 reserved_at_8[0x18];
3710 u8 reserved_at_40[0x40];
3713 struct mlx5_ifc_sqd2rts_qp_in_bits {
3717 u8 reserved_at_20[0x10];
3720 u8 reserved_at_40[0x8];
3723 u8 reserved_at_60[0x20];
3725 u8 opt_param_mask[0x20];
3727 u8 reserved_at_a0[0x20];
3729 struct mlx5_ifc_qpc_bits qpc;
3731 u8 reserved_at_800[0x80];
3734 struct mlx5_ifc_set_roce_address_out_bits {
3736 u8 reserved_at_8[0x18];
3740 u8 reserved_at_40[0x40];
3743 struct mlx5_ifc_set_roce_address_in_bits {
3745 u8 reserved_at_10[0x10];
3747 u8 reserved_at_20[0x10];
3750 u8 roce_address_index[0x10];
3751 u8 reserved_at_50[0xc];
3752 u8 vhca_port_num[0x4];
3754 u8 reserved_at_60[0x20];
3756 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3759 struct mlx5_ifc_set_mad_demux_out_bits {
3761 u8 reserved_at_8[0x18];
3765 u8 reserved_at_40[0x40];
3769 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3770 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3773 struct mlx5_ifc_set_mad_demux_in_bits {
3775 u8 reserved_at_10[0x10];
3777 u8 reserved_at_20[0x10];
3780 u8 reserved_at_40[0x20];
3782 u8 reserved_at_60[0x6];
3784 u8 reserved_at_68[0x18];
3787 struct mlx5_ifc_set_l2_table_entry_out_bits {
3789 u8 reserved_at_8[0x18];
3793 u8 reserved_at_40[0x40];
3796 struct mlx5_ifc_set_l2_table_entry_in_bits {
3798 u8 reserved_at_10[0x10];
3800 u8 reserved_at_20[0x10];
3803 u8 reserved_at_40[0x60];
3805 u8 reserved_at_a0[0x8];
3806 u8 table_index[0x18];
3808 u8 reserved_at_c0[0x20];
3810 u8 reserved_at_e0[0x13];
3814 struct mlx5_ifc_mac_address_layout_bits mac_address;
3816 u8 reserved_at_140[0xc0];
3819 struct mlx5_ifc_set_issi_out_bits {
3821 u8 reserved_at_8[0x18];
3825 u8 reserved_at_40[0x40];
3828 struct mlx5_ifc_set_issi_in_bits {
3830 u8 reserved_at_10[0x10];
3832 u8 reserved_at_20[0x10];
3835 u8 reserved_at_40[0x10];
3836 u8 current_issi[0x10];
3838 u8 reserved_at_60[0x20];
3841 struct mlx5_ifc_set_hca_cap_out_bits {
3843 u8 reserved_at_8[0x18];
3847 u8 reserved_at_40[0x40];
3850 struct mlx5_ifc_set_hca_cap_in_bits {
3852 u8 reserved_at_10[0x10];
3854 u8 reserved_at_20[0x10];
3857 u8 reserved_at_40[0x40];
3859 union mlx5_ifc_hca_cap_union_bits capability;
3863 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3864 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3865 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3866 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3869 struct mlx5_ifc_set_fte_out_bits {
3871 u8 reserved_at_8[0x18];
3875 u8 reserved_at_40[0x40];
3878 struct mlx5_ifc_set_fte_in_bits {
3880 u8 reserved_at_10[0x10];
3882 u8 reserved_at_20[0x10];
3885 u8 other_vport[0x1];
3886 u8 reserved_at_41[0xf];
3887 u8 vport_number[0x10];
3889 u8 reserved_at_60[0x20];
3892 u8 reserved_at_88[0x18];
3894 u8 reserved_at_a0[0x8];
3897 u8 reserved_at_c0[0x18];
3898 u8 modify_enable_mask[0x8];
3900 u8 reserved_at_e0[0x20];
3902 u8 flow_index[0x20];
3904 u8 reserved_at_120[0xe0];
3906 struct mlx5_ifc_flow_context_bits flow_context;
3909 struct mlx5_ifc_rts2rts_qp_out_bits {
3911 u8 reserved_at_8[0x18];
3915 u8 reserved_at_40[0x40];
3918 struct mlx5_ifc_rts2rts_qp_in_bits {
3922 u8 reserved_at_20[0x10];
3925 u8 reserved_at_40[0x8];
3928 u8 reserved_at_60[0x20];
3930 u8 opt_param_mask[0x20];
3932 u8 reserved_at_a0[0x20];
3934 struct mlx5_ifc_qpc_bits qpc;
3936 u8 reserved_at_800[0x80];
3939 struct mlx5_ifc_rtr2rts_qp_out_bits {
3941 u8 reserved_at_8[0x18];
3945 u8 reserved_at_40[0x40];
3948 struct mlx5_ifc_rtr2rts_qp_in_bits {
3952 u8 reserved_at_20[0x10];
3955 u8 reserved_at_40[0x8];
3958 u8 reserved_at_60[0x20];
3960 u8 opt_param_mask[0x20];
3962 u8 reserved_at_a0[0x20];
3964 struct mlx5_ifc_qpc_bits qpc;
3966 u8 reserved_at_800[0x80];
3969 struct mlx5_ifc_rst2init_qp_out_bits {
3971 u8 reserved_at_8[0x18];
3975 u8 reserved_at_40[0x40];
3978 struct mlx5_ifc_rst2init_qp_in_bits {
3982 u8 reserved_at_20[0x10];
3985 u8 reserved_at_40[0x8];
3988 u8 reserved_at_60[0x20];
3990 u8 opt_param_mask[0x20];
3992 u8 reserved_at_a0[0x20];
3994 struct mlx5_ifc_qpc_bits qpc;
3996 u8 reserved_at_800[0x80];
3999 struct mlx5_ifc_query_xrq_out_bits {
4001 u8 reserved_at_8[0x18];
4005 u8 reserved_at_40[0x40];
4007 struct mlx5_ifc_xrqc_bits xrq_context;
4010 struct mlx5_ifc_query_xrq_in_bits {
4012 u8 reserved_at_10[0x10];
4014 u8 reserved_at_20[0x10];
4017 u8 reserved_at_40[0x8];
4020 u8 reserved_at_60[0x20];
4023 struct mlx5_ifc_query_xrc_srq_out_bits {
4025 u8 reserved_at_8[0x18];
4029 u8 reserved_at_40[0x40];
4031 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4033 u8 reserved_at_280[0x600];
4038 struct mlx5_ifc_query_xrc_srq_in_bits {
4040 u8 reserved_at_10[0x10];
4042 u8 reserved_at_20[0x10];
4045 u8 reserved_at_40[0x8];
4048 u8 reserved_at_60[0x20];
4052 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4053 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4056 struct mlx5_ifc_query_vport_state_out_bits {
4058 u8 reserved_at_8[0x18];
4062 u8 reserved_at_40[0x20];
4064 u8 reserved_at_60[0x18];
4065 u8 admin_state[0x4];
4070 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4071 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4074 struct mlx5_ifc_arm_monitor_counter_in_bits {
4078 u8 reserved_at_20[0x10];
4081 u8 reserved_at_40[0x20];
4083 u8 reserved_at_60[0x20];
4086 struct mlx5_ifc_arm_monitor_counter_out_bits {
4088 u8 reserved_at_8[0x18];
4092 u8 reserved_at_40[0x40];
4096 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4097 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4100 enum mlx5_monitor_counter_ppcnt {
4101 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4102 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4103 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4104 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4105 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4106 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4110 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4113 struct mlx5_ifc_monitor_counter_output_bits {
4114 u8 reserved_at_0[0x4];
4116 u8 reserved_at_8[0x8];
4119 u8 counter_group_id[0x20];
4122 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4123 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4124 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4125 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4127 struct mlx5_ifc_set_monitor_counter_in_bits {
4131 u8 reserved_at_20[0x10];
4134 u8 reserved_at_40[0x10];
4135 u8 num_of_counters[0x10];
4137 u8 reserved_at_60[0x20];
4139 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4142 struct mlx5_ifc_set_monitor_counter_out_bits {
4144 u8 reserved_at_8[0x18];
4148 u8 reserved_at_40[0x40];
4151 struct mlx5_ifc_query_vport_state_in_bits {
4153 u8 reserved_at_10[0x10];
4155 u8 reserved_at_20[0x10];
4158 u8 other_vport[0x1];
4159 u8 reserved_at_41[0xf];
4160 u8 vport_number[0x10];
4162 u8 reserved_at_60[0x20];
4165 struct mlx5_ifc_query_vnic_env_out_bits {
4167 u8 reserved_at_8[0x18];
4171 u8 reserved_at_40[0x40];
4173 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4177 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4180 struct mlx5_ifc_query_vnic_env_in_bits {
4182 u8 reserved_at_10[0x10];
4184 u8 reserved_at_20[0x10];
4187 u8 other_vport[0x1];
4188 u8 reserved_at_41[0xf];
4189 u8 vport_number[0x10];
4191 u8 reserved_at_60[0x20];
4194 struct mlx5_ifc_query_vport_counter_out_bits {
4196 u8 reserved_at_8[0x18];
4200 u8 reserved_at_40[0x40];
4202 struct mlx5_ifc_traffic_counter_bits received_errors;
4204 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4206 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4208 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4210 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4212 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4214 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4216 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4218 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4220 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4222 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4224 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4226 u8 reserved_at_680[0xa00];
4230 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4233 struct mlx5_ifc_query_vport_counter_in_bits {
4235 u8 reserved_at_10[0x10];
4237 u8 reserved_at_20[0x10];
4240 u8 other_vport[0x1];
4241 u8 reserved_at_41[0xb];
4243 u8 vport_number[0x10];
4245 u8 reserved_at_60[0x60];
4248 u8 reserved_at_c1[0x1f];
4250 u8 reserved_at_e0[0x20];
4253 struct mlx5_ifc_query_tis_out_bits {
4255 u8 reserved_at_8[0x18];
4259 u8 reserved_at_40[0x40];
4261 struct mlx5_ifc_tisc_bits tis_context;
4264 struct mlx5_ifc_query_tis_in_bits {
4266 u8 reserved_at_10[0x10];
4268 u8 reserved_at_20[0x10];
4271 u8 reserved_at_40[0x8];
4274 u8 reserved_at_60[0x20];
4277 struct mlx5_ifc_query_tir_out_bits {
4279 u8 reserved_at_8[0x18];
4283 u8 reserved_at_40[0xc0];
4285 struct mlx5_ifc_tirc_bits tir_context;
4288 struct mlx5_ifc_query_tir_in_bits {
4290 u8 reserved_at_10[0x10];
4292 u8 reserved_at_20[0x10];
4295 u8 reserved_at_40[0x8];
4298 u8 reserved_at_60[0x20];
4301 struct mlx5_ifc_query_srq_out_bits {
4303 u8 reserved_at_8[0x18];
4307 u8 reserved_at_40[0x40];
4309 struct mlx5_ifc_srqc_bits srq_context_entry;
4311 u8 reserved_at_280[0x600];
4316 struct mlx5_ifc_query_srq_in_bits {
4318 u8 reserved_at_10[0x10];
4320 u8 reserved_at_20[0x10];
4323 u8 reserved_at_40[0x8];
4326 u8 reserved_at_60[0x20];
4329 struct mlx5_ifc_query_sq_out_bits {
4331 u8 reserved_at_8[0x18];
4335 u8 reserved_at_40[0xc0];
4337 struct mlx5_ifc_sqc_bits sq_context;
4340 struct mlx5_ifc_query_sq_in_bits {
4342 u8 reserved_at_10[0x10];
4344 u8 reserved_at_20[0x10];
4347 u8 reserved_at_40[0x8];
4350 u8 reserved_at_60[0x20];
4353 struct mlx5_ifc_query_special_contexts_out_bits {
4355 u8 reserved_at_8[0x18];
4359 u8 dump_fill_mkey[0x20];
4365 u8 reserved_at_a0[0x60];
4368 struct mlx5_ifc_query_special_contexts_in_bits {
4370 u8 reserved_at_10[0x10];
4372 u8 reserved_at_20[0x10];
4375 u8 reserved_at_40[0x40];
4378 struct mlx5_ifc_query_scheduling_element_out_bits {
4380 u8 reserved_at_10[0x10];
4382 u8 reserved_at_20[0x10];
4385 u8 reserved_at_40[0xc0];
4387 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4389 u8 reserved_at_300[0x100];
4393 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4396 struct mlx5_ifc_query_scheduling_element_in_bits {
4398 u8 reserved_at_10[0x10];
4400 u8 reserved_at_20[0x10];
4403 u8 scheduling_hierarchy[0x8];
4404 u8 reserved_at_48[0x18];
4406 u8 scheduling_element_id[0x20];
4408 u8 reserved_at_80[0x180];
4411 struct mlx5_ifc_query_rqt_out_bits {
4413 u8 reserved_at_8[0x18];
4417 u8 reserved_at_40[0xc0];
4419 struct mlx5_ifc_rqtc_bits rqt_context;
4422 struct mlx5_ifc_query_rqt_in_bits {
4424 u8 reserved_at_10[0x10];
4426 u8 reserved_at_20[0x10];
4429 u8 reserved_at_40[0x8];
4432 u8 reserved_at_60[0x20];
4435 struct mlx5_ifc_query_rq_out_bits {
4437 u8 reserved_at_8[0x18];
4441 u8 reserved_at_40[0xc0];
4443 struct mlx5_ifc_rqc_bits rq_context;
4446 struct mlx5_ifc_query_rq_in_bits {
4448 u8 reserved_at_10[0x10];
4450 u8 reserved_at_20[0x10];
4453 u8 reserved_at_40[0x8];
4456 u8 reserved_at_60[0x20];
4459 struct mlx5_ifc_query_roce_address_out_bits {
4461 u8 reserved_at_8[0x18];
4465 u8 reserved_at_40[0x40];
4467 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4470 struct mlx5_ifc_query_roce_address_in_bits {
4472 u8 reserved_at_10[0x10];
4474 u8 reserved_at_20[0x10];
4477 u8 roce_address_index[0x10];
4478 u8 reserved_at_50[0xc];
4479 u8 vhca_port_num[0x4];
4481 u8 reserved_at_60[0x20];
4484 struct mlx5_ifc_query_rmp_out_bits {
4486 u8 reserved_at_8[0x18];
4490 u8 reserved_at_40[0xc0];
4492 struct mlx5_ifc_rmpc_bits rmp_context;
4495 struct mlx5_ifc_query_rmp_in_bits {
4497 u8 reserved_at_10[0x10];
4499 u8 reserved_at_20[0x10];
4502 u8 reserved_at_40[0x8];
4505 u8 reserved_at_60[0x20];
4508 struct mlx5_ifc_query_qp_out_bits {
4510 u8 reserved_at_8[0x18];
4514 u8 reserved_at_40[0x40];
4516 u8 opt_param_mask[0x20];
4518 u8 reserved_at_a0[0x20];
4520 struct mlx5_ifc_qpc_bits qpc;
4522 u8 reserved_at_800[0x80];
4527 struct mlx5_ifc_query_qp_in_bits {
4529 u8 reserved_at_10[0x10];
4531 u8 reserved_at_20[0x10];
4534 u8 reserved_at_40[0x8];
4537 u8 reserved_at_60[0x20];
4540 struct mlx5_ifc_query_q_counter_out_bits {
4542 u8 reserved_at_8[0x18];
4546 u8 reserved_at_40[0x40];
4548 u8 rx_write_requests[0x20];
4550 u8 reserved_at_a0[0x20];
4552 u8 rx_read_requests[0x20];
4554 u8 reserved_at_e0[0x20];
4556 u8 rx_atomic_requests[0x20];
4558 u8 reserved_at_120[0x20];
4560 u8 rx_dct_connect[0x20];
4562 u8 reserved_at_160[0x20];
4564 u8 out_of_buffer[0x20];
4566 u8 reserved_at_1a0[0x20];
4568 u8 out_of_sequence[0x20];
4570 u8 reserved_at_1e0[0x20];
4572 u8 duplicate_request[0x20];
4574 u8 reserved_at_220[0x20];
4576 u8 rnr_nak_retry_err[0x20];
4578 u8 reserved_at_260[0x20];
4580 u8 packet_seq_err[0x20];
4582 u8 reserved_at_2a0[0x20];
4584 u8 implied_nak_seq_err[0x20];
4586 u8 reserved_at_2e0[0x20];
4588 u8 local_ack_timeout_err[0x20];
4590 u8 reserved_at_320[0xa0];
4592 u8 resp_local_length_error[0x20];
4594 u8 req_local_length_error[0x20];
4596 u8 resp_local_qp_error[0x20];
4598 u8 local_operation_error[0x20];
4600 u8 resp_local_protection[0x20];
4602 u8 req_local_protection[0x20];
4604 u8 resp_cqe_error[0x20];
4606 u8 req_cqe_error[0x20];
4608 u8 req_mw_binding[0x20];
4610 u8 req_bad_response[0x20];
4612 u8 req_remote_invalid_request[0x20];
4614 u8 resp_remote_invalid_request[0x20];
4616 u8 req_remote_access_errors[0x20];
4618 u8 resp_remote_access_errors[0x20];
4620 u8 req_remote_operation_errors[0x20];
4622 u8 req_transport_retries_exceeded[0x20];
4624 u8 cq_overflow[0x20];
4626 u8 resp_cqe_flush_error[0x20];
4628 u8 req_cqe_flush_error[0x20];
4630 u8 reserved_at_620[0x1e0];
4633 struct mlx5_ifc_query_q_counter_in_bits {
4635 u8 reserved_at_10[0x10];
4637 u8 reserved_at_20[0x10];
4640 u8 reserved_at_40[0x80];
4643 u8 reserved_at_c1[0x1f];
4645 u8 reserved_at_e0[0x18];
4646 u8 counter_set_id[0x8];
4649 struct mlx5_ifc_query_pages_out_bits {
4651 u8 reserved_at_8[0x18];
4655 u8 embedded_cpu_function[0x1];
4656 u8 reserved_at_41[0xf];
4657 u8 function_id[0x10];
4663 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4664 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4665 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4668 struct mlx5_ifc_query_pages_in_bits {
4670 u8 reserved_at_10[0x10];
4672 u8 reserved_at_20[0x10];
4675 u8 embedded_cpu_function[0x1];
4676 u8 reserved_at_41[0xf];
4677 u8 function_id[0x10];
4679 u8 reserved_at_60[0x20];
4682 struct mlx5_ifc_query_nic_vport_context_out_bits {
4684 u8 reserved_at_8[0x18];
4688 u8 reserved_at_40[0x40];
4690 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4693 struct mlx5_ifc_query_nic_vport_context_in_bits {
4695 u8 reserved_at_10[0x10];
4697 u8 reserved_at_20[0x10];
4700 u8 other_vport[0x1];
4701 u8 reserved_at_41[0xf];
4702 u8 vport_number[0x10];
4704 u8 reserved_at_60[0x5];
4705 u8 allowed_list_type[0x3];
4706 u8 reserved_at_68[0x18];
4709 struct mlx5_ifc_query_mkey_out_bits {
4711 u8 reserved_at_8[0x18];
4715 u8 reserved_at_40[0x40];
4717 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4719 u8 reserved_at_280[0x600];
4721 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4723 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4726 struct mlx5_ifc_query_mkey_in_bits {
4728 u8 reserved_at_10[0x10];
4730 u8 reserved_at_20[0x10];
4733 u8 reserved_at_40[0x8];
4734 u8 mkey_index[0x18];
4737 u8 reserved_at_61[0x1f];
4740 struct mlx5_ifc_query_mad_demux_out_bits {
4742 u8 reserved_at_8[0x18];
4746 u8 reserved_at_40[0x40];
4748 u8 mad_dumux_parameters_block[0x20];
4751 struct mlx5_ifc_query_mad_demux_in_bits {
4753 u8 reserved_at_10[0x10];
4755 u8 reserved_at_20[0x10];
4758 u8 reserved_at_40[0x40];
4761 struct mlx5_ifc_query_l2_table_entry_out_bits {
4763 u8 reserved_at_8[0x18];
4767 u8 reserved_at_40[0xa0];
4769 u8 reserved_at_e0[0x13];
4773 struct mlx5_ifc_mac_address_layout_bits mac_address;
4775 u8 reserved_at_140[0xc0];
4778 struct mlx5_ifc_query_l2_table_entry_in_bits {
4780 u8 reserved_at_10[0x10];
4782 u8 reserved_at_20[0x10];
4785 u8 reserved_at_40[0x60];
4787 u8 reserved_at_a0[0x8];
4788 u8 table_index[0x18];
4790 u8 reserved_at_c0[0x140];
4793 struct mlx5_ifc_query_issi_out_bits {
4795 u8 reserved_at_8[0x18];
4799 u8 reserved_at_40[0x10];
4800 u8 current_issi[0x10];
4802 u8 reserved_at_60[0xa0];
4804 u8 reserved_at_100[76][0x8];
4805 u8 supported_issi_dw0[0x20];
4808 struct mlx5_ifc_query_issi_in_bits {
4810 u8 reserved_at_10[0x10];
4812 u8 reserved_at_20[0x10];
4815 u8 reserved_at_40[0x40];
4818 struct mlx5_ifc_set_driver_version_out_bits {
4820 u8 reserved_0[0x18];
4823 u8 reserved_1[0x40];
4826 struct mlx5_ifc_set_driver_version_in_bits {
4828 u8 reserved_0[0x10];
4830 u8 reserved_1[0x10];
4833 u8 reserved_2[0x40];
4834 u8 driver_version[64][0x8];
4837 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4839 u8 reserved_at_8[0x18];
4843 u8 reserved_at_40[0x40];
4845 struct mlx5_ifc_pkey_bits pkey[0];
4848 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4850 u8 reserved_at_10[0x10];
4852 u8 reserved_at_20[0x10];
4855 u8 other_vport[0x1];
4856 u8 reserved_at_41[0xb];
4858 u8 vport_number[0x10];
4860 u8 reserved_at_60[0x10];
4861 u8 pkey_index[0x10];
4865 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4866 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4867 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4870 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4872 u8 reserved_at_8[0x18];
4876 u8 reserved_at_40[0x20];
4879 u8 reserved_at_70[0x10];
4881 struct mlx5_ifc_array128_auto_bits gid[0];
4884 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4886 u8 reserved_at_10[0x10];
4888 u8 reserved_at_20[0x10];
4891 u8 other_vport[0x1];
4892 u8 reserved_at_41[0xb];
4894 u8 vport_number[0x10];
4896 u8 reserved_at_60[0x10];
4900 struct mlx5_ifc_query_hca_vport_context_out_bits {
4902 u8 reserved_at_8[0x18];
4906 u8 reserved_at_40[0x40];
4908 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4911 struct mlx5_ifc_query_hca_vport_context_in_bits {
4913 u8 reserved_at_10[0x10];
4915 u8 reserved_at_20[0x10];
4918 u8 other_vport[0x1];
4919 u8 reserved_at_41[0xb];
4921 u8 vport_number[0x10];
4923 u8 reserved_at_60[0x20];
4926 struct mlx5_ifc_query_hca_cap_out_bits {
4928 u8 reserved_at_8[0x18];
4932 u8 reserved_at_40[0x40];
4934 union mlx5_ifc_hca_cap_union_bits capability;
4937 struct mlx5_ifc_query_hca_cap_in_bits {
4939 u8 reserved_at_10[0x10];
4941 u8 reserved_at_20[0x10];
4944 u8 reserved_at_40[0x40];
4947 struct mlx5_ifc_query_flow_table_out_bits {
4949 u8 reserved_at_8[0x18];
4953 u8 reserved_at_40[0x80];
4955 u8 reserved_at_c0[0x8];
4957 u8 reserved_at_d0[0x8];
4960 u8 reserved_at_e0[0x120];
4963 struct mlx5_ifc_query_flow_table_in_bits {
4965 u8 reserved_at_10[0x10];
4967 u8 reserved_at_20[0x10];
4970 u8 reserved_at_40[0x40];
4973 u8 reserved_at_88[0x18];
4975 u8 reserved_at_a0[0x8];
4978 u8 reserved_at_c0[0x140];
4981 struct mlx5_ifc_query_fte_out_bits {
4983 u8 reserved_at_8[0x18];
4987 u8 reserved_at_40[0x1c0];
4989 struct mlx5_ifc_flow_context_bits flow_context;
4992 struct mlx5_ifc_query_fte_in_bits {
4994 u8 reserved_at_10[0x10];
4996 u8 reserved_at_20[0x10];
4999 u8 reserved_at_40[0x40];
5002 u8 reserved_at_88[0x18];
5004 u8 reserved_at_a0[0x8];
5007 u8 reserved_at_c0[0x40];
5009 u8 flow_index[0x20];
5011 u8 reserved_at_120[0xe0];
5015 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5016 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5017 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5018 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5019 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5022 struct mlx5_ifc_query_flow_group_out_bits {
5024 u8 reserved_at_8[0x18];
5028 u8 reserved_at_40[0xa0];
5030 u8 start_flow_index[0x20];
5032 u8 reserved_at_100[0x20];
5034 u8 end_flow_index[0x20];
5036 u8 reserved_at_140[0xa0];
5038 u8 reserved_at_1e0[0x18];
5039 u8 match_criteria_enable[0x8];
5041 struct mlx5_ifc_fte_match_param_bits match_criteria;
5043 u8 reserved_at_1200[0xe00];
5046 struct mlx5_ifc_query_flow_group_in_bits {
5048 u8 reserved_at_10[0x10];
5050 u8 reserved_at_20[0x10];
5053 u8 reserved_at_40[0x40];
5056 u8 reserved_at_88[0x18];
5058 u8 reserved_at_a0[0x8];
5063 u8 reserved_at_e0[0x120];
5066 struct mlx5_ifc_query_flow_counter_out_bits {
5068 u8 reserved_at_8[0x18];
5072 u8 reserved_at_40[0x40];
5074 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5077 struct mlx5_ifc_query_flow_counter_in_bits {
5079 u8 reserved_at_10[0x10];
5081 u8 reserved_at_20[0x10];
5084 u8 reserved_at_40[0x80];
5087 u8 reserved_at_c1[0xf];
5088 u8 num_of_counters[0x10];
5090 u8 flow_counter_id[0x20];
5093 struct mlx5_ifc_query_esw_vport_context_out_bits {
5095 u8 reserved_at_8[0x18];
5099 u8 reserved_at_40[0x40];
5101 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5104 struct mlx5_ifc_query_esw_vport_context_in_bits {
5106 u8 reserved_at_10[0x10];
5108 u8 reserved_at_20[0x10];
5111 u8 other_vport[0x1];
5112 u8 reserved_at_41[0xf];
5113 u8 vport_number[0x10];
5115 u8 reserved_at_60[0x20];
5118 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5120 u8 reserved_at_8[0x18];
5124 u8 reserved_at_40[0x40];
5127 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5128 u8 reserved_at_0[0x1b];
5129 u8 fdb_to_vport_reg_c_id[0x1];
5130 u8 vport_cvlan_insert[0x1];
5131 u8 vport_svlan_insert[0x1];
5132 u8 vport_cvlan_strip[0x1];
5133 u8 vport_svlan_strip[0x1];
5136 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5138 u8 reserved_at_10[0x10];
5140 u8 reserved_at_20[0x10];
5143 u8 other_vport[0x1];
5144 u8 reserved_at_41[0xf];
5145 u8 vport_number[0x10];
5147 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5149 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5152 struct mlx5_ifc_query_eq_out_bits {
5154 u8 reserved_at_8[0x18];
5158 u8 reserved_at_40[0x40];
5160 struct mlx5_ifc_eqc_bits eq_context_entry;
5162 u8 reserved_at_280[0x40];
5164 u8 event_bitmask[0x40];
5166 u8 reserved_at_300[0x580];
5171 struct mlx5_ifc_query_eq_in_bits {
5173 u8 reserved_at_10[0x10];
5175 u8 reserved_at_20[0x10];
5178 u8 reserved_at_40[0x18];
5181 u8 reserved_at_60[0x20];
5184 struct mlx5_ifc_packet_reformat_context_in_bits {
5185 u8 reserved_at_0[0x5];
5186 u8 reformat_type[0x3];
5187 u8 reserved_at_8[0xe];
5188 u8 reformat_data_size[0xa];
5190 u8 reserved_at_20[0x10];
5191 u8 reformat_data[2][0x8];
5193 u8 more_reformat_data[0][0x8];
5196 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5198 u8 reserved_at_8[0x18];
5202 u8 reserved_at_40[0xa0];
5204 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5207 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5209 u8 reserved_at_10[0x10];
5211 u8 reserved_at_20[0x10];
5214 u8 packet_reformat_id[0x20];
5216 u8 reserved_at_60[0xa0];
5219 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5221 u8 reserved_at_8[0x18];
5225 u8 packet_reformat_id[0x20];
5227 u8 reserved_at_60[0x20];
5231 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5232 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5233 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5234 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5235 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5238 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5240 u8 reserved_at_10[0x10];
5242 u8 reserved_at_20[0x10];
5245 u8 reserved_at_40[0xa0];
5247 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5250 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5252 u8 reserved_at_8[0x18];
5256 u8 reserved_at_40[0x40];
5259 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5261 u8 reserved_at_10[0x10];
5263 u8 reserved_20[0x10];
5266 u8 packet_reformat_id[0x20];
5268 u8 reserved_60[0x20];
5271 struct mlx5_ifc_set_action_in_bits {
5272 u8 action_type[0x4];
5274 u8 reserved_at_10[0x3];
5276 u8 reserved_at_18[0x3];
5282 struct mlx5_ifc_add_action_in_bits {
5283 u8 action_type[0x4];
5285 u8 reserved_at_10[0x10];
5290 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5291 struct mlx5_ifc_set_action_in_bits set_action_in;
5292 struct mlx5_ifc_add_action_in_bits add_action_in;
5293 u8 reserved_at_0[0x40];
5297 MLX5_ACTION_TYPE_SET = 0x1,
5298 MLX5_ACTION_TYPE_ADD = 0x2,
5302 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5303 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5304 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5305 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5306 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5307 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5308 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5309 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5310 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5311 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5312 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5313 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5314 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5315 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5316 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5317 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5318 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5319 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5320 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5321 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5322 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5323 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5324 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5325 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5326 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5329 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5331 u8 reserved_at_8[0x18];
5335 u8 modify_header_id[0x20];
5337 u8 reserved_at_60[0x20];
5340 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5342 u8 reserved_at_10[0x10];
5344 u8 reserved_at_20[0x10];
5347 u8 reserved_at_40[0x20];
5350 u8 reserved_at_68[0x10];
5351 u8 num_of_actions[0x8];
5353 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5356 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5358 u8 reserved_at_8[0x18];
5362 u8 reserved_at_40[0x40];
5365 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5367 u8 reserved_at_10[0x10];
5369 u8 reserved_at_20[0x10];
5372 u8 modify_header_id[0x20];
5374 u8 reserved_at_60[0x20];
5377 struct mlx5_ifc_query_dct_out_bits {
5379 u8 reserved_at_8[0x18];
5383 u8 reserved_at_40[0x40];
5385 struct mlx5_ifc_dctc_bits dct_context_entry;
5387 u8 reserved_at_280[0x180];
5390 struct mlx5_ifc_query_dct_in_bits {
5392 u8 reserved_at_10[0x10];
5394 u8 reserved_at_20[0x10];
5397 u8 reserved_at_40[0x8];
5400 u8 reserved_at_60[0x20];
5403 struct mlx5_ifc_query_cq_out_bits {
5405 u8 reserved_at_8[0x18];
5409 u8 reserved_at_40[0x40];
5411 struct mlx5_ifc_cqc_bits cq_context;
5413 u8 reserved_at_280[0x600];
5418 struct mlx5_ifc_query_cq_in_bits {
5420 u8 reserved_at_10[0x10];
5422 u8 reserved_at_20[0x10];
5425 u8 reserved_at_40[0x8];
5428 u8 reserved_at_60[0x20];
5431 struct mlx5_ifc_query_cong_status_out_bits {
5433 u8 reserved_at_8[0x18];
5437 u8 reserved_at_40[0x20];
5441 u8 reserved_at_62[0x1e];
5444 struct mlx5_ifc_query_cong_status_in_bits {
5446 u8 reserved_at_10[0x10];
5448 u8 reserved_at_20[0x10];
5451 u8 reserved_at_40[0x18];
5453 u8 cong_protocol[0x4];
5455 u8 reserved_at_60[0x20];
5458 struct mlx5_ifc_query_cong_statistics_out_bits {
5460 u8 reserved_at_8[0x18];
5464 u8 reserved_at_40[0x40];
5466 u8 rp_cur_flows[0x20];
5470 u8 rp_cnp_ignored_high[0x20];
5472 u8 rp_cnp_ignored_low[0x20];
5474 u8 rp_cnp_handled_high[0x20];
5476 u8 rp_cnp_handled_low[0x20];
5478 u8 reserved_at_140[0x100];
5480 u8 time_stamp_high[0x20];
5482 u8 time_stamp_low[0x20];
5484 u8 accumulators_period[0x20];
5486 u8 np_ecn_marked_roce_packets_high[0x20];
5488 u8 np_ecn_marked_roce_packets_low[0x20];
5490 u8 np_cnp_sent_high[0x20];
5492 u8 np_cnp_sent_low[0x20];
5494 u8 reserved_at_320[0x560];
5497 struct mlx5_ifc_query_cong_statistics_in_bits {
5499 u8 reserved_at_10[0x10];
5501 u8 reserved_at_20[0x10];
5505 u8 reserved_at_41[0x1f];
5507 u8 reserved_at_60[0x20];
5510 struct mlx5_ifc_query_cong_params_out_bits {
5512 u8 reserved_at_8[0x18];
5516 u8 reserved_at_40[0x40];
5518 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5521 struct mlx5_ifc_query_cong_params_in_bits {
5523 u8 reserved_at_10[0x10];
5525 u8 reserved_at_20[0x10];
5528 u8 reserved_at_40[0x1c];
5529 u8 cong_protocol[0x4];
5531 u8 reserved_at_60[0x20];
5534 struct mlx5_ifc_query_adapter_out_bits {
5536 u8 reserved_at_8[0x18];
5540 u8 reserved_at_40[0x40];
5542 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5545 struct mlx5_ifc_query_adapter_in_bits {
5547 u8 reserved_at_10[0x10];
5549 u8 reserved_at_20[0x10];
5552 u8 reserved_at_40[0x40];
5555 struct mlx5_ifc_qp_2rst_out_bits {
5557 u8 reserved_at_8[0x18];
5561 u8 reserved_at_40[0x40];
5564 struct mlx5_ifc_qp_2rst_in_bits {
5568 u8 reserved_at_20[0x10];
5571 u8 reserved_at_40[0x8];
5574 u8 reserved_at_60[0x20];
5577 struct mlx5_ifc_qp_2err_out_bits {
5579 u8 reserved_at_8[0x18];
5583 u8 reserved_at_40[0x40];
5586 struct mlx5_ifc_qp_2err_in_bits {
5590 u8 reserved_at_20[0x10];
5593 u8 reserved_at_40[0x8];
5596 u8 reserved_at_60[0x20];
5599 struct mlx5_ifc_page_fault_resume_out_bits {
5601 u8 reserved_at_8[0x18];
5605 u8 reserved_at_40[0x40];
5608 struct mlx5_ifc_page_fault_resume_in_bits {
5610 u8 reserved_at_10[0x10];
5612 u8 reserved_at_20[0x10];
5616 u8 reserved_at_41[0x4];
5617 u8 page_fault_type[0x3];
5620 u8 reserved_at_60[0x8];
5624 struct mlx5_ifc_nop_out_bits {
5626 u8 reserved_at_8[0x18];
5630 u8 reserved_at_40[0x40];
5633 struct mlx5_ifc_nop_in_bits {
5635 u8 reserved_at_10[0x10];
5637 u8 reserved_at_20[0x10];
5640 u8 reserved_at_40[0x40];
5643 struct mlx5_ifc_modify_vport_state_out_bits {
5645 u8 reserved_at_8[0x18];
5649 u8 reserved_at_40[0x40];
5652 struct mlx5_ifc_modify_vport_state_in_bits {
5654 u8 reserved_at_10[0x10];
5656 u8 reserved_at_20[0x10];
5659 u8 other_vport[0x1];
5660 u8 reserved_at_41[0xf];
5661 u8 vport_number[0x10];
5663 u8 reserved_at_60[0x18];
5664 u8 admin_state[0x4];
5665 u8 reserved_at_7c[0x4];
5668 struct mlx5_ifc_modify_tis_out_bits {
5670 u8 reserved_at_8[0x18];
5674 u8 reserved_at_40[0x40];
5677 struct mlx5_ifc_modify_tis_bitmask_bits {
5678 u8 reserved_at_0[0x20];
5680 u8 reserved_at_20[0x1d];
5681 u8 lag_tx_port_affinity[0x1];
5682 u8 strict_lag_tx_port_affinity[0x1];
5686 struct mlx5_ifc_modify_tis_in_bits {
5690 u8 reserved_at_20[0x10];
5693 u8 reserved_at_40[0x8];
5696 u8 reserved_at_60[0x20];
5698 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5700 u8 reserved_at_c0[0x40];
5702 struct mlx5_ifc_tisc_bits ctx;
5705 struct mlx5_ifc_modify_tir_bitmask_bits {
5706 u8 reserved_at_0[0x20];
5708 u8 reserved_at_20[0x1b];
5710 u8 reserved_at_3c[0x1];
5712 u8 reserved_at_3e[0x1];
5716 struct mlx5_ifc_modify_tir_out_bits {
5718 u8 reserved_at_8[0x18];
5722 u8 reserved_at_40[0x40];
5725 struct mlx5_ifc_modify_tir_in_bits {
5729 u8 reserved_at_20[0x10];
5732 u8 reserved_at_40[0x8];
5735 u8 reserved_at_60[0x20];
5737 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5739 u8 reserved_at_c0[0x40];
5741 struct mlx5_ifc_tirc_bits ctx;
5744 struct mlx5_ifc_modify_sq_out_bits {
5746 u8 reserved_at_8[0x18];
5750 u8 reserved_at_40[0x40];
5753 struct mlx5_ifc_modify_sq_in_bits {
5757 u8 reserved_at_20[0x10];
5761 u8 reserved_at_44[0x4];
5764 u8 reserved_at_60[0x20];
5766 u8 modify_bitmask[0x40];
5768 u8 reserved_at_c0[0x40];
5770 struct mlx5_ifc_sqc_bits ctx;
5773 struct mlx5_ifc_modify_scheduling_element_out_bits {
5775 u8 reserved_at_8[0x18];
5779 u8 reserved_at_40[0x1c0];
5783 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5784 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5787 struct mlx5_ifc_modify_scheduling_element_in_bits {
5789 u8 reserved_at_10[0x10];
5791 u8 reserved_at_20[0x10];
5794 u8 scheduling_hierarchy[0x8];
5795 u8 reserved_at_48[0x18];
5797 u8 scheduling_element_id[0x20];
5799 u8 reserved_at_80[0x20];
5801 u8 modify_bitmask[0x20];
5803 u8 reserved_at_c0[0x40];
5805 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5807 u8 reserved_at_300[0x100];
5810 struct mlx5_ifc_modify_rqt_out_bits {
5812 u8 reserved_at_8[0x18];
5816 u8 reserved_at_40[0x40];
5819 struct mlx5_ifc_rqt_bitmask_bits {
5820 u8 reserved_at_0[0x20];
5822 u8 reserved_at_20[0x1f];
5826 struct mlx5_ifc_modify_rqt_in_bits {
5830 u8 reserved_at_20[0x10];
5833 u8 reserved_at_40[0x8];
5836 u8 reserved_at_60[0x20];
5838 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5840 u8 reserved_at_c0[0x40];
5842 struct mlx5_ifc_rqtc_bits ctx;
5845 struct mlx5_ifc_modify_rq_out_bits {
5847 u8 reserved_at_8[0x18];
5851 u8 reserved_at_40[0x40];
5855 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5856 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5857 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5860 struct mlx5_ifc_modify_rq_in_bits {
5864 u8 reserved_at_20[0x10];
5868 u8 reserved_at_44[0x4];
5871 u8 reserved_at_60[0x20];
5873 u8 modify_bitmask[0x40];
5875 u8 reserved_at_c0[0x40];
5877 struct mlx5_ifc_rqc_bits ctx;
5880 struct mlx5_ifc_modify_rmp_out_bits {
5882 u8 reserved_at_8[0x18];
5886 u8 reserved_at_40[0x40];
5889 struct mlx5_ifc_rmp_bitmask_bits {
5890 u8 reserved_at_0[0x20];
5892 u8 reserved_at_20[0x1f];
5896 struct mlx5_ifc_modify_rmp_in_bits {
5900 u8 reserved_at_20[0x10];
5904 u8 reserved_at_44[0x4];
5907 u8 reserved_at_60[0x20];
5909 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5911 u8 reserved_at_c0[0x40];
5913 struct mlx5_ifc_rmpc_bits ctx;
5916 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5918 u8 reserved_at_8[0x18];
5922 u8 reserved_at_40[0x40];
5925 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5926 u8 reserved_at_0[0x12];
5927 u8 affiliation[0x1];
5928 u8 reserved_at_13[0x1];
5929 u8 disable_uc_local_lb[0x1];
5930 u8 disable_mc_local_lb[0x1];
5935 u8 change_event[0x1];
5937 u8 permanent_address[0x1];
5938 u8 addresses_list[0x1];
5940 u8 reserved_at_1f[0x1];
5943 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5945 u8 reserved_at_10[0x10];
5947 u8 reserved_at_20[0x10];
5950 u8 other_vport[0x1];
5951 u8 reserved_at_41[0xf];
5952 u8 vport_number[0x10];
5954 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5956 u8 reserved_at_80[0x780];
5958 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5961 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5963 u8 reserved_at_8[0x18];
5967 u8 reserved_at_40[0x40];
5970 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5972 u8 reserved_at_10[0x10];
5974 u8 reserved_at_20[0x10];
5977 u8 other_vport[0x1];
5978 u8 reserved_at_41[0xb];
5980 u8 vport_number[0x10];
5982 u8 reserved_at_60[0x20];
5984 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5987 struct mlx5_ifc_modify_cq_out_bits {
5989 u8 reserved_at_8[0x18];
5993 u8 reserved_at_40[0x40];
5997 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5998 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6001 struct mlx5_ifc_modify_cq_in_bits {
6005 u8 reserved_at_20[0x10];
6008 u8 reserved_at_40[0x8];
6011 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6013 struct mlx5_ifc_cqc_bits cq_context;
6015 u8 reserved_at_280[0x60];
6017 u8 cq_umem_valid[0x1];
6018 u8 reserved_at_2e1[0x1f];
6020 u8 reserved_at_300[0x580];
6025 struct mlx5_ifc_modify_cong_status_out_bits {
6027 u8 reserved_at_8[0x18];
6031 u8 reserved_at_40[0x40];
6034 struct mlx5_ifc_modify_cong_status_in_bits {
6036 u8 reserved_at_10[0x10];
6038 u8 reserved_at_20[0x10];
6041 u8 reserved_at_40[0x18];
6043 u8 cong_protocol[0x4];
6047 u8 reserved_at_62[0x1e];
6050 struct mlx5_ifc_modify_cong_params_out_bits {
6052 u8 reserved_at_8[0x18];
6056 u8 reserved_at_40[0x40];
6059 struct mlx5_ifc_modify_cong_params_in_bits {
6061 u8 reserved_at_10[0x10];
6063 u8 reserved_at_20[0x10];
6066 u8 reserved_at_40[0x1c];
6067 u8 cong_protocol[0x4];
6069 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6071 u8 reserved_at_80[0x80];
6073 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6076 struct mlx5_ifc_manage_pages_out_bits {
6078 u8 reserved_at_8[0x18];
6082 u8 output_num_entries[0x20];
6084 u8 reserved_at_60[0x20];
6090 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6091 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6092 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6095 struct mlx5_ifc_manage_pages_in_bits {
6097 u8 reserved_at_10[0x10];
6099 u8 reserved_at_20[0x10];
6102 u8 embedded_cpu_function[0x1];
6103 u8 reserved_at_41[0xf];
6104 u8 function_id[0x10];
6106 u8 input_num_entries[0x20];
6111 struct mlx5_ifc_mad_ifc_out_bits {
6113 u8 reserved_at_8[0x18];
6117 u8 reserved_at_40[0x40];
6119 u8 response_mad_packet[256][0x8];
6122 struct mlx5_ifc_mad_ifc_in_bits {
6124 u8 reserved_at_10[0x10];
6126 u8 reserved_at_20[0x10];
6129 u8 remote_lid[0x10];
6130 u8 reserved_at_50[0x8];
6133 u8 reserved_at_60[0x20];
6138 struct mlx5_ifc_init_hca_out_bits {
6140 u8 reserved_at_8[0x18];
6144 u8 reserved_at_40[0x40];
6147 struct mlx5_ifc_init_hca_in_bits {
6149 u8 reserved_at_10[0x10];
6151 u8 reserved_at_20[0x10];
6154 u8 reserved_at_40[0x40];
6155 u8 sw_owner_id[4][0x20];
6158 struct mlx5_ifc_init2rtr_qp_out_bits {
6160 u8 reserved_at_8[0x18];
6164 u8 reserved_at_40[0x40];
6167 struct mlx5_ifc_init2rtr_qp_in_bits {
6171 u8 reserved_at_20[0x10];
6174 u8 reserved_at_40[0x8];
6177 u8 reserved_at_60[0x20];
6179 u8 opt_param_mask[0x20];
6181 u8 reserved_at_a0[0x20];
6183 struct mlx5_ifc_qpc_bits qpc;
6185 u8 reserved_at_800[0x80];
6188 struct mlx5_ifc_init2init_qp_out_bits {
6190 u8 reserved_at_8[0x18];
6194 u8 reserved_at_40[0x40];
6197 struct mlx5_ifc_init2init_qp_in_bits {
6201 u8 reserved_at_20[0x10];
6204 u8 reserved_at_40[0x8];
6207 u8 reserved_at_60[0x20];
6209 u8 opt_param_mask[0x20];
6211 u8 reserved_at_a0[0x20];
6213 struct mlx5_ifc_qpc_bits qpc;
6215 u8 reserved_at_800[0x80];
6218 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6220 u8 reserved_at_8[0x18];
6224 u8 reserved_at_40[0x40];
6226 u8 packet_headers_log[128][0x8];
6228 u8 packet_syndrome[64][0x8];
6231 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6233 u8 reserved_at_10[0x10];
6235 u8 reserved_at_20[0x10];
6238 u8 reserved_at_40[0x40];
6241 struct mlx5_ifc_gen_eqe_in_bits {
6243 u8 reserved_at_10[0x10];
6245 u8 reserved_at_20[0x10];
6248 u8 reserved_at_40[0x18];
6251 u8 reserved_at_60[0x20];
6256 struct mlx5_ifc_gen_eq_out_bits {
6258 u8 reserved_at_8[0x18];
6262 u8 reserved_at_40[0x40];
6265 struct mlx5_ifc_enable_hca_out_bits {
6267 u8 reserved_at_8[0x18];
6271 u8 reserved_at_40[0x20];
6274 struct mlx5_ifc_enable_hca_in_bits {
6276 u8 reserved_at_10[0x10];
6278 u8 reserved_at_20[0x10];
6281 u8 embedded_cpu_function[0x1];
6282 u8 reserved_at_41[0xf];
6283 u8 function_id[0x10];
6285 u8 reserved_at_60[0x20];
6288 struct mlx5_ifc_drain_dct_out_bits {
6290 u8 reserved_at_8[0x18];
6294 u8 reserved_at_40[0x40];
6297 struct mlx5_ifc_drain_dct_in_bits {
6301 u8 reserved_at_20[0x10];
6304 u8 reserved_at_40[0x8];
6307 u8 reserved_at_60[0x20];
6310 struct mlx5_ifc_disable_hca_out_bits {
6312 u8 reserved_at_8[0x18];
6316 u8 reserved_at_40[0x20];
6319 struct mlx5_ifc_disable_hca_in_bits {
6321 u8 reserved_at_10[0x10];
6323 u8 reserved_at_20[0x10];
6326 u8 embedded_cpu_function[0x1];
6327 u8 reserved_at_41[0xf];
6328 u8 function_id[0x10];
6330 u8 reserved_at_60[0x20];
6333 struct mlx5_ifc_detach_from_mcg_out_bits {
6335 u8 reserved_at_8[0x18];
6339 u8 reserved_at_40[0x40];
6342 struct mlx5_ifc_detach_from_mcg_in_bits {
6346 u8 reserved_at_20[0x10];
6349 u8 reserved_at_40[0x8];
6352 u8 reserved_at_60[0x20];
6354 u8 multicast_gid[16][0x8];
6357 struct mlx5_ifc_destroy_xrq_out_bits {
6359 u8 reserved_at_8[0x18];
6363 u8 reserved_at_40[0x40];
6366 struct mlx5_ifc_destroy_xrq_in_bits {
6370 u8 reserved_at_20[0x10];
6373 u8 reserved_at_40[0x8];
6376 u8 reserved_at_60[0x20];
6379 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6381 u8 reserved_at_8[0x18];
6385 u8 reserved_at_40[0x40];
6388 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6392 u8 reserved_at_20[0x10];
6395 u8 reserved_at_40[0x8];
6398 u8 reserved_at_60[0x20];
6401 struct mlx5_ifc_destroy_tis_out_bits {
6403 u8 reserved_at_8[0x18];
6407 u8 reserved_at_40[0x40];
6410 struct mlx5_ifc_destroy_tis_in_bits {
6414 u8 reserved_at_20[0x10];
6417 u8 reserved_at_40[0x8];
6420 u8 reserved_at_60[0x20];
6423 struct mlx5_ifc_destroy_tir_out_bits {
6425 u8 reserved_at_8[0x18];
6429 u8 reserved_at_40[0x40];
6432 struct mlx5_ifc_destroy_tir_in_bits {
6436 u8 reserved_at_20[0x10];
6439 u8 reserved_at_40[0x8];
6442 u8 reserved_at_60[0x20];
6445 struct mlx5_ifc_destroy_srq_out_bits {
6447 u8 reserved_at_8[0x18];
6451 u8 reserved_at_40[0x40];
6454 struct mlx5_ifc_destroy_srq_in_bits {
6458 u8 reserved_at_20[0x10];
6461 u8 reserved_at_40[0x8];
6464 u8 reserved_at_60[0x20];
6467 struct mlx5_ifc_destroy_sq_out_bits {
6469 u8 reserved_at_8[0x18];
6473 u8 reserved_at_40[0x40];
6476 struct mlx5_ifc_destroy_sq_in_bits {
6480 u8 reserved_at_20[0x10];
6483 u8 reserved_at_40[0x8];
6486 u8 reserved_at_60[0x20];
6489 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6491 u8 reserved_at_8[0x18];
6495 u8 reserved_at_40[0x1c0];
6498 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6500 u8 reserved_at_10[0x10];
6502 u8 reserved_at_20[0x10];
6505 u8 scheduling_hierarchy[0x8];
6506 u8 reserved_at_48[0x18];
6508 u8 scheduling_element_id[0x20];
6510 u8 reserved_at_80[0x180];
6513 struct mlx5_ifc_destroy_rqt_out_bits {
6515 u8 reserved_at_8[0x18];
6519 u8 reserved_at_40[0x40];
6522 struct mlx5_ifc_destroy_rqt_in_bits {
6526 u8 reserved_at_20[0x10];
6529 u8 reserved_at_40[0x8];
6532 u8 reserved_at_60[0x20];
6535 struct mlx5_ifc_destroy_rq_out_bits {
6537 u8 reserved_at_8[0x18];
6541 u8 reserved_at_40[0x40];
6544 struct mlx5_ifc_destroy_rq_in_bits {
6548 u8 reserved_at_20[0x10];
6551 u8 reserved_at_40[0x8];
6554 u8 reserved_at_60[0x20];
6557 struct mlx5_ifc_set_delay_drop_params_in_bits {
6559 u8 reserved_at_10[0x10];
6561 u8 reserved_at_20[0x10];
6564 u8 reserved_at_40[0x20];
6566 u8 reserved_at_60[0x10];
6567 u8 delay_drop_timeout[0x10];
6570 struct mlx5_ifc_set_delay_drop_params_out_bits {
6572 u8 reserved_at_8[0x18];
6576 u8 reserved_at_40[0x40];
6579 struct mlx5_ifc_destroy_rmp_out_bits {
6581 u8 reserved_at_8[0x18];
6585 u8 reserved_at_40[0x40];
6588 struct mlx5_ifc_destroy_rmp_in_bits {
6592 u8 reserved_at_20[0x10];
6595 u8 reserved_at_40[0x8];
6598 u8 reserved_at_60[0x20];
6601 struct mlx5_ifc_destroy_qp_out_bits {
6603 u8 reserved_at_8[0x18];
6607 u8 reserved_at_40[0x40];
6610 struct mlx5_ifc_destroy_qp_in_bits {
6614 u8 reserved_at_20[0x10];
6617 u8 reserved_at_40[0x8];
6620 u8 reserved_at_60[0x20];
6623 struct mlx5_ifc_destroy_psv_out_bits {
6625 u8 reserved_at_8[0x18];
6629 u8 reserved_at_40[0x40];
6632 struct mlx5_ifc_destroy_psv_in_bits {
6634 u8 reserved_at_10[0x10];
6636 u8 reserved_at_20[0x10];
6639 u8 reserved_at_40[0x8];
6642 u8 reserved_at_60[0x20];
6645 struct mlx5_ifc_destroy_mkey_out_bits {
6647 u8 reserved_at_8[0x18];
6651 u8 reserved_at_40[0x40];
6654 struct mlx5_ifc_destroy_mkey_in_bits {
6656 u8 reserved_at_10[0x10];
6658 u8 reserved_at_20[0x10];
6661 u8 reserved_at_40[0x8];
6662 u8 mkey_index[0x18];
6664 u8 reserved_at_60[0x20];
6667 struct mlx5_ifc_destroy_flow_table_out_bits {
6669 u8 reserved_at_8[0x18];
6673 u8 reserved_at_40[0x40];
6676 struct mlx5_ifc_destroy_flow_table_in_bits {
6678 u8 reserved_at_10[0x10];
6680 u8 reserved_at_20[0x10];
6683 u8 other_vport[0x1];
6684 u8 reserved_at_41[0xf];
6685 u8 vport_number[0x10];
6687 u8 reserved_at_60[0x20];
6690 u8 reserved_at_88[0x18];
6692 u8 reserved_at_a0[0x8];
6695 u8 reserved_at_c0[0x140];
6698 struct mlx5_ifc_destroy_flow_group_out_bits {
6700 u8 reserved_at_8[0x18];
6704 u8 reserved_at_40[0x40];
6707 struct mlx5_ifc_destroy_flow_group_in_bits {
6709 u8 reserved_at_10[0x10];
6711 u8 reserved_at_20[0x10];
6714 u8 other_vport[0x1];
6715 u8 reserved_at_41[0xf];
6716 u8 vport_number[0x10];
6718 u8 reserved_at_60[0x20];
6721 u8 reserved_at_88[0x18];
6723 u8 reserved_at_a0[0x8];
6728 u8 reserved_at_e0[0x120];
6731 struct mlx5_ifc_destroy_eq_out_bits {
6733 u8 reserved_at_8[0x18];
6737 u8 reserved_at_40[0x40];
6740 struct mlx5_ifc_destroy_eq_in_bits {
6742 u8 reserved_at_10[0x10];
6744 u8 reserved_at_20[0x10];
6747 u8 reserved_at_40[0x18];
6750 u8 reserved_at_60[0x20];
6753 struct mlx5_ifc_destroy_dct_out_bits {
6755 u8 reserved_at_8[0x18];
6759 u8 reserved_at_40[0x40];
6762 struct mlx5_ifc_destroy_dct_in_bits {
6766 u8 reserved_at_20[0x10];
6769 u8 reserved_at_40[0x8];
6772 u8 reserved_at_60[0x20];
6775 struct mlx5_ifc_destroy_cq_out_bits {
6777 u8 reserved_at_8[0x18];
6781 u8 reserved_at_40[0x40];
6784 struct mlx5_ifc_destroy_cq_in_bits {
6788 u8 reserved_at_20[0x10];
6791 u8 reserved_at_40[0x8];
6794 u8 reserved_at_60[0x20];
6797 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6799 u8 reserved_at_8[0x18];
6803 u8 reserved_at_40[0x40];
6806 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6808 u8 reserved_at_10[0x10];
6810 u8 reserved_at_20[0x10];
6813 u8 reserved_at_40[0x20];
6815 u8 reserved_at_60[0x10];
6816 u8 vxlan_udp_port[0x10];
6819 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6821 u8 reserved_at_8[0x18];
6825 u8 reserved_at_40[0x40];
6828 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6830 u8 reserved_at_10[0x10];
6832 u8 reserved_at_20[0x10];
6835 u8 reserved_at_40[0x60];
6837 u8 reserved_at_a0[0x8];
6838 u8 table_index[0x18];
6840 u8 reserved_at_c0[0x140];
6843 struct mlx5_ifc_delete_fte_out_bits {
6845 u8 reserved_at_8[0x18];
6849 u8 reserved_at_40[0x40];
6852 struct mlx5_ifc_delete_fte_in_bits {
6854 u8 reserved_at_10[0x10];
6856 u8 reserved_at_20[0x10];
6859 u8 other_vport[0x1];
6860 u8 reserved_at_41[0xf];
6861 u8 vport_number[0x10];
6863 u8 reserved_at_60[0x20];
6866 u8 reserved_at_88[0x18];
6868 u8 reserved_at_a0[0x8];
6871 u8 reserved_at_c0[0x40];
6873 u8 flow_index[0x20];
6875 u8 reserved_at_120[0xe0];
6878 struct mlx5_ifc_dealloc_xrcd_out_bits {
6880 u8 reserved_at_8[0x18];
6884 u8 reserved_at_40[0x40];
6887 struct mlx5_ifc_dealloc_xrcd_in_bits {
6891 u8 reserved_at_20[0x10];
6894 u8 reserved_at_40[0x8];
6897 u8 reserved_at_60[0x20];
6900 struct mlx5_ifc_dealloc_uar_out_bits {
6902 u8 reserved_at_8[0x18];
6906 u8 reserved_at_40[0x40];
6909 struct mlx5_ifc_dealloc_uar_in_bits {
6911 u8 reserved_at_10[0x10];
6913 u8 reserved_at_20[0x10];
6916 u8 reserved_at_40[0x8];
6919 u8 reserved_at_60[0x20];
6922 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6924 u8 reserved_at_8[0x18];
6928 u8 reserved_at_40[0x40];
6931 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6935 u8 reserved_at_20[0x10];
6938 u8 reserved_at_40[0x8];
6939 u8 transport_domain[0x18];
6941 u8 reserved_at_60[0x20];
6944 struct mlx5_ifc_dealloc_q_counter_out_bits {
6946 u8 reserved_at_8[0x18];
6950 u8 reserved_at_40[0x40];
6953 struct mlx5_ifc_dealloc_q_counter_in_bits {
6955 u8 reserved_at_10[0x10];
6957 u8 reserved_at_20[0x10];
6960 u8 reserved_at_40[0x18];
6961 u8 counter_set_id[0x8];
6963 u8 reserved_at_60[0x20];
6966 struct mlx5_ifc_dealloc_pd_out_bits {
6968 u8 reserved_at_8[0x18];
6972 u8 reserved_at_40[0x40];
6975 struct mlx5_ifc_dealloc_pd_in_bits {
6979 u8 reserved_at_20[0x10];
6982 u8 reserved_at_40[0x8];
6985 u8 reserved_at_60[0x20];
6988 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6990 u8 reserved_at_8[0x18];
6994 u8 reserved_at_40[0x40];
6997 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6999 u8 reserved_at_10[0x10];
7001 u8 reserved_at_20[0x10];
7004 u8 flow_counter_id[0x20];
7006 u8 reserved_at_60[0x20];
7009 struct mlx5_ifc_create_xrq_out_bits {
7011 u8 reserved_at_8[0x18];
7015 u8 reserved_at_40[0x8];
7018 u8 reserved_at_60[0x20];
7021 struct mlx5_ifc_create_xrq_in_bits {
7025 u8 reserved_at_20[0x10];
7028 u8 reserved_at_40[0x40];
7030 struct mlx5_ifc_xrqc_bits xrq_context;
7033 struct mlx5_ifc_create_xrc_srq_out_bits {
7035 u8 reserved_at_8[0x18];
7039 u8 reserved_at_40[0x8];
7042 u8 reserved_at_60[0x20];
7045 struct mlx5_ifc_create_xrc_srq_in_bits {
7049 u8 reserved_at_20[0x10];
7052 u8 reserved_at_40[0x40];
7054 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7056 u8 reserved_at_280[0x60];
7058 u8 xrc_srq_umem_valid[0x1];
7059 u8 reserved_at_2e1[0x1f];
7061 u8 reserved_at_300[0x580];
7066 struct mlx5_ifc_create_tis_out_bits {
7068 u8 reserved_at_8[0x18];
7072 u8 reserved_at_40[0x8];
7075 u8 reserved_at_60[0x20];
7078 struct mlx5_ifc_create_tis_in_bits {
7082 u8 reserved_at_20[0x10];
7085 u8 reserved_at_40[0xc0];
7087 struct mlx5_ifc_tisc_bits ctx;
7090 struct mlx5_ifc_create_tir_out_bits {
7092 u8 icm_address_63_40[0x18];
7096 u8 icm_address_39_32[0x8];
7099 u8 icm_address_31_0[0x20];
7102 struct mlx5_ifc_create_tir_in_bits {
7106 u8 reserved_at_20[0x10];
7109 u8 reserved_at_40[0xc0];
7111 struct mlx5_ifc_tirc_bits ctx;
7114 struct mlx5_ifc_create_srq_out_bits {
7116 u8 reserved_at_8[0x18];
7120 u8 reserved_at_40[0x8];
7123 u8 reserved_at_60[0x20];
7126 struct mlx5_ifc_create_srq_in_bits {
7130 u8 reserved_at_20[0x10];
7133 u8 reserved_at_40[0x40];
7135 struct mlx5_ifc_srqc_bits srq_context_entry;
7137 u8 reserved_at_280[0x600];
7142 struct mlx5_ifc_create_sq_out_bits {
7144 u8 reserved_at_8[0x18];
7148 u8 reserved_at_40[0x8];
7151 u8 reserved_at_60[0x20];
7154 struct mlx5_ifc_create_sq_in_bits {
7158 u8 reserved_at_20[0x10];
7161 u8 reserved_at_40[0xc0];
7163 struct mlx5_ifc_sqc_bits ctx;
7166 struct mlx5_ifc_create_scheduling_element_out_bits {
7168 u8 reserved_at_8[0x18];
7172 u8 reserved_at_40[0x40];
7174 u8 scheduling_element_id[0x20];
7176 u8 reserved_at_a0[0x160];
7179 struct mlx5_ifc_create_scheduling_element_in_bits {
7181 u8 reserved_at_10[0x10];
7183 u8 reserved_at_20[0x10];
7186 u8 scheduling_hierarchy[0x8];
7187 u8 reserved_at_48[0x18];
7189 u8 reserved_at_60[0xa0];
7191 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7193 u8 reserved_at_300[0x100];
7196 struct mlx5_ifc_create_rqt_out_bits {
7198 u8 reserved_at_8[0x18];
7202 u8 reserved_at_40[0x8];
7205 u8 reserved_at_60[0x20];
7208 struct mlx5_ifc_create_rqt_in_bits {
7212 u8 reserved_at_20[0x10];
7215 u8 reserved_at_40[0xc0];
7217 struct mlx5_ifc_rqtc_bits rqt_context;
7220 struct mlx5_ifc_create_rq_out_bits {
7222 u8 reserved_at_8[0x18];
7226 u8 reserved_at_40[0x8];
7229 u8 reserved_at_60[0x20];
7232 struct mlx5_ifc_create_rq_in_bits {
7236 u8 reserved_at_20[0x10];
7239 u8 reserved_at_40[0xc0];
7241 struct mlx5_ifc_rqc_bits ctx;
7244 struct mlx5_ifc_create_rmp_out_bits {
7246 u8 reserved_at_8[0x18];
7250 u8 reserved_at_40[0x8];
7253 u8 reserved_at_60[0x20];
7256 struct mlx5_ifc_create_rmp_in_bits {
7260 u8 reserved_at_20[0x10];
7263 u8 reserved_at_40[0xc0];
7265 struct mlx5_ifc_rmpc_bits ctx;
7268 struct mlx5_ifc_create_qp_out_bits {
7270 u8 reserved_at_8[0x18];
7274 u8 reserved_at_40[0x8];
7277 u8 reserved_at_60[0x20];
7280 struct mlx5_ifc_create_qp_in_bits {
7284 u8 reserved_at_20[0x10];
7287 u8 reserved_at_40[0x40];
7289 u8 opt_param_mask[0x20];
7291 u8 reserved_at_a0[0x20];
7293 struct mlx5_ifc_qpc_bits qpc;
7295 u8 reserved_at_800[0x60];
7297 u8 wq_umem_valid[0x1];
7298 u8 reserved_at_861[0x1f];
7303 struct mlx5_ifc_create_psv_out_bits {
7305 u8 reserved_at_8[0x18];
7309 u8 reserved_at_40[0x40];
7311 u8 reserved_at_80[0x8];
7312 u8 psv0_index[0x18];
7314 u8 reserved_at_a0[0x8];
7315 u8 psv1_index[0x18];
7317 u8 reserved_at_c0[0x8];
7318 u8 psv2_index[0x18];
7320 u8 reserved_at_e0[0x8];
7321 u8 psv3_index[0x18];
7324 struct mlx5_ifc_create_psv_in_bits {
7326 u8 reserved_at_10[0x10];
7328 u8 reserved_at_20[0x10];
7332 u8 reserved_at_44[0x4];
7335 u8 reserved_at_60[0x20];
7338 struct mlx5_ifc_create_mkey_out_bits {
7340 u8 reserved_at_8[0x18];
7344 u8 reserved_at_40[0x8];
7345 u8 mkey_index[0x18];
7347 u8 reserved_at_60[0x20];
7350 struct mlx5_ifc_create_mkey_in_bits {
7352 u8 reserved_at_10[0x10];
7354 u8 reserved_at_20[0x10];
7357 u8 reserved_at_40[0x20];
7360 u8 mkey_umem_valid[0x1];
7361 u8 reserved_at_62[0x1e];
7363 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7365 u8 reserved_at_280[0x80];
7367 u8 translations_octword_actual_size[0x20];
7369 u8 reserved_at_320[0x560];
7371 u8 klm_pas_mtt[0][0x20];
7374 struct mlx5_ifc_create_flow_table_out_bits {
7376 u8 reserved_at_8[0x18];
7380 u8 reserved_at_40[0x8];
7383 u8 reserved_at_60[0x20];
7386 struct mlx5_ifc_flow_table_context_bits {
7387 u8 reformat_en[0x1];
7389 u8 reserved_at_2[0x1];
7390 u8 termination_table[0x1];
7391 u8 table_miss_action[0x4];
7393 u8 reserved_at_10[0x8];
7396 u8 reserved_at_20[0x8];
7397 u8 table_miss_id[0x18];
7399 u8 reserved_at_40[0x8];
7400 u8 lag_master_next_table_id[0x18];
7402 u8 reserved_at_60[0xe0];
7405 struct mlx5_ifc_create_flow_table_in_bits {
7407 u8 reserved_at_10[0x10];
7409 u8 reserved_at_20[0x10];
7412 u8 other_vport[0x1];
7413 u8 reserved_at_41[0xf];
7414 u8 vport_number[0x10];
7416 u8 reserved_at_60[0x20];
7419 u8 reserved_at_88[0x18];
7421 u8 reserved_at_a0[0x20];
7423 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7426 struct mlx5_ifc_create_flow_group_out_bits {
7428 u8 reserved_at_8[0x18];
7432 u8 reserved_at_40[0x8];
7435 u8 reserved_at_60[0x20];
7439 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7440 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7441 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7442 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7445 struct mlx5_ifc_create_flow_group_in_bits {
7447 u8 reserved_at_10[0x10];
7449 u8 reserved_at_20[0x10];
7452 u8 other_vport[0x1];
7453 u8 reserved_at_41[0xf];
7454 u8 vport_number[0x10];
7456 u8 reserved_at_60[0x20];
7459 u8 reserved_at_88[0x18];
7461 u8 reserved_at_a0[0x8];
7464 u8 source_eswitch_owner_vhca_id_valid[0x1];
7466 u8 reserved_at_c1[0x1f];
7468 u8 start_flow_index[0x20];
7470 u8 reserved_at_100[0x20];
7472 u8 end_flow_index[0x20];
7474 u8 reserved_at_140[0xa0];
7476 u8 reserved_at_1e0[0x18];
7477 u8 match_criteria_enable[0x8];
7479 struct mlx5_ifc_fte_match_param_bits match_criteria;
7481 u8 reserved_at_1200[0xe00];
7484 struct mlx5_ifc_create_eq_out_bits {
7486 u8 reserved_at_8[0x18];
7490 u8 reserved_at_40[0x18];
7493 u8 reserved_at_60[0x20];
7496 struct mlx5_ifc_create_eq_in_bits {
7500 u8 reserved_at_20[0x10];
7503 u8 reserved_at_40[0x40];
7505 struct mlx5_ifc_eqc_bits eq_context_entry;
7507 u8 reserved_at_280[0x40];
7509 u8 event_bitmask[4][0x40];
7511 u8 reserved_at_3c0[0x4c0];
7516 struct mlx5_ifc_create_dct_out_bits {
7518 u8 reserved_at_8[0x18];
7522 u8 reserved_at_40[0x8];
7525 u8 reserved_at_60[0x20];
7528 struct mlx5_ifc_create_dct_in_bits {
7532 u8 reserved_at_20[0x10];
7535 u8 reserved_at_40[0x40];
7537 struct mlx5_ifc_dctc_bits dct_context_entry;
7539 u8 reserved_at_280[0x180];
7542 struct mlx5_ifc_create_cq_out_bits {
7544 u8 reserved_at_8[0x18];
7548 u8 reserved_at_40[0x8];
7551 u8 reserved_at_60[0x20];
7554 struct mlx5_ifc_create_cq_in_bits {
7558 u8 reserved_at_20[0x10];
7561 u8 reserved_at_40[0x40];
7563 struct mlx5_ifc_cqc_bits cq_context;
7565 u8 reserved_at_280[0x60];
7567 u8 cq_umem_valid[0x1];
7568 u8 reserved_at_2e1[0x59f];
7573 struct mlx5_ifc_config_int_moderation_out_bits {
7575 u8 reserved_at_8[0x18];
7579 u8 reserved_at_40[0x4];
7581 u8 int_vector[0x10];
7583 u8 reserved_at_60[0x20];
7587 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7588 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7591 struct mlx5_ifc_config_int_moderation_in_bits {
7593 u8 reserved_at_10[0x10];
7595 u8 reserved_at_20[0x10];
7598 u8 reserved_at_40[0x4];
7600 u8 int_vector[0x10];
7602 u8 reserved_at_60[0x20];
7605 struct mlx5_ifc_attach_to_mcg_out_bits {
7607 u8 reserved_at_8[0x18];
7611 u8 reserved_at_40[0x40];
7614 struct mlx5_ifc_attach_to_mcg_in_bits {
7618 u8 reserved_at_20[0x10];
7621 u8 reserved_at_40[0x8];
7624 u8 reserved_at_60[0x20];
7626 u8 multicast_gid[16][0x8];
7629 struct mlx5_ifc_arm_xrq_out_bits {
7631 u8 reserved_at_8[0x18];
7635 u8 reserved_at_40[0x40];
7638 struct mlx5_ifc_arm_xrq_in_bits {
7640 u8 reserved_at_10[0x10];
7642 u8 reserved_at_20[0x10];
7645 u8 reserved_at_40[0x8];
7648 u8 reserved_at_60[0x10];
7652 struct mlx5_ifc_arm_xrc_srq_out_bits {
7654 u8 reserved_at_8[0x18];
7658 u8 reserved_at_40[0x40];
7662 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7665 struct mlx5_ifc_arm_xrc_srq_in_bits {
7669 u8 reserved_at_20[0x10];
7672 u8 reserved_at_40[0x8];
7675 u8 reserved_at_60[0x10];
7679 struct mlx5_ifc_arm_rq_out_bits {
7681 u8 reserved_at_8[0x18];
7685 u8 reserved_at_40[0x40];
7689 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7690 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7693 struct mlx5_ifc_arm_rq_in_bits {
7697 u8 reserved_at_20[0x10];
7700 u8 reserved_at_40[0x8];
7701 u8 srq_number[0x18];
7703 u8 reserved_at_60[0x10];
7707 struct mlx5_ifc_arm_dct_out_bits {
7709 u8 reserved_at_8[0x18];
7713 u8 reserved_at_40[0x40];
7716 struct mlx5_ifc_arm_dct_in_bits {
7718 u8 reserved_at_10[0x10];
7720 u8 reserved_at_20[0x10];
7723 u8 reserved_at_40[0x8];
7724 u8 dct_number[0x18];
7726 u8 reserved_at_60[0x20];
7729 struct mlx5_ifc_alloc_xrcd_out_bits {
7731 u8 reserved_at_8[0x18];
7735 u8 reserved_at_40[0x8];
7738 u8 reserved_at_60[0x20];
7741 struct mlx5_ifc_alloc_xrcd_in_bits {
7745 u8 reserved_at_20[0x10];
7748 u8 reserved_at_40[0x40];
7751 struct mlx5_ifc_alloc_uar_out_bits {
7753 u8 reserved_at_8[0x18];
7757 u8 reserved_at_40[0x8];
7760 u8 reserved_at_60[0x20];
7763 struct mlx5_ifc_alloc_uar_in_bits {
7765 u8 reserved_at_10[0x10];
7767 u8 reserved_at_20[0x10];
7770 u8 reserved_at_40[0x40];
7773 struct mlx5_ifc_alloc_transport_domain_out_bits {
7775 u8 reserved_at_8[0x18];
7779 u8 reserved_at_40[0x8];
7780 u8 transport_domain[0x18];
7782 u8 reserved_at_60[0x20];
7785 struct mlx5_ifc_alloc_transport_domain_in_bits {
7789 u8 reserved_at_20[0x10];
7792 u8 reserved_at_40[0x40];
7795 struct mlx5_ifc_alloc_q_counter_out_bits {
7797 u8 reserved_at_8[0x18];
7801 u8 reserved_at_40[0x18];
7802 u8 counter_set_id[0x8];
7804 u8 reserved_at_60[0x20];
7807 struct mlx5_ifc_alloc_q_counter_in_bits {
7811 u8 reserved_at_20[0x10];
7814 u8 reserved_at_40[0x40];
7817 struct mlx5_ifc_alloc_pd_out_bits {
7819 u8 reserved_at_8[0x18];
7823 u8 reserved_at_40[0x8];
7826 u8 reserved_at_60[0x20];
7829 struct mlx5_ifc_alloc_pd_in_bits {
7833 u8 reserved_at_20[0x10];
7836 u8 reserved_at_40[0x40];
7839 struct mlx5_ifc_alloc_flow_counter_out_bits {
7841 u8 reserved_at_8[0x18];
7845 u8 flow_counter_id[0x20];
7847 u8 reserved_at_60[0x20];
7850 struct mlx5_ifc_alloc_flow_counter_in_bits {
7852 u8 reserved_at_10[0x10];
7854 u8 reserved_at_20[0x10];
7857 u8 reserved_at_40[0x38];
7858 u8 flow_counter_bulk[0x8];
7861 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7863 u8 reserved_at_8[0x18];
7867 u8 reserved_at_40[0x40];
7870 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7872 u8 reserved_at_10[0x10];
7874 u8 reserved_at_20[0x10];
7877 u8 reserved_at_40[0x20];
7879 u8 reserved_at_60[0x10];
7880 u8 vxlan_udp_port[0x10];
7883 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7885 u8 reserved_at_8[0x18];
7889 u8 reserved_at_40[0x40];
7892 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7894 u8 reserved_at_10[0x10];
7896 u8 reserved_at_20[0x10];
7899 u8 reserved_at_40[0x10];
7900 u8 rate_limit_index[0x10];
7902 u8 reserved_at_60[0x20];
7904 u8 rate_limit[0x20];
7906 u8 burst_upper_bound[0x20];
7908 u8 reserved_at_c0[0x10];
7909 u8 typical_packet_size[0x10];
7911 u8 reserved_at_e0[0x120];
7914 struct mlx5_ifc_access_register_out_bits {
7916 u8 reserved_at_8[0x18];
7920 u8 reserved_at_40[0x40];
7922 u8 register_data[0][0x20];
7926 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7927 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7930 struct mlx5_ifc_access_register_in_bits {
7932 u8 reserved_at_10[0x10];
7934 u8 reserved_at_20[0x10];
7937 u8 reserved_at_40[0x10];
7938 u8 register_id[0x10];
7942 u8 register_data[0][0x20];
7945 struct mlx5_ifc_sltp_reg_bits {
7950 u8 reserved_at_12[0x2];
7952 u8 reserved_at_18[0x8];
7954 u8 reserved_at_20[0x20];
7956 u8 reserved_at_40[0x7];
7962 u8 reserved_at_60[0xc];
7963 u8 ob_preemp_mode[0x4];
7967 u8 reserved_at_80[0x20];
7970 struct mlx5_ifc_slrg_reg_bits {
7975 u8 reserved_at_12[0x2];
7977 u8 reserved_at_18[0x8];
7979 u8 time_to_link_up[0x10];
7980 u8 reserved_at_30[0xc];
7981 u8 grade_lane_speed[0x4];
7983 u8 grade_version[0x8];
7986 u8 reserved_at_60[0x4];
7987 u8 height_grade_type[0x4];
7988 u8 height_grade[0x18];
7993 u8 reserved_at_a0[0x10];
7994 u8 height_sigma[0x10];
7996 u8 reserved_at_c0[0x20];
7998 u8 reserved_at_e0[0x4];
7999 u8 phase_grade_type[0x4];
8000 u8 phase_grade[0x18];
8002 u8 reserved_at_100[0x8];
8003 u8 phase_eo_pos[0x8];
8004 u8 reserved_at_110[0x8];
8005 u8 phase_eo_neg[0x8];
8007 u8 ffe_set_tested[0x10];
8008 u8 test_errors_per_lane[0x10];
8011 struct mlx5_ifc_pvlc_reg_bits {
8012 u8 reserved_at_0[0x8];
8014 u8 reserved_at_10[0x10];
8016 u8 reserved_at_20[0x1c];
8019 u8 reserved_at_40[0x1c];
8022 u8 reserved_at_60[0x1c];
8023 u8 vl_operational[0x4];
8026 struct mlx5_ifc_pude_reg_bits {
8029 u8 reserved_at_10[0x4];
8030 u8 admin_status[0x4];
8031 u8 reserved_at_18[0x4];
8032 u8 oper_status[0x4];
8034 u8 reserved_at_20[0x60];
8037 struct mlx5_ifc_ptys_reg_bits {
8038 u8 reserved_at_0[0x1];
8039 u8 an_disable_admin[0x1];
8040 u8 an_disable_cap[0x1];
8041 u8 reserved_at_3[0x5];
8043 u8 reserved_at_10[0xd];
8047 u8 reserved_at_24[0x1c];
8049 u8 ext_eth_proto_capability[0x20];
8051 u8 eth_proto_capability[0x20];
8053 u8 ib_link_width_capability[0x10];
8054 u8 ib_proto_capability[0x10];
8056 u8 ext_eth_proto_admin[0x20];
8058 u8 eth_proto_admin[0x20];
8060 u8 ib_link_width_admin[0x10];
8061 u8 ib_proto_admin[0x10];
8063 u8 ext_eth_proto_oper[0x20];
8065 u8 eth_proto_oper[0x20];
8067 u8 ib_link_width_oper[0x10];
8068 u8 ib_proto_oper[0x10];
8070 u8 reserved_at_160[0x1c];
8071 u8 connector_type[0x4];
8073 u8 eth_proto_lp_advertise[0x20];
8075 u8 reserved_at_1a0[0x60];
8078 struct mlx5_ifc_mlcr_reg_bits {
8079 u8 reserved_at_0[0x8];
8081 u8 reserved_at_10[0x20];
8083 u8 beacon_duration[0x10];
8084 u8 reserved_at_40[0x10];
8086 u8 beacon_remain[0x10];
8089 struct mlx5_ifc_ptas_reg_bits {
8090 u8 reserved_at_0[0x20];
8092 u8 algorithm_options[0x10];
8093 u8 reserved_at_30[0x4];
8094 u8 repetitions_mode[0x4];
8095 u8 num_of_repetitions[0x8];
8097 u8 grade_version[0x8];
8098 u8 height_grade_type[0x4];
8099 u8 phase_grade_type[0x4];
8100 u8 height_grade_weight[0x8];
8101 u8 phase_grade_weight[0x8];
8103 u8 gisim_measure_bits[0x10];
8104 u8 adaptive_tap_measure_bits[0x10];
8106 u8 ber_bath_high_error_threshold[0x10];
8107 u8 ber_bath_mid_error_threshold[0x10];
8109 u8 ber_bath_low_error_threshold[0x10];
8110 u8 one_ratio_high_threshold[0x10];
8112 u8 one_ratio_high_mid_threshold[0x10];
8113 u8 one_ratio_low_mid_threshold[0x10];
8115 u8 one_ratio_low_threshold[0x10];
8116 u8 ndeo_error_threshold[0x10];
8118 u8 mixer_offset_step_size[0x10];
8119 u8 reserved_at_110[0x8];
8120 u8 mix90_phase_for_voltage_bath[0x8];
8122 u8 mixer_offset_start[0x10];
8123 u8 mixer_offset_end[0x10];
8125 u8 reserved_at_140[0x15];
8126 u8 ber_test_time[0xb];
8129 struct mlx5_ifc_pspa_reg_bits {
8133 u8 reserved_at_18[0x8];
8135 u8 reserved_at_20[0x20];
8138 struct mlx5_ifc_pqdr_reg_bits {
8139 u8 reserved_at_0[0x8];
8141 u8 reserved_at_10[0x5];
8143 u8 reserved_at_18[0x6];
8146 u8 reserved_at_20[0x20];
8148 u8 reserved_at_40[0x10];
8149 u8 min_threshold[0x10];
8151 u8 reserved_at_60[0x10];
8152 u8 max_threshold[0x10];
8154 u8 reserved_at_80[0x10];
8155 u8 mark_probability_denominator[0x10];
8157 u8 reserved_at_a0[0x60];
8160 struct mlx5_ifc_ppsc_reg_bits {
8161 u8 reserved_at_0[0x8];
8163 u8 reserved_at_10[0x10];
8165 u8 reserved_at_20[0x60];
8167 u8 reserved_at_80[0x1c];
8170 u8 reserved_at_a0[0x1c];
8171 u8 wrps_status[0x4];
8173 u8 reserved_at_c0[0x8];
8174 u8 up_threshold[0x8];
8175 u8 reserved_at_d0[0x8];
8176 u8 down_threshold[0x8];
8178 u8 reserved_at_e0[0x20];
8180 u8 reserved_at_100[0x1c];
8183 u8 reserved_at_120[0x1c];
8184 u8 srps_status[0x4];
8186 u8 reserved_at_140[0x40];
8189 struct mlx5_ifc_pplr_reg_bits {
8190 u8 reserved_at_0[0x8];
8192 u8 reserved_at_10[0x10];
8194 u8 reserved_at_20[0x8];
8196 u8 reserved_at_30[0x8];
8200 struct mlx5_ifc_pplm_reg_bits {
8201 u8 reserved_at_0[0x8];
8203 u8 reserved_at_10[0x10];
8205 u8 reserved_at_20[0x20];
8207 u8 port_profile_mode[0x8];
8208 u8 static_port_profile[0x8];
8209 u8 active_port_profile[0x8];
8210 u8 reserved_at_58[0x8];
8212 u8 retransmission_active[0x8];
8213 u8 fec_mode_active[0x18];
8215 u8 rs_fec_correction_bypass_cap[0x4];
8216 u8 reserved_at_84[0x8];
8217 u8 fec_override_cap_56g[0x4];
8218 u8 fec_override_cap_100g[0x4];
8219 u8 fec_override_cap_50g[0x4];
8220 u8 fec_override_cap_25g[0x4];
8221 u8 fec_override_cap_10g_40g[0x4];
8223 u8 rs_fec_correction_bypass_admin[0x4];
8224 u8 reserved_at_a4[0x8];
8225 u8 fec_override_admin_56g[0x4];
8226 u8 fec_override_admin_100g[0x4];
8227 u8 fec_override_admin_50g[0x4];
8228 u8 fec_override_admin_25g[0x4];
8229 u8 fec_override_admin_10g_40g[0x4];
8232 struct mlx5_ifc_ppcnt_reg_bits {
8236 u8 reserved_at_12[0x8];
8240 u8 reserved_at_21[0x1c];
8243 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8246 struct mlx5_ifc_mpein_reg_bits {
8247 u8 reserved_at_0[0x2];
8251 u8 reserved_at_18[0x8];
8253 u8 capability_mask[0x20];
8255 u8 reserved_at_40[0x8];
8256 u8 link_width_enabled[0x8];
8257 u8 link_speed_enabled[0x10];
8259 u8 lane0_physical_position[0x8];
8260 u8 link_width_active[0x8];
8261 u8 link_speed_active[0x10];
8263 u8 num_of_pfs[0x10];
8264 u8 num_of_vfs[0x10];
8267 u8 reserved_at_b0[0x10];
8269 u8 max_read_request_size[0x4];
8270 u8 max_payload_size[0x4];
8271 u8 reserved_at_c8[0x5];
8274 u8 reserved_at_d4[0xb];
8275 u8 lane_reversal[0x1];
8277 u8 reserved_at_e0[0x14];
8280 u8 reserved_at_100[0x20];
8282 u8 device_status[0x10];
8284 u8 reserved_at_138[0x8];
8286 u8 reserved_at_140[0x10];
8287 u8 receiver_detect_result[0x10];
8289 u8 reserved_at_160[0x20];
8292 struct mlx5_ifc_mpcnt_reg_bits {
8293 u8 reserved_at_0[0x8];
8295 u8 reserved_at_10[0xa];
8299 u8 reserved_at_21[0x1f];
8301 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8304 struct mlx5_ifc_ppad_reg_bits {
8305 u8 reserved_at_0[0x3];
8307 u8 reserved_at_4[0x4];
8313 u8 reserved_at_40[0x40];
8316 struct mlx5_ifc_pmtu_reg_bits {
8317 u8 reserved_at_0[0x8];
8319 u8 reserved_at_10[0x10];
8322 u8 reserved_at_30[0x10];
8325 u8 reserved_at_50[0x10];
8328 u8 reserved_at_70[0x10];
8331 struct mlx5_ifc_pmpr_reg_bits {
8332 u8 reserved_at_0[0x8];
8334 u8 reserved_at_10[0x10];
8336 u8 reserved_at_20[0x18];
8337 u8 attenuation_5g[0x8];
8339 u8 reserved_at_40[0x18];
8340 u8 attenuation_7g[0x8];
8342 u8 reserved_at_60[0x18];
8343 u8 attenuation_12g[0x8];
8346 struct mlx5_ifc_pmpe_reg_bits {
8347 u8 reserved_at_0[0x8];
8349 u8 reserved_at_10[0xc];
8350 u8 module_status[0x4];
8352 u8 reserved_at_20[0x60];
8355 struct mlx5_ifc_pmpc_reg_bits {
8356 u8 module_state_updated[32][0x8];
8359 struct mlx5_ifc_pmlpn_reg_bits {
8360 u8 reserved_at_0[0x4];
8361 u8 mlpn_status[0x4];
8363 u8 reserved_at_10[0x10];
8366 u8 reserved_at_21[0x1f];
8369 struct mlx5_ifc_pmlp_reg_bits {
8371 u8 reserved_at_1[0x7];
8373 u8 reserved_at_10[0x8];
8376 u8 lane0_module_mapping[0x20];
8378 u8 lane1_module_mapping[0x20];
8380 u8 lane2_module_mapping[0x20];
8382 u8 lane3_module_mapping[0x20];
8384 u8 reserved_at_a0[0x160];
8387 struct mlx5_ifc_pmaos_reg_bits {
8388 u8 reserved_at_0[0x8];
8390 u8 reserved_at_10[0x4];
8391 u8 admin_status[0x4];
8392 u8 reserved_at_18[0x4];
8393 u8 oper_status[0x4];
8397 u8 reserved_at_22[0x1c];
8400 u8 reserved_at_40[0x40];
8403 struct mlx5_ifc_plpc_reg_bits {
8404 u8 reserved_at_0[0x4];
8406 u8 reserved_at_10[0x4];
8408 u8 reserved_at_18[0x8];
8410 u8 reserved_at_20[0x10];
8411 u8 lane_speed[0x10];
8413 u8 reserved_at_40[0x17];
8415 u8 fec_mode_policy[0x8];
8417 u8 retransmission_capability[0x8];
8418 u8 fec_mode_capability[0x18];
8420 u8 retransmission_support_admin[0x8];
8421 u8 fec_mode_support_admin[0x18];
8423 u8 retransmission_request_admin[0x8];
8424 u8 fec_mode_request_admin[0x18];
8426 u8 reserved_at_c0[0x80];
8429 struct mlx5_ifc_plib_reg_bits {
8430 u8 reserved_at_0[0x8];
8432 u8 reserved_at_10[0x8];
8435 u8 reserved_at_20[0x60];
8438 struct mlx5_ifc_plbf_reg_bits {
8439 u8 reserved_at_0[0x8];
8441 u8 reserved_at_10[0xd];
8444 u8 reserved_at_20[0x20];
8447 struct mlx5_ifc_pipg_reg_bits {
8448 u8 reserved_at_0[0x8];
8450 u8 reserved_at_10[0x10];
8453 u8 reserved_at_21[0x19];
8455 u8 reserved_at_3e[0x2];
8458 struct mlx5_ifc_pifr_reg_bits {
8459 u8 reserved_at_0[0x8];
8461 u8 reserved_at_10[0x10];
8463 u8 reserved_at_20[0xe0];
8465 u8 port_filter[8][0x20];
8467 u8 port_filter_update_en[8][0x20];
8470 struct mlx5_ifc_pfcc_reg_bits {
8471 u8 reserved_at_0[0x8];
8473 u8 reserved_at_10[0xb];
8474 u8 ppan_mask_n[0x1];
8475 u8 minor_stall_mask[0x1];
8476 u8 critical_stall_mask[0x1];
8477 u8 reserved_at_1e[0x2];
8480 u8 reserved_at_24[0x4];
8481 u8 prio_mask_tx[0x8];
8482 u8 reserved_at_30[0x8];
8483 u8 prio_mask_rx[0x8];
8487 u8 pptx_mask_n[0x1];
8488 u8 reserved_at_43[0x5];
8490 u8 reserved_at_50[0x10];
8494 u8 pprx_mask_n[0x1];
8495 u8 reserved_at_63[0x5];
8497 u8 reserved_at_70[0x10];
8499 u8 device_stall_minor_watermark[0x10];
8500 u8 device_stall_critical_watermark[0x10];
8502 u8 reserved_at_a0[0x60];
8505 struct mlx5_ifc_pelc_reg_bits {
8507 u8 reserved_at_4[0x4];
8509 u8 reserved_at_10[0x10];
8512 u8 op_capability[0x8];
8518 u8 capability[0x40];
8524 u8 reserved_at_140[0x80];
8527 struct mlx5_ifc_peir_reg_bits {
8528 u8 reserved_at_0[0x8];
8530 u8 reserved_at_10[0x10];
8532 u8 reserved_at_20[0xc];
8533 u8 error_count[0x4];
8534 u8 reserved_at_30[0x10];
8536 u8 reserved_at_40[0xc];
8538 u8 reserved_at_50[0x8];
8542 struct mlx5_ifc_mpegc_reg_bits {
8543 u8 reserved_at_0[0x30];
8544 u8 field_select[0x10];
8546 u8 tx_overflow_sense[0x1];
8549 u8 reserved_at_43[0x1b];
8550 u8 tx_lossy_overflow_oper[0x2];
8552 u8 reserved_at_60[0x100];
8555 struct mlx5_ifc_pcam_enhanced_features_bits {
8556 u8 reserved_at_0[0x6d];
8557 u8 rx_icrc_encapsulated_counter[0x1];
8558 u8 reserved_at_6e[0x4];
8559 u8 ptys_extended_ethernet[0x1];
8560 u8 reserved_at_73[0x3];
8562 u8 reserved_at_77[0x3];
8563 u8 per_lane_error_counters[0x1];
8564 u8 rx_buffer_fullness_counters[0x1];
8565 u8 ptys_connector_type[0x1];
8566 u8 reserved_at_7d[0x1];
8567 u8 ppcnt_discard_group[0x1];
8568 u8 ppcnt_statistical_group[0x1];
8571 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8572 u8 port_access_reg_cap_mask_127_to_96[0x20];
8573 u8 port_access_reg_cap_mask_95_to_64[0x20];
8575 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8577 u8 port_access_reg_cap_mask_34_to_32[0x3];
8579 u8 port_access_reg_cap_mask_31_to_13[0x13];
8582 u8 port_access_reg_cap_mask_10_to_09[0x2];
8584 u8 port_access_reg_cap_mask_07_to_00[0x8];
8587 struct mlx5_ifc_pcam_reg_bits {
8588 u8 reserved_at_0[0x8];
8589 u8 feature_group[0x8];
8590 u8 reserved_at_10[0x8];
8591 u8 access_reg_group[0x8];
8593 u8 reserved_at_20[0x20];
8596 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8597 u8 reserved_at_0[0x80];
8598 } port_access_reg_cap_mask;
8600 u8 reserved_at_c0[0x80];
8603 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8604 u8 reserved_at_0[0x80];
8607 u8 reserved_at_1c0[0xc0];
8610 struct mlx5_ifc_mcam_enhanced_features_bits {
8611 u8 reserved_at_0[0x6e];
8612 u8 pci_status_and_power[0x1];
8613 u8 reserved_at_6f[0x5];
8614 u8 mark_tx_action_cnp[0x1];
8615 u8 mark_tx_action_cqe[0x1];
8616 u8 dynamic_tx_overflow[0x1];
8617 u8 reserved_at_77[0x4];
8618 u8 pcie_outbound_stalled[0x1];
8619 u8 tx_overflow_buffer_pkt[0x1];
8620 u8 mtpps_enh_out_per_adj[0x1];
8622 u8 pcie_performance_group[0x1];
8625 struct mlx5_ifc_mcam_access_reg_bits {
8626 u8 reserved_at_0[0x1c];
8632 u8 regs_95_to_87[0x9];
8634 u8 regs_85_to_68[0x12];
8635 u8 tracer_registers[0x4];
8637 u8 regs_63_to_32[0x20];
8638 u8 regs_31_to_0[0x20];
8641 struct mlx5_ifc_mcam_reg_bits {
8642 u8 reserved_at_0[0x8];
8643 u8 feature_group[0x8];
8644 u8 reserved_at_10[0x8];
8645 u8 access_reg_group[0x8];
8647 u8 reserved_at_20[0x20];
8650 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8651 u8 reserved_at_0[0x80];
8652 } mng_access_reg_cap_mask;
8654 u8 reserved_at_c0[0x80];
8657 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8658 u8 reserved_at_0[0x80];
8659 } mng_feature_cap_mask;
8661 u8 reserved_at_1c0[0x80];
8664 struct mlx5_ifc_qcam_access_reg_cap_mask {
8665 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8667 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8671 u8 qcam_access_reg_cap_mask_0[0x1];
8674 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8675 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8676 u8 qpts_trust_both[0x1];
8679 struct mlx5_ifc_qcam_reg_bits {
8680 u8 reserved_at_0[0x8];
8681 u8 feature_group[0x8];
8682 u8 reserved_at_10[0x8];
8683 u8 access_reg_group[0x8];
8684 u8 reserved_at_20[0x20];
8687 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8688 u8 reserved_at_0[0x80];
8689 } qos_access_reg_cap_mask;
8691 u8 reserved_at_c0[0x80];
8694 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8695 u8 reserved_at_0[0x80];
8696 } qos_feature_cap_mask;
8698 u8 reserved_at_1c0[0x80];
8701 struct mlx5_ifc_core_dump_reg_bits {
8702 u8 reserved_at_0[0x18];
8703 u8 core_dump_type[0x8];
8705 u8 reserved_at_20[0x30];
8708 u8 reserved_at_60[0x8];
8710 u8 reserved_at_80[0x180];
8713 struct mlx5_ifc_pcap_reg_bits {
8714 u8 reserved_at_0[0x8];
8716 u8 reserved_at_10[0x10];
8718 u8 port_capability_mask[4][0x20];
8721 struct mlx5_ifc_paos_reg_bits {
8724 u8 reserved_at_10[0x4];
8725 u8 admin_status[0x4];
8726 u8 reserved_at_18[0x4];
8727 u8 oper_status[0x4];
8731 u8 reserved_at_22[0x1c];
8734 u8 reserved_at_40[0x40];
8737 struct mlx5_ifc_pamp_reg_bits {
8738 u8 reserved_at_0[0x8];
8739 u8 opamp_group[0x8];
8740 u8 reserved_at_10[0xc];
8741 u8 opamp_group_type[0x4];
8743 u8 start_index[0x10];
8744 u8 reserved_at_30[0x4];
8745 u8 num_of_indices[0xc];
8747 u8 index_data[18][0x10];
8750 struct mlx5_ifc_pcmr_reg_bits {
8751 u8 reserved_at_0[0x8];
8753 u8 reserved_at_10[0x10];
8754 u8 entropy_force_cap[0x1];
8755 u8 entropy_calc_cap[0x1];
8756 u8 entropy_gre_calc_cap[0x1];
8757 u8 reserved_at_23[0x1b];
8759 u8 reserved_at_3f[0x1];
8760 u8 entropy_force[0x1];
8761 u8 entropy_calc[0x1];
8762 u8 entropy_gre_calc[0x1];
8763 u8 reserved_at_43[0x1b];
8765 u8 reserved_at_5f[0x1];
8768 struct mlx5_ifc_lane_2_module_mapping_bits {
8769 u8 reserved_at_0[0x6];
8771 u8 reserved_at_8[0x6];
8773 u8 reserved_at_10[0x8];
8777 struct mlx5_ifc_bufferx_reg_bits {
8778 u8 reserved_at_0[0x6];
8781 u8 reserved_at_8[0xc];
8784 u8 xoff_threshold[0x10];
8785 u8 xon_threshold[0x10];
8788 struct mlx5_ifc_set_node_in_bits {
8789 u8 node_description[64][0x8];
8792 struct mlx5_ifc_register_power_settings_bits {
8793 u8 reserved_at_0[0x18];
8794 u8 power_settings_level[0x8];
8796 u8 reserved_at_20[0x60];
8799 struct mlx5_ifc_register_host_endianness_bits {
8801 u8 reserved_at_1[0x1f];
8803 u8 reserved_at_20[0x60];
8806 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8807 u8 reserved_at_0[0x20];
8811 u8 addressh_63_32[0x20];
8813 u8 addressl_31_0[0x20];
8816 struct mlx5_ifc_ud_adrs_vector_bits {
8820 u8 reserved_at_41[0x7];
8821 u8 destination_qp_dct[0x18];
8823 u8 static_rate[0x4];
8824 u8 sl_eth_prio[0x4];
8827 u8 rlid_udp_sport[0x10];
8829 u8 reserved_at_80[0x20];
8831 u8 rmac_47_16[0x20];
8837 u8 reserved_at_e0[0x1];
8839 u8 reserved_at_e2[0x2];
8840 u8 src_addr_index[0x8];
8841 u8 flow_label[0x14];
8843 u8 rgid_rip[16][0x8];
8846 struct mlx5_ifc_pages_req_event_bits {
8847 u8 reserved_at_0[0x10];
8848 u8 function_id[0x10];
8852 u8 reserved_at_40[0xa0];
8855 struct mlx5_ifc_eqe_bits {
8856 u8 reserved_at_0[0x8];
8858 u8 reserved_at_10[0x8];
8859 u8 event_sub_type[0x8];
8861 u8 reserved_at_20[0xe0];
8863 union mlx5_ifc_event_auto_bits event_data;
8865 u8 reserved_at_1e0[0x10];
8867 u8 reserved_at_1f8[0x7];
8872 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8875 struct mlx5_ifc_cmd_queue_entry_bits {
8877 u8 reserved_at_8[0x18];
8879 u8 input_length[0x20];
8881 u8 input_mailbox_pointer_63_32[0x20];
8883 u8 input_mailbox_pointer_31_9[0x17];
8884 u8 reserved_at_77[0x9];
8886 u8 command_input_inline_data[16][0x8];
8888 u8 command_output_inline_data[16][0x8];
8890 u8 output_mailbox_pointer_63_32[0x20];
8892 u8 output_mailbox_pointer_31_9[0x17];
8893 u8 reserved_at_1b7[0x9];
8895 u8 output_length[0x20];
8899 u8 reserved_at_1f0[0x8];
8904 struct mlx5_ifc_cmd_out_bits {
8906 u8 reserved_at_8[0x18];
8910 u8 command_output[0x20];
8913 struct mlx5_ifc_cmd_in_bits {
8915 u8 reserved_at_10[0x10];
8917 u8 reserved_at_20[0x10];
8920 u8 command[0][0x20];
8923 struct mlx5_ifc_cmd_if_box_bits {
8924 u8 mailbox_data[512][0x8];
8926 u8 reserved_at_1000[0x180];
8928 u8 next_pointer_63_32[0x20];
8930 u8 next_pointer_31_10[0x16];
8931 u8 reserved_at_11b6[0xa];
8933 u8 block_number[0x20];
8935 u8 reserved_at_11e0[0x8];
8937 u8 ctrl_signature[0x8];
8941 struct mlx5_ifc_mtt_bits {
8942 u8 ptag_63_32[0x20];
8945 u8 reserved_at_38[0x6];
8950 struct mlx5_ifc_query_wol_rol_out_bits {
8952 u8 reserved_at_8[0x18];
8956 u8 reserved_at_40[0x10];
8960 u8 reserved_at_60[0x20];
8963 struct mlx5_ifc_query_wol_rol_in_bits {
8965 u8 reserved_at_10[0x10];
8967 u8 reserved_at_20[0x10];
8970 u8 reserved_at_40[0x40];
8973 struct mlx5_ifc_set_wol_rol_out_bits {
8975 u8 reserved_at_8[0x18];
8979 u8 reserved_at_40[0x40];
8982 struct mlx5_ifc_set_wol_rol_in_bits {
8984 u8 reserved_at_10[0x10];
8986 u8 reserved_at_20[0x10];
8989 u8 rol_mode_valid[0x1];
8990 u8 wol_mode_valid[0x1];
8991 u8 reserved_at_42[0xe];
8995 u8 reserved_at_60[0x20];
8999 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9000 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9001 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9005 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9006 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9007 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9011 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9012 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9013 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9014 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9015 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9016 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9017 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9018 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9019 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9020 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9021 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9024 struct mlx5_ifc_initial_seg_bits {
9025 u8 fw_rev_minor[0x10];
9026 u8 fw_rev_major[0x10];
9028 u8 cmd_interface_rev[0x10];
9029 u8 fw_rev_subminor[0x10];
9031 u8 reserved_at_40[0x40];
9033 u8 cmdq_phy_addr_63_32[0x20];
9035 u8 cmdq_phy_addr_31_12[0x14];
9036 u8 reserved_at_b4[0x2];
9037 u8 nic_interface[0x2];
9038 u8 log_cmdq_size[0x4];
9039 u8 log_cmdq_stride[0x4];
9041 u8 command_doorbell_vector[0x20];
9043 u8 reserved_at_e0[0xf00];
9045 u8 initializing[0x1];
9046 u8 reserved_at_fe1[0x4];
9047 u8 nic_interface_supported[0x3];
9048 u8 embedded_cpu[0x1];
9049 u8 reserved_at_fe9[0x17];
9051 struct mlx5_ifc_health_buffer_bits health_buffer;
9053 u8 no_dram_nic_offset[0x20];
9055 u8 reserved_at_1220[0x6e40];
9057 u8 reserved_at_8060[0x1f];
9060 u8 health_syndrome[0x8];
9061 u8 health_counter[0x18];
9063 u8 reserved_at_80a0[0x17fc0];
9066 struct mlx5_ifc_mtpps_reg_bits {
9067 u8 reserved_at_0[0xc];
9068 u8 cap_number_of_pps_pins[0x4];
9069 u8 reserved_at_10[0x4];
9070 u8 cap_max_num_of_pps_in_pins[0x4];
9071 u8 reserved_at_18[0x4];
9072 u8 cap_max_num_of_pps_out_pins[0x4];
9074 u8 reserved_at_20[0x24];
9075 u8 cap_pin_3_mode[0x4];
9076 u8 reserved_at_48[0x4];
9077 u8 cap_pin_2_mode[0x4];
9078 u8 reserved_at_50[0x4];
9079 u8 cap_pin_1_mode[0x4];
9080 u8 reserved_at_58[0x4];
9081 u8 cap_pin_0_mode[0x4];
9083 u8 reserved_at_60[0x4];
9084 u8 cap_pin_7_mode[0x4];
9085 u8 reserved_at_68[0x4];
9086 u8 cap_pin_6_mode[0x4];
9087 u8 reserved_at_70[0x4];
9088 u8 cap_pin_5_mode[0x4];
9089 u8 reserved_at_78[0x4];
9090 u8 cap_pin_4_mode[0x4];
9092 u8 field_select[0x20];
9093 u8 reserved_at_a0[0x60];
9096 u8 reserved_at_101[0xb];
9098 u8 reserved_at_110[0x4];
9102 u8 reserved_at_120[0x20];
9104 u8 time_stamp[0x40];
9106 u8 out_pulse_duration[0x10];
9107 u8 out_periodic_adjustment[0x10];
9108 u8 enhanced_out_periodic_adjustment[0x20];
9110 u8 reserved_at_1c0[0x20];
9113 struct mlx5_ifc_mtppse_reg_bits {
9114 u8 reserved_at_0[0x18];
9117 u8 reserved_at_21[0x1b];
9118 u8 event_generation_mode[0x4];
9119 u8 reserved_at_40[0x40];
9122 struct mlx5_ifc_mcqs_reg_bits {
9123 u8 last_index_flag[0x1];
9124 u8 reserved_at_1[0x7];
9126 u8 component_index[0x10];
9128 u8 reserved_at_20[0x10];
9129 u8 identifier[0x10];
9131 u8 reserved_at_40[0x17];
9132 u8 component_status[0x5];
9133 u8 component_update_state[0x4];
9135 u8 last_update_state_changer_type[0x4];
9136 u8 last_update_state_changer_host_id[0x4];
9137 u8 reserved_at_68[0x18];
9140 struct mlx5_ifc_mcqi_cap_bits {
9141 u8 supported_info_bitmask[0x20];
9143 u8 component_size[0x20];
9145 u8 max_component_size[0x20];
9147 u8 log_mcda_word_size[0x4];
9148 u8 reserved_at_64[0xc];
9149 u8 mcda_max_write_size[0x10];
9152 u8 reserved_at_81[0x1];
9153 u8 match_chip_id[0x1];
9155 u8 check_user_timestamp[0x1];
9156 u8 match_base_guid_mac[0x1];
9157 u8 reserved_at_86[0x1a];
9160 struct mlx5_ifc_mcqi_version_bits {
9161 u8 reserved_at_0[0x2];
9162 u8 build_time_valid[0x1];
9163 u8 user_defined_time_valid[0x1];
9164 u8 reserved_at_4[0x14];
9165 u8 version_string_length[0x8];
9169 u8 build_time[0x40];
9171 u8 user_defined_time[0x40];
9173 u8 build_tool_version[0x20];
9175 u8 reserved_at_e0[0x20];
9177 u8 version_string[92][0x8];
9180 struct mlx5_ifc_mcqi_activation_method_bits {
9181 u8 pending_server_ac_power_cycle[0x1];
9182 u8 pending_server_dc_power_cycle[0x1];
9183 u8 pending_server_reboot[0x1];
9184 u8 pending_fw_reset[0x1];
9185 u8 auto_activate[0x1];
9186 u8 all_hosts_sync[0x1];
9187 u8 device_hw_reset[0x1];
9188 u8 reserved_at_7[0x19];
9191 union mlx5_ifc_mcqi_reg_data_bits {
9192 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9193 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9194 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9197 struct mlx5_ifc_mcqi_reg_bits {
9198 u8 read_pending_component[0x1];
9199 u8 reserved_at_1[0xf];
9200 u8 component_index[0x10];
9202 u8 reserved_at_20[0x20];
9204 u8 reserved_at_40[0x1b];
9211 u8 reserved_at_a0[0x10];
9214 union mlx5_ifc_mcqi_reg_data_bits data[0];
9217 struct mlx5_ifc_mcc_reg_bits {
9218 u8 reserved_at_0[0x4];
9219 u8 time_elapsed_since_last_cmd[0xc];
9220 u8 reserved_at_10[0x8];
9221 u8 instruction[0x8];
9223 u8 reserved_at_20[0x10];
9224 u8 component_index[0x10];
9226 u8 reserved_at_40[0x8];
9227 u8 update_handle[0x18];
9229 u8 handle_owner_type[0x4];
9230 u8 handle_owner_host_id[0x4];
9231 u8 reserved_at_68[0x1];
9232 u8 control_progress[0x7];
9234 u8 reserved_at_78[0x4];
9235 u8 control_state[0x4];
9237 u8 component_size[0x20];
9239 u8 reserved_at_a0[0x60];
9242 struct mlx5_ifc_mcda_reg_bits {
9243 u8 reserved_at_0[0x8];
9244 u8 update_handle[0x18];
9248 u8 reserved_at_40[0x10];
9251 u8 reserved_at_60[0x20];
9256 union mlx5_ifc_ports_control_registers_document_bits {
9257 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9258 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9259 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9260 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9261 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9262 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9263 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9264 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9265 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9266 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9267 struct mlx5_ifc_paos_reg_bits paos_reg;
9268 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9269 struct mlx5_ifc_peir_reg_bits peir_reg;
9270 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9271 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9272 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9273 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9274 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9275 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9276 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9277 struct mlx5_ifc_plib_reg_bits plib_reg;
9278 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9279 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9280 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9281 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9282 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9283 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9284 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9285 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9286 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9287 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9288 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9289 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9290 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9291 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9292 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9293 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9294 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9295 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9296 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9297 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9298 struct mlx5_ifc_pude_reg_bits pude_reg;
9299 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9300 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9301 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9302 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9303 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9304 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9305 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9306 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9307 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9308 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9309 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9310 u8 reserved_at_0[0x60e0];
9313 union mlx5_ifc_debug_enhancements_document_bits {
9314 struct mlx5_ifc_health_buffer_bits health_buffer;
9315 u8 reserved_at_0[0x200];
9318 union mlx5_ifc_uplink_pci_interface_document_bits {
9319 struct mlx5_ifc_initial_seg_bits initial_seg;
9320 u8 reserved_at_0[0x20060];
9323 struct mlx5_ifc_set_flow_table_root_out_bits {
9325 u8 reserved_at_8[0x18];
9329 u8 reserved_at_40[0x40];
9332 struct mlx5_ifc_set_flow_table_root_in_bits {
9334 u8 reserved_at_10[0x10];
9336 u8 reserved_at_20[0x10];
9339 u8 other_vport[0x1];
9340 u8 reserved_at_41[0xf];
9341 u8 vport_number[0x10];
9343 u8 reserved_at_60[0x20];
9346 u8 reserved_at_88[0x18];
9348 u8 reserved_at_a0[0x8];
9351 u8 reserved_at_c0[0x8];
9352 u8 underlay_qpn[0x18];
9353 u8 reserved_at_e0[0x120];
9357 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9358 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9361 struct mlx5_ifc_modify_flow_table_out_bits {
9363 u8 reserved_at_8[0x18];
9367 u8 reserved_at_40[0x40];
9370 struct mlx5_ifc_modify_flow_table_in_bits {
9372 u8 reserved_at_10[0x10];
9374 u8 reserved_at_20[0x10];
9377 u8 other_vport[0x1];
9378 u8 reserved_at_41[0xf];
9379 u8 vport_number[0x10];
9381 u8 reserved_at_60[0x10];
9382 u8 modify_field_select[0x10];
9385 u8 reserved_at_88[0x18];
9387 u8 reserved_at_a0[0x8];
9390 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9393 struct mlx5_ifc_ets_tcn_config_reg_bits {
9397 u8 reserved_at_3[0x9];
9399 u8 reserved_at_10[0x9];
9400 u8 bw_allocation[0x7];
9402 u8 reserved_at_20[0xc];
9403 u8 max_bw_units[0x4];
9404 u8 reserved_at_30[0x8];
9405 u8 max_bw_value[0x8];
9408 struct mlx5_ifc_ets_global_config_reg_bits {
9409 u8 reserved_at_0[0x2];
9411 u8 reserved_at_3[0x1d];
9413 u8 reserved_at_20[0xc];
9414 u8 max_bw_units[0x4];
9415 u8 reserved_at_30[0x8];
9416 u8 max_bw_value[0x8];
9419 struct mlx5_ifc_qetc_reg_bits {
9420 u8 reserved_at_0[0x8];
9421 u8 port_number[0x8];
9422 u8 reserved_at_10[0x30];
9424 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9425 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9428 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9430 u8 reserved_at_01[0x0b];
9434 struct mlx5_ifc_qpdpm_reg_bits {
9435 u8 reserved_at_0[0x8];
9437 u8 reserved_at_10[0x10];
9438 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9441 struct mlx5_ifc_qpts_reg_bits {
9442 u8 reserved_at_0[0x8];
9444 u8 reserved_at_10[0x2d];
9445 u8 trust_state[0x3];
9448 struct mlx5_ifc_pptb_reg_bits {
9449 u8 reserved_at_0[0x2];
9451 u8 reserved_at_4[0x4];
9453 u8 reserved_at_10[0x6];
9458 u8 prio_x_buff[0x20];
9461 u8 reserved_at_48[0x10];
9463 u8 untagged_buff[0x4];
9466 struct mlx5_ifc_pbmc_reg_bits {
9467 u8 reserved_at_0[0x8];
9469 u8 reserved_at_10[0x10];
9471 u8 xoff_timer_value[0x10];
9472 u8 xoff_refresh[0x10];
9474 u8 reserved_at_40[0x9];
9475 u8 fullness_threshold[0x7];
9476 u8 port_buffer_size[0x10];
9478 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9480 u8 reserved_at_2e0[0x40];
9483 struct mlx5_ifc_qtct_reg_bits {
9484 u8 reserved_at_0[0x8];
9485 u8 port_number[0x8];
9486 u8 reserved_at_10[0xd];
9489 u8 reserved_at_20[0x1d];
9493 struct mlx5_ifc_mcia_reg_bits {
9495 u8 reserved_at_1[0x7];
9497 u8 reserved_at_10[0x8];
9500 u8 i2c_device_address[0x8];
9501 u8 page_number[0x8];
9502 u8 device_address[0x10];
9504 u8 reserved_at_40[0x10];
9507 u8 reserved_at_60[0x20];
9523 struct mlx5_ifc_dcbx_param_bits {
9524 u8 dcbx_cee_cap[0x1];
9525 u8 dcbx_ieee_cap[0x1];
9526 u8 dcbx_standby_cap[0x1];
9527 u8 reserved_at_3[0x5];
9528 u8 port_number[0x8];
9529 u8 reserved_at_10[0xa];
9530 u8 max_application_table_size[6];
9531 u8 reserved_at_20[0x15];
9532 u8 version_oper[0x3];
9533 u8 reserved_at_38[5];
9534 u8 version_admin[0x3];
9535 u8 willing_admin[0x1];
9536 u8 reserved_at_41[0x3];
9537 u8 pfc_cap_oper[0x4];
9538 u8 reserved_at_48[0x4];
9539 u8 pfc_cap_admin[0x4];
9540 u8 reserved_at_50[0x4];
9541 u8 num_of_tc_oper[0x4];
9542 u8 reserved_at_58[0x4];
9543 u8 num_of_tc_admin[0x4];
9544 u8 remote_willing[0x1];
9545 u8 reserved_at_61[3];
9546 u8 remote_pfc_cap[4];
9547 u8 reserved_at_68[0x14];
9548 u8 remote_num_of_tc[0x4];
9549 u8 reserved_at_80[0x18];
9551 u8 reserved_at_a0[0x160];
9554 struct mlx5_ifc_lagc_bits {
9555 u8 reserved_at_0[0x1d];
9558 u8 reserved_at_20[0x14];
9559 u8 tx_remap_affinity_2[0x4];
9560 u8 reserved_at_38[0x4];
9561 u8 tx_remap_affinity_1[0x4];
9564 struct mlx5_ifc_create_lag_out_bits {
9566 u8 reserved_at_8[0x18];
9570 u8 reserved_at_40[0x40];
9573 struct mlx5_ifc_create_lag_in_bits {
9575 u8 reserved_at_10[0x10];
9577 u8 reserved_at_20[0x10];
9580 struct mlx5_ifc_lagc_bits ctx;
9583 struct mlx5_ifc_modify_lag_out_bits {
9585 u8 reserved_at_8[0x18];
9589 u8 reserved_at_40[0x40];
9592 struct mlx5_ifc_modify_lag_in_bits {
9594 u8 reserved_at_10[0x10];
9596 u8 reserved_at_20[0x10];
9599 u8 reserved_at_40[0x20];
9600 u8 field_select[0x20];
9602 struct mlx5_ifc_lagc_bits ctx;
9605 struct mlx5_ifc_query_lag_out_bits {
9607 u8 reserved_at_8[0x18];
9611 struct mlx5_ifc_lagc_bits ctx;
9614 struct mlx5_ifc_query_lag_in_bits {
9616 u8 reserved_at_10[0x10];
9618 u8 reserved_at_20[0x10];
9621 u8 reserved_at_40[0x40];
9624 struct mlx5_ifc_destroy_lag_out_bits {
9626 u8 reserved_at_8[0x18];
9630 u8 reserved_at_40[0x40];
9633 struct mlx5_ifc_destroy_lag_in_bits {
9635 u8 reserved_at_10[0x10];
9637 u8 reserved_at_20[0x10];
9640 u8 reserved_at_40[0x40];
9643 struct mlx5_ifc_create_vport_lag_out_bits {
9645 u8 reserved_at_8[0x18];
9649 u8 reserved_at_40[0x40];
9652 struct mlx5_ifc_create_vport_lag_in_bits {
9654 u8 reserved_at_10[0x10];
9656 u8 reserved_at_20[0x10];
9659 u8 reserved_at_40[0x40];
9662 struct mlx5_ifc_destroy_vport_lag_out_bits {
9664 u8 reserved_at_8[0x18];
9668 u8 reserved_at_40[0x40];
9671 struct mlx5_ifc_destroy_vport_lag_in_bits {
9673 u8 reserved_at_10[0x10];
9675 u8 reserved_at_20[0x10];
9678 u8 reserved_at_40[0x40];
9681 struct mlx5_ifc_alloc_memic_in_bits {
9683 u8 reserved_at_10[0x10];
9685 u8 reserved_at_20[0x10];
9688 u8 reserved_at_30[0x20];
9690 u8 reserved_at_40[0x18];
9691 u8 log_memic_addr_alignment[0x8];
9693 u8 range_start_addr[0x40];
9695 u8 range_size[0x20];
9697 u8 memic_size[0x20];
9700 struct mlx5_ifc_alloc_memic_out_bits {
9702 u8 reserved_at_8[0x18];
9706 u8 memic_start_addr[0x40];
9709 struct mlx5_ifc_dealloc_memic_in_bits {
9711 u8 reserved_at_10[0x10];
9713 u8 reserved_at_20[0x10];
9716 u8 reserved_at_40[0x40];
9718 u8 memic_start_addr[0x40];
9720 u8 memic_size[0x20];
9722 u8 reserved_at_e0[0x20];
9725 struct mlx5_ifc_dealloc_memic_out_bits {
9727 u8 reserved_at_8[0x18];
9731 u8 reserved_at_40[0x40];
9734 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9738 u8 vhca_tunnel_id[0x10];
9743 u8 reserved_at_60[0x20];
9746 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9748 u8 reserved_at_8[0x18];
9754 u8 reserved_at_60[0x20];
9757 struct mlx5_ifc_umem_bits {
9758 u8 reserved_at_0[0x80];
9760 u8 reserved_at_80[0x1b];
9761 u8 log_page_size[0x5];
9763 u8 page_offset[0x20];
9765 u8 num_of_mtt[0x40];
9767 struct mlx5_ifc_mtt_bits mtt[0];
9770 struct mlx5_ifc_uctx_bits {
9773 u8 reserved_at_20[0x160];
9776 struct mlx5_ifc_sw_icm_bits {
9777 u8 modify_field_select[0x40];
9779 u8 reserved_at_40[0x18];
9780 u8 log_sw_icm_size[0x8];
9782 u8 reserved_at_60[0x20];
9784 u8 sw_icm_start_addr[0x40];
9786 u8 reserved_at_c0[0x140];
9789 struct mlx5_ifc_geneve_tlv_option_bits {
9790 u8 modify_field_select[0x40];
9792 u8 reserved_at_40[0x18];
9793 u8 geneve_option_fte_index[0x8];
9795 u8 option_class[0x10];
9796 u8 option_type[0x8];
9797 u8 reserved_at_78[0x3];
9798 u8 option_data_length[0x5];
9800 u8 reserved_at_80[0x180];
9803 struct mlx5_ifc_create_umem_in_bits {
9807 u8 reserved_at_20[0x10];
9810 u8 reserved_at_40[0x40];
9812 struct mlx5_ifc_umem_bits umem;
9815 struct mlx5_ifc_create_uctx_in_bits {
9817 u8 reserved_at_10[0x10];
9819 u8 reserved_at_20[0x10];
9822 u8 reserved_at_40[0x40];
9824 struct mlx5_ifc_uctx_bits uctx;
9827 struct mlx5_ifc_destroy_uctx_in_bits {
9829 u8 reserved_at_10[0x10];
9831 u8 reserved_at_20[0x10];
9834 u8 reserved_at_40[0x10];
9837 u8 reserved_at_60[0x20];
9840 struct mlx5_ifc_create_sw_icm_in_bits {
9841 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9842 struct mlx5_ifc_sw_icm_bits sw_icm;
9845 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9846 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9847 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
9850 struct mlx5_ifc_mtrc_string_db_param_bits {
9851 u8 string_db_base_address[0x20];
9853 u8 reserved_at_20[0x8];
9854 u8 string_db_size[0x18];
9857 struct mlx5_ifc_mtrc_cap_bits {
9858 u8 trace_owner[0x1];
9859 u8 trace_to_memory[0x1];
9860 u8 reserved_at_2[0x4];
9862 u8 reserved_at_8[0x14];
9863 u8 num_string_db[0x4];
9865 u8 first_string_trace[0x8];
9866 u8 num_string_trace[0x8];
9867 u8 reserved_at_30[0x28];
9869 u8 log_max_trace_buffer_size[0x8];
9871 u8 reserved_at_60[0x20];
9873 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9875 u8 reserved_at_280[0x180];
9878 struct mlx5_ifc_mtrc_conf_bits {
9879 u8 reserved_at_0[0x1c];
9881 u8 reserved_at_20[0x18];
9882 u8 log_trace_buffer_size[0x8];
9883 u8 trace_mkey[0x20];
9884 u8 reserved_at_60[0x3a0];
9887 struct mlx5_ifc_mtrc_stdb_bits {
9888 u8 string_db_index[0x4];
9889 u8 reserved_at_4[0x4];
9891 u8 start_offset[0x20];
9892 u8 string_db_data[0];
9895 struct mlx5_ifc_mtrc_ctrl_bits {
9896 u8 trace_status[0x2];
9897 u8 reserved_at_2[0x2];
9899 u8 reserved_at_5[0xb];
9900 u8 modify_field_select[0x10];
9901 u8 reserved_at_20[0x2b];
9902 u8 current_timestamp52_32[0x15];
9903 u8 current_timestamp31_0[0x20];
9904 u8 reserved_at_80[0x180];
9907 struct mlx5_ifc_host_params_context_bits {
9908 u8 host_number[0x8];
9909 u8 reserved_at_8[0x7];
9910 u8 host_pf_disabled[0x1];
9911 u8 host_num_of_vfs[0x10];
9913 u8 host_total_vfs[0x10];
9914 u8 host_pci_bus[0x10];
9916 u8 reserved_at_40[0x10];
9917 u8 host_pci_device[0x10];
9919 u8 reserved_at_60[0x10];
9920 u8 host_pci_function[0x10];
9922 u8 reserved_at_80[0x180];
9925 struct mlx5_ifc_query_esw_functions_in_bits {
9927 u8 reserved_at_10[0x10];
9929 u8 reserved_at_20[0x10];
9932 u8 reserved_at_40[0x40];
9935 struct mlx5_ifc_query_esw_functions_out_bits {
9937 u8 reserved_at_8[0x18];
9941 u8 reserved_at_40[0x40];
9943 struct mlx5_ifc_host_params_context_bits host_params_context;
9945 u8 reserved_at_280[0x180];
9946 u8 host_sf_enable[0][0x40];
9949 struct mlx5_ifc_sf_partition_bits {
9950 u8 reserved_at_0[0x10];
9952 u8 log_sf_bar_size[0x8];
9955 struct mlx5_ifc_query_sf_partitions_out_bits {
9957 u8 reserved_at_8[0x18];
9961 u8 reserved_at_40[0x18];
9962 u8 num_sf_partitions[0x8];
9964 u8 reserved_at_60[0x20];
9966 struct mlx5_ifc_sf_partition_bits sf_partition[0];
9969 struct mlx5_ifc_query_sf_partitions_in_bits {
9971 u8 reserved_at_10[0x10];
9973 u8 reserved_at_20[0x10];
9976 u8 reserved_at_40[0x40];
9979 struct mlx5_ifc_dealloc_sf_out_bits {
9981 u8 reserved_at_8[0x18];
9985 u8 reserved_at_40[0x40];
9988 struct mlx5_ifc_dealloc_sf_in_bits {
9990 u8 reserved_at_10[0x10];
9992 u8 reserved_at_20[0x10];
9995 u8 reserved_at_40[0x10];
9996 u8 function_id[0x10];
9998 u8 reserved_at_60[0x20];
10001 struct mlx5_ifc_alloc_sf_out_bits {
10003 u8 reserved_at_8[0x18];
10007 u8 reserved_at_40[0x40];
10010 struct mlx5_ifc_alloc_sf_in_bits {
10012 u8 reserved_at_10[0x10];
10014 u8 reserved_at_20[0x10];
10017 u8 reserved_at_40[0x10];
10018 u8 function_id[0x10];
10020 u8 reserved_at_60[0x20];
10023 struct mlx5_ifc_affiliated_event_header_bits {
10024 u8 reserved_at_0[0x10];
10031 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10035 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10038 struct mlx5_ifc_encryption_key_obj_bits {
10039 u8 modify_field_select[0x40];
10041 u8 reserved_at_40[0x14];
10043 u8 reserved_at_58[0x4];
10046 u8 reserved_at_60[0x8];
10049 u8 reserved_at_80[0x180];
10052 u8 reserved_at_300[0x500];
10055 struct mlx5_ifc_create_encryption_key_in_bits {
10056 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10057 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10061 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10062 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10066 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10069 struct mlx5_ifc_tls_static_params_bits {
10071 u8 tls_version[0x4];
10073 u8 reserved_at_8[0x14];
10074 u8 encryption_standard[0x4];
10076 u8 reserved_at_20[0x20];
10078 u8 initial_record_number[0x40];
10080 u8 resync_tcp_sn[0x20];
10084 u8 implicit_iv[0x40];
10086 u8 reserved_at_100[0x8];
10087 u8 dek_index[0x18];
10089 u8 reserved_at_120[0xe0];
10092 struct mlx5_ifc_tls_progress_params_bits {
10093 u8 reserved_at_0[0x8];
10096 u8 next_record_tcp_sn[0x20];
10098 u8 hw_resync_tcp_sn[0x20];
10100 u8 record_tracker_state[0x2];
10101 u8 auth_state[0x2];
10102 u8 reserved_at_64[0x4];
10103 u8 hw_offset_record_number[0x18];
10106 #endif /* MLX5_IFC_H */