include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_MKEY = 0xff01,
  97         MLX5_OBJ_TYPE_QP = 0xff02,
  98         MLX5_OBJ_TYPE_PSV = 0xff03,
  99         MLX5_OBJ_TYPE_RMP = 0xff04,
 100         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 101         MLX5_OBJ_TYPE_RQ = 0xff06,
 102         MLX5_OBJ_TYPE_SQ = 0xff07,
 103         MLX5_OBJ_TYPE_TIR = 0xff08,
 104         MLX5_OBJ_TYPE_TIS = 0xff09,
 105         MLX5_OBJ_TYPE_DCT = 0xff0a,
 106         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 107         MLX5_OBJ_TYPE_RQT = 0xff0e,
 108         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 109         MLX5_OBJ_TYPE_CQ = 0xff10,
 110 };
 111
 112 enum {
 113         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 114         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 115         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 116         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 117         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 118         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 119         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 120         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 121         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 122         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 123         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 124         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 125         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 126         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 127         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 128         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 129         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 130         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 131         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 132         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 133         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 134         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 135         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 136         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 137         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 138         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 139         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 140         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 141         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 142         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 143         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 144         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 145         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 146         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 147         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 148         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 149         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 150         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 151         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 152         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 153         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 154         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 155         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 156         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 157         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 158         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 159         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 160         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 161         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 162         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 163         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 164         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 165         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 166         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 167         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 168         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 169         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 170         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 171         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 172         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 173         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 174         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 175         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 176         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 177         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 178         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 179         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 180         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 181         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 182         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 183         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 184         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 185         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 186         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 187         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 188         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 189         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 191         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 192         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 193         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 194         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 195         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 196         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 197         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 198         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 199         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 200         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 201         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 202         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 203         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 204         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 205         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 206         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 207         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 208         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 209         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 210         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 211         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 212         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 213         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 214         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 215         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 216         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 217         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 218         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 219         MLX5_CMD_OP_NOP                           = 0x80d,
 220         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 221         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 222         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 223         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 224         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 225         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 226         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 227         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 228         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 229         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 230         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 231         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 232         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 233         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 234         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 235         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 236         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 237         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 238         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 239         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 240         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 241         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 242         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 243         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 244         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 245         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 246         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 247         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 248         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 249         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 250         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 251         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 252         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 253         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 254         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 255         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 256         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 257         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 258         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 259         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 260         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 261         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 262         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 263         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 264         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 265         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 266         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 267         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 268         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 269         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 270         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 271         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 272         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 273         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 274         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 275         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 276         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 277         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 278         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 279         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 280         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 281         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 282         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 283         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 284         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 285         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 286         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 287         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 288         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 289         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 290         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 291         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 292         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 293         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 294         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 295         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 296         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 297         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 298         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 299         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 300         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 301         MLX5_CMD_OP_MAX
 302 };
 303
 304 /* Valid range for general commands that don't work over an object */
 305 enum {
 306         MLX5_CMD_OP_GENERAL_START = 0xb00,
 307         MLX5_CMD_OP_GENERAL_END = 0xd00,
 308 };
 309
 310 struct mlx5_ifc_flow_table_fields_supported_bits {
 311         u8         outer_dmac[0x1];
 312         u8         outer_smac[0x1];
 313         u8         outer_ether_type[0x1];
 314         u8         outer_ip_version[0x1];
 315         u8         outer_first_prio[0x1];
 316         u8         outer_first_cfi[0x1];
 317         u8         outer_first_vid[0x1];
 318         u8         outer_ipv4_ttl[0x1];
 319         u8         outer_second_prio[0x1];
 320         u8         outer_second_cfi[0x1];
 321         u8         outer_second_vid[0x1];
 322         u8         reserved_at_b[0x1];
 323         u8         outer_sip[0x1];
 324         u8         outer_dip[0x1];
 325         u8         outer_frag[0x1];
 326         u8         outer_ip_protocol[0x1];
 327         u8         outer_ip_ecn[0x1];
 328         u8         outer_ip_dscp[0x1];
 329         u8         outer_udp_sport[0x1];
 330         u8         outer_udp_dport[0x1];
 331         u8         outer_tcp_sport[0x1];
 332         u8         outer_tcp_dport[0x1];
 333         u8         outer_tcp_flags[0x1];
 334         u8         outer_gre_protocol[0x1];
 335         u8         outer_gre_key[0x1];
 336         u8         outer_vxlan_vni[0x1];
 337         u8         outer_geneve_vni[0x1];
 338         u8         outer_geneve_oam[0x1];
 339         u8         outer_geneve_protocol_type[0x1];
 340         u8         outer_geneve_opt_len[0x1];
 341         u8         reserved_at_1e[0x1];
 342         u8         source_eswitch_port[0x1];
 343
 344         u8         inner_dmac[0x1];
 345         u8         inner_smac[0x1];
 346         u8         inner_ether_type[0x1];
 347         u8         inner_ip_version[0x1];
 348         u8         inner_first_prio[0x1];
 349         u8         inner_first_cfi[0x1];
 350         u8         inner_first_vid[0x1];
 351         u8         reserved_at_27[0x1];
 352         u8         inner_second_prio[0x1];
 353         u8         inner_second_cfi[0x1];
 354         u8         inner_second_vid[0x1];
 355         u8         reserved_at_2b[0x1];
 356         u8         inner_sip[0x1];
 357         u8         inner_dip[0x1];
 358         u8         inner_frag[0x1];
 359         u8         inner_ip_protocol[0x1];
 360         u8         inner_ip_ecn[0x1];
 361         u8         inner_ip_dscp[0x1];
 362         u8         inner_udp_sport[0x1];
 363         u8         inner_udp_dport[0x1];
 364         u8         inner_tcp_sport[0x1];
 365         u8         inner_tcp_dport[0x1];
 366         u8         inner_tcp_flags[0x1];
 367         u8         reserved_at_37[0x9];
 368
 369         u8         geneve_tlv_option_0_data[0x1];
 370         u8         reserved_at_41[0x4];
 371         u8         outer_first_mpls_over_udp[0x4];
 372         u8         outer_first_mpls_over_gre[0x4];
 373         u8         inner_first_mpls[0x4];
 374         u8         outer_first_mpls[0x4];
 375         u8         reserved_at_55[0x2];
 376         u8         outer_esp_spi[0x1];
 377         u8         reserved_at_58[0x2];
 378         u8         bth_dst_qp[0x1];
 379         u8         reserved_at_5b[0x5];
 380
 381         u8         reserved_at_60[0x18];
 382         u8         metadata_reg_c_7[0x1];
 383         u8         metadata_reg_c_6[0x1];
 384         u8         metadata_reg_c_5[0x1];
 385         u8         metadata_reg_c_4[0x1];
 386         u8         metadata_reg_c_3[0x1];
 387         u8         metadata_reg_c_2[0x1];
 388         u8         metadata_reg_c_1[0x1];
 389         u8         metadata_reg_c_0[0x1];
 390 };
 391
 392 struct mlx5_ifc_flow_table_prop_layout_bits {
 393         u8         ft_support[0x1];
 394         u8         reserved_at_1[0x1];
 395         u8         flow_counter[0x1];
 396         u8         flow_modify_en[0x1];
 397         u8         modify_root[0x1];
 398         u8         identified_miss_table_mode[0x1];
 399         u8         flow_table_modify[0x1];
 400         u8         reformat[0x1];
 401         u8         decap[0x1];
 402         u8         reserved_at_9[0x1];
 403         u8         pop_vlan[0x1];
 404         u8         push_vlan[0x1];
 405         u8         reserved_at_c[0x1];
 406         u8         pop_vlan_2[0x1];
 407         u8         push_vlan_2[0x1];
 408         u8         reformat_and_vlan_action[0x1];
 409         u8         reserved_at_10[0x1];
 410         u8         sw_owner[0x1];
 411         u8         reformat_l3_tunnel_to_l2[0x1];
 412         u8         reformat_l2_to_l3_tunnel[0x1];
 413         u8         reformat_and_modify_action[0x1];
 414         u8         ignore_flow_level[0x1];
 415         u8         reserved_at_16[0x1];
 416         u8         table_miss_action_domain[0x1];
 417         u8         termination_table[0x1];
 418         u8         reformat_and_fwd_to_table[0x1];
 419         u8         reserved_at_1a[0x6];
 420         u8         termination_table_raw_traffic[0x1];
 421         u8         reserved_at_21[0x1];
 422         u8         log_max_ft_size[0x6];
 423         u8         log_max_modify_header_context[0x8];
 424         u8         max_modify_header_actions[0x8];
 425         u8         max_ft_level[0x8];
 426
 427         u8         reserved_at_40[0x20];
 428
 429         u8         reserved_at_60[0x18];
 430         u8         log_max_ft_num[0x8];
 431
 432         u8         reserved_at_80[0x18];
 433         u8         log_max_destination[0x8];
 434
 435         u8         log_max_flow_counter[0x8];
 436         u8         reserved_at_a8[0x10];
 437         u8         log_max_flow[0x8];
 438
 439         u8         reserved_at_c0[0x40];
 440
 441         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 442
 443         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 444 };
 445
 446 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 447         u8         send[0x1];
 448         u8         receive[0x1];
 449         u8         write[0x1];
 450         u8         read[0x1];
 451         u8         atomic[0x1];
 452         u8         srq_receive[0x1];
 453         u8         reserved_at_6[0x1a];
 454 };
 455
 456 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 457         u8         smac_47_16[0x20];
 458
 459         u8         smac_15_0[0x10];
 460         u8         ethertype[0x10];
 461
 462         u8         dmac_47_16[0x20];
 463
 464         u8         dmac_15_0[0x10];
 465         u8         first_prio[0x3];
 466         u8         first_cfi[0x1];
 467         u8         first_vid[0xc];
 468
 469         u8         ip_protocol[0x8];
 470         u8         ip_dscp[0x6];
 471         u8         ip_ecn[0x2];
 472         u8         cvlan_tag[0x1];
 473         u8         svlan_tag[0x1];
 474         u8         frag[0x1];
 475         u8         ip_version[0x4];
 476         u8         tcp_flags[0x9];
 477
 478         u8         tcp_sport[0x10];
 479         u8         tcp_dport[0x10];
 480
 481         u8         reserved_at_c0[0x18];
 482         u8         ttl_hoplimit[0x8];
 483
 484         u8         udp_sport[0x10];
 485         u8         udp_dport[0x10];
 486
 487         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 488
 489         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 490 };
 491
 492 struct mlx5_ifc_nvgre_key_bits {
 493         u8 hi[0x18];
 494         u8 lo[0x8];
 495 };
 496
 497 union mlx5_ifc_gre_key_bits {
 498         struct mlx5_ifc_nvgre_key_bits nvgre;
 499         u8 key[0x20];
 500 };
 501
 502 struct mlx5_ifc_fte_match_set_misc_bits {
 503         u8         gre_c_present[0x1];
 504         u8         reserved_at_1[0x1];
 505         u8         gre_k_present[0x1];
 506         u8         gre_s_present[0x1];
 507         u8         source_vhca_port[0x4];
 508         u8         source_sqn[0x18];
 509
 510         u8         source_eswitch_owner_vhca_id[0x10];
 511         u8         source_port[0x10];
 512
 513         u8         outer_second_prio[0x3];
 514         u8         outer_second_cfi[0x1];
 515         u8         outer_second_vid[0xc];
 516         u8         inner_second_prio[0x3];
 517         u8         inner_second_cfi[0x1];
 518         u8         inner_second_vid[0xc];
 519
 520         u8         outer_second_cvlan_tag[0x1];
 521         u8         inner_second_cvlan_tag[0x1];
 522         u8         outer_second_svlan_tag[0x1];
 523         u8         inner_second_svlan_tag[0x1];
 524         u8         reserved_at_64[0xc];
 525         u8         gre_protocol[0x10];
 526
 527         union mlx5_ifc_gre_key_bits gre_key;
 528
 529         u8         vxlan_vni[0x18];
 530         u8         reserved_at_b8[0x8];
 531
 532         u8         geneve_vni[0x18];
 533         u8         reserved_at_d8[0x7];
 534         u8         geneve_oam[0x1];
 535
 536         u8         reserved_at_e0[0xc];
 537         u8         outer_ipv6_flow_label[0x14];
 538
 539         u8         reserved_at_100[0xc];
 540         u8         inner_ipv6_flow_label[0x14];
 541
 542         u8         reserved_at_120[0xa];
 543         u8         geneve_opt_len[0x6];
 544         u8         geneve_protocol_type[0x10];
 545
 546         u8         reserved_at_140[0x8];
 547         u8         bth_dst_qp[0x18];
 548         u8         reserved_at_160[0x20];
 549         u8         outer_esp_spi[0x20];
 550         u8         reserved_at_1a0[0x60];
 551 };
 552
 553 struct mlx5_ifc_fte_match_mpls_bits {
 554         u8         mpls_label[0x14];
 555         u8         mpls_exp[0x3];
 556         u8         mpls_s_bos[0x1];
 557         u8         mpls_ttl[0x8];
 558 };
 559
 560 struct mlx5_ifc_fte_match_set_misc2_bits {
 561         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 562
 563         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 564
 565         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 566
 567         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 568
 569         u8         metadata_reg_c_7[0x20];
 570
 571         u8         metadata_reg_c_6[0x20];
 572
 573         u8         metadata_reg_c_5[0x20];
 574
 575         u8         metadata_reg_c_4[0x20];
 576
 577         u8         metadata_reg_c_3[0x20];
 578
 579         u8         metadata_reg_c_2[0x20];
 580
 581         u8         metadata_reg_c_1[0x20];
 582
 583         u8         metadata_reg_c_0[0x20];
 584
 585         u8         metadata_reg_a[0x20];
 586
 587         u8         reserved_at_1a0[0x60];
 588 };
 589
 590 struct mlx5_ifc_fte_match_set_misc3_bits {
 591         u8         inner_tcp_seq_num[0x20];
 592
 593         u8         outer_tcp_seq_num[0x20];
 594
 595         u8         inner_tcp_ack_num[0x20];
 596
 597         u8         outer_tcp_ack_num[0x20];
 598
 599         u8         reserved_at_80[0x8];
 600         u8         outer_vxlan_gpe_vni[0x18];
 601
 602         u8         outer_vxlan_gpe_next_protocol[0x8];
 603         u8         outer_vxlan_gpe_flags[0x8];
 604         u8         reserved_at_b0[0x10];
 605
 606         u8         icmp_header_data[0x20];
 607
 608         u8         icmpv6_header_data[0x20];
 609
 610         u8         icmp_type[0x8];
 611         u8         icmp_code[0x8];
 612         u8         icmpv6_type[0x8];
 613         u8         icmpv6_code[0x8];
 614
 615         u8         geneve_tlv_option_0_data[0x20];
 616
 617         u8         reserved_at_140[0xc0];
 618 };
 619
 620 struct mlx5_ifc_cmd_pas_bits {
 621         u8         pa_h[0x20];
 622
 623         u8         pa_l[0x14];
 624         u8         reserved_at_34[0xc];
 625 };
 626
 627 struct mlx5_ifc_uint64_bits {
 628         u8         hi[0x20];
 629
 630         u8         lo[0x20];
 631 };
 632
 633 enum {
 634         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 635         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 636         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 637         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 638         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 639         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 640         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 641         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 642         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 643         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 644 };
 645
 646 struct mlx5_ifc_ads_bits {
 647         u8         fl[0x1];
 648         u8         free_ar[0x1];
 649         u8         reserved_at_2[0xe];
 650         u8         pkey_index[0x10];
 651
 652         u8         reserved_at_20[0x8];
 653         u8         grh[0x1];
 654         u8         mlid[0x7];
 655         u8         rlid[0x10];
 656
 657         u8         ack_timeout[0x5];
 658         u8         reserved_at_45[0x3];
 659         u8         src_addr_index[0x8];
 660         u8         reserved_at_50[0x4];
 661         u8         stat_rate[0x4];
 662         u8         hop_limit[0x8];
 663
 664         u8         reserved_at_60[0x4];
 665         u8         tclass[0x8];
 666         u8         flow_label[0x14];
 667
 668         u8         rgid_rip[16][0x8];
 669
 670         u8         reserved_at_100[0x4];
 671         u8         f_dscp[0x1];
 672         u8         f_ecn[0x1];
 673         u8         reserved_at_106[0x1];
 674         u8         f_eth_prio[0x1];
 675         u8         ecn[0x2];
 676         u8         dscp[0x6];
 677         u8         udp_sport[0x10];
 678
 679         u8         dei_cfi[0x1];
 680         u8         eth_prio[0x3];
 681         u8         sl[0x4];
 682         u8         vhca_port_num[0x8];
 683         u8         rmac_47_32[0x10];
 684
 685         u8         rmac_31_0[0x20];
 686 };
 687
 688 struct mlx5_ifc_flow_table_nic_cap_bits {
 689         u8         nic_rx_multi_path_tirs[0x1];
 690         u8         nic_rx_multi_path_tirs_fts[0x1];
 691         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 692         u8         reserved_at_3[0x4];
 693         u8         sw_owner_reformat_supported[0x1];
 694         u8         reserved_at_8[0x18];
 695
 696         u8         encap_general_header[0x1];
 697         u8         reserved_at_21[0xa];
 698         u8         log_max_packet_reformat_context[0x5];
 699         u8         reserved_at_30[0x6];
 700         u8         max_encap_header_size[0xa];
 701         u8         reserved_at_40[0x1c0];
 702
 703         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 704
 705         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 706
 707         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 708
 709         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 710
 711         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 712
 713         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 714
 715         u8         reserved_at_e00[0x1200];
 716
 717         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 718
 719         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 720
 721         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 722
 723         u8         reserved_at_20c0[0x5f40];
 724 };
 725
 726 enum {
 727         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 728         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 729         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 730         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 731         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 732         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 733         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 734         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 735 };
 736
 737 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 738         u8      fdb_to_vport_reg_c_id[0x8];
 739         u8      reserved_at_8[0xd];
 740         u8      fdb_modify_header_fwd_to_table[0x1];
 741         u8      reserved_at_16[0x1];
 742         u8      flow_source[0x1];
 743         u8      reserved_at_18[0x2];
 744         u8      multi_fdb_encap[0x1];
 745         u8      egress_acl_forward_to_vport[0x1];
 746         u8      fdb_multi_path_to_table[0x1];
 747         u8      reserved_at_1d[0x3];
 748
 749         u8      reserved_at_20[0x1e0];
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 754
 755         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 756
 757         u8      reserved_at_800[0x1000];
 758
 759         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 760
 761         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 762
 763         u8      sw_steering_uplink_icm_address_rx[0x40];
 764
 765         u8      sw_steering_uplink_icm_address_tx[0x40];
 766
 767         u8      reserved_at_1900[0x6700];
 768 };
 769
 770 enum {
 771         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 772         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 773 };
 774
 775 struct mlx5_ifc_e_switch_cap_bits {
 776         u8         vport_svlan_strip[0x1];
 777         u8         vport_cvlan_strip[0x1];
 778         u8         vport_svlan_insert[0x1];
 779         u8         vport_cvlan_insert_if_not_exist[0x1];
 780         u8         vport_cvlan_insert_overwrite[0x1];
 781         u8         reserved_at_5[0x3];
 782         u8         esw_uplink_ingress_acl[0x1];
 783         u8         reserved_at_9[0x10];
 784         u8         esw_functions_changed[0x1];
 785         u8         reserved_at_1a[0x1];
 786         u8         ecpf_vport_exists[0x1];
 787         u8         counter_eswitch_affinity[0x1];
 788         u8         merged_eswitch[0x1];
 789         u8         nic_vport_node_guid_modify[0x1];
 790         u8         nic_vport_port_guid_modify[0x1];
 791
 792         u8         vxlan_encap_decap[0x1];
 793         u8         nvgre_encap_decap[0x1];
 794         u8         reserved_at_22[0x1];
 795         u8         log_max_fdb_encap_uplink[0x5];
 796         u8         reserved_at_21[0x3];
 797         u8         log_max_packet_reformat_context[0x5];
 798         u8         reserved_2b[0x6];
 799         u8         max_encap_header_size[0xa];
 800
 801         u8         reserved_at_40[0xb];
 802         u8         log_max_esw_sf[0x5];
 803         u8         esw_sf_base_id[0x10];
 804
 805         u8         reserved_at_60[0x7a0];
 806
 807 };
 808
 809 struct mlx5_ifc_qos_cap_bits {
 810         u8         packet_pacing[0x1];
 811         u8         esw_scheduling[0x1];
 812         u8         esw_bw_share[0x1];
 813         u8         esw_rate_limit[0x1];
 814         u8         reserved_at_4[0x1];
 815         u8         packet_pacing_burst_bound[0x1];
 816         u8         packet_pacing_typical_size[0x1];
 817         u8         reserved_at_7[0x4];
 818         u8         packet_pacing_uid[0x1];
 819         u8         reserved_at_c[0x14];
 820
 821         u8         reserved_at_20[0x20];
 822
 823         u8         packet_pacing_max_rate[0x20];
 824
 825         u8         packet_pacing_min_rate[0x20];
 826
 827         u8         reserved_at_80[0x10];
 828         u8         packet_pacing_rate_table_size[0x10];
 829
 830         u8         esw_element_type[0x10];
 831         u8         esw_tsar_type[0x10];
 832
 833         u8         reserved_at_c0[0x10];
 834         u8         max_qos_para_vport[0x10];
 835
 836         u8         max_tsar_bw_share[0x20];
 837
 838         u8         reserved_at_100[0x700];
 839 };
 840
 841 struct mlx5_ifc_debug_cap_bits {
 842         u8         core_dump_general[0x1];
 843         u8         core_dump_qp[0x1];
 844         u8         reserved_at_2[0x7];
 845         u8         resource_dump[0x1];
 846         u8         reserved_at_a[0x16];
 847
 848         u8         reserved_at_20[0x2];
 849         u8         stall_detect[0x1];
 850         u8         reserved_at_23[0x1d];
 851
 852         u8         reserved_at_40[0x7c0];
 853 };
 854
 855 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 856         u8         csum_cap[0x1];
 857         u8         vlan_cap[0x1];
 858         u8         lro_cap[0x1];
 859         u8         lro_psh_flag[0x1];
 860         u8         lro_time_stamp[0x1];
 861         u8         reserved_at_5[0x2];
 862         u8         wqe_vlan_insert[0x1];
 863         u8         self_lb_en_modifiable[0x1];
 864         u8         reserved_at_9[0x2];
 865         u8         max_lso_cap[0x5];
 866         u8         multi_pkt_send_wqe[0x2];
 867         u8         wqe_inline_mode[0x2];
 868         u8         rss_ind_tbl_cap[0x4];
 869         u8         reg_umr_sq[0x1];
 870         u8         scatter_fcs[0x1];
 871         u8         enhanced_multi_pkt_send_wqe[0x1];
 872         u8         tunnel_lso_const_out_ip_id[0x1];
 873         u8         reserved_at_1c[0x2];
 874         u8         tunnel_stateless_gre[0x1];
 875         u8         tunnel_stateless_vxlan[0x1];
 876
 877         u8         swp[0x1];
 878         u8         swp_csum[0x1];
 879         u8         swp_lso[0x1];
 880         u8         cqe_checksum_full[0x1];
 881         u8         tunnel_stateless_geneve_tx[0x1];
 882         u8         tunnel_stateless_mpls_over_udp[0x1];
 883         u8         tunnel_stateless_mpls_over_gre[0x1];
 884         u8         tunnel_stateless_vxlan_gpe[0x1];
 885         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 886         u8         tunnel_stateless_ip_over_ip[0x1];
 887         u8         insert_trailer[0x1];
 888         u8         reserved_at_2b[0x5];
 889         u8         max_vxlan_udp_ports[0x8];
 890         u8         reserved_at_38[0x6];
 891         u8         max_geneve_opt_len[0x1];
 892         u8         tunnel_stateless_geneve_rx[0x1];
 893
 894         u8         reserved_at_40[0x10];
 895         u8         lro_min_mss_size[0x10];
 896
 897         u8         reserved_at_60[0x120];
 898
 899         u8         lro_timer_supported_periods[4][0x20];
 900
 901         u8         reserved_at_200[0x600];
 902 };
 903
 904 struct mlx5_ifc_roce_cap_bits {
 905         u8         roce_apm[0x1];
 906         u8         reserved_at_1[0x3];
 907         u8         sw_r_roce_src_udp_port[0x1];
 908         u8         reserved_at_5[0x1b];
 909
 910         u8         reserved_at_20[0x60];
 911
 912         u8         reserved_at_80[0xc];
 913         u8         l3_type[0x4];
 914         u8         reserved_at_90[0x8];
 915         u8         roce_version[0x8];
 916
 917         u8         reserved_at_a0[0x10];
 918         u8         r_roce_dest_udp_port[0x10];
 919
 920         u8         r_roce_max_src_udp_port[0x10];
 921         u8         r_roce_min_src_udp_port[0x10];
 922
 923         u8         reserved_at_e0[0x10];
 924         u8         roce_address_table_size[0x10];
 925
 926         u8         reserved_at_100[0x700];
 927 };
 928
 929 struct mlx5_ifc_sync_steering_in_bits {
 930         u8         opcode[0x10];
 931         u8         uid[0x10];
 932
 933         u8         reserved_at_20[0x10];
 934         u8         op_mod[0x10];
 935
 936         u8         reserved_at_40[0xc0];
 937 };
 938
 939 struct mlx5_ifc_sync_steering_out_bits {
 940         u8         status[0x8];
 941         u8         reserved_at_8[0x18];
 942
 943         u8         syndrome[0x20];
 944
 945         u8         reserved_at_40[0x40];
 946 };
 947
 948 struct mlx5_ifc_device_mem_cap_bits {
 949         u8         memic[0x1];
 950         u8         reserved_at_1[0x1f];
 951
 952         u8         reserved_at_20[0xb];
 953         u8         log_min_memic_alloc_size[0x5];
 954         u8         reserved_at_30[0x8];
 955         u8         log_max_memic_addr_alignment[0x8];
 956
 957         u8         memic_bar_start_addr[0x40];
 958
 959         u8         memic_bar_size[0x20];
 960
 961         u8         max_memic_size[0x20];
 962
 963         u8         steering_sw_icm_start_address[0x40];
 964
 965         u8         reserved_at_100[0x8];
 966         u8         log_header_modify_sw_icm_size[0x8];
 967         u8         reserved_at_110[0x2];
 968         u8         log_sw_icm_alloc_granularity[0x6];
 969         u8         log_steering_sw_icm_size[0x8];
 970
 971         u8         reserved_at_120[0x20];
 972
 973         u8         header_modify_sw_icm_start_address[0x40];
 974
 975         u8         reserved_at_180[0x680];
 976 };
 977
 978 struct mlx5_ifc_device_event_cap_bits {
 979         u8         user_affiliated_events[4][0x40];
 980
 981         u8         user_unaffiliated_events[4][0x40];
 982 };
 983
 984 struct mlx5_ifc_device_virtio_emulation_cap_bits {
 985         u8         reserved_at_0[0x20];
 986
 987         u8         reserved_at_20[0x13];
 988         u8         log_doorbell_stride[0x5];
 989         u8         reserved_at_38[0x3];
 990         u8         log_doorbell_bar_size[0x5];
 991
 992         u8         doorbell_bar_offset[0x40];
 993
 994         u8         reserved_at_80[0x780];
 995 };
 996
 997 enum {
 998         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 999         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1000         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1001         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1002         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1003         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1004         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1005         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1006         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1007 };
1008
1009 enum {
1010         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1011         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1012         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1013         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1014         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1015         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1016         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1017         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1018         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1019 };
1020
1021 struct mlx5_ifc_atomic_caps_bits {
1022         u8         reserved_at_0[0x40];
1023
1024         u8         atomic_req_8B_endianness_mode[0x2];
1025         u8         reserved_at_42[0x4];
1026         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1027
1028         u8         reserved_at_47[0x19];
1029
1030         u8         reserved_at_60[0x20];
1031
1032         u8         reserved_at_80[0x10];
1033         u8         atomic_operations[0x10];
1034
1035         u8         reserved_at_a0[0x10];
1036         u8         atomic_size_qp[0x10];
1037
1038         u8         reserved_at_c0[0x10];
1039         u8         atomic_size_dc[0x10];
1040
1041         u8         reserved_at_e0[0x720];
1042 };
1043
1044 struct mlx5_ifc_odp_cap_bits {
1045         u8         reserved_at_0[0x40];
1046
1047         u8         sig[0x1];
1048         u8         reserved_at_41[0x1f];
1049
1050         u8         reserved_at_60[0x20];
1051
1052         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1053
1054         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1055
1056         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1057
1058         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1059
1060         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1061
1062         u8         reserved_at_120[0x6E0];
1063 };
1064
1065 struct mlx5_ifc_calc_op {
1066         u8        reserved_at_0[0x10];
1067         u8        reserved_at_10[0x9];
1068         u8        op_swap_endianness[0x1];
1069         u8        op_min[0x1];
1070         u8        op_xor[0x1];
1071         u8        op_or[0x1];
1072         u8        op_and[0x1];
1073         u8        op_max[0x1];
1074         u8        op_add[0x1];
1075 };
1076
1077 struct mlx5_ifc_vector_calc_cap_bits {
1078         u8         calc_matrix[0x1];
1079         u8         reserved_at_1[0x1f];
1080         u8         reserved_at_20[0x8];
1081         u8         max_vec_count[0x8];
1082         u8         reserved_at_30[0xd];
1083         u8         max_chunk_size[0x3];
1084         struct mlx5_ifc_calc_op calc0;
1085         struct mlx5_ifc_calc_op calc1;
1086         struct mlx5_ifc_calc_op calc2;
1087         struct mlx5_ifc_calc_op calc3;
1088
1089         u8         reserved_at_c0[0x720];
1090 };
1091
1092 struct mlx5_ifc_tls_cap_bits {
1093         u8         tls_1_2_aes_gcm_128[0x1];
1094         u8         tls_1_3_aes_gcm_128[0x1];
1095         u8         tls_1_2_aes_gcm_256[0x1];
1096         u8         tls_1_3_aes_gcm_256[0x1];
1097         u8         reserved_at_4[0x1c];
1098
1099         u8         reserved_at_20[0x7e0];
1100 };
1101
1102 struct mlx5_ifc_ipsec_cap_bits {
1103         u8         ipsec_full_offload[0x1];
1104         u8         ipsec_crypto_offload[0x1];
1105         u8         ipsec_esn[0x1];
1106         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1107         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1108         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1109         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1110         u8         reserved_at_7[0x4];
1111         u8         log_max_ipsec_offload[0x5];
1112         u8         reserved_at_10[0x10];
1113
1114         u8         min_log_ipsec_full_replay_window[0x8];
1115         u8         max_log_ipsec_full_replay_window[0x8];
1116         u8         reserved_at_30[0x7d0];
1117 };
1118
1119 enum {
1120         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1121         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1122         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1123         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1124 };
1125
1126 enum {
1127         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1128         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1129 };
1130
1131 enum {
1132         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1133         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1134         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1135         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1136         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1137 };
1138
1139 enum {
1140         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1141         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1142         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1143         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1144         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1145         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1146 };
1147
1148 enum {
1149         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1150         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1151 };
1152
1153 enum {
1154         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1155         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1156         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1157 };
1158
1159 enum {
1160         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1161         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1162 };
1163
1164 enum {
1165         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1166         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1167         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1168 };
1169
1170 enum {
1171         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1172         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1173         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1174         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1175 };
1176
1177 enum {
1178         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1179         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1180 };
1181
1182 #define MLX5_FC_BULK_SIZE_FACTOR 128
1183
1184 enum mlx5_fc_bulk_alloc_bitmask {
1185         MLX5_FC_BULK_128   = (1 << 0),
1186         MLX5_FC_BULK_256   = (1 << 1),
1187         MLX5_FC_BULK_512   = (1 << 2),
1188         MLX5_FC_BULK_1024  = (1 << 3),
1189         MLX5_FC_BULK_2048  = (1 << 4),
1190         MLX5_FC_BULK_4096  = (1 << 5),
1191         MLX5_FC_BULK_8192  = (1 << 6),
1192         MLX5_FC_BULK_16384 = (1 << 7),
1193 };
1194
1195 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1196
1197 struct mlx5_ifc_cmd_hca_cap_bits {
1198         u8         reserved_at_0[0x30];
1199         u8         vhca_id[0x10];
1200
1201         u8         reserved_at_40[0x40];
1202
1203         u8         log_max_srq_sz[0x8];
1204         u8         log_max_qp_sz[0x8];
1205         u8         event_cap[0x1];
1206         u8         reserved_at_91[0x7];
1207         u8         prio_tag_required[0x1];
1208         u8         reserved_at_99[0x2];
1209         u8         log_max_qp[0x5];
1210
1211         u8         reserved_at_a0[0x3];
1212         u8         ece_support[0x1];
1213         u8         reserved_at_a4[0x7];
1214         u8         log_max_srq[0x5];
1215         u8         reserved_at_b0[0x10];
1216
1217         u8         max_sgl_for_optimized_performance[0x8];
1218         u8         log_max_cq_sz[0x8];
1219         u8         reserved_at_d0[0xb];
1220         u8         log_max_cq[0x5];
1221
1222         u8         log_max_eq_sz[0x8];
1223         u8         relaxed_ordering_write[0x1];
1224         u8         relaxed_ordering_read[0x1];
1225         u8         log_max_mkey[0x6];
1226         u8         reserved_at_f0[0x8];
1227         u8         dump_fill_mkey[0x1];
1228         u8         reserved_at_f9[0x2];
1229         u8         fast_teardown[0x1];
1230         u8         log_max_eq[0x4];
1231
1232         u8         max_indirection[0x8];
1233         u8         fixed_buffer_size[0x1];
1234         u8         log_max_mrw_sz[0x7];
1235         u8         force_teardown[0x1];
1236         u8         reserved_at_111[0x1];
1237         u8         log_max_bsf_list_size[0x6];
1238         u8         umr_extended_translation_offset[0x1];
1239         u8         null_mkey[0x1];
1240         u8         log_max_klm_list_size[0x6];
1241
1242         u8         reserved_at_120[0xa];
1243         u8         log_max_ra_req_dc[0x6];
1244         u8         reserved_at_130[0xa];
1245         u8         log_max_ra_res_dc[0x6];
1246
1247         u8         reserved_at_140[0x6];
1248         u8         release_all_pages[0x1];
1249         u8         reserved_at_147[0x2];
1250         u8         roce_accl[0x1];
1251         u8         log_max_ra_req_qp[0x6];
1252         u8         reserved_at_150[0xa];
1253         u8         log_max_ra_res_qp[0x6];
1254
1255         u8         end_pad[0x1];
1256         u8         cc_query_allowed[0x1];
1257         u8         cc_modify_allowed[0x1];
1258         u8         start_pad[0x1];
1259         u8         cache_line_128byte[0x1];
1260         u8         reserved_at_165[0x4];
1261         u8         rts2rts_qp_counters_set_id[0x1];
1262         u8         reserved_at_16a[0x2];
1263         u8         vnic_env_int_rq_oob[0x1];
1264         u8         sbcam_reg[0x1];
1265         u8         reserved_at_16e[0x1];
1266         u8         qcam_reg[0x1];
1267         u8         gid_table_size[0x10];
1268
1269         u8         out_of_seq_cnt[0x1];
1270         u8         vport_counters[0x1];
1271         u8         retransmission_q_counters[0x1];
1272         u8         debug[0x1];
1273         u8         modify_rq_counter_set_id[0x1];
1274         u8         rq_delay_drop[0x1];
1275         u8         max_qp_cnt[0xa];
1276         u8         pkey_table_size[0x10];
1277
1278         u8         vport_group_manager[0x1];
1279         u8         vhca_group_manager[0x1];
1280         u8         ib_virt[0x1];
1281         u8         eth_virt[0x1];
1282         u8         vnic_env_queue_counters[0x1];
1283         u8         ets[0x1];
1284         u8         nic_flow_table[0x1];
1285         u8         eswitch_manager[0x1];
1286         u8         device_memory[0x1];
1287         u8         mcam_reg[0x1];
1288         u8         pcam_reg[0x1];
1289         u8         local_ca_ack_delay[0x5];
1290         u8         port_module_event[0x1];
1291         u8         enhanced_error_q_counters[0x1];
1292         u8         ports_check[0x1];
1293         u8         reserved_at_1b3[0x1];
1294         u8         disable_link_up[0x1];
1295         u8         beacon_led[0x1];
1296         u8         port_type[0x2];
1297         u8         num_ports[0x8];
1298
1299         u8         reserved_at_1c0[0x1];
1300         u8         pps[0x1];
1301         u8         pps_modify[0x1];
1302         u8         log_max_msg[0x5];
1303         u8         reserved_at_1c8[0x4];
1304         u8         max_tc[0x4];
1305         u8         temp_warn_event[0x1];
1306         u8         dcbx[0x1];
1307         u8         general_notification_event[0x1];
1308         u8         reserved_at_1d3[0x2];
1309         u8         fpga[0x1];
1310         u8         rol_s[0x1];
1311         u8         rol_g[0x1];
1312         u8         reserved_at_1d8[0x1];
1313         u8         wol_s[0x1];
1314         u8         wol_g[0x1];
1315         u8         wol_a[0x1];
1316         u8         wol_b[0x1];
1317         u8         wol_m[0x1];
1318         u8         wol_u[0x1];
1319         u8         wol_p[0x1];
1320
1321         u8         stat_rate_support[0x10];
1322         u8         reserved_at_1f0[0x1];
1323         u8         pci_sync_for_fw_update_event[0x1];
1324         u8         reserved_at_1f2[0x6];
1325         u8         init2_lag_tx_port_affinity[0x1];
1326         u8         reserved_at_1fa[0x3];
1327         u8         cqe_version[0x4];
1328
1329         u8         compact_address_vector[0x1];
1330         u8         striding_rq[0x1];
1331         u8         reserved_at_202[0x1];
1332         u8         ipoib_enhanced_offloads[0x1];
1333         u8         ipoib_basic_offloads[0x1];
1334         u8         reserved_at_205[0x1];
1335         u8         repeated_block_disabled[0x1];
1336         u8         umr_modify_entity_size_disabled[0x1];
1337         u8         umr_modify_atomic_disabled[0x1];
1338         u8         umr_indirect_mkey_disabled[0x1];
1339         u8         umr_fence[0x2];
1340         u8         dc_req_scat_data_cqe[0x1];
1341         u8         reserved_at_20d[0x2];
1342         u8         drain_sigerr[0x1];
1343         u8         cmdif_checksum[0x2];
1344         u8         sigerr_cqe[0x1];
1345         u8         reserved_at_213[0x1];
1346         u8         wq_signature[0x1];
1347         u8         sctr_data_cqe[0x1];
1348         u8         reserved_at_216[0x1];
1349         u8         sho[0x1];
1350         u8         tph[0x1];
1351         u8         rf[0x1];
1352         u8         dct[0x1];
1353         u8         qos[0x1];
1354         u8         eth_net_offloads[0x1];
1355         u8         roce[0x1];
1356         u8         atomic[0x1];
1357         u8         reserved_at_21f[0x1];
1358
1359         u8         cq_oi[0x1];
1360         u8         cq_resize[0x1];
1361         u8         cq_moderation[0x1];
1362         u8         reserved_at_223[0x3];
1363         u8         cq_eq_remap[0x1];
1364         u8         pg[0x1];
1365         u8         block_lb_mc[0x1];
1366         u8         reserved_at_229[0x1];
1367         u8         scqe_break_moderation[0x1];
1368         u8         cq_period_start_from_cqe[0x1];
1369         u8         cd[0x1];
1370         u8         reserved_at_22d[0x1];
1371         u8         apm[0x1];
1372         u8         vector_calc[0x1];
1373         u8         umr_ptr_rlky[0x1];
1374         u8         imaicl[0x1];
1375         u8         qp_packet_based[0x1];
1376         u8         reserved_at_233[0x3];
1377         u8         qkv[0x1];
1378         u8         pkv[0x1];
1379         u8         set_deth_sqpn[0x1];
1380         u8         reserved_at_239[0x3];
1381         u8         xrc[0x1];
1382         u8         ud[0x1];
1383         u8         uc[0x1];
1384         u8         rc[0x1];
1385
1386         u8         uar_4k[0x1];
1387         u8         reserved_at_241[0x9];
1388         u8         uar_sz[0x6];
1389         u8         reserved_at_250[0x8];
1390         u8         log_pg_sz[0x8];
1391
1392         u8         bf[0x1];
1393         u8         driver_version[0x1];
1394         u8         pad_tx_eth_packet[0x1];
1395         u8         reserved_at_263[0x8];
1396         u8         log_bf_reg_size[0x5];
1397
1398         u8         reserved_at_270[0x8];
1399         u8         lag_tx_port_affinity[0x1];
1400         u8         reserved_at_279[0x2];
1401         u8         lag_master[0x1];
1402         u8         num_lag_ports[0x4];
1403
1404         u8         reserved_at_280[0x10];
1405         u8         max_wqe_sz_sq[0x10];
1406
1407         u8         reserved_at_2a0[0x10];
1408         u8         max_wqe_sz_rq[0x10];
1409
1410         u8         max_flow_counter_31_16[0x10];
1411         u8         max_wqe_sz_sq_dc[0x10];
1412
1413         u8         reserved_at_2e0[0x7];
1414         u8         max_qp_mcg[0x19];
1415
1416         u8         reserved_at_300[0x10];
1417         u8         flow_counter_bulk_alloc[0x8];
1418         u8         log_max_mcg[0x8];
1419
1420         u8         reserved_at_320[0x3];
1421         u8         log_max_transport_domain[0x5];
1422         u8         reserved_at_328[0x3];
1423         u8         log_max_pd[0x5];
1424         u8         reserved_at_330[0xb];
1425         u8         log_max_xrcd[0x5];
1426
1427         u8         nic_receive_steering_discard[0x1];
1428         u8         receive_discard_vport_down[0x1];
1429         u8         transmit_discard_vport_down[0x1];
1430         u8         reserved_at_343[0x5];
1431         u8         log_max_flow_counter_bulk[0x8];
1432         u8         max_flow_counter_15_0[0x10];
1433
1434
1435         u8         reserved_at_360[0x3];
1436         u8         log_max_rq[0x5];
1437         u8         reserved_at_368[0x3];
1438         u8         log_max_sq[0x5];
1439         u8         reserved_at_370[0x3];
1440         u8         log_max_tir[0x5];
1441         u8         reserved_at_378[0x3];
1442         u8         log_max_tis[0x5];
1443
1444         u8         basic_cyclic_rcv_wqe[0x1];
1445         u8         reserved_at_381[0x2];
1446         u8         log_max_rmp[0x5];
1447         u8         reserved_at_388[0x3];
1448         u8         log_max_rqt[0x5];
1449         u8         reserved_at_390[0x3];
1450         u8         log_max_rqt_size[0x5];
1451         u8         reserved_at_398[0x3];
1452         u8         log_max_tis_per_sq[0x5];
1453
1454         u8         ext_stride_num_range[0x1];
1455         u8         reserved_at_3a1[0x2];
1456         u8         log_max_stride_sz_rq[0x5];
1457         u8         reserved_at_3a8[0x3];
1458         u8         log_min_stride_sz_rq[0x5];
1459         u8         reserved_at_3b0[0x3];
1460         u8         log_max_stride_sz_sq[0x5];
1461         u8         reserved_at_3b8[0x3];
1462         u8         log_min_stride_sz_sq[0x5];
1463
1464         u8         hairpin[0x1];
1465         u8         reserved_at_3c1[0x2];
1466         u8         log_max_hairpin_queues[0x5];
1467         u8         reserved_at_3c8[0x3];
1468         u8         log_max_hairpin_wq_data_sz[0x5];
1469         u8         reserved_at_3d0[0x3];
1470         u8         log_max_hairpin_num_packets[0x5];
1471         u8         reserved_at_3d8[0x3];
1472         u8         log_max_wq_sz[0x5];
1473
1474         u8         nic_vport_change_event[0x1];
1475         u8         disable_local_lb_uc[0x1];
1476         u8         disable_local_lb_mc[0x1];
1477         u8         log_min_hairpin_wq_data_sz[0x5];
1478         u8         reserved_at_3e8[0x3];
1479         u8         log_max_vlan_list[0x5];
1480         u8         reserved_at_3f0[0x3];
1481         u8         log_max_current_mc_list[0x5];
1482         u8         reserved_at_3f8[0x3];
1483         u8         log_max_current_uc_list[0x5];
1484
1485         u8         general_obj_types[0x40];
1486
1487         u8         reserved_at_440[0x20];
1488
1489         u8         reserved_at_460[0x3];
1490         u8         log_max_uctx[0x5];
1491         u8         reserved_at_468[0x2];
1492         u8         ipsec_offload[0x1];
1493         u8         log_max_umem[0x5];
1494         u8         max_num_eqs[0x10];
1495
1496         u8         reserved_at_480[0x1];
1497         u8         tls_tx[0x1];
1498         u8         tls_rx[0x1];
1499         u8         log_max_l2_table[0x5];
1500         u8         reserved_at_488[0x8];
1501         u8         log_uar_page_sz[0x10];
1502
1503         u8         reserved_at_4a0[0x20];
1504         u8         device_frequency_mhz[0x20];
1505         u8         device_frequency_khz[0x20];
1506
1507         u8         reserved_at_500[0x20];
1508         u8         num_of_uars_per_page[0x20];
1509
1510         u8         flex_parser_protocols[0x20];
1511
1512         u8         max_geneve_tlv_options[0x8];
1513         u8         reserved_at_568[0x3];
1514         u8         max_geneve_tlv_option_data_len[0x5];
1515         u8         reserved_at_570[0x10];
1516
1517         u8         reserved_at_580[0x33];
1518         u8         log_max_dek[0x5];
1519         u8         reserved_at_5b8[0x4];
1520         u8         mini_cqe_resp_stride_index[0x1];
1521         u8         cqe_128_always[0x1];
1522         u8         cqe_compression_128[0x1];
1523         u8         cqe_compression[0x1];
1524
1525         u8         cqe_compression_timeout[0x10];
1526         u8         cqe_compression_max_num[0x10];
1527
1528         u8         reserved_at_5e0[0x10];
1529         u8         tag_matching[0x1];
1530         u8         rndv_offload_rc[0x1];
1531         u8         rndv_offload_dc[0x1];
1532         u8         log_tag_matching_list_sz[0x5];
1533         u8         reserved_at_5f8[0x3];
1534         u8         log_max_xrq[0x5];
1535
1536         u8         affiliate_nic_vport_criteria[0x8];
1537         u8         native_port_num[0x8];
1538         u8         num_vhca_ports[0x8];
1539         u8         reserved_at_618[0x6];
1540         u8         sw_owner_id[0x1];
1541         u8         reserved_at_61f[0x1];
1542
1543         u8         max_num_of_monitor_counters[0x10];
1544         u8         num_ppcnt_monitor_counters[0x10];
1545
1546         u8         reserved_at_640[0x10];
1547         u8         num_q_monitor_counters[0x10];
1548
1549         u8         reserved_at_660[0x20];
1550
1551         u8         sf[0x1];
1552         u8         sf_set_partition[0x1];
1553         u8         reserved_at_682[0x1];
1554         u8         log_max_sf[0x5];
1555         u8         reserved_at_688[0x8];
1556         u8         log_min_sf_size[0x8];
1557         u8         max_num_sf_partitions[0x8];
1558
1559         u8         uctx_cap[0x20];
1560
1561         u8         reserved_at_6c0[0x4];
1562         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1563         u8         flex_parser_id_icmp_dw1[0x4];
1564         u8         flex_parser_id_icmp_dw0[0x4];
1565         u8         flex_parser_id_icmpv6_dw1[0x4];
1566         u8         flex_parser_id_icmpv6_dw0[0x4];
1567         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1568         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1569
1570         u8         reserved_at_6e0[0x10];
1571         u8         sf_base_id[0x10];
1572
1573         u8         reserved_at_700[0x80];
1574         u8         vhca_tunnel_commands[0x40];
1575         u8         reserved_at_7c0[0x40];
1576 };
1577
1578 enum mlx5_flow_destination_type {
1579         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1580         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1581         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1582
1583         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1584         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1585         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1586 };
1587
1588 enum mlx5_flow_table_miss_action {
1589         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1590         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1591         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1592 };
1593
1594 struct mlx5_ifc_dest_format_struct_bits {
1595         u8         destination_type[0x8];
1596         u8         destination_id[0x18];
1597
1598         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1599         u8         packet_reformat[0x1];
1600         u8         reserved_at_22[0xe];
1601         u8         destination_eswitch_owner_vhca_id[0x10];
1602 };
1603
1604 struct mlx5_ifc_flow_counter_list_bits {
1605         u8         flow_counter_id[0x20];
1606
1607         u8         reserved_at_20[0x20];
1608 };
1609
1610 struct mlx5_ifc_extended_dest_format_bits {
1611         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1612
1613         u8         packet_reformat_id[0x20];
1614
1615         u8         reserved_at_60[0x20];
1616 };
1617
1618 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1619         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1620         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1621 };
1622
1623 struct mlx5_ifc_fte_match_param_bits {
1624         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1625
1626         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1627
1628         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1629
1630         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1631
1632         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1633
1634         u8         reserved_at_a00[0x600];
1635 };
1636
1637 enum {
1638         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1639         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1640         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1641         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1642         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1643 };
1644
1645 struct mlx5_ifc_rx_hash_field_select_bits {
1646         u8         l3_prot_type[0x1];
1647         u8         l4_prot_type[0x1];
1648         u8         selected_fields[0x1e];
1649 };
1650
1651 enum {
1652         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1653         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1654 };
1655
1656 enum {
1657         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1658         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1659 };
1660
1661 struct mlx5_ifc_wq_bits {
1662         u8         wq_type[0x4];
1663         u8         wq_signature[0x1];
1664         u8         end_padding_mode[0x2];
1665         u8         cd_slave[0x1];
1666         u8         reserved_at_8[0x18];
1667
1668         u8         hds_skip_first_sge[0x1];
1669         u8         log2_hds_buf_size[0x3];
1670         u8         reserved_at_24[0x7];
1671         u8         page_offset[0x5];
1672         u8         lwm[0x10];
1673
1674         u8         reserved_at_40[0x8];
1675         u8         pd[0x18];
1676
1677         u8         reserved_at_60[0x8];
1678         u8         uar_page[0x18];
1679
1680         u8         dbr_addr[0x40];
1681
1682         u8         hw_counter[0x20];
1683
1684         u8         sw_counter[0x20];
1685
1686         u8         reserved_at_100[0xc];
1687         u8         log_wq_stride[0x4];
1688         u8         reserved_at_110[0x3];
1689         u8         log_wq_pg_sz[0x5];
1690         u8         reserved_at_118[0x3];
1691         u8         log_wq_sz[0x5];
1692
1693         u8         dbr_umem_valid[0x1];
1694         u8         wq_umem_valid[0x1];
1695         u8         reserved_at_122[0x1];
1696         u8         log_hairpin_num_packets[0x5];
1697         u8         reserved_at_128[0x3];
1698         u8         log_hairpin_data_sz[0x5];
1699
1700         u8         reserved_at_130[0x4];
1701         u8         log_wqe_num_of_strides[0x4];
1702         u8         two_byte_shift_en[0x1];
1703         u8         reserved_at_139[0x4];
1704         u8         log_wqe_stride_size[0x3];
1705
1706         u8         reserved_at_140[0x4c0];
1707
1708         struct mlx5_ifc_cmd_pas_bits pas[];
1709 };
1710
1711 struct mlx5_ifc_rq_num_bits {
1712         u8         reserved_at_0[0x8];
1713         u8         rq_num[0x18];
1714 };
1715
1716 struct mlx5_ifc_mac_address_layout_bits {
1717         u8         reserved_at_0[0x10];
1718         u8         mac_addr_47_32[0x10];
1719
1720         u8         mac_addr_31_0[0x20];
1721 };
1722
1723 struct mlx5_ifc_vlan_layout_bits {
1724         u8         reserved_at_0[0x14];
1725         u8         vlan[0x0c];
1726
1727         u8         reserved_at_20[0x20];
1728 };
1729
1730 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1731         u8         reserved_at_0[0xa0];
1732
1733         u8         min_time_between_cnps[0x20];
1734
1735         u8         reserved_at_c0[0x12];
1736         u8         cnp_dscp[0x6];
1737         u8         reserved_at_d8[0x4];
1738         u8         cnp_prio_mode[0x1];
1739         u8         cnp_802p_prio[0x3];
1740
1741         u8         reserved_at_e0[0x720];
1742 };
1743
1744 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1745         u8         reserved_at_0[0x60];
1746
1747         u8         reserved_at_60[0x4];
1748         u8         clamp_tgt_rate[0x1];
1749         u8         reserved_at_65[0x3];
1750         u8         clamp_tgt_rate_after_time_inc[0x1];
1751         u8         reserved_at_69[0x17];
1752
1753         u8         reserved_at_80[0x20];
1754
1755         u8         rpg_time_reset[0x20];
1756
1757         u8         rpg_byte_reset[0x20];
1758
1759         u8         rpg_threshold[0x20];
1760
1761         u8         rpg_max_rate[0x20];
1762
1763         u8         rpg_ai_rate[0x20];
1764
1765         u8         rpg_hai_rate[0x20];
1766
1767         u8         rpg_gd[0x20];
1768
1769         u8         rpg_min_dec_fac[0x20];
1770
1771         u8         rpg_min_rate[0x20];
1772
1773         u8         reserved_at_1c0[0xe0];
1774
1775         u8         rate_to_set_on_first_cnp[0x20];
1776
1777         u8         dce_tcp_g[0x20];
1778
1779         u8         dce_tcp_rtt[0x20];
1780
1781         u8         rate_reduce_monitor_period[0x20];
1782
1783         u8         reserved_at_320[0x20];
1784
1785         u8         initial_alpha_value[0x20];
1786
1787         u8         reserved_at_360[0x4a0];
1788 };
1789
1790 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1791         u8         reserved_at_0[0x80];
1792
1793         u8         rppp_max_rps[0x20];
1794
1795         u8         rpg_time_reset[0x20];
1796
1797         u8         rpg_byte_reset[0x20];
1798
1799         u8         rpg_threshold[0x20];
1800
1801         u8         rpg_max_rate[0x20];
1802
1803         u8         rpg_ai_rate[0x20];
1804
1805         u8         rpg_hai_rate[0x20];
1806
1807         u8         rpg_gd[0x20];
1808
1809         u8         rpg_min_dec_fac[0x20];
1810
1811         u8         rpg_min_rate[0x20];
1812
1813         u8         reserved_at_1c0[0x640];
1814 };
1815
1816 enum {
1817         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1818         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1819         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1820 };
1821
1822 struct mlx5_ifc_resize_field_select_bits {
1823         u8         resize_field_select[0x20];
1824 };
1825
1826 struct mlx5_ifc_resource_dump_bits {
1827         u8         more_dump[0x1];
1828         u8         inline_dump[0x1];
1829         u8         reserved_at_2[0xa];
1830         u8         seq_num[0x4];
1831         u8         segment_type[0x10];
1832
1833         u8         reserved_at_20[0x10];
1834         u8         vhca_id[0x10];
1835
1836         u8         index1[0x20];
1837
1838         u8         index2[0x20];
1839
1840         u8         num_of_obj1[0x10];
1841         u8         num_of_obj2[0x10];
1842
1843         u8         reserved_at_a0[0x20];
1844
1845         u8         device_opaque[0x40];
1846
1847         u8         mkey[0x20];
1848
1849         u8         size[0x20];
1850
1851         u8         address[0x40];
1852
1853         u8         inline_data[52][0x20];
1854 };
1855
1856 struct mlx5_ifc_resource_dump_menu_record_bits {
1857         u8         reserved_at_0[0x4];
1858         u8         num_of_obj2_supports_active[0x1];
1859         u8         num_of_obj2_supports_all[0x1];
1860         u8         must_have_num_of_obj2[0x1];
1861         u8         support_num_of_obj2[0x1];
1862         u8         num_of_obj1_supports_active[0x1];
1863         u8         num_of_obj1_supports_all[0x1];
1864         u8         must_have_num_of_obj1[0x1];
1865         u8         support_num_of_obj1[0x1];
1866         u8         must_have_index2[0x1];
1867         u8         support_index2[0x1];
1868         u8         must_have_index1[0x1];
1869         u8         support_index1[0x1];
1870         u8         segment_type[0x10];
1871
1872         u8         segment_name[4][0x20];
1873
1874         u8         index1_name[4][0x20];
1875
1876         u8         index2_name[4][0x20];
1877 };
1878
1879 struct mlx5_ifc_resource_dump_segment_header_bits {
1880         u8         length_dw[0x10];
1881         u8         segment_type[0x10];
1882 };
1883
1884 struct mlx5_ifc_resource_dump_command_segment_bits {
1885         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1886
1887         u8         segment_called[0x10];
1888         u8         vhca_id[0x10];
1889
1890         u8         index1[0x20];
1891
1892         u8         index2[0x20];
1893
1894         u8         num_of_obj1[0x10];
1895         u8         num_of_obj2[0x10];
1896 };
1897
1898 struct mlx5_ifc_resource_dump_error_segment_bits {
1899         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1900
1901         u8         reserved_at_20[0x10];
1902         u8         syndrome_id[0x10];
1903
1904         u8         reserved_at_40[0x40];
1905
1906         u8         error[8][0x20];
1907 };
1908
1909 struct mlx5_ifc_resource_dump_info_segment_bits {
1910         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1911
1912         u8         reserved_at_20[0x18];
1913         u8         dump_version[0x8];
1914
1915         u8         hw_version[0x20];
1916
1917         u8         fw_version[0x20];
1918 };
1919
1920 struct mlx5_ifc_resource_dump_menu_segment_bits {
1921         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1922
1923         u8         reserved_at_20[0x10];
1924         u8         num_of_records[0x10];
1925
1926         struct mlx5_ifc_resource_dump_menu_record_bits record[];
1927 };
1928
1929 struct mlx5_ifc_resource_dump_resource_segment_bits {
1930         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1931
1932         u8         reserved_at_20[0x20];
1933
1934         u8         index1[0x20];
1935
1936         u8         index2[0x20];
1937
1938         u8         payload[][0x20];
1939 };
1940
1941 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1942         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1943 };
1944
1945 struct mlx5_ifc_menu_resource_dump_response_bits {
1946         struct mlx5_ifc_resource_dump_info_segment_bits info;
1947         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1948         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1949         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1950 };
1951
1952 enum {
1953         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1954         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1955         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1956         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1957 };
1958
1959 struct mlx5_ifc_modify_field_select_bits {
1960         u8         modify_field_select[0x20];
1961 };
1962
1963 struct mlx5_ifc_field_select_r_roce_np_bits {
1964         u8         field_select_r_roce_np[0x20];
1965 };
1966
1967 struct mlx5_ifc_field_select_r_roce_rp_bits {
1968         u8         field_select_r_roce_rp[0x20];
1969 };
1970
1971 enum {
1972         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1973         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1974         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1975         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1976         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1977         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1978         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1979         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1980         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1981         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1982 };
1983
1984 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1985         u8         field_select_8021qaurp[0x20];
1986 };
1987
1988 struct mlx5_ifc_phys_layer_cntrs_bits {
1989         u8         time_since_last_clear_high[0x20];
1990
1991         u8         time_since_last_clear_low[0x20];
1992
1993         u8         symbol_errors_high[0x20];
1994
1995         u8         symbol_errors_low[0x20];
1996
1997         u8         sync_headers_errors_high[0x20];
1998
1999         u8         sync_headers_errors_low[0x20];
2000
2001         u8         edpl_bip_errors_lane0_high[0x20];
2002
2003         u8         edpl_bip_errors_lane0_low[0x20];
2004
2005         u8         edpl_bip_errors_lane1_high[0x20];
2006
2007         u8         edpl_bip_errors_lane1_low[0x20];
2008
2009         u8         edpl_bip_errors_lane2_high[0x20];
2010
2011         u8         edpl_bip_errors_lane2_low[0x20];
2012
2013         u8         edpl_bip_errors_lane3_high[0x20];
2014
2015         u8         edpl_bip_errors_lane3_low[0x20];
2016
2017         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2018
2019         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2020
2021         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2022
2023         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2024
2025         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2026
2027         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2028
2029         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2030
2031         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2032
2033         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2034
2035         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2036
2037         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2038
2039         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2040
2041         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2042
2043         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2044
2045         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2046
2047         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2048
2049         u8         rs_fec_corrected_blocks_high[0x20];
2050
2051         u8         rs_fec_corrected_blocks_low[0x20];
2052
2053         u8         rs_fec_uncorrectable_blocks_high[0x20];
2054
2055         u8         rs_fec_uncorrectable_blocks_low[0x20];
2056
2057         u8         rs_fec_no_errors_blocks_high[0x20];
2058
2059         u8         rs_fec_no_errors_blocks_low[0x20];
2060
2061         u8         rs_fec_single_error_blocks_high[0x20];
2062
2063         u8         rs_fec_single_error_blocks_low[0x20];
2064
2065         u8         rs_fec_corrected_symbols_total_high[0x20];
2066
2067         u8         rs_fec_corrected_symbols_total_low[0x20];
2068
2069         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2070
2071         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2072
2073         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2074
2075         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2076
2077         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2078
2079         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2080
2081         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2082
2083         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2084
2085         u8         link_down_events[0x20];
2086
2087         u8         successful_recovery_events[0x20];
2088
2089         u8         reserved_at_640[0x180];
2090 };
2091
2092 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2093         u8         time_since_last_clear_high[0x20];
2094
2095         u8         time_since_last_clear_low[0x20];
2096
2097         u8         phy_received_bits_high[0x20];
2098
2099         u8         phy_received_bits_low[0x20];
2100
2101         u8         phy_symbol_errors_high[0x20];
2102
2103         u8         phy_symbol_errors_low[0x20];
2104
2105         u8         phy_corrected_bits_high[0x20];
2106
2107         u8         phy_corrected_bits_low[0x20];
2108
2109         u8         phy_corrected_bits_lane0_high[0x20];
2110
2111         u8         phy_corrected_bits_lane0_low[0x20];
2112
2113         u8         phy_corrected_bits_lane1_high[0x20];
2114
2115         u8         phy_corrected_bits_lane1_low[0x20];
2116
2117         u8         phy_corrected_bits_lane2_high[0x20];
2118
2119         u8         phy_corrected_bits_lane2_low[0x20];
2120
2121         u8         phy_corrected_bits_lane3_high[0x20];
2122
2123         u8         phy_corrected_bits_lane3_low[0x20];
2124
2125         u8         reserved_at_200[0x5c0];
2126 };
2127
2128 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2129         u8         symbol_error_counter[0x10];
2130
2131         u8         link_error_recovery_counter[0x8];
2132
2133         u8         link_downed_counter[0x8];
2134
2135         u8         port_rcv_errors[0x10];
2136
2137         u8         port_rcv_remote_physical_errors[0x10];
2138
2139         u8         port_rcv_switch_relay_errors[0x10];
2140
2141         u8         port_xmit_discards[0x10];
2142
2143         u8         port_xmit_constraint_errors[0x8];
2144
2145         u8         port_rcv_constraint_errors[0x8];
2146
2147         u8         reserved_at_70[0x8];
2148
2149         u8         link_overrun_errors[0x8];
2150
2151         u8         reserved_at_80[0x10];
2152
2153         u8         vl_15_dropped[0x10];
2154
2155         u8         reserved_at_a0[0x80];
2156
2157         u8         port_xmit_wait[0x20];
2158 };
2159
2160 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2161         u8         transmit_queue_high[0x20];
2162
2163         u8         transmit_queue_low[0x20];
2164
2165         u8         no_buffer_discard_uc_high[0x20];
2166
2167         u8         no_buffer_discard_uc_low[0x20];
2168
2169         u8         reserved_at_80[0x740];
2170 };
2171
2172 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2173         u8         wred_discard_high[0x20];
2174
2175         u8         wred_discard_low[0x20];
2176
2177         u8         ecn_marked_tc_high[0x20];
2178
2179         u8         ecn_marked_tc_low[0x20];
2180
2181         u8         reserved_at_80[0x740];
2182 };
2183
2184 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2185         u8         rx_octets_high[0x20];
2186
2187         u8         rx_octets_low[0x20];
2188
2189         u8         reserved_at_40[0xc0];
2190
2191         u8         rx_frames_high[0x20];
2192
2193         u8         rx_frames_low[0x20];
2194
2195         u8         tx_octets_high[0x20];
2196
2197         u8         tx_octets_low[0x20];
2198
2199         u8         reserved_at_180[0xc0];
2200
2201         u8         tx_frames_high[0x20];
2202
2203         u8         tx_frames_low[0x20];
2204
2205         u8         rx_pause_high[0x20];
2206
2207         u8         rx_pause_low[0x20];
2208
2209         u8         rx_pause_duration_high[0x20];
2210
2211         u8         rx_pause_duration_low[0x20];
2212
2213         u8         tx_pause_high[0x20];
2214
2215         u8         tx_pause_low[0x20];
2216
2217         u8         tx_pause_duration_high[0x20];
2218
2219         u8         tx_pause_duration_low[0x20];
2220
2221         u8         rx_pause_transition_high[0x20];
2222
2223         u8         rx_pause_transition_low[0x20];
2224
2225         u8         rx_discards_high[0x20];
2226
2227         u8         rx_discards_low[0x20];
2228
2229         u8         device_stall_minor_watermark_cnt_high[0x20];
2230
2231         u8         device_stall_minor_watermark_cnt_low[0x20];
2232
2233         u8         device_stall_critical_watermark_cnt_high[0x20];
2234
2235         u8         device_stall_critical_watermark_cnt_low[0x20];
2236
2237         u8         reserved_at_480[0x340];
2238 };
2239
2240 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2241         u8         port_transmit_wait_high[0x20];
2242
2243         u8         port_transmit_wait_low[0x20];
2244
2245         u8         reserved_at_40[0x100];
2246
2247         u8         rx_buffer_almost_full_high[0x20];
2248
2249         u8         rx_buffer_almost_full_low[0x20];
2250
2251         u8         rx_buffer_full_high[0x20];
2252
2253         u8         rx_buffer_full_low[0x20];
2254
2255         u8         rx_icrc_encapsulated_high[0x20];
2256
2257         u8         rx_icrc_encapsulated_low[0x20];
2258
2259         u8         reserved_at_200[0x5c0];
2260 };
2261
2262 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2263         u8         dot3stats_alignment_errors_high[0x20];
2264
2265         u8         dot3stats_alignment_errors_low[0x20];
2266
2267         u8         dot3stats_fcs_errors_high[0x20];
2268
2269         u8         dot3stats_fcs_errors_low[0x20];
2270
2271         u8         dot3stats_single_collision_frames_high[0x20];
2272
2273         u8         dot3stats_single_collision_frames_low[0x20];
2274
2275         u8         dot3stats_multiple_collision_frames_high[0x20];
2276
2277         u8         dot3stats_multiple_collision_frames_low[0x20];
2278
2279         u8         dot3stats_sqe_test_errors_high[0x20];
2280
2281         u8         dot3stats_sqe_test_errors_low[0x20];
2282
2283         u8         dot3stats_deferred_transmissions_high[0x20];
2284
2285         u8         dot3stats_deferred_transmissions_low[0x20];
2286
2287         u8         dot3stats_late_collisions_high[0x20];
2288
2289         u8         dot3stats_late_collisions_low[0x20];
2290
2291         u8         dot3stats_excessive_collisions_high[0x20];
2292
2293         u8         dot3stats_excessive_collisions_low[0x20];
2294
2295         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2296
2297         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2298
2299         u8         dot3stats_carrier_sense_errors_high[0x20];
2300
2301         u8         dot3stats_carrier_sense_errors_low[0x20];
2302
2303         u8         dot3stats_frame_too_longs_high[0x20];
2304
2305         u8         dot3stats_frame_too_longs_low[0x20];
2306
2307         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2308
2309         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2310
2311         u8         dot3stats_symbol_errors_high[0x20];
2312
2313         u8         dot3stats_symbol_errors_low[0x20];
2314
2315         u8         dot3control_in_unknown_opcodes_high[0x20];
2316
2317         u8         dot3control_in_unknown_opcodes_low[0x20];
2318
2319         u8         dot3in_pause_frames_high[0x20];
2320
2321         u8         dot3in_pause_frames_low[0x20];
2322
2323         u8         dot3out_pause_frames_high[0x20];
2324
2325         u8         dot3out_pause_frames_low[0x20];
2326
2327         u8         reserved_at_400[0x3c0];
2328 };
2329
2330 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2331         u8         ether_stats_drop_events_high[0x20];
2332
2333         u8         ether_stats_drop_events_low[0x20];
2334
2335         u8         ether_stats_octets_high[0x20];
2336
2337         u8         ether_stats_octets_low[0x20];
2338
2339         u8         ether_stats_pkts_high[0x20];
2340
2341         u8         ether_stats_pkts_low[0x20];
2342
2343         u8         ether_stats_broadcast_pkts_high[0x20];
2344
2345         u8         ether_stats_broadcast_pkts_low[0x20];
2346
2347         u8         ether_stats_multicast_pkts_high[0x20];
2348
2349         u8         ether_stats_multicast_pkts_low[0x20];
2350
2351         u8         ether_stats_crc_align_errors_high[0x20];
2352
2353         u8         ether_stats_crc_align_errors_low[0x20];
2354
2355         u8         ether_stats_undersize_pkts_high[0x20];
2356
2357         u8         ether_stats_undersize_pkts_low[0x20];
2358
2359         u8         ether_stats_oversize_pkts_high[0x20];
2360
2361         u8         ether_stats_oversize_pkts_low[0x20];
2362
2363         u8         ether_stats_fragments_high[0x20];
2364
2365         u8         ether_stats_fragments_low[0x20];
2366
2367         u8         ether_stats_jabbers_high[0x20];
2368
2369         u8         ether_stats_jabbers_low[0x20];
2370
2371         u8         ether_stats_collisions_high[0x20];
2372
2373         u8         ether_stats_collisions_low[0x20];
2374
2375         u8         ether_stats_pkts64octets_high[0x20];
2376
2377         u8         ether_stats_pkts64octets_low[0x20];
2378
2379         u8         ether_stats_pkts65to127octets_high[0x20];
2380
2381         u8         ether_stats_pkts65to127octets_low[0x20];
2382
2383         u8         ether_stats_pkts128to255octets_high[0x20];
2384
2385         u8         ether_stats_pkts128to255octets_low[0x20];
2386
2387         u8         ether_stats_pkts256to511octets_high[0x20];
2388
2389         u8         ether_stats_pkts256to511octets_low[0x20];
2390
2391         u8         ether_stats_pkts512to1023octets_high[0x20];
2392
2393         u8         ether_stats_pkts512to1023octets_low[0x20];
2394
2395         u8         ether_stats_pkts1024to1518octets_high[0x20];
2396
2397         u8         ether_stats_pkts1024to1518octets_low[0x20];
2398
2399         u8         ether_stats_pkts1519to2047octets_high[0x20];
2400
2401         u8         ether_stats_pkts1519to2047octets_low[0x20];
2402
2403         u8         ether_stats_pkts2048to4095octets_high[0x20];
2404
2405         u8         ether_stats_pkts2048to4095octets_low[0x20];
2406
2407         u8         ether_stats_pkts4096to8191octets_high[0x20];
2408
2409         u8         ether_stats_pkts4096to8191octets_low[0x20];
2410
2411         u8         ether_stats_pkts8192to10239octets_high[0x20];
2412
2413         u8         ether_stats_pkts8192to10239octets_low[0x20];
2414
2415         u8         reserved_at_540[0x280];
2416 };
2417
2418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2419         u8         if_in_octets_high[0x20];
2420
2421         u8         if_in_octets_low[0x20];
2422
2423         u8         if_in_ucast_pkts_high[0x20];
2424
2425         u8         if_in_ucast_pkts_low[0x20];
2426
2427         u8         if_in_discards_high[0x20];
2428
2429         u8         if_in_discards_low[0x20];
2430
2431         u8         if_in_errors_high[0x20];
2432
2433         u8         if_in_errors_low[0x20];
2434
2435         u8         if_in_unknown_protos_high[0x20];
2436
2437         u8         if_in_unknown_protos_low[0x20];
2438
2439         u8         if_out_octets_high[0x20];
2440
2441         u8         if_out_octets_low[0x20];
2442
2443         u8         if_out_ucast_pkts_high[0x20];
2444
2445         u8         if_out_ucast_pkts_low[0x20];
2446
2447         u8         if_out_discards_high[0x20];
2448
2449         u8         if_out_discards_low[0x20];
2450
2451         u8         if_out_errors_high[0x20];
2452
2453         u8         if_out_errors_low[0x20];
2454
2455         u8         if_in_multicast_pkts_high[0x20];
2456
2457         u8         if_in_multicast_pkts_low[0x20];
2458
2459         u8         if_in_broadcast_pkts_high[0x20];
2460
2461         u8         if_in_broadcast_pkts_low[0x20];
2462
2463         u8         if_out_multicast_pkts_high[0x20];
2464
2465         u8         if_out_multicast_pkts_low[0x20];
2466
2467         u8         if_out_broadcast_pkts_high[0x20];
2468
2469         u8         if_out_broadcast_pkts_low[0x20];
2470
2471         u8         reserved_at_340[0x480];
2472 };
2473
2474 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2475         u8         a_frames_transmitted_ok_high[0x20];
2476
2477         u8         a_frames_transmitted_ok_low[0x20];
2478
2479         u8         a_frames_received_ok_high[0x20];
2480
2481         u8         a_frames_received_ok_low[0x20];
2482
2483         u8         a_frame_check_sequence_errors_high[0x20];
2484
2485         u8         a_frame_check_sequence_errors_low[0x20];
2486
2487         u8         a_alignment_errors_high[0x20];
2488
2489         u8         a_alignment_errors_low[0x20];
2490
2491         u8         a_octets_transmitted_ok_high[0x20];
2492
2493         u8         a_octets_transmitted_ok_low[0x20];
2494
2495         u8         a_octets_received_ok_high[0x20];
2496
2497         u8         a_octets_received_ok_low[0x20];
2498
2499         u8         a_multicast_frames_xmitted_ok_high[0x20];
2500
2501         u8         a_multicast_frames_xmitted_ok_low[0x20];
2502
2503         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2504
2505         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2506
2507         u8         a_multicast_frames_received_ok_high[0x20];
2508
2509         u8         a_multicast_frames_received_ok_low[0x20];
2510
2511         u8         a_broadcast_frames_received_ok_high[0x20];
2512
2513         u8         a_broadcast_frames_received_ok_low[0x20];
2514
2515         u8         a_in_range_length_errors_high[0x20];
2516
2517         u8         a_in_range_length_errors_low[0x20];
2518
2519         u8         a_out_of_range_length_field_high[0x20];
2520
2521         u8         a_out_of_range_length_field_low[0x20];
2522
2523         u8         a_frame_too_long_errors_high[0x20];
2524
2525         u8         a_frame_too_long_errors_low[0x20];
2526
2527         u8         a_symbol_error_during_carrier_high[0x20];
2528
2529         u8         a_symbol_error_during_carrier_low[0x20];
2530
2531         u8         a_mac_control_frames_transmitted_high[0x20];
2532
2533         u8         a_mac_control_frames_transmitted_low[0x20];
2534
2535         u8         a_mac_control_frames_received_high[0x20];
2536
2537         u8         a_mac_control_frames_received_low[0x20];
2538
2539         u8         a_unsupported_opcodes_received_high[0x20];
2540
2541         u8         a_unsupported_opcodes_received_low[0x20];
2542
2543         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2544
2545         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2546
2547         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2548
2549         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2550
2551         u8         reserved_at_4c0[0x300];
2552 };
2553
2554 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2555         u8         life_time_counter_high[0x20];
2556
2557         u8         life_time_counter_low[0x20];
2558
2559         u8         rx_errors[0x20];
2560
2561         u8         tx_errors[0x20];
2562
2563         u8         l0_to_recovery_eieos[0x20];
2564
2565         u8         l0_to_recovery_ts[0x20];
2566
2567         u8         l0_to_recovery_framing[0x20];
2568
2569         u8         l0_to_recovery_retrain[0x20];
2570
2571         u8         crc_error_dllp[0x20];
2572
2573         u8         crc_error_tlp[0x20];
2574
2575         u8         tx_overflow_buffer_pkt_high[0x20];
2576
2577         u8         tx_overflow_buffer_pkt_low[0x20];
2578
2579         u8         outbound_stalled_reads[0x20];
2580
2581         u8         outbound_stalled_writes[0x20];
2582
2583         u8         outbound_stalled_reads_events[0x20];
2584
2585         u8         outbound_stalled_writes_events[0x20];
2586
2587         u8         reserved_at_200[0x5c0];
2588 };
2589
2590 struct mlx5_ifc_cmd_inter_comp_event_bits {
2591         u8         command_completion_vector[0x20];
2592
2593         u8         reserved_at_20[0xc0];
2594 };
2595
2596 struct mlx5_ifc_stall_vl_event_bits {
2597         u8         reserved_at_0[0x18];
2598         u8         port_num[0x1];
2599         u8         reserved_at_19[0x3];
2600         u8         vl[0x4];
2601
2602         u8         reserved_at_20[0xa0];
2603 };
2604
2605 struct mlx5_ifc_db_bf_congestion_event_bits {
2606         u8         event_subtype[0x8];
2607         u8         reserved_at_8[0x8];
2608         u8         congestion_level[0x8];
2609         u8         reserved_at_18[0x8];
2610
2611         u8         reserved_at_20[0xa0];
2612 };
2613
2614 struct mlx5_ifc_gpio_event_bits {
2615         u8         reserved_at_0[0x60];
2616
2617         u8         gpio_event_hi[0x20];
2618
2619         u8         gpio_event_lo[0x20];
2620
2621         u8         reserved_at_a0[0x40];
2622 };
2623
2624 struct mlx5_ifc_port_state_change_event_bits {
2625         u8         reserved_at_0[0x40];
2626
2627         u8         port_num[0x4];
2628         u8         reserved_at_44[0x1c];
2629
2630         u8         reserved_at_60[0x80];
2631 };
2632
2633 struct mlx5_ifc_dropped_packet_logged_bits {
2634         u8         reserved_at_0[0xe0];
2635 };
2636
2637 enum {
2638         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2639         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2640 };
2641
2642 struct mlx5_ifc_cq_error_bits {
2643         u8         reserved_at_0[0x8];
2644         u8         cqn[0x18];
2645
2646         u8         reserved_at_20[0x20];
2647
2648         u8         reserved_at_40[0x18];
2649         u8         syndrome[0x8];
2650
2651         u8         reserved_at_60[0x80];
2652 };
2653
2654 struct mlx5_ifc_rdma_page_fault_event_bits {
2655         u8         bytes_committed[0x20];
2656
2657         u8         r_key[0x20];
2658
2659         u8         reserved_at_40[0x10];
2660         u8         packet_len[0x10];
2661
2662         u8         rdma_op_len[0x20];
2663
2664         u8         rdma_va[0x40];
2665
2666         u8         reserved_at_c0[0x5];
2667         u8         rdma[0x1];
2668         u8         write[0x1];
2669         u8         requestor[0x1];
2670         u8         qp_number[0x18];
2671 };
2672
2673 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2674         u8         bytes_committed[0x20];
2675
2676         u8         reserved_at_20[0x10];
2677         u8         wqe_index[0x10];
2678
2679         u8         reserved_at_40[0x10];
2680         u8         len[0x10];
2681
2682         u8         reserved_at_60[0x60];
2683
2684         u8         reserved_at_c0[0x5];
2685         u8         rdma[0x1];
2686         u8         write_read[0x1];
2687         u8         requestor[0x1];
2688         u8         qpn[0x18];
2689 };
2690
2691 struct mlx5_ifc_qp_events_bits {
2692         u8         reserved_at_0[0xa0];
2693
2694         u8         type[0x8];
2695         u8         reserved_at_a8[0x18];
2696
2697         u8         reserved_at_c0[0x8];
2698         u8         qpn_rqn_sqn[0x18];
2699 };
2700
2701 struct mlx5_ifc_dct_events_bits {
2702         u8         reserved_at_0[0xc0];
2703
2704         u8         reserved_at_c0[0x8];
2705         u8         dct_number[0x18];
2706 };
2707
2708 struct mlx5_ifc_comp_event_bits {
2709         u8         reserved_at_0[0xc0];
2710
2711         u8         reserved_at_c0[0x8];
2712         u8         cq_number[0x18];
2713 };
2714
2715 enum {
2716         MLX5_QPC_STATE_RST        = 0x0,
2717         MLX5_QPC_STATE_INIT       = 0x1,
2718         MLX5_QPC_STATE_RTR        = 0x2,
2719         MLX5_QPC_STATE_RTS        = 0x3,
2720         MLX5_QPC_STATE_SQER       = 0x4,
2721         MLX5_QPC_STATE_ERR        = 0x6,
2722         MLX5_QPC_STATE_SQD        = 0x7,
2723         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2724 };
2725
2726 enum {
2727         MLX5_QPC_ST_RC            = 0x0,
2728         MLX5_QPC_ST_UC            = 0x1,
2729         MLX5_QPC_ST_UD            = 0x2,
2730         MLX5_QPC_ST_XRC           = 0x3,
2731         MLX5_QPC_ST_DCI           = 0x5,
2732         MLX5_QPC_ST_QP0           = 0x7,
2733         MLX5_QPC_ST_QP1           = 0x8,
2734         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2735         MLX5_QPC_ST_REG_UMR       = 0xc,
2736 };
2737
2738 enum {
2739         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2740         MLX5_QPC_PM_STATE_REARM     = 0x1,
2741         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2742         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2743 };
2744
2745 enum {
2746         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2747 };
2748
2749 enum {
2750         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2751         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2752 };
2753
2754 enum {
2755         MLX5_QPC_MTU_256_BYTES        = 0x1,
2756         MLX5_QPC_MTU_512_BYTES        = 0x2,
2757         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2758         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2759         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2760         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2761 };
2762
2763 enum {
2764         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2765         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2766         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2767         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2768         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2769         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2770         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2771         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2772 };
2773
2774 enum {
2775         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2776         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2777         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2778 };
2779
2780 enum {
2781         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2782         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2783         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2784 };
2785
2786 struct mlx5_ifc_qpc_bits {
2787         u8         state[0x4];
2788         u8         lag_tx_port_affinity[0x4];
2789         u8         st[0x8];
2790         u8         reserved_at_10[0x3];
2791         u8         pm_state[0x2];
2792         u8         reserved_at_15[0x1];
2793         u8         req_e2e_credit_mode[0x2];
2794         u8         offload_type[0x4];
2795         u8         end_padding_mode[0x2];
2796         u8         reserved_at_1e[0x2];
2797
2798         u8         wq_signature[0x1];
2799         u8         block_lb_mc[0x1];
2800         u8         atomic_like_write_en[0x1];
2801         u8         latency_sensitive[0x1];
2802         u8         reserved_at_24[0x1];
2803         u8         drain_sigerr[0x1];
2804         u8         reserved_at_26[0x2];
2805         u8         pd[0x18];
2806
2807         u8         mtu[0x3];
2808         u8         log_msg_max[0x5];
2809         u8         reserved_at_48[0x1];
2810         u8         log_rq_size[0x4];
2811         u8         log_rq_stride[0x3];
2812         u8         no_sq[0x1];
2813         u8         log_sq_size[0x4];
2814         u8         reserved_at_55[0x6];
2815         u8         rlky[0x1];
2816         u8         ulp_stateless_offload_mode[0x4];
2817
2818         u8         counter_set_id[0x8];
2819         u8         uar_page[0x18];
2820
2821         u8         reserved_at_80[0x8];
2822         u8         user_index[0x18];
2823
2824         u8         reserved_at_a0[0x3];
2825         u8         log_page_size[0x5];
2826         u8         remote_qpn[0x18];
2827
2828         struct mlx5_ifc_ads_bits primary_address_path;
2829
2830         struct mlx5_ifc_ads_bits secondary_address_path;
2831
2832         u8         log_ack_req_freq[0x4];
2833         u8         reserved_at_384[0x4];
2834         u8         log_sra_max[0x3];
2835         u8         reserved_at_38b[0x2];
2836         u8         retry_count[0x3];
2837         u8         rnr_retry[0x3];
2838         u8         reserved_at_393[0x1];
2839         u8         fre[0x1];
2840         u8         cur_rnr_retry[0x3];
2841         u8         cur_retry_count[0x3];
2842         u8         reserved_at_39b[0x5];
2843
2844         u8         reserved_at_3a0[0x20];
2845
2846         u8         reserved_at_3c0[0x8];
2847         u8         next_send_psn[0x18];
2848
2849         u8         reserved_at_3e0[0x8];
2850         u8         cqn_snd[0x18];
2851
2852         u8         reserved_at_400[0x8];
2853         u8         deth_sqpn[0x18];
2854
2855         u8         reserved_at_420[0x20];
2856
2857         u8         reserved_at_440[0x8];
2858         u8         last_acked_psn[0x18];
2859
2860         u8         reserved_at_460[0x8];
2861         u8         ssn[0x18];
2862
2863         u8         reserved_at_480[0x8];
2864         u8         log_rra_max[0x3];
2865         u8         reserved_at_48b[0x1];
2866         u8         atomic_mode[0x4];
2867         u8         rre[0x1];
2868         u8         rwe[0x1];
2869         u8         rae[0x1];
2870         u8         reserved_at_493[0x1];
2871         u8         page_offset[0x6];
2872         u8         reserved_at_49a[0x3];
2873         u8         cd_slave_receive[0x1];
2874         u8         cd_slave_send[0x1];
2875         u8         cd_master[0x1];
2876
2877         u8         reserved_at_4a0[0x3];
2878         u8         min_rnr_nak[0x5];
2879         u8         next_rcv_psn[0x18];
2880
2881         u8         reserved_at_4c0[0x8];
2882         u8         xrcd[0x18];
2883
2884         u8         reserved_at_4e0[0x8];
2885         u8         cqn_rcv[0x18];
2886
2887         u8         dbr_addr[0x40];
2888
2889         u8         q_key[0x20];
2890
2891         u8         reserved_at_560[0x5];
2892         u8         rq_type[0x3];
2893         u8         srqn_rmpn_xrqn[0x18];
2894
2895         u8         reserved_at_580[0x8];
2896         u8         rmsn[0x18];
2897
2898         u8         hw_sq_wqebb_counter[0x10];
2899         u8         sw_sq_wqebb_counter[0x10];
2900
2901         u8         hw_rq_counter[0x20];
2902
2903         u8         sw_rq_counter[0x20];
2904
2905         u8         reserved_at_600[0x20];
2906
2907         u8         reserved_at_620[0xf];
2908         u8         cgs[0x1];
2909         u8         cs_req[0x8];
2910         u8         cs_res[0x8];
2911
2912         u8         dc_access_key[0x40];
2913
2914         u8         reserved_at_680[0x3];
2915         u8         dbr_umem_valid[0x1];
2916
2917         u8         reserved_at_684[0xbc];
2918 };
2919
2920 struct mlx5_ifc_roce_addr_layout_bits {
2921         u8         source_l3_address[16][0x8];
2922
2923         u8         reserved_at_80[0x3];
2924         u8         vlan_valid[0x1];
2925         u8         vlan_id[0xc];
2926         u8         source_mac_47_32[0x10];
2927
2928         u8         source_mac_31_0[0x20];
2929
2930         u8         reserved_at_c0[0x14];
2931         u8         roce_l3_type[0x4];
2932         u8         roce_version[0x8];
2933
2934         u8         reserved_at_e0[0x20];
2935 };
2936
2937 union mlx5_ifc_hca_cap_union_bits {
2938         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2939         struct mlx5_ifc_odp_cap_bits odp_cap;
2940         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2941         struct mlx5_ifc_roce_cap_bits roce_cap;
2942         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2943         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2944         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2945         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2946         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2947         struct mlx5_ifc_qos_cap_bits qos_cap;
2948         struct mlx5_ifc_debug_cap_bits debug_cap;
2949         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2950         struct mlx5_ifc_tls_cap_bits tls_cap;
2951         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2952         struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2953         u8         reserved_at_0[0x8000];
2954 };
2955
2956 enum {
2957         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2958         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2959         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2960         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2961         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2962         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2963         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2964         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2965         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2966         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2967         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2968 };
2969
2970 enum {
2971         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2972         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2973         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2974 };
2975
2976 struct mlx5_ifc_vlan_bits {
2977         u8         ethtype[0x10];
2978         u8         prio[0x3];
2979         u8         cfi[0x1];
2980         u8         vid[0xc];
2981 };
2982
2983 struct mlx5_ifc_flow_context_bits {
2984         struct mlx5_ifc_vlan_bits push_vlan;
2985
2986         u8         group_id[0x20];
2987
2988         u8         reserved_at_40[0x8];
2989         u8         flow_tag[0x18];
2990
2991         u8         reserved_at_60[0x10];
2992         u8         action[0x10];
2993
2994         u8         extended_destination[0x1];
2995         u8         reserved_at_81[0x1];
2996         u8         flow_source[0x2];
2997         u8         reserved_at_84[0x4];
2998         u8         destination_list_size[0x18];
2999
3000         u8         reserved_at_a0[0x8];
3001         u8         flow_counter_list_size[0x18];
3002
3003         u8         packet_reformat_id[0x20];
3004
3005         u8         modify_header_id[0x20];
3006
3007         struct mlx5_ifc_vlan_bits push_vlan_2;
3008
3009         u8         reserved_at_120[0xe0];
3010
3011         struct mlx5_ifc_fte_match_param_bits match_value;
3012
3013         u8         reserved_at_1200[0x600];
3014
3015         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3016 };
3017
3018 enum {
3019         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3020         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3021 };
3022
3023 struct mlx5_ifc_xrc_srqc_bits {
3024         u8         state[0x4];
3025         u8         log_xrc_srq_size[0x4];
3026         u8         reserved_at_8[0x18];
3027
3028         u8         wq_signature[0x1];
3029         u8         cont_srq[0x1];
3030         u8         reserved_at_22[0x1];
3031         u8         rlky[0x1];
3032         u8         basic_cyclic_rcv_wqe[0x1];
3033         u8         log_rq_stride[0x3];
3034         u8         xrcd[0x18];
3035
3036         u8         page_offset[0x6];
3037         u8         reserved_at_46[0x1];
3038         u8         dbr_umem_valid[0x1];
3039         u8         cqn[0x18];
3040
3041         u8         reserved_at_60[0x20];
3042
3043         u8         user_index_equal_xrc_srqn[0x1];
3044         u8         reserved_at_81[0x1];
3045         u8         log_page_size[0x6];
3046         u8         user_index[0x18];
3047
3048         u8         reserved_at_a0[0x20];
3049
3050         u8         reserved_at_c0[0x8];
3051         u8         pd[0x18];
3052
3053         u8         lwm[0x10];
3054         u8         wqe_cnt[0x10];
3055
3056         u8         reserved_at_100[0x40];
3057
3058         u8         db_record_addr_h[0x20];
3059
3060         u8         db_record_addr_l[0x1e];
3061         u8         reserved_at_17e[0x2];
3062
3063         u8         reserved_at_180[0x80];
3064 };
3065
3066 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3067         u8         counter_error_queues[0x20];
3068
3069         u8         total_error_queues[0x20];
3070
3071         u8         send_queue_priority_update_flow[0x20];
3072
3073         u8         reserved_at_60[0x20];
3074
3075         u8         nic_receive_steering_discard[0x40];
3076
3077         u8         receive_discard_vport_down[0x40];
3078
3079         u8         transmit_discard_vport_down[0x40];
3080
3081         u8         reserved_at_140[0xa0];
3082
3083         u8         internal_rq_out_of_buffer[0x20];
3084
3085         u8         reserved_at_200[0xe00];
3086 };
3087
3088 struct mlx5_ifc_traffic_counter_bits {
3089         u8         packets[0x40];
3090
3091         u8         octets[0x40];
3092 };
3093
3094 struct mlx5_ifc_tisc_bits {
3095         u8         strict_lag_tx_port_affinity[0x1];
3096         u8         tls_en[0x1];
3097         u8         reserved_at_2[0x2];
3098         u8         lag_tx_port_affinity[0x04];
3099
3100         u8         reserved_at_8[0x4];
3101         u8         prio[0x4];
3102         u8         reserved_at_10[0x10];
3103
3104         u8         reserved_at_20[0x100];
3105
3106         u8         reserved_at_120[0x8];
3107         u8         transport_domain[0x18];
3108
3109         u8         reserved_at_140[0x8];
3110         u8         underlay_qpn[0x18];
3111
3112         u8         reserved_at_160[0x8];
3113         u8         pd[0x18];
3114
3115         u8         reserved_at_180[0x380];
3116 };
3117
3118 enum {
3119         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3120         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3121 };
3122
3123 enum {
3124         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3125         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3126 };
3127
3128 enum {
3129         MLX5_RX_HASH_FN_NONE           = 0x0,
3130         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3131         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3132 };
3133
3134 enum {
3135         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3136         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3137 };
3138
3139 struct mlx5_ifc_tirc_bits {
3140         u8         reserved_at_0[0x20];
3141
3142         u8         disp_type[0x4];
3143         u8         tls_en[0x1];
3144         u8         reserved_at_25[0x1b];
3145
3146         u8         reserved_at_40[0x40];
3147
3148         u8         reserved_at_80[0x4];
3149         u8         lro_timeout_period_usecs[0x10];
3150         u8         lro_enable_mask[0x4];
3151         u8         lro_max_ip_payload_size[0x8];
3152
3153         u8         reserved_at_a0[0x40];
3154
3155         u8         reserved_at_e0[0x8];
3156         u8         inline_rqn[0x18];
3157
3158         u8         rx_hash_symmetric[0x1];
3159         u8         reserved_at_101[0x1];
3160         u8         tunneled_offload_en[0x1];
3161         u8         reserved_at_103[0x5];
3162         u8         indirect_table[0x18];
3163
3164         u8         rx_hash_fn[0x4];
3165         u8         reserved_at_124[0x2];
3166         u8         self_lb_block[0x2];
3167         u8         transport_domain[0x18];
3168
3169         u8         rx_hash_toeplitz_key[10][0x20];
3170
3171         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3172
3173         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3174
3175         u8         reserved_at_2c0[0x4c0];
3176 };
3177
3178 enum {
3179         MLX5_SRQC_STATE_GOOD   = 0x0,
3180         MLX5_SRQC_STATE_ERROR  = 0x1,
3181 };
3182
3183 struct mlx5_ifc_srqc_bits {
3184         u8         state[0x4];
3185         u8         log_srq_size[0x4];
3186         u8         reserved_at_8[0x18];
3187
3188         u8         wq_signature[0x1];
3189         u8         cont_srq[0x1];
3190         u8         reserved_at_22[0x1];
3191         u8         rlky[0x1];
3192         u8         reserved_at_24[0x1];
3193         u8         log_rq_stride[0x3];
3194         u8         xrcd[0x18];
3195
3196         u8         page_offset[0x6];
3197         u8         reserved_at_46[0x2];
3198         u8         cqn[0x18];
3199
3200         u8         reserved_at_60[0x20];
3201
3202         u8         reserved_at_80[0x2];
3203         u8         log_page_size[0x6];
3204         u8         reserved_at_88[0x18];
3205
3206         u8         reserved_at_a0[0x20];
3207
3208         u8         reserved_at_c0[0x8];
3209         u8         pd[0x18];
3210
3211         u8         lwm[0x10];
3212         u8         wqe_cnt[0x10];
3213
3214         u8         reserved_at_100[0x40];
3215
3216         u8         dbr_addr[0x40];
3217
3218         u8         reserved_at_180[0x80];
3219 };
3220
3221 enum {
3222         MLX5_SQC_STATE_RST  = 0x0,
3223         MLX5_SQC_STATE_RDY  = 0x1,
3224         MLX5_SQC_STATE_ERR  = 0x3,
3225 };
3226
3227 struct mlx5_ifc_sqc_bits {
3228         u8         rlky[0x1];
3229         u8         cd_master[0x1];
3230         u8         fre[0x1];
3231         u8         flush_in_error_en[0x1];
3232         u8         allow_multi_pkt_send_wqe[0x1];
3233         u8         min_wqe_inline_mode[0x3];
3234         u8         state[0x4];
3235         u8         reg_umr[0x1];
3236         u8         allow_swp[0x1];
3237         u8         hairpin[0x1];
3238         u8         reserved_at_f[0x11];
3239
3240         u8         reserved_at_20[0x8];
3241         u8         user_index[0x18];
3242
3243         u8         reserved_at_40[0x8];
3244         u8         cqn[0x18];
3245
3246         u8         reserved_at_60[0x8];
3247         u8         hairpin_peer_rq[0x18];
3248
3249         u8         reserved_at_80[0x10];
3250         u8         hairpin_peer_vhca[0x10];
3251
3252         u8         reserved_at_a0[0x50];
3253
3254         u8         packet_pacing_rate_limit_index[0x10];
3255         u8         tis_lst_sz[0x10];
3256         u8         reserved_at_110[0x10];
3257
3258         u8         reserved_at_120[0x40];
3259
3260         u8         reserved_at_160[0x8];
3261         u8         tis_num_0[0x18];
3262
3263         struct mlx5_ifc_wq_bits wq;
3264 };
3265
3266 enum {
3267         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3268         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3269         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3270         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3271 };
3272
3273 enum {
3274         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3275         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3276         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3277         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3278 };
3279
3280 struct mlx5_ifc_scheduling_context_bits {
3281         u8         element_type[0x8];
3282         u8         reserved_at_8[0x18];
3283
3284         u8         element_attributes[0x20];
3285
3286         u8         parent_element_id[0x20];
3287
3288         u8         reserved_at_60[0x40];
3289
3290         u8         bw_share[0x20];
3291
3292         u8         max_average_bw[0x20];
3293
3294         u8         reserved_at_e0[0x120];
3295 };
3296
3297 struct mlx5_ifc_rqtc_bits {
3298         u8         reserved_at_0[0xa0];
3299
3300         u8         reserved_at_a0[0x10];
3301         u8         rqt_max_size[0x10];
3302
3303         u8         reserved_at_c0[0x10];
3304         u8         rqt_actual_size[0x10];
3305
3306         u8         reserved_at_e0[0x6a0];
3307
3308         struct mlx5_ifc_rq_num_bits rq_num[];
3309 };
3310
3311 enum {
3312         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3313         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3314 };
3315
3316 enum {
3317         MLX5_RQC_STATE_RST  = 0x0,
3318         MLX5_RQC_STATE_RDY  = 0x1,
3319         MLX5_RQC_STATE_ERR  = 0x3,
3320 };
3321
3322 struct mlx5_ifc_rqc_bits {
3323         u8         rlky[0x1];
3324         u8         delay_drop_en[0x1];
3325         u8         scatter_fcs[0x1];
3326         u8         vsd[0x1];
3327         u8         mem_rq_type[0x4];
3328         u8         state[0x4];
3329         u8         reserved_at_c[0x1];
3330         u8         flush_in_error_en[0x1];
3331         u8         hairpin[0x1];
3332         u8         reserved_at_f[0x11];
3333
3334         u8         reserved_at_20[0x8];
3335         u8         user_index[0x18];
3336
3337         u8         reserved_at_40[0x8];
3338         u8         cqn[0x18];
3339
3340         u8         counter_set_id[0x8];
3341         u8         reserved_at_68[0x18];
3342
3343         u8         reserved_at_80[0x8];
3344         u8         rmpn[0x18];
3345
3346         u8         reserved_at_a0[0x8];
3347         u8         hairpin_peer_sq[0x18];
3348
3349         u8         reserved_at_c0[0x10];
3350         u8         hairpin_peer_vhca[0x10];
3351
3352         u8         reserved_at_e0[0xa0];
3353
3354         struct mlx5_ifc_wq_bits wq;
3355 };
3356
3357 enum {
3358         MLX5_RMPC_STATE_RDY  = 0x1,
3359         MLX5_RMPC_STATE_ERR  = 0x3,
3360 };
3361
3362 struct mlx5_ifc_rmpc_bits {
3363         u8         reserved_at_0[0x8];
3364         u8         state[0x4];
3365         u8         reserved_at_c[0x14];
3366
3367         u8         basic_cyclic_rcv_wqe[0x1];
3368         u8         reserved_at_21[0x1f];
3369
3370         u8         reserved_at_40[0x140];
3371
3372         struct mlx5_ifc_wq_bits wq;
3373 };
3374
3375 struct mlx5_ifc_nic_vport_context_bits {
3376         u8         reserved_at_0[0x5];
3377         u8         min_wqe_inline_mode[0x3];
3378         u8         reserved_at_8[0x15];
3379         u8         disable_mc_local_lb[0x1];
3380         u8         disable_uc_local_lb[0x1];
3381         u8         roce_en[0x1];
3382
3383         u8         arm_change_event[0x1];
3384         u8         reserved_at_21[0x1a];
3385         u8         event_on_mtu[0x1];
3386         u8         event_on_promisc_change[0x1];
3387         u8         event_on_vlan_change[0x1];
3388         u8         event_on_mc_address_change[0x1];
3389         u8         event_on_uc_address_change[0x1];
3390
3391         u8         reserved_at_40[0xc];
3392
3393         u8         affiliation_criteria[0x4];
3394         u8         affiliated_vhca_id[0x10];
3395
3396         u8         reserved_at_60[0xd0];
3397
3398         u8         mtu[0x10];
3399
3400         u8         system_image_guid[0x40];
3401         u8         port_guid[0x40];
3402         u8         node_guid[0x40];
3403
3404         u8         reserved_at_200[0x140];
3405         u8         qkey_violation_counter[0x10];
3406         u8         reserved_at_350[0x430];
3407
3408         u8         promisc_uc[0x1];
3409         u8         promisc_mc[0x1];
3410         u8         promisc_all[0x1];
3411         u8         reserved_at_783[0x2];
3412         u8         allowed_list_type[0x3];
3413         u8         reserved_at_788[0xc];
3414         u8         allowed_list_size[0xc];
3415
3416         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3417
3418         u8         reserved_at_7e0[0x20];
3419
3420         u8         current_uc_mac_address[][0x40];
3421 };
3422
3423 enum {
3424         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3425         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3426         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3427         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3428         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3429         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3430 };
3431
3432 struct mlx5_ifc_mkc_bits {
3433         u8         reserved_at_0[0x1];
3434         u8         free[0x1];
3435         u8         reserved_at_2[0x1];
3436         u8         access_mode_4_2[0x3];
3437         u8         reserved_at_6[0x7];
3438         u8         relaxed_ordering_write[0x1];
3439         u8         reserved_at_e[0x1];
3440         u8         small_fence_on_rdma_read_response[0x1];
3441         u8         umr_en[0x1];
3442         u8         a[0x1];
3443         u8         rw[0x1];
3444         u8         rr[0x1];
3445         u8         lw[0x1];
3446         u8         lr[0x1];
3447         u8         access_mode_1_0[0x2];
3448         u8         reserved_at_18[0x8];
3449
3450         u8         qpn[0x18];
3451         u8         mkey_7_0[0x8];
3452
3453         u8         reserved_at_40[0x20];
3454
3455         u8         length64[0x1];
3456         u8         bsf_en[0x1];
3457         u8         sync_umr[0x1];
3458         u8         reserved_at_63[0x2];
3459         u8         expected_sigerr_count[0x1];
3460         u8         reserved_at_66[0x1];
3461         u8         en_rinval[0x1];
3462         u8         pd[0x18];
3463
3464         u8         start_addr[0x40];
3465
3466         u8         len[0x40];
3467
3468         u8         bsf_octword_size[0x20];
3469
3470         u8         reserved_at_120[0x80];
3471
3472         u8         translations_octword_size[0x20];
3473
3474         u8         reserved_at_1c0[0x19];
3475         u8         relaxed_ordering_read[0x1];
3476         u8         reserved_at_1d9[0x1];
3477         u8         log_page_size[0x5];
3478
3479         u8         reserved_at_1e0[0x20];
3480 };
3481
3482 struct mlx5_ifc_pkey_bits {
3483         u8         reserved_at_0[0x10];
3484         u8         pkey[0x10];
3485 };
3486
3487 struct mlx5_ifc_array128_auto_bits {
3488         u8         array128_auto[16][0x8];
3489 };
3490
3491 struct mlx5_ifc_hca_vport_context_bits {
3492         u8         field_select[0x20];
3493
3494         u8         reserved_at_20[0xe0];
3495
3496         u8         sm_virt_aware[0x1];
3497         u8         has_smi[0x1];
3498         u8         has_raw[0x1];
3499         u8         grh_required[0x1];
3500         u8         reserved_at_104[0xc];
3501         u8         port_physical_state[0x4];
3502         u8         vport_state_policy[0x4];
3503         u8         port_state[0x4];
3504         u8         vport_state[0x4];
3505
3506         u8         reserved_at_120[0x20];
3507
3508         u8         system_image_guid[0x40];
3509
3510         u8         port_guid[0x40];
3511
3512         u8         node_guid[0x40];
3513
3514         u8         cap_mask1[0x20];
3515
3516         u8         cap_mask1_field_select[0x20];
3517
3518         u8         cap_mask2[0x20];
3519
3520         u8         cap_mask2_field_select[0x20];
3521
3522         u8         reserved_at_280[0x80];
3523
3524         u8         lid[0x10];
3525         u8         reserved_at_310[0x4];
3526         u8         init_type_reply[0x4];
3527         u8         lmc[0x3];
3528         u8         subnet_timeout[0x5];
3529
3530         u8         sm_lid[0x10];
3531         u8         sm_sl[0x4];
3532         u8         reserved_at_334[0xc];
3533
3534         u8         qkey_violation_counter[0x10];
3535         u8         pkey_violation_counter[0x10];
3536
3537         u8         reserved_at_360[0xca0];
3538 };
3539
3540 struct mlx5_ifc_esw_vport_context_bits {
3541         u8         fdb_to_vport_reg_c[0x1];
3542         u8         reserved_at_1[0x2];
3543         u8         vport_svlan_strip[0x1];
3544         u8         vport_cvlan_strip[0x1];
3545         u8         vport_svlan_insert[0x1];
3546         u8         vport_cvlan_insert[0x2];
3547         u8         fdb_to_vport_reg_c_id[0x8];
3548         u8         reserved_at_10[0x10];
3549
3550         u8         reserved_at_20[0x20];
3551
3552         u8         svlan_cfi[0x1];
3553         u8         svlan_pcp[0x3];
3554         u8         svlan_id[0xc];
3555         u8         cvlan_cfi[0x1];
3556         u8         cvlan_pcp[0x3];
3557         u8         cvlan_id[0xc];
3558
3559         u8         reserved_at_60[0x720];
3560
3561         u8         sw_steering_vport_icm_address_rx[0x40];
3562
3563         u8         sw_steering_vport_icm_address_tx[0x40];
3564 };
3565
3566 enum {
3567         MLX5_EQC_STATUS_OK                = 0x0,
3568         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3569 };
3570
3571 enum {
3572         MLX5_EQC_ST_ARMED  = 0x9,
3573         MLX5_EQC_ST_FIRED  = 0xa,
3574 };
3575
3576 struct mlx5_ifc_eqc_bits {
3577         u8         status[0x4];
3578         u8         reserved_at_4[0x9];
3579         u8         ec[0x1];
3580         u8         oi[0x1];
3581         u8         reserved_at_f[0x5];
3582         u8         st[0x4];
3583         u8         reserved_at_18[0x8];
3584
3585         u8         reserved_at_20[0x20];
3586
3587         u8         reserved_at_40[0x14];
3588         u8         page_offset[0x6];
3589         u8         reserved_at_5a[0x6];
3590
3591         u8         reserved_at_60[0x3];
3592         u8         log_eq_size[0x5];
3593         u8         uar_page[0x18];
3594
3595         u8         reserved_at_80[0x20];
3596
3597         u8         reserved_at_a0[0x18];
3598         u8         intr[0x8];
3599
3600         u8         reserved_at_c0[0x3];
3601         u8         log_page_size[0x5];
3602         u8         reserved_at_c8[0x18];
3603
3604         u8         reserved_at_e0[0x60];
3605
3606         u8         reserved_at_140[0x8];
3607         u8         consumer_counter[0x18];
3608
3609         u8         reserved_at_160[0x8];
3610         u8         producer_counter[0x18];
3611
3612         u8         reserved_at_180[0x80];
3613 };
3614
3615 enum {
3616         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3617         MLX5_DCTC_STATE_DRAINING  = 0x1,
3618         MLX5_DCTC_STATE_DRAINED   = 0x2,
3619 };
3620
3621 enum {
3622         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3623         MLX5_DCTC_CS_RES_NA         = 0x1,
3624         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3625 };
3626
3627 enum {
3628         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3629         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3630         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3631         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3632         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3633 };
3634
3635 struct mlx5_ifc_dctc_bits {
3636         u8         reserved_at_0[0x4];
3637         u8         state[0x4];
3638         u8         reserved_at_8[0x18];
3639
3640         u8         reserved_at_20[0x8];
3641         u8         user_index[0x18];
3642
3643         u8         reserved_at_40[0x8];
3644         u8         cqn[0x18];
3645
3646         u8         counter_set_id[0x8];
3647         u8         atomic_mode[0x4];
3648         u8         rre[0x1];
3649         u8         rwe[0x1];
3650         u8         rae[0x1];
3651         u8         atomic_like_write_en[0x1];
3652         u8         latency_sensitive[0x1];
3653         u8         rlky[0x1];
3654         u8         free_ar[0x1];
3655         u8         reserved_at_73[0xd];
3656
3657         u8         reserved_at_80[0x8];
3658         u8         cs_res[0x8];
3659         u8         reserved_at_90[0x3];
3660         u8         min_rnr_nak[0x5];
3661         u8         reserved_at_98[0x8];
3662
3663         u8         reserved_at_a0[0x8];
3664         u8         srqn_xrqn[0x18];
3665
3666         u8         reserved_at_c0[0x8];
3667         u8         pd[0x18];
3668
3669         u8         tclass[0x8];
3670         u8         reserved_at_e8[0x4];
3671         u8         flow_label[0x14];
3672
3673         u8         dc_access_key[0x40];
3674
3675         u8         reserved_at_140[0x5];
3676         u8         mtu[0x3];
3677         u8         port[0x8];
3678         u8         pkey_index[0x10];
3679
3680         u8         reserved_at_160[0x8];
3681         u8         my_addr_index[0x8];
3682         u8         reserved_at_170[0x8];
3683         u8         hop_limit[0x8];
3684
3685         u8         dc_access_key_violation_count[0x20];
3686
3687         u8         reserved_at_1a0[0x14];
3688         u8         dei_cfi[0x1];
3689         u8         eth_prio[0x3];
3690         u8         ecn[0x2];
3691         u8         dscp[0x6];
3692
3693         u8         reserved_at_1c0[0x40];
3694 };
3695
3696 enum {
3697         MLX5_CQC_STATUS_OK             = 0x0,
3698         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3699         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3700 };
3701
3702 enum {
3703         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3704         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3705 };
3706
3707 enum {
3708         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3709         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3710         MLX5_CQC_ST_FIRED                                 = 0xa,
3711 };
3712
3713 enum {
3714         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3715         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3716         MLX5_CQ_PERIOD_NUM_MODES
3717 };
3718
3719 struct mlx5_ifc_cqc_bits {
3720         u8         status[0x4];
3721         u8         reserved_at_4[0x2];
3722         u8         dbr_umem_valid[0x1];
3723         u8         reserved_at_7[0x1];
3724         u8         cqe_sz[0x3];
3725         u8         cc[0x1];
3726         u8         reserved_at_c[0x1];
3727         u8         scqe_break_moderation_en[0x1];
3728         u8         oi[0x1];
3729         u8         cq_period_mode[0x2];
3730         u8         cqe_comp_en[0x1];
3731         u8         mini_cqe_res_format[0x2];
3732         u8         st[0x4];
3733         u8         reserved_at_18[0x8];
3734
3735         u8         reserved_at_20[0x20];
3736
3737         u8         reserved_at_40[0x14];
3738         u8         page_offset[0x6];
3739         u8         reserved_at_5a[0x6];
3740
3741         u8         reserved_at_60[0x3];
3742         u8         log_cq_size[0x5];
3743         u8         uar_page[0x18];
3744
3745         u8         reserved_at_80[0x4];
3746         u8         cq_period[0xc];
3747         u8         cq_max_count[0x10];
3748
3749         u8         reserved_at_a0[0x18];
3750         u8         c_eqn[0x8];
3751
3752         u8         reserved_at_c0[0x3];
3753         u8         log_page_size[0x5];
3754         u8         reserved_at_c8[0x18];
3755
3756         u8         reserved_at_e0[0x20];
3757
3758         u8         reserved_at_100[0x8];
3759         u8         last_notified_index[0x18];
3760
3761         u8         reserved_at_120[0x8];
3762         u8         last_solicit_index[0x18];
3763
3764         u8         reserved_at_140[0x8];
3765         u8         consumer_counter[0x18];
3766
3767         u8         reserved_at_160[0x8];
3768         u8         producer_counter[0x18];
3769
3770         u8         reserved_at_180[0x40];
3771
3772         u8         dbr_addr[0x40];
3773 };
3774
3775 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3776         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3777         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3778         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3779         u8         reserved_at_0[0x800];
3780 };
3781
3782 struct mlx5_ifc_query_adapter_param_block_bits {
3783         u8         reserved_at_0[0xc0];
3784
3785         u8         reserved_at_c0[0x8];
3786         u8         ieee_vendor_id[0x18];
3787
3788         u8         reserved_at_e0[0x10];
3789         u8         vsd_vendor_id[0x10];
3790
3791         u8         vsd[208][0x8];
3792
3793         u8         vsd_contd_psid[16][0x8];
3794 };
3795
3796 enum {
3797         MLX5_XRQC_STATE_GOOD   = 0x0,
3798         MLX5_XRQC_STATE_ERROR  = 0x1,
3799 };
3800
3801 enum {
3802         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3803         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3804 };
3805
3806 enum {
3807         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3808 };
3809
3810 struct mlx5_ifc_tag_matching_topology_context_bits {
3811         u8         log_matching_list_sz[0x4];
3812         u8         reserved_at_4[0xc];
3813         u8         append_next_index[0x10];
3814
3815         u8         sw_phase_cnt[0x10];
3816         u8         hw_phase_cnt[0x10];
3817
3818         u8         reserved_at_40[0x40];
3819 };
3820
3821 struct mlx5_ifc_xrqc_bits {
3822         u8         state[0x4];
3823         u8         rlkey[0x1];
3824         u8         reserved_at_5[0xf];
3825         u8         topology[0x4];
3826         u8         reserved_at_18[0x4];
3827         u8         offload[0x4];
3828
3829         u8         reserved_at_20[0x8];
3830         u8         user_index[0x18];
3831
3832         u8         reserved_at_40[0x8];
3833         u8         cqn[0x18];
3834
3835         u8         reserved_at_60[0xa0];
3836
3837         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3838
3839         u8         reserved_at_180[0x280];
3840
3841         struct mlx5_ifc_wq_bits wq;
3842 };
3843
3844 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3845         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3846         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3847         u8         reserved_at_0[0x20];
3848 };
3849
3850 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3851         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3852         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3853         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3854         u8         reserved_at_0[0x20];
3855 };
3856
3857 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3858         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3859         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3860         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3861         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3862         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3863         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3864         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3865         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3866         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3867         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3868         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3869         u8         reserved_at_0[0x7c0];
3870 };
3871
3872 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3873         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3874         u8         reserved_at_0[0x7c0];
3875 };
3876
3877 union mlx5_ifc_event_auto_bits {
3878         struct mlx5_ifc_comp_event_bits comp_event;
3879         struct mlx5_ifc_dct_events_bits dct_events;
3880         struct mlx5_ifc_qp_events_bits qp_events;
3881         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3882         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3883         struct mlx5_ifc_cq_error_bits cq_error;
3884         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3885         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3886         struct mlx5_ifc_gpio_event_bits gpio_event;
3887         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3888         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3889         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3890         u8         reserved_at_0[0xe0];
3891 };
3892
3893 struct mlx5_ifc_health_buffer_bits {
3894         u8         reserved_at_0[0x100];
3895
3896         u8         assert_existptr[0x20];
3897
3898         u8         assert_callra[0x20];
3899
3900         u8         reserved_at_140[0x40];
3901
3902         u8         fw_version[0x20];
3903
3904         u8         hw_id[0x20];
3905
3906         u8         reserved_at_1c0[0x20];
3907
3908         u8         irisc_index[0x8];
3909         u8         synd[0x8];
3910         u8         ext_synd[0x10];
3911 };
3912
3913 struct mlx5_ifc_register_loopback_control_bits {
3914         u8         no_lb[0x1];
3915         u8         reserved_at_1[0x7];
3916         u8         port[0x8];
3917         u8         reserved_at_10[0x10];
3918
3919         u8         reserved_at_20[0x60];
3920 };
3921
3922 struct mlx5_ifc_vport_tc_element_bits {
3923         u8         traffic_class[0x4];
3924         u8         reserved_at_4[0xc];
3925         u8         vport_number[0x10];
3926 };
3927
3928 struct mlx5_ifc_vport_element_bits {
3929         u8         reserved_at_0[0x10];
3930         u8         vport_number[0x10];
3931 };
3932
3933 enum {
3934         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3935         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3936         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3937 };
3938
3939 struct mlx5_ifc_tsar_element_bits {
3940         u8         reserved_at_0[0x8];
3941         u8         tsar_type[0x8];
3942         u8         reserved_at_10[0x10];
3943 };
3944
3945 enum {
3946         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3947         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3948 };
3949
3950 struct mlx5_ifc_teardown_hca_out_bits {
3951         u8         status[0x8];
3952         u8         reserved_at_8[0x18];
3953
3954         u8         syndrome[0x20];
3955
3956         u8         reserved_at_40[0x3f];
3957
3958         u8         state[0x1];
3959 };
3960
3961 enum {
3962         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3963         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3964         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3965 };
3966
3967 struct mlx5_ifc_teardown_hca_in_bits {
3968         u8         opcode[0x10];
3969         u8         reserved_at_10[0x10];
3970
3971         u8         reserved_at_20[0x10];
3972         u8         op_mod[0x10];
3973
3974         u8         reserved_at_40[0x10];
3975         u8         profile[0x10];
3976
3977         u8         reserved_at_60[0x20];
3978 };
3979
3980 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3981         u8         status[0x8];
3982         u8         reserved_at_8[0x18];
3983
3984         u8         syndrome[0x20];
3985
3986         u8         reserved_at_40[0x40];
3987 };
3988
3989 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3990         u8         opcode[0x10];
3991         u8         uid[0x10];
3992
3993         u8         reserved_at_20[0x10];
3994         u8         op_mod[0x10];
3995
3996         u8         reserved_at_40[0x8];
3997         u8         qpn[0x18];
3998
3999         u8         reserved_at_60[0x20];
4000
4001         u8         opt_param_mask[0x20];
4002
4003         u8         reserved_at_a0[0x20];
4004
4005         struct mlx5_ifc_qpc_bits qpc;
4006
4007         u8         reserved_at_800[0x80];
4008 };
4009
4010 struct mlx5_ifc_sqd2rts_qp_out_bits {
4011         u8         status[0x8];
4012         u8         reserved_at_8[0x18];
4013
4014         u8         syndrome[0x20];
4015
4016         u8         reserved_at_40[0x40];
4017 };
4018
4019 struct mlx5_ifc_sqd2rts_qp_in_bits {
4020         u8         opcode[0x10];
4021         u8         uid[0x10];
4022
4023         u8         reserved_at_20[0x10];
4024         u8         op_mod[0x10];
4025
4026         u8         reserved_at_40[0x8];
4027         u8         qpn[0x18];
4028
4029         u8         reserved_at_60[0x20];
4030
4031         u8         opt_param_mask[0x20];
4032
4033         u8         reserved_at_a0[0x20];
4034
4035         struct mlx5_ifc_qpc_bits qpc;
4036
4037         u8         reserved_at_800[0x80];
4038 };
4039
4040 struct mlx5_ifc_set_roce_address_out_bits {
4041         u8         status[0x8];
4042         u8         reserved_at_8[0x18];
4043
4044         u8         syndrome[0x20];
4045
4046         u8         reserved_at_40[0x40];
4047 };
4048
4049 struct mlx5_ifc_set_roce_address_in_bits {
4050         u8         opcode[0x10];
4051         u8         reserved_at_10[0x10];
4052
4053         u8         reserved_at_20[0x10];
4054         u8         op_mod[0x10];
4055
4056         u8         roce_address_index[0x10];
4057         u8         reserved_at_50[0xc];
4058         u8         vhca_port_num[0x4];
4059
4060         u8         reserved_at_60[0x20];
4061
4062         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4063 };
4064
4065 struct mlx5_ifc_set_mad_demux_out_bits {
4066         u8         status[0x8];
4067         u8         reserved_at_8[0x18];
4068
4069         u8         syndrome[0x20];
4070
4071         u8         reserved_at_40[0x40];
4072 };
4073
4074 enum {
4075         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4076         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4077 };
4078
4079 struct mlx5_ifc_set_mad_demux_in_bits {
4080         u8         opcode[0x10];
4081         u8         reserved_at_10[0x10];
4082
4083         u8         reserved_at_20[0x10];
4084         u8         op_mod[0x10];
4085
4086         u8         reserved_at_40[0x20];
4087
4088         u8         reserved_at_60[0x6];
4089         u8         demux_mode[0x2];
4090         u8         reserved_at_68[0x18];
4091 };
4092
4093 struct mlx5_ifc_set_l2_table_entry_out_bits {
4094         u8         status[0x8];
4095         u8         reserved_at_8[0x18];
4096
4097         u8         syndrome[0x20];
4098
4099         u8         reserved_at_40[0x40];
4100 };
4101
4102 struct mlx5_ifc_set_l2_table_entry_in_bits {
4103         u8         opcode[0x10];
4104         u8         reserved_at_10[0x10];
4105
4106         u8         reserved_at_20[0x10];
4107         u8         op_mod[0x10];
4108
4109         u8         reserved_at_40[0x60];
4110
4111         u8         reserved_at_a0[0x8];
4112         u8         table_index[0x18];
4113
4114         u8         reserved_at_c0[0x20];
4115
4116         u8         reserved_at_e0[0x13];
4117         u8         vlan_valid[0x1];
4118         u8         vlan[0xc];
4119
4120         struct mlx5_ifc_mac_address_layout_bits mac_address;
4121
4122         u8         reserved_at_140[0xc0];
4123 };
4124
4125 struct mlx5_ifc_set_issi_out_bits {
4126         u8         status[0x8];
4127         u8         reserved_at_8[0x18];
4128
4129         u8         syndrome[0x20];
4130
4131         u8         reserved_at_40[0x40];
4132 };
4133
4134 struct mlx5_ifc_set_issi_in_bits {
4135         u8         opcode[0x10];
4136         u8         reserved_at_10[0x10];
4137
4138         u8         reserved_at_20[0x10];
4139         u8         op_mod[0x10];
4140
4141         u8         reserved_at_40[0x10];
4142         u8         current_issi[0x10];
4143
4144         u8         reserved_at_60[0x20];
4145 };
4146
4147 struct mlx5_ifc_set_hca_cap_out_bits {
4148         u8         status[0x8];
4149         u8         reserved_at_8[0x18];
4150
4151         u8         syndrome[0x20];
4152
4153         u8         reserved_at_40[0x40];
4154 };
4155
4156 struct mlx5_ifc_set_hca_cap_in_bits {
4157         u8         opcode[0x10];
4158         u8         reserved_at_10[0x10];
4159
4160         u8         reserved_at_20[0x10];
4161         u8         op_mod[0x10];
4162
4163         u8         reserved_at_40[0x40];
4164
4165         union mlx5_ifc_hca_cap_union_bits capability;
4166 };
4167
4168 enum {
4169         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4170         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4171         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4172         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4173         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4174 };
4175
4176 struct mlx5_ifc_set_fte_out_bits {
4177         u8         status[0x8];
4178         u8         reserved_at_8[0x18];
4179
4180         u8         syndrome[0x20];
4181
4182         u8         reserved_at_40[0x40];
4183 };
4184
4185 struct mlx5_ifc_set_fte_in_bits {
4186         u8         opcode[0x10];
4187         u8         reserved_at_10[0x10];
4188
4189         u8         reserved_at_20[0x10];
4190         u8         op_mod[0x10];
4191
4192         u8         other_vport[0x1];
4193         u8         reserved_at_41[0xf];
4194         u8         vport_number[0x10];
4195
4196         u8         reserved_at_60[0x20];
4197
4198         u8         table_type[0x8];
4199         u8         reserved_at_88[0x18];
4200
4201         u8         reserved_at_a0[0x8];
4202         u8         table_id[0x18];
4203
4204         u8         ignore_flow_level[0x1];
4205         u8         reserved_at_c1[0x17];
4206         u8         modify_enable_mask[0x8];
4207
4208         u8         reserved_at_e0[0x20];
4209
4210         u8         flow_index[0x20];
4211
4212         u8         reserved_at_120[0xe0];
4213
4214         struct mlx5_ifc_flow_context_bits flow_context;
4215 };
4216
4217 struct mlx5_ifc_rts2rts_qp_out_bits {
4218         u8         status[0x8];
4219         u8         reserved_at_8[0x18];
4220
4221         u8         syndrome[0x20];
4222
4223         u8         reserved_at_40[0x20];
4224         u8         ece[0x20];
4225 };
4226
4227 struct mlx5_ifc_rts2rts_qp_in_bits {
4228         u8         opcode[0x10];
4229         u8         uid[0x10];
4230
4231         u8         reserved_at_20[0x10];
4232         u8         op_mod[0x10];
4233
4234         u8         reserved_at_40[0x8];
4235         u8         qpn[0x18];
4236
4237         u8         reserved_at_60[0x20];
4238
4239         u8         opt_param_mask[0x20];
4240
4241         u8         ece[0x20];
4242
4243         struct mlx5_ifc_qpc_bits qpc;
4244
4245         u8         reserved_at_800[0x80];
4246 };
4247
4248 struct mlx5_ifc_rtr2rts_qp_out_bits {
4249         u8         status[0x8];
4250         u8         reserved_at_8[0x18];
4251
4252         u8         syndrome[0x20];
4253
4254         u8         reserved_at_40[0x20];
4255         u8         ece[0x20];
4256 };
4257
4258 struct mlx5_ifc_rtr2rts_qp_in_bits {
4259         u8         opcode[0x10];
4260         u8         uid[0x10];
4261
4262         u8         reserved_at_20[0x10];
4263         u8         op_mod[0x10];
4264
4265         u8         reserved_at_40[0x8];
4266         u8         qpn[0x18];
4267
4268         u8         reserved_at_60[0x20];
4269
4270         u8         opt_param_mask[0x20];
4271
4272         u8         ece[0x20];
4273
4274         struct mlx5_ifc_qpc_bits qpc;
4275
4276         u8         reserved_at_800[0x80];
4277 };
4278
4279 struct mlx5_ifc_rst2init_qp_out_bits {
4280         u8         status[0x8];
4281         u8         reserved_at_8[0x18];
4282
4283         u8         syndrome[0x20];
4284
4285         u8         reserved_at_40[0x40];
4286 };
4287
4288 struct mlx5_ifc_rst2init_qp_in_bits {
4289         u8         opcode[0x10];
4290         u8         uid[0x10];
4291
4292         u8         reserved_at_20[0x10];
4293         u8         op_mod[0x10];
4294
4295         u8         reserved_at_40[0x8];
4296         u8         qpn[0x18];
4297
4298         u8         reserved_at_60[0x20];
4299
4300         u8         opt_param_mask[0x20];
4301
4302         u8         reserved_at_a0[0x20];
4303
4304         struct mlx5_ifc_qpc_bits qpc;
4305
4306         u8         reserved_at_800[0x80];
4307 };
4308
4309 struct mlx5_ifc_query_xrq_out_bits {
4310         u8         status[0x8];
4311         u8         reserved_at_8[0x18];
4312
4313         u8         syndrome[0x20];
4314
4315         u8         reserved_at_40[0x40];
4316
4317         struct mlx5_ifc_xrqc_bits xrq_context;
4318 };
4319
4320 struct mlx5_ifc_query_xrq_in_bits {
4321         u8         opcode[0x10];
4322         u8         reserved_at_10[0x10];
4323
4324         u8         reserved_at_20[0x10];
4325         u8         op_mod[0x10];
4326
4327         u8         reserved_at_40[0x8];
4328         u8         xrqn[0x18];
4329
4330         u8         reserved_at_60[0x20];
4331 };
4332
4333 struct mlx5_ifc_query_xrc_srq_out_bits {
4334         u8         status[0x8];
4335         u8         reserved_at_8[0x18];
4336
4337         u8         syndrome[0x20];
4338
4339         u8         reserved_at_40[0x40];
4340
4341         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4342
4343         u8         reserved_at_280[0x600];
4344
4345         u8         pas[][0x40];
4346 };
4347
4348 struct mlx5_ifc_query_xrc_srq_in_bits {
4349         u8         opcode[0x10];
4350         u8         reserved_at_10[0x10];
4351
4352         u8         reserved_at_20[0x10];
4353         u8         op_mod[0x10];
4354
4355         u8         reserved_at_40[0x8];
4356         u8         xrc_srqn[0x18];
4357
4358         u8         reserved_at_60[0x20];
4359 };
4360
4361 enum {
4362         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4363         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4364 };
4365
4366 struct mlx5_ifc_query_vport_state_out_bits {
4367         u8         status[0x8];
4368         u8         reserved_at_8[0x18];
4369
4370         u8         syndrome[0x20];
4371
4372         u8         reserved_at_40[0x20];
4373
4374         u8         reserved_at_60[0x18];
4375         u8         admin_state[0x4];
4376         u8         state[0x4];
4377 };
4378
4379 enum {
4380         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4381         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4382 };
4383
4384 struct mlx5_ifc_arm_monitor_counter_in_bits {
4385         u8         opcode[0x10];
4386         u8         uid[0x10];
4387
4388         u8         reserved_at_20[0x10];
4389         u8         op_mod[0x10];
4390
4391         u8         reserved_at_40[0x20];
4392
4393         u8         reserved_at_60[0x20];
4394 };
4395
4396 struct mlx5_ifc_arm_monitor_counter_out_bits {
4397         u8         status[0x8];
4398         u8         reserved_at_8[0x18];
4399
4400         u8         syndrome[0x20];
4401
4402         u8         reserved_at_40[0x40];
4403 };
4404
4405 enum {
4406         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4407         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4408 };
4409
4410 enum mlx5_monitor_counter_ppcnt {
4411         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4412         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4413         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4414         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4415         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4416         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4417 };
4418
4419 enum {
4420         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4421 };
4422
4423 struct mlx5_ifc_monitor_counter_output_bits {
4424         u8         reserved_at_0[0x4];
4425         u8         type[0x4];
4426         u8         reserved_at_8[0x8];
4427         u8         counter[0x10];
4428
4429         u8         counter_group_id[0x20];
4430 };
4431
4432 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4433 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4434 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4435                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4436
4437 struct mlx5_ifc_set_monitor_counter_in_bits {
4438         u8         opcode[0x10];
4439         u8         uid[0x10];
4440
4441         u8         reserved_at_20[0x10];
4442         u8         op_mod[0x10];
4443
4444         u8         reserved_at_40[0x10];
4445         u8         num_of_counters[0x10];
4446
4447         u8         reserved_at_60[0x20];
4448
4449         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4450 };
4451
4452 struct mlx5_ifc_set_monitor_counter_out_bits {
4453         u8         status[0x8];
4454         u8         reserved_at_8[0x18];
4455
4456         u8         syndrome[0x20];
4457
4458         u8         reserved_at_40[0x40];
4459 };
4460
4461 struct mlx5_ifc_query_vport_state_in_bits {
4462         u8         opcode[0x10];
4463         u8         reserved_at_10[0x10];
4464
4465         u8         reserved_at_20[0x10];
4466         u8         op_mod[0x10];
4467
4468         u8         other_vport[0x1];
4469         u8         reserved_at_41[0xf];
4470         u8         vport_number[0x10];
4471
4472         u8         reserved_at_60[0x20];
4473 };
4474
4475 struct mlx5_ifc_query_vnic_env_out_bits {
4476         u8         status[0x8];
4477         u8         reserved_at_8[0x18];
4478
4479         u8         syndrome[0x20];
4480
4481         u8         reserved_at_40[0x40];
4482
4483         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4484 };
4485
4486 enum {
4487         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4488 };
4489
4490 struct mlx5_ifc_query_vnic_env_in_bits {
4491         u8         opcode[0x10];
4492         u8         reserved_at_10[0x10];
4493
4494         u8         reserved_at_20[0x10];
4495         u8         op_mod[0x10];
4496
4497         u8         other_vport[0x1];
4498         u8         reserved_at_41[0xf];
4499         u8         vport_number[0x10];
4500
4501         u8         reserved_at_60[0x20];
4502 };
4503
4504 struct mlx5_ifc_query_vport_counter_out_bits {
4505         u8         status[0x8];
4506         u8         reserved_at_8[0x18];
4507
4508         u8         syndrome[0x20];
4509
4510         u8         reserved_at_40[0x40];
4511
4512         struct mlx5_ifc_traffic_counter_bits received_errors;
4513
4514         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4515
4516         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4517
4518         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4519
4520         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4521
4522         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4523
4524         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4525
4526         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4527
4528         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4529
4530         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4531
4532         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4533
4534         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4535
4536         u8         reserved_at_680[0xa00];
4537 };
4538
4539 enum {
4540         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4541 };
4542
4543 struct mlx5_ifc_query_vport_counter_in_bits {
4544         u8         opcode[0x10];
4545         u8         reserved_at_10[0x10];
4546
4547         u8         reserved_at_20[0x10];
4548         u8         op_mod[0x10];
4549
4550         u8         other_vport[0x1];
4551         u8         reserved_at_41[0xb];
4552         u8         port_num[0x4];
4553         u8         vport_number[0x10];
4554
4555         u8         reserved_at_60[0x60];
4556
4557         u8         clear[0x1];
4558         u8         reserved_at_c1[0x1f];
4559
4560         u8         reserved_at_e0[0x20];
4561 };
4562
4563 struct mlx5_ifc_query_tis_out_bits {
4564         u8         status[0x8];
4565         u8         reserved_at_8[0x18];
4566
4567         u8         syndrome[0x20];
4568
4569         u8         reserved_at_40[0x40];
4570
4571         struct mlx5_ifc_tisc_bits tis_context;
4572 };
4573
4574 struct mlx5_ifc_query_tis_in_bits {
4575         u8         opcode[0x10];
4576         u8         reserved_at_10[0x10];
4577
4578         u8         reserved_at_20[0x10];
4579         u8         op_mod[0x10];
4580
4581         u8         reserved_at_40[0x8];
4582         u8         tisn[0x18];
4583
4584         u8         reserved_at_60[0x20];
4585 };
4586
4587 struct mlx5_ifc_query_tir_out_bits {
4588         u8         status[0x8];
4589         u8         reserved_at_8[0x18];
4590
4591         u8         syndrome[0x20];
4592
4593         u8         reserved_at_40[0xc0];
4594
4595         struct mlx5_ifc_tirc_bits tir_context;
4596 };
4597
4598 struct mlx5_ifc_query_tir_in_bits {
4599         u8         opcode[0x10];
4600         u8         reserved_at_10[0x10];
4601
4602         u8         reserved_at_20[0x10];
4603         u8         op_mod[0x10];
4604
4605         u8         reserved_at_40[0x8];
4606         u8         tirn[0x18];
4607
4608         u8         reserved_at_60[0x20];
4609 };
4610
4611 struct mlx5_ifc_query_srq_out_bits {
4612         u8         status[0x8];
4613         u8         reserved_at_8[0x18];
4614
4615         u8         syndrome[0x20];
4616
4617         u8         reserved_at_40[0x40];
4618
4619         struct mlx5_ifc_srqc_bits srq_context_entry;
4620
4621         u8         reserved_at_280[0x600];
4622
4623         u8         pas[][0x40];
4624 };
4625
4626 struct mlx5_ifc_query_srq_in_bits {
4627         u8         opcode[0x10];
4628         u8         reserved_at_10[0x10];
4629
4630         u8         reserved_at_20[0x10];
4631         u8         op_mod[0x10];
4632
4633         u8         reserved_at_40[0x8];
4634         u8         srqn[0x18];
4635
4636         u8         reserved_at_60[0x20];
4637 };
4638
4639 struct mlx5_ifc_query_sq_out_bits {
4640         u8         status[0x8];
4641         u8         reserved_at_8[0x18];
4642
4643         u8         syndrome[0x20];
4644
4645         u8         reserved_at_40[0xc0];
4646
4647         struct mlx5_ifc_sqc_bits sq_context;
4648 };
4649
4650 struct mlx5_ifc_query_sq_in_bits {
4651         u8         opcode[0x10];
4652         u8         reserved_at_10[0x10];
4653
4654         u8         reserved_at_20[0x10];
4655         u8         op_mod[0x10];
4656
4657         u8         reserved_at_40[0x8];
4658         u8         sqn[0x18];
4659
4660         u8         reserved_at_60[0x20];
4661 };
4662
4663 struct mlx5_ifc_query_special_contexts_out_bits {
4664         u8         status[0x8];
4665         u8         reserved_at_8[0x18];
4666
4667         u8         syndrome[0x20];
4668
4669         u8         dump_fill_mkey[0x20];
4670
4671         u8         resd_lkey[0x20];
4672
4673         u8         null_mkey[0x20];
4674
4675         u8         reserved_at_a0[0x60];
4676 };
4677
4678 struct mlx5_ifc_query_special_contexts_in_bits {
4679         u8         opcode[0x10];
4680         u8         reserved_at_10[0x10];
4681
4682         u8         reserved_at_20[0x10];
4683         u8         op_mod[0x10];
4684
4685         u8         reserved_at_40[0x40];
4686 };
4687
4688 struct mlx5_ifc_query_scheduling_element_out_bits {
4689         u8         opcode[0x10];
4690         u8         reserved_at_10[0x10];
4691
4692         u8         reserved_at_20[0x10];
4693         u8         op_mod[0x10];
4694
4695         u8         reserved_at_40[0xc0];
4696
4697         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4698
4699         u8         reserved_at_300[0x100];
4700 };
4701
4702 enum {
4703         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4704 };
4705
4706 struct mlx5_ifc_query_scheduling_element_in_bits {
4707         u8         opcode[0x10];
4708         u8         reserved_at_10[0x10];
4709
4710         u8         reserved_at_20[0x10];
4711         u8         op_mod[0x10];
4712
4713         u8         scheduling_hierarchy[0x8];
4714         u8         reserved_at_48[0x18];
4715
4716         u8         scheduling_element_id[0x20];
4717
4718         u8         reserved_at_80[0x180];
4719 };
4720
4721 struct mlx5_ifc_query_rqt_out_bits {
4722         u8         status[0x8];
4723         u8         reserved_at_8[0x18];
4724
4725         u8         syndrome[0x20];
4726
4727         u8         reserved_at_40[0xc0];
4728
4729         struct mlx5_ifc_rqtc_bits rqt_context;
4730 };
4731
4732 struct mlx5_ifc_query_rqt_in_bits {
4733         u8         opcode[0x10];
4734         u8         reserved_at_10[0x10];
4735
4736         u8         reserved_at_20[0x10];
4737         u8         op_mod[0x10];
4738
4739         u8         reserved_at_40[0x8];
4740         u8         rqtn[0x18];
4741
4742         u8         reserved_at_60[0x20];
4743 };
4744
4745 struct mlx5_ifc_query_rq_out_bits {
4746         u8         status[0x8];
4747         u8         reserved_at_8[0x18];
4748
4749         u8         syndrome[0x20];
4750
4751         u8         reserved_at_40[0xc0];
4752
4753         struct mlx5_ifc_rqc_bits rq_context;
4754 };
4755
4756 struct mlx5_ifc_query_rq_in_bits {
4757         u8         opcode[0x10];
4758         u8         reserved_at_10[0x10];
4759
4760         u8         reserved_at_20[0x10];
4761         u8         op_mod[0x10];
4762
4763         u8         reserved_at_40[0x8];
4764         u8         rqn[0x18];
4765
4766         u8         reserved_at_60[0x20];
4767 };
4768
4769 struct mlx5_ifc_query_roce_address_out_bits {
4770         u8         status[0x8];
4771         u8         reserved_at_8[0x18];
4772
4773         u8         syndrome[0x20];
4774
4775         u8         reserved_at_40[0x40];
4776
4777         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4778 };
4779
4780 struct mlx5_ifc_query_roce_address_in_bits {
4781         u8         opcode[0x10];
4782         u8         reserved_at_10[0x10];
4783
4784         u8         reserved_at_20[0x10];
4785         u8         op_mod[0x10];
4786
4787         u8         roce_address_index[0x10];
4788         u8         reserved_at_50[0xc];
4789         u8         vhca_port_num[0x4];
4790
4791         u8         reserved_at_60[0x20];
4792 };
4793
4794 struct mlx5_ifc_query_rmp_out_bits {
4795         u8         status[0x8];
4796         u8         reserved_at_8[0x18];
4797
4798         u8         syndrome[0x20];
4799
4800         u8         reserved_at_40[0xc0];
4801
4802         struct mlx5_ifc_rmpc_bits rmp_context;
4803 };
4804
4805 struct mlx5_ifc_query_rmp_in_bits {
4806         u8         opcode[0x10];
4807         u8         reserved_at_10[0x10];
4808
4809         u8         reserved_at_20[0x10];
4810         u8         op_mod[0x10];
4811
4812         u8         reserved_at_40[0x8];
4813         u8         rmpn[0x18];
4814
4815         u8         reserved_at_60[0x20];
4816 };
4817
4818 struct mlx5_ifc_query_qp_out_bits {
4819         u8         status[0x8];
4820         u8         reserved_at_8[0x18];
4821
4822         u8         syndrome[0x20];
4823
4824         u8         reserved_at_40[0x20];
4825         u8         ece[0x20];
4826
4827         u8         opt_param_mask[0x20];
4828
4829         u8         reserved_at_a0[0x20];
4830
4831         struct mlx5_ifc_qpc_bits qpc;
4832
4833         u8         reserved_at_800[0x80];
4834
4835         u8         pas[][0x40];
4836 };
4837
4838 struct mlx5_ifc_query_qp_in_bits {
4839         u8         opcode[0x10];
4840         u8         reserved_at_10[0x10];
4841
4842         u8         reserved_at_20[0x10];
4843         u8         op_mod[0x10];
4844
4845         u8         reserved_at_40[0x8];
4846         u8         qpn[0x18];
4847
4848         u8         reserved_at_60[0x20];
4849 };
4850
4851 struct mlx5_ifc_query_q_counter_out_bits {
4852         u8         status[0x8];
4853         u8         reserved_at_8[0x18];
4854
4855         u8         syndrome[0x20];
4856
4857         u8         reserved_at_40[0x40];
4858
4859         u8         rx_write_requests[0x20];
4860
4861         u8         reserved_at_a0[0x20];
4862
4863         u8         rx_read_requests[0x20];
4864
4865         u8         reserved_at_e0[0x20];
4866
4867         u8         rx_atomic_requests[0x20];
4868
4869         u8         reserved_at_120[0x20];
4870
4871         u8         rx_dct_connect[0x20];
4872
4873         u8         reserved_at_160[0x20];
4874
4875         u8         out_of_buffer[0x20];
4876
4877         u8         reserved_at_1a0[0x20];
4878
4879         u8         out_of_sequence[0x20];
4880
4881         u8         reserved_at_1e0[0x20];
4882
4883         u8         duplicate_request[0x20];
4884
4885         u8         reserved_at_220[0x20];
4886
4887         u8         rnr_nak_retry_err[0x20];
4888
4889         u8         reserved_at_260[0x20];
4890
4891         u8         packet_seq_err[0x20];
4892
4893         u8         reserved_at_2a0[0x20];
4894
4895         u8         implied_nak_seq_err[0x20];
4896
4897         u8         reserved_at_2e0[0x20];
4898
4899         u8         local_ack_timeout_err[0x20];
4900
4901         u8         reserved_at_320[0xa0];
4902
4903         u8         resp_local_length_error[0x20];
4904
4905         u8         req_local_length_error[0x20];
4906
4907         u8         resp_local_qp_error[0x20];
4908
4909         u8         local_operation_error[0x20];
4910
4911         u8         resp_local_protection[0x20];
4912
4913         u8         req_local_protection[0x20];
4914
4915         u8         resp_cqe_error[0x20];
4916
4917         u8         req_cqe_error[0x20];
4918
4919         u8         req_mw_binding[0x20];
4920
4921         u8         req_bad_response[0x20];
4922
4923         u8         req_remote_invalid_request[0x20];
4924
4925         u8         resp_remote_invalid_request[0x20];
4926
4927         u8         req_remote_access_errors[0x20];
4928
4929         u8         resp_remote_access_errors[0x20];
4930
4931         u8         req_remote_operation_errors[0x20];
4932
4933         u8         req_transport_retries_exceeded[0x20];
4934
4935         u8         cq_overflow[0x20];
4936
4937         u8         resp_cqe_flush_error[0x20];
4938
4939         u8         req_cqe_flush_error[0x20];
4940
4941         u8         reserved_at_620[0x20];
4942
4943         u8         roce_adp_retrans[0x20];
4944
4945         u8         roce_adp_retrans_to[0x20];
4946
4947         u8         roce_slow_restart[0x20];
4948
4949         u8         roce_slow_restart_cnps[0x20];
4950
4951         u8         roce_slow_restart_trans[0x20];
4952
4953         u8         reserved_at_6e0[0x120];
4954 };
4955
4956 struct mlx5_ifc_query_q_counter_in_bits {
4957         u8         opcode[0x10];
4958         u8         reserved_at_10[0x10];
4959
4960         u8         reserved_at_20[0x10];
4961         u8         op_mod[0x10];
4962
4963         u8         reserved_at_40[0x80];
4964
4965         u8         clear[0x1];
4966         u8         reserved_at_c1[0x1f];
4967
4968         u8         reserved_at_e0[0x18];
4969         u8         counter_set_id[0x8];
4970 };
4971
4972 struct mlx5_ifc_query_pages_out_bits {
4973         u8         status[0x8];
4974         u8         reserved_at_8[0x18];
4975
4976         u8         syndrome[0x20];
4977
4978         u8         embedded_cpu_function[0x1];
4979         u8         reserved_at_41[0xf];
4980         u8         function_id[0x10];
4981
4982         u8         num_pages[0x20];
4983 };
4984
4985 enum {
4986         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4987         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4988         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4989 };
4990
4991 struct mlx5_ifc_query_pages_in_bits {
4992         u8         opcode[0x10];
4993         u8         reserved_at_10[0x10];
4994
4995         u8         reserved_at_20[0x10];
4996         u8         op_mod[0x10];
4997
4998         u8         embedded_cpu_function[0x1];
4999         u8         reserved_at_41[0xf];
5000         u8         function_id[0x10];
5001
5002         u8         reserved_at_60[0x20];
5003 };
5004
5005 struct mlx5_ifc_query_nic_vport_context_out_bits {
5006         u8         status[0x8];
5007         u8         reserved_at_8[0x18];
5008
5009         u8         syndrome[0x20];
5010
5011         u8         reserved_at_40[0x40];
5012
5013         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5014 };
5015
5016 struct mlx5_ifc_query_nic_vport_context_in_bits {
5017         u8         opcode[0x10];
5018         u8         reserved_at_10[0x10];
5019
5020         u8         reserved_at_20[0x10];
5021         u8         op_mod[0x10];
5022
5023         u8         other_vport[0x1];
5024         u8         reserved_at_41[0xf];
5025         u8         vport_number[0x10];
5026
5027         u8         reserved_at_60[0x5];
5028         u8         allowed_list_type[0x3];
5029         u8         reserved_at_68[0x18];
5030 };
5031
5032 struct mlx5_ifc_query_mkey_out_bits {
5033         u8         status[0x8];
5034         u8         reserved_at_8[0x18];
5035
5036         u8         syndrome[0x20];
5037
5038         u8         reserved_at_40[0x40];
5039
5040         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5041
5042         u8         reserved_at_280[0x600];
5043
5044         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5045
5046         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5047 };
5048
5049 struct mlx5_ifc_query_mkey_in_bits {
5050         u8         opcode[0x10];
5051         u8         reserved_at_10[0x10];
5052
5053         u8         reserved_at_20[0x10];
5054         u8         op_mod[0x10];
5055
5056         u8         reserved_at_40[0x8];
5057         u8         mkey_index[0x18];
5058
5059         u8         pg_access[0x1];
5060         u8         reserved_at_61[0x1f];
5061 };
5062
5063 struct mlx5_ifc_query_mad_demux_out_bits {
5064         u8         status[0x8];
5065         u8         reserved_at_8[0x18];
5066
5067         u8         syndrome[0x20];
5068
5069         u8         reserved_at_40[0x40];
5070
5071         u8         mad_dumux_parameters_block[0x20];
5072 };
5073
5074 struct mlx5_ifc_query_mad_demux_in_bits {
5075         u8         opcode[0x10];
5076         u8         reserved_at_10[0x10];
5077
5078         u8         reserved_at_20[0x10];
5079         u8         op_mod[0x10];
5080
5081         u8         reserved_at_40[0x40];
5082 };
5083
5084 struct mlx5_ifc_query_l2_table_entry_out_bits {
5085         u8         status[0x8];
5086         u8         reserved_at_8[0x18];
5087
5088         u8         syndrome[0x20];
5089
5090         u8         reserved_at_40[0xa0];
5091
5092         u8         reserved_at_e0[0x13];
5093         u8         vlan_valid[0x1];
5094         u8         vlan[0xc];
5095
5096         struct mlx5_ifc_mac_address_layout_bits mac_address;
5097
5098         u8         reserved_at_140[0xc0];
5099 };
5100
5101 struct mlx5_ifc_query_l2_table_entry_in_bits {
5102         u8         opcode[0x10];
5103         u8         reserved_at_10[0x10];
5104
5105         u8         reserved_at_20[0x10];
5106         u8         op_mod[0x10];
5107
5108         u8         reserved_at_40[0x60];
5109
5110         u8         reserved_at_a0[0x8];
5111         u8         table_index[0x18];
5112
5113         u8         reserved_at_c0[0x140];
5114 };
5115
5116 struct mlx5_ifc_query_issi_out_bits {
5117         u8         status[0x8];
5118         u8         reserved_at_8[0x18];
5119
5120         u8         syndrome[0x20];
5121
5122         u8         reserved_at_40[0x10];
5123         u8         current_issi[0x10];
5124
5125         u8         reserved_at_60[0xa0];
5126
5127         u8         reserved_at_100[76][0x8];
5128         u8         supported_issi_dw0[0x20];
5129 };
5130
5131 struct mlx5_ifc_query_issi_in_bits {
5132         u8         opcode[0x10];
5133         u8         reserved_at_10[0x10];
5134
5135         u8         reserved_at_20[0x10];
5136         u8         op_mod[0x10];
5137
5138         u8         reserved_at_40[0x40];
5139 };
5140
5141 struct mlx5_ifc_set_driver_version_out_bits {
5142         u8         status[0x8];
5143         u8         reserved_0[0x18];
5144
5145         u8         syndrome[0x20];
5146         u8         reserved_1[0x40];
5147 };
5148
5149 struct mlx5_ifc_set_driver_version_in_bits {
5150         u8         opcode[0x10];
5151         u8         reserved_0[0x10];
5152
5153         u8         reserved_1[0x10];
5154         u8         op_mod[0x10];
5155
5156         u8         reserved_2[0x40];
5157         u8         driver_version[64][0x8];
5158 };
5159
5160 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5161         u8         status[0x8];
5162         u8         reserved_at_8[0x18];
5163
5164         u8         syndrome[0x20];
5165
5166         u8         reserved_at_40[0x40];
5167
5168         struct mlx5_ifc_pkey_bits pkey[];
5169 };
5170
5171 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5172         u8         opcode[0x10];
5173         u8         reserved_at_10[0x10];
5174
5175         u8         reserved_at_20[0x10];
5176         u8         op_mod[0x10];
5177
5178         u8         other_vport[0x1];
5179         u8         reserved_at_41[0xb];
5180         u8         port_num[0x4];
5181         u8         vport_number[0x10];
5182
5183         u8         reserved_at_60[0x10];
5184         u8         pkey_index[0x10];
5185 };
5186
5187 enum {
5188         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5189         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5190         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5191 };
5192
5193 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5194         u8         status[0x8];
5195         u8         reserved_at_8[0x18];
5196
5197         u8         syndrome[0x20];
5198
5199         u8         reserved_at_40[0x20];
5200
5201         u8         gids_num[0x10];
5202         u8         reserved_at_70[0x10];
5203
5204         struct mlx5_ifc_array128_auto_bits gid[];
5205 };
5206
5207 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5208         u8         opcode[0x10];
5209         u8         reserved_at_10[0x10];
5210
5211         u8         reserved_at_20[0x10];
5212         u8         op_mod[0x10];
5213
5214         u8         other_vport[0x1];
5215         u8         reserved_at_41[0xb];
5216         u8         port_num[0x4];
5217         u8         vport_number[0x10];
5218
5219         u8         reserved_at_60[0x10];
5220         u8         gid_index[0x10];
5221 };
5222
5223 struct mlx5_ifc_query_hca_vport_context_out_bits {
5224         u8         status[0x8];
5225         u8         reserved_at_8[0x18];
5226
5227         u8         syndrome[0x20];
5228
5229         u8         reserved_at_40[0x40];
5230
5231         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5232 };
5233
5234 struct mlx5_ifc_query_hca_vport_context_in_bits {
5235         u8         opcode[0x10];
5236         u8         reserved_at_10[0x10];
5237
5238         u8         reserved_at_20[0x10];
5239         u8         op_mod[0x10];
5240
5241         u8         other_vport[0x1];
5242         u8         reserved_at_41[0xb];
5243         u8         port_num[0x4];
5244         u8         vport_number[0x10];
5245
5246         u8         reserved_at_60[0x20];
5247 };
5248
5249 struct mlx5_ifc_query_hca_cap_out_bits {
5250         u8         status[0x8];
5251         u8         reserved_at_8[0x18];
5252
5253         u8         syndrome[0x20];
5254
5255         u8         reserved_at_40[0x40];
5256
5257         union mlx5_ifc_hca_cap_union_bits capability;
5258 };
5259
5260 struct mlx5_ifc_query_hca_cap_in_bits {
5261         u8         opcode[0x10];
5262         u8         reserved_at_10[0x10];
5263
5264         u8         reserved_at_20[0x10];
5265         u8         op_mod[0x10];
5266
5267         u8         other_function[0x1];
5268         u8         reserved_at_41[0xf];
5269         u8         function_id[0x10];
5270
5271         u8         reserved_at_60[0x20];
5272 };
5273
5274 struct mlx5_ifc_other_hca_cap_bits {
5275         u8         roce[0x1];
5276         u8         reserved_at_1[0x27f];
5277 };
5278
5279 struct mlx5_ifc_query_other_hca_cap_out_bits {
5280         u8         status[0x8];
5281         u8         reserved_at_8[0x18];
5282
5283         u8         syndrome[0x20];
5284
5285         u8         reserved_at_40[0x40];
5286
5287         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5288 };
5289
5290 struct mlx5_ifc_query_other_hca_cap_in_bits {
5291         u8         opcode[0x10];
5292         u8         reserved_at_10[0x10];
5293
5294         u8         reserved_at_20[0x10];
5295         u8         op_mod[0x10];
5296
5297         u8         reserved_at_40[0x10];
5298         u8         function_id[0x10];
5299
5300         u8         reserved_at_60[0x20];
5301 };
5302
5303 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5304         u8         status[0x8];
5305         u8         reserved_at_8[0x18];
5306
5307         u8         syndrome[0x20];
5308
5309         u8         reserved_at_40[0x40];
5310 };
5311
5312 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5313         u8         opcode[0x10];
5314         u8         reserved_at_10[0x10];
5315
5316         u8         reserved_at_20[0x10];
5317         u8         op_mod[0x10];
5318
5319         u8         reserved_at_40[0x10];
5320         u8         function_id[0x10];
5321         u8         field_select[0x20];
5322
5323         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5324 };
5325
5326 struct mlx5_ifc_flow_table_context_bits {
5327         u8         reformat_en[0x1];
5328         u8         decap_en[0x1];
5329         u8         sw_owner[0x1];
5330         u8         termination_table[0x1];
5331         u8         table_miss_action[0x4];
5332         u8         level[0x8];
5333         u8         reserved_at_10[0x8];
5334         u8         log_size[0x8];
5335
5336         u8         reserved_at_20[0x8];
5337         u8         table_miss_id[0x18];
5338
5339         u8         reserved_at_40[0x8];
5340         u8         lag_master_next_table_id[0x18];
5341
5342         u8         reserved_at_60[0x60];
5343
5344         u8         sw_owner_icm_root_1[0x40];
5345
5346         u8         sw_owner_icm_root_0[0x40];
5347
5348 };
5349
5350 struct mlx5_ifc_query_flow_table_out_bits {
5351         u8         status[0x8];
5352         u8         reserved_at_8[0x18];
5353
5354         u8         syndrome[0x20];
5355
5356         u8         reserved_at_40[0x80];
5357
5358         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5359 };
5360
5361 struct mlx5_ifc_query_flow_table_in_bits {
5362         u8         opcode[0x10];
5363         u8         reserved_at_10[0x10];
5364
5365         u8         reserved_at_20[0x10];
5366         u8         op_mod[0x10];
5367
5368         u8         reserved_at_40[0x40];
5369
5370         u8         table_type[0x8];
5371         u8         reserved_at_88[0x18];
5372
5373         u8         reserved_at_a0[0x8];
5374         u8         table_id[0x18];
5375
5376         u8         reserved_at_c0[0x140];
5377 };
5378
5379 struct mlx5_ifc_query_fte_out_bits {
5380         u8         status[0x8];
5381         u8         reserved_at_8[0x18];
5382
5383         u8         syndrome[0x20];
5384
5385         u8         reserved_at_40[0x1c0];
5386
5387         struct mlx5_ifc_flow_context_bits flow_context;
5388 };
5389
5390 struct mlx5_ifc_query_fte_in_bits {
5391         u8         opcode[0x10];
5392         u8         reserved_at_10[0x10];
5393
5394         u8         reserved_at_20[0x10];
5395         u8         op_mod[0x10];
5396
5397         u8         reserved_at_40[0x40];
5398
5399         u8         table_type[0x8];
5400         u8         reserved_at_88[0x18];
5401
5402         u8         reserved_at_a0[0x8];
5403         u8         table_id[0x18];
5404
5405         u8         reserved_at_c0[0x40];
5406
5407         u8         flow_index[0x20];
5408
5409         u8         reserved_at_120[0xe0];
5410 };
5411
5412 enum {
5413         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5414         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5415         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5416         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5417         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5418 };
5419
5420 struct mlx5_ifc_query_flow_group_out_bits {
5421         u8         status[0x8];
5422         u8         reserved_at_8[0x18];
5423
5424         u8         syndrome[0x20];
5425
5426         u8         reserved_at_40[0xa0];
5427
5428         u8         start_flow_index[0x20];
5429
5430         u8         reserved_at_100[0x20];
5431
5432         u8         end_flow_index[0x20];
5433
5434         u8         reserved_at_140[0xa0];
5435
5436         u8         reserved_at_1e0[0x18];
5437         u8         match_criteria_enable[0x8];
5438
5439         struct mlx5_ifc_fte_match_param_bits match_criteria;
5440
5441         u8         reserved_at_1200[0xe00];
5442 };
5443
5444 struct mlx5_ifc_query_flow_group_in_bits {
5445         u8         opcode[0x10];
5446         u8         reserved_at_10[0x10];
5447
5448         u8         reserved_at_20[0x10];
5449         u8         op_mod[0x10];
5450
5451         u8         reserved_at_40[0x40];
5452
5453         u8         table_type[0x8];
5454         u8         reserved_at_88[0x18];
5455
5456         u8         reserved_at_a0[0x8];
5457         u8         table_id[0x18];
5458
5459         u8         group_id[0x20];
5460
5461         u8         reserved_at_e0[0x120];
5462 };
5463
5464 struct mlx5_ifc_query_flow_counter_out_bits {
5465         u8         status[0x8];
5466         u8         reserved_at_8[0x18];
5467
5468         u8         syndrome[0x20];
5469
5470         u8         reserved_at_40[0x40];
5471
5472         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5473 };
5474
5475 struct mlx5_ifc_query_flow_counter_in_bits {
5476         u8         opcode[0x10];
5477         u8         reserved_at_10[0x10];
5478
5479         u8         reserved_at_20[0x10];
5480         u8         op_mod[0x10];
5481
5482         u8         reserved_at_40[0x80];
5483
5484         u8         clear[0x1];
5485         u8         reserved_at_c1[0xf];
5486         u8         num_of_counters[0x10];
5487
5488         u8         flow_counter_id[0x20];
5489 };
5490
5491 struct mlx5_ifc_query_esw_vport_context_out_bits {
5492         u8         status[0x8];
5493         u8         reserved_at_8[0x18];
5494
5495         u8         syndrome[0x20];
5496
5497         u8         reserved_at_40[0x40];
5498
5499         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5500 };
5501
5502 struct mlx5_ifc_query_esw_vport_context_in_bits {
5503         u8         opcode[0x10];
5504         u8         reserved_at_10[0x10];
5505
5506         u8         reserved_at_20[0x10];
5507         u8         op_mod[0x10];
5508
5509         u8         other_vport[0x1];
5510         u8         reserved_at_41[0xf];
5511         u8         vport_number[0x10];
5512
5513         u8         reserved_at_60[0x20];
5514 };
5515
5516 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5517         u8         status[0x8];
5518         u8         reserved_at_8[0x18];
5519
5520         u8         syndrome[0x20];
5521
5522         u8         reserved_at_40[0x40];
5523 };
5524
5525 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5526         u8         reserved_at_0[0x1b];
5527         u8         fdb_to_vport_reg_c_id[0x1];
5528         u8         vport_cvlan_insert[0x1];
5529         u8         vport_svlan_insert[0x1];
5530         u8         vport_cvlan_strip[0x1];
5531         u8         vport_svlan_strip[0x1];
5532 };
5533
5534 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5535         u8         opcode[0x10];
5536         u8         reserved_at_10[0x10];
5537
5538         u8         reserved_at_20[0x10];
5539         u8         op_mod[0x10];
5540
5541         u8         other_vport[0x1];
5542         u8         reserved_at_41[0xf];
5543         u8         vport_number[0x10];
5544
5545         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5546
5547         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5548 };
5549
5550 struct mlx5_ifc_query_eq_out_bits {
5551         u8         status[0x8];
5552         u8         reserved_at_8[0x18];
5553
5554         u8         syndrome[0x20];
5555
5556         u8         reserved_at_40[0x40];
5557
5558         struct mlx5_ifc_eqc_bits eq_context_entry;
5559
5560         u8         reserved_at_280[0x40];
5561
5562         u8         event_bitmask[0x40];
5563
5564         u8         reserved_at_300[0x580];
5565
5566         u8         pas[][0x40];
5567 };
5568
5569 struct mlx5_ifc_query_eq_in_bits {
5570         u8         opcode[0x10];
5571         u8         reserved_at_10[0x10];
5572
5573         u8         reserved_at_20[0x10];
5574         u8         op_mod[0x10];
5575
5576         u8         reserved_at_40[0x18];
5577         u8         eq_number[0x8];
5578
5579         u8         reserved_at_60[0x20];
5580 };
5581
5582 struct mlx5_ifc_packet_reformat_context_in_bits {
5583         u8         reserved_at_0[0x5];
5584         u8         reformat_type[0x3];
5585         u8         reserved_at_8[0xe];
5586         u8         reformat_data_size[0xa];
5587
5588         u8         reserved_at_20[0x10];
5589         u8         reformat_data[2][0x8];
5590
5591         u8         more_reformat_data[][0x8];
5592 };
5593
5594 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5595         u8         status[0x8];
5596         u8         reserved_at_8[0x18];
5597
5598         u8         syndrome[0x20];
5599
5600         u8         reserved_at_40[0xa0];
5601
5602         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5603 };
5604
5605 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5606         u8         opcode[0x10];
5607         u8         reserved_at_10[0x10];
5608
5609         u8         reserved_at_20[0x10];
5610         u8         op_mod[0x10];
5611
5612         u8         packet_reformat_id[0x20];
5613
5614         u8         reserved_at_60[0xa0];
5615 };
5616
5617 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5618         u8         status[0x8];
5619         u8         reserved_at_8[0x18];
5620
5621         u8         syndrome[0x20];
5622
5623         u8         packet_reformat_id[0x20];
5624
5625         u8         reserved_at_60[0x20];
5626 };
5627
5628 enum mlx5_reformat_ctx_type {
5629         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5630         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5631         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5632         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5633         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5634 };
5635
5636 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5637         u8         opcode[0x10];
5638         u8         reserved_at_10[0x10];
5639
5640         u8         reserved_at_20[0x10];
5641         u8         op_mod[0x10];
5642
5643         u8         reserved_at_40[0xa0];
5644
5645         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5646 };
5647
5648 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5649         u8         status[0x8];
5650         u8         reserved_at_8[0x18];
5651
5652         u8         syndrome[0x20];
5653
5654         u8         reserved_at_40[0x40];
5655 };
5656
5657 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5658         u8         opcode[0x10];
5659         u8         reserved_at_10[0x10];
5660
5661         u8         reserved_20[0x10];
5662         u8         op_mod[0x10];
5663
5664         u8         packet_reformat_id[0x20];
5665
5666         u8         reserved_60[0x20];
5667 };
5668
5669 struct mlx5_ifc_set_action_in_bits {
5670         u8         action_type[0x4];
5671         u8         field[0xc];
5672         u8         reserved_at_10[0x3];
5673         u8         offset[0x5];
5674         u8         reserved_at_18[0x3];
5675         u8         length[0x5];
5676
5677         u8         data[0x20];
5678 };
5679
5680 struct mlx5_ifc_add_action_in_bits {
5681         u8         action_type[0x4];
5682         u8         field[0xc];
5683         u8         reserved_at_10[0x10];
5684
5685         u8         data[0x20];
5686 };
5687
5688 struct mlx5_ifc_copy_action_in_bits {
5689         u8         action_type[0x4];
5690         u8         src_field[0xc];
5691         u8         reserved_at_10[0x3];
5692         u8         src_offset[0x5];
5693         u8         reserved_at_18[0x3];
5694         u8         length[0x5];
5695
5696         u8         reserved_at_20[0x4];
5697         u8         dst_field[0xc];
5698         u8         reserved_at_30[0x3];
5699         u8         dst_offset[0x5];
5700         u8         reserved_at_38[0x8];
5701 };
5702
5703 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5704         struct mlx5_ifc_set_action_in_bits  set_action_in;
5705         struct mlx5_ifc_add_action_in_bits  add_action_in;
5706         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5707         u8         reserved_at_0[0x40];
5708 };
5709
5710 enum {
5711         MLX5_ACTION_TYPE_SET   = 0x1,
5712         MLX5_ACTION_TYPE_ADD   = 0x2,
5713         MLX5_ACTION_TYPE_COPY  = 0x3,
5714 };
5715
5716 enum {
5717         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5718         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5719         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5720         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5721         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5722         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5723         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5724         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5725         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5726         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5727         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5728         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5729         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5730         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5731         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5732         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5733         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5734         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5735         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5736         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5737         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5738         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5739         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5740         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5741         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5742         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5743         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5744         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5745         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5746         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5747         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5748         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5749         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5750         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5751         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5752         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5753 };
5754
5755 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5756         u8         status[0x8];
5757         u8         reserved_at_8[0x18];
5758
5759         u8         syndrome[0x20];
5760
5761         u8         modify_header_id[0x20];
5762
5763         u8         reserved_at_60[0x20];
5764 };
5765
5766 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5767         u8         opcode[0x10];
5768         u8         reserved_at_10[0x10];
5769
5770         u8         reserved_at_20[0x10];
5771         u8         op_mod[0x10];
5772
5773         u8         reserved_at_40[0x20];
5774
5775         u8         table_type[0x8];
5776         u8         reserved_at_68[0x10];
5777         u8         num_of_actions[0x8];
5778
5779         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0];
5780 };
5781
5782 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5783         u8         status[0x8];
5784         u8         reserved_at_8[0x18];
5785
5786         u8         syndrome[0x20];
5787
5788         u8         reserved_at_40[0x40];
5789 };
5790
5791 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5792         u8         opcode[0x10];
5793         u8         reserved_at_10[0x10];
5794
5795         u8         reserved_at_20[0x10];
5796         u8         op_mod[0x10];
5797
5798         u8         modify_header_id[0x20];
5799
5800         u8         reserved_at_60[0x20];
5801 };
5802
5803 struct mlx5_ifc_query_dct_out_bits {
5804         u8         status[0x8];
5805         u8         reserved_at_8[0x18];
5806
5807         u8         syndrome[0x20];
5808
5809         u8         reserved_at_40[0x40];
5810
5811         struct mlx5_ifc_dctc_bits dct_context_entry;
5812
5813         u8         reserved_at_280[0x180];
5814 };
5815
5816 struct mlx5_ifc_query_dct_in_bits {
5817         u8         opcode[0x10];
5818         u8         reserved_at_10[0x10];
5819
5820         u8         reserved_at_20[0x10];
5821         u8         op_mod[0x10];
5822
5823         u8         reserved_at_40[0x8];
5824         u8         dctn[0x18];
5825
5826         u8         reserved_at_60[0x20];
5827 };
5828
5829 struct mlx5_ifc_query_cq_out_bits {
5830         u8         status[0x8];
5831         u8         reserved_at_8[0x18];
5832
5833         u8         syndrome[0x20];
5834
5835         u8         reserved_at_40[0x40];
5836
5837         struct mlx5_ifc_cqc_bits cq_context;
5838
5839         u8         reserved_at_280[0x600];
5840
5841         u8         pas[][0x40];
5842 };
5843
5844 struct mlx5_ifc_query_cq_in_bits {
5845         u8         opcode[0x10];
5846         u8         reserved_at_10[0x10];
5847
5848         u8         reserved_at_20[0x10];
5849         u8         op_mod[0x10];
5850
5851         u8         reserved_at_40[0x8];
5852         u8         cqn[0x18];
5853
5854         u8         reserved_at_60[0x20];
5855 };
5856
5857 struct mlx5_ifc_query_cong_status_out_bits {
5858         u8         status[0x8];
5859         u8         reserved_at_8[0x18];
5860
5861         u8         syndrome[0x20];
5862
5863         u8         reserved_at_40[0x20];
5864
5865         u8         enable[0x1];
5866         u8         tag_enable[0x1];
5867         u8         reserved_at_62[0x1e];
5868 };
5869
5870 struct mlx5_ifc_query_cong_status_in_bits {
5871         u8         opcode[0x10];
5872         u8         reserved_at_10[0x10];
5873
5874         u8         reserved_at_20[0x10];
5875         u8         op_mod[0x10];
5876
5877         u8         reserved_at_40[0x18];
5878         u8         priority[0x4];
5879         u8         cong_protocol[0x4];
5880
5881         u8         reserved_at_60[0x20];
5882 };
5883
5884 struct mlx5_ifc_query_cong_statistics_out_bits {
5885         u8         status[0x8];
5886         u8         reserved_at_8[0x18];
5887
5888         u8         syndrome[0x20];
5889
5890         u8         reserved_at_40[0x40];
5891
5892         u8         rp_cur_flows[0x20];
5893
5894         u8         sum_flows[0x20];
5895
5896         u8         rp_cnp_ignored_high[0x20];
5897
5898         u8         rp_cnp_ignored_low[0x20];
5899
5900         u8         rp_cnp_handled_high[0x20];
5901
5902         u8         rp_cnp_handled_low[0x20];
5903
5904         u8         reserved_at_140[0x100];
5905
5906         u8         time_stamp_high[0x20];
5907
5908         u8         time_stamp_low[0x20];
5909
5910         u8         accumulators_period[0x20];
5911
5912         u8         np_ecn_marked_roce_packets_high[0x20];
5913
5914         u8         np_ecn_marked_roce_packets_low[0x20];
5915
5916         u8         np_cnp_sent_high[0x20];
5917
5918         u8         np_cnp_sent_low[0x20];
5919
5920         u8         reserved_at_320[0x560];
5921 };
5922
5923 struct mlx5_ifc_query_cong_statistics_in_bits {
5924         u8         opcode[0x10];
5925         u8         reserved_at_10[0x10];
5926
5927         u8         reserved_at_20[0x10];
5928         u8         op_mod[0x10];
5929
5930         u8         clear[0x1];
5931         u8         reserved_at_41[0x1f];
5932
5933         u8         reserved_at_60[0x20];
5934 };
5935
5936 struct mlx5_ifc_query_cong_params_out_bits {
5937         u8         status[0x8];
5938         u8         reserved_at_8[0x18];
5939
5940         u8         syndrome[0x20];
5941
5942         u8         reserved_at_40[0x40];
5943
5944         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5945 };
5946
5947 struct mlx5_ifc_query_cong_params_in_bits {
5948         u8         opcode[0x10];
5949         u8         reserved_at_10[0x10];
5950
5951         u8         reserved_at_20[0x10];
5952         u8         op_mod[0x10];
5953
5954         u8         reserved_at_40[0x1c];
5955         u8         cong_protocol[0x4];
5956
5957         u8         reserved_at_60[0x20];
5958 };
5959
5960 struct mlx5_ifc_query_adapter_out_bits {
5961         u8         status[0x8];
5962         u8         reserved_at_8[0x18];
5963
5964         u8         syndrome[0x20];
5965
5966         u8         reserved_at_40[0x40];
5967
5968         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5969 };
5970
5971 struct mlx5_ifc_query_adapter_in_bits {
5972         u8         opcode[0x10];
5973         u8         reserved_at_10[0x10];
5974
5975         u8         reserved_at_20[0x10];
5976         u8         op_mod[0x10];
5977
5978         u8         reserved_at_40[0x40];
5979 };
5980
5981 struct mlx5_ifc_qp_2rst_out_bits {
5982         u8         status[0x8];
5983         u8         reserved_at_8[0x18];
5984
5985         u8         syndrome[0x20];
5986
5987         u8         reserved_at_40[0x40];
5988 };
5989
5990 struct mlx5_ifc_qp_2rst_in_bits {
5991         u8         opcode[0x10];
5992         u8         uid[0x10];
5993
5994         u8         reserved_at_20[0x10];
5995         u8         op_mod[0x10];
5996
5997         u8         reserved_at_40[0x8];
5998         u8         qpn[0x18];
5999
6000         u8         reserved_at_60[0x20];
6001 };
6002
6003 struct mlx5_ifc_qp_2err_out_bits {
6004         u8         status[0x8];
6005         u8         reserved_at_8[0x18];
6006
6007         u8         syndrome[0x20];
6008
6009         u8         reserved_at_40[0x40];
6010 };
6011
6012 struct mlx5_ifc_qp_2err_in_bits {
6013         u8         opcode[0x10];
6014         u8         uid[0x10];
6015
6016         u8         reserved_at_20[0x10];
6017         u8         op_mod[0x10];
6018
6019         u8         reserved_at_40[0x8];
6020         u8         qpn[0x18];
6021
6022         u8         reserved_at_60[0x20];
6023 };
6024
6025 struct mlx5_ifc_page_fault_resume_out_bits {
6026         u8         status[0x8];
6027         u8         reserved_at_8[0x18];
6028
6029         u8         syndrome[0x20];
6030
6031         u8         reserved_at_40[0x40];
6032 };
6033
6034 struct mlx5_ifc_page_fault_resume_in_bits {
6035         u8         opcode[0x10];
6036         u8         reserved_at_10[0x10];
6037
6038         u8         reserved_at_20[0x10];
6039         u8         op_mod[0x10];
6040
6041         u8         error[0x1];
6042         u8         reserved_at_41[0x4];
6043         u8         page_fault_type[0x3];
6044         u8         wq_number[0x18];
6045
6046         u8         reserved_at_60[0x8];
6047         u8         token[0x18];
6048 };
6049
6050 struct mlx5_ifc_nop_out_bits {
6051         u8         status[0x8];
6052         u8         reserved_at_8[0x18];
6053
6054         u8         syndrome[0x20];
6055
6056         u8         reserved_at_40[0x40];
6057 };
6058
6059 struct mlx5_ifc_nop_in_bits {
6060         u8         opcode[0x10];
6061         u8         reserved_at_10[0x10];
6062
6063         u8         reserved_at_20[0x10];
6064         u8         op_mod[0x10];
6065
6066         u8         reserved_at_40[0x40];
6067 };
6068
6069 struct mlx5_ifc_modify_vport_state_out_bits {
6070         u8         status[0x8];
6071         u8         reserved_at_8[0x18];
6072
6073         u8         syndrome[0x20];
6074
6075         u8         reserved_at_40[0x40];
6076 };
6077
6078 struct mlx5_ifc_modify_vport_state_in_bits {
6079         u8         opcode[0x10];
6080         u8         reserved_at_10[0x10];
6081
6082         u8         reserved_at_20[0x10];
6083         u8         op_mod[0x10];
6084
6085         u8         other_vport[0x1];
6086         u8         reserved_at_41[0xf];
6087         u8         vport_number[0x10];
6088
6089         u8         reserved_at_60[0x18];
6090         u8         admin_state[0x4];
6091         u8         reserved_at_7c[0x4];
6092 };
6093
6094 struct mlx5_ifc_modify_tis_out_bits {
6095         u8         status[0x8];
6096         u8         reserved_at_8[0x18];
6097
6098         u8         syndrome[0x20];
6099
6100         u8         reserved_at_40[0x40];
6101 };
6102
6103 struct mlx5_ifc_modify_tis_bitmask_bits {
6104         u8         reserved_at_0[0x20];
6105
6106         u8         reserved_at_20[0x1d];
6107         u8         lag_tx_port_affinity[0x1];
6108         u8         strict_lag_tx_port_affinity[0x1];
6109         u8         prio[0x1];
6110 };
6111
6112 struct mlx5_ifc_modify_tis_in_bits {
6113         u8         opcode[0x10];
6114         u8         uid[0x10];
6115
6116         u8         reserved_at_20[0x10];
6117         u8         op_mod[0x10];
6118
6119         u8         reserved_at_40[0x8];
6120         u8         tisn[0x18];
6121
6122         u8         reserved_at_60[0x20];
6123
6124         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6125
6126         u8         reserved_at_c0[0x40];
6127
6128         struct mlx5_ifc_tisc_bits ctx;
6129 };
6130
6131 struct mlx5_ifc_modify_tir_bitmask_bits {
6132         u8         reserved_at_0[0x20];
6133
6134         u8         reserved_at_20[0x1b];
6135         u8         self_lb_en[0x1];
6136         u8         reserved_at_3c[0x1];
6137         u8         hash[0x1];
6138         u8         reserved_at_3e[0x1];
6139         u8         lro[0x1];
6140 };
6141
6142 struct mlx5_ifc_modify_tir_out_bits {
6143         u8         status[0x8];
6144         u8         reserved_at_8[0x18];
6145
6146         u8         syndrome[0x20];
6147
6148         u8         reserved_at_40[0x40];
6149 };
6150
6151 struct mlx5_ifc_modify_tir_in_bits {
6152         u8         opcode[0x10];
6153         u8         uid[0x10];
6154
6155         u8         reserved_at_20[0x10];
6156         u8         op_mod[0x10];
6157
6158         u8         reserved_at_40[0x8];
6159         u8         tirn[0x18];
6160
6161         u8         reserved_at_60[0x20];
6162
6163         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6164
6165         u8         reserved_at_c0[0x40];
6166
6167         struct mlx5_ifc_tirc_bits ctx;
6168 };
6169
6170 struct mlx5_ifc_modify_sq_out_bits {
6171         u8         status[0x8];
6172         u8         reserved_at_8[0x18];
6173
6174         u8         syndrome[0x20];
6175
6176         u8         reserved_at_40[0x40];
6177 };
6178
6179 struct mlx5_ifc_modify_sq_in_bits {
6180         u8         opcode[0x10];
6181         u8         uid[0x10];
6182
6183         u8         reserved_at_20[0x10];
6184         u8         op_mod[0x10];
6185
6186         u8         sq_state[0x4];
6187         u8         reserved_at_44[0x4];
6188         u8         sqn[0x18];
6189
6190         u8         reserved_at_60[0x20];
6191
6192         u8         modify_bitmask[0x40];
6193
6194         u8         reserved_at_c0[0x40];
6195
6196         struct mlx5_ifc_sqc_bits ctx;
6197 };
6198
6199 struct mlx5_ifc_modify_scheduling_element_out_bits {
6200         u8         status[0x8];
6201         u8         reserved_at_8[0x18];
6202
6203         u8         syndrome[0x20];
6204
6205         u8         reserved_at_40[0x1c0];
6206 };
6207
6208 enum {
6209         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6210         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6211 };
6212
6213 struct mlx5_ifc_modify_scheduling_element_in_bits {
6214         u8         opcode[0x10];
6215         u8         reserved_at_10[0x10];
6216
6217         u8         reserved_at_20[0x10];
6218         u8         op_mod[0x10];
6219
6220         u8         scheduling_hierarchy[0x8];
6221         u8         reserved_at_48[0x18];
6222
6223         u8         scheduling_element_id[0x20];
6224
6225         u8         reserved_at_80[0x20];
6226
6227         u8         modify_bitmask[0x20];
6228
6229         u8         reserved_at_c0[0x40];
6230
6231         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6232
6233         u8         reserved_at_300[0x100];
6234 };
6235
6236 struct mlx5_ifc_modify_rqt_out_bits {
6237         u8         status[0x8];
6238         u8         reserved_at_8[0x18];
6239
6240         u8         syndrome[0x20];
6241
6242         u8         reserved_at_40[0x40];
6243 };
6244
6245 struct mlx5_ifc_rqt_bitmask_bits {
6246         u8         reserved_at_0[0x20];
6247
6248         u8         reserved_at_20[0x1f];
6249         u8         rqn_list[0x1];
6250 };
6251
6252 struct mlx5_ifc_modify_rqt_in_bits {
6253         u8         opcode[0x10];
6254         u8         uid[0x10];
6255
6256         u8         reserved_at_20[0x10];
6257         u8         op_mod[0x10];
6258
6259         u8         reserved_at_40[0x8];
6260         u8         rqtn[0x18];
6261
6262         u8         reserved_at_60[0x20];
6263
6264         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6265
6266         u8         reserved_at_c0[0x40];
6267
6268         struct mlx5_ifc_rqtc_bits ctx;
6269 };
6270
6271 struct mlx5_ifc_modify_rq_out_bits {
6272         u8         status[0x8];
6273         u8         reserved_at_8[0x18];
6274
6275         u8         syndrome[0x20];
6276
6277         u8         reserved_at_40[0x40];
6278 };
6279
6280 enum {
6281         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6282         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6283         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6284 };
6285
6286 struct mlx5_ifc_modify_rq_in_bits {
6287         u8         opcode[0x10];
6288         u8         uid[0x10];
6289
6290         u8         reserved_at_20[0x10];
6291         u8         op_mod[0x10];
6292
6293         u8         rq_state[0x4];
6294         u8         reserved_at_44[0x4];
6295         u8         rqn[0x18];
6296
6297         u8         reserved_at_60[0x20];
6298
6299         u8         modify_bitmask[0x40];
6300
6301         u8         reserved_at_c0[0x40];
6302
6303         struct mlx5_ifc_rqc_bits ctx;
6304 };
6305
6306 struct mlx5_ifc_modify_rmp_out_bits {
6307         u8         status[0x8];
6308         u8         reserved_at_8[0x18];
6309
6310         u8         syndrome[0x20];
6311
6312         u8         reserved_at_40[0x40];
6313 };
6314
6315 struct mlx5_ifc_rmp_bitmask_bits {
6316         u8         reserved_at_0[0x20];
6317
6318         u8         reserved_at_20[0x1f];
6319         u8         lwm[0x1];
6320 };
6321
6322 struct mlx5_ifc_modify_rmp_in_bits {
6323         u8         opcode[0x10];
6324         u8         uid[0x10];
6325
6326         u8         reserved_at_20[0x10];
6327         u8         op_mod[0x10];
6328
6329         u8         rmp_state[0x4];
6330         u8         reserved_at_44[0x4];
6331         u8         rmpn[0x18];
6332
6333         u8         reserved_at_60[0x20];
6334
6335         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6336
6337         u8         reserved_at_c0[0x40];
6338
6339         struct mlx5_ifc_rmpc_bits ctx;
6340 };
6341
6342 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6343         u8         status[0x8];
6344         u8         reserved_at_8[0x18];
6345
6346         u8         syndrome[0x20];
6347
6348         u8         reserved_at_40[0x40];
6349 };
6350
6351 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6352         u8         reserved_at_0[0x12];
6353         u8         affiliation[0x1];
6354         u8         reserved_at_13[0x1];
6355         u8         disable_uc_local_lb[0x1];
6356         u8         disable_mc_local_lb[0x1];
6357         u8         node_guid[0x1];
6358         u8         port_guid[0x1];
6359         u8         min_inline[0x1];
6360         u8         mtu[0x1];
6361         u8         change_event[0x1];
6362         u8         promisc[0x1];
6363         u8         permanent_address[0x1];
6364         u8         addresses_list[0x1];
6365         u8         roce_en[0x1];
6366         u8         reserved_at_1f[0x1];
6367 };
6368
6369 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6370         u8         opcode[0x10];
6371         u8         reserved_at_10[0x10];
6372
6373         u8         reserved_at_20[0x10];
6374         u8         op_mod[0x10];
6375
6376         u8         other_vport[0x1];
6377         u8         reserved_at_41[0xf];
6378         u8         vport_number[0x10];
6379
6380         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6381
6382         u8         reserved_at_80[0x780];
6383
6384         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6385 };
6386
6387 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6388         u8         status[0x8];
6389         u8         reserved_at_8[0x18];
6390
6391         u8         syndrome[0x20];
6392
6393         u8         reserved_at_40[0x40];
6394 };
6395
6396 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6397         u8         opcode[0x10];
6398         u8         reserved_at_10[0x10];
6399
6400         u8         reserved_at_20[0x10];
6401         u8         op_mod[0x10];
6402
6403         u8         other_vport[0x1];
6404         u8         reserved_at_41[0xb];
6405         u8         port_num[0x4];
6406         u8         vport_number[0x10];
6407
6408         u8         reserved_at_60[0x20];
6409
6410         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6411 };
6412
6413 struct mlx5_ifc_modify_cq_out_bits {
6414         u8         status[0x8];
6415         u8         reserved_at_8[0x18];
6416
6417         u8         syndrome[0x20];
6418
6419         u8         reserved_at_40[0x40];
6420 };
6421
6422 enum {
6423         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6424         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6425 };
6426
6427 struct mlx5_ifc_modify_cq_in_bits {
6428         u8         opcode[0x10];
6429         u8         uid[0x10];
6430
6431         u8         reserved_at_20[0x10];
6432         u8         op_mod[0x10];
6433
6434         u8         reserved_at_40[0x8];
6435         u8         cqn[0x18];
6436
6437         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6438
6439         struct mlx5_ifc_cqc_bits cq_context;
6440
6441         u8         reserved_at_280[0x60];
6442
6443         u8         cq_umem_valid[0x1];
6444         u8         reserved_at_2e1[0x1f];
6445
6446         u8         reserved_at_300[0x580];
6447
6448         u8         pas[][0x40];
6449 };
6450
6451 struct mlx5_ifc_modify_cong_status_out_bits {
6452         u8         status[0x8];
6453         u8         reserved_at_8[0x18];
6454
6455         u8         syndrome[0x20];
6456
6457         u8         reserved_at_40[0x40];
6458 };
6459
6460 struct mlx5_ifc_modify_cong_status_in_bits {
6461         u8         opcode[0x10];
6462         u8         reserved_at_10[0x10];
6463
6464         u8         reserved_at_20[0x10];
6465         u8         op_mod[0x10];
6466
6467         u8         reserved_at_40[0x18];
6468         u8         priority[0x4];
6469         u8         cong_protocol[0x4];
6470
6471         u8         enable[0x1];
6472         u8         tag_enable[0x1];
6473         u8         reserved_at_62[0x1e];
6474 };
6475
6476 struct mlx5_ifc_modify_cong_params_out_bits {
6477         u8         status[0x8];
6478         u8         reserved_at_8[0x18];
6479
6480         u8         syndrome[0x20];
6481
6482         u8         reserved_at_40[0x40];
6483 };
6484
6485 struct mlx5_ifc_modify_cong_params_in_bits {
6486         u8         opcode[0x10];
6487         u8         reserved_at_10[0x10];
6488
6489         u8         reserved_at_20[0x10];
6490         u8         op_mod[0x10];
6491
6492         u8         reserved_at_40[0x1c];
6493         u8         cong_protocol[0x4];
6494
6495         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6496
6497         u8         reserved_at_80[0x80];
6498
6499         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6500 };
6501
6502 struct mlx5_ifc_manage_pages_out_bits {
6503         u8         status[0x8];
6504         u8         reserved_at_8[0x18];
6505
6506         u8         syndrome[0x20];
6507
6508         u8         output_num_entries[0x20];
6509
6510         u8         reserved_at_60[0x20];
6511
6512         u8         pas[][0x40];
6513 };
6514
6515 enum {
6516         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6517         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6518         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6519 };
6520
6521 struct mlx5_ifc_manage_pages_in_bits {
6522         u8         opcode[0x10];
6523         u8         reserved_at_10[0x10];
6524
6525         u8         reserved_at_20[0x10];
6526         u8         op_mod[0x10];
6527
6528         u8         embedded_cpu_function[0x1];
6529         u8         reserved_at_41[0xf];
6530         u8         function_id[0x10];
6531
6532         u8         input_num_entries[0x20];
6533
6534         u8         pas[][0x40];
6535 };
6536
6537 struct mlx5_ifc_mad_ifc_out_bits {
6538         u8         status[0x8];
6539         u8         reserved_at_8[0x18];
6540
6541         u8         syndrome[0x20];
6542
6543         u8         reserved_at_40[0x40];
6544
6545         u8         response_mad_packet[256][0x8];
6546 };
6547
6548 struct mlx5_ifc_mad_ifc_in_bits {
6549         u8         opcode[0x10];
6550         u8         reserved_at_10[0x10];
6551
6552         u8         reserved_at_20[0x10];
6553         u8         op_mod[0x10];
6554
6555         u8         remote_lid[0x10];
6556         u8         reserved_at_50[0x8];
6557         u8         port[0x8];
6558
6559         u8         reserved_at_60[0x20];
6560
6561         u8         mad[256][0x8];
6562 };
6563
6564 struct mlx5_ifc_init_hca_out_bits {
6565         u8         status[0x8];
6566         u8         reserved_at_8[0x18];
6567
6568         u8         syndrome[0x20];
6569
6570         u8         reserved_at_40[0x40];
6571 };
6572
6573 struct mlx5_ifc_init_hca_in_bits {
6574         u8         opcode[0x10];
6575         u8         reserved_at_10[0x10];
6576
6577         u8         reserved_at_20[0x10];
6578         u8         op_mod[0x10];
6579
6580         u8         reserved_at_40[0x40];
6581         u8         sw_owner_id[4][0x20];
6582 };
6583
6584 struct mlx5_ifc_init2rtr_qp_out_bits {
6585         u8         status[0x8];
6586         u8         reserved_at_8[0x18];
6587
6588         u8         syndrome[0x20];
6589
6590         u8         reserved_at_40[0x20];
6591         u8         ece[0x20];
6592 };
6593
6594 struct mlx5_ifc_init2rtr_qp_in_bits {
6595         u8         opcode[0x10];
6596         u8         uid[0x10];
6597
6598         u8         reserved_at_20[0x10];
6599         u8         op_mod[0x10];
6600
6601         u8         reserved_at_40[0x8];
6602         u8         qpn[0x18];
6603
6604         u8         reserved_at_60[0x20];
6605
6606         u8         opt_param_mask[0x20];
6607
6608         u8         ece[0x20];
6609
6610         struct mlx5_ifc_qpc_bits qpc;
6611
6612         u8         reserved_at_800[0x80];
6613 };
6614
6615 struct mlx5_ifc_init2init_qp_out_bits {
6616         u8         status[0x8];
6617         u8         reserved_at_8[0x18];
6618
6619         u8         syndrome[0x20];
6620
6621         u8         reserved_at_40[0x40];
6622 };
6623
6624 struct mlx5_ifc_init2init_qp_in_bits {
6625         u8         opcode[0x10];
6626         u8         uid[0x10];
6627
6628         u8         reserved_at_20[0x10];
6629         u8         op_mod[0x10];
6630
6631         u8         reserved_at_40[0x8];
6632         u8         qpn[0x18];
6633
6634         u8         reserved_at_60[0x20];
6635
6636         u8         opt_param_mask[0x20];
6637
6638         u8         reserved_at_a0[0x20];
6639
6640         struct mlx5_ifc_qpc_bits qpc;
6641
6642         u8         reserved_at_800[0x80];
6643 };
6644
6645 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6646         u8         status[0x8];
6647         u8         reserved_at_8[0x18];
6648
6649         u8         syndrome[0x20];
6650
6651         u8         reserved_at_40[0x40];
6652
6653         u8         packet_headers_log[128][0x8];
6654
6655         u8         packet_syndrome[64][0x8];
6656 };
6657
6658 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6659         u8         opcode[0x10];
6660         u8         reserved_at_10[0x10];
6661
6662         u8         reserved_at_20[0x10];
6663         u8         op_mod[0x10];
6664
6665         u8         reserved_at_40[0x40];
6666 };
6667
6668 struct mlx5_ifc_gen_eqe_in_bits {
6669         u8         opcode[0x10];
6670         u8         reserved_at_10[0x10];
6671
6672         u8         reserved_at_20[0x10];
6673         u8         op_mod[0x10];
6674
6675         u8         reserved_at_40[0x18];
6676         u8         eq_number[0x8];
6677
6678         u8         reserved_at_60[0x20];
6679
6680         u8         eqe[64][0x8];
6681 };
6682
6683 struct mlx5_ifc_gen_eq_out_bits {
6684         u8         status[0x8];
6685         u8         reserved_at_8[0x18];
6686
6687         u8         syndrome[0x20];
6688
6689         u8         reserved_at_40[0x40];
6690 };
6691
6692 struct mlx5_ifc_enable_hca_out_bits {
6693         u8         status[0x8];
6694         u8         reserved_at_8[0x18];
6695
6696         u8         syndrome[0x20];
6697
6698         u8         reserved_at_40[0x20];
6699 };
6700
6701 struct mlx5_ifc_enable_hca_in_bits {
6702         u8         opcode[0x10];
6703         u8         reserved_at_10[0x10];
6704
6705         u8         reserved_at_20[0x10];
6706         u8         op_mod[0x10];
6707
6708         u8         embedded_cpu_function[0x1];
6709         u8         reserved_at_41[0xf];
6710         u8         function_id[0x10];
6711
6712         u8         reserved_at_60[0x20];
6713 };
6714
6715 struct mlx5_ifc_drain_dct_out_bits {
6716         u8         status[0x8];
6717         u8         reserved_at_8[0x18];
6718
6719         u8         syndrome[0x20];
6720
6721         u8         reserved_at_40[0x40];
6722 };
6723
6724 struct mlx5_ifc_drain_dct_in_bits {
6725         u8         opcode[0x10];
6726         u8         uid[0x10];
6727
6728         u8         reserved_at_20[0x10];
6729         u8         op_mod[0x10];
6730
6731         u8         reserved_at_40[0x8];
6732         u8         dctn[0x18];
6733
6734         u8         reserved_at_60[0x20];
6735 };
6736
6737 struct mlx5_ifc_disable_hca_out_bits {
6738         u8         status[0x8];
6739         u8         reserved_at_8[0x18];
6740
6741         u8         syndrome[0x20];
6742
6743         u8         reserved_at_40[0x20];
6744 };
6745
6746 struct mlx5_ifc_disable_hca_in_bits {
6747         u8         opcode[0x10];
6748         u8         reserved_at_10[0x10];
6749
6750         u8         reserved_at_20[0x10];
6751         u8         op_mod[0x10];
6752
6753         u8         embedded_cpu_function[0x1];
6754         u8         reserved_at_41[0xf];
6755         u8         function_id[0x10];
6756
6757         u8         reserved_at_60[0x20];
6758 };
6759
6760 struct mlx5_ifc_detach_from_mcg_out_bits {
6761         u8         status[0x8];
6762         u8         reserved_at_8[0x18];
6763
6764         u8         syndrome[0x20];
6765
6766         u8         reserved_at_40[0x40];
6767 };
6768
6769 struct mlx5_ifc_detach_from_mcg_in_bits {
6770         u8         opcode[0x10];
6771         u8         uid[0x10];
6772
6773         u8         reserved_at_20[0x10];
6774         u8         op_mod[0x10];
6775
6776         u8         reserved_at_40[0x8];
6777         u8         qpn[0x18];
6778
6779         u8         reserved_at_60[0x20];
6780
6781         u8         multicast_gid[16][0x8];
6782 };
6783
6784 struct mlx5_ifc_destroy_xrq_out_bits {
6785         u8         status[0x8];
6786         u8         reserved_at_8[0x18];
6787
6788         u8         syndrome[0x20];
6789
6790         u8         reserved_at_40[0x40];
6791 };
6792
6793 struct mlx5_ifc_destroy_xrq_in_bits {
6794         u8         opcode[0x10];
6795         u8         uid[0x10];
6796
6797         u8         reserved_at_20[0x10];
6798         u8         op_mod[0x10];
6799
6800         u8         reserved_at_40[0x8];
6801         u8         xrqn[0x18];
6802
6803         u8         reserved_at_60[0x20];
6804 };
6805
6806 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6807         u8         status[0x8];
6808         u8         reserved_at_8[0x18];
6809
6810         u8         syndrome[0x20];
6811
6812         u8         reserved_at_40[0x40];
6813 };
6814
6815 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6816         u8         opcode[0x10];
6817         u8         uid[0x10];
6818
6819         u8         reserved_at_20[0x10];
6820         u8         op_mod[0x10];
6821
6822         u8         reserved_at_40[0x8];
6823         u8         xrc_srqn[0x18];
6824
6825         u8         reserved_at_60[0x20];
6826 };
6827
6828 struct mlx5_ifc_destroy_tis_out_bits {
6829         u8         status[0x8];
6830         u8         reserved_at_8[0x18];
6831
6832         u8         syndrome[0x20];
6833
6834         u8         reserved_at_40[0x40];
6835 };
6836
6837 struct mlx5_ifc_destroy_tis_in_bits {
6838         u8         opcode[0x10];
6839         u8         uid[0x10];
6840
6841         u8         reserved_at_20[0x10];
6842         u8         op_mod[0x10];
6843
6844         u8         reserved_at_40[0x8];
6845         u8         tisn[0x18];
6846
6847         u8         reserved_at_60[0x20];
6848 };
6849
6850 struct mlx5_ifc_destroy_tir_out_bits {
6851         u8         status[0x8];
6852         u8         reserved_at_8[0x18];
6853
6854         u8         syndrome[0x20];
6855
6856         u8         reserved_at_40[0x40];
6857 };
6858
6859 struct mlx5_ifc_destroy_tir_in_bits {
6860         u8         opcode[0x10];
6861         u8         uid[0x10];
6862
6863         u8         reserved_at_20[0x10];
6864         u8         op_mod[0x10];
6865
6866         u8         reserved_at_40[0x8];
6867         u8         tirn[0x18];
6868
6869         u8         reserved_at_60[0x20];
6870 };
6871
6872 struct mlx5_ifc_destroy_srq_out_bits {
6873         u8         status[0x8];
6874         u8         reserved_at_8[0x18];
6875
6876         u8         syndrome[0x20];
6877
6878         u8         reserved_at_40[0x40];
6879 };
6880
6881 struct mlx5_ifc_destroy_srq_in_bits {
6882         u8         opcode[0x10];
6883         u8         uid[0x10];
6884
6885         u8         reserved_at_20[0x10];
6886         u8         op_mod[0x10];
6887
6888         u8         reserved_at_40[0x8];
6889         u8         srqn[0x18];
6890
6891         u8         reserved_at_60[0x20];
6892 };
6893
6894 struct mlx5_ifc_destroy_sq_out_bits {
6895         u8         status[0x8];
6896         u8         reserved_at_8[0x18];
6897
6898         u8         syndrome[0x20];
6899
6900         u8         reserved_at_40[0x40];
6901 };
6902
6903 struct mlx5_ifc_destroy_sq_in_bits {
6904         u8         opcode[0x10];
6905         u8         uid[0x10];
6906
6907         u8         reserved_at_20[0x10];
6908         u8         op_mod[0x10];
6909
6910         u8         reserved_at_40[0x8];
6911         u8         sqn[0x18];
6912
6913         u8         reserved_at_60[0x20];
6914 };
6915
6916 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6917         u8         status[0x8];
6918         u8         reserved_at_8[0x18];
6919
6920         u8         syndrome[0x20];
6921
6922         u8         reserved_at_40[0x1c0];
6923 };
6924
6925 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6926         u8         opcode[0x10];
6927         u8         reserved_at_10[0x10];
6928
6929         u8         reserved_at_20[0x10];
6930         u8         op_mod[0x10];
6931
6932         u8         scheduling_hierarchy[0x8];
6933         u8         reserved_at_48[0x18];
6934
6935         u8         scheduling_element_id[0x20];
6936
6937         u8         reserved_at_80[0x180];
6938 };
6939
6940 struct mlx5_ifc_destroy_rqt_out_bits {
6941         u8         status[0x8];
6942         u8         reserved_at_8[0x18];
6943
6944         u8         syndrome[0x20];
6945
6946         u8         reserved_at_40[0x40];
6947 };
6948
6949 struct mlx5_ifc_destroy_rqt_in_bits {
6950         u8         opcode[0x10];
6951         u8         uid[0x10];
6952
6953         u8         reserved_at_20[0x10];
6954         u8         op_mod[0x10];
6955
6956         u8         reserved_at_40[0x8];
6957         u8         rqtn[0x18];
6958
6959         u8         reserved_at_60[0x20];
6960 };
6961
6962 struct mlx5_ifc_destroy_rq_out_bits {
6963         u8         status[0x8];
6964         u8         reserved_at_8[0x18];
6965
6966         u8         syndrome[0x20];
6967
6968         u8         reserved_at_40[0x40];
6969 };
6970
6971 struct mlx5_ifc_destroy_rq_in_bits {
6972         u8         opcode[0x10];
6973         u8         uid[0x10];
6974
6975         u8         reserved_at_20[0x10];
6976         u8         op_mod[0x10];
6977
6978         u8         reserved_at_40[0x8];
6979         u8         rqn[0x18];
6980
6981         u8         reserved_at_60[0x20];
6982 };
6983
6984 struct mlx5_ifc_set_delay_drop_params_in_bits {
6985         u8         opcode[0x10];
6986         u8         reserved_at_10[0x10];
6987
6988         u8         reserved_at_20[0x10];
6989         u8         op_mod[0x10];
6990
6991         u8         reserved_at_40[0x20];
6992
6993         u8         reserved_at_60[0x10];
6994         u8         delay_drop_timeout[0x10];
6995 };
6996
6997 struct mlx5_ifc_set_delay_drop_params_out_bits {
6998         u8         status[0x8];
6999         u8         reserved_at_8[0x18];
7000
7001         u8         syndrome[0x20];
7002
7003         u8         reserved_at_40[0x40];
7004 };
7005
7006 struct mlx5_ifc_destroy_rmp_out_bits {
7007         u8         status[0x8];
7008         u8         reserved_at_8[0x18];
7009
7010         u8         syndrome[0x20];
7011
7012         u8         reserved_at_40[0x40];
7013 };
7014
7015 struct mlx5_ifc_destroy_rmp_in_bits {
7016         u8         opcode[0x10];
7017         u8         uid[0x10];
7018
7019         u8         reserved_at_20[0x10];
7020         u8         op_mod[0x10];
7021
7022         u8         reserved_at_40[0x8];
7023         u8         rmpn[0x18];
7024
7025         u8         reserved_at_60[0x20];
7026 };
7027
7028 struct mlx5_ifc_destroy_qp_out_bits {
7029         u8         status[0x8];
7030         u8         reserved_at_8[0x18];
7031
7032         u8         syndrome[0x20];
7033
7034         u8         reserved_at_40[0x40];
7035 };
7036
7037 struct mlx5_ifc_destroy_qp_in_bits {
7038         u8         opcode[0x10];
7039         u8         uid[0x10];
7040
7041         u8         reserved_at_20[0x10];
7042         u8         op_mod[0x10];
7043
7044         u8         reserved_at_40[0x8];
7045         u8         qpn[0x18];
7046
7047         u8         reserved_at_60[0x20];
7048 };
7049
7050 struct mlx5_ifc_destroy_psv_out_bits {
7051         u8         status[0x8];
7052         u8         reserved_at_8[0x18];
7053
7054         u8         syndrome[0x20];
7055
7056         u8         reserved_at_40[0x40];
7057 };
7058
7059 struct mlx5_ifc_destroy_psv_in_bits {
7060         u8         opcode[0x10];
7061         u8         reserved_at_10[0x10];
7062
7063         u8         reserved_at_20[0x10];
7064         u8         op_mod[0x10];
7065
7066         u8         reserved_at_40[0x8];
7067         u8         psvn[0x18];
7068
7069         u8         reserved_at_60[0x20];
7070 };
7071
7072 struct mlx5_ifc_destroy_mkey_out_bits {
7073         u8         status[0x8];
7074         u8         reserved_at_8[0x18];
7075
7076         u8         syndrome[0x20];
7077
7078         u8         reserved_at_40[0x40];
7079 };
7080
7081 struct mlx5_ifc_destroy_mkey_in_bits {
7082         u8         opcode[0x10];
7083         u8         reserved_at_10[0x10];
7084
7085         u8         reserved_at_20[0x10];
7086         u8         op_mod[0x10];
7087
7088         u8         reserved_at_40[0x8];
7089         u8         mkey_index[0x18];
7090
7091         u8         reserved_at_60[0x20];
7092 };
7093
7094 struct mlx5_ifc_destroy_flow_table_out_bits {
7095         u8         status[0x8];
7096         u8         reserved_at_8[0x18];
7097
7098         u8         syndrome[0x20];
7099
7100         u8         reserved_at_40[0x40];
7101 };
7102
7103 struct mlx5_ifc_destroy_flow_table_in_bits {
7104         u8         opcode[0x10];
7105         u8         reserved_at_10[0x10];
7106
7107         u8         reserved_at_20[0x10];
7108         u8         op_mod[0x10];
7109
7110         u8         other_vport[0x1];
7111         u8         reserved_at_41[0xf];
7112         u8         vport_number[0x10];
7113
7114         u8         reserved_at_60[0x20];
7115
7116         u8         table_type[0x8];
7117         u8         reserved_at_88[0x18];
7118
7119         u8         reserved_at_a0[0x8];
7120         u8         table_id[0x18];
7121
7122         u8         reserved_at_c0[0x140];
7123 };
7124
7125 struct mlx5_ifc_destroy_flow_group_out_bits {
7126         u8         status[0x8];
7127         u8         reserved_at_8[0x18];
7128
7129         u8         syndrome[0x20];
7130
7131         u8         reserved_at_40[0x40];
7132 };
7133
7134 struct mlx5_ifc_destroy_flow_group_in_bits {
7135         u8         opcode[0x10];
7136         u8         reserved_at_10[0x10];
7137
7138         u8         reserved_at_20[0x10];
7139         u8         op_mod[0x10];
7140
7141         u8         other_vport[0x1];
7142         u8         reserved_at_41[0xf];
7143         u8         vport_number[0x10];
7144
7145         u8         reserved_at_60[0x20];
7146
7147         u8         table_type[0x8];
7148         u8         reserved_at_88[0x18];
7149
7150         u8         reserved_at_a0[0x8];
7151         u8         table_id[0x18];
7152
7153         u8         group_id[0x20];
7154
7155         u8         reserved_at_e0[0x120];
7156 };
7157
7158 struct mlx5_ifc_destroy_eq_out_bits {
7159         u8         status[0x8];
7160         u8         reserved_at_8[0x18];
7161
7162         u8         syndrome[0x20];
7163
7164         u8         reserved_at_40[0x40];
7165 };
7166
7167 struct mlx5_ifc_destroy_eq_in_bits {
7168         u8         opcode[0x10];
7169         u8         reserved_at_10[0x10];
7170
7171         u8         reserved_at_20[0x10];
7172         u8         op_mod[0x10];
7173
7174         u8         reserved_at_40[0x18];
7175         u8         eq_number[0x8];
7176
7177         u8         reserved_at_60[0x20];
7178 };
7179
7180 struct mlx5_ifc_destroy_dct_out_bits {
7181         u8         status[0x8];
7182         u8         reserved_at_8[0x18];
7183
7184         u8         syndrome[0x20];
7185
7186         u8         reserved_at_40[0x40];
7187 };
7188
7189 struct mlx5_ifc_destroy_dct_in_bits {
7190         u8         opcode[0x10];
7191         u8         uid[0x10];
7192
7193         u8         reserved_at_20[0x10];
7194         u8         op_mod[0x10];
7195
7196         u8         reserved_at_40[0x8];
7197         u8         dctn[0x18];
7198
7199         u8         reserved_at_60[0x20];
7200 };
7201
7202 struct mlx5_ifc_destroy_cq_out_bits {
7203         u8         status[0x8];
7204         u8         reserved_at_8[0x18];
7205
7206         u8         syndrome[0x20];
7207
7208         u8         reserved_at_40[0x40];
7209 };
7210
7211 struct mlx5_ifc_destroy_cq_in_bits {
7212         u8         opcode[0x10];
7213         u8         uid[0x10];
7214
7215         u8         reserved_at_20[0x10];
7216         u8         op_mod[0x10];
7217
7218         u8         reserved_at_40[0x8];
7219         u8         cqn[0x18];
7220
7221         u8         reserved_at_60[0x20];
7222 };
7223
7224 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7225         u8         status[0x8];
7226         u8         reserved_at_8[0x18];
7227
7228         u8         syndrome[0x20];
7229
7230         u8         reserved_at_40[0x40];
7231 };
7232
7233 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7234         u8         opcode[0x10];
7235         u8         reserved_at_10[0x10];
7236
7237         u8         reserved_at_20[0x10];
7238         u8         op_mod[0x10];
7239
7240         u8         reserved_at_40[0x20];
7241
7242         u8         reserved_at_60[0x10];
7243         u8         vxlan_udp_port[0x10];
7244 };
7245
7246 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7247         u8         status[0x8];
7248         u8         reserved_at_8[0x18];
7249
7250         u8         syndrome[0x20];
7251
7252         u8         reserved_at_40[0x40];
7253 };
7254
7255 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7256         u8         opcode[0x10];
7257         u8         reserved_at_10[0x10];
7258
7259         u8         reserved_at_20[0x10];
7260         u8         op_mod[0x10];
7261
7262         u8         reserved_at_40[0x60];
7263
7264         u8         reserved_at_a0[0x8];
7265         u8         table_index[0x18];
7266
7267         u8         reserved_at_c0[0x140];
7268 };
7269
7270 struct mlx5_ifc_delete_fte_out_bits {
7271         u8         status[0x8];
7272         u8         reserved_at_8[0x18];
7273
7274         u8         syndrome[0x20];
7275
7276         u8         reserved_at_40[0x40];
7277 };
7278
7279 struct mlx5_ifc_delete_fte_in_bits {
7280         u8         opcode[0x10];
7281         u8         reserved_at_10[0x10];
7282
7283         u8         reserved_at_20[0x10];
7284         u8         op_mod[0x10];
7285
7286         u8         other_vport[0x1];
7287         u8         reserved_at_41[0xf];
7288         u8         vport_number[0x10];
7289
7290         u8         reserved_at_60[0x20];
7291
7292         u8         table_type[0x8];
7293         u8         reserved_at_88[0x18];
7294
7295         u8         reserved_at_a0[0x8];
7296         u8         table_id[0x18];
7297
7298         u8         reserved_at_c0[0x40];
7299
7300         u8         flow_index[0x20];
7301
7302         u8         reserved_at_120[0xe0];
7303 };
7304
7305 struct mlx5_ifc_dealloc_xrcd_out_bits {
7306         u8         status[0x8];
7307         u8         reserved_at_8[0x18];
7308
7309         u8         syndrome[0x20];
7310
7311         u8         reserved_at_40[0x40];
7312 };
7313
7314 struct mlx5_ifc_dealloc_xrcd_in_bits {
7315         u8         opcode[0x10];
7316         u8         uid[0x10];
7317
7318         u8         reserved_at_20[0x10];
7319         u8         op_mod[0x10];
7320
7321         u8         reserved_at_40[0x8];
7322         u8         xrcd[0x18];
7323
7324         u8         reserved_at_60[0x20];
7325 };
7326
7327 struct mlx5_ifc_dealloc_uar_out_bits {
7328         u8         status[0x8];
7329         u8         reserved_at_8[0x18];
7330
7331         u8         syndrome[0x20];
7332
7333         u8         reserved_at_40[0x40];
7334 };
7335
7336 struct mlx5_ifc_dealloc_uar_in_bits {
7337         u8         opcode[0x10];
7338         u8         reserved_at_10[0x10];
7339
7340         u8         reserved_at_20[0x10];
7341         u8         op_mod[0x10];
7342
7343         u8         reserved_at_40[0x8];
7344         u8         uar[0x18];
7345
7346         u8         reserved_at_60[0x20];
7347 };
7348
7349 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7350         u8         status[0x8];
7351         u8         reserved_at_8[0x18];
7352
7353         u8         syndrome[0x20];
7354
7355         u8         reserved_at_40[0x40];
7356 };
7357
7358 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7359         u8         opcode[0x10];
7360         u8         uid[0x10];
7361
7362         u8         reserved_at_20[0x10];
7363         u8         op_mod[0x10];
7364
7365         u8         reserved_at_40[0x8];
7366         u8         transport_domain[0x18];
7367
7368         u8         reserved_at_60[0x20];
7369 };
7370
7371 struct mlx5_ifc_dealloc_q_counter_out_bits {
7372         u8         status[0x8];
7373         u8         reserved_at_8[0x18];
7374
7375         u8         syndrome[0x20];
7376
7377         u8         reserved_at_40[0x40];
7378 };
7379
7380 struct mlx5_ifc_dealloc_q_counter_in_bits {
7381         u8         opcode[0x10];
7382         u8         reserved_at_10[0x10];
7383
7384         u8         reserved_at_20[0x10];
7385         u8         op_mod[0x10];
7386
7387         u8         reserved_at_40[0x18];
7388         u8         counter_set_id[0x8];
7389
7390         u8         reserved_at_60[0x20];
7391 };
7392
7393 struct mlx5_ifc_dealloc_pd_out_bits {
7394         u8         status[0x8];
7395         u8         reserved_at_8[0x18];
7396
7397         u8         syndrome[0x20];
7398
7399         u8         reserved_at_40[0x40];
7400 };
7401
7402 struct mlx5_ifc_dealloc_pd_in_bits {
7403         u8         opcode[0x10];
7404         u8         uid[0x10];
7405
7406         u8         reserved_at_20[0x10];
7407         u8         op_mod[0x10];
7408
7409         u8         reserved_at_40[0x8];
7410         u8         pd[0x18];
7411
7412         u8         reserved_at_60[0x20];
7413 };
7414
7415 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7416         u8         status[0x8];
7417         u8         reserved_at_8[0x18];
7418
7419         u8         syndrome[0x20];
7420
7421         u8         reserved_at_40[0x40];
7422 };
7423
7424 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7425         u8         opcode[0x10];
7426         u8         reserved_at_10[0x10];
7427
7428         u8         reserved_at_20[0x10];
7429         u8         op_mod[0x10];
7430
7431         u8         flow_counter_id[0x20];
7432
7433         u8         reserved_at_60[0x20];
7434 };
7435
7436 struct mlx5_ifc_create_xrq_out_bits {
7437         u8         status[0x8];
7438         u8         reserved_at_8[0x18];
7439
7440         u8         syndrome[0x20];
7441
7442         u8         reserved_at_40[0x8];
7443         u8         xrqn[0x18];
7444
7445         u8         reserved_at_60[0x20];
7446 };
7447
7448 struct mlx5_ifc_create_xrq_in_bits {
7449         u8         opcode[0x10];
7450         u8         uid[0x10];
7451
7452         u8         reserved_at_20[0x10];
7453         u8         op_mod[0x10];
7454
7455         u8         reserved_at_40[0x40];
7456
7457         struct mlx5_ifc_xrqc_bits xrq_context;
7458 };
7459
7460 struct mlx5_ifc_create_xrc_srq_out_bits {
7461         u8         status[0x8];
7462         u8         reserved_at_8[0x18];
7463
7464         u8         syndrome[0x20];
7465
7466         u8         reserved_at_40[0x8];
7467         u8         xrc_srqn[0x18];
7468
7469         u8         reserved_at_60[0x20];
7470 };
7471
7472 struct mlx5_ifc_create_xrc_srq_in_bits {
7473         u8         opcode[0x10];
7474         u8         uid[0x10];
7475
7476         u8         reserved_at_20[0x10];
7477         u8         op_mod[0x10];
7478
7479         u8         reserved_at_40[0x40];
7480
7481         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7482
7483         u8         reserved_at_280[0x60];
7484
7485         u8         xrc_srq_umem_valid[0x1];
7486         u8         reserved_at_2e1[0x1f];
7487
7488         u8         reserved_at_300[0x580];
7489
7490         u8         pas[][0x40];
7491 };
7492
7493 struct mlx5_ifc_create_tis_out_bits {
7494         u8         status[0x8];
7495         u8         reserved_at_8[0x18];
7496
7497         u8         syndrome[0x20];
7498
7499         u8         reserved_at_40[0x8];
7500         u8         tisn[0x18];
7501
7502         u8         reserved_at_60[0x20];
7503 };
7504
7505 struct mlx5_ifc_create_tis_in_bits {
7506         u8         opcode[0x10];
7507         u8         uid[0x10];
7508
7509         u8         reserved_at_20[0x10];
7510         u8         op_mod[0x10];
7511
7512         u8         reserved_at_40[0xc0];
7513
7514         struct mlx5_ifc_tisc_bits ctx;
7515 };
7516
7517 struct mlx5_ifc_create_tir_out_bits {
7518         u8         status[0x8];
7519         u8         icm_address_63_40[0x18];
7520
7521         u8         syndrome[0x20];
7522
7523         u8         icm_address_39_32[0x8];
7524         u8         tirn[0x18];
7525
7526         u8         icm_address_31_0[0x20];
7527 };
7528
7529 struct mlx5_ifc_create_tir_in_bits {
7530         u8         opcode[0x10];
7531         u8         uid[0x10];
7532
7533         u8         reserved_at_20[0x10];
7534         u8         op_mod[0x10];
7535
7536         u8         reserved_at_40[0xc0];
7537
7538         struct mlx5_ifc_tirc_bits ctx;
7539 };
7540
7541 struct mlx5_ifc_create_srq_out_bits {
7542         u8         status[0x8];
7543         u8         reserved_at_8[0x18];
7544
7545         u8         syndrome[0x20];
7546
7547         u8         reserved_at_40[0x8];
7548         u8         srqn[0x18];
7549
7550         u8         reserved_at_60[0x20];
7551 };
7552
7553 struct mlx5_ifc_create_srq_in_bits {
7554         u8         opcode[0x10];
7555         u8         uid[0x10];
7556
7557         u8         reserved_at_20[0x10];
7558         u8         op_mod[0x10];
7559
7560         u8         reserved_at_40[0x40];
7561
7562         struct mlx5_ifc_srqc_bits srq_context_entry;
7563
7564         u8         reserved_at_280[0x600];
7565
7566         u8         pas[][0x40];
7567 };
7568
7569 struct mlx5_ifc_create_sq_out_bits {
7570         u8         status[0x8];
7571         u8         reserved_at_8[0x18];
7572
7573         u8         syndrome[0x20];
7574
7575         u8         reserved_at_40[0x8];
7576         u8         sqn[0x18];
7577
7578         u8         reserved_at_60[0x20];
7579 };
7580
7581 struct mlx5_ifc_create_sq_in_bits {
7582         u8         opcode[0x10];
7583         u8         uid[0x10];
7584
7585         u8         reserved_at_20[0x10];
7586         u8         op_mod[0x10];
7587
7588         u8         reserved_at_40[0xc0];
7589
7590         struct mlx5_ifc_sqc_bits ctx;
7591 };
7592
7593 struct mlx5_ifc_create_scheduling_element_out_bits {
7594         u8         status[0x8];
7595         u8         reserved_at_8[0x18];
7596
7597         u8         syndrome[0x20];
7598
7599         u8         reserved_at_40[0x40];
7600
7601         u8         scheduling_element_id[0x20];
7602
7603         u8         reserved_at_a0[0x160];
7604 };
7605
7606 struct mlx5_ifc_create_scheduling_element_in_bits {
7607         u8         opcode[0x10];
7608         u8         reserved_at_10[0x10];
7609
7610         u8         reserved_at_20[0x10];
7611         u8         op_mod[0x10];
7612
7613         u8         scheduling_hierarchy[0x8];
7614         u8         reserved_at_48[0x18];
7615
7616         u8         reserved_at_60[0xa0];
7617
7618         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7619
7620         u8         reserved_at_300[0x100];
7621 };
7622
7623 struct mlx5_ifc_create_rqt_out_bits {
7624         u8         status[0x8];
7625         u8         reserved_at_8[0x18];
7626
7627         u8         syndrome[0x20];
7628
7629         u8         reserved_at_40[0x8];
7630         u8         rqtn[0x18];
7631
7632         u8         reserved_at_60[0x20];
7633 };
7634
7635 struct mlx5_ifc_create_rqt_in_bits {
7636         u8         opcode[0x10];
7637         u8         uid[0x10];
7638
7639         u8         reserved_at_20[0x10];
7640         u8         op_mod[0x10];
7641
7642         u8         reserved_at_40[0xc0];
7643
7644         struct mlx5_ifc_rqtc_bits rqt_context;
7645 };
7646
7647 struct mlx5_ifc_create_rq_out_bits {
7648         u8         status[0x8];
7649         u8         reserved_at_8[0x18];
7650
7651         u8         syndrome[0x20];
7652
7653         u8         reserved_at_40[0x8];
7654         u8         rqn[0x18];
7655
7656         u8         reserved_at_60[0x20];
7657 };
7658
7659 struct mlx5_ifc_create_rq_in_bits {
7660         u8         opcode[0x10];
7661         u8         uid[0x10];
7662
7663         u8         reserved_at_20[0x10];
7664         u8         op_mod[0x10];
7665
7666         u8         reserved_at_40[0xc0];
7667
7668         struct mlx5_ifc_rqc_bits ctx;
7669 };
7670
7671 struct mlx5_ifc_create_rmp_out_bits {
7672         u8         status[0x8];
7673         u8         reserved_at_8[0x18];
7674
7675         u8         syndrome[0x20];
7676
7677         u8         reserved_at_40[0x8];
7678         u8         rmpn[0x18];
7679
7680         u8         reserved_at_60[0x20];
7681 };
7682
7683 struct mlx5_ifc_create_rmp_in_bits {
7684         u8         opcode[0x10];
7685         u8         uid[0x10];
7686
7687         u8         reserved_at_20[0x10];
7688         u8         op_mod[0x10];
7689
7690         u8         reserved_at_40[0xc0];
7691
7692         struct mlx5_ifc_rmpc_bits ctx;
7693 };
7694
7695 struct mlx5_ifc_create_qp_out_bits {
7696         u8         status[0x8];
7697         u8         reserved_at_8[0x18];
7698
7699         u8         syndrome[0x20];
7700
7701         u8         reserved_at_40[0x8];
7702         u8         qpn[0x18];
7703
7704         u8         ece[0x20];
7705 };
7706
7707 struct mlx5_ifc_create_qp_in_bits {
7708         u8         opcode[0x10];
7709         u8         uid[0x10];
7710
7711         u8         reserved_at_20[0x10];
7712         u8         op_mod[0x10];
7713
7714         u8         reserved_at_40[0x40];
7715
7716         u8         opt_param_mask[0x20];
7717
7718         u8         ece[0x20];
7719
7720         struct mlx5_ifc_qpc_bits qpc;
7721
7722         u8         reserved_at_800[0x60];
7723
7724         u8         wq_umem_valid[0x1];
7725         u8         reserved_at_861[0x1f];
7726
7727         u8         pas[][0x40];
7728 };
7729
7730 struct mlx5_ifc_create_psv_out_bits {
7731         u8         status[0x8];
7732         u8         reserved_at_8[0x18];
7733
7734         u8         syndrome[0x20];
7735
7736         u8         reserved_at_40[0x40];
7737
7738         u8         reserved_at_80[0x8];
7739         u8         psv0_index[0x18];
7740
7741         u8         reserved_at_a0[0x8];
7742         u8         psv1_index[0x18];
7743
7744         u8         reserved_at_c0[0x8];
7745         u8         psv2_index[0x18];
7746
7747         u8         reserved_at_e0[0x8];
7748         u8         psv3_index[0x18];
7749 };
7750
7751 struct mlx5_ifc_create_psv_in_bits {
7752         u8         opcode[0x10];
7753         u8         reserved_at_10[0x10];
7754
7755         u8         reserved_at_20[0x10];
7756         u8         op_mod[0x10];
7757
7758         u8         num_psv[0x4];
7759         u8         reserved_at_44[0x4];
7760         u8         pd[0x18];
7761
7762         u8         reserved_at_60[0x20];
7763 };
7764
7765 struct mlx5_ifc_create_mkey_out_bits {
7766         u8         status[0x8];
7767         u8         reserved_at_8[0x18];
7768
7769         u8         syndrome[0x20];
7770
7771         u8         reserved_at_40[0x8];
7772         u8         mkey_index[0x18];
7773
7774         u8         reserved_at_60[0x20];
7775 };
7776
7777 struct mlx5_ifc_create_mkey_in_bits {
7778         u8         opcode[0x10];
7779         u8         reserved_at_10[0x10];
7780
7781         u8         reserved_at_20[0x10];
7782         u8         op_mod[0x10];
7783
7784         u8         reserved_at_40[0x20];
7785
7786         u8         pg_access[0x1];
7787         u8         mkey_umem_valid[0x1];
7788         u8         reserved_at_62[0x1e];
7789
7790         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7791
7792         u8         reserved_at_280[0x80];
7793
7794         u8         translations_octword_actual_size[0x20];
7795
7796         u8         reserved_at_320[0x560];
7797
7798         u8         klm_pas_mtt[][0x20];
7799 };
7800
7801 enum {
7802         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7803         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7804         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7805         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7806         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7807         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7808         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7809 };
7810
7811 struct mlx5_ifc_create_flow_table_out_bits {
7812         u8         status[0x8];
7813         u8         icm_address_63_40[0x18];
7814
7815         u8         syndrome[0x20];
7816
7817         u8         icm_address_39_32[0x8];
7818         u8         table_id[0x18];
7819
7820         u8         icm_address_31_0[0x20];
7821 };
7822
7823 struct mlx5_ifc_create_flow_table_in_bits {
7824         u8         opcode[0x10];
7825         u8         reserved_at_10[0x10];
7826
7827         u8         reserved_at_20[0x10];
7828         u8         op_mod[0x10];
7829
7830         u8         other_vport[0x1];
7831         u8         reserved_at_41[0xf];
7832         u8         vport_number[0x10];
7833
7834         u8         reserved_at_60[0x20];
7835
7836         u8         table_type[0x8];
7837         u8         reserved_at_88[0x18];
7838
7839         u8         reserved_at_a0[0x20];
7840
7841         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7842 };
7843
7844 struct mlx5_ifc_create_flow_group_out_bits {
7845         u8         status[0x8];
7846         u8         reserved_at_8[0x18];
7847
7848         u8         syndrome[0x20];
7849
7850         u8         reserved_at_40[0x8];
7851         u8         group_id[0x18];
7852
7853         u8         reserved_at_60[0x20];
7854 };
7855
7856 enum {
7857         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7858         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7859         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7860         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7861 };
7862
7863 struct mlx5_ifc_create_flow_group_in_bits {
7864         u8         opcode[0x10];
7865         u8         reserved_at_10[0x10];
7866
7867         u8         reserved_at_20[0x10];
7868         u8         op_mod[0x10];
7869
7870         u8         other_vport[0x1];
7871         u8         reserved_at_41[0xf];
7872         u8         vport_number[0x10];
7873
7874         u8         reserved_at_60[0x20];
7875
7876         u8         table_type[0x8];
7877         u8         reserved_at_88[0x18];
7878
7879         u8         reserved_at_a0[0x8];
7880         u8         table_id[0x18];
7881
7882         u8         source_eswitch_owner_vhca_id_valid[0x1];
7883
7884         u8         reserved_at_c1[0x1f];
7885
7886         u8         start_flow_index[0x20];
7887
7888         u8         reserved_at_100[0x20];
7889
7890         u8         end_flow_index[0x20];
7891
7892         u8         reserved_at_140[0xa0];
7893
7894         u8         reserved_at_1e0[0x18];
7895         u8         match_criteria_enable[0x8];
7896
7897         struct mlx5_ifc_fte_match_param_bits match_criteria;
7898
7899         u8         reserved_at_1200[0xe00];
7900 };
7901
7902 struct mlx5_ifc_create_eq_out_bits {
7903         u8         status[0x8];
7904         u8         reserved_at_8[0x18];
7905
7906         u8         syndrome[0x20];
7907
7908         u8         reserved_at_40[0x18];
7909         u8         eq_number[0x8];
7910
7911         u8         reserved_at_60[0x20];
7912 };
7913
7914 struct mlx5_ifc_create_eq_in_bits {
7915         u8         opcode[0x10];
7916         u8         uid[0x10];
7917
7918         u8         reserved_at_20[0x10];
7919         u8         op_mod[0x10];
7920
7921         u8         reserved_at_40[0x40];
7922
7923         struct mlx5_ifc_eqc_bits eq_context_entry;
7924
7925         u8         reserved_at_280[0x40];
7926
7927         u8         event_bitmask[4][0x40];
7928
7929         u8         reserved_at_3c0[0x4c0];
7930
7931         u8         pas[][0x40];
7932 };
7933
7934 struct mlx5_ifc_create_dct_out_bits {
7935         u8         status[0x8];
7936         u8         reserved_at_8[0x18];
7937
7938         u8         syndrome[0x20];
7939
7940         u8         reserved_at_40[0x8];
7941         u8         dctn[0x18];
7942
7943         u8         reserved_at_60[0x20];
7944 };
7945
7946 struct mlx5_ifc_create_dct_in_bits {
7947         u8         opcode[0x10];
7948         u8         uid[0x10];
7949
7950         u8         reserved_at_20[0x10];
7951         u8         op_mod[0x10];
7952
7953         u8         reserved_at_40[0x40];
7954
7955         struct mlx5_ifc_dctc_bits dct_context_entry;
7956
7957         u8         reserved_at_280[0x180];
7958 };
7959
7960 struct mlx5_ifc_create_cq_out_bits {
7961         u8         status[0x8];
7962         u8         reserved_at_8[0x18];
7963
7964         u8         syndrome[0x20];
7965
7966         u8         reserved_at_40[0x8];
7967         u8         cqn[0x18];
7968
7969         u8         reserved_at_60[0x20];
7970 };
7971
7972 struct mlx5_ifc_create_cq_in_bits {
7973         u8         opcode[0x10];
7974         u8         uid[0x10];
7975
7976         u8         reserved_at_20[0x10];
7977         u8         op_mod[0x10];
7978
7979         u8         reserved_at_40[0x40];
7980
7981         struct mlx5_ifc_cqc_bits cq_context;
7982
7983         u8         reserved_at_280[0x60];
7984
7985         u8         cq_umem_valid[0x1];
7986         u8         reserved_at_2e1[0x59f];
7987
7988         u8         pas[][0x40];
7989 };
7990
7991 struct mlx5_ifc_config_int_moderation_out_bits {
7992         u8         status[0x8];
7993         u8         reserved_at_8[0x18];
7994
7995         u8         syndrome[0x20];
7996
7997         u8         reserved_at_40[0x4];
7998         u8         min_delay[0xc];
7999         u8         int_vector[0x10];
8000
8001         u8         reserved_at_60[0x20];
8002 };
8003
8004 enum {
8005         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8006         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8007 };
8008
8009 struct mlx5_ifc_config_int_moderation_in_bits {
8010         u8         opcode[0x10];
8011         u8         reserved_at_10[0x10];
8012
8013         u8         reserved_at_20[0x10];
8014         u8         op_mod[0x10];
8015
8016         u8         reserved_at_40[0x4];
8017         u8         min_delay[0xc];
8018         u8         int_vector[0x10];
8019
8020         u8         reserved_at_60[0x20];
8021 };
8022
8023 struct mlx5_ifc_attach_to_mcg_out_bits {
8024         u8         status[0x8];
8025         u8         reserved_at_8[0x18];
8026
8027         u8         syndrome[0x20];
8028
8029         u8         reserved_at_40[0x40];
8030 };
8031
8032 struct mlx5_ifc_attach_to_mcg_in_bits {
8033         u8         opcode[0x10];
8034         u8         uid[0x10];
8035
8036         u8         reserved_at_20[0x10];
8037         u8         op_mod[0x10];
8038
8039         u8         reserved_at_40[0x8];
8040         u8         qpn[0x18];
8041
8042         u8         reserved_at_60[0x20];
8043
8044         u8         multicast_gid[16][0x8];
8045 };
8046
8047 struct mlx5_ifc_arm_xrq_out_bits {
8048         u8         status[0x8];
8049         u8         reserved_at_8[0x18];
8050
8051         u8         syndrome[0x20];
8052
8053         u8         reserved_at_40[0x40];
8054 };
8055
8056 struct mlx5_ifc_arm_xrq_in_bits {
8057         u8         opcode[0x10];
8058         u8         reserved_at_10[0x10];
8059
8060         u8         reserved_at_20[0x10];
8061         u8         op_mod[0x10];
8062
8063         u8         reserved_at_40[0x8];
8064         u8         xrqn[0x18];
8065
8066         u8         reserved_at_60[0x10];
8067         u8         lwm[0x10];
8068 };
8069
8070 struct mlx5_ifc_arm_xrc_srq_out_bits {
8071         u8         status[0x8];
8072         u8         reserved_at_8[0x18];
8073
8074         u8         syndrome[0x20];
8075
8076         u8         reserved_at_40[0x40];
8077 };
8078
8079 enum {
8080         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8081 };
8082
8083 struct mlx5_ifc_arm_xrc_srq_in_bits {
8084         u8         opcode[0x10];
8085         u8         uid[0x10];
8086
8087         u8         reserved_at_20[0x10];
8088         u8         op_mod[0x10];
8089
8090         u8         reserved_at_40[0x8];
8091         u8         xrc_srqn[0x18];
8092
8093         u8         reserved_at_60[0x10];
8094         u8         lwm[0x10];
8095 };
8096
8097 struct mlx5_ifc_arm_rq_out_bits {
8098         u8         status[0x8];
8099         u8         reserved_at_8[0x18];
8100
8101         u8         syndrome[0x20];
8102
8103         u8         reserved_at_40[0x40];
8104 };
8105
8106 enum {
8107         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8108         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8109 };
8110
8111 struct mlx5_ifc_arm_rq_in_bits {
8112         u8         opcode[0x10];
8113         u8         uid[0x10];
8114
8115         u8         reserved_at_20[0x10];
8116         u8         op_mod[0x10];
8117
8118         u8         reserved_at_40[0x8];
8119         u8         srq_number[0x18];
8120
8121         u8         reserved_at_60[0x10];
8122         u8         lwm[0x10];
8123 };
8124
8125 struct mlx5_ifc_arm_dct_out_bits {
8126         u8         status[0x8];
8127         u8         reserved_at_8[0x18];
8128
8129         u8         syndrome[0x20];
8130
8131         u8         reserved_at_40[0x40];
8132 };
8133
8134 struct mlx5_ifc_arm_dct_in_bits {
8135         u8         opcode[0x10];
8136         u8         reserved_at_10[0x10];
8137
8138         u8         reserved_at_20[0x10];
8139         u8         op_mod[0x10];
8140
8141         u8         reserved_at_40[0x8];
8142         u8         dct_number[0x18];
8143
8144         u8         reserved_at_60[0x20];
8145 };
8146
8147 struct mlx5_ifc_alloc_xrcd_out_bits {
8148         u8         status[0x8];
8149         u8         reserved_at_8[0x18];
8150
8151         u8         syndrome[0x20];
8152
8153         u8         reserved_at_40[0x8];
8154         u8         xrcd[0x18];
8155
8156         u8         reserved_at_60[0x20];
8157 };
8158
8159 struct mlx5_ifc_alloc_xrcd_in_bits {
8160         u8         opcode[0x10];
8161         u8         uid[0x10];
8162
8163         u8         reserved_at_20[0x10];
8164         u8         op_mod[0x10];
8165
8166         u8         reserved_at_40[0x40];
8167 };
8168
8169 struct mlx5_ifc_alloc_uar_out_bits {
8170         u8         status[0x8];
8171         u8         reserved_at_8[0x18];
8172
8173         u8         syndrome[0x20];
8174
8175         u8         reserved_at_40[0x8];
8176         u8         uar[0x18];
8177
8178         u8         reserved_at_60[0x20];
8179 };
8180
8181 struct mlx5_ifc_alloc_uar_in_bits {
8182         u8         opcode[0x10];
8183         u8         reserved_at_10[0x10];
8184
8185         u8         reserved_at_20[0x10];
8186         u8         op_mod[0x10];
8187
8188         u8         reserved_at_40[0x40];
8189 };
8190
8191 struct mlx5_ifc_alloc_transport_domain_out_bits {
8192         u8         status[0x8];
8193         u8         reserved_at_8[0x18];
8194
8195         u8         syndrome[0x20];
8196
8197         u8         reserved_at_40[0x8];
8198         u8         transport_domain[0x18];
8199
8200         u8         reserved_at_60[0x20];
8201 };
8202
8203 struct mlx5_ifc_alloc_transport_domain_in_bits {
8204         u8         opcode[0x10];
8205         u8         uid[0x10];
8206
8207         u8         reserved_at_20[0x10];
8208         u8         op_mod[0x10];
8209
8210         u8         reserved_at_40[0x40];
8211 };
8212
8213 struct mlx5_ifc_alloc_q_counter_out_bits {
8214         u8         status[0x8];
8215         u8         reserved_at_8[0x18];
8216
8217         u8         syndrome[0x20];
8218
8219         u8         reserved_at_40[0x18];
8220         u8         counter_set_id[0x8];
8221
8222         u8         reserved_at_60[0x20];
8223 };
8224
8225 struct mlx5_ifc_alloc_q_counter_in_bits {
8226         u8         opcode[0x10];
8227         u8         uid[0x10];
8228
8229         u8         reserved_at_20[0x10];
8230         u8         op_mod[0x10];
8231
8232         u8         reserved_at_40[0x40];
8233 };
8234
8235 struct mlx5_ifc_alloc_pd_out_bits {
8236         u8         status[0x8];
8237         u8         reserved_at_8[0x18];
8238
8239         u8         syndrome[0x20];
8240
8241         u8         reserved_at_40[0x8];
8242         u8         pd[0x18];
8243
8244         u8         reserved_at_60[0x20];
8245 };
8246
8247 struct mlx5_ifc_alloc_pd_in_bits {
8248         u8         opcode[0x10];
8249         u8         uid[0x10];
8250
8251         u8         reserved_at_20[0x10];
8252         u8         op_mod[0x10];
8253
8254         u8         reserved_at_40[0x40];
8255 };
8256
8257 struct mlx5_ifc_alloc_flow_counter_out_bits {
8258         u8         status[0x8];
8259         u8         reserved_at_8[0x18];
8260
8261         u8         syndrome[0x20];
8262
8263         u8         flow_counter_id[0x20];
8264
8265         u8         reserved_at_60[0x20];
8266 };
8267
8268 struct mlx5_ifc_alloc_flow_counter_in_bits {
8269         u8         opcode[0x10];
8270         u8         reserved_at_10[0x10];
8271
8272         u8         reserved_at_20[0x10];
8273         u8         op_mod[0x10];
8274
8275         u8         reserved_at_40[0x38];
8276         u8         flow_counter_bulk[0x8];
8277 };
8278
8279 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8280         u8         status[0x8];
8281         u8         reserved_at_8[0x18];
8282
8283         u8         syndrome[0x20];
8284
8285         u8         reserved_at_40[0x40];
8286 };
8287
8288 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8289         u8         opcode[0x10];
8290         u8         reserved_at_10[0x10];
8291
8292         u8         reserved_at_20[0x10];
8293         u8         op_mod[0x10];
8294
8295         u8         reserved_at_40[0x20];
8296
8297         u8         reserved_at_60[0x10];
8298         u8         vxlan_udp_port[0x10];
8299 };
8300
8301 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8302         u8         status[0x8];
8303         u8         reserved_at_8[0x18];
8304
8305         u8         syndrome[0x20];
8306
8307         u8         reserved_at_40[0x40];
8308 };
8309
8310 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8311         u8         rate_limit[0x20];
8312
8313         u8         burst_upper_bound[0x20];
8314
8315         u8         reserved_at_40[0x10];
8316         u8         typical_packet_size[0x10];
8317
8318         u8         reserved_at_60[0x120];
8319 };
8320
8321 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8322         u8         opcode[0x10];
8323         u8         uid[0x10];
8324
8325         u8         reserved_at_20[0x10];
8326         u8         op_mod[0x10];
8327
8328         u8         reserved_at_40[0x10];
8329         u8         rate_limit_index[0x10];
8330
8331         u8         reserved_at_60[0x20];
8332
8333         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8334 };
8335
8336 struct mlx5_ifc_access_register_out_bits {
8337         u8         status[0x8];
8338         u8         reserved_at_8[0x18];
8339
8340         u8         syndrome[0x20];
8341
8342         u8         reserved_at_40[0x40];
8343
8344         u8         register_data[][0x20];
8345 };
8346
8347 enum {
8348         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8349         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8350 };
8351
8352 struct mlx5_ifc_access_register_in_bits {
8353         u8         opcode[0x10];
8354         u8         reserved_at_10[0x10];
8355
8356         u8         reserved_at_20[0x10];
8357         u8         op_mod[0x10];
8358
8359         u8         reserved_at_40[0x10];
8360         u8         register_id[0x10];
8361
8362         u8         argument[0x20];
8363
8364         u8         register_data[][0x20];
8365 };
8366
8367 struct mlx5_ifc_sltp_reg_bits {
8368         u8         status[0x4];
8369         u8         version[0x4];
8370         u8         local_port[0x8];
8371         u8         pnat[0x2];
8372         u8         reserved_at_12[0x2];
8373         u8         lane[0x4];
8374         u8         reserved_at_18[0x8];
8375
8376         u8         reserved_at_20[0x20];
8377
8378         u8         reserved_at_40[0x7];
8379         u8         polarity[0x1];
8380         u8         ob_tap0[0x8];
8381         u8         ob_tap1[0x8];
8382         u8         ob_tap2[0x8];
8383
8384         u8         reserved_at_60[0xc];
8385         u8         ob_preemp_mode[0x4];
8386         u8         ob_reg[0x8];
8387         u8         ob_bias[0x8];
8388
8389         u8         reserved_at_80[0x20];
8390 };
8391
8392 struct mlx5_ifc_slrg_reg_bits {
8393         u8         status[0x4];
8394         u8         version[0x4];
8395         u8         local_port[0x8];
8396         u8         pnat[0x2];
8397         u8         reserved_at_12[0x2];
8398         u8         lane[0x4];
8399         u8         reserved_at_18[0x8];
8400
8401         u8         time_to_link_up[0x10];
8402         u8         reserved_at_30[0xc];
8403         u8         grade_lane_speed[0x4];
8404
8405         u8         grade_version[0x8];
8406         u8         grade[0x18];
8407
8408         u8         reserved_at_60[0x4];
8409         u8         height_grade_type[0x4];
8410         u8         height_grade[0x18];
8411
8412         u8         height_dz[0x10];
8413         u8         height_dv[0x10];
8414
8415         u8         reserved_at_a0[0x10];
8416         u8         height_sigma[0x10];
8417
8418         u8         reserved_at_c0[0x20];
8419
8420         u8         reserved_at_e0[0x4];
8421         u8         phase_grade_type[0x4];
8422         u8         phase_grade[0x18];
8423
8424         u8         reserved_at_100[0x8];
8425         u8         phase_eo_pos[0x8];
8426         u8         reserved_at_110[0x8];
8427         u8         phase_eo_neg[0x8];
8428
8429         u8         ffe_set_tested[0x10];
8430         u8         test_errors_per_lane[0x10];
8431 };
8432
8433 struct mlx5_ifc_pvlc_reg_bits {
8434         u8         reserved_at_0[0x8];
8435         u8         local_port[0x8];
8436         u8         reserved_at_10[0x10];
8437
8438         u8         reserved_at_20[0x1c];
8439         u8         vl_hw_cap[0x4];
8440
8441         u8         reserved_at_40[0x1c];
8442         u8         vl_admin[0x4];
8443
8444         u8         reserved_at_60[0x1c];
8445         u8         vl_operational[0x4];
8446 };
8447
8448 struct mlx5_ifc_pude_reg_bits {
8449         u8         swid[0x8];
8450         u8         local_port[0x8];
8451         u8         reserved_at_10[0x4];
8452         u8         admin_status[0x4];
8453         u8         reserved_at_18[0x4];
8454         u8         oper_status[0x4];
8455
8456         u8         reserved_at_20[0x60];
8457 };
8458
8459 struct mlx5_ifc_ptys_reg_bits {
8460         u8         reserved_at_0[0x1];
8461         u8         an_disable_admin[0x1];
8462         u8         an_disable_cap[0x1];
8463         u8         reserved_at_3[0x5];
8464         u8         local_port[0x8];
8465         u8         reserved_at_10[0xd];
8466         u8         proto_mask[0x3];
8467
8468         u8         an_status[0x4];
8469         u8         reserved_at_24[0xc];
8470         u8         data_rate_oper[0x10];
8471
8472         u8         ext_eth_proto_capability[0x20];
8473
8474         u8         eth_proto_capability[0x20];
8475
8476         u8         ib_link_width_capability[0x10];
8477         u8         ib_proto_capability[0x10];
8478
8479         u8         ext_eth_proto_admin[0x20];
8480
8481         u8         eth_proto_admin[0x20];
8482
8483         u8         ib_link_width_admin[0x10];
8484         u8         ib_proto_admin[0x10];
8485
8486         u8         ext_eth_proto_oper[0x20];
8487
8488         u8         eth_proto_oper[0x20];
8489
8490         u8         ib_link_width_oper[0x10];
8491         u8         ib_proto_oper[0x10];
8492
8493         u8         reserved_at_160[0x1c];
8494         u8         connector_type[0x4];
8495
8496         u8         eth_proto_lp_advertise[0x20];
8497
8498         u8         reserved_at_1a0[0x60];
8499 };
8500
8501 struct mlx5_ifc_mlcr_reg_bits {
8502         u8         reserved_at_0[0x8];
8503         u8         local_port[0x8];
8504         u8         reserved_at_10[0x20];
8505
8506         u8         beacon_duration[0x10];
8507         u8         reserved_at_40[0x10];
8508
8509         u8         beacon_remain[0x10];
8510 };
8511
8512 struct mlx5_ifc_ptas_reg_bits {
8513         u8         reserved_at_0[0x20];
8514
8515         u8         algorithm_options[0x10];
8516         u8         reserved_at_30[0x4];
8517         u8         repetitions_mode[0x4];
8518         u8         num_of_repetitions[0x8];
8519
8520         u8         grade_version[0x8];
8521         u8         height_grade_type[0x4];
8522         u8         phase_grade_type[0x4];
8523         u8         height_grade_weight[0x8];
8524         u8         phase_grade_weight[0x8];
8525
8526         u8         gisim_measure_bits[0x10];
8527         u8         adaptive_tap_measure_bits[0x10];
8528
8529         u8         ber_bath_high_error_threshold[0x10];
8530         u8         ber_bath_mid_error_threshold[0x10];
8531
8532         u8         ber_bath_low_error_threshold[0x10];
8533         u8         one_ratio_high_threshold[0x10];
8534
8535         u8         one_ratio_high_mid_threshold[0x10];
8536         u8         one_ratio_low_mid_threshold[0x10];
8537
8538         u8         one_ratio_low_threshold[0x10];
8539         u8         ndeo_error_threshold[0x10];
8540
8541         u8         mixer_offset_step_size[0x10];
8542         u8         reserved_at_110[0x8];
8543         u8         mix90_phase_for_voltage_bath[0x8];
8544
8545         u8         mixer_offset_start[0x10];
8546         u8         mixer_offset_end[0x10];
8547
8548         u8         reserved_at_140[0x15];
8549         u8         ber_test_time[0xb];
8550 };
8551
8552 struct mlx5_ifc_pspa_reg_bits {
8553         u8         swid[0x8];
8554         u8         local_port[0x8];
8555         u8         sub_port[0x8];
8556         u8         reserved_at_18[0x8];
8557
8558         u8         reserved_at_20[0x20];
8559 };
8560
8561 struct mlx5_ifc_pqdr_reg_bits {
8562         u8         reserved_at_0[0x8];
8563         u8         local_port[0x8];
8564         u8         reserved_at_10[0x5];
8565         u8         prio[0x3];
8566         u8         reserved_at_18[0x6];
8567         u8         mode[0x2];
8568
8569         u8         reserved_at_20[0x20];
8570
8571         u8         reserved_at_40[0x10];
8572         u8         min_threshold[0x10];
8573
8574         u8         reserved_at_60[0x10];
8575         u8         max_threshold[0x10];
8576
8577         u8         reserved_at_80[0x10];
8578         u8         mark_probability_denominator[0x10];
8579
8580         u8         reserved_at_a0[0x60];
8581 };
8582
8583 struct mlx5_ifc_ppsc_reg_bits {
8584         u8         reserved_at_0[0x8];
8585         u8         local_port[0x8];
8586         u8         reserved_at_10[0x10];
8587
8588         u8         reserved_at_20[0x60];
8589
8590         u8         reserved_at_80[0x1c];
8591         u8         wrps_admin[0x4];
8592
8593         u8         reserved_at_a0[0x1c];
8594         u8         wrps_status[0x4];
8595
8596         u8         reserved_at_c0[0x8];
8597         u8         up_threshold[0x8];
8598         u8         reserved_at_d0[0x8];
8599         u8         down_threshold[0x8];
8600
8601         u8         reserved_at_e0[0x20];
8602
8603         u8         reserved_at_100[0x1c];
8604         u8         srps_admin[0x4];
8605
8606         u8         reserved_at_120[0x1c];
8607         u8         srps_status[0x4];
8608
8609         u8         reserved_at_140[0x40];
8610 };
8611
8612 struct mlx5_ifc_pplr_reg_bits {
8613         u8         reserved_at_0[0x8];
8614         u8         local_port[0x8];
8615         u8         reserved_at_10[0x10];
8616
8617         u8         reserved_at_20[0x8];
8618         u8         lb_cap[0x8];
8619         u8         reserved_at_30[0x8];
8620         u8         lb_en[0x8];
8621 };
8622
8623 struct mlx5_ifc_pplm_reg_bits {
8624         u8         reserved_at_0[0x8];
8625         u8         local_port[0x8];
8626         u8         reserved_at_10[0x10];
8627
8628         u8         reserved_at_20[0x20];
8629
8630         u8         port_profile_mode[0x8];
8631         u8         static_port_profile[0x8];
8632         u8         active_port_profile[0x8];
8633         u8         reserved_at_58[0x8];
8634
8635         u8         retransmission_active[0x8];
8636         u8         fec_mode_active[0x18];
8637
8638         u8         rs_fec_correction_bypass_cap[0x4];
8639         u8         reserved_at_84[0x8];
8640         u8         fec_override_cap_56g[0x4];
8641         u8         fec_override_cap_100g[0x4];
8642         u8         fec_override_cap_50g[0x4];
8643         u8         fec_override_cap_25g[0x4];
8644         u8         fec_override_cap_10g_40g[0x4];
8645
8646         u8         rs_fec_correction_bypass_admin[0x4];
8647         u8         reserved_at_a4[0x8];
8648         u8         fec_override_admin_56g[0x4];
8649         u8         fec_override_admin_100g[0x4];
8650         u8         fec_override_admin_50g[0x4];
8651         u8         fec_override_admin_25g[0x4];
8652         u8         fec_override_admin_10g_40g[0x4];
8653
8654         u8         fec_override_cap_400g_8x[0x10];
8655         u8         fec_override_cap_200g_4x[0x10];
8656
8657         u8         fec_override_cap_100g_2x[0x10];
8658         u8         fec_override_cap_50g_1x[0x10];
8659
8660         u8         fec_override_admin_400g_8x[0x10];
8661         u8         fec_override_admin_200g_4x[0x10];
8662
8663         u8         fec_override_admin_100g_2x[0x10];
8664         u8         fec_override_admin_50g_1x[0x10];
8665 };
8666
8667 struct mlx5_ifc_ppcnt_reg_bits {
8668         u8         swid[0x8];
8669         u8         local_port[0x8];
8670         u8         pnat[0x2];
8671         u8         reserved_at_12[0x8];
8672         u8         grp[0x6];
8673
8674         u8         clr[0x1];
8675         u8         reserved_at_21[0x1c];
8676         u8         prio_tc[0x3];
8677
8678         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8679 };
8680
8681 struct mlx5_ifc_mpein_reg_bits {
8682         u8         reserved_at_0[0x2];
8683         u8         depth[0x6];
8684         u8         pcie_index[0x8];
8685         u8         node[0x8];
8686         u8         reserved_at_18[0x8];
8687
8688         u8         capability_mask[0x20];
8689
8690         u8         reserved_at_40[0x8];
8691         u8         link_width_enabled[0x8];
8692         u8         link_speed_enabled[0x10];
8693
8694         u8         lane0_physical_position[0x8];
8695         u8         link_width_active[0x8];
8696         u8         link_speed_active[0x10];
8697
8698         u8         num_of_pfs[0x10];
8699         u8         num_of_vfs[0x10];
8700
8701         u8         bdf0[0x10];
8702         u8         reserved_at_b0[0x10];
8703
8704         u8         max_read_request_size[0x4];
8705         u8         max_payload_size[0x4];
8706         u8         reserved_at_c8[0x5];
8707         u8         pwr_status[0x3];
8708         u8         port_type[0x4];
8709         u8         reserved_at_d4[0xb];
8710         u8         lane_reversal[0x1];
8711
8712         u8         reserved_at_e0[0x14];
8713         u8         pci_power[0xc];
8714
8715         u8         reserved_at_100[0x20];
8716
8717         u8         device_status[0x10];
8718         u8         port_state[0x8];
8719         u8         reserved_at_138[0x8];
8720
8721         u8         reserved_at_140[0x10];
8722         u8         receiver_detect_result[0x10];
8723
8724         u8         reserved_at_160[0x20];
8725 };
8726
8727 struct mlx5_ifc_mpcnt_reg_bits {
8728         u8         reserved_at_0[0x8];
8729         u8         pcie_index[0x8];
8730         u8         reserved_at_10[0xa];
8731         u8         grp[0x6];
8732
8733         u8         clr[0x1];
8734         u8         reserved_at_21[0x1f];
8735
8736         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8737 };
8738
8739 struct mlx5_ifc_ppad_reg_bits {
8740         u8         reserved_at_0[0x3];
8741         u8         single_mac[0x1];
8742         u8         reserved_at_4[0x4];
8743         u8         local_port[0x8];
8744         u8         mac_47_32[0x10];
8745
8746         u8         mac_31_0[0x20];
8747
8748         u8         reserved_at_40[0x40];
8749 };
8750
8751 struct mlx5_ifc_pmtu_reg_bits {
8752         u8         reserved_at_0[0x8];
8753         u8         local_port[0x8];
8754         u8         reserved_at_10[0x10];
8755
8756         u8         max_mtu[0x10];
8757         u8         reserved_at_30[0x10];
8758
8759         u8         admin_mtu[0x10];
8760         u8         reserved_at_50[0x10];
8761
8762         u8         oper_mtu[0x10];
8763         u8         reserved_at_70[0x10];
8764 };
8765
8766 struct mlx5_ifc_pmpr_reg_bits {
8767         u8         reserved_at_0[0x8];
8768         u8         module[0x8];
8769         u8         reserved_at_10[0x10];
8770
8771         u8         reserved_at_20[0x18];
8772         u8         attenuation_5g[0x8];
8773
8774         u8         reserved_at_40[0x18];
8775         u8         attenuation_7g[0x8];
8776
8777         u8         reserved_at_60[0x18];
8778         u8         attenuation_12g[0x8];
8779 };
8780
8781 struct mlx5_ifc_pmpe_reg_bits {
8782         u8         reserved_at_0[0x8];
8783         u8         module[0x8];
8784         u8         reserved_at_10[0xc];
8785         u8         module_status[0x4];
8786
8787         u8         reserved_at_20[0x60];
8788 };
8789
8790 struct mlx5_ifc_pmpc_reg_bits {
8791         u8         module_state_updated[32][0x8];
8792 };
8793
8794 struct mlx5_ifc_pmlpn_reg_bits {
8795         u8         reserved_at_0[0x4];
8796         u8         mlpn_status[0x4];
8797         u8         local_port[0x8];
8798         u8         reserved_at_10[0x10];
8799
8800         u8         e[0x1];
8801         u8         reserved_at_21[0x1f];
8802 };
8803
8804 struct mlx5_ifc_pmlp_reg_bits {
8805         u8         rxtx[0x1];
8806         u8         reserved_at_1[0x7];
8807         u8         local_port[0x8];
8808         u8         reserved_at_10[0x8];
8809         u8         width[0x8];
8810
8811         u8         lane0_module_mapping[0x20];
8812
8813         u8         lane1_module_mapping[0x20];
8814
8815         u8         lane2_module_mapping[0x20];
8816
8817         u8         lane3_module_mapping[0x20];
8818
8819         u8         reserved_at_a0[0x160];
8820 };
8821
8822 struct mlx5_ifc_pmaos_reg_bits {
8823         u8         reserved_at_0[0x8];
8824         u8         module[0x8];
8825         u8         reserved_at_10[0x4];
8826         u8         admin_status[0x4];
8827         u8         reserved_at_18[0x4];
8828         u8         oper_status[0x4];
8829
8830         u8         ase[0x1];
8831         u8         ee[0x1];
8832         u8         reserved_at_22[0x1c];
8833         u8         e[0x2];
8834
8835         u8         reserved_at_40[0x40];
8836 };
8837
8838 struct mlx5_ifc_plpc_reg_bits {
8839         u8         reserved_at_0[0x4];
8840         u8         profile_id[0xc];
8841         u8         reserved_at_10[0x4];
8842         u8         proto_mask[0x4];
8843         u8         reserved_at_18[0x8];
8844
8845         u8         reserved_at_20[0x10];
8846         u8         lane_speed[0x10];
8847
8848         u8         reserved_at_40[0x17];
8849         u8         lpbf[0x1];
8850         u8         fec_mode_policy[0x8];
8851
8852         u8         retransmission_capability[0x8];
8853         u8         fec_mode_capability[0x18];
8854
8855         u8         retransmission_support_admin[0x8];
8856         u8         fec_mode_support_admin[0x18];
8857
8858         u8         retransmission_request_admin[0x8];
8859         u8         fec_mode_request_admin[0x18];
8860
8861         u8         reserved_at_c0[0x80];
8862 };
8863
8864 struct mlx5_ifc_plib_reg_bits {
8865         u8         reserved_at_0[0x8];
8866         u8         local_port[0x8];
8867         u8         reserved_at_10[0x8];
8868         u8         ib_port[0x8];
8869
8870         u8         reserved_at_20[0x60];
8871 };
8872
8873 struct mlx5_ifc_plbf_reg_bits {
8874         u8         reserved_at_0[0x8];
8875         u8         local_port[0x8];
8876         u8         reserved_at_10[0xd];
8877         u8         lbf_mode[0x3];
8878
8879         u8         reserved_at_20[0x20];
8880 };
8881
8882 struct mlx5_ifc_pipg_reg_bits {
8883         u8         reserved_at_0[0x8];
8884         u8         local_port[0x8];
8885         u8         reserved_at_10[0x10];
8886
8887         u8         dic[0x1];
8888         u8         reserved_at_21[0x19];
8889         u8         ipg[0x4];
8890         u8         reserved_at_3e[0x2];
8891 };
8892
8893 struct mlx5_ifc_pifr_reg_bits {
8894         u8         reserved_at_0[0x8];
8895         u8         local_port[0x8];
8896         u8         reserved_at_10[0x10];
8897
8898         u8         reserved_at_20[0xe0];
8899
8900         u8         port_filter[8][0x20];
8901
8902         u8         port_filter_update_en[8][0x20];
8903 };
8904
8905 struct mlx5_ifc_pfcc_reg_bits {
8906         u8         reserved_at_0[0x8];
8907         u8         local_port[0x8];
8908         u8         reserved_at_10[0xb];
8909         u8         ppan_mask_n[0x1];
8910         u8         minor_stall_mask[0x1];
8911         u8         critical_stall_mask[0x1];
8912         u8         reserved_at_1e[0x2];
8913
8914         u8         ppan[0x4];
8915         u8         reserved_at_24[0x4];
8916         u8         prio_mask_tx[0x8];
8917         u8         reserved_at_30[0x8];
8918         u8         prio_mask_rx[0x8];
8919
8920         u8         pptx[0x1];
8921         u8         aptx[0x1];
8922         u8         pptx_mask_n[0x1];
8923         u8         reserved_at_43[0x5];
8924         u8         pfctx[0x8];
8925         u8         reserved_at_50[0x10];
8926
8927         u8         pprx[0x1];
8928         u8         aprx[0x1];
8929         u8         pprx_mask_n[0x1];
8930         u8         reserved_at_63[0x5];
8931         u8         pfcrx[0x8];
8932         u8         reserved_at_70[0x10];
8933
8934         u8         device_stall_minor_watermark[0x10];
8935         u8         device_stall_critical_watermark[0x10];
8936
8937         u8         reserved_at_a0[0x60];
8938 };
8939
8940 struct mlx5_ifc_pelc_reg_bits {
8941         u8         op[0x4];
8942         u8         reserved_at_4[0x4];
8943         u8         local_port[0x8];
8944         u8         reserved_at_10[0x10];
8945
8946         u8         op_admin[0x8];
8947         u8         op_capability[0x8];
8948         u8         op_request[0x8];
8949         u8         op_active[0x8];
8950
8951         u8         admin[0x40];
8952
8953         u8         capability[0x40];
8954
8955         u8         request[0x40];
8956
8957         u8         active[0x40];
8958
8959         u8         reserved_at_140[0x80];
8960 };
8961
8962 struct mlx5_ifc_peir_reg_bits {
8963         u8         reserved_at_0[0x8];
8964         u8         local_port[0x8];
8965         u8         reserved_at_10[0x10];
8966
8967         u8         reserved_at_20[0xc];
8968         u8         error_count[0x4];
8969         u8         reserved_at_30[0x10];
8970
8971         u8         reserved_at_40[0xc];
8972         u8         lane[0x4];
8973         u8         reserved_at_50[0x8];
8974         u8         error_type[0x8];
8975 };
8976
8977 struct mlx5_ifc_mpegc_reg_bits {
8978         u8         reserved_at_0[0x30];
8979         u8         field_select[0x10];
8980
8981         u8         tx_overflow_sense[0x1];
8982         u8         mark_cqe[0x1];
8983         u8         mark_cnp[0x1];
8984         u8         reserved_at_43[0x1b];
8985         u8         tx_lossy_overflow_oper[0x2];
8986
8987         u8         reserved_at_60[0x100];
8988 };
8989
8990 struct mlx5_ifc_pcam_enhanced_features_bits {
8991         u8         reserved_at_0[0x68];
8992         u8         fec_50G_per_lane_in_pplm[0x1];
8993         u8         reserved_at_69[0x4];
8994         u8         rx_icrc_encapsulated_counter[0x1];
8995         u8         reserved_at_6e[0x4];
8996         u8         ptys_extended_ethernet[0x1];
8997         u8         reserved_at_73[0x3];
8998         u8         pfcc_mask[0x1];
8999         u8         reserved_at_77[0x3];
9000         u8         per_lane_error_counters[0x1];
9001         u8         rx_buffer_fullness_counters[0x1];
9002         u8         ptys_connector_type[0x1];
9003         u8         reserved_at_7d[0x1];
9004         u8         ppcnt_discard_group[0x1];
9005         u8         ppcnt_statistical_group[0x1];
9006 };
9007
9008 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9009         u8         port_access_reg_cap_mask_127_to_96[0x20];
9010         u8         port_access_reg_cap_mask_95_to_64[0x20];
9011
9012         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9013         u8         pplm[0x1];
9014         u8         port_access_reg_cap_mask_34_to_32[0x3];
9015
9016         u8         port_access_reg_cap_mask_31_to_13[0x13];
9017         u8         pbmc[0x1];
9018         u8         pptb[0x1];
9019         u8         port_access_reg_cap_mask_10_to_09[0x2];
9020         u8         ppcnt[0x1];
9021         u8         port_access_reg_cap_mask_07_to_00[0x8];
9022 };
9023
9024 struct mlx5_ifc_pcam_reg_bits {
9025         u8         reserved_at_0[0x8];
9026         u8         feature_group[0x8];
9027         u8         reserved_at_10[0x8];
9028         u8         access_reg_group[0x8];
9029
9030         u8         reserved_at_20[0x20];
9031
9032         union {
9033                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9034                 u8         reserved_at_0[0x80];
9035         } port_access_reg_cap_mask;
9036
9037         u8         reserved_at_c0[0x80];
9038
9039         union {
9040                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9041                 u8         reserved_at_0[0x80];
9042         } feature_cap_mask;
9043
9044         u8         reserved_at_1c0[0xc0];
9045 };
9046
9047 struct mlx5_ifc_mcam_enhanced_features_bits {
9048         u8         reserved_at_0[0x6e];
9049         u8         pci_status_and_power[0x1];
9050         u8         reserved_at_6f[0x5];
9051         u8         mark_tx_action_cnp[0x1];
9052         u8         mark_tx_action_cqe[0x1];
9053         u8         dynamic_tx_overflow[0x1];
9054         u8         reserved_at_77[0x4];
9055         u8         pcie_outbound_stalled[0x1];
9056         u8         tx_overflow_buffer_pkt[0x1];
9057         u8         mtpps_enh_out_per_adj[0x1];
9058         u8         mtpps_fs[0x1];
9059         u8         pcie_performance_group[0x1];
9060 };
9061
9062 struct mlx5_ifc_mcam_access_reg_bits {
9063         u8         reserved_at_0[0x1c];
9064         u8         mcda[0x1];
9065         u8         mcc[0x1];
9066         u8         mcqi[0x1];
9067         u8         mcqs[0x1];
9068
9069         u8         regs_95_to_87[0x9];
9070         u8         mpegc[0x1];
9071         u8         regs_85_to_68[0x12];
9072         u8         tracer_registers[0x4];
9073
9074         u8         regs_63_to_32[0x20];
9075         u8         regs_31_to_0[0x20];
9076 };
9077
9078 struct mlx5_ifc_mcam_access_reg_bits1 {
9079         u8         regs_127_to_96[0x20];
9080
9081         u8         regs_95_to_64[0x20];
9082
9083         u8         regs_63_to_32[0x20];
9084
9085         u8         regs_31_to_0[0x20];
9086 };
9087
9088 struct mlx5_ifc_mcam_access_reg_bits2 {
9089         u8         regs_127_to_99[0x1d];
9090         u8         mirc[0x1];
9091         u8         regs_97_to_96[0x2];
9092
9093         u8         regs_95_to_64[0x20];
9094
9095         u8         regs_63_to_32[0x20];
9096
9097         u8         regs_31_to_0[0x20];
9098 };
9099
9100 struct mlx5_ifc_mcam_reg_bits {
9101         u8         reserved_at_0[0x8];
9102         u8         feature_group[0x8];
9103         u8         reserved_at_10[0x8];
9104         u8         access_reg_group[0x8];
9105
9106         u8         reserved_at_20[0x20];
9107
9108         union {
9109                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9110                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9111                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9112                 u8         reserved_at_0[0x80];
9113         } mng_access_reg_cap_mask;
9114
9115         u8         reserved_at_c0[0x80];
9116
9117         union {
9118                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9119                 u8         reserved_at_0[0x80];
9120         } mng_feature_cap_mask;
9121
9122         u8         reserved_at_1c0[0x80];
9123 };
9124
9125 struct mlx5_ifc_qcam_access_reg_cap_mask {
9126         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9127         u8         qpdpm[0x1];
9128         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9129         u8         qdpm[0x1];
9130         u8         qpts[0x1];
9131         u8         qcap[0x1];
9132         u8         qcam_access_reg_cap_mask_0[0x1];
9133 };
9134
9135 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9136         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9137         u8         qpts_trust_both[0x1];
9138 };
9139
9140 struct mlx5_ifc_qcam_reg_bits {
9141         u8         reserved_at_0[0x8];
9142         u8         feature_group[0x8];
9143         u8         reserved_at_10[0x8];
9144         u8         access_reg_group[0x8];
9145         u8         reserved_at_20[0x20];
9146
9147         union {
9148                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9149                 u8  reserved_at_0[0x80];
9150         } qos_access_reg_cap_mask;
9151
9152         u8         reserved_at_c0[0x80];
9153
9154         union {
9155                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9156                 u8  reserved_at_0[0x80];
9157         } qos_feature_cap_mask;
9158
9159         u8         reserved_at_1c0[0x80];
9160 };
9161
9162 struct mlx5_ifc_core_dump_reg_bits {
9163         u8         reserved_at_0[0x18];
9164         u8         core_dump_type[0x8];
9165
9166         u8         reserved_at_20[0x30];
9167         u8         vhca_id[0x10];
9168
9169         u8         reserved_at_60[0x8];
9170         u8         qpn[0x18];
9171         u8         reserved_at_80[0x180];
9172 };
9173
9174 struct mlx5_ifc_pcap_reg_bits {
9175         u8         reserved_at_0[0x8];
9176         u8         local_port[0x8];
9177         u8         reserved_at_10[0x10];
9178
9179         u8         port_capability_mask[4][0x20];
9180 };
9181
9182 struct mlx5_ifc_paos_reg_bits {
9183         u8         swid[0x8];
9184         u8         local_port[0x8];
9185         u8         reserved_at_10[0x4];
9186         u8         admin_status[0x4];
9187         u8         reserved_at_18[0x4];
9188         u8         oper_status[0x4];
9189
9190         u8         ase[0x1];
9191         u8         ee[0x1];
9192         u8         reserved_at_22[0x1c];
9193         u8         e[0x2];
9194
9195         u8         reserved_at_40[0x40];
9196 };
9197
9198 struct mlx5_ifc_pamp_reg_bits {
9199         u8         reserved_at_0[0x8];
9200         u8         opamp_group[0x8];
9201         u8         reserved_at_10[0xc];
9202         u8         opamp_group_type[0x4];
9203
9204         u8         start_index[0x10];
9205         u8         reserved_at_30[0x4];
9206         u8         num_of_indices[0xc];
9207
9208         u8         index_data[18][0x10];
9209 };
9210
9211 struct mlx5_ifc_pcmr_reg_bits {
9212         u8         reserved_at_0[0x8];
9213         u8         local_port[0x8];
9214         u8         reserved_at_10[0x10];
9215         u8         entropy_force_cap[0x1];
9216         u8         entropy_calc_cap[0x1];
9217         u8         entropy_gre_calc_cap[0x1];
9218         u8         reserved_at_23[0x1b];
9219         u8         fcs_cap[0x1];
9220         u8         reserved_at_3f[0x1];
9221         u8         entropy_force[0x1];
9222         u8         entropy_calc[0x1];
9223         u8         entropy_gre_calc[0x1];
9224         u8         reserved_at_43[0x1b];
9225         u8         fcs_chk[0x1];
9226         u8         reserved_at_5f[0x1];
9227 };
9228
9229 struct mlx5_ifc_lane_2_module_mapping_bits {
9230         u8         reserved_at_0[0x6];
9231         u8         rx_lane[0x2];
9232         u8         reserved_at_8[0x6];
9233         u8         tx_lane[0x2];
9234         u8         reserved_at_10[0x8];
9235         u8         module[0x8];
9236 };
9237
9238 struct mlx5_ifc_bufferx_reg_bits {
9239         u8         reserved_at_0[0x6];
9240         u8         lossy[0x1];
9241         u8         epsb[0x1];
9242         u8         reserved_at_8[0xc];
9243         u8         size[0xc];
9244
9245         u8         xoff_threshold[0x10];
9246         u8         xon_threshold[0x10];
9247 };
9248
9249 struct mlx5_ifc_set_node_in_bits {
9250         u8         node_description[64][0x8];
9251 };
9252
9253 struct mlx5_ifc_register_power_settings_bits {
9254         u8         reserved_at_0[0x18];
9255         u8         power_settings_level[0x8];
9256
9257         u8         reserved_at_20[0x60];
9258 };
9259
9260 struct mlx5_ifc_register_host_endianness_bits {
9261         u8         he[0x1];
9262         u8         reserved_at_1[0x1f];
9263
9264         u8         reserved_at_20[0x60];
9265 };
9266
9267 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9268         u8         reserved_at_0[0x20];
9269
9270         u8         mkey[0x20];
9271
9272         u8         addressh_63_32[0x20];
9273
9274         u8         addressl_31_0[0x20];
9275 };
9276
9277 struct mlx5_ifc_ud_adrs_vector_bits {
9278         u8         dc_key[0x40];
9279
9280         u8         ext[0x1];
9281         u8         reserved_at_41[0x7];
9282         u8         destination_qp_dct[0x18];
9283
9284         u8         static_rate[0x4];
9285         u8         sl_eth_prio[0x4];
9286         u8         fl[0x1];
9287         u8         mlid[0x7];
9288         u8         rlid_udp_sport[0x10];
9289
9290         u8         reserved_at_80[0x20];
9291
9292         u8         rmac_47_16[0x20];
9293
9294         u8         rmac_15_0[0x10];
9295         u8         tclass[0x8];
9296         u8         hop_limit[0x8];
9297
9298         u8         reserved_at_e0[0x1];
9299         u8         grh[0x1];
9300         u8         reserved_at_e2[0x2];
9301         u8         src_addr_index[0x8];
9302         u8         flow_label[0x14];
9303
9304         u8         rgid_rip[16][0x8];
9305 };
9306
9307 struct mlx5_ifc_pages_req_event_bits {
9308         u8         reserved_at_0[0x10];
9309         u8         function_id[0x10];
9310
9311         u8         num_pages[0x20];
9312
9313         u8         reserved_at_40[0xa0];
9314 };
9315
9316 struct mlx5_ifc_eqe_bits {
9317         u8         reserved_at_0[0x8];
9318         u8         event_type[0x8];
9319         u8         reserved_at_10[0x8];
9320         u8         event_sub_type[0x8];
9321
9322         u8         reserved_at_20[0xe0];
9323
9324         union mlx5_ifc_event_auto_bits event_data;
9325
9326         u8         reserved_at_1e0[0x10];
9327         u8         signature[0x8];
9328         u8         reserved_at_1f8[0x7];
9329         u8         owner[0x1];
9330 };
9331
9332 enum {
9333         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9334 };
9335
9336 struct mlx5_ifc_cmd_queue_entry_bits {
9337         u8         type[0x8];
9338         u8         reserved_at_8[0x18];
9339
9340         u8         input_length[0x20];
9341
9342         u8         input_mailbox_pointer_63_32[0x20];
9343
9344         u8         input_mailbox_pointer_31_9[0x17];
9345         u8         reserved_at_77[0x9];
9346
9347         u8         command_input_inline_data[16][0x8];
9348
9349         u8         command_output_inline_data[16][0x8];
9350
9351         u8         output_mailbox_pointer_63_32[0x20];
9352
9353         u8         output_mailbox_pointer_31_9[0x17];
9354         u8         reserved_at_1b7[0x9];
9355
9356         u8         output_length[0x20];
9357
9358         u8         token[0x8];
9359         u8         signature[0x8];
9360         u8         reserved_at_1f0[0x8];
9361         u8         status[0x7];
9362         u8         ownership[0x1];
9363 };
9364
9365 struct mlx5_ifc_cmd_out_bits {
9366         u8         status[0x8];
9367         u8         reserved_at_8[0x18];
9368
9369         u8         syndrome[0x20];
9370
9371         u8         command_output[0x20];
9372 };
9373
9374 struct mlx5_ifc_cmd_in_bits {
9375         u8         opcode[0x10];
9376         u8         reserved_at_10[0x10];
9377
9378         u8         reserved_at_20[0x10];
9379         u8         op_mod[0x10];
9380
9381         u8         command[][0x20];
9382 };
9383
9384 struct mlx5_ifc_cmd_if_box_bits {
9385         u8         mailbox_data[512][0x8];
9386
9387         u8         reserved_at_1000[0x180];
9388
9389         u8         next_pointer_63_32[0x20];
9390
9391         u8         next_pointer_31_10[0x16];
9392         u8         reserved_at_11b6[0xa];
9393
9394         u8         block_number[0x20];
9395
9396         u8         reserved_at_11e0[0x8];
9397         u8         token[0x8];
9398         u8         ctrl_signature[0x8];
9399         u8         signature[0x8];
9400 };
9401
9402 struct mlx5_ifc_mtt_bits {
9403         u8         ptag_63_32[0x20];
9404
9405         u8         ptag_31_8[0x18];
9406         u8         reserved_at_38[0x6];
9407         u8         wr_en[0x1];
9408         u8         rd_en[0x1];
9409 };
9410
9411 struct mlx5_ifc_query_wol_rol_out_bits {
9412         u8         status[0x8];
9413         u8         reserved_at_8[0x18];
9414
9415         u8         syndrome[0x20];
9416
9417         u8         reserved_at_40[0x10];
9418         u8         rol_mode[0x8];
9419         u8         wol_mode[0x8];
9420
9421         u8         reserved_at_60[0x20];
9422 };
9423
9424 struct mlx5_ifc_query_wol_rol_in_bits {
9425         u8         opcode[0x10];
9426         u8         reserved_at_10[0x10];
9427
9428         u8         reserved_at_20[0x10];
9429         u8         op_mod[0x10];
9430
9431         u8         reserved_at_40[0x40];
9432 };
9433
9434 struct mlx5_ifc_set_wol_rol_out_bits {
9435         u8         status[0x8];
9436         u8         reserved_at_8[0x18];
9437
9438         u8         syndrome[0x20];
9439
9440         u8         reserved_at_40[0x40];
9441 };
9442
9443 struct mlx5_ifc_set_wol_rol_in_bits {
9444         u8         opcode[0x10];
9445         u8         reserved_at_10[0x10];
9446
9447         u8         reserved_at_20[0x10];
9448         u8         op_mod[0x10];
9449
9450         u8         rol_mode_valid[0x1];
9451         u8         wol_mode_valid[0x1];
9452         u8         reserved_at_42[0xe];
9453         u8         rol_mode[0x8];
9454         u8         wol_mode[0x8];
9455
9456         u8         reserved_at_60[0x20];
9457 };
9458
9459 enum {
9460         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9461         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9462         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9463 };
9464
9465 enum {
9466         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9467         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9468         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9469 };
9470
9471 enum {
9472         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9473         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9474         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9475         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9476         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9477         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9478         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9479         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9480         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9481         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9482         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9483 };
9484
9485 struct mlx5_ifc_initial_seg_bits {
9486         u8         fw_rev_minor[0x10];
9487         u8         fw_rev_major[0x10];
9488
9489         u8         cmd_interface_rev[0x10];
9490         u8         fw_rev_subminor[0x10];
9491
9492         u8         reserved_at_40[0x40];
9493
9494         u8         cmdq_phy_addr_63_32[0x20];
9495
9496         u8         cmdq_phy_addr_31_12[0x14];
9497         u8         reserved_at_b4[0x2];
9498         u8         nic_interface[0x2];
9499         u8         log_cmdq_size[0x4];
9500         u8         log_cmdq_stride[0x4];
9501
9502         u8         command_doorbell_vector[0x20];
9503
9504         u8         reserved_at_e0[0xf00];
9505
9506         u8         initializing[0x1];
9507         u8         reserved_at_fe1[0x4];
9508         u8         nic_interface_supported[0x3];
9509         u8         embedded_cpu[0x1];
9510         u8         reserved_at_fe9[0x17];
9511
9512         struct mlx5_ifc_health_buffer_bits health_buffer;
9513
9514         u8         no_dram_nic_offset[0x20];
9515
9516         u8         reserved_at_1220[0x6e40];
9517
9518         u8         reserved_at_8060[0x1f];
9519         u8         clear_int[0x1];
9520
9521         u8         health_syndrome[0x8];
9522         u8         health_counter[0x18];
9523
9524         u8         reserved_at_80a0[0x17fc0];
9525 };
9526
9527 struct mlx5_ifc_mtpps_reg_bits {
9528         u8         reserved_at_0[0xc];
9529         u8         cap_number_of_pps_pins[0x4];
9530         u8         reserved_at_10[0x4];
9531         u8         cap_max_num_of_pps_in_pins[0x4];
9532         u8         reserved_at_18[0x4];
9533         u8         cap_max_num_of_pps_out_pins[0x4];
9534
9535         u8         reserved_at_20[0x24];
9536         u8         cap_pin_3_mode[0x4];
9537         u8         reserved_at_48[0x4];
9538         u8         cap_pin_2_mode[0x4];
9539         u8         reserved_at_50[0x4];
9540         u8         cap_pin_1_mode[0x4];
9541         u8         reserved_at_58[0x4];
9542         u8         cap_pin_0_mode[0x4];
9543
9544         u8         reserved_at_60[0x4];
9545         u8         cap_pin_7_mode[0x4];
9546         u8         reserved_at_68[0x4];
9547         u8         cap_pin_6_mode[0x4];
9548         u8         reserved_at_70[0x4];
9549         u8         cap_pin_5_mode[0x4];
9550         u8         reserved_at_78[0x4];
9551         u8         cap_pin_4_mode[0x4];
9552
9553         u8         field_select[0x20];
9554         u8         reserved_at_a0[0x60];
9555
9556         u8         enable[0x1];
9557         u8         reserved_at_101[0xb];
9558         u8         pattern[0x4];
9559         u8         reserved_at_110[0x4];
9560         u8         pin_mode[0x4];
9561         u8         pin[0x8];
9562
9563         u8         reserved_at_120[0x20];
9564
9565         u8         time_stamp[0x40];
9566
9567         u8         out_pulse_duration[0x10];
9568         u8         out_periodic_adjustment[0x10];
9569         u8         enhanced_out_periodic_adjustment[0x20];
9570
9571         u8         reserved_at_1c0[0x20];
9572 };
9573
9574 struct mlx5_ifc_mtppse_reg_bits {
9575         u8         reserved_at_0[0x18];
9576         u8         pin[0x8];
9577         u8         event_arm[0x1];
9578         u8         reserved_at_21[0x1b];
9579         u8         event_generation_mode[0x4];
9580         u8         reserved_at_40[0x40];
9581 };
9582
9583 struct mlx5_ifc_mcqs_reg_bits {
9584         u8         last_index_flag[0x1];
9585         u8         reserved_at_1[0x7];
9586         u8         fw_device[0x8];
9587         u8         component_index[0x10];
9588
9589         u8         reserved_at_20[0x10];
9590         u8         identifier[0x10];
9591
9592         u8         reserved_at_40[0x17];
9593         u8         component_status[0x5];
9594         u8         component_update_state[0x4];
9595
9596         u8         last_update_state_changer_type[0x4];
9597         u8         last_update_state_changer_host_id[0x4];
9598         u8         reserved_at_68[0x18];
9599 };
9600
9601 struct mlx5_ifc_mcqi_cap_bits {
9602         u8         supported_info_bitmask[0x20];
9603
9604         u8         component_size[0x20];
9605
9606         u8         max_component_size[0x20];
9607
9608         u8         log_mcda_word_size[0x4];
9609         u8         reserved_at_64[0xc];
9610         u8         mcda_max_write_size[0x10];
9611
9612         u8         rd_en[0x1];
9613         u8         reserved_at_81[0x1];
9614         u8         match_chip_id[0x1];
9615         u8         match_psid[0x1];
9616         u8         check_user_timestamp[0x1];
9617         u8         match_base_guid_mac[0x1];
9618         u8         reserved_at_86[0x1a];
9619 };
9620
9621 struct mlx5_ifc_mcqi_version_bits {
9622         u8         reserved_at_0[0x2];
9623         u8         build_time_valid[0x1];
9624         u8         user_defined_time_valid[0x1];
9625         u8         reserved_at_4[0x14];
9626         u8         version_string_length[0x8];
9627
9628         u8         version[0x20];
9629
9630         u8         build_time[0x40];
9631
9632         u8         user_defined_time[0x40];
9633
9634         u8         build_tool_version[0x20];
9635
9636         u8         reserved_at_e0[0x20];
9637
9638         u8         version_string[92][0x8];
9639 };
9640
9641 struct mlx5_ifc_mcqi_activation_method_bits {
9642         u8         pending_server_ac_power_cycle[0x1];
9643         u8         pending_server_dc_power_cycle[0x1];
9644         u8         pending_server_reboot[0x1];
9645         u8         pending_fw_reset[0x1];
9646         u8         auto_activate[0x1];
9647         u8         all_hosts_sync[0x1];
9648         u8         device_hw_reset[0x1];
9649         u8         reserved_at_7[0x19];
9650 };
9651
9652 union mlx5_ifc_mcqi_reg_data_bits {
9653         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9654         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9655         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9656 };
9657
9658 struct mlx5_ifc_mcqi_reg_bits {
9659         u8         read_pending_component[0x1];
9660         u8         reserved_at_1[0xf];
9661         u8         component_index[0x10];
9662
9663         u8         reserved_at_20[0x20];
9664
9665         u8         reserved_at_40[0x1b];
9666         u8         info_type[0x5];
9667
9668         u8         info_size[0x20];
9669
9670         u8         offset[0x20];
9671
9672         u8         reserved_at_a0[0x10];
9673         u8         data_size[0x10];
9674
9675         union mlx5_ifc_mcqi_reg_data_bits data[];
9676 };
9677
9678 struct mlx5_ifc_mcc_reg_bits {
9679         u8         reserved_at_0[0x4];
9680         u8         time_elapsed_since_last_cmd[0xc];
9681         u8         reserved_at_10[0x8];
9682         u8         instruction[0x8];
9683
9684         u8         reserved_at_20[0x10];
9685         u8         component_index[0x10];
9686
9687         u8         reserved_at_40[0x8];
9688         u8         update_handle[0x18];
9689
9690         u8         handle_owner_type[0x4];
9691         u8         handle_owner_host_id[0x4];
9692         u8         reserved_at_68[0x1];
9693         u8         control_progress[0x7];
9694         u8         error_code[0x8];
9695         u8         reserved_at_78[0x4];
9696         u8         control_state[0x4];
9697
9698         u8         component_size[0x20];
9699
9700         u8         reserved_at_a0[0x60];
9701 };
9702
9703 struct mlx5_ifc_mcda_reg_bits {
9704         u8         reserved_at_0[0x8];
9705         u8         update_handle[0x18];
9706
9707         u8         offset[0x20];
9708
9709         u8         reserved_at_40[0x10];
9710         u8         size[0x10];
9711
9712         u8         reserved_at_60[0x20];
9713
9714         u8         data[0][0x20];
9715 };
9716
9717 enum {
9718         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9719         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9720 };
9721
9722 enum {
9723         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9724         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9725         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9726 };
9727
9728 struct mlx5_ifc_mfrl_reg_bits {
9729         u8         reserved_at_0[0x20];
9730
9731         u8         reserved_at_20[0x2];
9732         u8         pci_sync_for_fw_update_start[0x1];
9733         u8         pci_sync_for_fw_update_resp[0x2];
9734         u8         rst_type_sel[0x3];
9735         u8         reserved_at_28[0x8];
9736         u8         reset_type[0x8];
9737         u8         reset_level[0x8];
9738 };
9739
9740 struct mlx5_ifc_mirc_reg_bits {
9741         u8         reserved_at_0[0x18];
9742         u8         status_code[0x8];
9743
9744         u8         reserved_at_20[0x20];
9745 };
9746
9747 union mlx5_ifc_ports_control_registers_document_bits {
9748         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9749         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9750         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9751         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9752         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9753         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9754         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9755         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9756         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9757         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9758         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9759         struct mlx5_ifc_paos_reg_bits paos_reg;
9760         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9761         struct mlx5_ifc_peir_reg_bits peir_reg;
9762         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9763         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9764         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9765         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9766         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9767         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9768         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9769         struct mlx5_ifc_plib_reg_bits plib_reg;
9770         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9771         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9772         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9773         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9774         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9775         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9776         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9777         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9778         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9779         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9780         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9781         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9782         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9783         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9784         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9785         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9786         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9787         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9788         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9789         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9790         struct mlx5_ifc_pude_reg_bits pude_reg;
9791         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9792         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9793         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9794         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9795         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9796         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9797         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9798         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9799         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9800         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9801         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9802         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9803         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9804         u8         reserved_at_0[0x60e0];
9805 };
9806
9807 union mlx5_ifc_debug_enhancements_document_bits {
9808         struct mlx5_ifc_health_buffer_bits health_buffer;
9809         u8         reserved_at_0[0x200];
9810 };
9811
9812 union mlx5_ifc_uplink_pci_interface_document_bits {
9813         struct mlx5_ifc_initial_seg_bits initial_seg;
9814         u8         reserved_at_0[0x20060];
9815 };
9816
9817 struct mlx5_ifc_set_flow_table_root_out_bits {
9818         u8         status[0x8];
9819         u8         reserved_at_8[0x18];
9820
9821         u8         syndrome[0x20];
9822
9823         u8         reserved_at_40[0x40];
9824 };
9825
9826 struct mlx5_ifc_set_flow_table_root_in_bits {
9827         u8         opcode[0x10];
9828         u8         reserved_at_10[0x10];
9829
9830         u8         reserved_at_20[0x10];
9831         u8         op_mod[0x10];
9832
9833         u8         other_vport[0x1];
9834         u8         reserved_at_41[0xf];
9835         u8         vport_number[0x10];
9836
9837         u8         reserved_at_60[0x20];
9838
9839         u8         table_type[0x8];
9840         u8         reserved_at_88[0x18];
9841
9842         u8         reserved_at_a0[0x8];
9843         u8         table_id[0x18];
9844
9845         u8         reserved_at_c0[0x8];
9846         u8         underlay_qpn[0x18];
9847         u8         reserved_at_e0[0x120];
9848 };
9849
9850 enum {
9851         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9852         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9853 };
9854
9855 struct mlx5_ifc_modify_flow_table_out_bits {
9856         u8         status[0x8];
9857         u8         reserved_at_8[0x18];
9858
9859         u8         syndrome[0x20];
9860
9861         u8         reserved_at_40[0x40];
9862 };
9863
9864 struct mlx5_ifc_modify_flow_table_in_bits {
9865         u8         opcode[0x10];
9866         u8         reserved_at_10[0x10];
9867
9868         u8         reserved_at_20[0x10];
9869         u8         op_mod[0x10];
9870
9871         u8         other_vport[0x1];
9872         u8         reserved_at_41[0xf];
9873         u8         vport_number[0x10];
9874
9875         u8         reserved_at_60[0x10];
9876         u8         modify_field_select[0x10];
9877
9878         u8         table_type[0x8];
9879         u8         reserved_at_88[0x18];
9880
9881         u8         reserved_at_a0[0x8];
9882         u8         table_id[0x18];
9883
9884         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9885 };
9886
9887 struct mlx5_ifc_ets_tcn_config_reg_bits {
9888         u8         g[0x1];
9889         u8         b[0x1];
9890         u8         r[0x1];
9891         u8         reserved_at_3[0x9];
9892         u8         group[0x4];
9893         u8         reserved_at_10[0x9];
9894         u8         bw_allocation[0x7];
9895
9896         u8         reserved_at_20[0xc];
9897         u8         max_bw_units[0x4];
9898         u8         reserved_at_30[0x8];
9899         u8         max_bw_value[0x8];
9900 };
9901
9902 struct mlx5_ifc_ets_global_config_reg_bits {
9903         u8         reserved_at_0[0x2];
9904         u8         r[0x1];
9905         u8         reserved_at_3[0x1d];
9906
9907         u8         reserved_at_20[0xc];
9908         u8         max_bw_units[0x4];
9909         u8         reserved_at_30[0x8];
9910         u8         max_bw_value[0x8];
9911 };
9912
9913 struct mlx5_ifc_qetc_reg_bits {
9914         u8                                         reserved_at_0[0x8];
9915         u8                                         port_number[0x8];
9916         u8                                         reserved_at_10[0x30];
9917
9918         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9919         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9920 };
9921
9922 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9923         u8         e[0x1];
9924         u8         reserved_at_01[0x0b];
9925         u8         prio[0x04];
9926 };
9927
9928 struct mlx5_ifc_qpdpm_reg_bits {
9929         u8                                     reserved_at_0[0x8];
9930         u8                                     local_port[0x8];
9931         u8                                     reserved_at_10[0x10];
9932         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9933 };
9934
9935 struct mlx5_ifc_qpts_reg_bits {
9936         u8         reserved_at_0[0x8];
9937         u8         local_port[0x8];
9938         u8         reserved_at_10[0x2d];
9939         u8         trust_state[0x3];
9940 };
9941
9942 struct mlx5_ifc_pptb_reg_bits {
9943         u8         reserved_at_0[0x2];
9944         u8         mm[0x2];
9945         u8         reserved_at_4[0x4];
9946         u8         local_port[0x8];
9947         u8         reserved_at_10[0x6];
9948         u8         cm[0x1];
9949         u8         um[0x1];
9950         u8         pm[0x8];
9951
9952         u8         prio_x_buff[0x20];
9953
9954         u8         pm_msb[0x8];
9955         u8         reserved_at_48[0x10];
9956         u8         ctrl_buff[0x4];
9957         u8         untagged_buff[0x4];
9958 };
9959
9960 struct mlx5_ifc_pbmc_reg_bits {
9961         u8         reserved_at_0[0x8];
9962         u8         local_port[0x8];
9963         u8         reserved_at_10[0x10];
9964
9965         u8         xoff_timer_value[0x10];
9966         u8         xoff_refresh[0x10];
9967
9968         u8         reserved_at_40[0x9];
9969         u8         fullness_threshold[0x7];
9970         u8         port_buffer_size[0x10];
9971
9972         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9973
9974         u8         reserved_at_2e0[0x40];
9975 };
9976
9977 struct mlx5_ifc_qtct_reg_bits {
9978         u8         reserved_at_0[0x8];
9979         u8         port_number[0x8];
9980         u8         reserved_at_10[0xd];
9981         u8         prio[0x3];
9982
9983         u8         reserved_at_20[0x1d];
9984         u8         tclass[0x3];
9985 };
9986
9987 struct mlx5_ifc_mcia_reg_bits {
9988         u8         l[0x1];
9989         u8         reserved_at_1[0x7];
9990         u8         module[0x8];
9991         u8         reserved_at_10[0x8];
9992         u8         status[0x8];
9993
9994         u8         i2c_device_address[0x8];
9995         u8         page_number[0x8];
9996         u8         device_address[0x10];
9997
9998         u8         reserved_at_40[0x10];
9999         u8         size[0x10];
10000
10001         u8         reserved_at_60[0x20];
10002
10003         u8         dword_0[0x20];
10004         u8         dword_1[0x20];
10005         u8         dword_2[0x20];
10006         u8         dword_3[0x20];
10007         u8         dword_4[0x20];
10008         u8         dword_5[0x20];
10009         u8         dword_6[0x20];
10010         u8         dword_7[0x20];
10011         u8         dword_8[0x20];
10012         u8         dword_9[0x20];
10013         u8         dword_10[0x20];
10014         u8         dword_11[0x20];
10015 };
10016
10017 struct mlx5_ifc_dcbx_param_bits {
10018         u8         dcbx_cee_cap[0x1];
10019         u8         dcbx_ieee_cap[0x1];
10020         u8         dcbx_standby_cap[0x1];
10021         u8         reserved_at_3[0x5];
10022         u8         port_number[0x8];
10023         u8         reserved_at_10[0xa];
10024         u8         max_application_table_size[6];
10025         u8         reserved_at_20[0x15];
10026         u8         version_oper[0x3];
10027         u8         reserved_at_38[5];
10028         u8         version_admin[0x3];
10029         u8         willing_admin[0x1];
10030         u8         reserved_at_41[0x3];
10031         u8         pfc_cap_oper[0x4];
10032         u8         reserved_at_48[0x4];
10033         u8         pfc_cap_admin[0x4];
10034         u8         reserved_at_50[0x4];
10035         u8         num_of_tc_oper[0x4];
10036         u8         reserved_at_58[0x4];
10037         u8         num_of_tc_admin[0x4];
10038         u8         remote_willing[0x1];
10039         u8         reserved_at_61[3];
10040         u8         remote_pfc_cap[4];
10041         u8         reserved_at_68[0x14];
10042         u8         remote_num_of_tc[0x4];
10043         u8         reserved_at_80[0x18];
10044         u8         error[0x8];
10045         u8         reserved_at_a0[0x160];
10046 };
10047
10048 struct mlx5_ifc_lagc_bits {
10049         u8         reserved_at_0[0x1d];
10050         u8         lag_state[0x3];
10051
10052         u8         reserved_at_20[0x14];
10053         u8         tx_remap_affinity_2[0x4];
10054         u8         reserved_at_38[0x4];
10055         u8         tx_remap_affinity_1[0x4];
10056 };
10057
10058 struct mlx5_ifc_create_lag_out_bits {
10059         u8         status[0x8];
10060         u8         reserved_at_8[0x18];
10061
10062         u8         syndrome[0x20];
10063
10064         u8         reserved_at_40[0x40];
10065 };
10066
10067 struct mlx5_ifc_create_lag_in_bits {
10068         u8         opcode[0x10];
10069         u8         reserved_at_10[0x10];
10070
10071         u8         reserved_at_20[0x10];
10072         u8         op_mod[0x10];
10073
10074         struct mlx5_ifc_lagc_bits ctx;
10075 };
10076
10077 struct mlx5_ifc_modify_lag_out_bits {
10078         u8         status[0x8];
10079         u8         reserved_at_8[0x18];
10080
10081         u8         syndrome[0x20];
10082
10083         u8         reserved_at_40[0x40];
10084 };
10085
10086 struct mlx5_ifc_modify_lag_in_bits {
10087         u8         opcode[0x10];
10088         u8         reserved_at_10[0x10];
10089
10090         u8         reserved_at_20[0x10];
10091         u8         op_mod[0x10];
10092
10093         u8         reserved_at_40[0x20];
10094         u8         field_select[0x20];
10095
10096         struct mlx5_ifc_lagc_bits ctx;
10097 };
10098
10099 struct mlx5_ifc_query_lag_out_bits {
10100         u8         status[0x8];
10101         u8         reserved_at_8[0x18];
10102
10103         u8         syndrome[0x20];
10104
10105         struct mlx5_ifc_lagc_bits ctx;
10106 };
10107
10108 struct mlx5_ifc_query_lag_in_bits {
10109         u8         opcode[0x10];
10110         u8         reserved_at_10[0x10];
10111
10112         u8         reserved_at_20[0x10];
10113         u8         op_mod[0x10];
10114
10115         u8         reserved_at_40[0x40];
10116 };
10117
10118 struct mlx5_ifc_destroy_lag_out_bits {
10119         u8         status[0x8];
10120         u8         reserved_at_8[0x18];
10121
10122         u8         syndrome[0x20];
10123
10124         u8         reserved_at_40[0x40];
10125 };
10126
10127 struct mlx5_ifc_destroy_lag_in_bits {
10128         u8         opcode[0x10];
10129         u8         reserved_at_10[0x10];
10130
10131         u8         reserved_at_20[0x10];
10132         u8         op_mod[0x10];
10133
10134         u8         reserved_at_40[0x40];
10135 };
10136
10137 struct mlx5_ifc_create_vport_lag_out_bits {
10138         u8         status[0x8];
10139         u8         reserved_at_8[0x18];
10140
10141         u8         syndrome[0x20];
10142
10143         u8         reserved_at_40[0x40];
10144 };
10145
10146 struct mlx5_ifc_create_vport_lag_in_bits {
10147         u8         opcode[0x10];
10148         u8         reserved_at_10[0x10];
10149
10150         u8         reserved_at_20[0x10];
10151         u8         op_mod[0x10];
10152
10153         u8         reserved_at_40[0x40];
10154 };
10155
10156 struct mlx5_ifc_destroy_vport_lag_out_bits {
10157         u8         status[0x8];
10158         u8         reserved_at_8[0x18];
10159
10160         u8         syndrome[0x20];
10161
10162         u8         reserved_at_40[0x40];
10163 };
10164
10165 struct mlx5_ifc_destroy_vport_lag_in_bits {
10166         u8         opcode[0x10];
10167         u8         reserved_at_10[0x10];
10168
10169         u8         reserved_at_20[0x10];
10170         u8         op_mod[0x10];
10171
10172         u8         reserved_at_40[0x40];
10173 };
10174
10175 struct mlx5_ifc_alloc_memic_in_bits {
10176         u8         opcode[0x10];
10177         u8         reserved_at_10[0x10];
10178
10179         u8         reserved_at_20[0x10];
10180         u8         op_mod[0x10];
10181
10182         u8         reserved_at_30[0x20];
10183
10184         u8         reserved_at_40[0x18];
10185         u8         log_memic_addr_alignment[0x8];
10186
10187         u8         range_start_addr[0x40];
10188
10189         u8         range_size[0x20];
10190
10191         u8         memic_size[0x20];
10192 };
10193
10194 struct mlx5_ifc_alloc_memic_out_bits {
10195         u8         status[0x8];
10196         u8         reserved_at_8[0x18];
10197
10198         u8         syndrome[0x20];
10199
10200         u8         memic_start_addr[0x40];
10201 };
10202
10203 struct mlx5_ifc_dealloc_memic_in_bits {
10204         u8         opcode[0x10];
10205         u8         reserved_at_10[0x10];
10206
10207         u8         reserved_at_20[0x10];
10208         u8         op_mod[0x10];
10209
10210         u8         reserved_at_40[0x40];
10211
10212         u8         memic_start_addr[0x40];
10213
10214         u8         memic_size[0x20];
10215
10216         u8         reserved_at_e0[0x20];
10217 };
10218
10219 struct mlx5_ifc_dealloc_memic_out_bits {
10220         u8         status[0x8];
10221         u8         reserved_at_8[0x18];
10222
10223         u8         syndrome[0x20];
10224
10225         u8         reserved_at_40[0x40];
10226 };
10227
10228 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10229         u8         opcode[0x10];
10230         u8         uid[0x10];
10231
10232         u8         vhca_tunnel_id[0x10];
10233         u8         obj_type[0x10];
10234
10235         u8         obj_id[0x20];
10236
10237         u8         reserved_at_60[0x20];
10238 };
10239
10240 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10241         u8         status[0x8];
10242         u8         reserved_at_8[0x18];
10243
10244         u8         syndrome[0x20];
10245
10246         u8         obj_id[0x20];
10247
10248         u8         reserved_at_60[0x20];
10249 };
10250
10251 struct mlx5_ifc_umem_bits {
10252         u8         reserved_at_0[0x80];
10253
10254         u8         reserved_at_80[0x1b];
10255         u8         log_page_size[0x5];
10256
10257         u8         page_offset[0x20];
10258
10259         u8         num_of_mtt[0x40];
10260
10261         struct mlx5_ifc_mtt_bits  mtt[];
10262 };
10263
10264 struct mlx5_ifc_uctx_bits {
10265         u8         cap[0x20];
10266
10267         u8         reserved_at_20[0x160];
10268 };
10269
10270 struct mlx5_ifc_sw_icm_bits {
10271         u8         modify_field_select[0x40];
10272
10273         u8         reserved_at_40[0x18];
10274         u8         log_sw_icm_size[0x8];
10275
10276         u8         reserved_at_60[0x20];
10277
10278         u8         sw_icm_start_addr[0x40];
10279
10280         u8         reserved_at_c0[0x140];
10281 };
10282
10283 struct mlx5_ifc_geneve_tlv_option_bits {
10284         u8         modify_field_select[0x40];
10285
10286         u8         reserved_at_40[0x18];
10287         u8         geneve_option_fte_index[0x8];
10288
10289         u8         option_class[0x10];
10290         u8         option_type[0x8];
10291         u8         reserved_at_78[0x3];
10292         u8         option_data_length[0x5];
10293
10294         u8         reserved_at_80[0x180];
10295 };
10296
10297 struct mlx5_ifc_create_umem_in_bits {
10298         u8         opcode[0x10];
10299         u8         uid[0x10];
10300
10301         u8         reserved_at_20[0x10];
10302         u8         op_mod[0x10];
10303
10304         u8         reserved_at_40[0x40];
10305
10306         struct mlx5_ifc_umem_bits  umem;
10307 };
10308
10309 struct mlx5_ifc_create_uctx_in_bits {
10310         u8         opcode[0x10];
10311         u8         reserved_at_10[0x10];
10312
10313         u8         reserved_at_20[0x10];
10314         u8         op_mod[0x10];
10315
10316         u8         reserved_at_40[0x40];
10317
10318         struct mlx5_ifc_uctx_bits  uctx;
10319 };
10320
10321 struct mlx5_ifc_destroy_uctx_in_bits {
10322         u8         opcode[0x10];
10323         u8         reserved_at_10[0x10];
10324
10325         u8         reserved_at_20[0x10];
10326         u8         op_mod[0x10];
10327
10328         u8         reserved_at_40[0x10];
10329         u8         uid[0x10];
10330
10331         u8         reserved_at_60[0x20];
10332 };
10333
10334 struct mlx5_ifc_create_sw_icm_in_bits {
10335         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10336         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10337 };
10338
10339 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10340         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10341         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10342 };
10343
10344 struct mlx5_ifc_mtrc_string_db_param_bits {
10345         u8         string_db_base_address[0x20];
10346
10347         u8         reserved_at_20[0x8];
10348         u8         string_db_size[0x18];
10349 };
10350
10351 struct mlx5_ifc_mtrc_cap_bits {
10352         u8         trace_owner[0x1];
10353         u8         trace_to_memory[0x1];
10354         u8         reserved_at_2[0x4];
10355         u8         trc_ver[0x2];
10356         u8         reserved_at_8[0x14];
10357         u8         num_string_db[0x4];
10358
10359         u8         first_string_trace[0x8];
10360         u8         num_string_trace[0x8];
10361         u8         reserved_at_30[0x28];
10362
10363         u8         log_max_trace_buffer_size[0x8];
10364
10365         u8         reserved_at_60[0x20];
10366
10367         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10368
10369         u8         reserved_at_280[0x180];
10370 };
10371
10372 struct mlx5_ifc_mtrc_conf_bits {
10373         u8         reserved_at_0[0x1c];
10374         u8         trace_mode[0x4];
10375         u8         reserved_at_20[0x18];
10376         u8         log_trace_buffer_size[0x8];
10377         u8         trace_mkey[0x20];
10378         u8         reserved_at_60[0x3a0];
10379 };
10380
10381 struct mlx5_ifc_mtrc_stdb_bits {
10382         u8         string_db_index[0x4];
10383         u8         reserved_at_4[0x4];
10384         u8         read_size[0x18];
10385         u8         start_offset[0x20];
10386         u8         string_db_data[];
10387 };
10388
10389 struct mlx5_ifc_mtrc_ctrl_bits {
10390         u8         trace_status[0x2];
10391         u8         reserved_at_2[0x2];
10392         u8         arm_event[0x1];
10393         u8         reserved_at_5[0xb];
10394         u8         modify_field_select[0x10];
10395         u8         reserved_at_20[0x2b];
10396         u8         current_timestamp52_32[0x15];
10397         u8         current_timestamp31_0[0x20];
10398         u8         reserved_at_80[0x180];
10399 };
10400
10401 struct mlx5_ifc_host_params_context_bits {
10402         u8         host_number[0x8];
10403         u8         reserved_at_8[0x7];
10404         u8         host_pf_disabled[0x1];
10405         u8         host_num_of_vfs[0x10];
10406
10407         u8         host_total_vfs[0x10];
10408         u8         host_pci_bus[0x10];
10409
10410         u8         reserved_at_40[0x10];
10411         u8         host_pci_device[0x10];
10412
10413         u8         reserved_at_60[0x10];
10414         u8         host_pci_function[0x10];
10415
10416         u8         reserved_at_80[0x180];
10417 };
10418
10419 struct mlx5_ifc_query_esw_functions_in_bits {
10420         u8         opcode[0x10];
10421         u8         reserved_at_10[0x10];
10422
10423         u8         reserved_at_20[0x10];
10424         u8         op_mod[0x10];
10425
10426         u8         reserved_at_40[0x40];
10427 };
10428
10429 struct mlx5_ifc_query_esw_functions_out_bits {
10430         u8         status[0x8];
10431         u8         reserved_at_8[0x18];
10432
10433         u8         syndrome[0x20];
10434
10435         u8         reserved_at_40[0x40];
10436
10437         struct mlx5_ifc_host_params_context_bits host_params_context;
10438
10439         u8         reserved_at_280[0x180];
10440         u8         host_sf_enable[][0x40];
10441 };
10442
10443 struct mlx5_ifc_sf_partition_bits {
10444         u8         reserved_at_0[0x10];
10445         u8         log_num_sf[0x8];
10446         u8         log_sf_bar_size[0x8];
10447 };
10448
10449 struct mlx5_ifc_query_sf_partitions_out_bits {
10450         u8         status[0x8];
10451         u8         reserved_at_8[0x18];
10452
10453         u8         syndrome[0x20];
10454
10455         u8         reserved_at_40[0x18];
10456         u8         num_sf_partitions[0x8];
10457
10458         u8         reserved_at_60[0x20];
10459
10460         struct mlx5_ifc_sf_partition_bits sf_partition[];
10461 };
10462
10463 struct mlx5_ifc_query_sf_partitions_in_bits {
10464         u8         opcode[0x10];
10465         u8         reserved_at_10[0x10];
10466
10467         u8         reserved_at_20[0x10];
10468         u8         op_mod[0x10];
10469
10470         u8         reserved_at_40[0x40];
10471 };
10472
10473 struct mlx5_ifc_dealloc_sf_out_bits {
10474         u8         status[0x8];
10475         u8         reserved_at_8[0x18];
10476
10477         u8         syndrome[0x20];
10478
10479         u8         reserved_at_40[0x40];
10480 };
10481
10482 struct mlx5_ifc_dealloc_sf_in_bits {
10483         u8         opcode[0x10];
10484         u8         reserved_at_10[0x10];
10485
10486         u8         reserved_at_20[0x10];
10487         u8         op_mod[0x10];
10488
10489         u8         reserved_at_40[0x10];
10490         u8         function_id[0x10];
10491
10492         u8         reserved_at_60[0x20];
10493 };
10494
10495 struct mlx5_ifc_alloc_sf_out_bits {
10496         u8         status[0x8];
10497         u8         reserved_at_8[0x18];
10498
10499         u8         syndrome[0x20];
10500
10501         u8         reserved_at_40[0x40];
10502 };
10503
10504 struct mlx5_ifc_alloc_sf_in_bits {
10505         u8         opcode[0x10];
10506         u8         reserved_at_10[0x10];
10507
10508         u8         reserved_at_20[0x10];
10509         u8         op_mod[0x10];
10510
10511         u8         reserved_at_40[0x10];
10512         u8         function_id[0x10];
10513
10514         u8         reserved_at_60[0x20];
10515 };
10516
10517 struct mlx5_ifc_affiliated_event_header_bits {
10518         u8         reserved_at_0[0x10];
10519         u8         obj_type[0x10];
10520
10521         u8         obj_id[0x20];
10522 };
10523
10524 enum {
10525         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10526         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10527 };
10528
10529 enum {
10530         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10531         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10532 };
10533
10534 enum {
10535         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10536         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10537         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10538 };
10539
10540 struct mlx5_ifc_ipsec_obj_bits {
10541         u8         modify_field_select[0x40];
10542         u8         full_offload[0x1];
10543         u8         reserved_at_41[0x1];
10544         u8         esn_en[0x1];
10545         u8         esn_overlap[0x1];
10546         u8         reserved_at_44[0x2];
10547         u8         icv_length[0x2];
10548         u8         reserved_at_48[0x4];
10549         u8         aso_return_reg[0x4];
10550         u8         reserved_at_50[0x10];
10551
10552         u8         esn_msb[0x20];
10553
10554         u8         reserved_at_80[0x8];
10555         u8         dekn[0x18];
10556
10557         u8         salt[0x20];
10558
10559         u8         implicit_iv[0x40];
10560
10561         u8         reserved_at_100[0x700];
10562 };
10563
10564 struct mlx5_ifc_create_ipsec_obj_in_bits {
10565         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10566         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10567 };
10568
10569 enum {
10570         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10571         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10572 };
10573
10574 struct mlx5_ifc_query_ipsec_obj_out_bits {
10575         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10576         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10577 };
10578
10579 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10580         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10581         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10582 };
10583
10584 struct mlx5_ifc_encryption_key_obj_bits {
10585         u8         modify_field_select[0x40];
10586
10587         u8         reserved_at_40[0x14];
10588         u8         key_size[0x4];
10589         u8         reserved_at_58[0x4];
10590         u8         key_type[0x4];
10591
10592         u8         reserved_at_60[0x8];
10593         u8         pd[0x18];
10594
10595         u8         reserved_at_80[0x180];
10596         u8         key[8][0x20];
10597
10598         u8         reserved_at_300[0x500];
10599 };
10600
10601 struct mlx5_ifc_create_encryption_key_in_bits {
10602         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10603         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10604 };
10605
10606 enum {
10607         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10608         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10609 };
10610
10611 enum {
10612         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10613         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10614 };
10615
10616 struct mlx5_ifc_tls_static_params_bits {
10617         u8         const_2[0x2];
10618         u8         tls_version[0x4];
10619         u8         const_1[0x2];
10620         u8         reserved_at_8[0x14];
10621         u8         encryption_standard[0x4];
10622
10623         u8         reserved_at_20[0x20];
10624
10625         u8         initial_record_number[0x40];
10626
10627         u8         resync_tcp_sn[0x20];
10628
10629         u8         gcm_iv[0x20];
10630
10631         u8         implicit_iv[0x40];
10632
10633         u8         reserved_at_100[0x8];
10634         u8         dek_index[0x18];
10635
10636         u8         reserved_at_120[0xe0];
10637 };
10638
10639 struct mlx5_ifc_tls_progress_params_bits {
10640         u8         reserved_at_0[0x8];
10641         u8         tisn[0x18];
10642
10643         u8         next_record_tcp_sn[0x20];
10644
10645         u8         hw_resync_tcp_sn[0x20];
10646
10647         u8         record_tracker_state[0x2];
10648         u8         auth_state[0x2];
10649         u8         reserved_at_64[0x4];
10650         u8         hw_offset_record_number[0x18];
10651 };
10652
10653 #endif /* MLX5_IFC_H */