include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77         MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
  78 };
  79
  80 enum {
  81         MLX5_SHARED_RESOURCE_UID = 0xffff,
  82 };
  83
  84 enum {
  85         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  86 };
  87
  88 enum {
  89         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  90         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  91         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
  92 };
  93
  94 enum {
  95         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  96         MLX5_OBJ_TYPE_MKEY = 0xff01,
  97         MLX5_OBJ_TYPE_QP = 0xff02,
  98         MLX5_OBJ_TYPE_PSV = 0xff03,
  99         MLX5_OBJ_TYPE_RMP = 0xff04,
 100         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
 101         MLX5_OBJ_TYPE_RQ = 0xff06,
 102         MLX5_OBJ_TYPE_SQ = 0xff07,
 103         MLX5_OBJ_TYPE_TIR = 0xff08,
 104         MLX5_OBJ_TYPE_TIS = 0xff09,
 105         MLX5_OBJ_TYPE_DCT = 0xff0a,
 106         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 107         MLX5_OBJ_TYPE_RQT = 0xff0e,
 108         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 109         MLX5_OBJ_TYPE_CQ = 0xff10,
 110 };
 111
 112 enum {
 113         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 114         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 115         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 116         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 117         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 118         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 119         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 120         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 121         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 122         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 123         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 124         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 125         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 126         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 127         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 128         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 129         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 130         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 131         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 132         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 133         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 134         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 135         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 136         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 137         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 138         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 139         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 140         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 141         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 142         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 143         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 144         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 145         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 146         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 147         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 148         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 149         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 150         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 151         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 152         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 153         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 154         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 155         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 156         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 157         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 158         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 159         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 160         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 161         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 162         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 163         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 164         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 165         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 166         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 167         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 168         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 169         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 170         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 171         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 172         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 173         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 174         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 175         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 176         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 177         MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
 178         MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
 179         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 180         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 181         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 182         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 183         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 184         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 185         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 186         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 187         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 188         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 189         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 190         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 191         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 192         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 193         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 194         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 195         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 196         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 197         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 198         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 199         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 200         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 201         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 202         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 203         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 204         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 205         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 206         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 207         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 208         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 209         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 210         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 211         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 212         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 213         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 214         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 215         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 216         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 217         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 218         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 219         MLX5_CMD_OP_NOP                           = 0x80d,
 220         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 221         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 222         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 223         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 224         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 225         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 226         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 227         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 228         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 229         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 230         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 231         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 232         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 233         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 234         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 235         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 236         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 237         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 238         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 239         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 240         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 241         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 242         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 243         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 244         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 245         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 246         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 247         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 248         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 249         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 250         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 251         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 252         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 253         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 254         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 255         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 256         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 257         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 258         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 259         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 260         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 261         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 262         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 263         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 264         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 265         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 266         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 267         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 268         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 269         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 270         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 271         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 272         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 273         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 274         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 275         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 276         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 277         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 278         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 279         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 280         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 281         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 282         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 283         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 284         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 285         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 286         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 287         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 288         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 289         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 290         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 291         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 292         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 293         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 294         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 295         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 296         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 297         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 298         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 299         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 300         MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
 301         MLX5_CMD_OP_MAX
 302 };
 303
 304 /* Valid range for general commands that don't work over an object */
 305 enum {
 306         MLX5_CMD_OP_GENERAL_START = 0xb00,
 307         MLX5_CMD_OP_GENERAL_END = 0xd00,
 308 };
 309
 310 struct mlx5_ifc_flow_table_fields_supported_bits {
 311         u8         outer_dmac[0x1];
 312         u8         outer_smac[0x1];
 313         u8         outer_ether_type[0x1];
 314         u8         outer_ip_version[0x1];
 315         u8         outer_first_prio[0x1];
 316         u8         outer_first_cfi[0x1];
 317         u8         outer_first_vid[0x1];
 318         u8         outer_ipv4_ttl[0x1];
 319         u8         outer_second_prio[0x1];
 320         u8         outer_second_cfi[0x1];
 321         u8         outer_second_vid[0x1];
 322         u8         reserved_at_b[0x1];
 323         u8         outer_sip[0x1];
 324         u8         outer_dip[0x1];
 325         u8         outer_frag[0x1];
 326         u8         outer_ip_protocol[0x1];
 327         u8         outer_ip_ecn[0x1];
 328         u8         outer_ip_dscp[0x1];
 329         u8         outer_udp_sport[0x1];
 330         u8         outer_udp_dport[0x1];
 331         u8         outer_tcp_sport[0x1];
 332         u8         outer_tcp_dport[0x1];
 333         u8         outer_tcp_flags[0x1];
 334         u8         outer_gre_protocol[0x1];
 335         u8         outer_gre_key[0x1];
 336         u8         outer_vxlan_vni[0x1];
 337         u8         outer_geneve_vni[0x1];
 338         u8         outer_geneve_oam[0x1];
 339         u8         outer_geneve_protocol_type[0x1];
 340         u8         outer_geneve_opt_len[0x1];
 341         u8         reserved_at_1e[0x1];
 342         u8         source_eswitch_port[0x1];
 343
 344         u8         inner_dmac[0x1];
 345         u8         inner_smac[0x1];
 346         u8         inner_ether_type[0x1];
 347         u8         inner_ip_version[0x1];
 348         u8         inner_first_prio[0x1];
 349         u8         inner_first_cfi[0x1];
 350         u8         inner_first_vid[0x1];
 351         u8         reserved_at_27[0x1];
 352         u8         inner_second_prio[0x1];
 353         u8         inner_second_cfi[0x1];
 354         u8         inner_second_vid[0x1];
 355         u8         reserved_at_2b[0x1];
 356         u8         inner_sip[0x1];
 357         u8         inner_dip[0x1];
 358         u8         inner_frag[0x1];
 359         u8         inner_ip_protocol[0x1];
 360         u8         inner_ip_ecn[0x1];
 361         u8         inner_ip_dscp[0x1];
 362         u8         inner_udp_sport[0x1];
 363         u8         inner_udp_dport[0x1];
 364         u8         inner_tcp_sport[0x1];
 365         u8         inner_tcp_dport[0x1];
 366         u8         inner_tcp_flags[0x1];
 367         u8         reserved_at_37[0x9];
 368
 369         u8         geneve_tlv_option_0_data[0x1];
 370         u8         reserved_at_41[0x4];
 371         u8         outer_first_mpls_over_udp[0x4];
 372         u8         outer_first_mpls_over_gre[0x4];
 373         u8         inner_first_mpls[0x4];
 374         u8         outer_first_mpls[0x4];
 375         u8         reserved_at_55[0x2];
 376         u8         outer_esp_spi[0x1];
 377         u8         reserved_at_58[0x2];
 378         u8         bth_dst_qp[0x1];
 379         u8         reserved_at_5b[0x5];
 380
 381         u8         reserved_at_60[0x18];
 382         u8         metadata_reg_c_7[0x1];
 383         u8         metadata_reg_c_6[0x1];
 384         u8         metadata_reg_c_5[0x1];
 385         u8         metadata_reg_c_4[0x1];
 386         u8         metadata_reg_c_3[0x1];
 387         u8         metadata_reg_c_2[0x1];
 388         u8         metadata_reg_c_1[0x1];
 389         u8         metadata_reg_c_0[0x1];
 390 };
 391
 392 struct mlx5_ifc_flow_table_prop_layout_bits {
 393         u8         ft_support[0x1];
 394         u8         reserved_at_1[0x1];
 395         u8         flow_counter[0x1];
 396         u8         flow_modify_en[0x1];
 397         u8         modify_root[0x1];
 398         u8         identified_miss_table_mode[0x1];
 399         u8         flow_table_modify[0x1];
 400         u8         reformat[0x1];
 401         u8         decap[0x1];
 402         u8         reserved_at_9[0x1];
 403         u8         pop_vlan[0x1];
 404         u8         push_vlan[0x1];
 405         u8         reserved_at_c[0x1];
 406         u8         pop_vlan_2[0x1];
 407         u8         push_vlan_2[0x1];
 408         u8         reformat_and_vlan_action[0x1];
 409         u8         reserved_at_10[0x1];
 410         u8         sw_owner[0x1];
 411         u8         reformat_l3_tunnel_to_l2[0x1];
 412         u8         reformat_l2_to_l3_tunnel[0x1];
 413         u8         reformat_and_modify_action[0x1];
 414         u8         ignore_flow_level[0x1];
 415         u8         reserved_at_16[0x1];
 416         u8         table_miss_action_domain[0x1];
 417         u8         termination_table[0x1];
 418         u8         reformat_and_fwd_to_table[0x1];
 419         u8         reserved_at_1a[0x6];
 420         u8         termination_table_raw_traffic[0x1];
 421         u8         reserved_at_21[0x1];
 422         u8         log_max_ft_size[0x6];
 423         u8         log_max_modify_header_context[0x8];
 424         u8         max_modify_header_actions[0x8];
 425         u8         max_ft_level[0x8];
 426
 427         u8         reserved_at_40[0x20];
 428
 429         u8         reserved_at_60[0x18];
 430         u8         log_max_ft_num[0x8];
 431
 432         u8         reserved_at_80[0x18];
 433         u8         log_max_destination[0x8];
 434
 435         u8         log_max_flow_counter[0x8];
 436         u8         reserved_at_a8[0x10];
 437         u8         log_max_flow[0x8];
 438
 439         u8         reserved_at_c0[0x40];
 440
 441         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 442
 443         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 444 };
 445
 446 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 447         u8         send[0x1];
 448         u8         receive[0x1];
 449         u8         write[0x1];
 450         u8         read[0x1];
 451         u8         atomic[0x1];
 452         u8         srq_receive[0x1];
 453         u8         reserved_at_6[0x1a];
 454 };
 455
 456 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 457         u8         smac_47_16[0x20];
 458
 459         u8         smac_15_0[0x10];
 460         u8         ethertype[0x10];
 461
 462         u8         dmac_47_16[0x20];
 463
 464         u8         dmac_15_0[0x10];
 465         u8         first_prio[0x3];
 466         u8         first_cfi[0x1];
 467         u8         first_vid[0xc];
 468
 469         u8         ip_protocol[0x8];
 470         u8         ip_dscp[0x6];
 471         u8         ip_ecn[0x2];
 472         u8         cvlan_tag[0x1];
 473         u8         svlan_tag[0x1];
 474         u8         frag[0x1];
 475         u8         ip_version[0x4];
 476         u8         tcp_flags[0x9];
 477
 478         u8         tcp_sport[0x10];
 479         u8         tcp_dport[0x10];
 480
 481         u8         reserved_at_c0[0x18];
 482         u8         ttl_hoplimit[0x8];
 483
 484         u8         udp_sport[0x10];
 485         u8         udp_dport[0x10];
 486
 487         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 488
 489         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 490 };
 491
 492 struct mlx5_ifc_nvgre_key_bits {
 493         u8 hi[0x18];
 494         u8 lo[0x8];
 495 };
 496
 497 union mlx5_ifc_gre_key_bits {
 498         struct mlx5_ifc_nvgre_key_bits nvgre;
 499         u8 key[0x20];
 500 };
 501
 502 struct mlx5_ifc_fte_match_set_misc_bits {
 503         u8         gre_c_present[0x1];
 504         u8         reserved_at_1[0x1];
 505         u8         gre_k_present[0x1];
 506         u8         gre_s_present[0x1];
 507         u8         source_vhca_port[0x4];
 508         u8         source_sqn[0x18];
 509
 510         u8         source_eswitch_owner_vhca_id[0x10];
 511         u8         source_port[0x10];
 512
 513         u8         outer_second_prio[0x3];
 514         u8         outer_second_cfi[0x1];
 515         u8         outer_second_vid[0xc];
 516         u8         inner_second_prio[0x3];
 517         u8         inner_second_cfi[0x1];
 518         u8         inner_second_vid[0xc];
 519
 520         u8         outer_second_cvlan_tag[0x1];
 521         u8         inner_second_cvlan_tag[0x1];
 522         u8         outer_second_svlan_tag[0x1];
 523         u8         inner_second_svlan_tag[0x1];
 524         u8         reserved_at_64[0xc];
 525         u8         gre_protocol[0x10];
 526
 527         union mlx5_ifc_gre_key_bits gre_key;
 528
 529         u8         vxlan_vni[0x18];
 530         u8         reserved_at_b8[0x8];
 531
 532         u8         geneve_vni[0x18];
 533         u8         reserved_at_d8[0x7];
 534         u8         geneve_oam[0x1];
 535
 536         u8         reserved_at_e0[0xc];
 537         u8         outer_ipv6_flow_label[0x14];
 538
 539         u8         reserved_at_100[0xc];
 540         u8         inner_ipv6_flow_label[0x14];
 541
 542         u8         reserved_at_120[0xa];
 543         u8         geneve_opt_len[0x6];
 544         u8         geneve_protocol_type[0x10];
 545
 546         u8         reserved_at_140[0x8];
 547         u8         bth_dst_qp[0x18];
 548         u8         reserved_at_160[0x20];
 549         u8         outer_esp_spi[0x20];
 550         u8         reserved_at_1a0[0x60];
 551 };
 552
 553 struct mlx5_ifc_fte_match_mpls_bits {
 554         u8         mpls_label[0x14];
 555         u8         mpls_exp[0x3];
 556         u8         mpls_s_bos[0x1];
 557         u8         mpls_ttl[0x8];
 558 };
 559
 560 struct mlx5_ifc_fte_match_set_misc2_bits {
 561         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 562
 563         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 564
 565         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 566
 567         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 568
 569         u8         metadata_reg_c_7[0x20];
 570
 571         u8         metadata_reg_c_6[0x20];
 572
 573         u8         metadata_reg_c_5[0x20];
 574
 575         u8         metadata_reg_c_4[0x20];
 576
 577         u8         metadata_reg_c_3[0x20];
 578
 579         u8         metadata_reg_c_2[0x20];
 580
 581         u8         metadata_reg_c_1[0x20];
 582
 583         u8         metadata_reg_c_0[0x20];
 584
 585         u8         metadata_reg_a[0x20];
 586
 587         u8         reserved_at_1a0[0x60];
 588 };
 589
 590 struct mlx5_ifc_fte_match_set_misc3_bits {
 591         u8         inner_tcp_seq_num[0x20];
 592
 593         u8         outer_tcp_seq_num[0x20];
 594
 595         u8         inner_tcp_ack_num[0x20];
 596
 597         u8         outer_tcp_ack_num[0x20];
 598
 599         u8         reserved_at_80[0x8];
 600         u8         outer_vxlan_gpe_vni[0x18];
 601
 602         u8         outer_vxlan_gpe_next_protocol[0x8];
 603         u8         outer_vxlan_gpe_flags[0x8];
 604         u8         reserved_at_b0[0x10];
 605
 606         u8         icmp_header_data[0x20];
 607
 608         u8         icmpv6_header_data[0x20];
 609
 610         u8         icmp_type[0x8];
 611         u8         icmp_code[0x8];
 612         u8         icmpv6_type[0x8];
 613         u8         icmpv6_code[0x8];
 614
 615         u8         geneve_tlv_option_0_data[0x20];
 616
 617         u8         reserved_at_140[0xc0];
 618 };
 619
 620 struct mlx5_ifc_cmd_pas_bits {
 621         u8         pa_h[0x20];
 622
 623         u8         pa_l[0x14];
 624         u8         reserved_at_34[0xc];
 625 };
 626
 627 struct mlx5_ifc_uint64_bits {
 628         u8         hi[0x20];
 629
 630         u8         lo[0x20];
 631 };
 632
 633 enum {
 634         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 635         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 636         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 637         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 638         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 639         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 640         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 641         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 642         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 643         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 644 };
 645
 646 struct mlx5_ifc_ads_bits {
 647         u8         fl[0x1];
 648         u8         free_ar[0x1];
 649         u8         reserved_at_2[0xe];
 650         u8         pkey_index[0x10];
 651
 652         u8         reserved_at_20[0x8];
 653         u8         grh[0x1];
 654         u8         mlid[0x7];
 655         u8         rlid[0x10];
 656
 657         u8         ack_timeout[0x5];
 658         u8         reserved_at_45[0x3];
 659         u8         src_addr_index[0x8];
 660         u8         reserved_at_50[0x4];
 661         u8         stat_rate[0x4];
 662         u8         hop_limit[0x8];
 663
 664         u8         reserved_at_60[0x4];
 665         u8         tclass[0x8];
 666         u8         flow_label[0x14];
 667
 668         u8         rgid_rip[16][0x8];
 669
 670         u8         reserved_at_100[0x4];
 671         u8         f_dscp[0x1];
 672         u8         f_ecn[0x1];
 673         u8         reserved_at_106[0x1];
 674         u8         f_eth_prio[0x1];
 675         u8         ecn[0x2];
 676         u8         dscp[0x6];
 677         u8         udp_sport[0x10];
 678
 679         u8         dei_cfi[0x1];
 680         u8         eth_prio[0x3];
 681         u8         sl[0x4];
 682         u8         vhca_port_num[0x8];
 683         u8         rmac_47_32[0x10];
 684
 685         u8         rmac_31_0[0x20];
 686 };
 687
 688 struct mlx5_ifc_flow_table_nic_cap_bits {
 689         u8         nic_rx_multi_path_tirs[0x1];
 690         u8         nic_rx_multi_path_tirs_fts[0x1];
 691         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 692         u8         reserved_at_3[0x4];
 693         u8         sw_owner_reformat_supported[0x1];
 694         u8         reserved_at_8[0x18];
 695
 696         u8         encap_general_header[0x1];
 697         u8         reserved_at_21[0xa];
 698         u8         log_max_packet_reformat_context[0x5];
 699         u8         reserved_at_30[0x6];
 700         u8         max_encap_header_size[0xa];
 701         u8         reserved_at_40[0x1c0];
 702
 703         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 704
 705         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 706
 707         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 708
 709         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 710
 711         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 712
 713         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 714
 715         u8         reserved_at_e00[0x1200];
 716
 717         u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
 718
 719         u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
 720
 721         u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
 722
 723         u8         reserved_at_20c0[0x5f40];
 724 };
 725
 726 enum {
 727         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 728         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 729         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 730         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 731         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 732         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 733         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 734         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 735 };
 736
 737 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 738         u8      fdb_to_vport_reg_c_id[0x8];
 739         u8      reserved_at_8[0xd];
 740         u8      fdb_modify_header_fwd_to_table[0x1];
 741         u8      reserved_at_16[0x1];
 742         u8      flow_source[0x1];
 743         u8      reserved_at_18[0x2];
 744         u8      multi_fdb_encap[0x1];
 745         u8      egress_acl_forward_to_vport[0x1];
 746         u8      fdb_multi_path_to_table[0x1];
 747         u8      reserved_at_1d[0x3];
 748
 749         u8      reserved_at_20[0x1e0];
 750
 751         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 752
 753         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 754
 755         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 756
 757         u8      reserved_at_800[0x1000];
 758
 759         u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
 760
 761         u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
 762
 763         u8      sw_steering_uplink_icm_address_rx[0x40];
 764
 765         u8      sw_steering_uplink_icm_address_tx[0x40];
 766
 767         u8      reserved_at_1900[0x6700];
 768 };
 769
 770 enum {
 771         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 772         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 773 };
 774
 775 struct mlx5_ifc_e_switch_cap_bits {
 776         u8         vport_svlan_strip[0x1];
 777         u8         vport_cvlan_strip[0x1];
 778         u8         vport_svlan_insert[0x1];
 779         u8         vport_cvlan_insert_if_not_exist[0x1];
 780         u8         vport_cvlan_insert_overwrite[0x1];
 781         u8         reserved_at_5[0x3];
 782         u8         esw_uplink_ingress_acl[0x1];
 783         u8         reserved_at_9[0x10];
 784         u8         esw_functions_changed[0x1];
 785         u8         reserved_at_1a[0x1];
 786         u8         ecpf_vport_exists[0x1];
 787         u8         counter_eswitch_affinity[0x1];
 788         u8         merged_eswitch[0x1];
 789         u8         nic_vport_node_guid_modify[0x1];
 790         u8         nic_vport_port_guid_modify[0x1];
 791
 792         u8         vxlan_encap_decap[0x1];
 793         u8         nvgre_encap_decap[0x1];
 794         u8         reserved_at_22[0x1];
 795         u8         log_max_fdb_encap_uplink[0x5];
 796         u8         reserved_at_21[0x3];
 797         u8         log_max_packet_reformat_context[0x5];
 798         u8         reserved_2b[0x6];
 799         u8         max_encap_header_size[0xa];
 800
 801         u8         reserved_at_40[0xb];
 802         u8         log_max_esw_sf[0x5];
 803         u8         esw_sf_base_id[0x10];
 804
 805         u8         reserved_at_60[0x7a0];
 806
 807 };
 808
 809 struct mlx5_ifc_qos_cap_bits {
 810         u8         packet_pacing[0x1];
 811         u8         esw_scheduling[0x1];
 812         u8         esw_bw_share[0x1];
 813         u8         esw_rate_limit[0x1];
 814         u8         reserved_at_4[0x1];
 815         u8         packet_pacing_burst_bound[0x1];
 816         u8         packet_pacing_typical_size[0x1];
 817         u8         reserved_at_7[0x4];
 818         u8         packet_pacing_uid[0x1];
 819         u8         reserved_at_c[0x14];
 820
 821         u8         reserved_at_20[0x20];
 822
 823         u8         packet_pacing_max_rate[0x20];
 824
 825         u8         packet_pacing_min_rate[0x20];
 826
 827         u8         reserved_at_80[0x10];
 828         u8         packet_pacing_rate_table_size[0x10];
 829
 830         u8         esw_element_type[0x10];
 831         u8         esw_tsar_type[0x10];
 832
 833         u8         reserved_at_c0[0x10];
 834         u8         max_qos_para_vport[0x10];
 835
 836         u8         max_tsar_bw_share[0x20];
 837
 838         u8         reserved_at_100[0x700];
 839 };
 840
 841 struct mlx5_ifc_debug_cap_bits {
 842         u8         core_dump_general[0x1];
 843         u8         core_dump_qp[0x1];
 844         u8         reserved_at_2[0x7];
 845         u8         resource_dump[0x1];
 846         u8         reserved_at_a[0x16];
 847
 848         u8         reserved_at_20[0x2];
 849         u8         stall_detect[0x1];
 850         u8         reserved_at_23[0x1d];
 851
 852         u8         reserved_at_40[0x7c0];
 853 };
 854
 855 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 856         u8         csum_cap[0x1];
 857         u8         vlan_cap[0x1];
 858         u8         lro_cap[0x1];
 859         u8         lro_psh_flag[0x1];
 860         u8         lro_time_stamp[0x1];
 861         u8         reserved_at_5[0x2];
 862         u8         wqe_vlan_insert[0x1];
 863         u8         self_lb_en_modifiable[0x1];
 864         u8         reserved_at_9[0x2];
 865         u8         max_lso_cap[0x5];
 866         u8         multi_pkt_send_wqe[0x2];
 867         u8         wqe_inline_mode[0x2];
 868         u8         rss_ind_tbl_cap[0x4];
 869         u8         reg_umr_sq[0x1];
 870         u8         scatter_fcs[0x1];
 871         u8         enhanced_multi_pkt_send_wqe[0x1];
 872         u8         tunnel_lso_const_out_ip_id[0x1];
 873         u8         reserved_at_1c[0x2];
 874         u8         tunnel_stateless_gre[0x1];
 875         u8         tunnel_stateless_vxlan[0x1];
 876
 877         u8         swp[0x1];
 878         u8         swp_csum[0x1];
 879         u8         swp_lso[0x1];
 880         u8         cqe_checksum_full[0x1];
 881         u8         tunnel_stateless_geneve_tx[0x1];
 882         u8         tunnel_stateless_mpls_over_udp[0x1];
 883         u8         tunnel_stateless_mpls_over_gre[0x1];
 884         u8         tunnel_stateless_vxlan_gpe[0x1];
 885         u8         tunnel_stateless_ipv4_over_vxlan[0x1];
 886         u8         tunnel_stateless_ip_over_ip[0x1];
 887         u8         insert_trailer[0x1];
 888         u8         reserved_at_2b[0x5];
 889         u8         max_vxlan_udp_ports[0x8];
 890         u8         reserved_at_38[0x6];
 891         u8         max_geneve_opt_len[0x1];
 892         u8         tunnel_stateless_geneve_rx[0x1];
 893
 894         u8         reserved_at_40[0x10];
 895         u8         lro_min_mss_size[0x10];
 896
 897         u8         reserved_at_60[0x120];
 898
 899         u8         lro_timer_supported_periods[4][0x20];
 900
 901         u8         reserved_at_200[0x600];
 902 };
 903
 904 struct mlx5_ifc_roce_cap_bits {
 905         u8         roce_apm[0x1];
 906         u8         reserved_at_1[0x3];
 907         u8         sw_r_roce_src_udp_port[0x1];
 908         u8         reserved_at_5[0x1b];
 909
 910         u8         reserved_at_20[0x60];
 911
 912         u8         reserved_at_80[0xc];
 913         u8         l3_type[0x4];
 914         u8         reserved_at_90[0x8];
 915         u8         roce_version[0x8];
 916
 917         u8         reserved_at_a0[0x10];
 918         u8         r_roce_dest_udp_port[0x10];
 919
 920         u8         r_roce_max_src_udp_port[0x10];
 921         u8         r_roce_min_src_udp_port[0x10];
 922
 923         u8         reserved_at_e0[0x10];
 924         u8         roce_address_table_size[0x10];
 925
 926         u8         reserved_at_100[0x700];
 927 };
 928
 929 struct mlx5_ifc_sync_steering_in_bits {
 930         u8         opcode[0x10];
 931         u8         uid[0x10];
 932
 933         u8         reserved_at_20[0x10];
 934         u8         op_mod[0x10];
 935
 936         u8         reserved_at_40[0xc0];
 937 };
 938
 939 struct mlx5_ifc_sync_steering_out_bits {
 940         u8         status[0x8];
 941         u8         reserved_at_8[0x18];
 942
 943         u8         syndrome[0x20];
 944
 945         u8         reserved_at_40[0x40];
 946 };
 947
 948 struct mlx5_ifc_device_mem_cap_bits {
 949         u8         memic[0x1];
 950         u8         reserved_at_1[0x1f];
 951
 952         u8         reserved_at_20[0xb];
 953         u8         log_min_memic_alloc_size[0x5];
 954         u8         reserved_at_30[0x8];
 955         u8         log_max_memic_addr_alignment[0x8];
 956
 957         u8         memic_bar_start_addr[0x40];
 958
 959         u8         memic_bar_size[0x20];
 960
 961         u8         max_memic_size[0x20];
 962
 963         u8         steering_sw_icm_start_address[0x40];
 964
 965         u8         reserved_at_100[0x8];
 966         u8         log_header_modify_sw_icm_size[0x8];
 967         u8         reserved_at_110[0x2];
 968         u8         log_sw_icm_alloc_granularity[0x6];
 969         u8         log_steering_sw_icm_size[0x8];
 970
 971         u8         reserved_at_120[0x20];
 972
 973         u8         header_modify_sw_icm_start_address[0x40];
 974
 975         u8         reserved_at_180[0x680];
 976 };
 977
 978 struct mlx5_ifc_device_event_cap_bits {
 979         u8         user_affiliated_events[4][0x40];
 980
 981         u8         user_unaffiliated_events[4][0x40];
 982 };
 983
 984 struct mlx5_ifc_device_virtio_emulation_cap_bits {
 985         u8         reserved_at_0[0x20];
 986
 987         u8         reserved_at_20[0x13];
 988         u8         log_doorbell_stride[0x5];
 989         u8         reserved_at_38[0x3];
 990         u8         log_doorbell_bar_size[0x5];
 991
 992         u8         doorbell_bar_offset[0x40];
 993
 994         u8         reserved_at_80[0x780];
 995 };
 996
 997 enum {
 998         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 999         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1000         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1001         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1002         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1003         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1004         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1005         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1006         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1007 };
1008
1009 enum {
1010         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1011         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1012         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1013         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1014         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1015         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1016         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1017         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1018         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1019 };
1020
1021 struct mlx5_ifc_atomic_caps_bits {
1022         u8         reserved_at_0[0x40];
1023
1024         u8         atomic_req_8B_endianness_mode[0x2];
1025         u8         reserved_at_42[0x4];
1026         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1027
1028         u8         reserved_at_47[0x19];
1029
1030         u8         reserved_at_60[0x20];
1031
1032         u8         reserved_at_80[0x10];
1033         u8         atomic_operations[0x10];
1034
1035         u8         reserved_at_a0[0x10];
1036         u8         atomic_size_qp[0x10];
1037
1038         u8         reserved_at_c0[0x10];
1039         u8         atomic_size_dc[0x10];
1040
1041         u8         reserved_at_e0[0x720];
1042 };
1043
1044 struct mlx5_ifc_odp_cap_bits {
1045         u8         reserved_at_0[0x40];
1046
1047         u8         sig[0x1];
1048         u8         reserved_at_41[0x1f];
1049
1050         u8         reserved_at_60[0x20];
1051
1052         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1053
1054         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1055
1056         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1057
1058         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1059
1060         struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1061
1062         u8         reserved_at_120[0x6E0];
1063 };
1064
1065 struct mlx5_ifc_calc_op {
1066         u8        reserved_at_0[0x10];
1067         u8        reserved_at_10[0x9];
1068         u8        op_swap_endianness[0x1];
1069         u8        op_min[0x1];
1070         u8        op_xor[0x1];
1071         u8        op_or[0x1];
1072         u8        op_and[0x1];
1073         u8        op_max[0x1];
1074         u8        op_add[0x1];
1075 };
1076
1077 struct mlx5_ifc_vector_calc_cap_bits {
1078         u8         calc_matrix[0x1];
1079         u8         reserved_at_1[0x1f];
1080         u8         reserved_at_20[0x8];
1081         u8         max_vec_count[0x8];
1082         u8         reserved_at_30[0xd];
1083         u8         max_chunk_size[0x3];
1084         struct mlx5_ifc_calc_op calc0;
1085         struct mlx5_ifc_calc_op calc1;
1086         struct mlx5_ifc_calc_op calc2;
1087         struct mlx5_ifc_calc_op calc3;
1088
1089         u8         reserved_at_c0[0x720];
1090 };
1091
1092 struct mlx5_ifc_tls_cap_bits {
1093         u8         tls_1_2_aes_gcm_128[0x1];
1094         u8         tls_1_3_aes_gcm_128[0x1];
1095         u8         tls_1_2_aes_gcm_256[0x1];
1096         u8         tls_1_3_aes_gcm_256[0x1];
1097         u8         reserved_at_4[0x1c];
1098
1099         u8         reserved_at_20[0x7e0];
1100 };
1101
1102 struct mlx5_ifc_ipsec_cap_bits {
1103         u8         ipsec_full_offload[0x1];
1104         u8         ipsec_crypto_offload[0x1];
1105         u8         ipsec_esn[0x1];
1106         u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1107         u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1108         u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1109         u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1110         u8         reserved_at_7[0x4];
1111         u8         log_max_ipsec_offload[0x5];
1112         u8         reserved_at_10[0x10];
1113
1114         u8         min_log_ipsec_full_replay_window[0x8];
1115         u8         max_log_ipsec_full_replay_window[0x8];
1116         u8         reserved_at_30[0x7d0];
1117 };
1118
1119 enum {
1120         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1121         MLX5_WQ_TYPE_CYCLIC       = 0x1,
1122         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1123         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1124 };
1125
1126 enum {
1127         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1128         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1129 };
1130
1131 enum {
1132         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1133         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1134         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1135         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1136         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1137 };
1138
1139 enum {
1140         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1141         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1142         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1143         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1144         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1145         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1146 };
1147
1148 enum {
1149         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1150         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1151 };
1152
1153 enum {
1154         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1155         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1156         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1157 };
1158
1159 enum {
1160         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1161         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1162 };
1163
1164 enum {
1165         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1166         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1167         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1168 };
1169
1170 enum {
1171         MLX5_FLEX_PARSER_GENEVE_ENABLED         = 1 << 3,
1172         MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED      = 1 << 7,
1173         MLX5_FLEX_PARSER_ICMP_V4_ENABLED        = 1 << 8,
1174         MLX5_FLEX_PARSER_ICMP_V6_ENABLED        = 1 << 9,
1175 };
1176
1177 enum {
1178         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1179         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1180 };
1181
1182 #define MLX5_FC_BULK_SIZE_FACTOR 128
1183
1184 enum mlx5_fc_bulk_alloc_bitmask {
1185         MLX5_FC_BULK_128   = (1 << 0),
1186         MLX5_FC_BULK_256   = (1 << 1),
1187         MLX5_FC_BULK_512   = (1 << 2),
1188         MLX5_FC_BULK_1024  = (1 << 3),
1189         MLX5_FC_BULK_2048  = (1 << 4),
1190         MLX5_FC_BULK_4096  = (1 << 5),
1191         MLX5_FC_BULK_8192  = (1 << 6),
1192         MLX5_FC_BULK_16384 = (1 << 7),
1193 };
1194
1195 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1196
1197 struct mlx5_ifc_cmd_hca_cap_bits {
1198         u8         reserved_at_0[0x30];
1199         u8         vhca_id[0x10];
1200
1201         u8         reserved_at_40[0x40];
1202
1203         u8         log_max_srq_sz[0x8];
1204         u8         log_max_qp_sz[0x8];
1205         u8         event_cap[0x1];
1206         u8         reserved_at_91[0x7];
1207         u8         prio_tag_required[0x1];
1208         u8         reserved_at_99[0x2];
1209         u8         log_max_qp[0x5];
1210
1211         u8         reserved_at_a0[0x3];
1212         u8         ece_support[0x1];
1213         u8         reserved_at_a4[0x7];
1214         u8         log_max_srq[0x5];
1215         u8         reserved_at_b0[0x10];
1216
1217         u8         max_sgl_for_optimized_performance[0x8];
1218         u8         log_max_cq_sz[0x8];
1219         u8         reserved_at_d0[0xb];
1220         u8         log_max_cq[0x5];
1221
1222         u8         log_max_eq_sz[0x8];
1223         u8         relaxed_ordering_write[0x1];
1224         u8         relaxed_ordering_read[0x1];
1225         u8         log_max_mkey[0x6];
1226         u8         reserved_at_f0[0x8];
1227         u8         dump_fill_mkey[0x1];
1228         u8         reserved_at_f9[0x2];
1229         u8         fast_teardown[0x1];
1230         u8         log_max_eq[0x4];
1231
1232         u8         max_indirection[0x8];
1233         u8         fixed_buffer_size[0x1];
1234         u8         log_max_mrw_sz[0x7];
1235         u8         force_teardown[0x1];
1236         u8         reserved_at_111[0x1];
1237         u8         log_max_bsf_list_size[0x6];
1238         u8         umr_extended_translation_offset[0x1];
1239         u8         null_mkey[0x1];
1240         u8         log_max_klm_list_size[0x6];
1241
1242         u8         reserved_at_120[0xa];
1243         u8         log_max_ra_req_dc[0x6];
1244         u8         reserved_at_130[0xa];
1245         u8         log_max_ra_res_dc[0x6];
1246
1247         u8         reserved_at_140[0x6];
1248         u8         release_all_pages[0x1];
1249         u8         reserved_at_147[0x2];
1250         u8         roce_accl[0x1];
1251         u8         log_max_ra_req_qp[0x6];
1252         u8         reserved_at_150[0xa];
1253         u8         log_max_ra_res_qp[0x6];
1254
1255         u8         end_pad[0x1];
1256         u8         cc_query_allowed[0x1];
1257         u8         cc_modify_allowed[0x1];
1258         u8         start_pad[0x1];
1259         u8         cache_line_128byte[0x1];
1260         u8         reserved_at_165[0x4];
1261         u8         rts2rts_qp_counters_set_id[0x1];
1262         u8         reserved_at_16a[0x2];
1263         u8         vnic_env_int_rq_oob[0x1];
1264         u8         sbcam_reg[0x1];
1265         u8         reserved_at_16e[0x1];
1266         u8         qcam_reg[0x1];
1267         u8         gid_table_size[0x10];
1268
1269         u8         out_of_seq_cnt[0x1];
1270         u8         vport_counters[0x1];
1271         u8         retransmission_q_counters[0x1];
1272         u8         debug[0x1];
1273         u8         modify_rq_counter_set_id[0x1];
1274         u8         rq_delay_drop[0x1];
1275         u8         max_qp_cnt[0xa];
1276         u8         pkey_table_size[0x10];
1277
1278         u8         vport_group_manager[0x1];
1279         u8         vhca_group_manager[0x1];
1280         u8         ib_virt[0x1];
1281         u8         eth_virt[0x1];
1282         u8         vnic_env_queue_counters[0x1];
1283         u8         ets[0x1];
1284         u8         nic_flow_table[0x1];
1285         u8         eswitch_manager[0x1];
1286         u8         device_memory[0x1];
1287         u8         mcam_reg[0x1];
1288         u8         pcam_reg[0x1];
1289         u8         local_ca_ack_delay[0x5];
1290         u8         port_module_event[0x1];
1291         u8         enhanced_error_q_counters[0x1];
1292         u8         ports_check[0x1];
1293         u8         reserved_at_1b3[0x1];
1294         u8         disable_link_up[0x1];
1295         u8         beacon_led[0x1];
1296         u8         port_type[0x2];
1297         u8         num_ports[0x8];
1298
1299         u8         reserved_at_1c0[0x1];
1300         u8         pps[0x1];
1301         u8         pps_modify[0x1];
1302         u8         log_max_msg[0x5];
1303         u8         reserved_at_1c8[0x4];
1304         u8         max_tc[0x4];
1305         u8         temp_warn_event[0x1];
1306         u8         dcbx[0x1];
1307         u8         general_notification_event[0x1];
1308         u8         reserved_at_1d3[0x2];
1309         u8         fpga[0x1];
1310         u8         rol_s[0x1];
1311         u8         rol_g[0x1];
1312         u8         reserved_at_1d8[0x1];
1313         u8         wol_s[0x1];
1314         u8         wol_g[0x1];
1315         u8         wol_a[0x1];
1316         u8         wol_b[0x1];
1317         u8         wol_m[0x1];
1318         u8         wol_u[0x1];
1319         u8         wol_p[0x1];
1320
1321         u8         stat_rate_support[0x10];
1322         u8         reserved_at_1f0[0x1];
1323         u8         pci_sync_for_fw_update_event[0x1];
1324         u8         reserved_at_1f2[0x6];
1325         u8         init2_lag_tx_port_affinity[0x1];
1326         u8         reserved_at_1fa[0x3];
1327         u8         cqe_version[0x4];
1328
1329         u8         compact_address_vector[0x1];
1330         u8         striding_rq[0x1];
1331         u8         reserved_at_202[0x1];
1332         u8         ipoib_enhanced_offloads[0x1];
1333         u8         ipoib_basic_offloads[0x1];
1334         u8         reserved_at_205[0x1];
1335         u8         repeated_block_disabled[0x1];
1336         u8         umr_modify_entity_size_disabled[0x1];
1337         u8         umr_modify_atomic_disabled[0x1];
1338         u8         umr_indirect_mkey_disabled[0x1];
1339         u8         umr_fence[0x2];
1340         u8         dc_req_scat_data_cqe[0x1];
1341         u8         reserved_at_20d[0x2];
1342         u8         drain_sigerr[0x1];
1343         u8         cmdif_checksum[0x2];
1344         u8         sigerr_cqe[0x1];
1345         u8         reserved_at_213[0x1];
1346         u8         wq_signature[0x1];
1347         u8         sctr_data_cqe[0x1];
1348         u8         reserved_at_216[0x1];
1349         u8         sho[0x1];
1350         u8         tph[0x1];
1351         u8         rf[0x1];
1352         u8         dct[0x1];
1353         u8         qos[0x1];
1354         u8         eth_net_offloads[0x1];
1355         u8         roce[0x1];
1356         u8         atomic[0x1];
1357         u8         reserved_at_21f[0x1];
1358
1359         u8         cq_oi[0x1];
1360         u8         cq_resize[0x1];
1361         u8         cq_moderation[0x1];
1362         u8         reserved_at_223[0x3];
1363         u8         cq_eq_remap[0x1];
1364         u8         pg[0x1];
1365         u8         block_lb_mc[0x1];
1366         u8         reserved_at_229[0x1];
1367         u8         scqe_break_moderation[0x1];
1368         u8         cq_period_start_from_cqe[0x1];
1369         u8         cd[0x1];
1370         u8         reserved_at_22d[0x1];
1371         u8         apm[0x1];
1372         u8         vector_calc[0x1];
1373         u8         umr_ptr_rlky[0x1];
1374         u8         imaicl[0x1];
1375         u8         qp_packet_based[0x1];
1376         u8         reserved_at_233[0x3];
1377         u8         qkv[0x1];
1378         u8         pkv[0x1];
1379         u8         set_deth_sqpn[0x1];
1380         u8         reserved_at_239[0x3];
1381         u8         xrc[0x1];
1382         u8         ud[0x1];
1383         u8         uc[0x1];
1384         u8         rc[0x1];
1385
1386         u8         uar_4k[0x1];
1387         u8         reserved_at_241[0x9];
1388         u8         uar_sz[0x6];
1389         u8         reserved_at_250[0x8];
1390         u8         log_pg_sz[0x8];
1391
1392         u8         bf[0x1];
1393         u8         driver_version[0x1];
1394         u8         pad_tx_eth_packet[0x1];
1395         u8         reserved_at_263[0x8];
1396         u8         log_bf_reg_size[0x5];
1397
1398         u8         reserved_at_270[0x8];
1399         u8         lag_tx_port_affinity[0x1];
1400         u8         reserved_at_279[0x2];
1401         u8         lag_master[0x1];
1402         u8         num_lag_ports[0x4];
1403
1404         u8         reserved_at_280[0x10];
1405         u8         max_wqe_sz_sq[0x10];
1406
1407         u8         reserved_at_2a0[0x10];
1408         u8         max_wqe_sz_rq[0x10];
1409
1410         u8         max_flow_counter_31_16[0x10];
1411         u8         max_wqe_sz_sq_dc[0x10];
1412
1413         u8         reserved_at_2e0[0x7];
1414         u8         max_qp_mcg[0x19];
1415
1416         u8         reserved_at_300[0x10];
1417         u8         flow_counter_bulk_alloc[0x8];
1418         u8         log_max_mcg[0x8];
1419
1420         u8         reserved_at_320[0x3];
1421         u8         log_max_transport_domain[0x5];
1422         u8         reserved_at_328[0x3];
1423         u8         log_max_pd[0x5];
1424         u8         reserved_at_330[0xb];
1425         u8         log_max_xrcd[0x5];
1426
1427         u8         nic_receive_steering_discard[0x1];
1428         u8         receive_discard_vport_down[0x1];
1429         u8         transmit_discard_vport_down[0x1];
1430         u8         reserved_at_343[0x5];
1431         u8         log_max_flow_counter_bulk[0x8];
1432         u8         max_flow_counter_15_0[0x10];
1433
1434
1435         u8         reserved_at_360[0x3];
1436         u8         log_max_rq[0x5];
1437         u8         reserved_at_368[0x3];
1438         u8         log_max_sq[0x5];
1439         u8         reserved_at_370[0x3];
1440         u8         log_max_tir[0x5];
1441         u8         reserved_at_378[0x3];
1442         u8         log_max_tis[0x5];
1443
1444         u8         basic_cyclic_rcv_wqe[0x1];
1445         u8         reserved_at_381[0x2];
1446         u8         log_max_rmp[0x5];
1447         u8         reserved_at_388[0x3];
1448         u8         log_max_rqt[0x5];
1449         u8         reserved_at_390[0x3];
1450         u8         log_max_rqt_size[0x5];
1451         u8         reserved_at_398[0x3];
1452         u8         log_max_tis_per_sq[0x5];
1453
1454         u8         ext_stride_num_range[0x1];
1455         u8         reserved_at_3a1[0x2];
1456         u8         log_max_stride_sz_rq[0x5];
1457         u8         reserved_at_3a8[0x3];
1458         u8         log_min_stride_sz_rq[0x5];
1459         u8         reserved_at_3b0[0x3];
1460         u8         log_max_stride_sz_sq[0x5];
1461         u8         reserved_at_3b8[0x3];
1462         u8         log_min_stride_sz_sq[0x5];
1463
1464         u8         hairpin[0x1];
1465         u8         reserved_at_3c1[0x2];
1466         u8         log_max_hairpin_queues[0x5];
1467         u8         reserved_at_3c8[0x3];
1468         u8         log_max_hairpin_wq_data_sz[0x5];
1469         u8         reserved_at_3d0[0x3];
1470         u8         log_max_hairpin_num_packets[0x5];
1471         u8         reserved_at_3d8[0x3];
1472         u8         log_max_wq_sz[0x5];
1473
1474         u8         nic_vport_change_event[0x1];
1475         u8         disable_local_lb_uc[0x1];
1476         u8         disable_local_lb_mc[0x1];
1477         u8         log_min_hairpin_wq_data_sz[0x5];
1478         u8         reserved_at_3e8[0x3];
1479         u8         log_max_vlan_list[0x5];
1480         u8         reserved_at_3f0[0x3];
1481         u8         log_max_current_mc_list[0x5];
1482         u8         reserved_at_3f8[0x3];
1483         u8         log_max_current_uc_list[0x5];
1484
1485         u8         general_obj_types[0x40];
1486
1487         u8         reserved_at_440[0x20];
1488
1489         u8         reserved_at_460[0x3];
1490         u8         log_max_uctx[0x5];
1491         u8         reserved_at_468[0x2];
1492         u8         ipsec_offload[0x1];
1493         u8         log_max_umem[0x5];
1494         u8         max_num_eqs[0x10];
1495
1496         u8         reserved_at_480[0x1];
1497         u8         tls_tx[0x1];
1498         u8         tls_rx[0x1];
1499         u8         log_max_l2_table[0x5];
1500         u8         reserved_at_488[0x8];
1501         u8         log_uar_page_sz[0x10];
1502
1503         u8         reserved_at_4a0[0x20];
1504         u8         device_frequency_mhz[0x20];
1505         u8         device_frequency_khz[0x20];
1506
1507         u8         reserved_at_500[0x20];
1508         u8         num_of_uars_per_page[0x20];
1509
1510         u8         flex_parser_protocols[0x20];
1511
1512         u8         max_geneve_tlv_options[0x8];
1513         u8         reserved_at_568[0x3];
1514         u8         max_geneve_tlv_option_data_len[0x5];
1515         u8         reserved_at_570[0x10];
1516
1517         u8         reserved_at_580[0x33];
1518         u8         log_max_dek[0x5];
1519         u8         reserved_at_5b8[0x4];
1520         u8         mini_cqe_resp_stride_index[0x1];
1521         u8         cqe_128_always[0x1];
1522         u8         cqe_compression_128[0x1];
1523         u8         cqe_compression[0x1];
1524
1525         u8         cqe_compression_timeout[0x10];
1526         u8         cqe_compression_max_num[0x10];
1527
1528         u8         reserved_at_5e0[0x10];
1529         u8         tag_matching[0x1];
1530         u8         rndv_offload_rc[0x1];
1531         u8         rndv_offload_dc[0x1];
1532         u8         log_tag_matching_list_sz[0x5];
1533         u8         reserved_at_5f8[0x3];
1534         u8         log_max_xrq[0x5];
1535
1536         u8         affiliate_nic_vport_criteria[0x8];
1537         u8         native_port_num[0x8];
1538         u8         num_vhca_ports[0x8];
1539         u8         reserved_at_618[0x6];
1540         u8         sw_owner_id[0x1];
1541         u8         reserved_at_61f[0x1];
1542
1543         u8         max_num_of_monitor_counters[0x10];
1544         u8         num_ppcnt_monitor_counters[0x10];
1545
1546         u8         reserved_at_640[0x10];
1547         u8         num_q_monitor_counters[0x10];
1548
1549         u8         reserved_at_660[0x20];
1550
1551         u8         sf[0x1];
1552         u8         sf_set_partition[0x1];
1553         u8         reserved_at_682[0x1];
1554         u8         log_max_sf[0x5];
1555         u8         reserved_at_688[0x8];
1556         u8         log_min_sf_size[0x8];
1557         u8         max_num_sf_partitions[0x8];
1558
1559         u8         uctx_cap[0x20];
1560
1561         u8         reserved_at_6c0[0x4];
1562         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1563         u8         flex_parser_id_icmp_dw1[0x4];
1564         u8         flex_parser_id_icmp_dw0[0x4];
1565         u8         flex_parser_id_icmpv6_dw1[0x4];
1566         u8         flex_parser_id_icmpv6_dw0[0x4];
1567         u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1568         u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1569
1570         u8         reserved_at_6e0[0x10];
1571         u8         sf_base_id[0x10];
1572
1573         u8         reserved_at_700[0x80];
1574         u8         vhca_tunnel_commands[0x40];
1575         u8         reserved_at_7c0[0x40];
1576 };
1577
1578 enum mlx5_flow_destination_type {
1579         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1580         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1581         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1582
1583         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1584         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1585         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1586 };
1587
1588 enum mlx5_flow_table_miss_action {
1589         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1590         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1591         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1592 };
1593
1594 struct mlx5_ifc_dest_format_struct_bits {
1595         u8         destination_type[0x8];
1596         u8         destination_id[0x18];
1597
1598         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1599         u8         packet_reformat[0x1];
1600         u8         reserved_at_22[0xe];
1601         u8         destination_eswitch_owner_vhca_id[0x10];
1602 };
1603
1604 struct mlx5_ifc_flow_counter_list_bits {
1605         u8         flow_counter_id[0x20];
1606
1607         u8         reserved_at_20[0x20];
1608 };
1609
1610 struct mlx5_ifc_extended_dest_format_bits {
1611         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1612
1613         u8         packet_reformat_id[0x20];
1614
1615         u8         reserved_at_60[0x20];
1616 };
1617
1618 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1619         struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1620         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1621 };
1622
1623 struct mlx5_ifc_fte_match_param_bits {
1624         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1625
1626         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1627
1628         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1629
1630         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1631
1632         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1633
1634         u8         reserved_at_a00[0x600];
1635 };
1636
1637 enum {
1638         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1639         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1640         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1641         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1642         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1643 };
1644
1645 struct mlx5_ifc_rx_hash_field_select_bits {
1646         u8         l3_prot_type[0x1];
1647         u8         l4_prot_type[0x1];
1648         u8         selected_fields[0x1e];
1649 };
1650
1651 enum {
1652         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1653         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1654 };
1655
1656 enum {
1657         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1658         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1659 };
1660
1661 struct mlx5_ifc_wq_bits {
1662         u8         wq_type[0x4];
1663         u8         wq_signature[0x1];
1664         u8         end_padding_mode[0x2];
1665         u8         cd_slave[0x1];
1666         u8         reserved_at_8[0x18];
1667
1668         u8         hds_skip_first_sge[0x1];
1669         u8         log2_hds_buf_size[0x3];
1670         u8         reserved_at_24[0x7];
1671         u8         page_offset[0x5];
1672         u8         lwm[0x10];
1673
1674         u8         reserved_at_40[0x8];
1675         u8         pd[0x18];
1676
1677         u8         reserved_at_60[0x8];
1678         u8         uar_page[0x18];
1679
1680         u8         dbr_addr[0x40];
1681
1682         u8         hw_counter[0x20];
1683
1684         u8         sw_counter[0x20];
1685
1686         u8         reserved_at_100[0xc];
1687         u8         log_wq_stride[0x4];
1688         u8         reserved_at_110[0x3];
1689         u8         log_wq_pg_sz[0x5];
1690         u8         reserved_at_118[0x3];
1691         u8         log_wq_sz[0x5];
1692
1693         u8         dbr_umem_valid[0x1];
1694         u8         wq_umem_valid[0x1];
1695         u8         reserved_at_122[0x1];
1696         u8         log_hairpin_num_packets[0x5];
1697         u8         reserved_at_128[0x3];
1698         u8         log_hairpin_data_sz[0x5];
1699
1700         u8         reserved_at_130[0x4];
1701         u8         log_wqe_num_of_strides[0x4];
1702         u8         two_byte_shift_en[0x1];
1703         u8         reserved_at_139[0x4];
1704         u8         log_wqe_stride_size[0x3];
1705
1706         u8         reserved_at_140[0x4c0];
1707
1708         struct mlx5_ifc_cmd_pas_bits pas[];
1709 };
1710
1711 struct mlx5_ifc_rq_num_bits {
1712         u8         reserved_at_0[0x8];
1713         u8         rq_num[0x18];
1714 };
1715
1716 struct mlx5_ifc_mac_address_layout_bits {
1717         u8         reserved_at_0[0x10];
1718         u8         mac_addr_47_32[0x10];
1719
1720         u8         mac_addr_31_0[0x20];
1721 };
1722
1723 struct mlx5_ifc_vlan_layout_bits {
1724         u8         reserved_at_0[0x14];
1725         u8         vlan[0x0c];
1726
1727         u8         reserved_at_20[0x20];
1728 };
1729
1730 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1731         u8         reserved_at_0[0xa0];
1732
1733         u8         min_time_between_cnps[0x20];
1734
1735         u8         reserved_at_c0[0x12];
1736         u8         cnp_dscp[0x6];
1737         u8         reserved_at_d8[0x4];
1738         u8         cnp_prio_mode[0x1];
1739         u8         cnp_802p_prio[0x3];
1740
1741         u8         reserved_at_e0[0x720];
1742 };
1743
1744 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1745         u8         reserved_at_0[0x60];
1746
1747         u8         reserved_at_60[0x4];
1748         u8         clamp_tgt_rate[0x1];
1749         u8         reserved_at_65[0x3];
1750         u8         clamp_tgt_rate_after_time_inc[0x1];
1751         u8         reserved_at_69[0x17];
1752
1753         u8         reserved_at_80[0x20];
1754
1755         u8         rpg_time_reset[0x20];
1756
1757         u8         rpg_byte_reset[0x20];
1758
1759         u8         rpg_threshold[0x20];
1760
1761         u8         rpg_max_rate[0x20];
1762
1763         u8         rpg_ai_rate[0x20];
1764
1765         u8         rpg_hai_rate[0x20];
1766
1767         u8         rpg_gd[0x20];
1768
1769         u8         rpg_min_dec_fac[0x20];
1770
1771         u8         rpg_min_rate[0x20];
1772
1773         u8         reserved_at_1c0[0xe0];
1774
1775         u8         rate_to_set_on_first_cnp[0x20];
1776
1777         u8         dce_tcp_g[0x20];
1778
1779         u8         dce_tcp_rtt[0x20];
1780
1781         u8         rate_reduce_monitor_period[0x20];
1782
1783         u8         reserved_at_320[0x20];
1784
1785         u8         initial_alpha_value[0x20];
1786
1787         u8         reserved_at_360[0x4a0];
1788 };
1789
1790 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1791         u8         reserved_at_0[0x80];
1792
1793         u8         rppp_max_rps[0x20];
1794
1795         u8         rpg_time_reset[0x20];
1796
1797         u8         rpg_byte_reset[0x20];
1798
1799         u8         rpg_threshold[0x20];
1800
1801         u8         rpg_max_rate[0x20];
1802
1803         u8         rpg_ai_rate[0x20];
1804
1805         u8         rpg_hai_rate[0x20];
1806
1807         u8         rpg_gd[0x20];
1808
1809         u8         rpg_min_dec_fac[0x20];
1810
1811         u8         rpg_min_rate[0x20];
1812
1813         u8         reserved_at_1c0[0x640];
1814 };
1815
1816 enum {
1817         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1818         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1819         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1820 };
1821
1822 struct mlx5_ifc_resize_field_select_bits {
1823         u8         resize_field_select[0x20];
1824 };
1825
1826 struct mlx5_ifc_resource_dump_bits {
1827         u8         more_dump[0x1];
1828         u8         inline_dump[0x1];
1829         u8         reserved_at_2[0xa];
1830         u8         seq_num[0x4];
1831         u8         segment_type[0x10];
1832
1833         u8         reserved_at_20[0x10];
1834         u8         vhca_id[0x10];
1835
1836         u8         index1[0x20];
1837
1838         u8         index2[0x20];
1839
1840         u8         num_of_obj1[0x10];
1841         u8         num_of_obj2[0x10];
1842
1843         u8         reserved_at_a0[0x20];
1844
1845         u8         device_opaque[0x40];
1846
1847         u8         mkey[0x20];
1848
1849         u8         size[0x20];
1850
1851         u8         address[0x40];
1852
1853         u8         inline_data[52][0x20];
1854 };
1855
1856 struct mlx5_ifc_resource_dump_menu_record_bits {
1857         u8         reserved_at_0[0x4];
1858         u8         num_of_obj2_supports_active[0x1];
1859         u8         num_of_obj2_supports_all[0x1];
1860         u8         must_have_num_of_obj2[0x1];
1861         u8         support_num_of_obj2[0x1];
1862         u8         num_of_obj1_supports_active[0x1];
1863         u8         num_of_obj1_supports_all[0x1];
1864         u8         must_have_num_of_obj1[0x1];
1865         u8         support_num_of_obj1[0x1];
1866         u8         must_have_index2[0x1];
1867         u8         support_index2[0x1];
1868         u8         must_have_index1[0x1];
1869         u8         support_index1[0x1];
1870         u8         segment_type[0x10];
1871
1872         u8         segment_name[4][0x20];
1873
1874         u8         index1_name[4][0x20];
1875
1876         u8         index2_name[4][0x20];
1877 };
1878
1879 struct mlx5_ifc_resource_dump_segment_header_bits {
1880         u8         length_dw[0x10];
1881         u8         segment_type[0x10];
1882 };
1883
1884 struct mlx5_ifc_resource_dump_command_segment_bits {
1885         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1886
1887         u8         segment_called[0x10];
1888         u8         vhca_id[0x10];
1889
1890         u8         index1[0x20];
1891
1892         u8         index2[0x20];
1893
1894         u8         num_of_obj1[0x10];
1895         u8         num_of_obj2[0x10];
1896 };
1897
1898 struct mlx5_ifc_resource_dump_error_segment_bits {
1899         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1900
1901         u8         reserved_at_20[0x10];
1902         u8         syndrome_id[0x10];
1903
1904         u8         reserved_at_40[0x40];
1905
1906         u8         error[8][0x20];
1907 };
1908
1909 struct mlx5_ifc_resource_dump_info_segment_bits {
1910         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1911
1912         u8         reserved_at_20[0x18];
1913         u8         dump_version[0x8];
1914
1915         u8         hw_version[0x20];
1916
1917         u8         fw_version[0x20];
1918 };
1919
1920 struct mlx5_ifc_resource_dump_menu_segment_bits {
1921         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1922
1923         u8         reserved_at_20[0x10];
1924         u8         num_of_records[0x10];
1925
1926         struct mlx5_ifc_resource_dump_menu_record_bits record[];
1927 };
1928
1929 struct mlx5_ifc_resource_dump_resource_segment_bits {
1930         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1931
1932         u8         reserved_at_20[0x20];
1933
1934         u8         index1[0x20];
1935
1936         u8         index2[0x20];
1937
1938         u8         payload[][0x20];
1939 };
1940
1941 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1942         struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1943 };
1944
1945 struct mlx5_ifc_menu_resource_dump_response_bits {
1946         struct mlx5_ifc_resource_dump_info_segment_bits info;
1947         struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1948         struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1949         struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1950 };
1951
1952 enum {
1953         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1954         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1955         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1956         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1957 };
1958
1959 struct mlx5_ifc_modify_field_select_bits {
1960         u8         modify_field_select[0x20];
1961 };
1962
1963 struct mlx5_ifc_field_select_r_roce_np_bits {
1964         u8         field_select_r_roce_np[0x20];
1965 };
1966
1967 struct mlx5_ifc_field_select_r_roce_rp_bits {
1968         u8         field_select_r_roce_rp[0x20];
1969 };
1970
1971 enum {
1972         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1973         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1974         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1975         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1976         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1977         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1978         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1979         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1980         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1981         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1982 };
1983
1984 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1985         u8         field_select_8021qaurp[0x20];
1986 };
1987
1988 struct mlx5_ifc_phys_layer_cntrs_bits {
1989         u8         time_since_last_clear_high[0x20];
1990
1991         u8         time_since_last_clear_low[0x20];
1992
1993         u8         symbol_errors_high[0x20];
1994
1995         u8         symbol_errors_low[0x20];
1996
1997         u8         sync_headers_errors_high[0x20];
1998
1999         u8         sync_headers_errors_low[0x20];
2000
2001         u8         edpl_bip_errors_lane0_high[0x20];
2002
2003         u8         edpl_bip_errors_lane0_low[0x20];
2004
2005         u8         edpl_bip_errors_lane1_high[0x20];
2006
2007         u8         edpl_bip_errors_lane1_low[0x20];
2008
2009         u8         edpl_bip_errors_lane2_high[0x20];
2010
2011         u8         edpl_bip_errors_lane2_low[0x20];
2012
2013         u8         edpl_bip_errors_lane3_high[0x20];
2014
2015         u8         edpl_bip_errors_lane3_low[0x20];
2016
2017         u8         fc_fec_corrected_blocks_lane0_high[0x20];
2018
2019         u8         fc_fec_corrected_blocks_lane0_low[0x20];
2020
2021         u8         fc_fec_corrected_blocks_lane1_high[0x20];
2022
2023         u8         fc_fec_corrected_blocks_lane1_low[0x20];
2024
2025         u8         fc_fec_corrected_blocks_lane2_high[0x20];
2026
2027         u8         fc_fec_corrected_blocks_lane2_low[0x20];
2028
2029         u8         fc_fec_corrected_blocks_lane3_high[0x20];
2030
2031         u8         fc_fec_corrected_blocks_lane3_low[0x20];
2032
2033         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2034
2035         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2036
2037         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2038
2039         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2040
2041         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2042
2043         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2044
2045         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2046
2047         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2048
2049         u8         rs_fec_corrected_blocks_high[0x20];
2050
2051         u8         rs_fec_corrected_blocks_low[0x20];
2052
2053         u8         rs_fec_uncorrectable_blocks_high[0x20];
2054
2055         u8         rs_fec_uncorrectable_blocks_low[0x20];
2056
2057         u8         rs_fec_no_errors_blocks_high[0x20];
2058
2059         u8         rs_fec_no_errors_blocks_low[0x20];
2060
2061         u8         rs_fec_single_error_blocks_high[0x20];
2062
2063         u8         rs_fec_single_error_blocks_low[0x20];
2064
2065         u8         rs_fec_corrected_symbols_total_high[0x20];
2066
2067         u8         rs_fec_corrected_symbols_total_low[0x20];
2068
2069         u8         rs_fec_corrected_symbols_lane0_high[0x20];
2070
2071         u8         rs_fec_corrected_symbols_lane0_low[0x20];
2072
2073         u8         rs_fec_corrected_symbols_lane1_high[0x20];
2074
2075         u8         rs_fec_corrected_symbols_lane1_low[0x20];
2076
2077         u8         rs_fec_corrected_symbols_lane2_high[0x20];
2078
2079         u8         rs_fec_corrected_symbols_lane2_low[0x20];
2080
2081         u8         rs_fec_corrected_symbols_lane3_high[0x20];
2082
2083         u8         rs_fec_corrected_symbols_lane3_low[0x20];
2084
2085         u8         link_down_events[0x20];
2086
2087         u8         successful_recovery_events[0x20];
2088
2089         u8         reserved_at_640[0x180];
2090 };
2091
2092 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2093         u8         time_since_last_clear_high[0x20];
2094
2095         u8         time_since_last_clear_low[0x20];
2096
2097         u8         phy_received_bits_high[0x20];
2098
2099         u8         phy_received_bits_low[0x20];
2100
2101         u8         phy_symbol_errors_high[0x20];
2102
2103         u8         phy_symbol_errors_low[0x20];
2104
2105         u8         phy_corrected_bits_high[0x20];
2106
2107         u8         phy_corrected_bits_low[0x20];
2108
2109         u8         phy_corrected_bits_lane0_high[0x20];
2110
2111         u8         phy_corrected_bits_lane0_low[0x20];
2112
2113         u8         phy_corrected_bits_lane1_high[0x20];
2114
2115         u8         phy_corrected_bits_lane1_low[0x20];
2116
2117         u8         phy_corrected_bits_lane2_high[0x20];
2118
2119         u8         phy_corrected_bits_lane2_low[0x20];
2120
2121         u8         phy_corrected_bits_lane3_high[0x20];
2122
2123         u8         phy_corrected_bits_lane3_low[0x20];
2124
2125         u8         reserved_at_200[0x5c0];
2126 };
2127
2128 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2129         u8         symbol_error_counter[0x10];
2130
2131         u8         link_error_recovery_counter[0x8];
2132
2133         u8         link_downed_counter[0x8];
2134
2135         u8         port_rcv_errors[0x10];
2136
2137         u8         port_rcv_remote_physical_errors[0x10];
2138
2139         u8         port_rcv_switch_relay_errors[0x10];
2140
2141         u8         port_xmit_discards[0x10];
2142
2143         u8         port_xmit_constraint_errors[0x8];
2144
2145         u8         port_rcv_constraint_errors[0x8];
2146
2147         u8         reserved_at_70[0x8];
2148
2149         u8         link_overrun_errors[0x8];
2150
2151         u8         reserved_at_80[0x10];
2152
2153         u8         vl_15_dropped[0x10];
2154
2155         u8         reserved_at_a0[0x80];
2156
2157         u8         port_xmit_wait[0x20];
2158 };
2159
2160 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2161         u8         transmit_queue_high[0x20];
2162
2163         u8         transmit_queue_low[0x20];
2164
2165         u8         no_buffer_discard_uc_high[0x20];
2166
2167         u8         no_buffer_discard_uc_low[0x20];
2168
2169         u8         reserved_at_80[0x740];
2170 };
2171
2172 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2173         u8         wred_discard_high[0x20];
2174
2175         u8         wred_discard_low[0x20];
2176
2177         u8         ecn_marked_tc_high[0x20];
2178
2179         u8         ecn_marked_tc_low[0x20];
2180
2181         u8         reserved_at_80[0x740];
2182 };
2183
2184 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2185         u8         rx_octets_high[0x20];
2186
2187         u8         rx_octets_low[0x20];
2188
2189         u8         reserved_at_40[0xc0];
2190
2191         u8         rx_frames_high[0x20];
2192
2193         u8         rx_frames_low[0x20];
2194
2195         u8         tx_octets_high[0x20];
2196
2197         u8         tx_octets_low[0x20];
2198
2199         u8         reserved_at_180[0xc0];
2200
2201         u8         tx_frames_high[0x20];
2202
2203         u8         tx_frames_low[0x20];
2204
2205         u8         rx_pause_high[0x20];
2206
2207         u8         rx_pause_low[0x20];
2208
2209         u8         rx_pause_duration_high[0x20];
2210
2211         u8         rx_pause_duration_low[0x20];
2212
2213         u8         tx_pause_high[0x20];
2214
2215         u8         tx_pause_low[0x20];
2216
2217         u8         tx_pause_duration_high[0x20];
2218
2219         u8         tx_pause_duration_low[0x20];
2220
2221         u8         rx_pause_transition_high[0x20];
2222
2223         u8         rx_pause_transition_low[0x20];
2224
2225         u8         rx_discards_high[0x20];
2226
2227         u8         rx_discards_low[0x20];
2228
2229         u8         device_stall_minor_watermark_cnt_high[0x20];
2230
2231         u8         device_stall_minor_watermark_cnt_low[0x20];
2232
2233         u8         device_stall_critical_watermark_cnt_high[0x20];
2234
2235         u8         device_stall_critical_watermark_cnt_low[0x20];
2236
2237         u8         reserved_at_480[0x340];
2238 };
2239
2240 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2241         u8         port_transmit_wait_high[0x20];
2242
2243         u8         port_transmit_wait_low[0x20];
2244
2245         u8         reserved_at_40[0x100];
2246
2247         u8         rx_buffer_almost_full_high[0x20];
2248
2249         u8         rx_buffer_almost_full_low[0x20];
2250
2251         u8         rx_buffer_full_high[0x20];
2252
2253         u8         rx_buffer_full_low[0x20];
2254
2255         u8         rx_icrc_encapsulated_high[0x20];
2256
2257         u8         rx_icrc_encapsulated_low[0x20];
2258
2259         u8         reserved_at_200[0x5c0];
2260 };
2261
2262 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2263         u8         dot3stats_alignment_errors_high[0x20];
2264
2265         u8         dot3stats_alignment_errors_low[0x20];
2266
2267         u8         dot3stats_fcs_errors_high[0x20];
2268
2269         u8         dot3stats_fcs_errors_low[0x20];
2270
2271         u8         dot3stats_single_collision_frames_high[0x20];
2272
2273         u8         dot3stats_single_collision_frames_low[0x20];
2274
2275         u8         dot3stats_multiple_collision_frames_high[0x20];
2276
2277         u8         dot3stats_multiple_collision_frames_low[0x20];
2278
2279         u8         dot3stats_sqe_test_errors_high[0x20];
2280
2281         u8         dot3stats_sqe_test_errors_low[0x20];
2282
2283         u8         dot3stats_deferred_transmissions_high[0x20];
2284
2285         u8         dot3stats_deferred_transmissions_low[0x20];
2286
2287         u8         dot3stats_late_collisions_high[0x20];
2288
2289         u8         dot3stats_late_collisions_low[0x20];
2290
2291         u8         dot3stats_excessive_collisions_high[0x20];
2292
2293         u8         dot3stats_excessive_collisions_low[0x20];
2294
2295         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2296
2297         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2298
2299         u8         dot3stats_carrier_sense_errors_high[0x20];
2300
2301         u8         dot3stats_carrier_sense_errors_low[0x20];
2302
2303         u8         dot3stats_frame_too_longs_high[0x20];
2304
2305         u8         dot3stats_frame_too_longs_low[0x20];
2306
2307         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2308
2309         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2310
2311         u8         dot3stats_symbol_errors_high[0x20];
2312
2313         u8         dot3stats_symbol_errors_low[0x20];
2314
2315         u8         dot3control_in_unknown_opcodes_high[0x20];
2316
2317         u8         dot3control_in_unknown_opcodes_low[0x20];
2318
2319         u8         dot3in_pause_frames_high[0x20];
2320
2321         u8         dot3in_pause_frames_low[0x20];
2322
2323         u8         dot3out_pause_frames_high[0x20];
2324
2325         u8         dot3out_pause_frames_low[0x20];
2326
2327         u8         reserved_at_400[0x3c0];
2328 };
2329
2330 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2331         u8         ether_stats_drop_events_high[0x20];
2332
2333         u8         ether_stats_drop_events_low[0x20];
2334
2335         u8         ether_stats_octets_high[0x20];
2336
2337         u8         ether_stats_octets_low[0x20];
2338
2339         u8         ether_stats_pkts_high[0x20];
2340
2341         u8         ether_stats_pkts_low[0x20];
2342
2343         u8         ether_stats_broadcast_pkts_high[0x20];
2344
2345         u8         ether_stats_broadcast_pkts_low[0x20];
2346
2347         u8         ether_stats_multicast_pkts_high[0x20];
2348
2349         u8         ether_stats_multicast_pkts_low[0x20];
2350
2351         u8         ether_stats_crc_align_errors_high[0x20];
2352
2353         u8         ether_stats_crc_align_errors_low[0x20];
2354
2355         u8         ether_stats_undersize_pkts_high[0x20];
2356
2357         u8         ether_stats_undersize_pkts_low[0x20];
2358
2359         u8         ether_stats_oversize_pkts_high[0x20];
2360
2361         u8         ether_stats_oversize_pkts_low[0x20];
2362
2363         u8         ether_stats_fragments_high[0x20];
2364
2365         u8         ether_stats_fragments_low[0x20];
2366
2367         u8         ether_stats_jabbers_high[0x20];
2368
2369         u8         ether_stats_jabbers_low[0x20];
2370
2371         u8         ether_stats_collisions_high[0x20];
2372
2373         u8         ether_stats_collisions_low[0x20];
2374
2375         u8         ether_stats_pkts64octets_high[0x20];
2376
2377         u8         ether_stats_pkts64octets_low[0x20];
2378
2379         u8         ether_stats_pkts65to127octets_high[0x20];
2380
2381         u8         ether_stats_pkts65to127octets_low[0x20];
2382
2383         u8         ether_stats_pkts128to255octets_high[0x20];
2384
2385         u8         ether_stats_pkts128to255octets_low[0x20];
2386
2387         u8         ether_stats_pkts256to511octets_high[0x20];
2388
2389         u8         ether_stats_pkts256to511octets_low[0x20];
2390
2391         u8         ether_stats_pkts512to1023octets_high[0x20];
2392
2393         u8         ether_stats_pkts512to1023octets_low[0x20];
2394
2395         u8         ether_stats_pkts1024to1518octets_high[0x20];
2396
2397         u8         ether_stats_pkts1024to1518octets_low[0x20];
2398
2399         u8         ether_stats_pkts1519to2047octets_high[0x20];
2400
2401         u8         ether_stats_pkts1519to2047octets_low[0x20];
2402
2403         u8         ether_stats_pkts2048to4095octets_high[0x20];
2404
2405         u8         ether_stats_pkts2048to4095octets_low[0x20];
2406
2407         u8         ether_stats_pkts4096to8191octets_high[0x20];
2408
2409         u8         ether_stats_pkts4096to8191octets_low[0x20];
2410
2411         u8         ether_stats_pkts8192to10239octets_high[0x20];
2412
2413         u8         ether_stats_pkts8192to10239octets_low[0x20];
2414
2415         u8         reserved_at_540[0x280];
2416 };
2417
2418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2419         u8         if_in_octets_high[0x20];
2420
2421         u8         if_in_octets_low[0x20];
2422
2423         u8         if_in_ucast_pkts_high[0x20];
2424
2425         u8         if_in_ucast_pkts_low[0x20];
2426
2427         u8         if_in_discards_high[0x20];
2428
2429         u8         if_in_discards_low[0x20];
2430
2431         u8         if_in_errors_high[0x20];
2432
2433         u8         if_in_errors_low[0x20];
2434
2435         u8         if_in_unknown_protos_high[0x20];
2436
2437         u8         if_in_unknown_protos_low[0x20];
2438
2439         u8         if_out_octets_high[0x20];
2440
2441         u8         if_out_octets_low[0x20];
2442
2443         u8         if_out_ucast_pkts_high[0x20];
2444
2445         u8         if_out_ucast_pkts_low[0x20];
2446
2447         u8         if_out_discards_high[0x20];
2448
2449         u8         if_out_discards_low[0x20];
2450
2451         u8         if_out_errors_high[0x20];
2452
2453         u8         if_out_errors_low[0x20];
2454
2455         u8         if_in_multicast_pkts_high[0x20];
2456
2457         u8         if_in_multicast_pkts_low[0x20];
2458
2459         u8         if_in_broadcast_pkts_high[0x20];
2460
2461         u8         if_in_broadcast_pkts_low[0x20];
2462
2463         u8         if_out_multicast_pkts_high[0x20];
2464
2465         u8         if_out_multicast_pkts_low[0x20];
2466
2467         u8         if_out_broadcast_pkts_high[0x20];
2468
2469         u8         if_out_broadcast_pkts_low[0x20];
2470
2471         u8         reserved_at_340[0x480];
2472 };
2473
2474 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2475         u8         a_frames_transmitted_ok_high[0x20];
2476
2477         u8         a_frames_transmitted_ok_low[0x20];
2478
2479         u8         a_frames_received_ok_high[0x20];
2480
2481         u8         a_frames_received_ok_low[0x20];
2482
2483         u8         a_frame_check_sequence_errors_high[0x20];
2484
2485         u8         a_frame_check_sequence_errors_low[0x20];
2486
2487         u8         a_alignment_errors_high[0x20];
2488
2489         u8         a_alignment_errors_low[0x20];
2490
2491         u8         a_octets_transmitted_ok_high[0x20];
2492
2493         u8         a_octets_transmitted_ok_low[0x20];
2494
2495         u8         a_octets_received_ok_high[0x20];
2496
2497         u8         a_octets_received_ok_low[0x20];
2498
2499         u8         a_multicast_frames_xmitted_ok_high[0x20];
2500
2501         u8         a_multicast_frames_xmitted_ok_low[0x20];
2502
2503         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2504
2505         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2506
2507         u8         a_multicast_frames_received_ok_high[0x20];
2508
2509         u8         a_multicast_frames_received_ok_low[0x20];
2510
2511         u8         a_broadcast_frames_received_ok_high[0x20];
2512
2513         u8         a_broadcast_frames_received_ok_low[0x20];
2514
2515         u8         a_in_range_length_errors_high[0x20];
2516
2517         u8         a_in_range_length_errors_low[0x20];
2518
2519         u8         a_out_of_range_length_field_high[0x20];
2520
2521         u8         a_out_of_range_length_field_low[0x20];
2522
2523         u8         a_frame_too_long_errors_high[0x20];
2524
2525         u8         a_frame_too_long_errors_low[0x20];
2526
2527         u8         a_symbol_error_during_carrier_high[0x20];
2528
2529         u8         a_symbol_error_during_carrier_low[0x20];
2530
2531         u8         a_mac_control_frames_transmitted_high[0x20];
2532
2533         u8         a_mac_control_frames_transmitted_low[0x20];
2534
2535         u8         a_mac_control_frames_received_high[0x20];
2536
2537         u8         a_mac_control_frames_received_low[0x20];
2538
2539         u8         a_unsupported_opcodes_received_high[0x20];
2540
2541         u8         a_unsupported_opcodes_received_low[0x20];
2542
2543         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2544
2545         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2546
2547         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2548
2549         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2550
2551         u8         reserved_at_4c0[0x300];
2552 };
2553
2554 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2555         u8         life_time_counter_high[0x20];
2556
2557         u8         life_time_counter_low[0x20];
2558
2559         u8         rx_errors[0x20];
2560
2561         u8         tx_errors[0x20];
2562
2563         u8         l0_to_recovery_eieos[0x20];
2564
2565         u8         l0_to_recovery_ts[0x20];
2566
2567         u8         l0_to_recovery_framing[0x20];
2568
2569         u8         l0_to_recovery_retrain[0x20];
2570
2571         u8         crc_error_dllp[0x20];
2572
2573         u8         crc_error_tlp[0x20];
2574
2575         u8         tx_overflow_buffer_pkt_high[0x20];
2576
2577         u8         tx_overflow_buffer_pkt_low[0x20];
2578
2579         u8         outbound_stalled_reads[0x20];
2580
2581         u8         outbound_stalled_writes[0x20];
2582
2583         u8         outbound_stalled_reads_events[0x20];
2584
2585         u8         outbound_stalled_writes_events[0x20];
2586
2587         u8         reserved_at_200[0x5c0];
2588 };
2589
2590 struct mlx5_ifc_cmd_inter_comp_event_bits {
2591         u8         command_completion_vector[0x20];
2592
2593         u8         reserved_at_20[0xc0];
2594 };
2595
2596 struct mlx5_ifc_stall_vl_event_bits {
2597         u8         reserved_at_0[0x18];
2598         u8         port_num[0x1];
2599         u8         reserved_at_19[0x3];
2600         u8         vl[0x4];
2601
2602         u8         reserved_at_20[0xa0];
2603 };
2604
2605 struct mlx5_ifc_db_bf_congestion_event_bits {
2606         u8         event_subtype[0x8];
2607         u8         reserved_at_8[0x8];
2608         u8         congestion_level[0x8];
2609         u8         reserved_at_18[0x8];
2610
2611         u8         reserved_at_20[0xa0];
2612 };
2613
2614 struct mlx5_ifc_gpio_event_bits {
2615         u8         reserved_at_0[0x60];
2616
2617         u8         gpio_event_hi[0x20];
2618
2619         u8         gpio_event_lo[0x20];
2620
2621         u8         reserved_at_a0[0x40];
2622 };
2623
2624 struct mlx5_ifc_port_state_change_event_bits {
2625         u8         reserved_at_0[0x40];
2626
2627         u8         port_num[0x4];
2628         u8         reserved_at_44[0x1c];
2629
2630         u8         reserved_at_60[0x80];
2631 };
2632
2633 struct mlx5_ifc_dropped_packet_logged_bits {
2634         u8         reserved_at_0[0xe0];
2635 };
2636
2637 enum {
2638         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2639         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2640 };
2641
2642 struct mlx5_ifc_cq_error_bits {
2643         u8         reserved_at_0[0x8];
2644         u8         cqn[0x18];
2645
2646         u8         reserved_at_20[0x20];
2647
2648         u8         reserved_at_40[0x18];
2649         u8         syndrome[0x8];
2650
2651         u8         reserved_at_60[0x80];
2652 };
2653
2654 struct mlx5_ifc_rdma_page_fault_event_bits {
2655         u8         bytes_committed[0x20];
2656
2657         u8         r_key[0x20];
2658
2659         u8         reserved_at_40[0x10];
2660         u8         packet_len[0x10];
2661
2662         u8         rdma_op_len[0x20];
2663
2664         u8         rdma_va[0x40];
2665
2666         u8         reserved_at_c0[0x5];
2667         u8         rdma[0x1];
2668         u8         write[0x1];
2669         u8         requestor[0x1];
2670         u8         qp_number[0x18];
2671 };
2672
2673 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2674         u8         bytes_committed[0x20];
2675
2676         u8         reserved_at_20[0x10];
2677         u8         wqe_index[0x10];
2678
2679         u8         reserved_at_40[0x10];
2680         u8         len[0x10];
2681
2682         u8         reserved_at_60[0x60];
2683
2684         u8         reserved_at_c0[0x5];
2685         u8         rdma[0x1];
2686         u8         write_read[0x1];
2687         u8         requestor[0x1];
2688         u8         qpn[0x18];
2689 };
2690
2691 struct mlx5_ifc_qp_events_bits {
2692         u8         reserved_at_0[0xa0];
2693
2694         u8         type[0x8];
2695         u8         reserved_at_a8[0x18];
2696
2697         u8         reserved_at_c0[0x8];
2698         u8         qpn_rqn_sqn[0x18];
2699 };
2700
2701 struct mlx5_ifc_dct_events_bits {
2702         u8         reserved_at_0[0xc0];
2703
2704         u8         reserved_at_c0[0x8];
2705         u8         dct_number[0x18];
2706 };
2707
2708 struct mlx5_ifc_comp_event_bits {
2709         u8         reserved_at_0[0xc0];
2710
2711         u8         reserved_at_c0[0x8];
2712         u8         cq_number[0x18];
2713 };
2714
2715 enum {
2716         MLX5_QPC_STATE_RST        = 0x0,
2717         MLX5_QPC_STATE_INIT       = 0x1,
2718         MLX5_QPC_STATE_RTR        = 0x2,
2719         MLX5_QPC_STATE_RTS        = 0x3,
2720         MLX5_QPC_STATE_SQER       = 0x4,
2721         MLX5_QPC_STATE_ERR        = 0x6,
2722         MLX5_QPC_STATE_SQD        = 0x7,
2723         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2724 };
2725
2726 enum {
2727         MLX5_QPC_ST_RC            = 0x0,
2728         MLX5_QPC_ST_UC            = 0x1,
2729         MLX5_QPC_ST_UD            = 0x2,
2730         MLX5_QPC_ST_XRC           = 0x3,
2731         MLX5_QPC_ST_DCI           = 0x5,
2732         MLX5_QPC_ST_QP0           = 0x7,
2733         MLX5_QPC_ST_QP1           = 0x8,
2734         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2735         MLX5_QPC_ST_REG_UMR       = 0xc,
2736 };
2737
2738 enum {
2739         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2740         MLX5_QPC_PM_STATE_REARM     = 0x1,
2741         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2742         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2743 };
2744
2745 enum {
2746         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2747 };
2748
2749 enum {
2750         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2751         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2752 };
2753
2754 enum {
2755         MLX5_QPC_MTU_256_BYTES        = 0x1,
2756         MLX5_QPC_MTU_512_BYTES        = 0x2,
2757         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2758         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2759         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2760         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2761 };
2762
2763 enum {
2764         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2765         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2766         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2767         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2768         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2769         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2770         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2771         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2772 };
2773
2774 enum {
2775         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2776         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2777         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2778 };
2779
2780 enum {
2781         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2782         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2783         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2784 };
2785
2786 struct mlx5_ifc_qpc_bits {
2787         u8         state[0x4];
2788         u8         lag_tx_port_affinity[0x4];
2789         u8         st[0x8];
2790         u8         reserved_at_10[0x3];
2791         u8         pm_state[0x2];
2792         u8         reserved_at_15[0x1];
2793         u8         req_e2e_credit_mode[0x2];
2794         u8         offload_type[0x4];
2795         u8         end_padding_mode[0x2];
2796         u8         reserved_at_1e[0x2];
2797
2798         u8         wq_signature[0x1];
2799         u8         block_lb_mc[0x1];
2800         u8         atomic_like_write_en[0x1];
2801         u8         latency_sensitive[0x1];
2802         u8         reserved_at_24[0x1];
2803         u8         drain_sigerr[0x1];
2804         u8         reserved_at_26[0x2];
2805         u8         pd[0x18];
2806
2807         u8         mtu[0x3];
2808         u8         log_msg_max[0x5];
2809         u8         reserved_at_48[0x1];
2810         u8         log_rq_size[0x4];
2811         u8         log_rq_stride[0x3];
2812         u8         no_sq[0x1];
2813         u8         log_sq_size[0x4];
2814         u8         reserved_at_55[0x6];
2815         u8         rlky[0x1];
2816         u8         ulp_stateless_offload_mode[0x4];
2817
2818         u8         counter_set_id[0x8];
2819         u8         uar_page[0x18];
2820
2821         u8         reserved_at_80[0x8];
2822         u8         user_index[0x18];
2823
2824         u8         reserved_at_a0[0x3];
2825         u8         log_page_size[0x5];
2826         u8         remote_qpn[0x18];
2827
2828         struct mlx5_ifc_ads_bits primary_address_path;
2829
2830         struct mlx5_ifc_ads_bits secondary_address_path;
2831
2832         u8         log_ack_req_freq[0x4];
2833         u8         reserved_at_384[0x4];
2834         u8         log_sra_max[0x3];
2835         u8         reserved_at_38b[0x2];
2836         u8         retry_count[0x3];
2837         u8         rnr_retry[0x3];
2838         u8         reserved_at_393[0x1];
2839         u8         fre[0x1];
2840         u8         cur_rnr_retry[0x3];
2841         u8         cur_retry_count[0x3];
2842         u8         reserved_at_39b[0x5];
2843
2844         u8         reserved_at_3a0[0x20];
2845
2846         u8         reserved_at_3c0[0x8];
2847         u8         next_send_psn[0x18];
2848
2849         u8         reserved_at_3e0[0x8];
2850         u8         cqn_snd[0x18];
2851
2852         u8         reserved_at_400[0x8];
2853         u8         deth_sqpn[0x18];
2854
2855         u8         reserved_at_420[0x20];
2856
2857         u8         reserved_at_440[0x8];
2858         u8         last_acked_psn[0x18];
2859
2860         u8         reserved_at_460[0x8];
2861         u8         ssn[0x18];
2862
2863         u8         reserved_at_480[0x8];
2864         u8         log_rra_max[0x3];
2865         u8         reserved_at_48b[0x1];
2866         u8         atomic_mode[0x4];
2867         u8         rre[0x1];
2868         u8         rwe[0x1];
2869         u8         rae[0x1];
2870         u8         reserved_at_493[0x1];
2871         u8         page_offset[0x6];
2872         u8         reserved_at_49a[0x3];
2873         u8         cd_slave_receive[0x1];
2874         u8         cd_slave_send[0x1];
2875         u8         cd_master[0x1];
2876
2877         u8         reserved_at_4a0[0x3];
2878         u8         min_rnr_nak[0x5];
2879         u8         next_rcv_psn[0x18];
2880
2881         u8         reserved_at_4c0[0x8];
2882         u8         xrcd[0x18];
2883
2884         u8         reserved_at_4e0[0x8];
2885         u8         cqn_rcv[0x18];
2886
2887         u8         dbr_addr[0x40];
2888
2889         u8         q_key[0x20];
2890
2891         u8         reserved_at_560[0x5];
2892         u8         rq_type[0x3];
2893         u8         srqn_rmpn_xrqn[0x18];
2894
2895         u8         reserved_at_580[0x8];
2896         u8         rmsn[0x18];
2897
2898         u8         hw_sq_wqebb_counter[0x10];
2899         u8         sw_sq_wqebb_counter[0x10];
2900
2901         u8         hw_rq_counter[0x20];
2902
2903         u8         sw_rq_counter[0x20];
2904
2905         u8         reserved_at_600[0x20];
2906
2907         u8         reserved_at_620[0xf];
2908         u8         cgs[0x1];
2909         u8         cs_req[0x8];
2910         u8         cs_res[0x8];
2911
2912         u8         dc_access_key[0x40];
2913
2914         u8         reserved_at_680[0x3];
2915         u8         dbr_umem_valid[0x1];
2916
2917         u8         reserved_at_684[0xbc];
2918 };
2919
2920 struct mlx5_ifc_roce_addr_layout_bits {
2921         u8         source_l3_address[16][0x8];
2922
2923         u8         reserved_at_80[0x3];
2924         u8         vlan_valid[0x1];
2925         u8         vlan_id[0xc];
2926         u8         source_mac_47_32[0x10];
2927
2928         u8         source_mac_31_0[0x20];
2929
2930         u8         reserved_at_c0[0x14];
2931         u8         roce_l3_type[0x4];
2932         u8         roce_version[0x8];
2933
2934         u8         reserved_at_e0[0x20];
2935 };
2936
2937 union mlx5_ifc_hca_cap_union_bits {
2938         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2939         struct mlx5_ifc_odp_cap_bits odp_cap;
2940         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2941         struct mlx5_ifc_roce_cap_bits roce_cap;
2942         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2943         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2944         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2945         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2946         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2947         struct mlx5_ifc_qos_cap_bits qos_cap;
2948         struct mlx5_ifc_debug_cap_bits debug_cap;
2949         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2950         struct mlx5_ifc_tls_cap_bits tls_cap;
2951         struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2952         struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2953         u8         reserved_at_0[0x8000];
2954 };
2955
2956 enum {
2957         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2958         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2959         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2960         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2961         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2962         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2963         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2964         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2965         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2966         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2967         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2968 };
2969
2970 enum {
2971         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2972         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2973         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2974 };
2975
2976 struct mlx5_ifc_vlan_bits {
2977         u8         ethtype[0x10];
2978         u8         prio[0x3];
2979         u8         cfi[0x1];
2980         u8         vid[0xc];
2981 };
2982
2983 struct mlx5_ifc_flow_context_bits {
2984         struct mlx5_ifc_vlan_bits push_vlan;
2985
2986         u8         group_id[0x20];
2987
2988         u8         reserved_at_40[0x8];
2989         u8         flow_tag[0x18];
2990
2991         u8         reserved_at_60[0x10];
2992         u8         action[0x10];
2993
2994         u8         extended_destination[0x1];
2995         u8         reserved_at_81[0x1];
2996         u8         flow_source[0x2];
2997         u8         reserved_at_84[0x4];
2998         u8         destination_list_size[0x18];
2999
3000         u8         reserved_at_a0[0x8];
3001         u8         flow_counter_list_size[0x18];
3002
3003         u8         packet_reformat_id[0x20];
3004
3005         u8         modify_header_id[0x20];
3006
3007         struct mlx5_ifc_vlan_bits push_vlan_2;
3008
3009         u8         reserved_at_120[0xe0];
3010
3011         struct mlx5_ifc_fte_match_param_bits match_value;
3012
3013         u8         reserved_at_1200[0x600];
3014
3015         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3016 };
3017
3018 enum {
3019         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3020         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3021 };
3022
3023 struct mlx5_ifc_xrc_srqc_bits {
3024         u8         state[0x4];
3025         u8         log_xrc_srq_size[0x4];
3026         u8         reserved_at_8[0x18];
3027
3028         u8         wq_signature[0x1];
3029         u8         cont_srq[0x1];
3030         u8         reserved_at_22[0x1];
3031         u8         rlky[0x1];
3032         u8         basic_cyclic_rcv_wqe[0x1];
3033         u8         log_rq_stride[0x3];
3034         u8         xrcd[0x18];
3035
3036         u8         page_offset[0x6];
3037         u8         reserved_at_46[0x1];
3038         u8         dbr_umem_valid[0x1];
3039         u8         cqn[0x18];
3040
3041         u8         reserved_at_60[0x20];
3042
3043         u8         user_index_equal_xrc_srqn[0x1];
3044         u8         reserved_at_81[0x1];
3045         u8         log_page_size[0x6];
3046         u8         user_index[0x18];
3047
3048         u8         reserved_at_a0[0x20];
3049
3050         u8         reserved_at_c0[0x8];
3051         u8         pd[0x18];
3052
3053         u8         lwm[0x10];
3054         u8         wqe_cnt[0x10];
3055
3056         u8         reserved_at_100[0x40];
3057
3058         u8         db_record_addr_h[0x20];
3059
3060         u8         db_record_addr_l[0x1e];
3061         u8         reserved_at_17e[0x2];
3062
3063         u8         reserved_at_180[0x80];
3064 };
3065
3066 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3067         u8         counter_error_queues[0x20];
3068
3069         u8         total_error_queues[0x20];
3070
3071         u8         send_queue_priority_update_flow[0x20];
3072
3073         u8         reserved_at_60[0x20];
3074
3075         u8         nic_receive_steering_discard[0x40];
3076
3077         u8         receive_discard_vport_down[0x40];
3078
3079         u8         transmit_discard_vport_down[0x40];
3080
3081         u8         reserved_at_140[0xa0];
3082
3083         u8         internal_rq_out_of_buffer[0x20];
3084
3085         u8         reserved_at_200[0xe00];
3086 };
3087
3088 struct mlx5_ifc_traffic_counter_bits {
3089         u8         packets[0x40];
3090
3091         u8         octets[0x40];
3092 };
3093
3094 struct mlx5_ifc_tisc_bits {
3095         u8         strict_lag_tx_port_affinity[0x1];
3096         u8         tls_en[0x1];
3097         u8         reserved_at_2[0x2];
3098         u8         lag_tx_port_affinity[0x04];
3099
3100         u8         reserved_at_8[0x4];
3101         u8         prio[0x4];
3102         u8         reserved_at_10[0x10];
3103
3104         u8         reserved_at_20[0x100];
3105
3106         u8         reserved_at_120[0x8];
3107         u8         transport_domain[0x18];
3108
3109         u8         reserved_at_140[0x8];
3110         u8         underlay_qpn[0x18];
3111
3112         u8         reserved_at_160[0x8];
3113         u8         pd[0x18];
3114
3115         u8         reserved_at_180[0x380];
3116 };
3117
3118 enum {
3119         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3120         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3121 };
3122
3123 enum {
3124         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
3125         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
3126 };
3127
3128 enum {
3129         MLX5_RX_HASH_FN_NONE           = 0x0,
3130         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3131         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3132 };
3133
3134 enum {
3135         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3136         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3137 };
3138
3139 struct mlx5_ifc_tirc_bits {
3140         u8         reserved_at_0[0x20];
3141
3142         u8         disp_type[0x4];
3143         u8         tls_en[0x1];
3144         u8         reserved_at_25[0x1b];
3145
3146         u8         reserved_at_40[0x40];
3147
3148         u8         reserved_at_80[0x4];
3149         u8         lro_timeout_period_usecs[0x10];
3150         u8         lro_enable_mask[0x4];
3151         u8         lro_max_ip_payload_size[0x8];
3152
3153         u8         reserved_at_a0[0x40];
3154
3155         u8         reserved_at_e0[0x8];
3156         u8         inline_rqn[0x18];
3157
3158         u8         rx_hash_symmetric[0x1];
3159         u8         reserved_at_101[0x1];
3160         u8         tunneled_offload_en[0x1];
3161         u8         reserved_at_103[0x5];
3162         u8         indirect_table[0x18];
3163
3164         u8         rx_hash_fn[0x4];
3165         u8         reserved_at_124[0x2];
3166         u8         self_lb_block[0x2];
3167         u8         transport_domain[0x18];
3168
3169         u8         rx_hash_toeplitz_key[10][0x20];
3170
3171         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3172
3173         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3174
3175         u8         reserved_at_2c0[0x4c0];
3176 };
3177
3178 enum {
3179         MLX5_SRQC_STATE_GOOD   = 0x0,
3180         MLX5_SRQC_STATE_ERROR  = 0x1,
3181 };
3182
3183 struct mlx5_ifc_srqc_bits {
3184         u8         state[0x4];
3185         u8         log_srq_size[0x4];
3186         u8         reserved_at_8[0x18];
3187
3188         u8         wq_signature[0x1];
3189         u8         cont_srq[0x1];
3190         u8         reserved_at_22[0x1];
3191         u8         rlky[0x1];
3192         u8         reserved_at_24[0x1];
3193         u8         log_rq_stride[0x3];
3194         u8         xrcd[0x18];
3195
3196         u8         page_offset[0x6];
3197         u8         reserved_at_46[0x2];
3198         u8         cqn[0x18];
3199
3200         u8         reserved_at_60[0x20];
3201
3202         u8         reserved_at_80[0x2];
3203         u8         log_page_size[0x6];
3204         u8         reserved_at_88[0x18];
3205
3206         u8         reserved_at_a0[0x20];
3207
3208         u8         reserved_at_c0[0x8];
3209         u8         pd[0x18];
3210
3211         u8         lwm[0x10];
3212         u8         wqe_cnt[0x10];
3213
3214         u8         reserved_at_100[0x40];
3215
3216         u8         dbr_addr[0x40];
3217
3218         u8         reserved_at_180[0x80];
3219 };
3220
3221 enum {
3222         MLX5_SQC_STATE_RST  = 0x0,
3223         MLX5_SQC_STATE_RDY  = 0x1,
3224         MLX5_SQC_STATE_ERR  = 0x3,
3225 };
3226
3227 struct mlx5_ifc_sqc_bits {
3228         u8         rlky[0x1];
3229         u8         cd_master[0x1];
3230         u8         fre[0x1];
3231         u8         flush_in_error_en[0x1];
3232         u8         allow_multi_pkt_send_wqe[0x1];
3233         u8         min_wqe_inline_mode[0x3];
3234         u8         state[0x4];
3235         u8         reg_umr[0x1];
3236         u8         allow_swp[0x1];
3237         u8         hairpin[0x1];
3238         u8         reserved_at_f[0x11];
3239
3240         u8         reserved_at_20[0x8];
3241         u8         user_index[0x18];
3242
3243         u8         reserved_at_40[0x8];
3244         u8         cqn[0x18];
3245
3246         u8         reserved_at_60[0x8];
3247         u8         hairpin_peer_rq[0x18];
3248
3249         u8         reserved_at_80[0x10];
3250         u8         hairpin_peer_vhca[0x10];
3251
3252         u8         reserved_at_a0[0x50];
3253
3254         u8         packet_pacing_rate_limit_index[0x10];
3255         u8         tis_lst_sz[0x10];
3256         u8         reserved_at_110[0x10];
3257
3258         u8         reserved_at_120[0x40];
3259
3260         u8         reserved_at_160[0x8];
3261         u8         tis_num_0[0x18];
3262
3263         struct mlx5_ifc_wq_bits wq;
3264 };
3265
3266 enum {
3267         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3268         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3269         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3270         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3271 };
3272
3273 enum {
3274         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
3275         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
3276         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
3277         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
3278 };
3279
3280 struct mlx5_ifc_scheduling_context_bits {
3281         u8         element_type[0x8];
3282         u8         reserved_at_8[0x18];
3283
3284         u8         element_attributes[0x20];
3285
3286         u8         parent_element_id[0x20];
3287
3288         u8         reserved_at_60[0x40];
3289
3290         u8         bw_share[0x20];
3291
3292         u8         max_average_bw[0x20];
3293
3294         u8         reserved_at_e0[0x120];
3295 };
3296
3297 struct mlx5_ifc_rqtc_bits {
3298         u8         reserved_at_0[0xa0];
3299
3300         u8         reserved_at_a0[0x10];
3301         u8         rqt_max_size[0x10];
3302
3303         u8         reserved_at_c0[0x10];
3304         u8         rqt_actual_size[0x10];
3305
3306         u8         reserved_at_e0[0x6a0];
3307
3308         struct mlx5_ifc_rq_num_bits rq_num[];
3309 };
3310
3311 enum {
3312         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3313         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3314 };
3315
3316 enum {
3317         MLX5_RQC_STATE_RST  = 0x0,
3318         MLX5_RQC_STATE_RDY  = 0x1,
3319         MLX5_RQC_STATE_ERR  = 0x3,
3320 };
3321
3322 struct mlx5_ifc_rqc_bits {
3323         u8         rlky[0x1];
3324         u8         delay_drop_en[0x1];
3325         u8         scatter_fcs[0x1];
3326         u8         vsd[0x1];
3327         u8         mem_rq_type[0x4];
3328         u8         state[0x4];
3329         u8         reserved_at_c[0x1];
3330         u8         flush_in_error_en[0x1];
3331         u8         hairpin[0x1];
3332         u8         reserved_at_f[0x11];
3333
3334         u8         reserved_at_20[0x8];
3335         u8         user_index[0x18];
3336
3337         u8         reserved_at_40[0x8];
3338         u8         cqn[0x18];
3339
3340         u8         counter_set_id[0x8];
3341         u8         reserved_at_68[0x18];
3342
3343         u8         reserved_at_80[0x8];
3344         u8         rmpn[0x18];
3345
3346         u8         reserved_at_a0[0x8];
3347         u8         hairpin_peer_sq[0x18];
3348
3349         u8         reserved_at_c0[0x10];
3350         u8         hairpin_peer_vhca[0x10];
3351
3352         u8         reserved_at_e0[0xa0];
3353
3354         struct mlx5_ifc_wq_bits wq;
3355 };
3356
3357 enum {
3358         MLX5_RMPC_STATE_RDY  = 0x1,
3359         MLX5_RMPC_STATE_ERR  = 0x3,
3360 };
3361
3362 struct mlx5_ifc_rmpc_bits {
3363         u8         reserved_at_0[0x8];
3364         u8         state[0x4];
3365         u8         reserved_at_c[0x14];
3366
3367         u8         basic_cyclic_rcv_wqe[0x1];
3368         u8         reserved_at_21[0x1f];
3369
3370         u8         reserved_at_40[0x140];
3371
3372         struct mlx5_ifc_wq_bits wq;
3373 };
3374
3375 struct mlx5_ifc_nic_vport_context_bits {
3376         u8         reserved_at_0[0x5];
3377         u8         min_wqe_inline_mode[0x3];
3378         u8         reserved_at_8[0x15];
3379         u8         disable_mc_local_lb[0x1];
3380         u8         disable_uc_local_lb[0x1];
3381         u8         roce_en[0x1];
3382
3383         u8         arm_change_event[0x1];
3384         u8         reserved_at_21[0x1a];
3385         u8         event_on_mtu[0x1];
3386         u8         event_on_promisc_change[0x1];
3387         u8         event_on_vlan_change[0x1];
3388         u8         event_on_mc_address_change[0x1];
3389         u8         event_on_uc_address_change[0x1];
3390
3391         u8         reserved_at_40[0xc];
3392
3393         u8         affiliation_criteria[0x4];
3394         u8         affiliated_vhca_id[0x10];
3395
3396         u8         reserved_at_60[0xd0];
3397
3398         u8         mtu[0x10];
3399
3400         u8         system_image_guid[0x40];
3401         u8         port_guid[0x40];
3402         u8         node_guid[0x40];
3403
3404         u8         reserved_at_200[0x140];
3405         u8         qkey_violation_counter[0x10];
3406         u8         reserved_at_350[0x430];
3407
3408         u8         promisc_uc[0x1];
3409         u8         promisc_mc[0x1];
3410         u8         promisc_all[0x1];
3411         u8         reserved_at_783[0x2];
3412         u8         allowed_list_type[0x3];
3413         u8         reserved_at_788[0xc];
3414         u8         allowed_list_size[0xc];
3415
3416         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3417
3418         u8         reserved_at_7e0[0x20];
3419
3420         u8         current_uc_mac_address[][0x40];
3421 };
3422
3423 enum {
3424         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3425         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3426         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3427         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3428         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3429         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3430 };
3431
3432 struct mlx5_ifc_mkc_bits {
3433         u8         reserved_at_0[0x1];
3434         u8         free[0x1];
3435         u8         reserved_at_2[0x1];
3436         u8         access_mode_4_2[0x3];
3437         u8         reserved_at_6[0x7];
3438         u8         relaxed_ordering_write[0x1];
3439         u8         reserved_at_e[0x1];
3440         u8         small_fence_on_rdma_read_response[0x1];
3441         u8         umr_en[0x1];
3442         u8         a[0x1];
3443         u8         rw[0x1];
3444         u8         rr[0x1];
3445         u8         lw[0x1];
3446         u8         lr[0x1];
3447         u8         access_mode_1_0[0x2];
3448         u8         reserved_at_18[0x8];
3449
3450         u8         qpn[0x18];
3451         u8         mkey_7_0[0x8];
3452
3453         u8         reserved_at_40[0x20];
3454
3455         u8         length64[0x1];
3456         u8         bsf_en[0x1];
3457         u8         sync_umr[0x1];
3458         u8         reserved_at_63[0x2];
3459         u8         expected_sigerr_count[0x1];
3460         u8         reserved_at_66[0x1];
3461         u8         en_rinval[0x1];
3462         u8         pd[0x18];
3463
3464         u8         start_addr[0x40];
3465
3466         u8         len[0x40];
3467
3468         u8         bsf_octword_size[0x20];
3469
3470         u8         reserved_at_120[0x80];
3471
3472         u8         translations_octword_size[0x20];
3473
3474         u8         reserved_at_1c0[0x19];
3475         u8         relaxed_ordering_read[0x1];
3476         u8         reserved_at_1d9[0x1];
3477         u8         log_page_size[0x5];
3478
3479         u8         reserved_at_1e0[0x20];
3480 };
3481
3482 struct mlx5_ifc_pkey_bits {
3483         u8         reserved_at_0[0x10];
3484         u8         pkey[0x10];
3485 };
3486
3487 struct mlx5_ifc_array128_auto_bits {
3488         u8         array128_auto[16][0x8];
3489 };
3490
3491 struct mlx5_ifc_hca_vport_context_bits {
3492         u8         field_select[0x20];
3493
3494         u8         reserved_at_20[0xe0];
3495
3496         u8         sm_virt_aware[0x1];
3497         u8         has_smi[0x1];
3498         u8         has_raw[0x1];
3499         u8         grh_required[0x1];
3500         u8         reserved_at_104[0xc];
3501         u8         port_physical_state[0x4];
3502         u8         vport_state_policy[0x4];
3503         u8         port_state[0x4];
3504         u8         vport_state[0x4];
3505
3506         u8         reserved_at_120[0x20];
3507
3508         u8         system_image_guid[0x40];
3509
3510         u8         port_guid[0x40];
3511
3512         u8         node_guid[0x40];
3513
3514         u8         cap_mask1[0x20];
3515
3516         u8         cap_mask1_field_select[0x20];
3517
3518         u8         cap_mask2[0x20];
3519
3520         u8         cap_mask2_field_select[0x20];
3521
3522         u8         reserved_at_280[0x80];
3523
3524         u8         lid[0x10];
3525         u8         reserved_at_310[0x4];
3526         u8         init_type_reply[0x4];
3527         u8         lmc[0x3];
3528         u8         subnet_timeout[0x5];
3529
3530         u8         sm_lid[0x10];
3531         u8         sm_sl[0x4];
3532         u8         reserved_at_334[0xc];
3533
3534         u8         qkey_violation_counter[0x10];
3535         u8         pkey_violation_counter[0x10];
3536
3537         u8         reserved_at_360[0xca0];
3538 };
3539
3540 struct mlx5_ifc_esw_vport_context_bits {
3541         u8         fdb_to_vport_reg_c[0x1];
3542         u8         reserved_at_1[0x2];
3543         u8         vport_svlan_strip[0x1];
3544         u8         vport_cvlan_strip[0x1];
3545         u8         vport_svlan_insert[0x1];
3546         u8         vport_cvlan_insert[0x2];
3547         u8         fdb_to_vport_reg_c_id[0x8];
3548         u8         reserved_at_10[0x10];
3549
3550         u8         reserved_at_20[0x20];
3551
3552         u8         svlan_cfi[0x1];
3553         u8         svlan_pcp[0x3];
3554         u8         svlan_id[0xc];
3555         u8         cvlan_cfi[0x1];
3556         u8         cvlan_pcp[0x3];
3557         u8         cvlan_id[0xc];
3558
3559         u8         reserved_at_60[0x720];
3560
3561         u8         sw_steering_vport_icm_address_rx[0x40];
3562
3563         u8         sw_steering_vport_icm_address_tx[0x40];
3564 };
3565
3566 enum {
3567         MLX5_EQC_STATUS_OK                = 0x0,
3568         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3569 };
3570
3571 enum {
3572         MLX5_EQC_ST_ARMED  = 0x9,
3573         MLX5_EQC_ST_FIRED  = 0xa,
3574 };
3575
3576 struct mlx5_ifc_eqc_bits {
3577         u8         status[0x4];
3578         u8         reserved_at_4[0x9];
3579         u8         ec[0x1];
3580         u8         oi[0x1];
3581         u8         reserved_at_f[0x5];
3582         u8         st[0x4];
3583         u8         reserved_at_18[0x8];
3584
3585         u8         reserved_at_20[0x20];
3586
3587         u8         reserved_at_40[0x14];
3588         u8         page_offset[0x6];
3589         u8         reserved_at_5a[0x6];
3590
3591         u8         reserved_at_60[0x3];
3592         u8         log_eq_size[0x5];
3593         u8         uar_page[0x18];
3594
3595         u8         reserved_at_80[0x20];
3596
3597         u8         reserved_at_a0[0x18];
3598         u8         intr[0x8];
3599
3600         u8         reserved_at_c0[0x3];
3601         u8         log_page_size[0x5];
3602         u8         reserved_at_c8[0x18];
3603
3604         u8         reserved_at_e0[0x60];
3605
3606         u8         reserved_at_140[0x8];
3607         u8         consumer_counter[0x18];
3608
3609         u8         reserved_at_160[0x8];
3610         u8         producer_counter[0x18];
3611
3612         u8         reserved_at_180[0x80];
3613 };
3614
3615 enum {
3616         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3617         MLX5_DCTC_STATE_DRAINING  = 0x1,
3618         MLX5_DCTC_STATE_DRAINED   = 0x2,
3619 };
3620
3621 enum {
3622         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3623         MLX5_DCTC_CS_RES_NA         = 0x1,
3624         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3625 };
3626
3627 enum {
3628         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3629         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3630         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3631         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3632         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3633 };
3634
3635 struct mlx5_ifc_dctc_bits {
3636         u8         reserved_at_0[0x4];
3637         u8         state[0x4];
3638         u8         reserved_at_8[0x18];
3639
3640         u8         reserved_at_20[0x8];
3641         u8         user_index[0x18];
3642
3643         u8         reserved_at_40[0x8];
3644         u8         cqn[0x18];
3645
3646         u8         counter_set_id[0x8];
3647         u8         atomic_mode[0x4];
3648         u8         rre[0x1];
3649         u8         rwe[0x1];
3650         u8         rae[0x1];
3651         u8         atomic_like_write_en[0x1];
3652         u8         latency_sensitive[0x1];
3653         u8         rlky[0x1];
3654         u8         free_ar[0x1];
3655         u8         reserved_at_73[0xd];
3656
3657         u8         reserved_at_80[0x8];
3658         u8         cs_res[0x8];
3659         u8         reserved_at_90[0x3];
3660         u8         min_rnr_nak[0x5];
3661         u8         reserved_at_98[0x8];
3662
3663         u8         reserved_at_a0[0x8];
3664         u8         srqn_xrqn[0x18];
3665
3666         u8         reserved_at_c0[0x8];
3667         u8         pd[0x18];
3668
3669         u8         tclass[0x8];
3670         u8         reserved_at_e8[0x4];
3671         u8         flow_label[0x14];
3672
3673         u8         dc_access_key[0x40];
3674
3675         u8         reserved_at_140[0x5];
3676         u8         mtu[0x3];
3677         u8         port[0x8];
3678         u8         pkey_index[0x10];
3679
3680         u8         reserved_at_160[0x8];
3681         u8         my_addr_index[0x8];
3682         u8         reserved_at_170[0x8];
3683         u8         hop_limit[0x8];
3684
3685         u8         dc_access_key_violation_count[0x20];
3686
3687         u8         reserved_at_1a0[0x14];
3688         u8         dei_cfi[0x1];
3689         u8         eth_prio[0x3];
3690         u8         ecn[0x2];
3691         u8         dscp[0x6];
3692
3693         u8         reserved_at_1c0[0x20];
3694         u8         ece[0x20];
3695 };
3696
3697 enum {
3698         MLX5_CQC_STATUS_OK             = 0x0,
3699         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3700         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3701 };
3702
3703 enum {
3704         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3705         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3706 };
3707
3708 enum {
3709         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3710         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3711         MLX5_CQC_ST_FIRED                                 = 0xa,
3712 };
3713
3714 enum {
3715         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3716         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3717         MLX5_CQ_PERIOD_NUM_MODES
3718 };
3719
3720 struct mlx5_ifc_cqc_bits {
3721         u8         status[0x4];
3722         u8         reserved_at_4[0x2];
3723         u8         dbr_umem_valid[0x1];
3724         u8         reserved_at_7[0x1];
3725         u8         cqe_sz[0x3];
3726         u8         cc[0x1];
3727         u8         reserved_at_c[0x1];
3728         u8         scqe_break_moderation_en[0x1];
3729         u8         oi[0x1];
3730         u8         cq_period_mode[0x2];
3731         u8         cqe_comp_en[0x1];
3732         u8         mini_cqe_res_format[0x2];
3733         u8         st[0x4];
3734         u8         reserved_at_18[0x8];
3735
3736         u8         reserved_at_20[0x20];
3737
3738         u8         reserved_at_40[0x14];
3739         u8         page_offset[0x6];
3740         u8         reserved_at_5a[0x6];
3741
3742         u8         reserved_at_60[0x3];
3743         u8         log_cq_size[0x5];
3744         u8         uar_page[0x18];
3745
3746         u8         reserved_at_80[0x4];
3747         u8         cq_period[0xc];
3748         u8         cq_max_count[0x10];
3749
3750         u8         reserved_at_a0[0x18];
3751         u8         c_eqn[0x8];
3752
3753         u8         reserved_at_c0[0x3];
3754         u8         log_page_size[0x5];
3755         u8         reserved_at_c8[0x18];
3756
3757         u8         reserved_at_e0[0x20];
3758
3759         u8         reserved_at_100[0x8];
3760         u8         last_notified_index[0x18];
3761
3762         u8         reserved_at_120[0x8];
3763         u8         last_solicit_index[0x18];
3764
3765         u8         reserved_at_140[0x8];
3766         u8         consumer_counter[0x18];
3767
3768         u8         reserved_at_160[0x8];
3769         u8         producer_counter[0x18];
3770
3771         u8         reserved_at_180[0x40];
3772
3773         u8         dbr_addr[0x40];
3774 };
3775
3776 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3777         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3778         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3779         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3780         u8         reserved_at_0[0x800];
3781 };
3782
3783 struct mlx5_ifc_query_adapter_param_block_bits {
3784         u8         reserved_at_0[0xc0];
3785
3786         u8         reserved_at_c0[0x8];
3787         u8         ieee_vendor_id[0x18];
3788
3789         u8         reserved_at_e0[0x10];
3790         u8         vsd_vendor_id[0x10];
3791
3792         u8         vsd[208][0x8];
3793
3794         u8         vsd_contd_psid[16][0x8];
3795 };
3796
3797 enum {
3798         MLX5_XRQC_STATE_GOOD   = 0x0,
3799         MLX5_XRQC_STATE_ERROR  = 0x1,
3800 };
3801
3802 enum {
3803         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3804         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3805 };
3806
3807 enum {
3808         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3809 };
3810
3811 struct mlx5_ifc_tag_matching_topology_context_bits {
3812         u8         log_matching_list_sz[0x4];
3813         u8         reserved_at_4[0xc];
3814         u8         append_next_index[0x10];
3815
3816         u8         sw_phase_cnt[0x10];
3817         u8         hw_phase_cnt[0x10];
3818
3819         u8         reserved_at_40[0x40];
3820 };
3821
3822 struct mlx5_ifc_xrqc_bits {
3823         u8         state[0x4];
3824         u8         rlkey[0x1];
3825         u8         reserved_at_5[0xf];
3826         u8         topology[0x4];
3827         u8         reserved_at_18[0x4];
3828         u8         offload[0x4];
3829
3830         u8         reserved_at_20[0x8];
3831         u8         user_index[0x18];
3832
3833         u8         reserved_at_40[0x8];
3834         u8         cqn[0x18];
3835
3836         u8         reserved_at_60[0xa0];
3837
3838         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3839
3840         u8         reserved_at_180[0x280];
3841
3842         struct mlx5_ifc_wq_bits wq;
3843 };
3844
3845 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3846         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3847         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3848         u8         reserved_at_0[0x20];
3849 };
3850
3851 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3852         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3853         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3854         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3855         u8         reserved_at_0[0x20];
3856 };
3857
3858 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3859         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3860         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3861         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3862         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3863         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3864         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3865         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3866         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3867         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3868         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3869         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3870         u8         reserved_at_0[0x7c0];
3871 };
3872
3873 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3874         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3875         u8         reserved_at_0[0x7c0];
3876 };
3877
3878 union mlx5_ifc_event_auto_bits {
3879         struct mlx5_ifc_comp_event_bits comp_event;
3880         struct mlx5_ifc_dct_events_bits dct_events;
3881         struct mlx5_ifc_qp_events_bits qp_events;
3882         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3883         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3884         struct mlx5_ifc_cq_error_bits cq_error;
3885         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3886         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3887         struct mlx5_ifc_gpio_event_bits gpio_event;
3888         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3889         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3890         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3891         u8         reserved_at_0[0xe0];
3892 };
3893
3894 struct mlx5_ifc_health_buffer_bits {
3895         u8         reserved_at_0[0x100];
3896
3897         u8         assert_existptr[0x20];
3898
3899         u8         assert_callra[0x20];
3900
3901         u8         reserved_at_140[0x40];
3902
3903         u8         fw_version[0x20];
3904
3905         u8         hw_id[0x20];
3906
3907         u8         reserved_at_1c0[0x20];
3908
3909         u8         irisc_index[0x8];
3910         u8         synd[0x8];
3911         u8         ext_synd[0x10];
3912 };
3913
3914 struct mlx5_ifc_register_loopback_control_bits {
3915         u8         no_lb[0x1];
3916         u8         reserved_at_1[0x7];
3917         u8         port[0x8];
3918         u8         reserved_at_10[0x10];
3919
3920         u8         reserved_at_20[0x60];
3921 };
3922
3923 struct mlx5_ifc_vport_tc_element_bits {
3924         u8         traffic_class[0x4];
3925         u8         reserved_at_4[0xc];
3926         u8         vport_number[0x10];
3927 };
3928
3929 struct mlx5_ifc_vport_element_bits {
3930         u8         reserved_at_0[0x10];
3931         u8         vport_number[0x10];
3932 };
3933
3934 enum {
3935         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3936         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3937         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3938 };
3939
3940 struct mlx5_ifc_tsar_element_bits {
3941         u8         reserved_at_0[0x8];
3942         u8         tsar_type[0x8];
3943         u8         reserved_at_10[0x10];
3944 };
3945
3946 enum {
3947         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3948         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3949 };
3950
3951 struct mlx5_ifc_teardown_hca_out_bits {
3952         u8         status[0x8];
3953         u8         reserved_at_8[0x18];
3954
3955         u8         syndrome[0x20];
3956
3957         u8         reserved_at_40[0x3f];
3958
3959         u8         state[0x1];
3960 };
3961
3962 enum {
3963         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3964         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3965         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3966 };
3967
3968 struct mlx5_ifc_teardown_hca_in_bits {
3969         u8         opcode[0x10];
3970         u8         reserved_at_10[0x10];
3971
3972         u8         reserved_at_20[0x10];
3973         u8         op_mod[0x10];
3974
3975         u8         reserved_at_40[0x10];
3976         u8         profile[0x10];
3977
3978         u8         reserved_at_60[0x20];
3979 };
3980
3981 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3982         u8         status[0x8];
3983         u8         reserved_at_8[0x18];
3984
3985         u8         syndrome[0x20];
3986
3987         u8         reserved_at_40[0x40];
3988 };
3989
3990 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3991         u8         opcode[0x10];
3992         u8         uid[0x10];
3993
3994         u8         reserved_at_20[0x10];
3995         u8         op_mod[0x10];
3996
3997         u8         reserved_at_40[0x8];
3998         u8         qpn[0x18];
3999
4000         u8         reserved_at_60[0x20];
4001
4002         u8         opt_param_mask[0x20];
4003
4004         u8         reserved_at_a0[0x20];
4005
4006         struct mlx5_ifc_qpc_bits qpc;
4007
4008         u8         reserved_at_800[0x80];
4009 };
4010
4011 struct mlx5_ifc_sqd2rts_qp_out_bits {
4012         u8         status[0x8];
4013         u8         reserved_at_8[0x18];
4014
4015         u8         syndrome[0x20];
4016
4017         u8         reserved_at_40[0x40];
4018 };
4019
4020 struct mlx5_ifc_sqd2rts_qp_in_bits {
4021         u8         opcode[0x10];
4022         u8         uid[0x10];
4023
4024         u8         reserved_at_20[0x10];
4025         u8         op_mod[0x10];
4026
4027         u8         reserved_at_40[0x8];
4028         u8         qpn[0x18];
4029
4030         u8         reserved_at_60[0x20];
4031
4032         u8         opt_param_mask[0x20];
4033
4034         u8         reserved_at_a0[0x20];
4035
4036         struct mlx5_ifc_qpc_bits qpc;
4037
4038         u8         reserved_at_800[0x80];
4039 };
4040
4041 struct mlx5_ifc_set_roce_address_out_bits {
4042         u8         status[0x8];
4043         u8         reserved_at_8[0x18];
4044
4045         u8         syndrome[0x20];
4046
4047         u8         reserved_at_40[0x40];
4048 };
4049
4050 struct mlx5_ifc_set_roce_address_in_bits {
4051         u8         opcode[0x10];
4052         u8         reserved_at_10[0x10];
4053
4054         u8         reserved_at_20[0x10];
4055         u8         op_mod[0x10];
4056
4057         u8         roce_address_index[0x10];
4058         u8         reserved_at_50[0xc];
4059         u8         vhca_port_num[0x4];
4060
4061         u8         reserved_at_60[0x20];
4062
4063         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4064 };
4065
4066 struct mlx5_ifc_set_mad_demux_out_bits {
4067         u8         status[0x8];
4068         u8         reserved_at_8[0x18];
4069
4070         u8         syndrome[0x20];
4071
4072         u8         reserved_at_40[0x40];
4073 };
4074
4075 enum {
4076         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4077         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4078 };
4079
4080 struct mlx5_ifc_set_mad_demux_in_bits {
4081         u8         opcode[0x10];
4082         u8         reserved_at_10[0x10];
4083
4084         u8         reserved_at_20[0x10];
4085         u8         op_mod[0x10];
4086
4087         u8         reserved_at_40[0x20];
4088
4089         u8         reserved_at_60[0x6];
4090         u8         demux_mode[0x2];
4091         u8         reserved_at_68[0x18];
4092 };
4093
4094 struct mlx5_ifc_set_l2_table_entry_out_bits {
4095         u8         status[0x8];
4096         u8         reserved_at_8[0x18];
4097
4098         u8         syndrome[0x20];
4099
4100         u8         reserved_at_40[0x40];
4101 };
4102
4103 struct mlx5_ifc_set_l2_table_entry_in_bits {
4104         u8         opcode[0x10];
4105         u8         reserved_at_10[0x10];
4106
4107         u8         reserved_at_20[0x10];
4108         u8         op_mod[0x10];
4109
4110         u8         reserved_at_40[0x60];
4111
4112         u8         reserved_at_a0[0x8];
4113         u8         table_index[0x18];
4114
4115         u8         reserved_at_c0[0x20];
4116
4117         u8         reserved_at_e0[0x13];
4118         u8         vlan_valid[0x1];
4119         u8         vlan[0xc];
4120
4121         struct mlx5_ifc_mac_address_layout_bits mac_address;
4122
4123         u8         reserved_at_140[0xc0];
4124 };
4125
4126 struct mlx5_ifc_set_issi_out_bits {
4127         u8         status[0x8];
4128         u8         reserved_at_8[0x18];
4129
4130         u8         syndrome[0x20];
4131
4132         u8         reserved_at_40[0x40];
4133 };
4134
4135 struct mlx5_ifc_set_issi_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_at_10[0x10];
4138
4139         u8         reserved_at_20[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_at_40[0x10];
4143         u8         current_issi[0x10];
4144
4145         u8         reserved_at_60[0x20];
4146 };
4147
4148 struct mlx5_ifc_set_hca_cap_out_bits {
4149         u8         status[0x8];
4150         u8         reserved_at_8[0x18];
4151
4152         u8         syndrome[0x20];
4153
4154         u8         reserved_at_40[0x40];
4155 };
4156
4157 struct mlx5_ifc_set_hca_cap_in_bits {
4158         u8         opcode[0x10];
4159         u8         reserved_at_10[0x10];
4160
4161         u8         reserved_at_20[0x10];
4162         u8         op_mod[0x10];
4163
4164         u8         reserved_at_40[0x40];
4165
4166         union mlx5_ifc_hca_cap_union_bits capability;
4167 };
4168
4169 enum {
4170         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4171         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4172         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4173         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4174         MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4175 };
4176
4177 struct mlx5_ifc_set_fte_out_bits {
4178         u8         status[0x8];
4179         u8         reserved_at_8[0x18];
4180
4181         u8         syndrome[0x20];
4182
4183         u8         reserved_at_40[0x40];
4184 };
4185
4186 struct mlx5_ifc_set_fte_in_bits {
4187         u8         opcode[0x10];
4188         u8         reserved_at_10[0x10];
4189
4190         u8         reserved_at_20[0x10];
4191         u8         op_mod[0x10];
4192
4193         u8         other_vport[0x1];
4194         u8         reserved_at_41[0xf];
4195         u8         vport_number[0x10];
4196
4197         u8         reserved_at_60[0x20];
4198
4199         u8         table_type[0x8];
4200         u8         reserved_at_88[0x18];
4201
4202         u8         reserved_at_a0[0x8];
4203         u8         table_id[0x18];
4204
4205         u8         ignore_flow_level[0x1];
4206         u8         reserved_at_c1[0x17];
4207         u8         modify_enable_mask[0x8];
4208
4209         u8         reserved_at_e0[0x20];
4210
4211         u8         flow_index[0x20];
4212
4213         u8         reserved_at_120[0xe0];
4214
4215         struct mlx5_ifc_flow_context_bits flow_context;
4216 };
4217
4218 struct mlx5_ifc_rts2rts_qp_out_bits {
4219         u8         status[0x8];
4220         u8         reserved_at_8[0x18];
4221
4222         u8         syndrome[0x20];
4223
4224         u8         reserved_at_40[0x20];
4225         u8         ece[0x20];
4226 };
4227
4228 struct mlx5_ifc_rts2rts_qp_in_bits {
4229         u8         opcode[0x10];
4230         u8         uid[0x10];
4231
4232         u8         reserved_at_20[0x10];
4233         u8         op_mod[0x10];
4234
4235         u8         reserved_at_40[0x8];
4236         u8         qpn[0x18];
4237
4238         u8         reserved_at_60[0x20];
4239
4240         u8         opt_param_mask[0x20];
4241
4242         u8         ece[0x20];
4243
4244         struct mlx5_ifc_qpc_bits qpc;
4245
4246         u8         reserved_at_800[0x80];
4247 };
4248
4249 struct mlx5_ifc_rtr2rts_qp_out_bits {
4250         u8         status[0x8];
4251         u8         reserved_at_8[0x18];
4252
4253         u8         syndrome[0x20];
4254
4255         u8         reserved_at_40[0x20];
4256         u8         ece[0x20];
4257 };
4258
4259 struct mlx5_ifc_rtr2rts_qp_in_bits {
4260         u8         opcode[0x10];
4261         u8         uid[0x10];
4262
4263         u8         reserved_at_20[0x10];
4264         u8         op_mod[0x10];
4265
4266         u8         reserved_at_40[0x8];
4267         u8         qpn[0x18];
4268
4269         u8         reserved_at_60[0x20];
4270
4271         u8         opt_param_mask[0x20];
4272
4273         u8         ece[0x20];
4274
4275         struct mlx5_ifc_qpc_bits qpc;
4276
4277         u8         reserved_at_800[0x80];
4278 };
4279
4280 struct mlx5_ifc_rst2init_qp_out_bits {
4281         u8         status[0x8];
4282         u8         reserved_at_8[0x18];
4283
4284         u8         syndrome[0x20];
4285
4286         u8         reserved_at_40[0x40];
4287 };
4288
4289 struct mlx5_ifc_rst2init_qp_in_bits {
4290         u8         opcode[0x10];
4291         u8         uid[0x10];
4292
4293         u8         reserved_at_20[0x10];
4294         u8         op_mod[0x10];
4295
4296         u8         reserved_at_40[0x8];
4297         u8         qpn[0x18];
4298
4299         u8         reserved_at_60[0x20];
4300
4301         u8         opt_param_mask[0x20];
4302
4303         u8         reserved_at_a0[0x20];
4304
4305         struct mlx5_ifc_qpc_bits qpc;
4306
4307         u8         reserved_at_800[0x80];
4308 };
4309
4310 struct mlx5_ifc_query_xrq_out_bits {
4311         u8         status[0x8];
4312         u8         reserved_at_8[0x18];
4313
4314         u8         syndrome[0x20];
4315
4316         u8         reserved_at_40[0x40];
4317
4318         struct mlx5_ifc_xrqc_bits xrq_context;
4319 };
4320
4321 struct mlx5_ifc_query_xrq_in_bits {
4322         u8         opcode[0x10];
4323         u8         reserved_at_10[0x10];
4324
4325         u8         reserved_at_20[0x10];
4326         u8         op_mod[0x10];
4327
4328         u8         reserved_at_40[0x8];
4329         u8         xrqn[0x18];
4330
4331         u8         reserved_at_60[0x20];
4332 };
4333
4334 struct mlx5_ifc_query_xrc_srq_out_bits {
4335         u8         status[0x8];
4336         u8         reserved_at_8[0x18];
4337
4338         u8         syndrome[0x20];
4339
4340         u8         reserved_at_40[0x40];
4341
4342         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4343
4344         u8         reserved_at_280[0x600];
4345
4346         u8         pas[][0x40];
4347 };
4348
4349 struct mlx5_ifc_query_xrc_srq_in_bits {
4350         u8         opcode[0x10];
4351         u8         reserved_at_10[0x10];
4352
4353         u8         reserved_at_20[0x10];
4354         u8         op_mod[0x10];
4355
4356         u8         reserved_at_40[0x8];
4357         u8         xrc_srqn[0x18];
4358
4359         u8         reserved_at_60[0x20];
4360 };
4361
4362 enum {
4363         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4364         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4365 };
4366
4367 struct mlx5_ifc_query_vport_state_out_bits {
4368         u8         status[0x8];
4369         u8         reserved_at_8[0x18];
4370
4371         u8         syndrome[0x20];
4372
4373         u8         reserved_at_40[0x20];
4374
4375         u8         reserved_at_60[0x18];
4376         u8         admin_state[0x4];
4377         u8         state[0x4];
4378 };
4379
4380 enum {
4381         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4382         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4383 };
4384
4385 struct mlx5_ifc_arm_monitor_counter_in_bits {
4386         u8         opcode[0x10];
4387         u8         uid[0x10];
4388
4389         u8         reserved_at_20[0x10];
4390         u8         op_mod[0x10];
4391
4392         u8         reserved_at_40[0x20];
4393
4394         u8         reserved_at_60[0x20];
4395 };
4396
4397 struct mlx5_ifc_arm_monitor_counter_out_bits {
4398         u8         status[0x8];
4399         u8         reserved_at_8[0x18];
4400
4401         u8         syndrome[0x20];
4402
4403         u8         reserved_at_40[0x40];
4404 };
4405
4406 enum {
4407         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4408         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4409 };
4410
4411 enum mlx5_monitor_counter_ppcnt {
4412         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4413         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4414         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4415         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4416         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4417         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4418 };
4419
4420 enum {
4421         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4422 };
4423
4424 struct mlx5_ifc_monitor_counter_output_bits {
4425         u8         reserved_at_0[0x4];
4426         u8         type[0x4];
4427         u8         reserved_at_8[0x8];
4428         u8         counter[0x10];
4429
4430         u8         counter_group_id[0x20];
4431 };
4432
4433 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4434 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4435 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4436                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4437
4438 struct mlx5_ifc_set_monitor_counter_in_bits {
4439         u8         opcode[0x10];
4440         u8         uid[0x10];
4441
4442         u8         reserved_at_20[0x10];
4443         u8         op_mod[0x10];
4444
4445         u8         reserved_at_40[0x10];
4446         u8         num_of_counters[0x10];
4447
4448         u8         reserved_at_60[0x20];
4449
4450         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4451 };
4452
4453 struct mlx5_ifc_set_monitor_counter_out_bits {
4454         u8         status[0x8];
4455         u8         reserved_at_8[0x18];
4456
4457         u8         syndrome[0x20];
4458
4459         u8         reserved_at_40[0x40];
4460 };
4461
4462 struct mlx5_ifc_query_vport_state_in_bits {
4463         u8         opcode[0x10];
4464         u8         reserved_at_10[0x10];
4465
4466         u8         reserved_at_20[0x10];
4467         u8         op_mod[0x10];
4468
4469         u8         other_vport[0x1];
4470         u8         reserved_at_41[0xf];
4471         u8         vport_number[0x10];
4472
4473         u8         reserved_at_60[0x20];
4474 };
4475
4476 struct mlx5_ifc_query_vnic_env_out_bits {
4477         u8         status[0x8];
4478         u8         reserved_at_8[0x18];
4479
4480         u8         syndrome[0x20];
4481
4482         u8         reserved_at_40[0x40];
4483
4484         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4485 };
4486
4487 enum {
4488         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4489 };
4490
4491 struct mlx5_ifc_query_vnic_env_in_bits {
4492         u8         opcode[0x10];
4493         u8         reserved_at_10[0x10];
4494
4495         u8         reserved_at_20[0x10];
4496         u8         op_mod[0x10];
4497
4498         u8         other_vport[0x1];
4499         u8         reserved_at_41[0xf];
4500         u8         vport_number[0x10];
4501
4502         u8         reserved_at_60[0x20];
4503 };
4504
4505 struct mlx5_ifc_query_vport_counter_out_bits {
4506         u8         status[0x8];
4507         u8         reserved_at_8[0x18];
4508
4509         u8         syndrome[0x20];
4510
4511         u8         reserved_at_40[0x40];
4512
4513         struct mlx5_ifc_traffic_counter_bits received_errors;
4514
4515         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4516
4517         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4518
4519         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4520
4521         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4522
4523         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4524
4525         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4526
4527         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4528
4529         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4530
4531         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4532
4533         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4534
4535         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4536
4537         u8         reserved_at_680[0xa00];
4538 };
4539
4540 enum {
4541         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4542 };
4543
4544 struct mlx5_ifc_query_vport_counter_in_bits {
4545         u8         opcode[0x10];
4546         u8         reserved_at_10[0x10];
4547
4548         u8         reserved_at_20[0x10];
4549         u8         op_mod[0x10];
4550
4551         u8         other_vport[0x1];
4552         u8         reserved_at_41[0xb];
4553         u8         port_num[0x4];
4554         u8         vport_number[0x10];
4555
4556         u8         reserved_at_60[0x60];
4557
4558         u8         clear[0x1];
4559         u8         reserved_at_c1[0x1f];
4560
4561         u8         reserved_at_e0[0x20];
4562 };
4563
4564 struct mlx5_ifc_query_tis_out_bits {
4565         u8         status[0x8];
4566         u8         reserved_at_8[0x18];
4567
4568         u8         syndrome[0x20];
4569
4570         u8         reserved_at_40[0x40];
4571
4572         struct mlx5_ifc_tisc_bits tis_context;
4573 };
4574
4575 struct mlx5_ifc_query_tis_in_bits {
4576         u8         opcode[0x10];
4577         u8         reserved_at_10[0x10];
4578
4579         u8         reserved_at_20[0x10];
4580         u8         op_mod[0x10];
4581
4582         u8         reserved_at_40[0x8];
4583         u8         tisn[0x18];
4584
4585         u8         reserved_at_60[0x20];
4586 };
4587
4588 struct mlx5_ifc_query_tir_out_bits {
4589         u8         status[0x8];
4590         u8         reserved_at_8[0x18];
4591
4592         u8         syndrome[0x20];
4593
4594         u8         reserved_at_40[0xc0];
4595
4596         struct mlx5_ifc_tirc_bits tir_context;
4597 };
4598
4599 struct mlx5_ifc_query_tir_in_bits {
4600         u8         opcode[0x10];
4601         u8         reserved_at_10[0x10];
4602
4603         u8         reserved_at_20[0x10];
4604         u8         op_mod[0x10];
4605
4606         u8         reserved_at_40[0x8];
4607         u8         tirn[0x18];
4608
4609         u8         reserved_at_60[0x20];
4610 };
4611
4612 struct mlx5_ifc_query_srq_out_bits {
4613         u8         status[0x8];
4614         u8         reserved_at_8[0x18];
4615
4616         u8         syndrome[0x20];
4617
4618         u8         reserved_at_40[0x40];
4619
4620         struct mlx5_ifc_srqc_bits srq_context_entry;
4621
4622         u8         reserved_at_280[0x600];
4623
4624         u8         pas[][0x40];
4625 };
4626
4627 struct mlx5_ifc_query_srq_in_bits {
4628         u8         opcode[0x10];
4629         u8         reserved_at_10[0x10];
4630
4631         u8         reserved_at_20[0x10];
4632         u8         op_mod[0x10];
4633
4634         u8         reserved_at_40[0x8];
4635         u8         srqn[0x18];
4636
4637         u8         reserved_at_60[0x20];
4638 };
4639
4640 struct mlx5_ifc_query_sq_out_bits {
4641         u8         status[0x8];
4642         u8         reserved_at_8[0x18];
4643
4644         u8         syndrome[0x20];
4645
4646         u8         reserved_at_40[0xc0];
4647
4648         struct mlx5_ifc_sqc_bits sq_context;
4649 };
4650
4651 struct mlx5_ifc_query_sq_in_bits {
4652         u8         opcode[0x10];
4653         u8         reserved_at_10[0x10];
4654
4655         u8         reserved_at_20[0x10];
4656         u8         op_mod[0x10];
4657
4658         u8         reserved_at_40[0x8];
4659         u8         sqn[0x18];
4660
4661         u8         reserved_at_60[0x20];
4662 };
4663
4664 struct mlx5_ifc_query_special_contexts_out_bits {
4665         u8         status[0x8];
4666         u8         reserved_at_8[0x18];
4667
4668         u8         syndrome[0x20];
4669
4670         u8         dump_fill_mkey[0x20];
4671
4672         u8         resd_lkey[0x20];
4673
4674         u8         null_mkey[0x20];
4675
4676         u8         reserved_at_a0[0x60];
4677 };
4678
4679 struct mlx5_ifc_query_special_contexts_in_bits {
4680         u8         opcode[0x10];
4681         u8         reserved_at_10[0x10];
4682
4683         u8         reserved_at_20[0x10];
4684         u8         op_mod[0x10];
4685
4686         u8         reserved_at_40[0x40];
4687 };
4688
4689 struct mlx5_ifc_query_scheduling_element_out_bits {
4690         u8         opcode[0x10];
4691         u8         reserved_at_10[0x10];
4692
4693         u8         reserved_at_20[0x10];
4694         u8         op_mod[0x10];
4695
4696         u8         reserved_at_40[0xc0];
4697
4698         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4699
4700         u8         reserved_at_300[0x100];
4701 };
4702
4703 enum {
4704         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4705 };
4706
4707 struct mlx5_ifc_query_scheduling_element_in_bits {
4708         u8         opcode[0x10];
4709         u8         reserved_at_10[0x10];
4710
4711         u8         reserved_at_20[0x10];
4712         u8         op_mod[0x10];
4713
4714         u8         scheduling_hierarchy[0x8];
4715         u8         reserved_at_48[0x18];
4716
4717         u8         scheduling_element_id[0x20];
4718
4719         u8         reserved_at_80[0x180];
4720 };
4721
4722 struct mlx5_ifc_query_rqt_out_bits {
4723         u8         status[0x8];
4724         u8         reserved_at_8[0x18];
4725
4726         u8         syndrome[0x20];
4727
4728         u8         reserved_at_40[0xc0];
4729
4730         struct mlx5_ifc_rqtc_bits rqt_context;
4731 };
4732
4733 struct mlx5_ifc_query_rqt_in_bits {
4734         u8         opcode[0x10];
4735         u8         reserved_at_10[0x10];
4736
4737         u8         reserved_at_20[0x10];
4738         u8         op_mod[0x10];
4739
4740         u8         reserved_at_40[0x8];
4741         u8         rqtn[0x18];
4742
4743         u8         reserved_at_60[0x20];
4744 };
4745
4746 struct mlx5_ifc_query_rq_out_bits {
4747         u8         status[0x8];
4748         u8         reserved_at_8[0x18];
4749
4750         u8         syndrome[0x20];
4751
4752         u8         reserved_at_40[0xc0];
4753
4754         struct mlx5_ifc_rqc_bits rq_context;
4755 };
4756
4757 struct mlx5_ifc_query_rq_in_bits {
4758         u8         opcode[0x10];
4759         u8         reserved_at_10[0x10];
4760
4761         u8         reserved_at_20[0x10];
4762         u8         op_mod[0x10];
4763
4764         u8         reserved_at_40[0x8];
4765         u8         rqn[0x18];
4766
4767         u8         reserved_at_60[0x20];
4768 };
4769
4770 struct mlx5_ifc_query_roce_address_out_bits {
4771         u8         status[0x8];
4772         u8         reserved_at_8[0x18];
4773
4774         u8         syndrome[0x20];
4775
4776         u8         reserved_at_40[0x40];
4777
4778         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4779 };
4780
4781 struct mlx5_ifc_query_roce_address_in_bits {
4782         u8         opcode[0x10];
4783         u8         reserved_at_10[0x10];
4784
4785         u8         reserved_at_20[0x10];
4786         u8         op_mod[0x10];
4787
4788         u8         roce_address_index[0x10];
4789         u8         reserved_at_50[0xc];
4790         u8         vhca_port_num[0x4];
4791
4792         u8         reserved_at_60[0x20];
4793 };
4794
4795 struct mlx5_ifc_query_rmp_out_bits {
4796         u8         status[0x8];
4797         u8         reserved_at_8[0x18];
4798
4799         u8         syndrome[0x20];
4800
4801         u8         reserved_at_40[0xc0];
4802
4803         struct mlx5_ifc_rmpc_bits rmp_context;
4804 };
4805
4806 struct mlx5_ifc_query_rmp_in_bits {
4807         u8         opcode[0x10];
4808         u8         reserved_at_10[0x10];
4809
4810         u8         reserved_at_20[0x10];
4811         u8         op_mod[0x10];
4812
4813         u8         reserved_at_40[0x8];
4814         u8         rmpn[0x18];
4815
4816         u8         reserved_at_60[0x20];
4817 };
4818
4819 struct mlx5_ifc_query_qp_out_bits {
4820         u8         status[0x8];
4821         u8         reserved_at_8[0x18];
4822
4823         u8         syndrome[0x20];
4824
4825         u8         reserved_at_40[0x20];
4826         u8         ece[0x20];
4827
4828         u8         opt_param_mask[0x20];
4829
4830         u8         reserved_at_a0[0x20];
4831
4832         struct mlx5_ifc_qpc_bits qpc;
4833
4834         u8         reserved_at_800[0x80];
4835
4836         u8         pas[][0x40];
4837 };
4838
4839 struct mlx5_ifc_query_qp_in_bits {
4840         u8         opcode[0x10];
4841         u8         reserved_at_10[0x10];
4842
4843         u8         reserved_at_20[0x10];
4844         u8         op_mod[0x10];
4845
4846         u8         reserved_at_40[0x8];
4847         u8         qpn[0x18];
4848
4849         u8         reserved_at_60[0x20];
4850 };
4851
4852 struct mlx5_ifc_query_q_counter_out_bits {
4853         u8         status[0x8];
4854         u8         reserved_at_8[0x18];
4855
4856         u8         syndrome[0x20];
4857
4858         u8         reserved_at_40[0x40];
4859
4860         u8         rx_write_requests[0x20];
4861
4862         u8         reserved_at_a0[0x20];
4863
4864         u8         rx_read_requests[0x20];
4865
4866         u8         reserved_at_e0[0x20];
4867
4868         u8         rx_atomic_requests[0x20];
4869
4870         u8         reserved_at_120[0x20];
4871
4872         u8         rx_dct_connect[0x20];
4873
4874         u8         reserved_at_160[0x20];
4875
4876         u8         out_of_buffer[0x20];
4877
4878         u8         reserved_at_1a0[0x20];
4879
4880         u8         out_of_sequence[0x20];
4881
4882         u8         reserved_at_1e0[0x20];
4883
4884         u8         duplicate_request[0x20];
4885
4886         u8         reserved_at_220[0x20];
4887
4888         u8         rnr_nak_retry_err[0x20];
4889
4890         u8         reserved_at_260[0x20];
4891
4892         u8         packet_seq_err[0x20];
4893
4894         u8         reserved_at_2a0[0x20];
4895
4896         u8         implied_nak_seq_err[0x20];
4897
4898         u8         reserved_at_2e0[0x20];
4899
4900         u8         local_ack_timeout_err[0x20];
4901
4902         u8         reserved_at_320[0xa0];
4903
4904         u8         resp_local_length_error[0x20];
4905
4906         u8         req_local_length_error[0x20];
4907
4908         u8         resp_local_qp_error[0x20];
4909
4910         u8         local_operation_error[0x20];
4911
4912         u8         resp_local_protection[0x20];
4913
4914         u8         req_local_protection[0x20];
4915
4916         u8         resp_cqe_error[0x20];
4917
4918         u8         req_cqe_error[0x20];
4919
4920         u8         req_mw_binding[0x20];
4921
4922         u8         req_bad_response[0x20];
4923
4924         u8         req_remote_invalid_request[0x20];
4925
4926         u8         resp_remote_invalid_request[0x20];
4927
4928         u8         req_remote_access_errors[0x20];
4929
4930         u8         resp_remote_access_errors[0x20];
4931
4932         u8         req_remote_operation_errors[0x20];
4933
4934         u8         req_transport_retries_exceeded[0x20];
4935
4936         u8         cq_overflow[0x20];
4937
4938         u8         resp_cqe_flush_error[0x20];
4939
4940         u8         req_cqe_flush_error[0x20];
4941
4942         u8         reserved_at_620[0x20];
4943
4944         u8         roce_adp_retrans[0x20];
4945
4946         u8         roce_adp_retrans_to[0x20];
4947
4948         u8         roce_slow_restart[0x20];
4949
4950         u8         roce_slow_restart_cnps[0x20];
4951
4952         u8         roce_slow_restart_trans[0x20];
4953
4954         u8         reserved_at_6e0[0x120];
4955 };
4956
4957 struct mlx5_ifc_query_q_counter_in_bits {
4958         u8         opcode[0x10];
4959         u8         reserved_at_10[0x10];
4960
4961         u8         reserved_at_20[0x10];
4962         u8         op_mod[0x10];
4963
4964         u8         reserved_at_40[0x80];
4965
4966         u8         clear[0x1];
4967         u8         reserved_at_c1[0x1f];
4968
4969         u8         reserved_at_e0[0x18];
4970         u8         counter_set_id[0x8];
4971 };
4972
4973 struct mlx5_ifc_query_pages_out_bits {
4974         u8         status[0x8];
4975         u8         reserved_at_8[0x18];
4976
4977         u8         syndrome[0x20];
4978
4979         u8         embedded_cpu_function[0x1];
4980         u8         reserved_at_41[0xf];
4981         u8         function_id[0x10];
4982
4983         u8         num_pages[0x20];
4984 };
4985
4986 enum {
4987         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4988         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4989         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4990 };
4991
4992 struct mlx5_ifc_query_pages_in_bits {
4993         u8         opcode[0x10];
4994         u8         reserved_at_10[0x10];
4995
4996         u8         reserved_at_20[0x10];
4997         u8         op_mod[0x10];
4998
4999         u8         embedded_cpu_function[0x1];
5000         u8         reserved_at_41[0xf];
5001         u8         function_id[0x10];
5002
5003         u8         reserved_at_60[0x20];
5004 };
5005
5006 struct mlx5_ifc_query_nic_vport_context_out_bits {
5007         u8         status[0x8];
5008         u8         reserved_at_8[0x18];
5009
5010         u8         syndrome[0x20];
5011
5012         u8         reserved_at_40[0x40];
5013
5014         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5015 };
5016
5017 struct mlx5_ifc_query_nic_vport_context_in_bits {
5018         u8         opcode[0x10];
5019         u8         reserved_at_10[0x10];
5020
5021         u8         reserved_at_20[0x10];
5022         u8         op_mod[0x10];
5023
5024         u8         other_vport[0x1];
5025         u8         reserved_at_41[0xf];
5026         u8         vport_number[0x10];
5027
5028         u8         reserved_at_60[0x5];
5029         u8         allowed_list_type[0x3];
5030         u8         reserved_at_68[0x18];
5031 };
5032
5033 struct mlx5_ifc_query_mkey_out_bits {
5034         u8         status[0x8];
5035         u8         reserved_at_8[0x18];
5036
5037         u8         syndrome[0x20];
5038
5039         u8         reserved_at_40[0x40];
5040
5041         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5042
5043         u8         reserved_at_280[0x600];
5044
5045         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5046
5047         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5048 };
5049
5050 struct mlx5_ifc_query_mkey_in_bits {
5051         u8         opcode[0x10];
5052         u8         reserved_at_10[0x10];
5053
5054         u8         reserved_at_20[0x10];
5055         u8         op_mod[0x10];
5056
5057         u8         reserved_at_40[0x8];
5058         u8         mkey_index[0x18];
5059
5060         u8         pg_access[0x1];
5061         u8         reserved_at_61[0x1f];
5062 };
5063
5064 struct mlx5_ifc_query_mad_demux_out_bits {
5065         u8         status[0x8];
5066         u8         reserved_at_8[0x18];
5067
5068         u8         syndrome[0x20];
5069
5070         u8         reserved_at_40[0x40];
5071
5072         u8         mad_dumux_parameters_block[0x20];
5073 };
5074
5075 struct mlx5_ifc_query_mad_demux_in_bits {
5076         u8         opcode[0x10];
5077         u8         reserved_at_10[0x10];
5078
5079         u8         reserved_at_20[0x10];
5080         u8         op_mod[0x10];
5081
5082         u8         reserved_at_40[0x40];
5083 };
5084
5085 struct mlx5_ifc_query_l2_table_entry_out_bits {
5086         u8         status[0x8];
5087         u8         reserved_at_8[0x18];
5088
5089         u8         syndrome[0x20];
5090
5091         u8         reserved_at_40[0xa0];
5092
5093         u8         reserved_at_e0[0x13];
5094         u8         vlan_valid[0x1];
5095         u8         vlan[0xc];
5096
5097         struct mlx5_ifc_mac_address_layout_bits mac_address;
5098
5099         u8         reserved_at_140[0xc0];
5100 };
5101
5102 struct mlx5_ifc_query_l2_table_entry_in_bits {
5103         u8         opcode[0x10];
5104         u8         reserved_at_10[0x10];
5105
5106         u8         reserved_at_20[0x10];
5107         u8         op_mod[0x10];
5108
5109         u8         reserved_at_40[0x60];
5110
5111         u8         reserved_at_a0[0x8];
5112         u8         table_index[0x18];
5113
5114         u8         reserved_at_c0[0x140];
5115 };
5116
5117 struct mlx5_ifc_query_issi_out_bits {
5118         u8         status[0x8];
5119         u8         reserved_at_8[0x18];
5120
5121         u8         syndrome[0x20];
5122
5123         u8         reserved_at_40[0x10];
5124         u8         current_issi[0x10];
5125
5126         u8         reserved_at_60[0xa0];
5127
5128         u8         reserved_at_100[76][0x8];
5129         u8         supported_issi_dw0[0x20];
5130 };
5131
5132 struct mlx5_ifc_query_issi_in_bits {
5133         u8         opcode[0x10];
5134         u8         reserved_at_10[0x10];
5135
5136         u8         reserved_at_20[0x10];
5137         u8         op_mod[0x10];
5138
5139         u8         reserved_at_40[0x40];
5140 };
5141
5142 struct mlx5_ifc_set_driver_version_out_bits {
5143         u8         status[0x8];
5144         u8         reserved_0[0x18];
5145
5146         u8         syndrome[0x20];
5147         u8         reserved_1[0x40];
5148 };
5149
5150 struct mlx5_ifc_set_driver_version_in_bits {
5151         u8         opcode[0x10];
5152         u8         reserved_0[0x10];
5153
5154         u8         reserved_1[0x10];
5155         u8         op_mod[0x10];
5156
5157         u8         reserved_2[0x40];
5158         u8         driver_version[64][0x8];
5159 };
5160
5161 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5162         u8         status[0x8];
5163         u8         reserved_at_8[0x18];
5164
5165         u8         syndrome[0x20];
5166
5167         u8         reserved_at_40[0x40];
5168
5169         struct mlx5_ifc_pkey_bits pkey[];
5170 };
5171
5172 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5173         u8         opcode[0x10];
5174         u8         reserved_at_10[0x10];
5175
5176         u8         reserved_at_20[0x10];
5177         u8         op_mod[0x10];
5178
5179         u8         other_vport[0x1];
5180         u8         reserved_at_41[0xb];
5181         u8         port_num[0x4];
5182         u8         vport_number[0x10];
5183
5184         u8         reserved_at_60[0x10];
5185         u8         pkey_index[0x10];
5186 };
5187
5188 enum {
5189         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
5190         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
5191         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5192 };
5193
5194 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5195         u8         status[0x8];
5196         u8         reserved_at_8[0x18];
5197
5198         u8         syndrome[0x20];
5199
5200         u8         reserved_at_40[0x20];
5201
5202         u8         gids_num[0x10];
5203         u8         reserved_at_70[0x10];
5204
5205         struct mlx5_ifc_array128_auto_bits gid[];
5206 };
5207
5208 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5209         u8         opcode[0x10];
5210         u8         reserved_at_10[0x10];
5211
5212         u8         reserved_at_20[0x10];
5213         u8         op_mod[0x10];
5214
5215         u8         other_vport[0x1];
5216         u8         reserved_at_41[0xb];
5217         u8         port_num[0x4];
5218         u8         vport_number[0x10];
5219
5220         u8         reserved_at_60[0x10];
5221         u8         gid_index[0x10];
5222 };
5223
5224 struct mlx5_ifc_query_hca_vport_context_out_bits {
5225         u8         status[0x8];
5226         u8         reserved_at_8[0x18];
5227
5228         u8         syndrome[0x20];
5229
5230         u8         reserved_at_40[0x40];
5231
5232         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5233 };
5234
5235 struct mlx5_ifc_query_hca_vport_context_in_bits {
5236         u8         opcode[0x10];
5237         u8         reserved_at_10[0x10];
5238
5239         u8         reserved_at_20[0x10];
5240         u8         op_mod[0x10];
5241
5242         u8         other_vport[0x1];
5243         u8         reserved_at_41[0xb];
5244         u8         port_num[0x4];
5245         u8         vport_number[0x10];
5246
5247         u8         reserved_at_60[0x20];
5248 };
5249
5250 struct mlx5_ifc_query_hca_cap_out_bits {
5251         u8         status[0x8];
5252         u8         reserved_at_8[0x18];
5253
5254         u8         syndrome[0x20];
5255
5256         u8         reserved_at_40[0x40];
5257
5258         union mlx5_ifc_hca_cap_union_bits capability;
5259 };
5260
5261 struct mlx5_ifc_query_hca_cap_in_bits {
5262         u8         opcode[0x10];
5263         u8         reserved_at_10[0x10];
5264
5265         u8         reserved_at_20[0x10];
5266         u8         op_mod[0x10];
5267
5268         u8         other_function[0x1];
5269         u8         reserved_at_41[0xf];
5270         u8         function_id[0x10];
5271
5272         u8         reserved_at_60[0x20];
5273 };
5274
5275 struct mlx5_ifc_other_hca_cap_bits {
5276         u8         roce[0x1];
5277         u8         reserved_at_1[0x27f];
5278 };
5279
5280 struct mlx5_ifc_query_other_hca_cap_out_bits {
5281         u8         status[0x8];
5282         u8         reserved_at_8[0x18];
5283
5284         u8         syndrome[0x20];
5285
5286         u8         reserved_at_40[0x40];
5287
5288         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5289 };
5290
5291 struct mlx5_ifc_query_other_hca_cap_in_bits {
5292         u8         opcode[0x10];
5293         u8         reserved_at_10[0x10];
5294
5295         u8         reserved_at_20[0x10];
5296         u8         op_mod[0x10];
5297
5298         u8         reserved_at_40[0x10];
5299         u8         function_id[0x10];
5300
5301         u8         reserved_at_60[0x20];
5302 };
5303
5304 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5305         u8         status[0x8];
5306         u8         reserved_at_8[0x18];
5307
5308         u8         syndrome[0x20];
5309
5310         u8         reserved_at_40[0x40];
5311 };
5312
5313 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5314         u8         opcode[0x10];
5315         u8         reserved_at_10[0x10];
5316
5317         u8         reserved_at_20[0x10];
5318         u8         op_mod[0x10];
5319
5320         u8         reserved_at_40[0x10];
5321         u8         function_id[0x10];
5322         u8         field_select[0x20];
5323
5324         struct     mlx5_ifc_other_hca_cap_bits other_capability;
5325 };
5326
5327 struct mlx5_ifc_flow_table_context_bits {
5328         u8         reformat_en[0x1];
5329         u8         decap_en[0x1];
5330         u8         sw_owner[0x1];
5331         u8         termination_table[0x1];
5332         u8         table_miss_action[0x4];
5333         u8         level[0x8];
5334         u8         reserved_at_10[0x8];
5335         u8         log_size[0x8];
5336
5337         u8         reserved_at_20[0x8];
5338         u8         table_miss_id[0x18];
5339
5340         u8         reserved_at_40[0x8];
5341         u8         lag_master_next_table_id[0x18];
5342
5343         u8         reserved_at_60[0x60];
5344
5345         u8         sw_owner_icm_root_1[0x40];
5346
5347         u8         sw_owner_icm_root_0[0x40];
5348
5349 };
5350
5351 struct mlx5_ifc_query_flow_table_out_bits {
5352         u8         status[0x8];
5353         u8         reserved_at_8[0x18];
5354
5355         u8         syndrome[0x20];
5356
5357         u8         reserved_at_40[0x80];
5358
5359         struct mlx5_ifc_flow_table_context_bits flow_table_context;
5360 };
5361
5362 struct mlx5_ifc_query_flow_table_in_bits {
5363         u8         opcode[0x10];
5364         u8         reserved_at_10[0x10];
5365
5366         u8         reserved_at_20[0x10];
5367         u8         op_mod[0x10];
5368
5369         u8         reserved_at_40[0x40];
5370
5371         u8         table_type[0x8];
5372         u8         reserved_at_88[0x18];
5373
5374         u8         reserved_at_a0[0x8];
5375         u8         table_id[0x18];
5376
5377         u8         reserved_at_c0[0x140];
5378 };
5379
5380 struct mlx5_ifc_query_fte_out_bits {
5381         u8         status[0x8];
5382         u8         reserved_at_8[0x18];
5383
5384         u8         syndrome[0x20];
5385
5386         u8         reserved_at_40[0x1c0];
5387
5388         struct mlx5_ifc_flow_context_bits flow_context;
5389 };
5390
5391 struct mlx5_ifc_query_fte_in_bits {
5392         u8         opcode[0x10];
5393         u8         reserved_at_10[0x10];
5394
5395         u8         reserved_at_20[0x10];
5396         u8         op_mod[0x10];
5397
5398         u8         reserved_at_40[0x40];
5399
5400         u8         table_type[0x8];
5401         u8         reserved_at_88[0x18];
5402
5403         u8         reserved_at_a0[0x8];
5404         u8         table_id[0x18];
5405
5406         u8         reserved_at_c0[0x40];
5407
5408         u8         flow_index[0x20];
5409
5410         u8         reserved_at_120[0xe0];
5411 };
5412
5413 enum {
5414         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5415         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5416         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5417         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5418         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5419 };
5420
5421 struct mlx5_ifc_query_flow_group_out_bits {
5422         u8         status[0x8];
5423         u8         reserved_at_8[0x18];
5424
5425         u8         syndrome[0x20];
5426
5427         u8         reserved_at_40[0xa0];
5428
5429         u8         start_flow_index[0x20];
5430
5431         u8         reserved_at_100[0x20];
5432
5433         u8         end_flow_index[0x20];
5434
5435         u8         reserved_at_140[0xa0];
5436
5437         u8         reserved_at_1e0[0x18];
5438         u8         match_criteria_enable[0x8];
5439
5440         struct mlx5_ifc_fte_match_param_bits match_criteria;
5441
5442         u8         reserved_at_1200[0xe00];
5443 };
5444
5445 struct mlx5_ifc_query_flow_group_in_bits {
5446         u8         opcode[0x10];
5447         u8         reserved_at_10[0x10];
5448
5449         u8         reserved_at_20[0x10];
5450         u8         op_mod[0x10];
5451
5452         u8         reserved_at_40[0x40];
5453
5454         u8         table_type[0x8];
5455         u8         reserved_at_88[0x18];
5456
5457         u8         reserved_at_a0[0x8];
5458         u8         table_id[0x18];
5459
5460         u8         group_id[0x20];
5461
5462         u8         reserved_at_e0[0x120];
5463 };
5464
5465 struct mlx5_ifc_query_flow_counter_out_bits {
5466         u8         status[0x8];
5467         u8         reserved_at_8[0x18];
5468
5469         u8         syndrome[0x20];
5470
5471         u8         reserved_at_40[0x40];
5472
5473         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
5474 };
5475
5476 struct mlx5_ifc_query_flow_counter_in_bits {
5477         u8         opcode[0x10];
5478         u8         reserved_at_10[0x10];
5479
5480         u8         reserved_at_20[0x10];
5481         u8         op_mod[0x10];
5482
5483         u8         reserved_at_40[0x80];
5484
5485         u8         clear[0x1];
5486         u8         reserved_at_c1[0xf];
5487         u8         num_of_counters[0x10];
5488
5489         u8         flow_counter_id[0x20];
5490 };
5491
5492 struct mlx5_ifc_query_esw_vport_context_out_bits {
5493         u8         status[0x8];
5494         u8         reserved_at_8[0x18];
5495
5496         u8         syndrome[0x20];
5497
5498         u8         reserved_at_40[0x40];
5499
5500         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5501 };
5502
5503 struct mlx5_ifc_query_esw_vport_context_in_bits {
5504         u8         opcode[0x10];
5505         u8         reserved_at_10[0x10];
5506
5507         u8         reserved_at_20[0x10];
5508         u8         op_mod[0x10];
5509
5510         u8         other_vport[0x1];
5511         u8         reserved_at_41[0xf];
5512         u8         vport_number[0x10];
5513
5514         u8         reserved_at_60[0x20];
5515 };
5516
5517 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5518         u8         status[0x8];
5519         u8         reserved_at_8[0x18];
5520
5521         u8         syndrome[0x20];
5522
5523         u8         reserved_at_40[0x40];
5524 };
5525
5526 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5527         u8         reserved_at_0[0x1b];
5528         u8         fdb_to_vport_reg_c_id[0x1];
5529         u8         vport_cvlan_insert[0x1];
5530         u8         vport_svlan_insert[0x1];
5531         u8         vport_cvlan_strip[0x1];
5532         u8         vport_svlan_strip[0x1];
5533 };
5534
5535 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5536         u8         opcode[0x10];
5537         u8         reserved_at_10[0x10];
5538
5539         u8         reserved_at_20[0x10];
5540         u8         op_mod[0x10];
5541
5542         u8         other_vport[0x1];
5543         u8         reserved_at_41[0xf];
5544         u8         vport_number[0x10];
5545
5546         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5547
5548         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5549 };
5550
5551 struct mlx5_ifc_query_eq_out_bits {
5552         u8         status[0x8];
5553         u8         reserved_at_8[0x18];
5554
5555         u8         syndrome[0x20];
5556
5557         u8         reserved_at_40[0x40];
5558
5559         struct mlx5_ifc_eqc_bits eq_context_entry;
5560
5561         u8         reserved_at_280[0x40];
5562
5563         u8         event_bitmask[0x40];
5564
5565         u8         reserved_at_300[0x580];
5566
5567         u8         pas[][0x40];
5568 };
5569
5570 struct mlx5_ifc_query_eq_in_bits {
5571         u8         opcode[0x10];
5572         u8         reserved_at_10[0x10];
5573
5574         u8         reserved_at_20[0x10];
5575         u8         op_mod[0x10];
5576
5577         u8         reserved_at_40[0x18];
5578         u8         eq_number[0x8];
5579
5580         u8         reserved_at_60[0x20];
5581 };
5582
5583 struct mlx5_ifc_packet_reformat_context_in_bits {
5584         u8         reserved_at_0[0x5];
5585         u8         reformat_type[0x3];
5586         u8         reserved_at_8[0xe];
5587         u8         reformat_data_size[0xa];
5588
5589         u8         reserved_at_20[0x10];
5590         u8         reformat_data[2][0x8];
5591
5592         u8         more_reformat_data[][0x8];
5593 };
5594
5595 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5596         u8         status[0x8];
5597         u8         reserved_at_8[0x18];
5598
5599         u8         syndrome[0x20];
5600
5601         u8         reserved_at_40[0xa0];
5602
5603         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
5604 };
5605
5606 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5607         u8         opcode[0x10];
5608         u8         reserved_at_10[0x10];
5609
5610         u8         reserved_at_20[0x10];
5611         u8         op_mod[0x10];
5612
5613         u8         packet_reformat_id[0x20];
5614
5615         u8         reserved_at_60[0xa0];
5616 };
5617
5618 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5619         u8         status[0x8];
5620         u8         reserved_at_8[0x18];
5621
5622         u8         syndrome[0x20];
5623
5624         u8         packet_reformat_id[0x20];
5625
5626         u8         reserved_at_60[0x20];
5627 };
5628
5629 enum mlx5_reformat_ctx_type {
5630         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5631         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5632         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5633         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5634         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5635 };
5636
5637 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5638         u8         opcode[0x10];
5639         u8         reserved_at_10[0x10];
5640
5641         u8         reserved_at_20[0x10];
5642         u8         op_mod[0x10];
5643
5644         u8         reserved_at_40[0xa0];
5645
5646         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5647 };
5648
5649 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5650         u8         status[0x8];
5651         u8         reserved_at_8[0x18];
5652
5653         u8         syndrome[0x20];
5654
5655         u8         reserved_at_40[0x40];
5656 };
5657
5658 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5659         u8         opcode[0x10];
5660         u8         reserved_at_10[0x10];
5661
5662         u8         reserved_20[0x10];
5663         u8         op_mod[0x10];
5664
5665         u8         packet_reformat_id[0x20];
5666
5667         u8         reserved_60[0x20];
5668 };
5669
5670 struct mlx5_ifc_set_action_in_bits {
5671         u8         action_type[0x4];
5672         u8         field[0xc];
5673         u8         reserved_at_10[0x3];
5674         u8         offset[0x5];
5675         u8         reserved_at_18[0x3];
5676         u8         length[0x5];
5677
5678         u8         data[0x20];
5679 };
5680
5681 struct mlx5_ifc_add_action_in_bits {
5682         u8         action_type[0x4];
5683         u8         field[0xc];
5684         u8         reserved_at_10[0x10];
5685
5686         u8         data[0x20];
5687 };
5688
5689 struct mlx5_ifc_copy_action_in_bits {
5690         u8         action_type[0x4];
5691         u8         src_field[0xc];
5692         u8         reserved_at_10[0x3];
5693         u8         src_offset[0x5];
5694         u8         reserved_at_18[0x3];
5695         u8         length[0x5];
5696
5697         u8         reserved_at_20[0x4];
5698         u8         dst_field[0xc];
5699         u8         reserved_at_30[0x3];
5700         u8         dst_offset[0x5];
5701         u8         reserved_at_38[0x8];
5702 };
5703
5704 union mlx5_ifc_set_add_copy_action_in_auto_bits {
5705         struct mlx5_ifc_set_action_in_bits  set_action_in;
5706         struct mlx5_ifc_add_action_in_bits  add_action_in;
5707         struct mlx5_ifc_copy_action_in_bits copy_action_in;
5708         u8         reserved_at_0[0x40];
5709 };
5710
5711 enum {
5712         MLX5_ACTION_TYPE_SET   = 0x1,
5713         MLX5_ACTION_TYPE_ADD   = 0x2,
5714         MLX5_ACTION_TYPE_COPY  = 0x3,
5715 };
5716
5717 enum {
5718         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5719         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5720         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5721         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5722         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5723         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5724         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5725         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5726         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5727         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5728         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5729         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5730         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5731         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5732         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5733         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5734         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5735         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5736         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5737         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5738         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5739         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5740         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5741         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5742         MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
5743         MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
5744         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5745         MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
5746         MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
5747         MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
5748         MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
5749         MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
5750         MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
5751         MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
5752         MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
5753         MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
5754 };
5755
5756 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5757         u8         status[0x8];
5758         u8         reserved_at_8[0x18];
5759
5760         u8         syndrome[0x20];
5761
5762         u8         modify_header_id[0x20];
5763
5764         u8         reserved_at_60[0x20];
5765 };
5766
5767 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5768         u8         opcode[0x10];
5769         u8         reserved_at_10[0x10];
5770
5771         u8         reserved_at_20[0x10];
5772         u8         op_mod[0x10];
5773
5774         u8         reserved_at_40[0x20];
5775
5776         u8         table_type[0x8];
5777         u8         reserved_at_68[0x10];
5778         u8         num_of_actions[0x8];
5779
5780         union mlx5_ifc_set_add_copy_action_in_auto_bits actions[0];
5781 };
5782
5783 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5784         u8         status[0x8];
5785         u8         reserved_at_8[0x18];
5786
5787         u8         syndrome[0x20];
5788
5789         u8         reserved_at_40[0x40];
5790 };
5791
5792 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5793         u8         opcode[0x10];
5794         u8         reserved_at_10[0x10];
5795
5796         u8         reserved_at_20[0x10];
5797         u8         op_mod[0x10];
5798
5799         u8         modify_header_id[0x20];
5800
5801         u8         reserved_at_60[0x20];
5802 };
5803
5804 struct mlx5_ifc_query_dct_out_bits {
5805         u8         status[0x8];
5806         u8         reserved_at_8[0x18];
5807
5808         u8         syndrome[0x20];
5809
5810         u8         reserved_at_40[0x40];
5811
5812         struct mlx5_ifc_dctc_bits dct_context_entry;
5813
5814         u8         reserved_at_280[0x180];
5815 };
5816
5817 struct mlx5_ifc_query_dct_in_bits {
5818         u8         opcode[0x10];
5819         u8         reserved_at_10[0x10];
5820
5821         u8         reserved_at_20[0x10];
5822         u8         op_mod[0x10];
5823
5824         u8         reserved_at_40[0x8];
5825         u8         dctn[0x18];
5826
5827         u8         reserved_at_60[0x20];
5828 };
5829
5830 struct mlx5_ifc_query_cq_out_bits {
5831         u8         status[0x8];
5832         u8         reserved_at_8[0x18];
5833
5834         u8         syndrome[0x20];
5835
5836         u8         reserved_at_40[0x40];
5837
5838         struct mlx5_ifc_cqc_bits cq_context;
5839
5840         u8         reserved_at_280[0x600];
5841
5842         u8         pas[][0x40];
5843 };
5844
5845 struct mlx5_ifc_query_cq_in_bits {
5846         u8         opcode[0x10];
5847         u8         reserved_at_10[0x10];
5848
5849         u8         reserved_at_20[0x10];
5850         u8         op_mod[0x10];
5851
5852         u8         reserved_at_40[0x8];
5853         u8         cqn[0x18];
5854
5855         u8         reserved_at_60[0x20];
5856 };
5857
5858 struct mlx5_ifc_query_cong_status_out_bits {
5859         u8         status[0x8];
5860         u8         reserved_at_8[0x18];
5861
5862         u8         syndrome[0x20];
5863
5864         u8         reserved_at_40[0x20];
5865
5866         u8         enable[0x1];
5867         u8         tag_enable[0x1];
5868         u8         reserved_at_62[0x1e];
5869 };
5870
5871 struct mlx5_ifc_query_cong_status_in_bits {
5872         u8         opcode[0x10];
5873         u8         reserved_at_10[0x10];
5874
5875         u8         reserved_at_20[0x10];
5876         u8         op_mod[0x10];
5877
5878         u8         reserved_at_40[0x18];
5879         u8         priority[0x4];
5880         u8         cong_protocol[0x4];
5881
5882         u8         reserved_at_60[0x20];
5883 };
5884
5885 struct mlx5_ifc_query_cong_statistics_out_bits {
5886         u8         status[0x8];
5887         u8         reserved_at_8[0x18];
5888
5889         u8         syndrome[0x20];
5890
5891         u8         reserved_at_40[0x40];
5892
5893         u8         rp_cur_flows[0x20];
5894
5895         u8         sum_flows[0x20];
5896
5897         u8         rp_cnp_ignored_high[0x20];
5898
5899         u8         rp_cnp_ignored_low[0x20];
5900
5901         u8         rp_cnp_handled_high[0x20];
5902
5903         u8         rp_cnp_handled_low[0x20];
5904
5905         u8         reserved_at_140[0x100];
5906
5907         u8         time_stamp_high[0x20];
5908
5909         u8         time_stamp_low[0x20];
5910
5911         u8         accumulators_period[0x20];
5912
5913         u8         np_ecn_marked_roce_packets_high[0x20];
5914
5915         u8         np_ecn_marked_roce_packets_low[0x20];
5916
5917         u8         np_cnp_sent_high[0x20];
5918
5919         u8         np_cnp_sent_low[0x20];
5920
5921         u8         reserved_at_320[0x560];
5922 };
5923
5924 struct mlx5_ifc_query_cong_statistics_in_bits {
5925         u8         opcode[0x10];
5926         u8         reserved_at_10[0x10];
5927
5928         u8         reserved_at_20[0x10];
5929         u8         op_mod[0x10];
5930
5931         u8         clear[0x1];
5932         u8         reserved_at_41[0x1f];
5933
5934         u8         reserved_at_60[0x20];
5935 };
5936
5937 struct mlx5_ifc_query_cong_params_out_bits {
5938         u8         status[0x8];
5939         u8         reserved_at_8[0x18];
5940
5941         u8         syndrome[0x20];
5942
5943         u8         reserved_at_40[0x40];
5944
5945         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5946 };
5947
5948 struct mlx5_ifc_query_cong_params_in_bits {
5949         u8         opcode[0x10];
5950         u8         reserved_at_10[0x10];
5951
5952         u8         reserved_at_20[0x10];
5953         u8         op_mod[0x10];
5954
5955         u8         reserved_at_40[0x1c];
5956         u8         cong_protocol[0x4];
5957
5958         u8         reserved_at_60[0x20];
5959 };
5960
5961 struct mlx5_ifc_query_adapter_out_bits {
5962         u8         status[0x8];
5963         u8         reserved_at_8[0x18];
5964
5965         u8         syndrome[0x20];
5966
5967         u8         reserved_at_40[0x40];
5968
5969         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5970 };
5971
5972 struct mlx5_ifc_query_adapter_in_bits {
5973         u8         opcode[0x10];
5974         u8         reserved_at_10[0x10];
5975
5976         u8         reserved_at_20[0x10];
5977         u8         op_mod[0x10];
5978
5979         u8         reserved_at_40[0x40];
5980 };
5981
5982 struct mlx5_ifc_qp_2rst_out_bits {
5983         u8         status[0x8];
5984         u8         reserved_at_8[0x18];
5985
5986         u8         syndrome[0x20];
5987
5988         u8         reserved_at_40[0x40];
5989 };
5990
5991 struct mlx5_ifc_qp_2rst_in_bits {
5992         u8         opcode[0x10];
5993         u8         uid[0x10];
5994
5995         u8         reserved_at_20[0x10];
5996         u8         op_mod[0x10];
5997
5998         u8         reserved_at_40[0x8];
5999         u8         qpn[0x18];
6000
6001         u8         reserved_at_60[0x20];
6002 };
6003
6004 struct mlx5_ifc_qp_2err_out_bits {
6005         u8         status[0x8];
6006         u8         reserved_at_8[0x18];
6007
6008         u8         syndrome[0x20];
6009
6010         u8         reserved_at_40[0x40];
6011 };
6012
6013 struct mlx5_ifc_qp_2err_in_bits {
6014         u8         opcode[0x10];
6015         u8         uid[0x10];
6016
6017         u8         reserved_at_20[0x10];
6018         u8         op_mod[0x10];
6019
6020         u8         reserved_at_40[0x8];
6021         u8         qpn[0x18];
6022
6023         u8         reserved_at_60[0x20];
6024 };
6025
6026 struct mlx5_ifc_page_fault_resume_out_bits {
6027         u8         status[0x8];
6028         u8         reserved_at_8[0x18];
6029
6030         u8         syndrome[0x20];
6031
6032         u8         reserved_at_40[0x40];
6033 };
6034
6035 struct mlx5_ifc_page_fault_resume_in_bits {
6036         u8         opcode[0x10];
6037         u8         reserved_at_10[0x10];
6038
6039         u8         reserved_at_20[0x10];
6040         u8         op_mod[0x10];
6041
6042         u8         error[0x1];
6043         u8         reserved_at_41[0x4];
6044         u8         page_fault_type[0x3];
6045         u8         wq_number[0x18];
6046
6047         u8         reserved_at_60[0x8];
6048         u8         token[0x18];
6049 };
6050
6051 struct mlx5_ifc_nop_out_bits {
6052         u8         status[0x8];
6053         u8         reserved_at_8[0x18];
6054
6055         u8         syndrome[0x20];
6056
6057         u8         reserved_at_40[0x40];
6058 };
6059
6060 struct mlx5_ifc_nop_in_bits {
6061         u8         opcode[0x10];
6062         u8         reserved_at_10[0x10];
6063
6064         u8         reserved_at_20[0x10];
6065         u8         op_mod[0x10];
6066
6067         u8         reserved_at_40[0x40];
6068 };
6069
6070 struct mlx5_ifc_modify_vport_state_out_bits {
6071         u8         status[0x8];
6072         u8         reserved_at_8[0x18];
6073
6074         u8         syndrome[0x20];
6075
6076         u8         reserved_at_40[0x40];
6077 };
6078
6079 struct mlx5_ifc_modify_vport_state_in_bits {
6080         u8         opcode[0x10];
6081         u8         reserved_at_10[0x10];
6082
6083         u8         reserved_at_20[0x10];
6084         u8         op_mod[0x10];
6085
6086         u8         other_vport[0x1];
6087         u8         reserved_at_41[0xf];
6088         u8         vport_number[0x10];
6089
6090         u8         reserved_at_60[0x18];
6091         u8         admin_state[0x4];
6092         u8         reserved_at_7c[0x4];
6093 };
6094
6095 struct mlx5_ifc_modify_tis_out_bits {
6096         u8         status[0x8];
6097         u8         reserved_at_8[0x18];
6098
6099         u8         syndrome[0x20];
6100
6101         u8         reserved_at_40[0x40];
6102 };
6103
6104 struct mlx5_ifc_modify_tis_bitmask_bits {
6105         u8         reserved_at_0[0x20];
6106
6107         u8         reserved_at_20[0x1d];
6108         u8         lag_tx_port_affinity[0x1];
6109         u8         strict_lag_tx_port_affinity[0x1];
6110         u8         prio[0x1];
6111 };
6112
6113 struct mlx5_ifc_modify_tis_in_bits {
6114         u8         opcode[0x10];
6115         u8         uid[0x10];
6116
6117         u8         reserved_at_20[0x10];
6118         u8         op_mod[0x10];
6119
6120         u8         reserved_at_40[0x8];
6121         u8         tisn[0x18];
6122
6123         u8         reserved_at_60[0x20];
6124
6125         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6126
6127         u8         reserved_at_c0[0x40];
6128
6129         struct mlx5_ifc_tisc_bits ctx;
6130 };
6131
6132 struct mlx5_ifc_modify_tir_bitmask_bits {
6133         u8         reserved_at_0[0x20];
6134
6135         u8         reserved_at_20[0x1b];
6136         u8         self_lb_en[0x1];
6137         u8         reserved_at_3c[0x1];
6138         u8         hash[0x1];
6139         u8         reserved_at_3e[0x1];
6140         u8         lro[0x1];
6141 };
6142
6143 struct mlx5_ifc_modify_tir_out_bits {
6144         u8         status[0x8];
6145         u8         reserved_at_8[0x18];
6146
6147         u8         syndrome[0x20];
6148
6149         u8         reserved_at_40[0x40];
6150 };
6151
6152 struct mlx5_ifc_modify_tir_in_bits {
6153         u8         opcode[0x10];
6154         u8         uid[0x10];
6155
6156         u8         reserved_at_20[0x10];
6157         u8         op_mod[0x10];
6158
6159         u8         reserved_at_40[0x8];
6160         u8         tirn[0x18];
6161
6162         u8         reserved_at_60[0x20];
6163
6164         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6165
6166         u8         reserved_at_c0[0x40];
6167
6168         struct mlx5_ifc_tirc_bits ctx;
6169 };
6170
6171 struct mlx5_ifc_modify_sq_out_bits {
6172         u8         status[0x8];
6173         u8         reserved_at_8[0x18];
6174
6175         u8         syndrome[0x20];
6176
6177         u8         reserved_at_40[0x40];
6178 };
6179
6180 struct mlx5_ifc_modify_sq_in_bits {
6181         u8         opcode[0x10];
6182         u8         uid[0x10];
6183
6184         u8         reserved_at_20[0x10];
6185         u8         op_mod[0x10];
6186
6187         u8         sq_state[0x4];
6188         u8         reserved_at_44[0x4];
6189         u8         sqn[0x18];
6190
6191         u8         reserved_at_60[0x20];
6192
6193         u8         modify_bitmask[0x40];
6194
6195         u8         reserved_at_c0[0x40];
6196
6197         struct mlx5_ifc_sqc_bits ctx;
6198 };
6199
6200 struct mlx5_ifc_modify_scheduling_element_out_bits {
6201         u8         status[0x8];
6202         u8         reserved_at_8[0x18];
6203
6204         u8         syndrome[0x20];
6205
6206         u8         reserved_at_40[0x1c0];
6207 };
6208
6209 enum {
6210         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6211         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6212 };
6213
6214 struct mlx5_ifc_modify_scheduling_element_in_bits {
6215         u8         opcode[0x10];
6216         u8         reserved_at_10[0x10];
6217
6218         u8         reserved_at_20[0x10];
6219         u8         op_mod[0x10];
6220
6221         u8         scheduling_hierarchy[0x8];
6222         u8         reserved_at_48[0x18];
6223
6224         u8         scheduling_element_id[0x20];
6225
6226         u8         reserved_at_80[0x20];
6227
6228         u8         modify_bitmask[0x20];
6229
6230         u8         reserved_at_c0[0x40];
6231
6232         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6233
6234         u8         reserved_at_300[0x100];
6235 };
6236
6237 struct mlx5_ifc_modify_rqt_out_bits {
6238         u8         status[0x8];
6239         u8         reserved_at_8[0x18];
6240
6241         u8         syndrome[0x20];
6242
6243         u8         reserved_at_40[0x40];
6244 };
6245
6246 struct mlx5_ifc_rqt_bitmask_bits {
6247         u8         reserved_at_0[0x20];
6248
6249         u8         reserved_at_20[0x1f];
6250         u8         rqn_list[0x1];
6251 };
6252
6253 struct mlx5_ifc_modify_rqt_in_bits {
6254         u8         opcode[0x10];
6255         u8         uid[0x10];
6256
6257         u8         reserved_at_20[0x10];
6258         u8         op_mod[0x10];
6259
6260         u8         reserved_at_40[0x8];
6261         u8         rqtn[0x18];
6262
6263         u8         reserved_at_60[0x20];
6264
6265         struct mlx5_ifc_rqt_bitmask_bits bitmask;
6266
6267         u8         reserved_at_c0[0x40];
6268
6269         struct mlx5_ifc_rqtc_bits ctx;
6270 };
6271
6272 struct mlx5_ifc_modify_rq_out_bits {
6273         u8         status[0x8];
6274         u8         reserved_at_8[0x18];
6275
6276         u8         syndrome[0x20];
6277
6278         u8         reserved_at_40[0x40];
6279 };
6280
6281 enum {
6282         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6283         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6284         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6285 };
6286
6287 struct mlx5_ifc_modify_rq_in_bits {
6288         u8         opcode[0x10];
6289         u8         uid[0x10];
6290
6291         u8         reserved_at_20[0x10];
6292         u8         op_mod[0x10];
6293
6294         u8         rq_state[0x4];
6295         u8         reserved_at_44[0x4];
6296         u8         rqn[0x18];
6297
6298         u8         reserved_at_60[0x20];
6299
6300         u8         modify_bitmask[0x40];
6301
6302         u8         reserved_at_c0[0x40];
6303
6304         struct mlx5_ifc_rqc_bits ctx;
6305 };
6306
6307 struct mlx5_ifc_modify_rmp_out_bits {
6308         u8         status[0x8];
6309         u8         reserved_at_8[0x18];
6310
6311         u8         syndrome[0x20];
6312
6313         u8         reserved_at_40[0x40];
6314 };
6315
6316 struct mlx5_ifc_rmp_bitmask_bits {
6317         u8         reserved_at_0[0x20];
6318
6319         u8         reserved_at_20[0x1f];
6320         u8         lwm[0x1];
6321 };
6322
6323 struct mlx5_ifc_modify_rmp_in_bits {
6324         u8         opcode[0x10];
6325         u8         uid[0x10];
6326
6327         u8         reserved_at_20[0x10];
6328         u8         op_mod[0x10];
6329
6330         u8         rmp_state[0x4];
6331         u8         reserved_at_44[0x4];
6332         u8         rmpn[0x18];
6333
6334         u8         reserved_at_60[0x20];
6335
6336         struct mlx5_ifc_rmp_bitmask_bits bitmask;
6337
6338         u8         reserved_at_c0[0x40];
6339
6340         struct mlx5_ifc_rmpc_bits ctx;
6341 };
6342
6343 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6344         u8         status[0x8];
6345         u8         reserved_at_8[0x18];
6346
6347         u8         syndrome[0x20];
6348
6349         u8         reserved_at_40[0x40];
6350 };
6351
6352 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6353         u8         reserved_at_0[0x12];
6354         u8         affiliation[0x1];
6355         u8         reserved_at_13[0x1];
6356         u8         disable_uc_local_lb[0x1];
6357         u8         disable_mc_local_lb[0x1];
6358         u8         node_guid[0x1];
6359         u8         port_guid[0x1];
6360         u8         min_inline[0x1];
6361         u8         mtu[0x1];
6362         u8         change_event[0x1];
6363         u8         promisc[0x1];
6364         u8         permanent_address[0x1];
6365         u8         addresses_list[0x1];
6366         u8         roce_en[0x1];
6367         u8         reserved_at_1f[0x1];
6368 };
6369
6370 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6371         u8         opcode[0x10];
6372         u8         reserved_at_10[0x10];
6373
6374         u8         reserved_at_20[0x10];
6375         u8         op_mod[0x10];
6376
6377         u8         other_vport[0x1];
6378         u8         reserved_at_41[0xf];
6379         u8         vport_number[0x10];
6380
6381         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6382
6383         u8         reserved_at_80[0x780];
6384
6385         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6386 };
6387
6388 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6389         u8         status[0x8];
6390         u8         reserved_at_8[0x18];
6391
6392         u8         syndrome[0x20];
6393
6394         u8         reserved_at_40[0x40];
6395 };
6396
6397 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6398         u8         opcode[0x10];
6399         u8         reserved_at_10[0x10];
6400
6401         u8         reserved_at_20[0x10];
6402         u8         op_mod[0x10];
6403
6404         u8         other_vport[0x1];
6405         u8         reserved_at_41[0xb];
6406         u8         port_num[0x4];
6407         u8         vport_number[0x10];
6408
6409         u8         reserved_at_60[0x20];
6410
6411         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6412 };
6413
6414 struct mlx5_ifc_modify_cq_out_bits {
6415         u8         status[0x8];
6416         u8         reserved_at_8[0x18];
6417
6418         u8         syndrome[0x20];
6419
6420         u8         reserved_at_40[0x40];
6421 };
6422
6423 enum {
6424         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
6425         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
6426 };
6427
6428 struct mlx5_ifc_modify_cq_in_bits {
6429         u8         opcode[0x10];
6430         u8         uid[0x10];
6431
6432         u8         reserved_at_20[0x10];
6433         u8         op_mod[0x10];
6434
6435         u8         reserved_at_40[0x8];
6436         u8         cqn[0x18];
6437
6438         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6439
6440         struct mlx5_ifc_cqc_bits cq_context;
6441
6442         u8         reserved_at_280[0x60];
6443
6444         u8         cq_umem_valid[0x1];
6445         u8         reserved_at_2e1[0x1f];
6446
6447         u8         reserved_at_300[0x580];
6448
6449         u8         pas[][0x40];
6450 };
6451
6452 struct mlx5_ifc_modify_cong_status_out_bits {
6453         u8         status[0x8];
6454         u8         reserved_at_8[0x18];
6455
6456         u8         syndrome[0x20];
6457
6458         u8         reserved_at_40[0x40];
6459 };
6460
6461 struct mlx5_ifc_modify_cong_status_in_bits {
6462         u8         opcode[0x10];
6463         u8         reserved_at_10[0x10];
6464
6465         u8         reserved_at_20[0x10];
6466         u8         op_mod[0x10];
6467
6468         u8         reserved_at_40[0x18];
6469         u8         priority[0x4];
6470         u8         cong_protocol[0x4];
6471
6472         u8         enable[0x1];
6473         u8         tag_enable[0x1];
6474         u8         reserved_at_62[0x1e];
6475 };
6476
6477 struct mlx5_ifc_modify_cong_params_out_bits {
6478         u8         status[0x8];
6479         u8         reserved_at_8[0x18];
6480
6481         u8         syndrome[0x20];
6482
6483         u8         reserved_at_40[0x40];
6484 };
6485
6486 struct mlx5_ifc_modify_cong_params_in_bits {
6487         u8         opcode[0x10];
6488         u8         reserved_at_10[0x10];
6489
6490         u8         reserved_at_20[0x10];
6491         u8         op_mod[0x10];
6492
6493         u8         reserved_at_40[0x1c];
6494         u8         cong_protocol[0x4];
6495
6496         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6497
6498         u8         reserved_at_80[0x80];
6499
6500         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6501 };
6502
6503 struct mlx5_ifc_manage_pages_out_bits {
6504         u8         status[0x8];
6505         u8         reserved_at_8[0x18];
6506
6507         u8         syndrome[0x20];
6508
6509         u8         output_num_entries[0x20];
6510
6511         u8         reserved_at_60[0x20];
6512
6513         u8         pas[][0x40];
6514 };
6515
6516 enum {
6517         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6518         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6519         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6520 };
6521
6522 struct mlx5_ifc_manage_pages_in_bits {
6523         u8         opcode[0x10];
6524         u8         reserved_at_10[0x10];
6525
6526         u8         reserved_at_20[0x10];
6527         u8         op_mod[0x10];
6528
6529         u8         embedded_cpu_function[0x1];
6530         u8         reserved_at_41[0xf];
6531         u8         function_id[0x10];
6532
6533         u8         input_num_entries[0x20];
6534
6535         u8         pas[][0x40];
6536 };
6537
6538 struct mlx5_ifc_mad_ifc_out_bits {
6539         u8         status[0x8];
6540         u8         reserved_at_8[0x18];
6541
6542         u8         syndrome[0x20];
6543
6544         u8         reserved_at_40[0x40];
6545
6546         u8         response_mad_packet[256][0x8];
6547 };
6548
6549 struct mlx5_ifc_mad_ifc_in_bits {
6550         u8         opcode[0x10];
6551         u8         reserved_at_10[0x10];
6552
6553         u8         reserved_at_20[0x10];
6554         u8         op_mod[0x10];
6555
6556         u8         remote_lid[0x10];
6557         u8         reserved_at_50[0x8];
6558         u8         port[0x8];
6559
6560         u8         reserved_at_60[0x20];
6561
6562         u8         mad[256][0x8];
6563 };
6564
6565 struct mlx5_ifc_init_hca_out_bits {
6566         u8         status[0x8];
6567         u8         reserved_at_8[0x18];
6568
6569         u8         syndrome[0x20];
6570
6571         u8         reserved_at_40[0x40];
6572 };
6573
6574 struct mlx5_ifc_init_hca_in_bits {
6575         u8         opcode[0x10];
6576         u8         reserved_at_10[0x10];
6577
6578         u8         reserved_at_20[0x10];
6579         u8         op_mod[0x10];
6580
6581         u8         reserved_at_40[0x40];
6582         u8         sw_owner_id[4][0x20];
6583 };
6584
6585 struct mlx5_ifc_init2rtr_qp_out_bits {
6586         u8         status[0x8];
6587         u8         reserved_at_8[0x18];
6588
6589         u8         syndrome[0x20];
6590
6591         u8         reserved_at_40[0x20];
6592         u8         ece[0x20];
6593 };
6594
6595 struct mlx5_ifc_init2rtr_qp_in_bits {
6596         u8         opcode[0x10];
6597         u8         uid[0x10];
6598
6599         u8         reserved_at_20[0x10];
6600         u8         op_mod[0x10];
6601
6602         u8         reserved_at_40[0x8];
6603         u8         qpn[0x18];
6604
6605         u8         reserved_at_60[0x20];
6606
6607         u8         opt_param_mask[0x20];
6608
6609         u8         ece[0x20];
6610
6611         struct mlx5_ifc_qpc_bits qpc;
6612
6613         u8         reserved_at_800[0x80];
6614 };
6615
6616 struct mlx5_ifc_init2init_qp_out_bits {
6617         u8         status[0x8];
6618         u8         reserved_at_8[0x18];
6619
6620         u8         syndrome[0x20];
6621
6622         u8         reserved_at_40[0x40];
6623 };
6624
6625 struct mlx5_ifc_init2init_qp_in_bits {
6626         u8         opcode[0x10];
6627         u8         uid[0x10];
6628
6629         u8         reserved_at_20[0x10];
6630         u8         op_mod[0x10];
6631
6632         u8         reserved_at_40[0x8];
6633         u8         qpn[0x18];
6634
6635         u8         reserved_at_60[0x20];
6636
6637         u8         opt_param_mask[0x20];
6638
6639         u8         reserved_at_a0[0x20];
6640
6641         struct mlx5_ifc_qpc_bits qpc;
6642
6643         u8         reserved_at_800[0x80];
6644 };
6645
6646 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6647         u8         status[0x8];
6648         u8         reserved_at_8[0x18];
6649
6650         u8         syndrome[0x20];
6651
6652         u8         reserved_at_40[0x40];
6653
6654         u8         packet_headers_log[128][0x8];
6655
6656         u8         packet_syndrome[64][0x8];
6657 };
6658
6659 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6660         u8         opcode[0x10];
6661         u8         reserved_at_10[0x10];
6662
6663         u8         reserved_at_20[0x10];
6664         u8         op_mod[0x10];
6665
6666         u8         reserved_at_40[0x40];
6667 };
6668
6669 struct mlx5_ifc_gen_eqe_in_bits {
6670         u8         opcode[0x10];
6671         u8         reserved_at_10[0x10];
6672
6673         u8         reserved_at_20[0x10];
6674         u8         op_mod[0x10];
6675
6676         u8         reserved_at_40[0x18];
6677         u8         eq_number[0x8];
6678
6679         u8         reserved_at_60[0x20];
6680
6681         u8         eqe[64][0x8];
6682 };
6683
6684 struct mlx5_ifc_gen_eq_out_bits {
6685         u8         status[0x8];
6686         u8         reserved_at_8[0x18];
6687
6688         u8         syndrome[0x20];
6689
6690         u8         reserved_at_40[0x40];
6691 };
6692
6693 struct mlx5_ifc_enable_hca_out_bits {
6694         u8         status[0x8];
6695         u8         reserved_at_8[0x18];
6696
6697         u8         syndrome[0x20];
6698
6699         u8         reserved_at_40[0x20];
6700 };
6701
6702 struct mlx5_ifc_enable_hca_in_bits {
6703         u8         opcode[0x10];
6704         u8         reserved_at_10[0x10];
6705
6706         u8         reserved_at_20[0x10];
6707         u8         op_mod[0x10];
6708
6709         u8         embedded_cpu_function[0x1];
6710         u8         reserved_at_41[0xf];
6711         u8         function_id[0x10];
6712
6713         u8         reserved_at_60[0x20];
6714 };
6715
6716 struct mlx5_ifc_drain_dct_out_bits {
6717         u8         status[0x8];
6718         u8         reserved_at_8[0x18];
6719
6720         u8         syndrome[0x20];
6721
6722         u8         reserved_at_40[0x40];
6723 };
6724
6725 struct mlx5_ifc_drain_dct_in_bits {
6726         u8         opcode[0x10];
6727         u8         uid[0x10];
6728
6729         u8         reserved_at_20[0x10];
6730         u8         op_mod[0x10];
6731
6732         u8         reserved_at_40[0x8];
6733         u8         dctn[0x18];
6734
6735         u8         reserved_at_60[0x20];
6736 };
6737
6738 struct mlx5_ifc_disable_hca_out_bits {
6739         u8         status[0x8];
6740         u8         reserved_at_8[0x18];
6741
6742         u8         syndrome[0x20];
6743
6744         u8         reserved_at_40[0x20];
6745 };
6746
6747 struct mlx5_ifc_disable_hca_in_bits {
6748         u8         opcode[0x10];
6749         u8         reserved_at_10[0x10];
6750
6751         u8         reserved_at_20[0x10];
6752         u8         op_mod[0x10];
6753
6754         u8         embedded_cpu_function[0x1];
6755         u8         reserved_at_41[0xf];
6756         u8         function_id[0x10];
6757
6758         u8         reserved_at_60[0x20];
6759 };
6760
6761 struct mlx5_ifc_detach_from_mcg_out_bits {
6762         u8         status[0x8];
6763         u8         reserved_at_8[0x18];
6764
6765         u8         syndrome[0x20];
6766
6767         u8         reserved_at_40[0x40];
6768 };
6769
6770 struct mlx5_ifc_detach_from_mcg_in_bits {
6771         u8         opcode[0x10];
6772         u8         uid[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0x8];
6778         u8         qpn[0x18];
6779
6780         u8         reserved_at_60[0x20];
6781
6782         u8         multicast_gid[16][0x8];
6783 };
6784
6785 struct mlx5_ifc_destroy_xrq_out_bits {
6786         u8         status[0x8];
6787         u8         reserved_at_8[0x18];
6788
6789         u8         syndrome[0x20];
6790
6791         u8         reserved_at_40[0x40];
6792 };
6793
6794 struct mlx5_ifc_destroy_xrq_in_bits {
6795         u8         opcode[0x10];
6796         u8         uid[0x10];
6797
6798         u8         reserved_at_20[0x10];
6799         u8         op_mod[0x10];
6800
6801         u8         reserved_at_40[0x8];
6802         u8         xrqn[0x18];
6803
6804         u8         reserved_at_60[0x20];
6805 };
6806
6807 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6808         u8         status[0x8];
6809         u8         reserved_at_8[0x18];
6810
6811         u8         syndrome[0x20];
6812
6813         u8         reserved_at_40[0x40];
6814 };
6815
6816 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6817         u8         opcode[0x10];
6818         u8         uid[0x10];
6819
6820         u8         reserved_at_20[0x10];
6821         u8         op_mod[0x10];
6822
6823         u8         reserved_at_40[0x8];
6824         u8         xrc_srqn[0x18];
6825
6826         u8         reserved_at_60[0x20];
6827 };
6828
6829 struct mlx5_ifc_destroy_tis_out_bits {
6830         u8         status[0x8];
6831         u8         reserved_at_8[0x18];
6832
6833         u8         syndrome[0x20];
6834
6835         u8         reserved_at_40[0x40];
6836 };
6837
6838 struct mlx5_ifc_destroy_tis_in_bits {
6839         u8         opcode[0x10];
6840         u8         uid[0x10];
6841
6842         u8         reserved_at_20[0x10];
6843         u8         op_mod[0x10];
6844
6845         u8         reserved_at_40[0x8];
6846         u8         tisn[0x18];
6847
6848         u8         reserved_at_60[0x20];
6849 };
6850
6851 struct mlx5_ifc_destroy_tir_out_bits {
6852         u8         status[0x8];
6853         u8         reserved_at_8[0x18];
6854
6855         u8         syndrome[0x20];
6856
6857         u8         reserved_at_40[0x40];
6858 };
6859
6860 struct mlx5_ifc_destroy_tir_in_bits {
6861         u8         opcode[0x10];
6862         u8         uid[0x10];
6863
6864         u8         reserved_at_20[0x10];
6865         u8         op_mod[0x10];
6866
6867         u8         reserved_at_40[0x8];
6868         u8         tirn[0x18];
6869
6870         u8         reserved_at_60[0x20];
6871 };
6872
6873 struct mlx5_ifc_destroy_srq_out_bits {
6874         u8         status[0x8];
6875         u8         reserved_at_8[0x18];
6876
6877         u8         syndrome[0x20];
6878
6879         u8         reserved_at_40[0x40];
6880 };
6881
6882 struct mlx5_ifc_destroy_srq_in_bits {
6883         u8         opcode[0x10];
6884         u8         uid[0x10];
6885
6886         u8         reserved_at_20[0x10];
6887         u8         op_mod[0x10];
6888
6889         u8         reserved_at_40[0x8];
6890         u8         srqn[0x18];
6891
6892         u8         reserved_at_60[0x20];
6893 };
6894
6895 struct mlx5_ifc_destroy_sq_out_bits {
6896         u8         status[0x8];
6897         u8         reserved_at_8[0x18];
6898
6899         u8         syndrome[0x20];
6900
6901         u8         reserved_at_40[0x40];
6902 };
6903
6904 struct mlx5_ifc_destroy_sq_in_bits {
6905         u8         opcode[0x10];
6906         u8         uid[0x10];
6907
6908         u8         reserved_at_20[0x10];
6909         u8         op_mod[0x10];
6910
6911         u8         reserved_at_40[0x8];
6912         u8         sqn[0x18];
6913
6914         u8         reserved_at_60[0x20];
6915 };
6916
6917 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6918         u8         status[0x8];
6919         u8         reserved_at_8[0x18];
6920
6921         u8         syndrome[0x20];
6922
6923         u8         reserved_at_40[0x1c0];
6924 };
6925
6926 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6927         u8         opcode[0x10];
6928         u8         reserved_at_10[0x10];
6929
6930         u8         reserved_at_20[0x10];
6931         u8         op_mod[0x10];
6932
6933         u8         scheduling_hierarchy[0x8];
6934         u8         reserved_at_48[0x18];
6935
6936         u8         scheduling_element_id[0x20];
6937
6938         u8         reserved_at_80[0x180];
6939 };
6940
6941 struct mlx5_ifc_destroy_rqt_out_bits {
6942         u8         status[0x8];
6943         u8         reserved_at_8[0x18];
6944
6945         u8         syndrome[0x20];
6946
6947         u8         reserved_at_40[0x40];
6948 };
6949
6950 struct mlx5_ifc_destroy_rqt_in_bits {
6951         u8         opcode[0x10];
6952         u8         uid[0x10];
6953
6954         u8         reserved_at_20[0x10];
6955         u8         op_mod[0x10];
6956
6957         u8         reserved_at_40[0x8];
6958         u8         rqtn[0x18];
6959
6960         u8         reserved_at_60[0x20];
6961 };
6962
6963 struct mlx5_ifc_destroy_rq_out_bits {
6964         u8         status[0x8];
6965         u8         reserved_at_8[0x18];
6966
6967         u8         syndrome[0x20];
6968
6969         u8         reserved_at_40[0x40];
6970 };
6971
6972 struct mlx5_ifc_destroy_rq_in_bits {
6973         u8         opcode[0x10];
6974         u8         uid[0x10];
6975
6976         u8         reserved_at_20[0x10];
6977         u8         op_mod[0x10];
6978
6979         u8         reserved_at_40[0x8];
6980         u8         rqn[0x18];
6981
6982         u8         reserved_at_60[0x20];
6983 };
6984
6985 struct mlx5_ifc_set_delay_drop_params_in_bits {
6986         u8         opcode[0x10];
6987         u8         reserved_at_10[0x10];
6988
6989         u8         reserved_at_20[0x10];
6990         u8         op_mod[0x10];
6991
6992         u8         reserved_at_40[0x20];
6993
6994         u8         reserved_at_60[0x10];
6995         u8         delay_drop_timeout[0x10];
6996 };
6997
6998 struct mlx5_ifc_set_delay_drop_params_out_bits {
6999         u8         status[0x8];
7000         u8         reserved_at_8[0x18];
7001
7002         u8         syndrome[0x20];
7003
7004         u8         reserved_at_40[0x40];
7005 };
7006
7007 struct mlx5_ifc_destroy_rmp_out_bits {
7008         u8         status[0x8];
7009         u8         reserved_at_8[0x18];
7010
7011         u8         syndrome[0x20];
7012
7013         u8         reserved_at_40[0x40];
7014 };
7015
7016 struct mlx5_ifc_destroy_rmp_in_bits {
7017         u8         opcode[0x10];
7018         u8         uid[0x10];
7019
7020         u8         reserved_at_20[0x10];
7021         u8         op_mod[0x10];
7022
7023         u8         reserved_at_40[0x8];
7024         u8         rmpn[0x18];
7025
7026         u8         reserved_at_60[0x20];
7027 };
7028
7029 struct mlx5_ifc_destroy_qp_out_bits {
7030         u8         status[0x8];
7031         u8         reserved_at_8[0x18];
7032
7033         u8         syndrome[0x20];
7034
7035         u8         reserved_at_40[0x40];
7036 };
7037
7038 struct mlx5_ifc_destroy_qp_in_bits {
7039         u8         opcode[0x10];
7040         u8         uid[0x10];
7041
7042         u8         reserved_at_20[0x10];
7043         u8         op_mod[0x10];
7044
7045         u8         reserved_at_40[0x8];
7046         u8         qpn[0x18];
7047
7048         u8         reserved_at_60[0x20];
7049 };
7050
7051 struct mlx5_ifc_destroy_psv_out_bits {
7052         u8         status[0x8];
7053         u8         reserved_at_8[0x18];
7054
7055         u8         syndrome[0x20];
7056
7057         u8         reserved_at_40[0x40];
7058 };
7059
7060 struct mlx5_ifc_destroy_psv_in_bits {
7061         u8         opcode[0x10];
7062         u8         reserved_at_10[0x10];
7063
7064         u8         reserved_at_20[0x10];
7065         u8         op_mod[0x10];
7066
7067         u8         reserved_at_40[0x8];
7068         u8         psvn[0x18];
7069
7070         u8         reserved_at_60[0x20];
7071 };
7072
7073 struct mlx5_ifc_destroy_mkey_out_bits {
7074         u8         status[0x8];
7075         u8         reserved_at_8[0x18];
7076
7077         u8         syndrome[0x20];
7078
7079         u8         reserved_at_40[0x40];
7080 };
7081
7082 struct mlx5_ifc_destroy_mkey_in_bits {
7083         u8         opcode[0x10];
7084         u8         reserved_at_10[0x10];
7085
7086         u8         reserved_at_20[0x10];
7087         u8         op_mod[0x10];
7088
7089         u8         reserved_at_40[0x8];
7090         u8         mkey_index[0x18];
7091
7092         u8         reserved_at_60[0x20];
7093 };
7094
7095 struct mlx5_ifc_destroy_flow_table_out_bits {
7096         u8         status[0x8];
7097         u8         reserved_at_8[0x18];
7098
7099         u8         syndrome[0x20];
7100
7101         u8         reserved_at_40[0x40];
7102 };
7103
7104 struct mlx5_ifc_destroy_flow_table_in_bits {
7105         u8         opcode[0x10];
7106         u8         reserved_at_10[0x10];
7107
7108         u8         reserved_at_20[0x10];
7109         u8         op_mod[0x10];
7110
7111         u8         other_vport[0x1];
7112         u8         reserved_at_41[0xf];
7113         u8         vport_number[0x10];
7114
7115         u8         reserved_at_60[0x20];
7116
7117         u8         table_type[0x8];
7118         u8         reserved_at_88[0x18];
7119
7120         u8         reserved_at_a0[0x8];
7121         u8         table_id[0x18];
7122
7123         u8         reserved_at_c0[0x140];
7124 };
7125
7126 struct mlx5_ifc_destroy_flow_group_out_bits {
7127         u8         status[0x8];
7128         u8         reserved_at_8[0x18];
7129
7130         u8         syndrome[0x20];
7131
7132         u8         reserved_at_40[0x40];
7133 };
7134
7135 struct mlx5_ifc_destroy_flow_group_in_bits {
7136         u8         opcode[0x10];
7137         u8         reserved_at_10[0x10];
7138
7139         u8         reserved_at_20[0x10];
7140         u8         op_mod[0x10];
7141
7142         u8         other_vport[0x1];
7143         u8         reserved_at_41[0xf];
7144         u8         vport_number[0x10];
7145
7146         u8         reserved_at_60[0x20];
7147
7148         u8         table_type[0x8];
7149         u8         reserved_at_88[0x18];
7150
7151         u8         reserved_at_a0[0x8];
7152         u8         table_id[0x18];
7153
7154         u8         group_id[0x20];
7155
7156         u8         reserved_at_e0[0x120];
7157 };
7158
7159 struct mlx5_ifc_destroy_eq_out_bits {
7160         u8         status[0x8];
7161         u8         reserved_at_8[0x18];
7162
7163         u8         syndrome[0x20];
7164
7165         u8         reserved_at_40[0x40];
7166 };
7167
7168 struct mlx5_ifc_destroy_eq_in_bits {
7169         u8         opcode[0x10];
7170         u8         reserved_at_10[0x10];
7171
7172         u8         reserved_at_20[0x10];
7173         u8         op_mod[0x10];
7174
7175         u8         reserved_at_40[0x18];
7176         u8         eq_number[0x8];
7177
7178         u8         reserved_at_60[0x20];
7179 };
7180
7181 struct mlx5_ifc_destroy_dct_out_bits {
7182         u8         status[0x8];
7183         u8         reserved_at_8[0x18];
7184
7185         u8         syndrome[0x20];
7186
7187         u8         reserved_at_40[0x40];
7188 };
7189
7190 struct mlx5_ifc_destroy_dct_in_bits {
7191         u8         opcode[0x10];
7192         u8         uid[0x10];
7193
7194         u8         reserved_at_20[0x10];
7195         u8         op_mod[0x10];
7196
7197         u8         reserved_at_40[0x8];
7198         u8         dctn[0x18];
7199
7200         u8         reserved_at_60[0x20];
7201 };
7202
7203 struct mlx5_ifc_destroy_cq_out_bits {
7204         u8         status[0x8];
7205         u8         reserved_at_8[0x18];
7206
7207         u8         syndrome[0x20];
7208
7209         u8         reserved_at_40[0x40];
7210 };
7211
7212 struct mlx5_ifc_destroy_cq_in_bits {
7213         u8         opcode[0x10];
7214         u8         uid[0x10];
7215
7216         u8         reserved_at_20[0x10];
7217         u8         op_mod[0x10];
7218
7219         u8         reserved_at_40[0x8];
7220         u8         cqn[0x18];
7221
7222         u8         reserved_at_60[0x20];
7223 };
7224
7225 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7226         u8         status[0x8];
7227         u8         reserved_at_8[0x18];
7228
7229         u8         syndrome[0x20];
7230
7231         u8         reserved_at_40[0x40];
7232 };
7233
7234 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7235         u8         opcode[0x10];
7236         u8         reserved_at_10[0x10];
7237
7238         u8         reserved_at_20[0x10];
7239         u8         op_mod[0x10];
7240
7241         u8         reserved_at_40[0x20];
7242
7243         u8         reserved_at_60[0x10];
7244         u8         vxlan_udp_port[0x10];
7245 };
7246
7247 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7248         u8         status[0x8];
7249         u8         reserved_at_8[0x18];
7250
7251         u8         syndrome[0x20];
7252
7253         u8         reserved_at_40[0x40];
7254 };
7255
7256 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7257         u8         opcode[0x10];
7258         u8         reserved_at_10[0x10];
7259
7260         u8         reserved_at_20[0x10];
7261         u8         op_mod[0x10];
7262
7263         u8         reserved_at_40[0x60];
7264
7265         u8         reserved_at_a0[0x8];
7266         u8         table_index[0x18];
7267
7268         u8         reserved_at_c0[0x140];
7269 };
7270
7271 struct mlx5_ifc_delete_fte_out_bits {
7272         u8         status[0x8];
7273         u8         reserved_at_8[0x18];
7274
7275         u8         syndrome[0x20];
7276
7277         u8         reserved_at_40[0x40];
7278 };
7279
7280 struct mlx5_ifc_delete_fte_in_bits {
7281         u8         opcode[0x10];
7282         u8         reserved_at_10[0x10];
7283
7284         u8         reserved_at_20[0x10];
7285         u8         op_mod[0x10];
7286
7287         u8         other_vport[0x1];
7288         u8         reserved_at_41[0xf];
7289         u8         vport_number[0x10];
7290
7291         u8         reserved_at_60[0x20];
7292
7293         u8         table_type[0x8];
7294         u8         reserved_at_88[0x18];
7295
7296         u8         reserved_at_a0[0x8];
7297         u8         table_id[0x18];
7298
7299         u8         reserved_at_c0[0x40];
7300
7301         u8         flow_index[0x20];
7302
7303         u8         reserved_at_120[0xe0];
7304 };
7305
7306 struct mlx5_ifc_dealloc_xrcd_out_bits {
7307         u8         status[0x8];
7308         u8         reserved_at_8[0x18];
7309
7310         u8         syndrome[0x20];
7311
7312         u8         reserved_at_40[0x40];
7313 };
7314
7315 struct mlx5_ifc_dealloc_xrcd_in_bits {
7316         u8         opcode[0x10];
7317         u8         uid[0x10];
7318
7319         u8         reserved_at_20[0x10];
7320         u8         op_mod[0x10];
7321
7322         u8         reserved_at_40[0x8];
7323         u8         xrcd[0x18];
7324
7325         u8         reserved_at_60[0x20];
7326 };
7327
7328 struct mlx5_ifc_dealloc_uar_out_bits {
7329         u8         status[0x8];
7330         u8         reserved_at_8[0x18];
7331
7332         u8         syndrome[0x20];
7333
7334         u8         reserved_at_40[0x40];
7335 };
7336
7337 struct mlx5_ifc_dealloc_uar_in_bits {
7338         u8         opcode[0x10];
7339         u8         reserved_at_10[0x10];
7340
7341         u8         reserved_at_20[0x10];
7342         u8         op_mod[0x10];
7343
7344         u8         reserved_at_40[0x8];
7345         u8         uar[0x18];
7346
7347         u8         reserved_at_60[0x20];
7348 };
7349
7350 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7351         u8         status[0x8];
7352         u8         reserved_at_8[0x18];
7353
7354         u8         syndrome[0x20];
7355
7356         u8         reserved_at_40[0x40];
7357 };
7358
7359 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7360         u8         opcode[0x10];
7361         u8         uid[0x10];
7362
7363         u8         reserved_at_20[0x10];
7364         u8         op_mod[0x10];
7365
7366         u8         reserved_at_40[0x8];
7367         u8         transport_domain[0x18];
7368
7369         u8         reserved_at_60[0x20];
7370 };
7371
7372 struct mlx5_ifc_dealloc_q_counter_out_bits {
7373         u8         status[0x8];
7374         u8         reserved_at_8[0x18];
7375
7376         u8         syndrome[0x20];
7377
7378         u8         reserved_at_40[0x40];
7379 };
7380
7381 struct mlx5_ifc_dealloc_q_counter_in_bits {
7382         u8         opcode[0x10];
7383         u8         reserved_at_10[0x10];
7384
7385         u8         reserved_at_20[0x10];
7386         u8         op_mod[0x10];
7387
7388         u8         reserved_at_40[0x18];
7389         u8         counter_set_id[0x8];
7390
7391         u8         reserved_at_60[0x20];
7392 };
7393
7394 struct mlx5_ifc_dealloc_pd_out_bits {
7395         u8         status[0x8];
7396         u8         reserved_at_8[0x18];
7397
7398         u8         syndrome[0x20];
7399
7400         u8         reserved_at_40[0x40];
7401 };
7402
7403 struct mlx5_ifc_dealloc_pd_in_bits {
7404         u8         opcode[0x10];
7405         u8         uid[0x10];
7406
7407         u8         reserved_at_20[0x10];
7408         u8         op_mod[0x10];
7409
7410         u8         reserved_at_40[0x8];
7411         u8         pd[0x18];
7412
7413         u8         reserved_at_60[0x20];
7414 };
7415
7416 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7417         u8         status[0x8];
7418         u8         reserved_at_8[0x18];
7419
7420         u8         syndrome[0x20];
7421
7422         u8         reserved_at_40[0x40];
7423 };
7424
7425 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7426         u8         opcode[0x10];
7427         u8         reserved_at_10[0x10];
7428
7429         u8         reserved_at_20[0x10];
7430         u8         op_mod[0x10];
7431
7432         u8         flow_counter_id[0x20];
7433
7434         u8         reserved_at_60[0x20];
7435 };
7436
7437 struct mlx5_ifc_create_xrq_out_bits {
7438         u8         status[0x8];
7439         u8         reserved_at_8[0x18];
7440
7441         u8         syndrome[0x20];
7442
7443         u8         reserved_at_40[0x8];
7444         u8         xrqn[0x18];
7445
7446         u8         reserved_at_60[0x20];
7447 };
7448
7449 struct mlx5_ifc_create_xrq_in_bits {
7450         u8         opcode[0x10];
7451         u8         uid[0x10];
7452
7453         u8         reserved_at_20[0x10];
7454         u8         op_mod[0x10];
7455
7456         u8         reserved_at_40[0x40];
7457
7458         struct mlx5_ifc_xrqc_bits xrq_context;
7459 };
7460
7461 struct mlx5_ifc_create_xrc_srq_out_bits {
7462         u8         status[0x8];
7463         u8         reserved_at_8[0x18];
7464
7465         u8         syndrome[0x20];
7466
7467         u8         reserved_at_40[0x8];
7468         u8         xrc_srqn[0x18];
7469
7470         u8         reserved_at_60[0x20];
7471 };
7472
7473 struct mlx5_ifc_create_xrc_srq_in_bits {
7474         u8         opcode[0x10];
7475         u8         uid[0x10];
7476
7477         u8         reserved_at_20[0x10];
7478         u8         op_mod[0x10];
7479
7480         u8         reserved_at_40[0x40];
7481
7482         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7483
7484         u8         reserved_at_280[0x60];
7485
7486         u8         xrc_srq_umem_valid[0x1];
7487         u8         reserved_at_2e1[0x1f];
7488
7489         u8         reserved_at_300[0x580];
7490
7491         u8         pas[][0x40];
7492 };
7493
7494 struct mlx5_ifc_create_tis_out_bits {
7495         u8         status[0x8];
7496         u8         reserved_at_8[0x18];
7497
7498         u8         syndrome[0x20];
7499
7500         u8         reserved_at_40[0x8];
7501         u8         tisn[0x18];
7502
7503         u8         reserved_at_60[0x20];
7504 };
7505
7506 struct mlx5_ifc_create_tis_in_bits {
7507         u8         opcode[0x10];
7508         u8         uid[0x10];
7509
7510         u8         reserved_at_20[0x10];
7511         u8         op_mod[0x10];
7512
7513         u8         reserved_at_40[0xc0];
7514
7515         struct mlx5_ifc_tisc_bits ctx;
7516 };
7517
7518 struct mlx5_ifc_create_tir_out_bits {
7519         u8         status[0x8];
7520         u8         icm_address_63_40[0x18];
7521
7522         u8         syndrome[0x20];
7523
7524         u8         icm_address_39_32[0x8];
7525         u8         tirn[0x18];
7526
7527         u8         icm_address_31_0[0x20];
7528 };
7529
7530 struct mlx5_ifc_create_tir_in_bits {
7531         u8         opcode[0x10];
7532         u8         uid[0x10];
7533
7534         u8         reserved_at_20[0x10];
7535         u8         op_mod[0x10];
7536
7537         u8         reserved_at_40[0xc0];
7538
7539         struct mlx5_ifc_tirc_bits ctx;
7540 };
7541
7542 struct mlx5_ifc_create_srq_out_bits {
7543         u8         status[0x8];
7544         u8         reserved_at_8[0x18];
7545
7546         u8         syndrome[0x20];
7547
7548         u8         reserved_at_40[0x8];
7549         u8         srqn[0x18];
7550
7551         u8         reserved_at_60[0x20];
7552 };
7553
7554 struct mlx5_ifc_create_srq_in_bits {
7555         u8         opcode[0x10];
7556         u8         uid[0x10];
7557
7558         u8         reserved_at_20[0x10];
7559         u8         op_mod[0x10];
7560
7561         u8         reserved_at_40[0x40];
7562
7563         struct mlx5_ifc_srqc_bits srq_context_entry;
7564
7565         u8         reserved_at_280[0x600];
7566
7567         u8         pas[][0x40];
7568 };
7569
7570 struct mlx5_ifc_create_sq_out_bits {
7571         u8         status[0x8];
7572         u8         reserved_at_8[0x18];
7573
7574         u8         syndrome[0x20];
7575
7576         u8         reserved_at_40[0x8];
7577         u8         sqn[0x18];
7578
7579         u8         reserved_at_60[0x20];
7580 };
7581
7582 struct mlx5_ifc_create_sq_in_bits {
7583         u8         opcode[0x10];
7584         u8         uid[0x10];
7585
7586         u8         reserved_at_20[0x10];
7587         u8         op_mod[0x10];
7588
7589         u8         reserved_at_40[0xc0];
7590
7591         struct mlx5_ifc_sqc_bits ctx;
7592 };
7593
7594 struct mlx5_ifc_create_scheduling_element_out_bits {
7595         u8         status[0x8];
7596         u8         reserved_at_8[0x18];
7597
7598         u8         syndrome[0x20];
7599
7600         u8         reserved_at_40[0x40];
7601
7602         u8         scheduling_element_id[0x20];
7603
7604         u8         reserved_at_a0[0x160];
7605 };
7606
7607 struct mlx5_ifc_create_scheduling_element_in_bits {
7608         u8         opcode[0x10];
7609         u8         reserved_at_10[0x10];
7610
7611         u8         reserved_at_20[0x10];
7612         u8         op_mod[0x10];
7613
7614         u8         scheduling_hierarchy[0x8];
7615         u8         reserved_at_48[0x18];
7616
7617         u8         reserved_at_60[0xa0];
7618
7619         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7620
7621         u8         reserved_at_300[0x100];
7622 };
7623
7624 struct mlx5_ifc_create_rqt_out_bits {
7625         u8         status[0x8];
7626         u8         reserved_at_8[0x18];
7627
7628         u8         syndrome[0x20];
7629
7630         u8         reserved_at_40[0x8];
7631         u8         rqtn[0x18];
7632
7633         u8         reserved_at_60[0x20];
7634 };
7635
7636 struct mlx5_ifc_create_rqt_in_bits {
7637         u8         opcode[0x10];
7638         u8         uid[0x10];
7639
7640         u8         reserved_at_20[0x10];
7641         u8         op_mod[0x10];
7642
7643         u8         reserved_at_40[0xc0];
7644
7645         struct mlx5_ifc_rqtc_bits rqt_context;
7646 };
7647
7648 struct mlx5_ifc_create_rq_out_bits {
7649         u8         status[0x8];
7650         u8         reserved_at_8[0x18];
7651
7652         u8         syndrome[0x20];
7653
7654         u8         reserved_at_40[0x8];
7655         u8         rqn[0x18];
7656
7657         u8         reserved_at_60[0x20];
7658 };
7659
7660 struct mlx5_ifc_create_rq_in_bits {
7661         u8         opcode[0x10];
7662         u8         uid[0x10];
7663
7664         u8         reserved_at_20[0x10];
7665         u8         op_mod[0x10];
7666
7667         u8         reserved_at_40[0xc0];
7668
7669         struct mlx5_ifc_rqc_bits ctx;
7670 };
7671
7672 struct mlx5_ifc_create_rmp_out_bits {
7673         u8         status[0x8];
7674         u8         reserved_at_8[0x18];
7675
7676         u8         syndrome[0x20];
7677
7678         u8         reserved_at_40[0x8];
7679         u8         rmpn[0x18];
7680
7681         u8         reserved_at_60[0x20];
7682 };
7683
7684 struct mlx5_ifc_create_rmp_in_bits {
7685         u8         opcode[0x10];
7686         u8         uid[0x10];
7687
7688         u8         reserved_at_20[0x10];
7689         u8         op_mod[0x10];
7690
7691         u8         reserved_at_40[0xc0];
7692
7693         struct mlx5_ifc_rmpc_bits ctx;
7694 };
7695
7696 struct mlx5_ifc_create_qp_out_bits {
7697         u8         status[0x8];
7698         u8         reserved_at_8[0x18];
7699
7700         u8         syndrome[0x20];
7701
7702         u8         reserved_at_40[0x8];
7703         u8         qpn[0x18];
7704
7705         u8         ece[0x20];
7706 };
7707
7708 struct mlx5_ifc_create_qp_in_bits {
7709         u8         opcode[0x10];
7710         u8         uid[0x10];
7711
7712         u8         reserved_at_20[0x10];
7713         u8         op_mod[0x10];
7714
7715         u8         reserved_at_40[0x40];
7716
7717         u8         opt_param_mask[0x20];
7718
7719         u8         ece[0x20];
7720
7721         struct mlx5_ifc_qpc_bits qpc;
7722
7723         u8         reserved_at_800[0x60];
7724
7725         u8         wq_umem_valid[0x1];
7726         u8         reserved_at_861[0x1f];
7727
7728         u8         pas[][0x40];
7729 };
7730
7731 struct mlx5_ifc_create_psv_out_bits {
7732         u8         status[0x8];
7733         u8         reserved_at_8[0x18];
7734
7735         u8         syndrome[0x20];
7736
7737         u8         reserved_at_40[0x40];
7738
7739         u8         reserved_at_80[0x8];
7740         u8         psv0_index[0x18];
7741
7742         u8         reserved_at_a0[0x8];
7743         u8         psv1_index[0x18];
7744
7745         u8         reserved_at_c0[0x8];
7746         u8         psv2_index[0x18];
7747
7748         u8         reserved_at_e0[0x8];
7749         u8         psv3_index[0x18];
7750 };
7751
7752 struct mlx5_ifc_create_psv_in_bits {
7753         u8         opcode[0x10];
7754         u8         reserved_at_10[0x10];
7755
7756         u8         reserved_at_20[0x10];
7757         u8         op_mod[0x10];
7758
7759         u8         num_psv[0x4];
7760         u8         reserved_at_44[0x4];
7761         u8         pd[0x18];
7762
7763         u8         reserved_at_60[0x20];
7764 };
7765
7766 struct mlx5_ifc_create_mkey_out_bits {
7767         u8         status[0x8];
7768         u8         reserved_at_8[0x18];
7769
7770         u8         syndrome[0x20];
7771
7772         u8         reserved_at_40[0x8];
7773         u8         mkey_index[0x18];
7774
7775         u8         reserved_at_60[0x20];
7776 };
7777
7778 struct mlx5_ifc_create_mkey_in_bits {
7779         u8         opcode[0x10];
7780         u8         reserved_at_10[0x10];
7781
7782         u8         reserved_at_20[0x10];
7783         u8         op_mod[0x10];
7784
7785         u8         reserved_at_40[0x20];
7786
7787         u8         pg_access[0x1];
7788         u8         mkey_umem_valid[0x1];
7789         u8         reserved_at_62[0x1e];
7790
7791         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7792
7793         u8         reserved_at_280[0x80];
7794
7795         u8         translations_octword_actual_size[0x20];
7796
7797         u8         reserved_at_320[0x560];
7798
7799         u8         klm_pas_mtt[][0x20];
7800 };
7801
7802 enum {
7803         MLX5_FLOW_TABLE_TYPE_NIC_RX             = 0x0,
7804         MLX5_FLOW_TABLE_TYPE_NIC_TX             = 0x1,
7805         MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL     = 0x2,
7806         MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL    = 0x3,
7807         MLX5_FLOW_TABLE_TYPE_FDB                = 0X4,
7808         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX         = 0X5,
7809         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX         = 0X6,
7810 };
7811
7812 struct mlx5_ifc_create_flow_table_out_bits {
7813         u8         status[0x8];
7814         u8         icm_address_63_40[0x18];
7815
7816         u8         syndrome[0x20];
7817
7818         u8         icm_address_39_32[0x8];
7819         u8         table_id[0x18];
7820
7821         u8         icm_address_31_0[0x20];
7822 };
7823
7824 struct mlx5_ifc_create_flow_table_in_bits {
7825         u8         opcode[0x10];
7826         u8         reserved_at_10[0x10];
7827
7828         u8         reserved_at_20[0x10];
7829         u8         op_mod[0x10];
7830
7831         u8         other_vport[0x1];
7832         u8         reserved_at_41[0xf];
7833         u8         vport_number[0x10];
7834
7835         u8         reserved_at_60[0x20];
7836
7837         u8         table_type[0x8];
7838         u8         reserved_at_88[0x18];
7839
7840         u8         reserved_at_a0[0x20];
7841
7842         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7843 };
7844
7845 struct mlx5_ifc_create_flow_group_out_bits {
7846         u8         status[0x8];
7847         u8         reserved_at_8[0x18];
7848
7849         u8         syndrome[0x20];
7850
7851         u8         reserved_at_40[0x8];
7852         u8         group_id[0x18];
7853
7854         u8         reserved_at_60[0x20];
7855 };
7856
7857 enum {
7858         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7859         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7860         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7861         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7862 };
7863
7864 struct mlx5_ifc_create_flow_group_in_bits {
7865         u8         opcode[0x10];
7866         u8         reserved_at_10[0x10];
7867
7868         u8         reserved_at_20[0x10];
7869         u8         op_mod[0x10];
7870
7871         u8         other_vport[0x1];
7872         u8         reserved_at_41[0xf];
7873         u8         vport_number[0x10];
7874
7875         u8         reserved_at_60[0x20];
7876
7877         u8         table_type[0x8];
7878         u8         reserved_at_88[0x18];
7879
7880         u8         reserved_at_a0[0x8];
7881         u8         table_id[0x18];
7882
7883         u8         source_eswitch_owner_vhca_id_valid[0x1];
7884
7885         u8         reserved_at_c1[0x1f];
7886
7887         u8         start_flow_index[0x20];
7888
7889         u8         reserved_at_100[0x20];
7890
7891         u8         end_flow_index[0x20];
7892
7893         u8         reserved_at_140[0xa0];
7894
7895         u8         reserved_at_1e0[0x18];
7896         u8         match_criteria_enable[0x8];
7897
7898         struct mlx5_ifc_fte_match_param_bits match_criteria;
7899
7900         u8         reserved_at_1200[0xe00];
7901 };
7902
7903 struct mlx5_ifc_create_eq_out_bits {
7904         u8         status[0x8];
7905         u8         reserved_at_8[0x18];
7906
7907         u8         syndrome[0x20];
7908
7909         u8         reserved_at_40[0x18];
7910         u8         eq_number[0x8];
7911
7912         u8         reserved_at_60[0x20];
7913 };
7914
7915 struct mlx5_ifc_create_eq_in_bits {
7916         u8         opcode[0x10];
7917         u8         uid[0x10];
7918
7919         u8         reserved_at_20[0x10];
7920         u8         op_mod[0x10];
7921
7922         u8         reserved_at_40[0x40];
7923
7924         struct mlx5_ifc_eqc_bits eq_context_entry;
7925
7926         u8         reserved_at_280[0x40];
7927
7928         u8         event_bitmask[4][0x40];
7929
7930         u8         reserved_at_3c0[0x4c0];
7931
7932         u8         pas[][0x40];
7933 };
7934
7935 struct mlx5_ifc_create_dct_out_bits {
7936         u8         status[0x8];
7937         u8         reserved_at_8[0x18];
7938
7939         u8         syndrome[0x20];
7940
7941         u8         reserved_at_40[0x8];
7942         u8         dctn[0x18];
7943
7944         u8         ece[0x20];
7945 };
7946
7947 struct mlx5_ifc_create_dct_in_bits {
7948         u8         opcode[0x10];
7949         u8         uid[0x10];
7950
7951         u8         reserved_at_20[0x10];
7952         u8         op_mod[0x10];
7953
7954         u8         reserved_at_40[0x40];
7955
7956         struct mlx5_ifc_dctc_bits dct_context_entry;
7957
7958         u8         reserved_at_280[0x180];
7959 };
7960
7961 struct mlx5_ifc_create_cq_out_bits {
7962         u8         status[0x8];
7963         u8         reserved_at_8[0x18];
7964
7965         u8         syndrome[0x20];
7966
7967         u8         reserved_at_40[0x8];
7968         u8         cqn[0x18];
7969
7970         u8         reserved_at_60[0x20];
7971 };
7972
7973 struct mlx5_ifc_create_cq_in_bits {
7974         u8         opcode[0x10];
7975         u8         uid[0x10];
7976
7977         u8         reserved_at_20[0x10];
7978         u8         op_mod[0x10];
7979
7980         u8         reserved_at_40[0x40];
7981
7982         struct mlx5_ifc_cqc_bits cq_context;
7983
7984         u8         reserved_at_280[0x60];
7985
7986         u8         cq_umem_valid[0x1];
7987         u8         reserved_at_2e1[0x59f];
7988
7989         u8         pas[][0x40];
7990 };
7991
7992 struct mlx5_ifc_config_int_moderation_out_bits {
7993         u8         status[0x8];
7994         u8         reserved_at_8[0x18];
7995
7996         u8         syndrome[0x20];
7997
7998         u8         reserved_at_40[0x4];
7999         u8         min_delay[0xc];
8000         u8         int_vector[0x10];
8001
8002         u8         reserved_at_60[0x20];
8003 };
8004
8005 enum {
8006         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8007         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8008 };
8009
8010 struct mlx5_ifc_config_int_moderation_in_bits {
8011         u8         opcode[0x10];
8012         u8         reserved_at_10[0x10];
8013
8014         u8         reserved_at_20[0x10];
8015         u8         op_mod[0x10];
8016
8017         u8         reserved_at_40[0x4];
8018         u8         min_delay[0xc];
8019         u8         int_vector[0x10];
8020
8021         u8         reserved_at_60[0x20];
8022 };
8023
8024 struct mlx5_ifc_attach_to_mcg_out_bits {
8025         u8         status[0x8];
8026         u8         reserved_at_8[0x18];
8027
8028         u8         syndrome[0x20];
8029
8030         u8         reserved_at_40[0x40];
8031 };
8032
8033 struct mlx5_ifc_attach_to_mcg_in_bits {
8034         u8         opcode[0x10];
8035         u8         uid[0x10];
8036
8037         u8         reserved_at_20[0x10];
8038         u8         op_mod[0x10];
8039
8040         u8         reserved_at_40[0x8];
8041         u8         qpn[0x18];
8042
8043         u8         reserved_at_60[0x20];
8044
8045         u8         multicast_gid[16][0x8];
8046 };
8047
8048 struct mlx5_ifc_arm_xrq_out_bits {
8049         u8         status[0x8];
8050         u8         reserved_at_8[0x18];
8051
8052         u8         syndrome[0x20];
8053
8054         u8         reserved_at_40[0x40];
8055 };
8056
8057 struct mlx5_ifc_arm_xrq_in_bits {
8058         u8         opcode[0x10];
8059         u8         reserved_at_10[0x10];
8060
8061         u8         reserved_at_20[0x10];
8062         u8         op_mod[0x10];
8063
8064         u8         reserved_at_40[0x8];
8065         u8         xrqn[0x18];
8066
8067         u8         reserved_at_60[0x10];
8068         u8         lwm[0x10];
8069 };
8070
8071 struct mlx5_ifc_arm_xrc_srq_out_bits {
8072         u8         status[0x8];
8073         u8         reserved_at_8[0x18];
8074
8075         u8         syndrome[0x20];
8076
8077         u8         reserved_at_40[0x40];
8078 };
8079
8080 enum {
8081         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8082 };
8083
8084 struct mlx5_ifc_arm_xrc_srq_in_bits {
8085         u8         opcode[0x10];
8086         u8         uid[0x10];
8087
8088         u8         reserved_at_20[0x10];
8089         u8         op_mod[0x10];
8090
8091         u8         reserved_at_40[0x8];
8092         u8         xrc_srqn[0x18];
8093
8094         u8         reserved_at_60[0x10];
8095         u8         lwm[0x10];
8096 };
8097
8098 struct mlx5_ifc_arm_rq_out_bits {
8099         u8         status[0x8];
8100         u8         reserved_at_8[0x18];
8101
8102         u8         syndrome[0x20];
8103
8104         u8         reserved_at_40[0x40];
8105 };
8106
8107 enum {
8108         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8109         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8110 };
8111
8112 struct mlx5_ifc_arm_rq_in_bits {
8113         u8         opcode[0x10];
8114         u8         uid[0x10];
8115
8116         u8         reserved_at_20[0x10];
8117         u8         op_mod[0x10];
8118
8119         u8         reserved_at_40[0x8];
8120         u8         srq_number[0x18];
8121
8122         u8         reserved_at_60[0x10];
8123         u8         lwm[0x10];
8124 };
8125
8126 struct mlx5_ifc_arm_dct_out_bits {
8127         u8         status[0x8];
8128         u8         reserved_at_8[0x18];
8129
8130         u8         syndrome[0x20];
8131
8132         u8         reserved_at_40[0x40];
8133 };
8134
8135 struct mlx5_ifc_arm_dct_in_bits {
8136         u8         opcode[0x10];
8137         u8         reserved_at_10[0x10];
8138
8139         u8         reserved_at_20[0x10];
8140         u8         op_mod[0x10];
8141
8142         u8         reserved_at_40[0x8];
8143         u8         dct_number[0x18];
8144
8145         u8         reserved_at_60[0x20];
8146 };
8147
8148 struct mlx5_ifc_alloc_xrcd_out_bits {
8149         u8         status[0x8];
8150         u8         reserved_at_8[0x18];
8151
8152         u8         syndrome[0x20];
8153
8154         u8         reserved_at_40[0x8];
8155         u8         xrcd[0x18];
8156
8157         u8         reserved_at_60[0x20];
8158 };
8159
8160 struct mlx5_ifc_alloc_xrcd_in_bits {
8161         u8         opcode[0x10];
8162         u8         uid[0x10];
8163
8164         u8         reserved_at_20[0x10];
8165         u8         op_mod[0x10];
8166
8167         u8         reserved_at_40[0x40];
8168 };
8169
8170 struct mlx5_ifc_alloc_uar_out_bits {
8171         u8         status[0x8];
8172         u8         reserved_at_8[0x18];
8173
8174         u8         syndrome[0x20];
8175
8176         u8         reserved_at_40[0x8];
8177         u8         uar[0x18];
8178
8179         u8         reserved_at_60[0x20];
8180 };
8181
8182 struct mlx5_ifc_alloc_uar_in_bits {
8183         u8         opcode[0x10];
8184         u8         reserved_at_10[0x10];
8185
8186         u8         reserved_at_20[0x10];
8187         u8         op_mod[0x10];
8188
8189         u8         reserved_at_40[0x40];
8190 };
8191
8192 struct mlx5_ifc_alloc_transport_domain_out_bits {
8193         u8         status[0x8];
8194         u8         reserved_at_8[0x18];
8195
8196         u8         syndrome[0x20];
8197
8198         u8         reserved_at_40[0x8];
8199         u8         transport_domain[0x18];
8200
8201         u8         reserved_at_60[0x20];
8202 };
8203
8204 struct mlx5_ifc_alloc_transport_domain_in_bits {
8205         u8         opcode[0x10];
8206         u8         uid[0x10];
8207
8208         u8         reserved_at_20[0x10];
8209         u8         op_mod[0x10];
8210
8211         u8         reserved_at_40[0x40];
8212 };
8213
8214 struct mlx5_ifc_alloc_q_counter_out_bits {
8215         u8         status[0x8];
8216         u8         reserved_at_8[0x18];
8217
8218         u8         syndrome[0x20];
8219
8220         u8         reserved_at_40[0x18];
8221         u8         counter_set_id[0x8];
8222
8223         u8         reserved_at_60[0x20];
8224 };
8225
8226 struct mlx5_ifc_alloc_q_counter_in_bits {
8227         u8         opcode[0x10];
8228         u8         uid[0x10];
8229
8230         u8         reserved_at_20[0x10];
8231         u8         op_mod[0x10];
8232
8233         u8         reserved_at_40[0x40];
8234 };
8235
8236 struct mlx5_ifc_alloc_pd_out_bits {
8237         u8         status[0x8];
8238         u8         reserved_at_8[0x18];
8239
8240         u8         syndrome[0x20];
8241
8242         u8         reserved_at_40[0x8];
8243         u8         pd[0x18];
8244
8245         u8         reserved_at_60[0x20];
8246 };
8247
8248 struct mlx5_ifc_alloc_pd_in_bits {
8249         u8         opcode[0x10];
8250         u8         uid[0x10];
8251
8252         u8         reserved_at_20[0x10];
8253         u8         op_mod[0x10];
8254
8255         u8         reserved_at_40[0x40];
8256 };
8257
8258 struct mlx5_ifc_alloc_flow_counter_out_bits {
8259         u8         status[0x8];
8260         u8         reserved_at_8[0x18];
8261
8262         u8         syndrome[0x20];
8263
8264         u8         flow_counter_id[0x20];
8265
8266         u8         reserved_at_60[0x20];
8267 };
8268
8269 struct mlx5_ifc_alloc_flow_counter_in_bits {
8270         u8         opcode[0x10];
8271         u8         reserved_at_10[0x10];
8272
8273         u8         reserved_at_20[0x10];
8274         u8         op_mod[0x10];
8275
8276         u8         reserved_at_40[0x38];
8277         u8         flow_counter_bulk[0x8];
8278 };
8279
8280 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8281         u8         status[0x8];
8282         u8         reserved_at_8[0x18];
8283
8284         u8         syndrome[0x20];
8285
8286         u8         reserved_at_40[0x40];
8287 };
8288
8289 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8290         u8         opcode[0x10];
8291         u8         reserved_at_10[0x10];
8292
8293         u8         reserved_at_20[0x10];
8294         u8         op_mod[0x10];
8295
8296         u8         reserved_at_40[0x20];
8297
8298         u8         reserved_at_60[0x10];
8299         u8         vxlan_udp_port[0x10];
8300 };
8301
8302 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8303         u8         status[0x8];
8304         u8         reserved_at_8[0x18];
8305
8306         u8         syndrome[0x20];
8307
8308         u8         reserved_at_40[0x40];
8309 };
8310
8311 struct mlx5_ifc_set_pp_rate_limit_context_bits {
8312         u8         rate_limit[0x20];
8313
8314         u8         burst_upper_bound[0x20];
8315
8316         u8         reserved_at_40[0x10];
8317         u8         typical_packet_size[0x10];
8318
8319         u8         reserved_at_60[0x120];
8320 };
8321
8322 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8323         u8         opcode[0x10];
8324         u8         uid[0x10];
8325
8326         u8         reserved_at_20[0x10];
8327         u8         op_mod[0x10];
8328
8329         u8         reserved_at_40[0x10];
8330         u8         rate_limit_index[0x10];
8331
8332         u8         reserved_at_60[0x20];
8333
8334         struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
8335 };
8336
8337 struct mlx5_ifc_access_register_out_bits {
8338         u8         status[0x8];
8339         u8         reserved_at_8[0x18];
8340
8341         u8         syndrome[0x20];
8342
8343         u8         reserved_at_40[0x40];
8344
8345         u8         register_data[][0x20];
8346 };
8347
8348 enum {
8349         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
8350         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
8351 };
8352
8353 struct mlx5_ifc_access_register_in_bits {
8354         u8         opcode[0x10];
8355         u8         reserved_at_10[0x10];
8356
8357         u8         reserved_at_20[0x10];
8358         u8         op_mod[0x10];
8359
8360         u8         reserved_at_40[0x10];
8361         u8         register_id[0x10];
8362
8363         u8         argument[0x20];
8364
8365         u8         register_data[][0x20];
8366 };
8367
8368 struct mlx5_ifc_sltp_reg_bits {
8369         u8         status[0x4];
8370         u8         version[0x4];
8371         u8         local_port[0x8];
8372         u8         pnat[0x2];
8373         u8         reserved_at_12[0x2];
8374         u8         lane[0x4];
8375         u8         reserved_at_18[0x8];
8376
8377         u8         reserved_at_20[0x20];
8378
8379         u8         reserved_at_40[0x7];
8380         u8         polarity[0x1];
8381         u8         ob_tap0[0x8];
8382         u8         ob_tap1[0x8];
8383         u8         ob_tap2[0x8];
8384
8385         u8         reserved_at_60[0xc];
8386         u8         ob_preemp_mode[0x4];
8387         u8         ob_reg[0x8];
8388         u8         ob_bias[0x8];
8389
8390         u8         reserved_at_80[0x20];
8391 };
8392
8393 struct mlx5_ifc_slrg_reg_bits {
8394         u8         status[0x4];
8395         u8         version[0x4];
8396         u8         local_port[0x8];
8397         u8         pnat[0x2];
8398         u8         reserved_at_12[0x2];
8399         u8         lane[0x4];
8400         u8         reserved_at_18[0x8];
8401
8402         u8         time_to_link_up[0x10];
8403         u8         reserved_at_30[0xc];
8404         u8         grade_lane_speed[0x4];
8405
8406         u8         grade_version[0x8];
8407         u8         grade[0x18];
8408
8409         u8         reserved_at_60[0x4];
8410         u8         height_grade_type[0x4];
8411         u8         height_grade[0x18];
8412
8413         u8         height_dz[0x10];
8414         u8         height_dv[0x10];
8415
8416         u8         reserved_at_a0[0x10];
8417         u8         height_sigma[0x10];
8418
8419         u8         reserved_at_c0[0x20];
8420
8421         u8         reserved_at_e0[0x4];
8422         u8         phase_grade_type[0x4];
8423         u8         phase_grade[0x18];
8424
8425         u8         reserved_at_100[0x8];
8426         u8         phase_eo_pos[0x8];
8427         u8         reserved_at_110[0x8];
8428         u8         phase_eo_neg[0x8];
8429
8430         u8         ffe_set_tested[0x10];
8431         u8         test_errors_per_lane[0x10];
8432 };
8433
8434 struct mlx5_ifc_pvlc_reg_bits {
8435         u8         reserved_at_0[0x8];
8436         u8         local_port[0x8];
8437         u8         reserved_at_10[0x10];
8438
8439         u8         reserved_at_20[0x1c];
8440         u8         vl_hw_cap[0x4];
8441
8442         u8         reserved_at_40[0x1c];
8443         u8         vl_admin[0x4];
8444
8445         u8         reserved_at_60[0x1c];
8446         u8         vl_operational[0x4];
8447 };
8448
8449 struct mlx5_ifc_pude_reg_bits {
8450         u8         swid[0x8];
8451         u8         local_port[0x8];
8452         u8         reserved_at_10[0x4];
8453         u8         admin_status[0x4];
8454         u8         reserved_at_18[0x4];
8455         u8         oper_status[0x4];
8456
8457         u8         reserved_at_20[0x60];
8458 };
8459
8460 struct mlx5_ifc_ptys_reg_bits {
8461         u8         reserved_at_0[0x1];
8462         u8         an_disable_admin[0x1];
8463         u8         an_disable_cap[0x1];
8464         u8         reserved_at_3[0x5];
8465         u8         local_port[0x8];
8466         u8         reserved_at_10[0xd];
8467         u8         proto_mask[0x3];
8468
8469         u8         an_status[0x4];
8470         u8         reserved_at_24[0xc];
8471         u8         data_rate_oper[0x10];
8472
8473         u8         ext_eth_proto_capability[0x20];
8474
8475         u8         eth_proto_capability[0x20];
8476
8477         u8         ib_link_width_capability[0x10];
8478         u8         ib_proto_capability[0x10];
8479
8480         u8         ext_eth_proto_admin[0x20];
8481
8482         u8         eth_proto_admin[0x20];
8483
8484         u8         ib_link_width_admin[0x10];
8485         u8         ib_proto_admin[0x10];
8486
8487         u8         ext_eth_proto_oper[0x20];
8488
8489         u8         eth_proto_oper[0x20];
8490
8491         u8         ib_link_width_oper[0x10];
8492         u8         ib_proto_oper[0x10];
8493
8494         u8         reserved_at_160[0x1c];
8495         u8         connector_type[0x4];
8496
8497         u8         eth_proto_lp_advertise[0x20];
8498
8499         u8         reserved_at_1a0[0x60];
8500 };
8501
8502 struct mlx5_ifc_mlcr_reg_bits {
8503         u8         reserved_at_0[0x8];
8504         u8         local_port[0x8];
8505         u8         reserved_at_10[0x20];
8506
8507         u8         beacon_duration[0x10];
8508         u8         reserved_at_40[0x10];
8509
8510         u8         beacon_remain[0x10];
8511 };
8512
8513 struct mlx5_ifc_ptas_reg_bits {
8514         u8         reserved_at_0[0x20];
8515
8516         u8         algorithm_options[0x10];
8517         u8         reserved_at_30[0x4];
8518         u8         repetitions_mode[0x4];
8519         u8         num_of_repetitions[0x8];
8520
8521         u8         grade_version[0x8];
8522         u8         height_grade_type[0x4];
8523         u8         phase_grade_type[0x4];
8524         u8         height_grade_weight[0x8];
8525         u8         phase_grade_weight[0x8];
8526
8527         u8         gisim_measure_bits[0x10];
8528         u8         adaptive_tap_measure_bits[0x10];
8529
8530         u8         ber_bath_high_error_threshold[0x10];
8531         u8         ber_bath_mid_error_threshold[0x10];
8532
8533         u8         ber_bath_low_error_threshold[0x10];
8534         u8         one_ratio_high_threshold[0x10];
8535
8536         u8         one_ratio_high_mid_threshold[0x10];
8537         u8         one_ratio_low_mid_threshold[0x10];
8538
8539         u8         one_ratio_low_threshold[0x10];
8540         u8         ndeo_error_threshold[0x10];
8541
8542         u8         mixer_offset_step_size[0x10];
8543         u8         reserved_at_110[0x8];
8544         u8         mix90_phase_for_voltage_bath[0x8];
8545
8546         u8         mixer_offset_start[0x10];
8547         u8         mixer_offset_end[0x10];
8548
8549         u8         reserved_at_140[0x15];
8550         u8         ber_test_time[0xb];
8551 };
8552
8553 struct mlx5_ifc_pspa_reg_bits {
8554         u8         swid[0x8];
8555         u8         local_port[0x8];
8556         u8         sub_port[0x8];
8557         u8         reserved_at_18[0x8];
8558
8559         u8         reserved_at_20[0x20];
8560 };
8561
8562 struct mlx5_ifc_pqdr_reg_bits {
8563         u8         reserved_at_0[0x8];
8564         u8         local_port[0x8];
8565         u8         reserved_at_10[0x5];
8566         u8         prio[0x3];
8567         u8         reserved_at_18[0x6];
8568         u8         mode[0x2];
8569
8570         u8         reserved_at_20[0x20];
8571
8572         u8         reserved_at_40[0x10];
8573         u8         min_threshold[0x10];
8574
8575         u8         reserved_at_60[0x10];
8576         u8         max_threshold[0x10];
8577
8578         u8         reserved_at_80[0x10];
8579         u8         mark_probability_denominator[0x10];
8580
8581         u8         reserved_at_a0[0x60];
8582 };
8583
8584 struct mlx5_ifc_ppsc_reg_bits {
8585         u8         reserved_at_0[0x8];
8586         u8         local_port[0x8];
8587         u8         reserved_at_10[0x10];
8588
8589         u8         reserved_at_20[0x60];
8590
8591         u8         reserved_at_80[0x1c];
8592         u8         wrps_admin[0x4];
8593
8594         u8         reserved_at_a0[0x1c];
8595         u8         wrps_status[0x4];
8596
8597         u8         reserved_at_c0[0x8];
8598         u8         up_threshold[0x8];
8599         u8         reserved_at_d0[0x8];
8600         u8         down_threshold[0x8];
8601
8602         u8         reserved_at_e0[0x20];
8603
8604         u8         reserved_at_100[0x1c];
8605         u8         srps_admin[0x4];
8606
8607         u8         reserved_at_120[0x1c];
8608         u8         srps_status[0x4];
8609
8610         u8         reserved_at_140[0x40];
8611 };
8612
8613 struct mlx5_ifc_pplr_reg_bits {
8614         u8         reserved_at_0[0x8];
8615         u8         local_port[0x8];
8616         u8         reserved_at_10[0x10];
8617
8618         u8         reserved_at_20[0x8];
8619         u8         lb_cap[0x8];
8620         u8         reserved_at_30[0x8];
8621         u8         lb_en[0x8];
8622 };
8623
8624 struct mlx5_ifc_pplm_reg_bits {
8625         u8         reserved_at_0[0x8];
8626         u8         local_port[0x8];
8627         u8         reserved_at_10[0x10];
8628
8629         u8         reserved_at_20[0x20];
8630
8631         u8         port_profile_mode[0x8];
8632         u8         static_port_profile[0x8];
8633         u8         active_port_profile[0x8];
8634         u8         reserved_at_58[0x8];
8635
8636         u8         retransmission_active[0x8];
8637         u8         fec_mode_active[0x18];
8638
8639         u8         rs_fec_correction_bypass_cap[0x4];
8640         u8         reserved_at_84[0x8];
8641         u8         fec_override_cap_56g[0x4];
8642         u8         fec_override_cap_100g[0x4];
8643         u8         fec_override_cap_50g[0x4];
8644         u8         fec_override_cap_25g[0x4];
8645         u8         fec_override_cap_10g_40g[0x4];
8646
8647         u8         rs_fec_correction_bypass_admin[0x4];
8648         u8         reserved_at_a4[0x8];
8649         u8         fec_override_admin_56g[0x4];
8650         u8         fec_override_admin_100g[0x4];
8651         u8         fec_override_admin_50g[0x4];
8652         u8         fec_override_admin_25g[0x4];
8653         u8         fec_override_admin_10g_40g[0x4];
8654
8655         u8         fec_override_cap_400g_8x[0x10];
8656         u8         fec_override_cap_200g_4x[0x10];
8657
8658         u8         fec_override_cap_100g_2x[0x10];
8659         u8         fec_override_cap_50g_1x[0x10];
8660
8661         u8         fec_override_admin_400g_8x[0x10];
8662         u8         fec_override_admin_200g_4x[0x10];
8663
8664         u8         fec_override_admin_100g_2x[0x10];
8665         u8         fec_override_admin_50g_1x[0x10];
8666 };
8667
8668 struct mlx5_ifc_ppcnt_reg_bits {
8669         u8         swid[0x8];
8670         u8         local_port[0x8];
8671         u8         pnat[0x2];
8672         u8         reserved_at_12[0x8];
8673         u8         grp[0x6];
8674
8675         u8         clr[0x1];
8676         u8         reserved_at_21[0x1c];
8677         u8         prio_tc[0x3];
8678
8679         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8680 };
8681
8682 struct mlx5_ifc_mpein_reg_bits {
8683         u8         reserved_at_0[0x2];
8684         u8         depth[0x6];
8685         u8         pcie_index[0x8];
8686         u8         node[0x8];
8687         u8         reserved_at_18[0x8];
8688
8689         u8         capability_mask[0x20];
8690
8691         u8         reserved_at_40[0x8];
8692         u8         link_width_enabled[0x8];
8693         u8         link_speed_enabled[0x10];
8694
8695         u8         lane0_physical_position[0x8];
8696         u8         link_width_active[0x8];
8697         u8         link_speed_active[0x10];
8698
8699         u8         num_of_pfs[0x10];
8700         u8         num_of_vfs[0x10];
8701
8702         u8         bdf0[0x10];
8703         u8         reserved_at_b0[0x10];
8704
8705         u8         max_read_request_size[0x4];
8706         u8         max_payload_size[0x4];
8707         u8         reserved_at_c8[0x5];
8708         u8         pwr_status[0x3];
8709         u8         port_type[0x4];
8710         u8         reserved_at_d4[0xb];
8711         u8         lane_reversal[0x1];
8712
8713         u8         reserved_at_e0[0x14];
8714         u8         pci_power[0xc];
8715
8716         u8         reserved_at_100[0x20];
8717
8718         u8         device_status[0x10];
8719         u8         port_state[0x8];
8720         u8         reserved_at_138[0x8];
8721
8722         u8         reserved_at_140[0x10];
8723         u8         receiver_detect_result[0x10];
8724
8725         u8         reserved_at_160[0x20];
8726 };
8727
8728 struct mlx5_ifc_mpcnt_reg_bits {
8729         u8         reserved_at_0[0x8];
8730         u8         pcie_index[0x8];
8731         u8         reserved_at_10[0xa];
8732         u8         grp[0x6];
8733
8734         u8         clr[0x1];
8735         u8         reserved_at_21[0x1f];
8736
8737         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8738 };
8739
8740 struct mlx5_ifc_ppad_reg_bits {
8741         u8         reserved_at_0[0x3];
8742         u8         single_mac[0x1];
8743         u8         reserved_at_4[0x4];
8744         u8         local_port[0x8];
8745         u8         mac_47_32[0x10];
8746
8747         u8         mac_31_0[0x20];
8748
8749         u8         reserved_at_40[0x40];
8750 };
8751
8752 struct mlx5_ifc_pmtu_reg_bits {
8753         u8         reserved_at_0[0x8];
8754         u8         local_port[0x8];
8755         u8         reserved_at_10[0x10];
8756
8757         u8         max_mtu[0x10];
8758         u8         reserved_at_30[0x10];
8759
8760         u8         admin_mtu[0x10];
8761         u8         reserved_at_50[0x10];
8762
8763         u8         oper_mtu[0x10];
8764         u8         reserved_at_70[0x10];
8765 };
8766
8767 struct mlx5_ifc_pmpr_reg_bits {
8768         u8         reserved_at_0[0x8];
8769         u8         module[0x8];
8770         u8         reserved_at_10[0x10];
8771
8772         u8         reserved_at_20[0x18];
8773         u8         attenuation_5g[0x8];
8774
8775         u8         reserved_at_40[0x18];
8776         u8         attenuation_7g[0x8];
8777
8778         u8         reserved_at_60[0x18];
8779         u8         attenuation_12g[0x8];
8780 };
8781
8782 struct mlx5_ifc_pmpe_reg_bits {
8783         u8         reserved_at_0[0x8];
8784         u8         module[0x8];
8785         u8         reserved_at_10[0xc];
8786         u8         module_status[0x4];
8787
8788         u8         reserved_at_20[0x60];
8789 };
8790
8791 struct mlx5_ifc_pmpc_reg_bits {
8792         u8         module_state_updated[32][0x8];
8793 };
8794
8795 struct mlx5_ifc_pmlpn_reg_bits {
8796         u8         reserved_at_0[0x4];
8797         u8         mlpn_status[0x4];
8798         u8         local_port[0x8];
8799         u8         reserved_at_10[0x10];
8800
8801         u8         e[0x1];
8802         u8         reserved_at_21[0x1f];
8803 };
8804
8805 struct mlx5_ifc_pmlp_reg_bits {
8806         u8         rxtx[0x1];
8807         u8         reserved_at_1[0x7];
8808         u8         local_port[0x8];
8809         u8         reserved_at_10[0x8];
8810         u8         width[0x8];
8811
8812         u8         lane0_module_mapping[0x20];
8813
8814         u8         lane1_module_mapping[0x20];
8815
8816         u8         lane2_module_mapping[0x20];
8817
8818         u8         lane3_module_mapping[0x20];
8819
8820         u8         reserved_at_a0[0x160];
8821 };
8822
8823 struct mlx5_ifc_pmaos_reg_bits {
8824         u8         reserved_at_0[0x8];
8825         u8         module[0x8];
8826         u8         reserved_at_10[0x4];
8827         u8         admin_status[0x4];
8828         u8         reserved_at_18[0x4];
8829         u8         oper_status[0x4];
8830
8831         u8         ase[0x1];
8832         u8         ee[0x1];
8833         u8         reserved_at_22[0x1c];
8834         u8         e[0x2];
8835
8836         u8         reserved_at_40[0x40];
8837 };
8838
8839 struct mlx5_ifc_plpc_reg_bits {
8840         u8         reserved_at_0[0x4];
8841         u8         profile_id[0xc];
8842         u8         reserved_at_10[0x4];
8843         u8         proto_mask[0x4];
8844         u8         reserved_at_18[0x8];
8845
8846         u8         reserved_at_20[0x10];
8847         u8         lane_speed[0x10];
8848
8849         u8         reserved_at_40[0x17];
8850         u8         lpbf[0x1];
8851         u8         fec_mode_policy[0x8];
8852
8853         u8         retransmission_capability[0x8];
8854         u8         fec_mode_capability[0x18];
8855
8856         u8         retransmission_support_admin[0x8];
8857         u8         fec_mode_support_admin[0x18];
8858
8859         u8         retransmission_request_admin[0x8];
8860         u8         fec_mode_request_admin[0x18];
8861
8862         u8         reserved_at_c0[0x80];
8863 };
8864
8865 struct mlx5_ifc_plib_reg_bits {
8866         u8         reserved_at_0[0x8];
8867         u8         local_port[0x8];
8868         u8         reserved_at_10[0x8];
8869         u8         ib_port[0x8];
8870
8871         u8         reserved_at_20[0x60];
8872 };
8873
8874 struct mlx5_ifc_plbf_reg_bits {
8875         u8         reserved_at_0[0x8];
8876         u8         local_port[0x8];
8877         u8         reserved_at_10[0xd];
8878         u8         lbf_mode[0x3];
8879
8880         u8         reserved_at_20[0x20];
8881 };
8882
8883 struct mlx5_ifc_pipg_reg_bits {
8884         u8         reserved_at_0[0x8];
8885         u8         local_port[0x8];
8886         u8         reserved_at_10[0x10];
8887
8888         u8         dic[0x1];
8889         u8         reserved_at_21[0x19];
8890         u8         ipg[0x4];
8891         u8         reserved_at_3e[0x2];
8892 };
8893
8894 struct mlx5_ifc_pifr_reg_bits {
8895         u8         reserved_at_0[0x8];
8896         u8         local_port[0x8];
8897         u8         reserved_at_10[0x10];
8898
8899         u8         reserved_at_20[0xe0];
8900
8901         u8         port_filter[8][0x20];
8902
8903         u8         port_filter_update_en[8][0x20];
8904 };
8905
8906 struct mlx5_ifc_pfcc_reg_bits {
8907         u8         reserved_at_0[0x8];
8908         u8         local_port[0x8];
8909         u8         reserved_at_10[0xb];
8910         u8         ppan_mask_n[0x1];
8911         u8         minor_stall_mask[0x1];
8912         u8         critical_stall_mask[0x1];
8913         u8         reserved_at_1e[0x2];
8914
8915         u8         ppan[0x4];
8916         u8         reserved_at_24[0x4];
8917         u8         prio_mask_tx[0x8];
8918         u8         reserved_at_30[0x8];
8919         u8         prio_mask_rx[0x8];
8920
8921         u8         pptx[0x1];
8922         u8         aptx[0x1];
8923         u8         pptx_mask_n[0x1];
8924         u8         reserved_at_43[0x5];
8925         u8         pfctx[0x8];
8926         u8         reserved_at_50[0x10];
8927
8928         u8         pprx[0x1];
8929         u8         aprx[0x1];
8930         u8         pprx_mask_n[0x1];
8931         u8         reserved_at_63[0x5];
8932         u8         pfcrx[0x8];
8933         u8         reserved_at_70[0x10];
8934
8935         u8         device_stall_minor_watermark[0x10];
8936         u8         device_stall_critical_watermark[0x10];
8937
8938         u8         reserved_at_a0[0x60];
8939 };
8940
8941 struct mlx5_ifc_pelc_reg_bits {
8942         u8         op[0x4];
8943         u8         reserved_at_4[0x4];
8944         u8         local_port[0x8];
8945         u8         reserved_at_10[0x10];
8946
8947         u8         op_admin[0x8];
8948         u8         op_capability[0x8];
8949         u8         op_request[0x8];
8950         u8         op_active[0x8];
8951
8952         u8         admin[0x40];
8953
8954         u8         capability[0x40];
8955
8956         u8         request[0x40];
8957
8958         u8         active[0x40];
8959
8960         u8         reserved_at_140[0x80];
8961 };
8962
8963 struct mlx5_ifc_peir_reg_bits {
8964         u8         reserved_at_0[0x8];
8965         u8         local_port[0x8];
8966         u8         reserved_at_10[0x10];
8967
8968         u8         reserved_at_20[0xc];
8969         u8         error_count[0x4];
8970         u8         reserved_at_30[0x10];
8971
8972         u8         reserved_at_40[0xc];
8973         u8         lane[0x4];
8974         u8         reserved_at_50[0x8];
8975         u8         error_type[0x8];
8976 };
8977
8978 struct mlx5_ifc_mpegc_reg_bits {
8979         u8         reserved_at_0[0x30];
8980         u8         field_select[0x10];
8981
8982         u8         tx_overflow_sense[0x1];
8983         u8         mark_cqe[0x1];
8984         u8         mark_cnp[0x1];
8985         u8         reserved_at_43[0x1b];
8986         u8         tx_lossy_overflow_oper[0x2];
8987
8988         u8         reserved_at_60[0x100];
8989 };
8990
8991 struct mlx5_ifc_pcam_enhanced_features_bits {
8992         u8         reserved_at_0[0x68];
8993         u8         fec_50G_per_lane_in_pplm[0x1];
8994         u8         reserved_at_69[0x4];
8995         u8         rx_icrc_encapsulated_counter[0x1];
8996         u8         reserved_at_6e[0x4];
8997         u8         ptys_extended_ethernet[0x1];
8998         u8         reserved_at_73[0x3];
8999         u8         pfcc_mask[0x1];
9000         u8         reserved_at_77[0x3];
9001         u8         per_lane_error_counters[0x1];
9002         u8         rx_buffer_fullness_counters[0x1];
9003         u8         ptys_connector_type[0x1];
9004         u8         reserved_at_7d[0x1];
9005         u8         ppcnt_discard_group[0x1];
9006         u8         ppcnt_statistical_group[0x1];
9007 };
9008
9009 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9010         u8         port_access_reg_cap_mask_127_to_96[0x20];
9011         u8         port_access_reg_cap_mask_95_to_64[0x20];
9012
9013         u8         port_access_reg_cap_mask_63_to_36[0x1c];
9014         u8         pplm[0x1];
9015         u8         port_access_reg_cap_mask_34_to_32[0x3];
9016
9017         u8         port_access_reg_cap_mask_31_to_13[0x13];
9018         u8         pbmc[0x1];
9019         u8         pptb[0x1];
9020         u8         port_access_reg_cap_mask_10_to_09[0x2];
9021         u8         ppcnt[0x1];
9022         u8         port_access_reg_cap_mask_07_to_00[0x8];
9023 };
9024
9025 struct mlx5_ifc_pcam_reg_bits {
9026         u8         reserved_at_0[0x8];
9027         u8         feature_group[0x8];
9028         u8         reserved_at_10[0x8];
9029         u8         access_reg_group[0x8];
9030
9031         u8         reserved_at_20[0x20];
9032
9033         union {
9034                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9035                 u8         reserved_at_0[0x80];
9036         } port_access_reg_cap_mask;
9037
9038         u8         reserved_at_c0[0x80];
9039
9040         union {
9041                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9042                 u8         reserved_at_0[0x80];
9043         } feature_cap_mask;
9044
9045         u8         reserved_at_1c0[0xc0];
9046 };
9047
9048 struct mlx5_ifc_mcam_enhanced_features_bits {
9049         u8         reserved_at_0[0x6e];
9050         u8         pci_status_and_power[0x1];
9051         u8         reserved_at_6f[0x5];
9052         u8         mark_tx_action_cnp[0x1];
9053         u8         mark_tx_action_cqe[0x1];
9054         u8         dynamic_tx_overflow[0x1];
9055         u8         reserved_at_77[0x4];
9056         u8         pcie_outbound_stalled[0x1];
9057         u8         tx_overflow_buffer_pkt[0x1];
9058         u8         mtpps_enh_out_per_adj[0x1];
9059         u8         mtpps_fs[0x1];
9060         u8         pcie_performance_group[0x1];
9061 };
9062
9063 struct mlx5_ifc_mcam_access_reg_bits {
9064         u8         reserved_at_0[0x1c];
9065         u8         mcda[0x1];
9066         u8         mcc[0x1];
9067         u8         mcqi[0x1];
9068         u8         mcqs[0x1];
9069
9070         u8         regs_95_to_87[0x9];
9071         u8         mpegc[0x1];
9072         u8         regs_85_to_68[0x12];
9073         u8         tracer_registers[0x4];
9074
9075         u8         regs_63_to_32[0x20];
9076         u8         regs_31_to_0[0x20];
9077 };
9078
9079 struct mlx5_ifc_mcam_access_reg_bits1 {
9080         u8         regs_127_to_96[0x20];
9081
9082         u8         regs_95_to_64[0x20];
9083
9084         u8         regs_63_to_32[0x20];
9085
9086         u8         regs_31_to_0[0x20];
9087 };
9088
9089 struct mlx5_ifc_mcam_access_reg_bits2 {
9090         u8         regs_127_to_99[0x1d];
9091         u8         mirc[0x1];
9092         u8         regs_97_to_96[0x2];
9093
9094         u8         regs_95_to_64[0x20];
9095
9096         u8         regs_63_to_32[0x20];
9097
9098         u8         regs_31_to_0[0x20];
9099 };
9100
9101 struct mlx5_ifc_mcam_reg_bits {
9102         u8         reserved_at_0[0x8];
9103         u8         feature_group[0x8];
9104         u8         reserved_at_10[0x8];
9105         u8         access_reg_group[0x8];
9106
9107         u8         reserved_at_20[0x20];
9108
9109         union {
9110                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9111                 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9112                 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9113                 u8         reserved_at_0[0x80];
9114         } mng_access_reg_cap_mask;
9115
9116         u8         reserved_at_c0[0x80];
9117
9118         union {
9119                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9120                 u8         reserved_at_0[0x80];
9121         } mng_feature_cap_mask;
9122
9123         u8         reserved_at_1c0[0x80];
9124 };
9125
9126 struct mlx5_ifc_qcam_access_reg_cap_mask {
9127         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9128         u8         qpdpm[0x1];
9129         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9130         u8         qdpm[0x1];
9131         u8         qpts[0x1];
9132         u8         qcap[0x1];
9133         u8         qcam_access_reg_cap_mask_0[0x1];
9134 };
9135
9136 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9137         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9138         u8         qpts_trust_both[0x1];
9139 };
9140
9141 struct mlx5_ifc_qcam_reg_bits {
9142         u8         reserved_at_0[0x8];
9143         u8         feature_group[0x8];
9144         u8         reserved_at_10[0x8];
9145         u8         access_reg_group[0x8];
9146         u8         reserved_at_20[0x20];
9147
9148         union {
9149                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9150                 u8  reserved_at_0[0x80];
9151         } qos_access_reg_cap_mask;
9152
9153         u8         reserved_at_c0[0x80];
9154
9155         union {
9156                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9157                 u8  reserved_at_0[0x80];
9158         } qos_feature_cap_mask;
9159
9160         u8         reserved_at_1c0[0x80];
9161 };
9162
9163 struct mlx5_ifc_core_dump_reg_bits {
9164         u8         reserved_at_0[0x18];
9165         u8         core_dump_type[0x8];
9166
9167         u8         reserved_at_20[0x30];
9168         u8         vhca_id[0x10];
9169
9170         u8         reserved_at_60[0x8];
9171         u8         qpn[0x18];
9172         u8         reserved_at_80[0x180];
9173 };
9174
9175 struct mlx5_ifc_pcap_reg_bits {
9176         u8         reserved_at_0[0x8];
9177         u8         local_port[0x8];
9178         u8         reserved_at_10[0x10];
9179
9180         u8         port_capability_mask[4][0x20];
9181 };
9182
9183 struct mlx5_ifc_paos_reg_bits {
9184         u8         swid[0x8];
9185         u8         local_port[0x8];
9186         u8         reserved_at_10[0x4];
9187         u8         admin_status[0x4];
9188         u8         reserved_at_18[0x4];
9189         u8         oper_status[0x4];
9190
9191         u8         ase[0x1];
9192         u8         ee[0x1];
9193         u8         reserved_at_22[0x1c];
9194         u8         e[0x2];
9195
9196         u8         reserved_at_40[0x40];
9197 };
9198
9199 struct mlx5_ifc_pamp_reg_bits {
9200         u8         reserved_at_0[0x8];
9201         u8         opamp_group[0x8];
9202         u8         reserved_at_10[0xc];
9203         u8         opamp_group_type[0x4];
9204
9205         u8         start_index[0x10];
9206         u8         reserved_at_30[0x4];
9207         u8         num_of_indices[0xc];
9208
9209         u8         index_data[18][0x10];
9210 };
9211
9212 struct mlx5_ifc_pcmr_reg_bits {
9213         u8         reserved_at_0[0x8];
9214         u8         local_port[0x8];
9215         u8         reserved_at_10[0x10];
9216         u8         entropy_force_cap[0x1];
9217         u8         entropy_calc_cap[0x1];
9218         u8         entropy_gre_calc_cap[0x1];
9219         u8         reserved_at_23[0x1b];
9220         u8         fcs_cap[0x1];
9221         u8         reserved_at_3f[0x1];
9222         u8         entropy_force[0x1];
9223         u8         entropy_calc[0x1];
9224         u8         entropy_gre_calc[0x1];
9225         u8         reserved_at_43[0x1b];
9226         u8         fcs_chk[0x1];
9227         u8         reserved_at_5f[0x1];
9228 };
9229
9230 struct mlx5_ifc_lane_2_module_mapping_bits {
9231         u8         reserved_at_0[0x6];
9232         u8         rx_lane[0x2];
9233         u8         reserved_at_8[0x6];
9234         u8         tx_lane[0x2];
9235         u8         reserved_at_10[0x8];
9236         u8         module[0x8];
9237 };
9238
9239 struct mlx5_ifc_bufferx_reg_bits {
9240         u8         reserved_at_0[0x6];
9241         u8         lossy[0x1];
9242         u8         epsb[0x1];
9243         u8         reserved_at_8[0xc];
9244         u8         size[0xc];
9245
9246         u8         xoff_threshold[0x10];
9247         u8         xon_threshold[0x10];
9248 };
9249
9250 struct mlx5_ifc_set_node_in_bits {
9251         u8         node_description[64][0x8];
9252 };
9253
9254 struct mlx5_ifc_register_power_settings_bits {
9255         u8         reserved_at_0[0x18];
9256         u8         power_settings_level[0x8];
9257
9258         u8         reserved_at_20[0x60];
9259 };
9260
9261 struct mlx5_ifc_register_host_endianness_bits {
9262         u8         he[0x1];
9263         u8         reserved_at_1[0x1f];
9264
9265         u8         reserved_at_20[0x60];
9266 };
9267
9268 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9269         u8         reserved_at_0[0x20];
9270
9271         u8         mkey[0x20];
9272
9273         u8         addressh_63_32[0x20];
9274
9275         u8         addressl_31_0[0x20];
9276 };
9277
9278 struct mlx5_ifc_ud_adrs_vector_bits {
9279         u8         dc_key[0x40];
9280
9281         u8         ext[0x1];
9282         u8         reserved_at_41[0x7];
9283         u8         destination_qp_dct[0x18];
9284
9285         u8         static_rate[0x4];
9286         u8         sl_eth_prio[0x4];
9287         u8         fl[0x1];
9288         u8         mlid[0x7];
9289         u8         rlid_udp_sport[0x10];
9290
9291         u8         reserved_at_80[0x20];
9292
9293         u8         rmac_47_16[0x20];
9294
9295         u8         rmac_15_0[0x10];
9296         u8         tclass[0x8];
9297         u8         hop_limit[0x8];
9298
9299         u8         reserved_at_e0[0x1];
9300         u8         grh[0x1];
9301         u8         reserved_at_e2[0x2];
9302         u8         src_addr_index[0x8];
9303         u8         flow_label[0x14];
9304
9305         u8         rgid_rip[16][0x8];
9306 };
9307
9308 struct mlx5_ifc_pages_req_event_bits {
9309         u8         reserved_at_0[0x10];
9310         u8         function_id[0x10];
9311
9312         u8         num_pages[0x20];
9313
9314         u8         reserved_at_40[0xa0];
9315 };
9316
9317 struct mlx5_ifc_eqe_bits {
9318         u8         reserved_at_0[0x8];
9319         u8         event_type[0x8];
9320         u8         reserved_at_10[0x8];
9321         u8         event_sub_type[0x8];
9322
9323         u8         reserved_at_20[0xe0];
9324
9325         union mlx5_ifc_event_auto_bits event_data;
9326
9327         u8         reserved_at_1e0[0x10];
9328         u8         signature[0x8];
9329         u8         reserved_at_1f8[0x7];
9330         u8         owner[0x1];
9331 };
9332
9333 enum {
9334         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
9335 };
9336
9337 struct mlx5_ifc_cmd_queue_entry_bits {
9338         u8         type[0x8];
9339         u8         reserved_at_8[0x18];
9340
9341         u8         input_length[0x20];
9342
9343         u8         input_mailbox_pointer_63_32[0x20];
9344
9345         u8         input_mailbox_pointer_31_9[0x17];
9346         u8         reserved_at_77[0x9];
9347
9348         u8         command_input_inline_data[16][0x8];
9349
9350         u8         command_output_inline_data[16][0x8];
9351
9352         u8         output_mailbox_pointer_63_32[0x20];
9353
9354         u8         output_mailbox_pointer_31_9[0x17];
9355         u8         reserved_at_1b7[0x9];
9356
9357         u8         output_length[0x20];
9358
9359         u8         token[0x8];
9360         u8         signature[0x8];
9361         u8         reserved_at_1f0[0x8];
9362         u8         status[0x7];
9363         u8         ownership[0x1];
9364 };
9365
9366 struct mlx5_ifc_cmd_out_bits {
9367         u8         status[0x8];
9368         u8         reserved_at_8[0x18];
9369
9370         u8         syndrome[0x20];
9371
9372         u8         command_output[0x20];
9373 };
9374
9375 struct mlx5_ifc_cmd_in_bits {
9376         u8         opcode[0x10];
9377         u8         reserved_at_10[0x10];
9378
9379         u8         reserved_at_20[0x10];
9380         u8         op_mod[0x10];
9381
9382         u8         command[][0x20];
9383 };
9384
9385 struct mlx5_ifc_cmd_if_box_bits {
9386         u8         mailbox_data[512][0x8];
9387
9388         u8         reserved_at_1000[0x180];
9389
9390         u8         next_pointer_63_32[0x20];
9391
9392         u8         next_pointer_31_10[0x16];
9393         u8         reserved_at_11b6[0xa];
9394
9395         u8         block_number[0x20];
9396
9397         u8         reserved_at_11e0[0x8];
9398         u8         token[0x8];
9399         u8         ctrl_signature[0x8];
9400         u8         signature[0x8];
9401 };
9402
9403 struct mlx5_ifc_mtt_bits {
9404         u8         ptag_63_32[0x20];
9405
9406         u8         ptag_31_8[0x18];
9407         u8         reserved_at_38[0x6];
9408         u8         wr_en[0x1];
9409         u8         rd_en[0x1];
9410 };
9411
9412 struct mlx5_ifc_query_wol_rol_out_bits {
9413         u8         status[0x8];
9414         u8         reserved_at_8[0x18];
9415
9416         u8         syndrome[0x20];
9417
9418         u8         reserved_at_40[0x10];
9419         u8         rol_mode[0x8];
9420         u8         wol_mode[0x8];
9421
9422         u8         reserved_at_60[0x20];
9423 };
9424
9425 struct mlx5_ifc_query_wol_rol_in_bits {
9426         u8         opcode[0x10];
9427         u8         reserved_at_10[0x10];
9428
9429         u8         reserved_at_20[0x10];
9430         u8         op_mod[0x10];
9431
9432         u8         reserved_at_40[0x40];
9433 };
9434
9435 struct mlx5_ifc_set_wol_rol_out_bits {
9436         u8         status[0x8];
9437         u8         reserved_at_8[0x18];
9438
9439         u8         syndrome[0x20];
9440
9441         u8         reserved_at_40[0x40];
9442 };
9443
9444 struct mlx5_ifc_set_wol_rol_in_bits {
9445         u8         opcode[0x10];
9446         u8         reserved_at_10[0x10];
9447
9448         u8         reserved_at_20[0x10];
9449         u8         op_mod[0x10];
9450
9451         u8         rol_mode_valid[0x1];
9452         u8         wol_mode_valid[0x1];
9453         u8         reserved_at_42[0xe];
9454         u8         rol_mode[0x8];
9455         u8         wol_mode[0x8];
9456
9457         u8         reserved_at_60[0x20];
9458 };
9459
9460 enum {
9461         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
9462         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
9463         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
9464 };
9465
9466 enum {
9467         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
9468         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
9469         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
9470 };
9471
9472 enum {
9473         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
9474         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
9475         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9476         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9477         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9478         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9479         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9480         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9481         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9482         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9483         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9484 };
9485
9486 struct mlx5_ifc_initial_seg_bits {
9487         u8         fw_rev_minor[0x10];
9488         u8         fw_rev_major[0x10];
9489
9490         u8         cmd_interface_rev[0x10];
9491         u8         fw_rev_subminor[0x10];
9492
9493         u8         reserved_at_40[0x40];
9494
9495         u8         cmdq_phy_addr_63_32[0x20];
9496
9497         u8         cmdq_phy_addr_31_12[0x14];
9498         u8         reserved_at_b4[0x2];
9499         u8         nic_interface[0x2];
9500         u8         log_cmdq_size[0x4];
9501         u8         log_cmdq_stride[0x4];
9502
9503         u8         command_doorbell_vector[0x20];
9504
9505         u8         reserved_at_e0[0xf00];
9506
9507         u8         initializing[0x1];
9508         u8         reserved_at_fe1[0x4];
9509         u8         nic_interface_supported[0x3];
9510         u8         embedded_cpu[0x1];
9511         u8         reserved_at_fe9[0x17];
9512
9513         struct mlx5_ifc_health_buffer_bits health_buffer;
9514
9515         u8         no_dram_nic_offset[0x20];
9516
9517         u8         reserved_at_1220[0x6e40];
9518
9519         u8         reserved_at_8060[0x1f];
9520         u8         clear_int[0x1];
9521
9522         u8         health_syndrome[0x8];
9523         u8         health_counter[0x18];
9524
9525         u8         reserved_at_80a0[0x17fc0];
9526 };
9527
9528 struct mlx5_ifc_mtpps_reg_bits {
9529         u8         reserved_at_0[0xc];
9530         u8         cap_number_of_pps_pins[0x4];
9531         u8         reserved_at_10[0x4];
9532         u8         cap_max_num_of_pps_in_pins[0x4];
9533         u8         reserved_at_18[0x4];
9534         u8         cap_max_num_of_pps_out_pins[0x4];
9535
9536         u8         reserved_at_20[0x24];
9537         u8         cap_pin_3_mode[0x4];
9538         u8         reserved_at_48[0x4];
9539         u8         cap_pin_2_mode[0x4];
9540         u8         reserved_at_50[0x4];
9541         u8         cap_pin_1_mode[0x4];
9542         u8         reserved_at_58[0x4];
9543         u8         cap_pin_0_mode[0x4];
9544
9545         u8         reserved_at_60[0x4];
9546         u8         cap_pin_7_mode[0x4];
9547         u8         reserved_at_68[0x4];
9548         u8         cap_pin_6_mode[0x4];
9549         u8         reserved_at_70[0x4];
9550         u8         cap_pin_5_mode[0x4];
9551         u8         reserved_at_78[0x4];
9552         u8         cap_pin_4_mode[0x4];
9553
9554         u8         field_select[0x20];
9555         u8         reserved_at_a0[0x60];
9556
9557         u8         enable[0x1];
9558         u8         reserved_at_101[0xb];
9559         u8         pattern[0x4];
9560         u8         reserved_at_110[0x4];
9561         u8         pin_mode[0x4];
9562         u8         pin[0x8];
9563
9564         u8         reserved_at_120[0x20];
9565
9566         u8         time_stamp[0x40];
9567
9568         u8         out_pulse_duration[0x10];
9569         u8         out_periodic_adjustment[0x10];
9570         u8         enhanced_out_periodic_adjustment[0x20];
9571
9572         u8         reserved_at_1c0[0x20];
9573 };
9574
9575 struct mlx5_ifc_mtppse_reg_bits {
9576         u8         reserved_at_0[0x18];
9577         u8         pin[0x8];
9578         u8         event_arm[0x1];
9579         u8         reserved_at_21[0x1b];
9580         u8         event_generation_mode[0x4];
9581         u8         reserved_at_40[0x40];
9582 };
9583
9584 struct mlx5_ifc_mcqs_reg_bits {
9585         u8         last_index_flag[0x1];
9586         u8         reserved_at_1[0x7];
9587         u8         fw_device[0x8];
9588         u8         component_index[0x10];
9589
9590         u8         reserved_at_20[0x10];
9591         u8         identifier[0x10];
9592
9593         u8         reserved_at_40[0x17];
9594         u8         component_status[0x5];
9595         u8         component_update_state[0x4];
9596
9597         u8         last_update_state_changer_type[0x4];
9598         u8         last_update_state_changer_host_id[0x4];
9599         u8         reserved_at_68[0x18];
9600 };
9601
9602 struct mlx5_ifc_mcqi_cap_bits {
9603         u8         supported_info_bitmask[0x20];
9604
9605         u8         component_size[0x20];
9606
9607         u8         max_component_size[0x20];
9608
9609         u8         log_mcda_word_size[0x4];
9610         u8         reserved_at_64[0xc];
9611         u8         mcda_max_write_size[0x10];
9612
9613         u8         rd_en[0x1];
9614         u8         reserved_at_81[0x1];
9615         u8         match_chip_id[0x1];
9616         u8         match_psid[0x1];
9617         u8         check_user_timestamp[0x1];
9618         u8         match_base_guid_mac[0x1];
9619         u8         reserved_at_86[0x1a];
9620 };
9621
9622 struct mlx5_ifc_mcqi_version_bits {
9623         u8         reserved_at_0[0x2];
9624         u8         build_time_valid[0x1];
9625         u8         user_defined_time_valid[0x1];
9626         u8         reserved_at_4[0x14];
9627         u8         version_string_length[0x8];
9628
9629         u8         version[0x20];
9630
9631         u8         build_time[0x40];
9632
9633         u8         user_defined_time[0x40];
9634
9635         u8         build_tool_version[0x20];
9636
9637         u8         reserved_at_e0[0x20];
9638
9639         u8         version_string[92][0x8];
9640 };
9641
9642 struct mlx5_ifc_mcqi_activation_method_bits {
9643         u8         pending_server_ac_power_cycle[0x1];
9644         u8         pending_server_dc_power_cycle[0x1];
9645         u8         pending_server_reboot[0x1];
9646         u8         pending_fw_reset[0x1];
9647         u8         auto_activate[0x1];
9648         u8         all_hosts_sync[0x1];
9649         u8         device_hw_reset[0x1];
9650         u8         reserved_at_7[0x19];
9651 };
9652
9653 union mlx5_ifc_mcqi_reg_data_bits {
9654         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9655         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9656         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9657 };
9658
9659 struct mlx5_ifc_mcqi_reg_bits {
9660         u8         read_pending_component[0x1];
9661         u8         reserved_at_1[0xf];
9662         u8         component_index[0x10];
9663
9664         u8         reserved_at_20[0x20];
9665
9666         u8         reserved_at_40[0x1b];
9667         u8         info_type[0x5];
9668
9669         u8         info_size[0x20];
9670
9671         u8         offset[0x20];
9672
9673         u8         reserved_at_a0[0x10];
9674         u8         data_size[0x10];
9675
9676         union mlx5_ifc_mcqi_reg_data_bits data[];
9677 };
9678
9679 struct mlx5_ifc_mcc_reg_bits {
9680         u8         reserved_at_0[0x4];
9681         u8         time_elapsed_since_last_cmd[0xc];
9682         u8         reserved_at_10[0x8];
9683         u8         instruction[0x8];
9684
9685         u8         reserved_at_20[0x10];
9686         u8         component_index[0x10];
9687
9688         u8         reserved_at_40[0x8];
9689         u8         update_handle[0x18];
9690
9691         u8         handle_owner_type[0x4];
9692         u8         handle_owner_host_id[0x4];
9693         u8         reserved_at_68[0x1];
9694         u8         control_progress[0x7];
9695         u8         error_code[0x8];
9696         u8         reserved_at_78[0x4];
9697         u8         control_state[0x4];
9698
9699         u8         component_size[0x20];
9700
9701         u8         reserved_at_a0[0x60];
9702 };
9703
9704 struct mlx5_ifc_mcda_reg_bits {
9705         u8         reserved_at_0[0x8];
9706         u8         update_handle[0x18];
9707
9708         u8         offset[0x20];
9709
9710         u8         reserved_at_40[0x10];
9711         u8         size[0x10];
9712
9713         u8         reserved_at_60[0x20];
9714
9715         u8         data[0][0x20];
9716 };
9717
9718 enum {
9719         MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
9720         MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
9721 };
9722
9723 enum {
9724         MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
9725         MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
9726         MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
9727 };
9728
9729 struct mlx5_ifc_mfrl_reg_bits {
9730         u8         reserved_at_0[0x20];
9731
9732         u8         reserved_at_20[0x2];
9733         u8         pci_sync_for_fw_update_start[0x1];
9734         u8         pci_sync_for_fw_update_resp[0x2];
9735         u8         rst_type_sel[0x3];
9736         u8         reserved_at_28[0x8];
9737         u8         reset_type[0x8];
9738         u8         reset_level[0x8];
9739 };
9740
9741 struct mlx5_ifc_mirc_reg_bits {
9742         u8         reserved_at_0[0x18];
9743         u8         status_code[0x8];
9744
9745         u8         reserved_at_20[0x20];
9746 };
9747
9748 union mlx5_ifc_ports_control_registers_document_bits {
9749         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9750         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9751         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9752         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9753         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9754         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9755         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9756         struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9757         struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9758         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9759         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9760         struct mlx5_ifc_paos_reg_bits paos_reg;
9761         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9762         struct mlx5_ifc_peir_reg_bits peir_reg;
9763         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9764         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9765         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9766         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9767         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9768         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9769         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9770         struct mlx5_ifc_plib_reg_bits plib_reg;
9771         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9772         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9773         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9774         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9775         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9776         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9777         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9778         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9779         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9780         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9781         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9782         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9783         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9784         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9785         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9786         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9787         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9788         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9789         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9790         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9791         struct mlx5_ifc_pude_reg_bits pude_reg;
9792         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9793         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9794         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9795         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9796         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9797         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9798         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9799         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9800         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9801         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9802         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9803         struct mlx5_ifc_mirc_reg_bits mirc_reg;
9804         struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
9805         u8         reserved_at_0[0x60e0];
9806 };
9807
9808 union mlx5_ifc_debug_enhancements_document_bits {
9809         struct mlx5_ifc_health_buffer_bits health_buffer;
9810         u8         reserved_at_0[0x200];
9811 };
9812
9813 union mlx5_ifc_uplink_pci_interface_document_bits {
9814         struct mlx5_ifc_initial_seg_bits initial_seg;
9815         u8         reserved_at_0[0x20060];
9816 };
9817
9818 struct mlx5_ifc_set_flow_table_root_out_bits {
9819         u8         status[0x8];
9820         u8         reserved_at_8[0x18];
9821
9822         u8         syndrome[0x20];
9823
9824         u8         reserved_at_40[0x40];
9825 };
9826
9827 struct mlx5_ifc_set_flow_table_root_in_bits {
9828         u8         opcode[0x10];
9829         u8         reserved_at_10[0x10];
9830
9831         u8         reserved_at_20[0x10];
9832         u8         op_mod[0x10];
9833
9834         u8         other_vport[0x1];
9835         u8         reserved_at_41[0xf];
9836         u8         vport_number[0x10];
9837
9838         u8         reserved_at_60[0x20];
9839
9840         u8         table_type[0x8];
9841         u8         reserved_at_88[0x18];
9842
9843         u8         reserved_at_a0[0x8];
9844         u8         table_id[0x18];
9845
9846         u8         reserved_at_c0[0x8];
9847         u8         underlay_qpn[0x18];
9848         u8         reserved_at_e0[0x120];
9849 };
9850
9851 enum {
9852         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9853         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9854 };
9855
9856 struct mlx5_ifc_modify_flow_table_out_bits {
9857         u8         status[0x8];
9858         u8         reserved_at_8[0x18];
9859
9860         u8         syndrome[0x20];
9861
9862         u8         reserved_at_40[0x40];
9863 };
9864
9865 struct mlx5_ifc_modify_flow_table_in_bits {
9866         u8         opcode[0x10];
9867         u8         reserved_at_10[0x10];
9868
9869         u8         reserved_at_20[0x10];
9870         u8         op_mod[0x10];
9871
9872         u8         other_vport[0x1];
9873         u8         reserved_at_41[0xf];
9874         u8         vport_number[0x10];
9875
9876         u8         reserved_at_60[0x10];
9877         u8         modify_field_select[0x10];
9878
9879         u8         table_type[0x8];
9880         u8         reserved_at_88[0x18];
9881
9882         u8         reserved_at_a0[0x8];
9883         u8         table_id[0x18];
9884
9885         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9886 };
9887
9888 struct mlx5_ifc_ets_tcn_config_reg_bits {
9889         u8         g[0x1];
9890         u8         b[0x1];
9891         u8         r[0x1];
9892         u8         reserved_at_3[0x9];
9893         u8         group[0x4];
9894         u8         reserved_at_10[0x9];
9895         u8         bw_allocation[0x7];
9896
9897         u8         reserved_at_20[0xc];
9898         u8         max_bw_units[0x4];
9899         u8         reserved_at_30[0x8];
9900         u8         max_bw_value[0x8];
9901 };
9902
9903 struct mlx5_ifc_ets_global_config_reg_bits {
9904         u8         reserved_at_0[0x2];
9905         u8         r[0x1];
9906         u8         reserved_at_3[0x1d];
9907
9908         u8         reserved_at_20[0xc];
9909         u8         max_bw_units[0x4];
9910         u8         reserved_at_30[0x8];
9911         u8         max_bw_value[0x8];
9912 };
9913
9914 struct mlx5_ifc_qetc_reg_bits {
9915         u8                                         reserved_at_0[0x8];
9916         u8                                         port_number[0x8];
9917         u8                                         reserved_at_10[0x30];
9918
9919         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9920         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9921 };
9922
9923 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9924         u8         e[0x1];
9925         u8         reserved_at_01[0x0b];
9926         u8         prio[0x04];
9927 };
9928
9929 struct mlx5_ifc_qpdpm_reg_bits {
9930         u8                                     reserved_at_0[0x8];
9931         u8                                     local_port[0x8];
9932         u8                                     reserved_at_10[0x10];
9933         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9934 };
9935
9936 struct mlx5_ifc_qpts_reg_bits {
9937         u8         reserved_at_0[0x8];
9938         u8         local_port[0x8];
9939         u8         reserved_at_10[0x2d];
9940         u8         trust_state[0x3];
9941 };
9942
9943 struct mlx5_ifc_pptb_reg_bits {
9944         u8         reserved_at_0[0x2];
9945         u8         mm[0x2];
9946         u8         reserved_at_4[0x4];
9947         u8         local_port[0x8];
9948         u8         reserved_at_10[0x6];
9949         u8         cm[0x1];
9950         u8         um[0x1];
9951         u8         pm[0x8];
9952
9953         u8         prio_x_buff[0x20];
9954
9955         u8         pm_msb[0x8];
9956         u8         reserved_at_48[0x10];
9957         u8         ctrl_buff[0x4];
9958         u8         untagged_buff[0x4];
9959 };
9960
9961 struct mlx5_ifc_pbmc_reg_bits {
9962         u8         reserved_at_0[0x8];
9963         u8         local_port[0x8];
9964         u8         reserved_at_10[0x10];
9965
9966         u8         xoff_timer_value[0x10];
9967         u8         xoff_refresh[0x10];
9968
9969         u8         reserved_at_40[0x9];
9970         u8         fullness_threshold[0x7];
9971         u8         port_buffer_size[0x10];
9972
9973         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9974
9975         u8         reserved_at_2e0[0x40];
9976 };
9977
9978 struct mlx5_ifc_qtct_reg_bits {
9979         u8         reserved_at_0[0x8];
9980         u8         port_number[0x8];
9981         u8         reserved_at_10[0xd];
9982         u8         prio[0x3];
9983
9984         u8         reserved_at_20[0x1d];
9985         u8         tclass[0x3];
9986 };
9987
9988 struct mlx5_ifc_mcia_reg_bits {
9989         u8         l[0x1];
9990         u8         reserved_at_1[0x7];
9991         u8         module[0x8];
9992         u8         reserved_at_10[0x8];
9993         u8         status[0x8];
9994
9995         u8         i2c_device_address[0x8];
9996         u8         page_number[0x8];
9997         u8         device_address[0x10];
9998
9999         u8         reserved_at_40[0x10];
10000         u8         size[0x10];
10001
10002         u8         reserved_at_60[0x20];
10003
10004         u8         dword_0[0x20];
10005         u8         dword_1[0x20];
10006         u8         dword_2[0x20];
10007         u8         dword_3[0x20];
10008         u8         dword_4[0x20];
10009         u8         dword_5[0x20];
10010         u8         dword_6[0x20];
10011         u8         dword_7[0x20];
10012         u8         dword_8[0x20];
10013         u8         dword_9[0x20];
10014         u8         dword_10[0x20];
10015         u8         dword_11[0x20];
10016 };
10017
10018 struct mlx5_ifc_dcbx_param_bits {
10019         u8         dcbx_cee_cap[0x1];
10020         u8         dcbx_ieee_cap[0x1];
10021         u8         dcbx_standby_cap[0x1];
10022         u8         reserved_at_3[0x5];
10023         u8         port_number[0x8];
10024         u8         reserved_at_10[0xa];
10025         u8         max_application_table_size[6];
10026         u8         reserved_at_20[0x15];
10027         u8         version_oper[0x3];
10028         u8         reserved_at_38[5];
10029         u8         version_admin[0x3];
10030         u8         willing_admin[0x1];
10031         u8         reserved_at_41[0x3];
10032         u8         pfc_cap_oper[0x4];
10033         u8         reserved_at_48[0x4];
10034         u8         pfc_cap_admin[0x4];
10035         u8         reserved_at_50[0x4];
10036         u8         num_of_tc_oper[0x4];
10037         u8         reserved_at_58[0x4];
10038         u8         num_of_tc_admin[0x4];
10039         u8         remote_willing[0x1];
10040         u8         reserved_at_61[3];
10041         u8         remote_pfc_cap[4];
10042         u8         reserved_at_68[0x14];
10043         u8         remote_num_of_tc[0x4];
10044         u8         reserved_at_80[0x18];
10045         u8         error[0x8];
10046         u8         reserved_at_a0[0x160];
10047 };
10048
10049 struct mlx5_ifc_lagc_bits {
10050         u8         reserved_at_0[0x1d];
10051         u8         lag_state[0x3];
10052
10053         u8         reserved_at_20[0x14];
10054         u8         tx_remap_affinity_2[0x4];
10055         u8         reserved_at_38[0x4];
10056         u8         tx_remap_affinity_1[0x4];
10057 };
10058
10059 struct mlx5_ifc_create_lag_out_bits {
10060         u8         status[0x8];
10061         u8         reserved_at_8[0x18];
10062
10063         u8         syndrome[0x20];
10064
10065         u8         reserved_at_40[0x40];
10066 };
10067
10068 struct mlx5_ifc_create_lag_in_bits {
10069         u8         opcode[0x10];
10070         u8         reserved_at_10[0x10];
10071
10072         u8         reserved_at_20[0x10];
10073         u8         op_mod[0x10];
10074
10075         struct mlx5_ifc_lagc_bits ctx;
10076 };
10077
10078 struct mlx5_ifc_modify_lag_out_bits {
10079         u8         status[0x8];
10080         u8         reserved_at_8[0x18];
10081
10082         u8         syndrome[0x20];
10083
10084         u8         reserved_at_40[0x40];
10085 };
10086
10087 struct mlx5_ifc_modify_lag_in_bits {
10088         u8         opcode[0x10];
10089         u8         reserved_at_10[0x10];
10090
10091         u8         reserved_at_20[0x10];
10092         u8         op_mod[0x10];
10093
10094         u8         reserved_at_40[0x20];
10095         u8         field_select[0x20];
10096
10097         struct mlx5_ifc_lagc_bits ctx;
10098 };
10099
10100 struct mlx5_ifc_query_lag_out_bits {
10101         u8         status[0x8];
10102         u8         reserved_at_8[0x18];
10103
10104         u8         syndrome[0x20];
10105
10106         struct mlx5_ifc_lagc_bits ctx;
10107 };
10108
10109 struct mlx5_ifc_query_lag_in_bits {
10110         u8         opcode[0x10];
10111         u8         reserved_at_10[0x10];
10112
10113         u8         reserved_at_20[0x10];
10114         u8         op_mod[0x10];
10115
10116         u8         reserved_at_40[0x40];
10117 };
10118
10119 struct mlx5_ifc_destroy_lag_out_bits {
10120         u8         status[0x8];
10121         u8         reserved_at_8[0x18];
10122
10123         u8         syndrome[0x20];
10124
10125         u8         reserved_at_40[0x40];
10126 };
10127
10128 struct mlx5_ifc_destroy_lag_in_bits {
10129         u8         opcode[0x10];
10130         u8         reserved_at_10[0x10];
10131
10132         u8         reserved_at_20[0x10];
10133         u8         op_mod[0x10];
10134
10135         u8         reserved_at_40[0x40];
10136 };
10137
10138 struct mlx5_ifc_create_vport_lag_out_bits {
10139         u8         status[0x8];
10140         u8         reserved_at_8[0x18];
10141
10142         u8         syndrome[0x20];
10143
10144         u8         reserved_at_40[0x40];
10145 };
10146
10147 struct mlx5_ifc_create_vport_lag_in_bits {
10148         u8         opcode[0x10];
10149         u8         reserved_at_10[0x10];
10150
10151         u8         reserved_at_20[0x10];
10152         u8         op_mod[0x10];
10153
10154         u8         reserved_at_40[0x40];
10155 };
10156
10157 struct mlx5_ifc_destroy_vport_lag_out_bits {
10158         u8         status[0x8];
10159         u8         reserved_at_8[0x18];
10160
10161         u8         syndrome[0x20];
10162
10163         u8         reserved_at_40[0x40];
10164 };
10165
10166 struct mlx5_ifc_destroy_vport_lag_in_bits {
10167         u8         opcode[0x10];
10168         u8         reserved_at_10[0x10];
10169
10170         u8         reserved_at_20[0x10];
10171         u8         op_mod[0x10];
10172
10173         u8         reserved_at_40[0x40];
10174 };
10175
10176 struct mlx5_ifc_alloc_memic_in_bits {
10177         u8         opcode[0x10];
10178         u8         reserved_at_10[0x10];
10179
10180         u8         reserved_at_20[0x10];
10181         u8         op_mod[0x10];
10182
10183         u8         reserved_at_30[0x20];
10184
10185         u8         reserved_at_40[0x18];
10186         u8         log_memic_addr_alignment[0x8];
10187
10188         u8         range_start_addr[0x40];
10189
10190         u8         range_size[0x20];
10191
10192         u8         memic_size[0x20];
10193 };
10194
10195 struct mlx5_ifc_alloc_memic_out_bits {
10196         u8         status[0x8];
10197         u8         reserved_at_8[0x18];
10198
10199         u8         syndrome[0x20];
10200
10201         u8         memic_start_addr[0x40];
10202 };
10203
10204 struct mlx5_ifc_dealloc_memic_in_bits {
10205         u8         opcode[0x10];
10206         u8         reserved_at_10[0x10];
10207
10208         u8         reserved_at_20[0x10];
10209         u8         op_mod[0x10];
10210
10211         u8         reserved_at_40[0x40];
10212
10213         u8         memic_start_addr[0x40];
10214
10215         u8         memic_size[0x20];
10216
10217         u8         reserved_at_e0[0x20];
10218 };
10219
10220 struct mlx5_ifc_dealloc_memic_out_bits {
10221         u8         status[0x8];
10222         u8         reserved_at_8[0x18];
10223
10224         u8         syndrome[0x20];
10225
10226         u8         reserved_at_40[0x40];
10227 };
10228
10229 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10230         u8         opcode[0x10];
10231         u8         uid[0x10];
10232
10233         u8         vhca_tunnel_id[0x10];
10234         u8         obj_type[0x10];
10235
10236         u8         obj_id[0x20];
10237
10238         u8         reserved_at_60[0x20];
10239 };
10240
10241 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10242         u8         status[0x8];
10243         u8         reserved_at_8[0x18];
10244
10245         u8         syndrome[0x20];
10246
10247         u8         obj_id[0x20];
10248
10249         u8         reserved_at_60[0x20];
10250 };
10251
10252 struct mlx5_ifc_umem_bits {
10253         u8         reserved_at_0[0x80];
10254
10255         u8         reserved_at_80[0x1b];
10256         u8         log_page_size[0x5];
10257
10258         u8         page_offset[0x20];
10259
10260         u8         num_of_mtt[0x40];
10261
10262         struct mlx5_ifc_mtt_bits  mtt[];
10263 };
10264
10265 struct mlx5_ifc_uctx_bits {
10266         u8         cap[0x20];
10267
10268         u8         reserved_at_20[0x160];
10269 };
10270
10271 struct mlx5_ifc_sw_icm_bits {
10272         u8         modify_field_select[0x40];
10273
10274         u8         reserved_at_40[0x18];
10275         u8         log_sw_icm_size[0x8];
10276
10277         u8         reserved_at_60[0x20];
10278
10279         u8         sw_icm_start_addr[0x40];
10280
10281         u8         reserved_at_c0[0x140];
10282 };
10283
10284 struct mlx5_ifc_geneve_tlv_option_bits {
10285         u8         modify_field_select[0x40];
10286
10287         u8         reserved_at_40[0x18];
10288         u8         geneve_option_fte_index[0x8];
10289
10290         u8         option_class[0x10];
10291         u8         option_type[0x8];
10292         u8         reserved_at_78[0x3];
10293         u8         option_data_length[0x5];
10294
10295         u8         reserved_at_80[0x180];
10296 };
10297
10298 struct mlx5_ifc_create_umem_in_bits {
10299         u8         opcode[0x10];
10300         u8         uid[0x10];
10301
10302         u8         reserved_at_20[0x10];
10303         u8         op_mod[0x10];
10304
10305         u8         reserved_at_40[0x40];
10306
10307         struct mlx5_ifc_umem_bits  umem;
10308 };
10309
10310 struct mlx5_ifc_create_uctx_in_bits {
10311         u8         opcode[0x10];
10312         u8         reserved_at_10[0x10];
10313
10314         u8         reserved_at_20[0x10];
10315         u8         op_mod[0x10];
10316
10317         u8         reserved_at_40[0x40];
10318
10319         struct mlx5_ifc_uctx_bits  uctx;
10320 };
10321
10322 struct mlx5_ifc_destroy_uctx_in_bits {
10323         u8         opcode[0x10];
10324         u8         reserved_at_10[0x10];
10325
10326         u8         reserved_at_20[0x10];
10327         u8         op_mod[0x10];
10328
10329         u8         reserved_at_40[0x10];
10330         u8         uid[0x10];
10331
10332         u8         reserved_at_60[0x20];
10333 };
10334
10335 struct mlx5_ifc_create_sw_icm_in_bits {
10336         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10337         struct mlx5_ifc_sw_icm_bits                   sw_icm;
10338 };
10339
10340 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10341         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
10342         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
10343 };
10344
10345 struct mlx5_ifc_mtrc_string_db_param_bits {
10346         u8         string_db_base_address[0x20];
10347
10348         u8         reserved_at_20[0x8];
10349         u8         string_db_size[0x18];
10350 };
10351
10352 struct mlx5_ifc_mtrc_cap_bits {
10353         u8         trace_owner[0x1];
10354         u8         trace_to_memory[0x1];
10355         u8         reserved_at_2[0x4];
10356         u8         trc_ver[0x2];
10357         u8         reserved_at_8[0x14];
10358         u8         num_string_db[0x4];
10359
10360         u8         first_string_trace[0x8];
10361         u8         num_string_trace[0x8];
10362         u8         reserved_at_30[0x28];
10363
10364         u8         log_max_trace_buffer_size[0x8];
10365
10366         u8         reserved_at_60[0x20];
10367
10368         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10369
10370         u8         reserved_at_280[0x180];
10371 };
10372
10373 struct mlx5_ifc_mtrc_conf_bits {
10374         u8         reserved_at_0[0x1c];
10375         u8         trace_mode[0x4];
10376         u8         reserved_at_20[0x18];
10377         u8         log_trace_buffer_size[0x8];
10378         u8         trace_mkey[0x20];
10379         u8         reserved_at_60[0x3a0];
10380 };
10381
10382 struct mlx5_ifc_mtrc_stdb_bits {
10383         u8         string_db_index[0x4];
10384         u8         reserved_at_4[0x4];
10385         u8         read_size[0x18];
10386         u8         start_offset[0x20];
10387         u8         string_db_data[];
10388 };
10389
10390 struct mlx5_ifc_mtrc_ctrl_bits {
10391         u8         trace_status[0x2];
10392         u8         reserved_at_2[0x2];
10393         u8         arm_event[0x1];
10394         u8         reserved_at_5[0xb];
10395         u8         modify_field_select[0x10];
10396         u8         reserved_at_20[0x2b];
10397         u8         current_timestamp52_32[0x15];
10398         u8         current_timestamp31_0[0x20];
10399         u8         reserved_at_80[0x180];
10400 };
10401
10402 struct mlx5_ifc_host_params_context_bits {
10403         u8         host_number[0x8];
10404         u8         reserved_at_8[0x7];
10405         u8         host_pf_disabled[0x1];
10406         u8         host_num_of_vfs[0x10];
10407
10408         u8         host_total_vfs[0x10];
10409         u8         host_pci_bus[0x10];
10410
10411         u8         reserved_at_40[0x10];
10412         u8         host_pci_device[0x10];
10413
10414         u8         reserved_at_60[0x10];
10415         u8         host_pci_function[0x10];
10416
10417         u8         reserved_at_80[0x180];
10418 };
10419
10420 struct mlx5_ifc_query_esw_functions_in_bits {
10421         u8         opcode[0x10];
10422         u8         reserved_at_10[0x10];
10423
10424         u8         reserved_at_20[0x10];
10425         u8         op_mod[0x10];
10426
10427         u8         reserved_at_40[0x40];
10428 };
10429
10430 struct mlx5_ifc_query_esw_functions_out_bits {
10431         u8         status[0x8];
10432         u8         reserved_at_8[0x18];
10433
10434         u8         syndrome[0x20];
10435
10436         u8         reserved_at_40[0x40];
10437
10438         struct mlx5_ifc_host_params_context_bits host_params_context;
10439
10440         u8         reserved_at_280[0x180];
10441         u8         host_sf_enable[][0x40];
10442 };
10443
10444 struct mlx5_ifc_sf_partition_bits {
10445         u8         reserved_at_0[0x10];
10446         u8         log_num_sf[0x8];
10447         u8         log_sf_bar_size[0x8];
10448 };
10449
10450 struct mlx5_ifc_query_sf_partitions_out_bits {
10451         u8         status[0x8];
10452         u8         reserved_at_8[0x18];
10453
10454         u8         syndrome[0x20];
10455
10456         u8         reserved_at_40[0x18];
10457         u8         num_sf_partitions[0x8];
10458
10459         u8         reserved_at_60[0x20];
10460
10461         struct mlx5_ifc_sf_partition_bits sf_partition[];
10462 };
10463
10464 struct mlx5_ifc_query_sf_partitions_in_bits {
10465         u8         opcode[0x10];
10466         u8         reserved_at_10[0x10];
10467
10468         u8         reserved_at_20[0x10];
10469         u8         op_mod[0x10];
10470
10471         u8         reserved_at_40[0x40];
10472 };
10473
10474 struct mlx5_ifc_dealloc_sf_out_bits {
10475         u8         status[0x8];
10476         u8         reserved_at_8[0x18];
10477
10478         u8         syndrome[0x20];
10479
10480         u8         reserved_at_40[0x40];
10481 };
10482
10483 struct mlx5_ifc_dealloc_sf_in_bits {
10484         u8         opcode[0x10];
10485         u8         reserved_at_10[0x10];
10486
10487         u8         reserved_at_20[0x10];
10488         u8         op_mod[0x10];
10489
10490         u8         reserved_at_40[0x10];
10491         u8         function_id[0x10];
10492
10493         u8         reserved_at_60[0x20];
10494 };
10495
10496 struct mlx5_ifc_alloc_sf_out_bits {
10497         u8         status[0x8];
10498         u8         reserved_at_8[0x18];
10499
10500         u8         syndrome[0x20];
10501
10502         u8         reserved_at_40[0x40];
10503 };
10504
10505 struct mlx5_ifc_alloc_sf_in_bits {
10506         u8         opcode[0x10];
10507         u8         reserved_at_10[0x10];
10508
10509         u8         reserved_at_20[0x10];
10510         u8         op_mod[0x10];
10511
10512         u8         reserved_at_40[0x10];
10513         u8         function_id[0x10];
10514
10515         u8         reserved_at_60[0x20];
10516 };
10517
10518 struct mlx5_ifc_affiliated_event_header_bits {
10519         u8         reserved_at_0[0x10];
10520         u8         obj_type[0x10];
10521
10522         u8         obj_id[0x20];
10523 };
10524
10525 enum {
10526         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10527         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
10528 };
10529
10530 enum {
10531         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10532         MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
10533 };
10534
10535 enum {
10536         MLX5_IPSEC_OBJECT_ICV_LEN_16B,
10537         MLX5_IPSEC_OBJECT_ICV_LEN_12B,
10538         MLX5_IPSEC_OBJECT_ICV_LEN_8B,
10539 };
10540
10541 struct mlx5_ifc_ipsec_obj_bits {
10542         u8         modify_field_select[0x40];
10543         u8         full_offload[0x1];
10544         u8         reserved_at_41[0x1];
10545         u8         esn_en[0x1];
10546         u8         esn_overlap[0x1];
10547         u8         reserved_at_44[0x2];
10548         u8         icv_length[0x2];
10549         u8         reserved_at_48[0x4];
10550         u8         aso_return_reg[0x4];
10551         u8         reserved_at_50[0x10];
10552
10553         u8         esn_msb[0x20];
10554
10555         u8         reserved_at_80[0x8];
10556         u8         dekn[0x18];
10557
10558         u8         salt[0x20];
10559
10560         u8         implicit_iv[0x40];
10561
10562         u8         reserved_at_100[0x700];
10563 };
10564
10565 struct mlx5_ifc_create_ipsec_obj_in_bits {
10566         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10567         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10568 };
10569
10570 enum {
10571         MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
10572         MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
10573 };
10574
10575 struct mlx5_ifc_query_ipsec_obj_out_bits {
10576         struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
10577         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10578 };
10579
10580 struct mlx5_ifc_modify_ipsec_obj_in_bits {
10581         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10582         struct mlx5_ifc_ipsec_obj_bits ipsec_object;
10583 };
10584
10585 struct mlx5_ifc_encryption_key_obj_bits {
10586         u8         modify_field_select[0x40];
10587
10588         u8         reserved_at_40[0x14];
10589         u8         key_size[0x4];
10590         u8         reserved_at_58[0x4];
10591         u8         key_type[0x4];
10592
10593         u8         reserved_at_60[0x8];
10594         u8         pd[0x18];
10595
10596         u8         reserved_at_80[0x180];
10597         u8         key[8][0x20];
10598
10599         u8         reserved_at_300[0x500];
10600 };
10601
10602 struct mlx5_ifc_create_encryption_key_in_bits {
10603         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10604         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10605 };
10606
10607 enum {
10608         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10609         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10610 };
10611
10612 enum {
10613         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
10614         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
10615 };
10616
10617 struct mlx5_ifc_tls_static_params_bits {
10618         u8         const_2[0x2];
10619         u8         tls_version[0x4];
10620         u8         const_1[0x2];
10621         u8         reserved_at_8[0x14];
10622         u8         encryption_standard[0x4];
10623
10624         u8         reserved_at_20[0x20];
10625
10626         u8         initial_record_number[0x40];
10627
10628         u8         resync_tcp_sn[0x20];
10629
10630         u8         gcm_iv[0x20];
10631
10632         u8         implicit_iv[0x40];
10633
10634         u8         reserved_at_100[0x8];
10635         u8         dek_index[0x18];
10636
10637         u8         reserved_at_120[0xe0];
10638 };
10639
10640 struct mlx5_ifc_tls_progress_params_bits {
10641         u8         reserved_at_0[0x8];
10642         u8         tisn[0x18];
10643
10644         u8         next_record_tcp_sn[0x20];
10645
10646         u8         hw_resync_tcp_sn[0x20];
10647
10648         u8         record_tracker_state[0x2];
10649         u8         auth_state[0x2];
10650         u8         reserved_at_64[0x4];
10651         u8         hw_offset_record_number[0x18];
10652 };
10653
10654 #endif /* MLX5_IFC_H */