2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
45 #include <linux/mlx5/device.h>
46 #include <linux/mlx5/doorbell.h>
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
64 CMD_STATUS_SUCCESS = 0,
70 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SYNC_UMR = 4,
80 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
102 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
103 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
104 MLX5_CMD_OP_INIT_HCA = 0x102,
105 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
106 MLX5_CMD_OP_ENABLE_HCA = 0x104,
107 MLX5_CMD_OP_DISABLE_HCA = 0x105,
108 MLX5_CMD_OP_QUERY_PAGES = 0x107,
109 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
110 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
112 MLX5_CMD_OP_CREATE_MKEY = 0x200,
113 MLX5_CMD_OP_QUERY_MKEY = 0x201,
114 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
115 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
117 MLX5_CMD_OP_CREATE_EQ = 0x301,
118 MLX5_CMD_OP_DESTROY_EQ = 0x302,
119 MLX5_CMD_OP_QUERY_EQ = 0x303,
121 MLX5_CMD_OP_CREATE_CQ = 0x400,
122 MLX5_CMD_OP_DESTROY_CQ = 0x401,
123 MLX5_CMD_OP_QUERY_CQ = 0x402,
124 MLX5_CMD_OP_MODIFY_CQ = 0x403,
126 MLX5_CMD_OP_CREATE_QP = 0x500,
127 MLX5_CMD_OP_DESTROY_QP = 0x501,
128 MLX5_CMD_OP_RST2INIT_QP = 0x502,
129 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
130 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
131 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
132 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
133 MLX5_CMD_OP_2ERR_QP = 0x507,
134 MLX5_CMD_OP_RTS2SQD_QP = 0x508,
135 MLX5_CMD_OP_SQD2RTS_QP = 0x509,
136 MLX5_CMD_OP_2RST_QP = 0x50a,
137 MLX5_CMD_OP_QUERY_QP = 0x50b,
138 MLX5_CMD_OP_CONF_SQP = 0x50c,
139 MLX5_CMD_OP_MAD_IFC = 0x50d,
140 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
141 MLX5_CMD_OP_SUSPEND_QP = 0x50f,
142 MLX5_CMD_OP_UNSUSPEND_QP = 0x510,
143 MLX5_CMD_OP_SQD2SQD_QP = 0x511,
144 MLX5_CMD_OP_ALLOC_QP_COUNTER_SET = 0x512,
145 MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET = 0x513,
146 MLX5_CMD_OP_QUERY_QP_COUNTER_SET = 0x514,
148 MLX5_CMD_OP_CREATE_PSV = 0x600,
149 MLX5_CMD_OP_DESTROY_PSV = 0x601,
150 MLX5_CMD_OP_QUERY_PSV = 0x602,
151 MLX5_CMD_OP_QUERY_SIG_RULE_TABLE = 0x603,
152 MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE = 0x604,
154 MLX5_CMD_OP_CREATE_SRQ = 0x700,
155 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
156 MLX5_CMD_OP_QUERY_SRQ = 0x702,
157 MLX5_CMD_OP_ARM_RQ = 0x703,
158 MLX5_CMD_OP_RESIZE_SRQ = 0x704,
160 MLX5_CMD_OP_ALLOC_PD = 0x800,
161 MLX5_CMD_OP_DEALLOC_PD = 0x801,
162 MLX5_CMD_OP_ALLOC_UAR = 0x802,
163 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
165 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
166 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
169 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
170 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
172 MLX5_CMD_OP_ACCESS_REG = 0x805,
173 MLX5_CMD_OP_MAX = 0x810,
177 MLX5_REG_PCAP = 0x5001,
178 MLX5_REG_PMTU = 0x5003,
179 MLX5_REG_PTYS = 0x5004,
180 MLX5_REG_PAOS = 0x5006,
181 MLX5_REG_PMAOS = 0x5012,
182 MLX5_REG_PUDE = 0x5009,
183 MLX5_REG_PMPE = 0x5010,
184 MLX5_REG_PELC = 0x500e,
185 MLX5_REG_PMLP = 0, /* TBD */
186 MLX5_REG_NODE_DESC = 0x6001,
187 MLX5_REG_HOST_ENDIANNESS = 0x7004,
196 struct mlx5_field_desc {
201 struct mlx5_rsc_debug {
202 struct mlx5_core_dev *dev;
204 enum dbg_rsc_type type;
206 struct mlx5_field_desc fields[0];
209 enum mlx5_dev_event {
210 MLX5_DEV_EVENT_SYS_ERROR,
211 MLX5_DEV_EVENT_PORT_UP,
212 MLX5_DEV_EVENT_PORT_DOWN,
213 MLX5_DEV_EVENT_PORT_INITIALIZED,
214 MLX5_DEV_EVENT_LID_CHANGE,
215 MLX5_DEV_EVENT_PKEY_CHANGE,
216 MLX5_DEV_EVENT_GUID_CHANGE,
217 MLX5_DEV_EVENT_CLIENT_REREG,
220 struct mlx5_uuar_info {
221 struct mlx5_uar *uars;
223 int num_low_latency_uuars;
224 unsigned long *bitmap;
229 * protect uuar allocation data structs
237 void __iomem *regreg;
239 struct mlx5_uar *uar;
240 unsigned long offset;
242 /* protect blue flame buffer selection when needed
246 /* serialize 64 bit writes when done as two 32 bit accesses
252 struct mlx5_cmd_first {
256 struct mlx5_cmd_msg {
257 struct list_head list;
258 struct cache_ent *cache;
260 struct mlx5_cmd_first first;
261 struct mlx5_cmd_mailbox *next;
264 struct mlx5_cmd_debug {
265 struct dentry *dbg_root;
266 struct dentry *dbg_in;
267 struct dentry *dbg_out;
268 struct dentry *dbg_outlen;
269 struct dentry *dbg_status;
270 struct dentry *dbg_run;
279 /* protect block chain allocations
282 struct list_head head;
285 struct cmd_msg_cache {
286 struct cache_ent large;
287 struct cache_ent med;
291 struct mlx5_cmd_stats {
296 struct dentry *count;
297 /* protect command average calculations */
311 /* protect command queue allocations
313 spinlock_t alloc_lock;
315 /* protect token allocations
317 spinlock_t token_lock;
319 unsigned long bitmask;
320 char wq_name[MLX5_CMD_WQ_MAX_NAME];
321 struct workqueue_struct *wq;
322 struct semaphore sem;
323 struct semaphore pages_sem;
325 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
326 struct pci_pool *pool;
327 struct mlx5_cmd_debug dbg;
328 struct cmd_msg_cache cache;
329 int checksum_disabled;
330 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
333 struct mlx5_port_caps {
350 u16 stat_rate_support;
357 int bf_regs_per_page;
358 struct mlx5_port_caps port[MLX5_MAX_PORTS];
359 u8 ext_port_cap[MLX5_MAX_PORTS];
362 u8 local_ca_ack_delay;
368 struct mlx5_cmd_mailbox {
371 struct mlx5_cmd_mailbox *next;
374 struct mlx5_buf_list {
380 struct mlx5_buf_list direct;
381 struct mlx5_buf_list *page_list;
389 struct mlx5_core_dev *dev;
390 __be32 __iomem *doorbell;
398 char name[MLX5_MAX_EQ_NAME];
399 struct list_head list;
401 struct mlx5_rsc_debug *dbg;
405 struct mlx5_core_mr {
413 struct mlx5_core_srq {
417 int max_avail_gather;
419 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
422 struct completion free;
425 struct mlx5_eq_table {
426 void __iomem *update_ci;
427 void __iomem *update_arm_ci;
428 struct list_head *comp_eq_head;
429 struct mlx5_eq pages_eq;
430 struct mlx5_eq async_eq;
431 struct mlx5_eq cmd_eq;
432 struct msix_entry *msix_arr;
433 int num_comp_vectors;
441 struct list_head bf_list;
442 unsigned free_bf_bmap;
443 void __iomem *wc_map;
448 struct mlx5_core_health {
449 struct health_buffer __iomem *health;
450 __be32 __iomem *health_counter;
451 struct timer_list timer;
452 struct list_head list;
457 struct mlx5_cq_table {
458 /* protect radix tree
461 struct radix_tree_root tree;
464 struct mlx5_qp_table {
465 /* protect radix tree
468 struct radix_tree_root tree;
471 struct mlx5_srq_table {
472 /* protect radix tree
475 struct radix_tree_root tree;
479 char name[MLX5_MAX_NAME_LEN];
480 struct mlx5_eq_table eq_table;
481 struct mlx5_uuar_info uuari;
482 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
485 struct workqueue_struct *pg_wq;
486 struct rb_root page_root;
489 struct list_head free_list;
491 struct mlx5_core_health health;
493 struct mlx5_srq_table srq_table;
495 /* start: qp staff */
496 struct mlx5_qp_table qp_table;
497 struct dentry *qp_debugfs;
498 struct dentry *eq_debugfs;
499 struct dentry *cq_debugfs;
500 struct dentry *cmdif_debugfs;
503 /* start: cq staff */
504 struct mlx5_cq_table cq_table;
507 /* start: alloc staff */
508 struct mutex pgdir_mutex;
509 struct list_head pgdir_list;
510 /* end: alloc staff */
511 struct dentry *dbg_root;
513 /* protect mkey key part */
514 spinlock_t mkey_lock;
518 struct mlx5_core_dev {
519 struct pci_dev *pdev;
521 char board_id[MLX5_BOARD_ID_LEN];
523 struct mlx5_caps caps;
524 phys_addr_t iseg_base;
525 struct mlx5_init_seg __iomem *iseg;
526 void (*event) (struct mlx5_core_dev *dev,
527 enum mlx5_dev_event event,
529 struct mlx5_priv priv;
530 struct mlx5_profile *profile;
537 struct mlx5_db_pgdir *pgdir;
538 struct mlx5_ib_user_db_page *user_page;
545 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
549 MLX5_COMP_EQ_SIZE = 1024,
552 struct mlx5_db_pgdir {
553 struct list_head list;
554 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
559 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
561 struct mlx5_cmd_work_ent {
562 struct mlx5_cmd_msg *in;
563 struct mlx5_cmd_msg *out;
566 mlx5_cmd_cbk_t callback;
569 struct completion done;
570 struct mlx5_cmd *cmd;
571 struct work_struct work;
572 struct mlx5_cmd_layout *lay;
587 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
589 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
590 return buf->direct.buf + offset;
592 return buf->page_list[offset >> PAGE_SHIFT].buf +
593 (offset & (PAGE_SIZE - 1));
596 extern struct workqueue_struct *mlx5_core_wq;
598 #define STRUCT_FIELD(header, field) \
599 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
600 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
603 size_t struct_offset_bytes;
604 size_t struct_size_bytes;
609 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
611 return pci_get_drvdata(pdev);
614 extern struct dentry *mlx5_debugfs_root;
616 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
618 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
621 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
623 return ioread32be(&dev->iseg->fw_rev) >> 16;
626 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
628 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
631 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
633 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
636 static inline void *mlx5_vzalloc(unsigned long size)
640 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
646 static inline void mlx5_vfree(const void *addr)
648 if (addr && is_vmalloc_addr(addr))
654 int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev);
655 void mlx5_dev_cleanup(struct mlx5_core_dev *dev);
656 int mlx5_cmd_init(struct mlx5_core_dev *dev);
657 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
658 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
659 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
660 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
661 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
663 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
664 void *out, int out_size, mlx5_cmd_cbk_t callback,
666 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
667 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
668 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
669 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
670 void mlx5_health_cleanup(void);
671 void __init mlx5_health_init(void);
672 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
673 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
674 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
675 struct mlx5_buf *buf);
676 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
677 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
678 gfp_t flags, int npages);
679 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
680 struct mlx5_cmd_mailbox *head);
681 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
682 struct mlx5_create_srq_mbox_in *in, int inlen);
683 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
684 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
685 struct mlx5_query_srq_mbox_out *out);
686 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
687 u16 lwm, int is_srq);
688 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
689 struct mlx5_create_mkey_mbox_in *in, int inlen,
690 mlx5_cmd_cbk_t callback, void *context,
691 struct mlx5_create_mkey_mbox_out *out);
692 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
693 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
694 struct mlx5_query_mkey_mbox_out *out, int outlen);
695 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
697 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
698 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
699 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
700 u16 opmod, int port);
701 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
702 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
703 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
704 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
705 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
707 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
708 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
709 void mlx5_register_debugfs(void);
710 void mlx5_unregister_debugfs(void);
711 int mlx5_eq_init(struct mlx5_core_dev *dev);
712 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
713 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
714 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
715 void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type);
716 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
717 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
718 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
719 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
720 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
721 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
722 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
723 int mlx5_start_eqs(struct mlx5_core_dev *dev);
724 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
725 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
726 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
728 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
729 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
730 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
731 int size_in, void *data_out, int size_out,
732 u16 reg_num, int arg, int write);
733 int mlx5_set_port_caps(struct mlx5_core_dev *dev, int port_num, u32 caps);
735 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
736 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
737 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
738 struct mlx5_query_eq_mbox_out *out, int outlen);
739 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
740 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
741 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
742 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
743 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
744 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
746 const char *mlx5_command_str(int command);
747 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
748 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
750 static inline u32 mlx5_mkey_to_idx(u32 mkey)
755 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
757 return mkey_idx << 8;
760 static inline u8 mlx5_mkey_variant(u32 mkey)
766 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
767 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
771 MAX_MR_CACHE_ENTRIES = 16,
774 struct mlx5_profile {
780 } mr_cache[MAX_MR_CACHE_ENTRIES];
783 #endif /* MLX5_DRIVER_H */