2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/spinlock_types.h>
40 #include <linux/semaphore.h>
41 #include <linux/slab.h>
42 #include <linux/vmalloc.h>
43 #include <linux/radix-tree.h>
45 #include <linux/mlx5/device.h>
46 #include <linux/mlx5/doorbell.h>
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
54 /* one minute for the sake of bringup. Generally, commands must always
55 * complete and we may need to increase this timeout value
57 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
58 MLX5_CMD_WQ_MAX_NAME = 32,
64 CMD_STATUS_SUCCESS = 0,
70 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SYNC_UMR = 4,
80 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
87 MLX5_MAX_IRQ_NAME = 32
91 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
92 MLX5_ATOMIC_MODE_CX = 2 << 16,
93 MLX5_ATOMIC_MODE_8B = 3 << 16,
94 MLX5_ATOMIC_MODE_16B = 4 << 16,
95 MLX5_ATOMIC_MODE_32B = 5 << 16,
96 MLX5_ATOMIC_MODE_64B = 6 << 16,
97 MLX5_ATOMIC_MODE_128B = 7 << 16,
98 MLX5_ATOMIC_MODE_256B = 8 << 16,
102 MLX5_REG_PCAP = 0x5001,
103 MLX5_REG_PMTU = 0x5003,
104 MLX5_REG_PTYS = 0x5004,
105 MLX5_REG_PAOS = 0x5006,
106 MLX5_REG_PFCC = 0x5007,
107 MLX5_REG_PPCNT = 0x5008,
108 MLX5_REG_PMAOS = 0x5012,
109 MLX5_REG_PUDE = 0x5009,
110 MLX5_REG_PMPE = 0x5010,
111 MLX5_REG_PELC = 0x500e,
112 MLX5_REG_PVLC = 0x500f,
113 MLX5_REG_PMLP = 0, /* TBD */
114 MLX5_REG_NODE_DESC = 0x6001,
115 MLX5_REG_HOST_ENDIANNESS = 0x7004,
119 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
120 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
123 enum mlx5_page_fault_resume_flags {
124 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
125 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
126 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
127 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
136 struct mlx5_field_desc {
141 struct mlx5_rsc_debug {
142 struct mlx5_core_dev *dev;
144 enum dbg_rsc_type type;
146 struct mlx5_field_desc fields[0];
149 enum mlx5_dev_event {
150 MLX5_DEV_EVENT_SYS_ERROR,
151 MLX5_DEV_EVENT_PORT_UP,
152 MLX5_DEV_EVENT_PORT_DOWN,
153 MLX5_DEV_EVENT_PORT_INITIALIZED,
154 MLX5_DEV_EVENT_LID_CHANGE,
155 MLX5_DEV_EVENT_PKEY_CHANGE,
156 MLX5_DEV_EVENT_GUID_CHANGE,
157 MLX5_DEV_EVENT_CLIENT_REREG,
160 enum mlx5_port_status {
165 struct mlx5_uuar_info {
166 struct mlx5_uar *uars;
168 int num_low_latency_uuars;
169 unsigned long *bitmap;
174 * protect uuar allocation data structs
182 void __iomem *regreg;
184 struct mlx5_uar *uar;
185 unsigned long offset;
187 /* protect blue flame buffer selection when needed
191 /* serialize 64 bit writes when done as two 32 bit accesses
197 struct mlx5_cmd_first {
201 struct mlx5_cmd_msg {
202 struct list_head list;
203 struct cache_ent *cache;
205 struct mlx5_cmd_first first;
206 struct mlx5_cmd_mailbox *next;
209 struct mlx5_cmd_debug {
210 struct dentry *dbg_root;
211 struct dentry *dbg_in;
212 struct dentry *dbg_out;
213 struct dentry *dbg_outlen;
214 struct dentry *dbg_status;
215 struct dentry *dbg_run;
224 /* protect block chain allocations
227 struct list_head head;
230 struct cmd_msg_cache {
231 struct cache_ent large;
232 struct cache_ent med;
236 struct mlx5_cmd_stats {
241 struct dentry *count;
242 /* protect command average calculations */
248 dma_addr_t alloc_dma;
259 /* protect command queue allocations
261 spinlock_t alloc_lock;
263 /* protect token allocations
265 spinlock_t token_lock;
267 unsigned long bitmask;
268 char wq_name[MLX5_CMD_WQ_MAX_NAME];
269 struct workqueue_struct *wq;
270 struct semaphore sem;
271 struct semaphore pages_sem;
273 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
274 struct pci_pool *pool;
275 struct mlx5_cmd_debug dbg;
276 struct cmd_msg_cache cache;
277 int checksum_disabled;
278 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
281 struct mlx5_port_caps {
287 struct mlx5_cmd_mailbox {
290 struct mlx5_cmd_mailbox *next;
293 struct mlx5_buf_list {
299 struct mlx5_buf_list direct;
306 struct mlx5_core_dev *dev;
307 __be32 __iomem *doorbell;
315 struct list_head list;
317 struct mlx5_rsc_debug *dbg;
320 struct mlx5_core_psv {
332 struct mlx5_core_sig_ctx {
333 struct mlx5_core_psv psv_memory;
334 struct mlx5_core_psv psv_wire;
335 struct ib_sig_err err_item;
336 bool sig_status_checked;
341 struct mlx5_core_mr {
349 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
350 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
351 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
356 struct mlx5_core_rsc_common {
357 enum mlx5_res_type res;
359 struct completion free;
362 struct mlx5_core_srq {
363 struct mlx5_core_rsc_common common; /* must be first */
367 int max_avail_gather;
369 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
372 struct completion free;
375 struct mlx5_eq_table {
376 void __iomem *update_ci;
377 void __iomem *update_arm_ci;
378 struct list_head comp_eqs_list;
379 struct mlx5_eq pages_eq;
380 struct mlx5_eq async_eq;
381 struct mlx5_eq cmd_eq;
382 int num_comp_vectors;
390 struct list_head bf_list;
391 unsigned free_bf_bmap;
392 void __iomem *bf_map;
397 struct mlx5_core_health {
398 struct health_buffer __iomem *health;
399 __be32 __iomem *health_counter;
400 struct timer_list timer;
404 struct workqueue_struct *wq;
405 struct work_struct work;
408 struct mlx5_cq_table {
409 /* protect radix tree
412 struct radix_tree_root tree;
415 struct mlx5_qp_table {
416 /* protect radix tree
419 struct radix_tree_root tree;
422 struct mlx5_srq_table {
423 /* protect radix tree
426 struct radix_tree_root tree;
429 struct mlx5_mr_table {
430 /* protect radix tree
433 struct radix_tree_root tree;
436 struct mlx5_vf_context {
440 struct mlx5_core_sriov {
441 struct mlx5_vf_context *vfs_ctx;
446 struct mlx5_irq_info {
448 char name[MLX5_MAX_IRQ_NAME];
454 char name[MLX5_MAX_NAME_LEN];
455 struct mlx5_eq_table eq_table;
456 struct msix_entry *msix_arr;
457 struct mlx5_irq_info *irq_info;
458 struct mlx5_uuar_info uuari;
459 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
461 struct io_mapping *bf_mapping;
464 struct workqueue_struct *pg_wq;
465 struct rb_root page_root;
468 struct list_head free_list;
471 struct mlx5_core_health health;
473 struct mlx5_srq_table srq_table;
475 /* start: qp staff */
476 struct mlx5_qp_table qp_table;
477 struct dentry *qp_debugfs;
478 struct dentry *eq_debugfs;
479 struct dentry *cq_debugfs;
480 struct dentry *cmdif_debugfs;
483 /* start: cq staff */
484 struct mlx5_cq_table cq_table;
487 /* start: mr staff */
488 struct mlx5_mr_table mr_table;
491 /* start: alloc staff */
492 /* protect buffer alocation according to numa node */
493 struct mutex alloc_mutex;
496 struct mutex pgdir_mutex;
497 struct list_head pgdir_list;
498 /* end: alloc staff */
499 struct dentry *dbg_root;
501 /* protect mkey key part */
502 spinlock_t mkey_lock;
505 struct list_head dev_list;
506 struct list_head ctx_list;
509 struct mlx5_eswitch *eswitch;
510 struct mlx5_core_sriov sriov;
511 unsigned long pci_dev_data;
512 struct mlx5_flow_root_namespace *root_ns;
513 struct mlx5_flow_root_namespace *fdb_root_ns;
516 enum mlx5_device_state {
517 MLX5_DEVICE_STATE_UP,
518 MLX5_DEVICE_STATE_INTERNAL_ERROR,
521 enum mlx5_interface_state {
522 MLX5_INTERFACE_STATE_DOWN,
523 MLX5_INTERFACE_STATE_UP,
526 enum mlx5_pci_status {
527 MLX5_PCI_STATUS_DISABLED,
528 MLX5_PCI_STATUS_ENABLED,
531 struct mlx5_core_dev {
532 struct pci_dev *pdev;
534 struct mutex pci_status_mutex;
535 enum mlx5_pci_status pci_status;
537 char board_id[MLX5_BOARD_ID_LEN];
539 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
540 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
541 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
542 phys_addr_t iseg_base;
543 struct mlx5_init_seg __iomem *iseg;
544 enum mlx5_device_state state;
545 /* sync interface state */
546 struct mutex intf_state_mutex;
547 enum mlx5_interface_state interface_state;
548 void (*event) (struct mlx5_core_dev *dev,
549 enum mlx5_dev_event event,
550 unsigned long param);
551 struct mlx5_priv priv;
552 struct mlx5_profile *profile;
560 struct mlx5_db_pgdir *pgdir;
561 struct mlx5_ib_user_db_page *user_page;
568 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
572 MLX5_COMP_EQ_SIZE = 1024,
576 MLX5_PTYS_IB = 1 << 0,
577 MLX5_PTYS_EN = 1 << 2,
580 struct mlx5_db_pgdir {
581 struct list_head list;
582 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
587 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
589 struct mlx5_cmd_work_ent {
590 struct mlx5_cmd_msg *in;
591 struct mlx5_cmd_msg *out;
594 mlx5_cmd_cbk_t callback;
597 struct completion done;
598 struct mlx5_cmd *cmd;
599 struct work_struct work;
600 struct mlx5_cmd_layout *lay;
615 enum port_state_policy {
619 enum phy_port_state {
623 struct mlx5_hca_vport_context {
628 enum port_state_policy policy;
629 enum phy_port_state phys_state;
630 enum ib_port_state vport_state;
631 u8 port_physical_state;
640 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
645 u16 qkey_violation_counter;
646 u16 pkey_violation_counter;
650 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
652 return buf->direct.buf + offset;
655 extern struct workqueue_struct *mlx5_core_wq;
657 #define STRUCT_FIELD(header, field) \
658 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
659 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
661 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
663 return pci_get_drvdata(pdev);
666 extern struct dentry *mlx5_debugfs_root;
668 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
670 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
673 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
675 return ioread32be(&dev->iseg->fw_rev) >> 16;
678 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
680 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
683 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
685 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
688 static inline void *mlx5_vzalloc(unsigned long size)
692 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
698 static inline u32 mlx5_base_mkey(const u32 key)
700 return key & 0xffffff00u;
703 int mlx5_cmd_init(struct mlx5_core_dev *dev);
704 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
705 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
706 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
707 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
708 int mlx5_cmd_status_to_err_v2(void *ptr);
709 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
710 enum mlx5_cap_mode cap_mode);
711 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
713 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
714 void *out, int out_size, mlx5_cmd_cbk_t callback,
716 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
717 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
718 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
719 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
720 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
721 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
722 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
723 int mlx5_health_init(struct mlx5_core_dev *dev);
724 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
725 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
726 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
727 struct mlx5_buf *buf, int node);
728 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
729 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
730 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
731 gfp_t flags, int npages);
732 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
733 struct mlx5_cmd_mailbox *head);
734 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
735 struct mlx5_create_srq_mbox_in *in, int inlen,
737 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
738 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
739 struct mlx5_query_srq_mbox_out *out);
740 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
741 u16 lwm, int is_srq);
742 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
743 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
744 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
745 struct mlx5_create_mkey_mbox_in *in, int inlen,
746 mlx5_cmd_cbk_t callback, void *context,
747 struct mlx5_create_mkey_mbox_out *out);
748 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
749 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
750 struct mlx5_query_mkey_mbox_out *out, int outlen);
751 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
753 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
754 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
755 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
757 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
758 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
759 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
760 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
761 int mlx5_sriov_init(struct mlx5_core_dev *dev);
762 int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
763 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
765 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
766 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
767 void mlx5_register_debugfs(void);
768 void mlx5_unregister_debugfs(void);
769 int mlx5_eq_init(struct mlx5_core_dev *dev);
770 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
771 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
772 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
773 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
774 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
775 void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
777 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
778 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
779 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec);
780 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
781 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
782 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
783 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
784 int mlx5_start_eqs(struct mlx5_core_dev *dev);
785 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
786 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
788 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
789 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
791 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
792 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
793 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
794 int size_in, void *data_out, int size_out,
795 u16 reg_num, int arg, int write);
797 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
798 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
799 int ptys_size, int proto_mask, u8 local_port);
800 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
801 u32 *proto_cap, int proto_mask);
802 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
803 u32 *proto_admin, int proto_mask);
804 int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
805 u8 *link_width_oper, u8 local_port);
806 int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
807 u8 *proto_oper, int proto_mask,
809 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
811 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
812 enum mlx5_port_status status);
813 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
814 enum mlx5_port_status *status);
816 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
817 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
818 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
821 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
822 u8 *vl_hw_cap, u8 local_port);
824 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
825 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
826 u32 *rx_pause, u32 *tx_pause);
828 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
829 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
830 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
831 struct mlx5_query_eq_mbox_out *out, int outlen);
832 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
833 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
834 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
835 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
836 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
837 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
839 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
841 const char *mlx5_command_str(int command);
842 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
843 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
844 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
845 int npsvs, u32 *sig_index);
846 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
847 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
848 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
849 struct mlx5_odp_caps *odp_caps);
851 static inline int fw_initializing(struct mlx5_core_dev *dev)
853 return ioread32be(&dev->iseg->initializing) >> 31;
856 static inline u32 mlx5_mkey_to_idx(u32 mkey)
861 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
863 return mkey_idx << 8;
866 static inline u8 mlx5_mkey_variant(u32 mkey)
872 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
873 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
877 MAX_MR_CACHE_ENTRIES = 16,
881 MLX5_INTERFACE_PROTOCOL_IB = 0,
882 MLX5_INTERFACE_PROTOCOL_ETH = 1,
885 struct mlx5_interface {
886 void * (*add)(struct mlx5_core_dev *dev);
887 void (*remove)(struct mlx5_core_dev *dev, void *context);
888 void (*event)(struct mlx5_core_dev *dev, void *context,
889 enum mlx5_dev_event event, unsigned long param);
890 void * (*get_dev)(void *context);
892 struct list_head list;
895 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
896 int mlx5_register_interface(struct mlx5_interface *intf);
897 void mlx5_unregister_interface(struct mlx5_interface *intf);
898 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
900 struct mlx5_profile {
906 } mr_cache[MAX_MR_CACHE_ENTRIES];
910 MLX5_PCI_DEV_IS_VF = 1 << 0,
913 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
915 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
918 static inline int mlx5_get_gid_table_len(u16 param)
921 pr_warn("gid table length is zero\n");
925 return 8 * (1 << param);
929 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
932 #endif /* MLX5_DRIVER_H */