2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
60 #define MLX5_ADEV_NAME "mlx5_core"
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
65 MLX5_BOARD_ID_LEN = 64,
69 MLX5_CMD_WQ_MAX_NAME = 32,
75 CMD_STATUS_SUCCESS = 0,
81 MLX5_SQP_IEEE_1588 = 2,
83 MLX5_SQP_SYNC_UMR = 4,
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
159 enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
164 enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
176 enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
189 enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
196 enum mlx5_coredev_type {
202 struct mlx5_field_desc {
206 struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
209 enum dbg_rsc_type type;
211 struct mlx5_field_desc fields[];
214 enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
219 enum mlx5_port_status {
224 enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
227 MLX5_CMDIF_STATE_DOWN,
230 struct mlx5_cmd_first {
234 struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
242 struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
251 struct cmd_msg_cache {
252 /* protect block chain allocations
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
261 MLX5_NUM_COMMAND_CACHES = 5,
264 struct mlx5_cmd_stats {
268 /* protect command average calculations */
275 enum mlx5_cmdif_state state;
277 dma_addr_t alloc_dma;
288 /* protect command queue allocations
290 spinlock_t alloc_lock;
292 /* protect token allocations
294 spinlock_t token_lock;
296 unsigned long bitmask;
297 char wq_name[MLX5_CMD_WQ_MAX_NAME];
298 struct workqueue_struct *wq;
299 struct semaphore sem;
300 struct semaphore pages_sem;
303 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
304 struct dma_pool *pool;
305 struct mlx5_cmd_debug dbg;
306 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
307 int checksum_disabled;
308 struct mlx5_cmd_stats *stats;
311 struct mlx5_cmd_mailbox {
314 struct mlx5_cmd_mailbox *next;
317 struct mlx5_buf_list {
322 struct mlx5_frag_buf {
323 struct mlx5_buf_list *frags;
329 struct mlx5_frag_buf_ctrl {
330 struct mlx5_buf_list *frags;
339 struct mlx5_core_psv {
351 struct mlx5_core_sig_ctx {
352 struct mlx5_core_psv psv_memory;
353 struct mlx5_core_psv psv_wire;
354 struct ib_sig_err err_item;
355 bool sig_status_checked;
363 MLX5_MKEY_INDIRECT_DEVX,
366 struct mlx5_core_mkey {
372 struct wait_queue_head wait;
376 #define MLX5_24BIT_MASK ((1 << 24) - 1)
379 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
380 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
381 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
385 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
388 struct mlx5_core_rsc_common {
389 enum mlx5_res_type res;
391 struct completion free;
394 struct mlx5_uars_page {
398 struct list_head list;
400 unsigned long *reg_bitmap; /* for non fast path bf regs */
401 unsigned long *fp_bitmap;
402 unsigned int reg_avail;
403 unsigned int fp_avail;
404 struct kref ref_count;
405 struct mlx5_core_dev *mdev;
408 struct mlx5_bfreg_head {
409 /* protect blue flame registers allocations */
411 struct list_head list;
414 struct mlx5_bfreg_data {
415 struct mlx5_bfreg_head reg_head;
416 struct mlx5_bfreg_head wc_head;
419 struct mlx5_sq_bfreg {
421 struct mlx5_uars_page *up;
427 struct mlx5_core_health {
428 struct health_buffer __iomem *health;
429 __be32 __iomem *health_counter;
430 struct timer_list timer;
436 /* wq spinlock to synchronize draining */
438 struct workqueue_struct *wq;
440 struct work_struct fatal_report_work;
441 struct work_struct report_work;
442 struct devlink_health_reporter *fw_reporter;
443 struct devlink_health_reporter *fw_fatal_reporter;
444 struct delayed_work update_fw_log_ts_work;
447 struct mlx5_qp_table {
448 struct notifier_block nb;
450 /* protect radix tree
453 struct radix_tree_root tree;
456 struct mlx5_vf_context {
460 /* Valid bits are used to validate administrative guid only.
461 * Enabled after ndo_set_vf_guid
463 u8 port_guid_valid:1;
464 u8 node_guid_valid:1;
465 enum port_state_policy policy;
468 struct mlx5_core_sriov {
469 struct mlx5_vf_context *vfs_ctx;
474 struct mlx5_fc_pool {
475 struct mlx5_core_dev *dev;
476 struct mutex pool_lock; /* protects pool lists */
477 struct list_head fully_used;
478 struct list_head partially_used;
479 struct list_head unused;
485 struct mlx5_fc_stats {
486 spinlock_t counters_idr_lock; /* protects counters_idr */
487 struct idr counters_idr;
488 struct list_head counters;
489 struct llist_head addlist;
490 struct llist_head dellist;
492 struct workqueue_struct *wq;
493 struct delayed_work work;
494 unsigned long next_query;
495 unsigned long sampling_interval; /* jiffies */
497 struct mlx5_fc_pool fc_pool;
505 struct mlx5_fw_reset;
506 struct mlx5_eq_table;
507 struct mlx5_irq_table;
508 struct mlx5_vhca_state_notifier;
509 struct mlx5_sf_dev_table;
510 struct mlx5_sf_hw_table;
511 struct mlx5_sf_table;
513 struct mlx5_rate_limit {
519 struct mlx5_rl_entry {
520 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
527 struct mlx5_rl_table {
528 /* protect rate limit table */
529 struct mutex rl_lock;
533 struct mlx5_rl_entry *rl_entry;
537 struct mlx5_core_roce {
538 struct mlx5_flow_table *ft;
539 struct mlx5_flow_group *fg;
540 struct mlx5_flow_handle *allow_rule;
544 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
545 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
546 /* Set during device detach to block any further devices
547 * creation/deletion on drivers rescan. Unset during device attach.
549 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
553 struct auxiliary_device adev;
554 struct mlx5_core_dev *mdev;
560 /* IRQ table valid only for real pci devices PF or VF */
561 struct mlx5_irq_table *irq_table;
562 struct mlx5_eq_table *eq_table;
565 struct mlx5_nb pg_nb;
566 struct workqueue_struct *pg_wq;
567 struct xarray page_root_xa;
570 struct list_head free_list;
574 struct mlx5_core_health health;
575 struct list_head traps;
577 /* start: qp staff */
578 struct dentry *qp_debugfs;
579 struct dentry *eq_debugfs;
580 struct dentry *cq_debugfs;
581 struct dentry *cmdif_debugfs;
584 /* start: alloc staff */
585 /* protect buffer allocation according to numa node */
586 struct mutex alloc_mutex;
589 struct mutex pgdir_mutex;
590 struct list_head pgdir_list;
591 /* end: alloc staff */
592 struct dentry *dbg_root;
594 struct list_head ctx_list;
596 struct mlx5_adev **adev;
598 struct mlx5_events *events;
600 struct mlx5_flow_steering *steering;
601 struct mlx5_mpfs *mpfs;
602 struct mlx5_eswitch *eswitch;
603 struct mlx5_core_sriov sriov;
604 struct mlx5_lag *lag;
606 struct mlx5_devcom *devcom;
607 struct mlx5_fw_reset *fw_reset;
608 struct mlx5_core_roce roce;
609 struct mlx5_fc_stats fc_stats;
610 struct mlx5_rl_table rl_table;
611 struct mlx5_ft_pool *ft_pool;
613 struct mlx5_bfreg_data bfregs;
614 struct mlx5_uars_page *uar;
615 #ifdef CONFIG_MLX5_SF
616 struct mlx5_vhca_state_notifier *vhca_state_notifier;
617 struct mlx5_sf_dev_table *sf_dev_table;
618 struct mlx5_core_dev *parent_mdev;
620 #ifdef CONFIG_MLX5_SF_MANAGER
621 struct mlx5_sf_hw_table *sf_hw_table;
622 struct mlx5_sf_table *sf_table;
626 enum mlx5_device_state {
627 MLX5_DEVICE_STATE_UP = 1,
628 MLX5_DEVICE_STATE_INTERNAL_ERROR,
631 enum mlx5_interface_state {
632 MLX5_INTERFACE_STATE_UP = BIT(0),
635 enum mlx5_pci_status {
636 MLX5_PCI_STATUS_DISABLED,
637 MLX5_PCI_STATUS_ENABLED,
640 enum mlx5_pagefault_type_flags {
641 MLX5_PFAULT_REQUESTOR = 1 << 0,
642 MLX5_PFAULT_WRITE = 1 << 1,
643 MLX5_PFAULT_RDMA = 1 << 2,
647 /* protects tirs list changes while tirs refresh */
648 struct mutex list_lock;
649 struct list_head tirs_list;
653 struct mlx5e_resources {
654 struct mlx5e_hw_objs {
657 struct mlx5_core_mkey mkey;
658 struct mlx5_sq_bfreg bfreg;
660 struct devlink_port dl_port;
661 struct net_device *uplink_netdev;
664 enum mlx5_sw_icm_type {
665 MLX5_SW_ICM_TYPE_STEERING,
666 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
669 #define MLX5_MAX_RESERVED_GIDS 8
671 struct mlx5_rsvd_gids {
677 #define MAX_PIN_NUM 8
679 u8 pin_caps[MAX_PIN_NUM];
680 struct work_struct out_work;
681 u64 start[MAX_PIN_NUM];
686 struct cyclecounter cycles;
687 struct timecounter tc;
689 unsigned long overflow_period;
690 struct delayed_work overflow_work;
694 struct mlx5_nb pps_nb;
696 struct hwtstamp_config hwtstamp_config;
697 struct ptp_clock *ptp;
698 struct ptp_clock_info ptp_info;
699 struct mlx5_pps pps_info;
700 struct mlx5_timer timer;
704 struct mlx5_fw_tracer;
709 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
710 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
713 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
714 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
718 MR_CACHE_LAST_STD_ENTRY = 20,
719 MLX5_IMR_MTT_CACHE_ENTRY,
720 MLX5_IMR_KSM_CACHE_ENTRY,
724 struct mlx5_profile {
730 } mr_cache[MAX_MR_CACHE_ENTRIES];
733 struct mlx5_hca_cap {
734 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
735 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
738 struct mlx5_core_dev {
739 struct device *device;
740 enum mlx5_coredev_type coredev_type;
741 struct pci_dev *pdev;
743 struct mutex pci_status_mutex;
744 enum mlx5_pci_status pci_status;
746 char board_id[MLX5_BOARD_ID_LEN];
749 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
750 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
751 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
752 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
753 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
756 struct mlx5_timeouts *timeouts;
758 phys_addr_t iseg_base;
759 struct mlx5_init_seg __iomem *iseg;
760 phys_addr_t bar_addr;
761 enum mlx5_device_state state;
762 /* sync interface state */
763 struct mutex intf_state_mutex;
764 unsigned long intf_state;
765 struct mlx5_priv priv;
766 struct mlx5_profile profile;
768 struct mlx5e_resources mlx5e_res;
770 struct mlx5_vxlan *vxlan;
771 struct mlx5_geneve *geneve;
773 struct mlx5_rsvd_gids reserved_gids;
776 #ifdef CONFIG_MLX5_FPGA
777 struct mlx5_fpga_device *fpga;
779 #ifdef CONFIG_MLX5_ACCEL
780 const struct mlx5_accel_ipsec_ops *ipsec_ops;
782 struct mlx5_clock clock;
783 struct mlx5_ib_clock_info *clock_info;
784 struct mlx5_fw_tracer *tracer;
785 struct mlx5_rsc_dump *rsc_dump;
787 struct mlx5_hv_vhca *hv_vhca;
793 struct mlx5_db_pgdir *pgdir;
794 struct mlx5_ib_user_db_page *user_page;
801 MLX5_COMP_EQ_SIZE = 1024,
805 MLX5_PTYS_IB = 1 << 0,
806 MLX5_PTYS_EN = 1 << 2,
809 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
812 MLX5_CMD_ENT_STATE_PENDING_COMP,
815 struct mlx5_cmd_work_ent {
817 struct mlx5_cmd_msg *in;
818 struct mlx5_cmd_msg *out;
821 mlx5_cmd_cbk_t callback;
822 struct delayed_work cb_timeout_work;
825 struct completion handling;
826 struct completion done;
827 struct mlx5_cmd *cmd;
828 struct work_struct work;
829 struct mlx5_cmd_layout *lay;
838 /* Track the max comp handlers */
847 enum phy_port_state {
851 struct mlx5_hca_vport_context {
856 enum port_state_policy policy;
857 enum phy_port_state phys_state;
858 enum ib_port_state vport_state;
859 u8 port_physical_state;
868 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
873 u16 qkey_violation_counter;
874 u16 pkey_violation_counter;
878 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
880 return buf->frags->buf + offset;
883 #define STRUCT_FIELD(header, field) \
884 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
885 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
887 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
889 return pci_get_drvdata(pdev);
892 extern struct dentry *mlx5_debugfs_root;
894 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
896 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
899 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
901 return ioread32be(&dev->iseg->fw_rev) >> 16;
904 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
906 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
909 static inline u32 mlx5_base_mkey(const u32 key)
911 return key & 0xffffff00u;
914 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
916 return ((u32)1 << log_sz) << log_stride;
919 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
920 u8 log_stride, u8 log_sz,
922 struct mlx5_frag_buf_ctrl *fbc)
925 fbc->log_stride = log_stride;
926 fbc->log_sz = log_sz;
927 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
928 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
929 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
930 fbc->strides_offset = strides_offset;
933 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
934 u8 log_stride, u8 log_sz,
935 struct mlx5_frag_buf_ctrl *fbc)
937 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
940 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
945 ix += fbc->strides_offset;
946 frag = ix >> fbc->log_frag_strides;
948 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
952 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
954 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
956 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
960 CMD_ALLOWED_OPCODE_ALL,
963 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
964 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
965 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
967 struct mlx5_async_ctx {
968 struct mlx5_core_dev *dev;
969 atomic_t num_inflight;
970 struct wait_queue_head wait;
973 struct mlx5_async_work;
975 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
977 struct mlx5_async_work {
978 struct mlx5_async_ctx *ctx;
979 mlx5_async_cbk_t user_callback;
982 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
983 struct mlx5_async_ctx *ctx);
984 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
985 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
986 void *out, int out_size, mlx5_async_cbk_t callback,
987 struct mlx5_async_work *work);
989 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
992 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
994 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
995 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
998 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1000 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1001 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1004 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1005 void *out, int out_size);
1006 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
1007 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1009 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1010 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
1011 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
1012 void mlx5_health_flush(struct mlx5_core_dev *dev);
1013 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1014 int mlx5_health_init(struct mlx5_core_dev *dev);
1015 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1016 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1017 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1018 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1019 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
1020 int size, struct mlx5_frag_buf *buf);
1021 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1022 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1023 struct mlx5_frag_buf *buf, int node);
1024 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1025 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1026 gfp_t flags, int npages);
1027 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1028 struct mlx5_cmd_mailbox *head);
1029 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
1030 struct mlx5_core_mkey *mkey,
1031 u32 *in, int inlen);
1032 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
1033 struct mlx5_core_mkey *mkey);
1034 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
1035 u32 *out, int outlen);
1036 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1037 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1038 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1039 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1040 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1041 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1042 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1043 s32 npages, bool ec_function);
1044 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1045 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1046 void mlx5_register_debugfs(void);
1047 void mlx5_unregister_debugfs(void);
1049 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
1050 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1051 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1052 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1053 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1054 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1056 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1057 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1058 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1059 int size_in, void *data_out, int size_out,
1060 u16 reg_num, int arg, int write);
1062 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1063 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1065 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1067 const char *mlx5_command_str(int command);
1068 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1069 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1070 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1071 int npsvs, u32 *sig_index);
1072 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1073 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1074 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1075 struct mlx5_odp_caps *odp_caps);
1076 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1077 u8 port_num, void *out, size_t sz);
1079 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1080 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1081 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1082 struct mlx5_rate_limit *rl);
1083 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1084 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1085 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1086 bool dedicated_entry, u16 *index);
1087 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1088 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1089 struct mlx5_rate_limit *rl_1);
1090 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1091 bool map_wc, bool fast_path);
1092 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1094 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1096 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1097 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1098 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1099 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1100 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1102 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1107 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1109 return mkey_idx << 8;
1112 static inline u8 mlx5_mkey_variant(u32 mkey)
1117 /* Async-atomic event notifier used by mlx5 core to forward FW
1118 * evetns received from event queue to mlx5 consumers.
1119 * Optimise event queue dipatching.
1121 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1122 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1124 /* Async-atomic event notifier used for forwarding
1125 * evetns from the event queue into the to mlx5 events dispatcher,
1126 * eswitch, clock and others.
1128 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1129 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1131 /* Blocking event notifier used to forward SW events, used for slow path */
1132 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1133 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1134 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1137 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1139 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1140 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1141 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1142 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1143 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1144 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1145 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1146 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1147 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1148 struct net_device *slave);
1149 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1153 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1154 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1155 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1156 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1157 u64 length, u32 log_alignment, u16 uid,
1158 phys_addr_t *addr, u32 *obj_id);
1159 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1160 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1162 #ifdef CONFIG_MLX5_CORE_IPOIB
1163 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1164 struct ib_device *ibdev,
1166 void (*setup)(struct net_device *));
1167 #endif /* CONFIG_MLX5_CORE_IPOIB */
1168 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1169 struct ib_device *device,
1170 struct rdma_netdev_alloc_params *params);
1173 MLX5_PCI_DEV_IS_VF = 1 << 0,
1176 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1178 return dev->coredev_type == MLX5_COREDEV_PF;
1181 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1183 return dev->coredev_type == MLX5_COREDEV_VF;
1186 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1188 return dev->caps.embedded_cpu;
1192 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1194 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1197 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1199 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1202 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1204 return dev->priv.sriov.max_vfs;
1207 static inline int mlx5_get_gid_table_len(u16 param)
1210 pr_warn("gid table length is zero\n");
1214 return 8 * (1 << param);
1217 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1219 return !!(dev->priv.rl_table.max_size);
1222 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1224 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1225 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1228 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1230 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1233 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1235 return mlx5_core_is_mp_slave(dev) ||
1236 mlx5_core_is_mp_master(dev);
1239 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1241 if (!mlx5_core_mp_enabled(dev))
1244 return MLX5_CAP_GEN(dev, native_port_num);
1247 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1249 int idx = MLX5_CAP_GEN(dev, native_port_num);
1251 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1254 return PCI_FUNC(dev->pdev->devfn);
1258 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1261 static inline bool mlx5_is_roce_init_enabled(struct mlx5_core_dev *dev)
1263 struct devlink *devlink = priv_to_devlink(dev);
1264 union devlink_param_value val;
1267 err = devlink_param_driverinit_value_get(devlink,
1268 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1270 return err ? MLX5_CAP_GEN(dev, roce) : val.vbool;
1273 #endif /* MLX5_DRIVER_H */