2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/radix-tree.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
51 #include <linux/mlx5/device.h>
52 #include <linux/mlx5/doorbell.h>
53 #include <linux/mlx5/eq.h>
54 #include <linux/timecounter.h>
55 #include <linux/ptp_clock_kernel.h>
58 MLX5_BOARD_ID_LEN = 64,
59 MLX5_MAX_NAME_LEN = 16,
63 /* one minute for the sake of bringup. Generally, commands must always
64 * complete and we may need to increase this timeout value
66 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
67 MLX5_CMD_WQ_MAX_NAME = 32,
73 CMD_STATUS_SUCCESS = 0,
79 MLX5_SQP_IEEE_1588 = 2,
81 MLX5_SQP_SYNC_UMR = 4,
89 MLX5_ATOMIC_MODE_OFFSET = 16,
90 MLX5_ATOMIC_MODE_IB_COMP = 1,
91 MLX5_ATOMIC_MODE_CX = 2,
92 MLX5_ATOMIC_MODE_8B = 3,
93 MLX5_ATOMIC_MODE_16B = 4,
94 MLX5_ATOMIC_MODE_32B = 5,
95 MLX5_ATOMIC_MODE_64B = 6,
96 MLX5_ATOMIC_MODE_128B = 7,
97 MLX5_ATOMIC_MODE_256B = 8,
101 MLX5_REG_QPTS = 0x4002,
102 MLX5_REG_QETCR = 0x4005,
103 MLX5_REG_QTCT = 0x400a,
104 MLX5_REG_QPDPM = 0x4013,
105 MLX5_REG_QCAM = 0x4019,
106 MLX5_REG_DCBX_PARAM = 0x4020,
107 MLX5_REG_DCBX_APP = 0x4021,
108 MLX5_REG_FPGA_CAP = 0x4022,
109 MLX5_REG_FPGA_CTRL = 0x4023,
110 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
111 MLX5_REG_PCAP = 0x5001,
112 MLX5_REG_PMTU = 0x5003,
113 MLX5_REG_PTYS = 0x5004,
114 MLX5_REG_PAOS = 0x5006,
115 MLX5_REG_PFCC = 0x5007,
116 MLX5_REG_PPCNT = 0x5008,
117 MLX5_REG_PPTB = 0x500b,
118 MLX5_REG_PBMC = 0x500c,
119 MLX5_REG_PMAOS = 0x5012,
120 MLX5_REG_PUDE = 0x5009,
121 MLX5_REG_PMPE = 0x5010,
122 MLX5_REG_PELC = 0x500e,
123 MLX5_REG_PVLC = 0x500f,
124 MLX5_REG_PCMR = 0x5041,
125 MLX5_REG_PMLP = 0x5002,
126 MLX5_REG_PPLM = 0x5023,
127 MLX5_REG_PCAM = 0x507f,
128 MLX5_REG_NODE_DESC = 0x6001,
129 MLX5_REG_HOST_ENDIANNESS = 0x7004,
130 MLX5_REG_MCIA = 0x9014,
131 MLX5_REG_MLCR = 0x902b,
132 MLX5_REG_MTRC_CAP = 0x9040,
133 MLX5_REG_MTRC_CONF = 0x9041,
134 MLX5_REG_MTRC_STDB = 0x9042,
135 MLX5_REG_MTRC_CTRL = 0x9043,
136 MLX5_REG_MPEIN = 0x9050,
137 MLX5_REG_MPCNT = 0x9051,
138 MLX5_REG_MTPPS = 0x9053,
139 MLX5_REG_MTPPSE = 0x9054,
140 MLX5_REG_MPEGC = 0x9056,
141 MLX5_REG_MCQI = 0x9061,
142 MLX5_REG_MCC = 0x9062,
143 MLX5_REG_MCDA = 0x9063,
144 MLX5_REG_MCAM = 0x907f,
147 enum mlx5_qpts_trust_state {
148 MLX5_QPTS_TRUST_PCP = 1,
149 MLX5_QPTS_TRUST_DSCP = 2,
152 enum mlx5_dcbx_oper_mode {
153 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
154 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
158 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
159 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
160 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
161 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
164 enum mlx5_page_fault_resume_flags {
165 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
166 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
167 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
168 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
177 enum port_state_policy {
178 MLX5_POLICY_DOWN = 0,
180 MLX5_POLICY_FOLLOW = 2,
181 MLX5_POLICY_INVALID = 0xffffffff
184 struct mlx5_field_desc {
189 struct mlx5_rsc_debug {
190 struct mlx5_core_dev *dev;
192 enum dbg_rsc_type type;
194 struct mlx5_field_desc fields[0];
197 enum mlx5_dev_event {
198 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
199 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
202 enum mlx5_port_status {
207 struct mlx5_bfreg_info {
209 int num_low_latency_bfregs;
213 * protect bfreg allocation data structs
219 u32 num_static_sys_pages;
220 u32 total_num_bfregs;
224 struct mlx5_cmd_first {
228 struct mlx5_cmd_msg {
229 struct list_head list;
230 struct cmd_msg_cache *parent;
232 struct mlx5_cmd_first first;
233 struct mlx5_cmd_mailbox *next;
236 struct mlx5_cmd_debug {
237 struct dentry *dbg_root;
238 struct dentry *dbg_in;
239 struct dentry *dbg_out;
240 struct dentry *dbg_outlen;
241 struct dentry *dbg_status;
242 struct dentry *dbg_run;
250 struct cmd_msg_cache {
251 /* protect block chain allocations
254 struct list_head head;
255 unsigned int max_inbox_size;
256 unsigned int num_ent;
260 MLX5_NUM_COMMAND_CACHES = 5,
263 struct mlx5_cmd_stats {
268 struct dentry *count;
269 /* protect command average calculations */
277 dma_addr_t alloc_dma;
288 /* protect command queue allocations
290 spinlock_t alloc_lock;
292 /* protect token allocations
294 spinlock_t token_lock;
296 unsigned long bitmask;
297 char wq_name[MLX5_CMD_WQ_MAX_NAME];
298 struct workqueue_struct *wq;
299 struct semaphore sem;
300 struct semaphore pages_sem;
302 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
303 struct dma_pool *pool;
304 struct mlx5_cmd_debug dbg;
305 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
306 int checksum_disabled;
307 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
310 struct mlx5_port_caps {
317 struct mlx5_cmd_mailbox {
320 struct mlx5_cmd_mailbox *next;
323 struct mlx5_buf_list {
328 struct mlx5_frag_buf {
329 struct mlx5_buf_list *frags;
335 struct mlx5_frag_buf_ctrl {
336 struct mlx5_buf_list *frags;
345 struct mlx5_core_psv {
357 struct mlx5_core_sig_ctx {
358 struct mlx5_core_psv psv_memory;
359 struct mlx5_core_psv psv_wire;
360 struct ib_sig_err err_item;
361 bool sig_status_checked;
369 MLX5_MKEY_INDIRECT_DEVX,
372 struct mlx5_core_mkey {
380 #define MLX5_24BIT_MASK ((1 << 24) - 1)
383 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
384 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
385 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
389 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
392 struct mlx5_core_rsc_common {
393 enum mlx5_res_type res;
395 struct completion free;
398 struct mlx5_uars_page {
402 struct list_head list;
404 unsigned long *reg_bitmap; /* for non fast path bf regs */
405 unsigned long *fp_bitmap;
406 unsigned int reg_avail;
407 unsigned int fp_avail;
408 struct kref ref_count;
409 struct mlx5_core_dev *mdev;
412 struct mlx5_bfreg_head {
413 /* protect blue flame registers allocations */
415 struct list_head list;
418 struct mlx5_bfreg_data {
419 struct mlx5_bfreg_head reg_head;
420 struct mlx5_bfreg_head wc_head;
423 struct mlx5_sq_bfreg {
425 struct mlx5_uars_page *up;
431 struct mlx5_core_health {
432 struct health_buffer __iomem *health;
433 __be32 __iomem *health_counter;
434 struct timer_list timer;
438 /* wq spinlock to synchronize draining */
440 struct workqueue_struct *wq;
442 struct work_struct work;
443 struct delayed_work recover_work;
446 struct mlx5_qp_table {
447 struct notifier_block nb;
449 /* protect radix tree
452 struct radix_tree_root tree;
455 struct mlx5_mkey_table {
456 /* protect radix tree
459 struct radix_tree_root tree;
462 struct mlx5_vf_context {
466 enum port_state_policy policy;
469 struct mlx5_core_sriov {
470 struct mlx5_vf_context *vfs_ctx;
475 struct mlx5_fc_stats {
476 spinlock_t counters_idr_lock; /* protects counters_idr */
477 struct idr counters_idr;
478 struct list_head counters;
479 struct llist_head addlist;
480 struct llist_head dellist;
482 struct workqueue_struct *wq;
483 struct delayed_work work;
484 unsigned long next_query;
485 unsigned long sampling_interval; /* jiffies */
493 struct mlx5_eq_table;
495 struct mlx5_rate_limit {
501 struct mlx5_rl_entry {
502 struct mlx5_rate_limit rl;
507 struct mlx5_rl_table {
508 /* protect rate limit table */
509 struct mutex rl_lock;
513 struct mlx5_rl_entry *rl_entry;
517 char name[MLX5_MAX_NAME_LEN];
518 struct mlx5_eq_table *eq_table;
521 struct mlx5_nb pg_nb;
522 struct workqueue_struct *pg_wq;
523 struct rb_root page_root;
526 struct list_head free_list;
530 struct mlx5_core_health health;
532 /* start: qp staff */
533 struct mlx5_qp_table qp_table;
534 struct dentry *qp_debugfs;
535 struct dentry *eq_debugfs;
536 struct dentry *cq_debugfs;
537 struct dentry *cmdif_debugfs;
540 /* start: mkey staff */
541 struct mlx5_mkey_table mkey_table;
542 /* end: mkey staff */
544 /* start: alloc staff */
545 /* protect buffer alocation according to numa node */
546 struct mutex alloc_mutex;
549 struct mutex pgdir_mutex;
550 struct list_head pgdir_list;
551 /* end: alloc staff */
552 struct dentry *dbg_root;
554 /* protect mkey key part */
555 spinlock_t mkey_lock;
558 struct list_head dev_list;
559 struct list_head ctx_list;
561 struct mlx5_events *events;
563 struct mlx5_flow_steering *steering;
564 struct mlx5_mpfs *mpfs;
565 struct mlx5_eswitch *eswitch;
566 struct mlx5_core_sriov sriov;
567 struct mlx5_lag *lag;
568 struct mlx5_devcom *devcom;
569 unsigned long pci_dev_data;
570 struct mlx5_fc_stats fc_stats;
571 struct mlx5_rl_table rl_table;
573 struct mlx5_bfreg_data bfregs;
574 struct mlx5_uars_page *uar;
577 enum mlx5_device_state {
578 MLX5_DEVICE_STATE_UP,
579 MLX5_DEVICE_STATE_INTERNAL_ERROR,
582 enum mlx5_interface_state {
583 MLX5_INTERFACE_STATE_UP = BIT(0),
586 enum mlx5_pci_status {
587 MLX5_PCI_STATUS_DISABLED,
588 MLX5_PCI_STATUS_ENABLED,
591 enum mlx5_pagefault_type_flags {
592 MLX5_PFAULT_REQUESTOR = 1 << 0,
593 MLX5_PFAULT_WRITE = 1 << 1,
594 MLX5_PFAULT_RDMA = 1 << 2,
598 struct list_head tirs_list;
602 struct mlx5e_resources {
605 struct mlx5_core_mkey mkey;
606 struct mlx5_sq_bfreg bfreg;
609 #define MLX5_MAX_RESERVED_GIDS 8
611 struct mlx5_rsvd_gids {
617 #define MAX_PIN_NUM 8
619 u8 pin_caps[MAX_PIN_NUM];
620 struct work_struct out_work;
621 u64 start[MAX_PIN_NUM];
626 struct mlx5_core_dev *mdev;
627 struct mlx5_nb pps_nb;
629 struct cyclecounter cycles;
630 struct timecounter tc;
631 struct hwtstamp_config hwtstamp_config;
633 unsigned long overflow_period;
634 struct delayed_work overflow_work;
635 struct ptp_clock *ptp;
636 struct ptp_clock_info ptp_info;
637 struct mlx5_pps pps_info;
640 struct mlx5_fw_tracer;
643 struct mlx5_core_dev {
644 struct pci_dev *pdev;
646 struct mutex pci_status_mutex;
647 enum mlx5_pci_status pci_status;
649 char board_id[MLX5_BOARD_ID_LEN];
651 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
653 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
654 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
655 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
656 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
657 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
658 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
662 phys_addr_t iseg_base;
663 struct mlx5_init_seg __iomem *iseg;
664 phys_addr_t bar_addr;
665 enum mlx5_device_state state;
666 /* sync interface state */
667 struct mutex intf_state_mutex;
668 unsigned long intf_state;
669 struct mlx5_priv priv;
670 struct mlx5_profile *profile;
673 struct mlx5e_resources mlx5e_res;
674 struct mlx5_vxlan *vxlan;
676 struct mlx5_rsvd_gids reserved_gids;
679 #ifdef CONFIG_MLX5_FPGA
680 struct mlx5_fpga_device *fpga;
682 struct mlx5_clock clock;
683 struct mlx5_ib_clock_info *clock_info;
684 struct page *clock_info_page;
685 struct mlx5_fw_tracer *tracer;
691 struct mlx5_db_pgdir *pgdir;
692 struct mlx5_ib_user_db_page *user_page;
699 MLX5_COMP_EQ_SIZE = 1024,
703 MLX5_PTYS_IB = 1 << 0,
704 MLX5_PTYS_EN = 1 << 2,
707 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
710 MLX5_CMD_ENT_STATE_PENDING_COMP,
713 struct mlx5_cmd_work_ent {
715 struct mlx5_cmd_msg *in;
716 struct mlx5_cmd_msg *out;
719 mlx5_cmd_cbk_t callback;
720 struct delayed_work cb_timeout_work;
723 struct completion done;
724 struct mlx5_cmd *cmd;
725 struct work_struct work;
726 struct mlx5_cmd_layout *lay;
742 enum phy_port_state {
746 struct mlx5_hca_vport_context {
751 enum port_state_policy policy;
752 enum phy_port_state phys_state;
753 enum ib_port_state vport_state;
754 u8 port_physical_state;
763 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
768 u16 qkey_violation_counter;
769 u16 pkey_violation_counter;
773 static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
775 return buf->frags->buf + offset;
778 #define STRUCT_FIELD(header, field) \
779 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
780 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
782 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
784 return pci_get_drvdata(pdev);
787 extern struct dentry *mlx5_debugfs_root;
789 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
791 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
794 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
796 return ioread32be(&dev->iseg->fw_rev) >> 16;
799 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
801 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
804 static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
806 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
809 static inline u32 mlx5_base_mkey(const u32 key)
811 return key & 0xffffff00u;
814 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
815 u8 log_stride, u8 log_sz,
817 struct mlx5_frag_buf_ctrl *fbc)
820 fbc->log_stride = log_stride;
821 fbc->log_sz = log_sz;
822 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
823 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
824 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
825 fbc->strides_offset = strides_offset;
828 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
829 u8 log_stride, u8 log_sz,
830 struct mlx5_frag_buf_ctrl *fbc)
832 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
835 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
840 ix += fbc->strides_offset;
841 frag = ix >> fbc->log_frag_strides;
843 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
847 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
849 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
851 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
854 int mlx5_cmd_init(struct mlx5_core_dev *dev);
855 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
856 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
857 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
859 struct mlx5_async_ctx {
860 struct mlx5_core_dev *dev;
861 atomic_t num_inflight;
862 struct wait_queue_head wait;
865 struct mlx5_async_work;
867 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
869 struct mlx5_async_work {
870 struct mlx5_async_ctx *ctx;
871 mlx5_async_cbk_t user_callback;
874 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
875 struct mlx5_async_ctx *ctx);
876 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
877 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
878 void *out, int out_size, mlx5_async_cbk_t callback,
879 struct mlx5_async_work *work);
881 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
883 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
884 void *out, int out_size);
885 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
887 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
888 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
889 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
890 void mlx5_health_flush(struct mlx5_core_dev *dev);
891 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
892 int mlx5_health_init(struct mlx5_core_dev *dev);
893 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
894 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
895 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
896 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
897 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
898 int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size,
899 struct mlx5_frag_buf *buf, int node);
900 int mlx5_buf_alloc(struct mlx5_core_dev *dev,
901 int size, struct mlx5_frag_buf *buf);
902 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
903 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
904 struct mlx5_frag_buf *buf, int node);
905 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
906 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
907 gfp_t flags, int npages);
908 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
909 struct mlx5_cmd_mailbox *head);
910 void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
911 void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
912 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
913 struct mlx5_core_mkey *mkey,
914 struct mlx5_async_ctx *async_ctx, u32 *in,
915 int inlen, u32 *out, int outlen,
916 mlx5_async_cbk_t callback,
917 struct mlx5_async_work *context);
918 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
919 struct mlx5_core_mkey *mkey,
921 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
922 struct mlx5_core_mkey *mkey);
923 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
924 u32 *out, int outlen);
925 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
926 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
927 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
928 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
929 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
930 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
931 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
932 s32 npages, bool ec_function);
933 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
934 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
935 void mlx5_register_debugfs(void);
936 void mlx5_unregister_debugfs(void);
938 void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
939 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
940 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
942 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
943 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
945 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
946 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
947 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
948 int size_in, void *data_out, int size_out,
949 u16 reg_num, int arg, int write);
951 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
952 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
954 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
956 const char *mlx5_command_str(int command);
957 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
958 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
959 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
960 int npsvs, u32 *sig_index);
961 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
962 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
963 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
964 struct mlx5_odp_caps *odp_caps);
965 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
966 u8 port_num, void *out, size_t sz);
968 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
969 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
970 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
971 struct mlx5_rate_limit *rl);
972 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
973 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
974 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
975 struct mlx5_rate_limit *rl_1);
976 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
977 bool map_wc, bool fast_path);
978 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
980 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
982 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
983 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
984 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
985 u8 roce_version, u8 roce_l3_type, const u8 *gid,
986 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
988 static inline int fw_initializing(struct mlx5_core_dev *dev)
990 return ioread32be(&dev->iseg->initializing) >> 31;
993 static inline u32 mlx5_mkey_to_idx(u32 mkey)
998 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1000 return mkey_idx << 8;
1003 static inline u8 mlx5_mkey_variant(u32 mkey)
1009 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1010 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1014 MR_CACHE_LAST_STD_ENTRY = 20,
1015 MLX5_IMR_MTT_CACHE_ENTRY,
1016 MLX5_IMR_KSM_CACHE_ENTRY,
1017 MAX_MR_CACHE_ENTRIES
1021 MLX5_INTERFACE_PROTOCOL_IB = 0,
1022 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1025 struct mlx5_interface {
1026 void * (*add)(struct mlx5_core_dev *dev);
1027 void (*remove)(struct mlx5_core_dev *dev, void *context);
1028 int (*attach)(struct mlx5_core_dev *dev, void *context);
1029 void (*detach)(struct mlx5_core_dev *dev, void *context);
1031 struct list_head list;
1034 int mlx5_register_interface(struct mlx5_interface *intf);
1035 void mlx5_unregister_interface(struct mlx5_interface *intf);
1036 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1037 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1039 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1041 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1042 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1043 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1044 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1045 bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1046 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1047 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1048 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1052 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1053 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1055 #ifdef CONFIG_MLX5_CORE_IPOIB
1056 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1057 struct ib_device *ibdev,
1059 void (*setup)(struct net_device *));
1060 #endif /* CONFIG_MLX5_CORE_IPOIB */
1061 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1062 struct ib_device *device,
1063 struct rdma_netdev_alloc_params *params);
1065 struct mlx5_profile {
1071 } mr_cache[MAX_MR_CACHE_ENTRIES];
1075 MLX5_PCI_DEV_IS_VF = 1 << 0,
1078 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1080 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1083 static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1085 return dev->caps.embedded_cpu;
1088 static inline bool mlx5_core_is_ecpf_esw_manager(struct mlx5_core_dev *dev)
1090 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1093 static inline bool mlx5_ecpf_vport_exists(struct mlx5_core_dev *dev)
1095 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1098 #define MLX5_HOST_PF_MAX_VFS (127u)
1099 static inline u16 mlx5_core_max_vfs(struct mlx5_core_dev *dev)
1101 if (mlx5_core_is_ecpf_esw_manager(dev))
1102 return MLX5_HOST_PF_MAX_VFS;
1104 return pci_sriov_get_totalvfs(dev->pdev);
1107 static inline int mlx5_get_gid_table_len(u16 param)
1110 pr_warn("gid table length is zero\n");
1114 return 8 * (1 << param);
1117 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1119 return !!(dev->priv.rl_table.max_size);
1122 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1124 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1125 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1128 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1130 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1133 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1135 return mlx5_core_is_mp_slave(dev) ||
1136 mlx5_core_is_mp_master(dev);
1139 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1141 if (!mlx5_core_mp_enabled(dev))
1144 return MLX5_CAP_GEN(dev, native_port_num);
1148 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1151 #endif /* MLX5_DRIVER_H */