2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
63 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
65 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
68 /* insert a value to a struct */
69 #define MLX5_SET(typ, p, fld, v) do { \
71 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
72 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
73 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
74 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
75 << __mlx5_dw_bit_off(typ, fld))); \
78 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
79 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
80 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
81 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
82 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
83 << __mlx5_dw_bit_off(typ, fld))); \
86 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
87 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
88 __mlx5_mask(typ, fld))
90 #define MLX5_GET_PR(typ, p, fld) ({ \
91 u32 ___t = MLX5_GET(typ, p, fld); \
92 pr_debug(#fld " = 0x%x\n", ___t); \
96 #define __MLX5_SET64(typ, p, fld, v) do { \
97 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
98 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
101 #define MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
103 __MLX5_SET64(typ, p, fld, v); \
106 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld[idx], v); \
111 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
113 #define MLX5_GET64_PR(typ, p, fld) ({ \
114 u64 ___t = MLX5_GET64(typ, p, fld); \
115 pr_debug(#fld " = 0x%llx\n", ___t); \
119 /* Big endian getters */
120 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
121 __mlx5_64_off(typ, fld)))
123 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
125 switch (sizeof(tmp)) { \
127 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
130 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
133 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
136 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
142 enum mlx5_inline_modes {
143 MLX5_INLINE_MODE_NONE,
146 MLX5_INLINE_MODE_TCP_UDP,
150 MLX5_MAX_COMMANDS = 32,
151 MLX5_CMD_DATA_BLOCK_SIZE = 512,
152 MLX5_PCI_CMD_XPORT = 7,
153 MLX5_MKEY_BSF_OCTO_SIZE = 4,
158 MLX5_EXTENDED_UD_AV = 0x80000000,
162 MLX5_CQ_STATE_ARMED = 9,
163 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
164 MLX5_CQ_STATE_FIRED = 0xa,
168 MLX5_STAT_RATE_OFFSET = 5,
172 MLX5_INLINE_SEG = 0x80000000,
176 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
180 MLX5_MIN_PKEY_TABLE_SIZE = 128,
181 MLX5_MAX_LOG_PKEY_TABLE = 5,
185 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
189 MLX5_PFAULT_SUBTYPE_WQE = 0,
190 MLX5_PFAULT_SUBTYPE_RDMA = 1,
194 MLX5_PERM_LOCAL_READ = 1 << 2,
195 MLX5_PERM_LOCAL_WRITE = 1 << 3,
196 MLX5_PERM_REMOTE_READ = 1 << 4,
197 MLX5_PERM_REMOTE_WRITE = 1 << 5,
198 MLX5_PERM_ATOMIC = 1 << 6,
199 MLX5_PERM_UMR_EN = 1 << 7,
203 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
204 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
205 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
206 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
207 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
216 MLX5_ADAPTER_PAGE_SHIFT = 12,
217 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
221 MLX5_BFREGS_PER_UAR = 4,
222 MLX5_MAX_UARS = 1 << 8,
223 MLX5_NON_FP_BFREGS_PER_UAR = 2,
224 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
225 MLX5_NON_FP_BFREGS_PER_UAR,
226 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
227 MLX5_NON_FP_BFREGS_PER_UAR,
228 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
229 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
233 MLX5_MKEY_MASK_LEN = 1ull << 0,
234 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
235 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
236 MLX5_MKEY_MASK_PD = 1ull << 7,
237 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
238 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
239 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
240 MLX5_MKEY_MASK_KEY = 1ull << 13,
241 MLX5_MKEY_MASK_QPN = 1ull << 14,
242 MLX5_MKEY_MASK_LR = 1ull << 17,
243 MLX5_MKEY_MASK_LW = 1ull << 18,
244 MLX5_MKEY_MASK_RR = 1ull << 19,
245 MLX5_MKEY_MASK_RW = 1ull << 20,
246 MLX5_MKEY_MASK_A = 1ull << 21,
247 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
248 MLX5_MKEY_MASK_FREE = 1ull << 29,
252 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
254 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
255 MLX5_UMR_CHECK_FREE = (2 << 5),
257 MLX5_UMR_INLINE = (1 << 7),
260 #define MLX5_UMR_MTT_ALIGNMENT 0x40
261 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
262 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
264 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
267 MLX5_EVENT_QUEUE_TYPE_QP = 0,
268 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
269 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
273 MLX5_EVENT_TYPE_COMP = 0x0,
275 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
276 MLX5_EVENT_TYPE_COMM_EST = 0x02,
277 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
278 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
279 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
281 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
282 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
283 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
284 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
285 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
286 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
288 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
289 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
290 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
291 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
292 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
293 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
294 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
296 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
297 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
299 MLX5_EVENT_TYPE_CMD = 0x0a,
300 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
302 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
303 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
305 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
309 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
313 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
314 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
315 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
316 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
317 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
318 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
319 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
323 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
324 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
325 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
326 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
327 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
328 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
329 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
330 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
331 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
332 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
333 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
334 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
338 MLX5_ROCE_VERSION_1 = 0,
339 MLX5_ROCE_VERSION_2 = 2,
343 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
344 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
348 MLX5_ROCE_L3_TYPE_IPV4 = 0,
349 MLX5_ROCE_L3_TYPE_IPV6 = 1,
353 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
354 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
358 MLX5_OPCODE_NOP = 0x00,
359 MLX5_OPCODE_SEND_INVAL = 0x01,
360 MLX5_OPCODE_RDMA_WRITE = 0x08,
361 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
362 MLX5_OPCODE_SEND = 0x0a,
363 MLX5_OPCODE_SEND_IMM = 0x0b,
364 MLX5_OPCODE_LSO = 0x0e,
365 MLX5_OPCODE_RDMA_READ = 0x10,
366 MLX5_OPCODE_ATOMIC_CS = 0x11,
367 MLX5_OPCODE_ATOMIC_FA = 0x12,
368 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
369 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
370 MLX5_OPCODE_BIND_MW = 0x18,
371 MLX5_OPCODE_CONFIG_CMD = 0x1f,
373 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
374 MLX5_RECV_OPCODE_SEND = 0x01,
375 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
376 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
378 MLX5_CQE_OPCODE_ERROR = 0x1e,
379 MLX5_CQE_OPCODE_RESIZE = 0x16,
381 MLX5_OPCODE_SET_PSV = 0x20,
382 MLX5_OPCODE_GET_PSV = 0x21,
383 MLX5_OPCODE_CHECK_PSV = 0x22,
384 MLX5_OPCODE_RGET_PSV = 0x26,
385 MLX5_OPCODE_RCHECK_PSV = 0x27,
387 MLX5_OPCODE_UMR = 0x25,
392 MLX5_SET_PORT_RESET_QKEY = 0,
393 MLX5_SET_PORT_GUID0 = 16,
394 MLX5_SET_PORT_NODE_GUID = 17,
395 MLX5_SET_PORT_SYS_GUID = 18,
396 MLX5_SET_PORT_GID_TABLE = 19,
397 MLX5_SET_PORT_PKEY_TABLE = 20,
401 MLX5_BW_NO_LIMIT = 0,
402 MLX5_100_MBPS_UNIT = 3,
407 MLX5_MAX_PAGE_SHIFT = 31
411 MLX5_CAP_OFF_CMDIF_CSUM = 46,
416 * Max wqe size for rdma read is 512 bytes, so this
417 * limits our max_sge_rd as the wqe needs to fit:
418 * - ctrl segment (16 bytes)
419 * - rdma segment (16 bytes)
420 * - scatter elements (16 bytes each)
422 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
425 enum mlx5_odp_transport_cap_bits {
426 MLX5_ODP_SUPPORT_SEND = 1 << 31,
427 MLX5_ODP_SUPPORT_RECV = 1 << 30,
428 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
429 MLX5_ODP_SUPPORT_READ = 1 << 28,
432 struct mlx5_odp_caps {
438 } per_transport_caps;
439 char reserved2[0xe4];
442 struct mlx5_cmd_layout {
457 struct health_buffer {
458 __be32 assert_var[5];
460 __be32 assert_exit_ptr;
461 __be32 assert_callra;
471 struct mlx5_init_seg {
473 __be32 cmdif_rev_fw_sub;
476 __be32 cmdq_addr_l_sz;
480 struct health_buffer health;
482 __be32 internal_timer_h;
483 __be32 internal_timer_l;
485 __be32 health_counter;
488 __be32 ieee1588_clk_type;
492 struct mlx5_eqe_comp {
497 struct mlx5_eqe_qp_srq {
504 struct mlx5_eqe_cq_err {
510 struct mlx5_eqe_port_state {
515 struct mlx5_eqe_gpio {
520 struct mlx5_eqe_congestion {
526 struct mlx5_eqe_stall_vl {
531 struct mlx5_eqe_cmd {
536 struct mlx5_eqe_page_req {
543 struct mlx5_eqe_page_fault {
544 __be32 bytes_committed;
550 __be16 packet_length;
558 __be16 packet_length;
566 struct mlx5_eqe_vport_change {
572 struct mlx5_eqe_port_module {
581 struct mlx5_eqe_pps {
599 struct mlx5_eqe_cmd cmd;
600 struct mlx5_eqe_comp comp;
601 struct mlx5_eqe_qp_srq qp_srq;
602 struct mlx5_eqe_cq_err cq_err;
603 struct mlx5_eqe_port_state port;
604 struct mlx5_eqe_gpio gpio;
605 struct mlx5_eqe_congestion cong;
606 struct mlx5_eqe_stall_vl stall_vl;
607 struct mlx5_eqe_page_req req_pages;
608 struct mlx5_eqe_page_fault page_fault;
609 struct mlx5_eqe_vport_change vport_change;
610 struct mlx5_eqe_port_module port_module;
611 struct mlx5_eqe_pps pps;
626 struct mlx5_cmd_prot_block {
627 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
638 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
641 struct mlx5_err_cqe {
647 __be32 s_wqe_opcode_qpn;
654 u8 outer_l3_tunneled;
657 u8 lro_tcppsh_abort_dupack;
660 __be32 lro_ack_seq_num;
661 __be32 rss_hash_result;
671 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
672 __be32 imm_inval_pkey;
683 struct mlx5_mini_cqe8 {
685 __be32 rx_hash_result;
701 MLX5_INLINE_DATA32_SEG,
702 MLX5_INLINE_DATA64_SEG,
707 MLX5_CQE_FORMAT_CSUM = 0x1,
710 #define MLX5_MINI_CQE_ARRAY_SIZE 8
712 static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
714 return (cqe->op_own >> 2) & 0x3;
717 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
719 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
722 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
724 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
727 static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
729 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
732 static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
734 return cqe->outer_l3_tunneled & 0x1;
737 static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
739 return !!(cqe->l4_l3_hdr_type & 0x1);
742 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
746 hi = be32_to_cpu(cqe->timestamp_h);
747 lo = be32_to_cpu(cqe->timestamp_l);
749 return (u64)lo | ((u64)hi << 32);
752 struct mpwrq_cqe_bc {
753 __be16 filler_consumed_strides;
757 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
759 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
761 return be16_to_cpu(bc->byte_cnt);
764 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
766 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
769 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
771 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
773 return mpwrq_get_cqe_bc_consumed_strides(bc);
776 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
778 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
780 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
783 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
785 return be16_to_cpu(cqe->wqe_counter);
789 CQE_L4_HDR_TYPE_NONE = 0x0,
790 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
791 CQE_L4_HDR_TYPE_UDP = 0x2,
792 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
793 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
797 CQE_RSS_HTYPE_IP = 0x3 << 2,
798 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
799 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
801 CQE_RSS_HTYPE_L4 = 0x3 << 6,
802 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
803 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
808 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
809 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
810 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
819 struct mlx5_sig_err_cqe {
821 __be32 expected_trans_sig;
822 __be32 actual_trans_sig;
823 __be32 expected_reftag;
824 __be32 actual_reftag;
836 struct mlx5_wqe_srq_next_seg {
838 __be16 next_wqe_index;
849 union mlx5_ext_cqe inl_grh;
850 struct mlx5_cqe64 cqe64;
854 MLX5_MKEY_STATUS_FREE = 1 << 6,
858 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
859 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
860 MLX5_MKEY_BSF_EN = 1 << 30,
861 MLX5_MKEY_LEN64 = 1 << 31,
864 struct mlx5_mkey_seg {
865 /* This is a two bit field occupying bits 31-30.
866 * bit 31 is always 0,
867 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
878 __be32 bsfs_octo_size;
886 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
889 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
893 VPORT_STATE_DOWN = 0x0,
894 VPORT_STATE_UP = 0x1,
898 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
899 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
900 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
904 MLX5_L3_PROT_TYPE_IPV4 = 0,
905 MLX5_L3_PROT_TYPE_IPV6 = 1,
909 MLX5_L4_PROT_TYPE_TCP = 0,
910 MLX5_L4_PROT_TYPE_UDP = 1,
914 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
915 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
916 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
917 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
918 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
922 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
923 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
924 MLX5_MATCH_INNER_HEADERS = 1 << 2,
929 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
930 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
934 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
935 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
936 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
939 enum mlx5_list_type {
940 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
941 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
942 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
946 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
947 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
951 MLX5_WOL_DISABLE = 0,
952 MLX5_WOL_SECURED_MAGIC = 1 << 1,
953 MLX5_WOL_MAGIC = 1 << 2,
954 MLX5_WOL_ARP = 1 << 3,
955 MLX5_WOL_BROADCAST = 1 << 4,
956 MLX5_WOL_MULTICAST = 1 << 5,
957 MLX5_WOL_UNICAST = 1 << 6,
958 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
965 HCA_CAP_OPMOD_GET_MAX = 0,
966 HCA_CAP_OPMOD_GET_CUR = 1,
970 MLX5_CAP_GENERAL = 0,
971 MLX5_CAP_ETHERNET_OFFLOADS,
975 MLX5_CAP_IPOIB_OFFLOADS,
976 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
978 MLX5_CAP_ESWITCH_FLOW_TABLE,
981 MLX5_CAP_VECTOR_CALC,
983 /* NUM OF CAP Types */
987 enum mlx5_pcam_reg_groups {
988 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
991 enum mlx5_pcam_feature_groups {
992 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
995 enum mlx5_mcam_reg_groups {
996 MLX5_MCAM_REGS_FIRST_128 = 0x0,
999 enum mlx5_mcam_feature_groups {
1000 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1003 /* GET Dev Caps macros */
1004 #define MLX5_CAP_GEN(mdev, cap) \
1005 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1007 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1008 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1010 #define MLX5_CAP_ETH(mdev, cap) \
1011 MLX5_GET(per_protocol_networking_offload_caps,\
1012 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1014 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1015 MLX5_GET(per_protocol_networking_offload_caps,\
1016 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1018 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1019 MLX5_GET(per_protocol_networking_offload_caps,\
1020 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1022 #define MLX5_CAP_ROCE(mdev, cap) \
1023 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1025 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1026 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1028 #define MLX5_CAP_ATOMIC(mdev, cap) \
1029 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1031 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1032 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1034 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1035 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1037 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1038 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1040 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1041 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1043 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1044 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1046 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1047 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1049 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1050 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1052 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1053 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1055 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1056 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1058 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1059 MLX5_GET(flow_table_eswitch_cap, \
1060 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1062 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1063 MLX5_GET(flow_table_eswitch_cap, \
1064 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1066 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1067 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1069 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1070 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1072 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1073 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1075 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1076 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1078 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1079 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1081 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1082 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1084 #define MLX5_CAP_ESW(mdev, cap) \
1085 MLX5_GET(e_switch_cap, \
1086 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1088 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1089 MLX5_GET(e_switch_cap, \
1090 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1092 #define MLX5_CAP_ODP(mdev, cap)\
1093 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1095 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1096 MLX5_GET(vector_calc_cap, \
1097 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1099 #define MLX5_CAP_QOS(mdev, cap)\
1100 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1102 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1103 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1105 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1106 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1108 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1109 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1111 #define MLX5_CAP_FPGA(mdev, cap) \
1112 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1114 #define MLX5_CAP64_FPGA(mdev, cap) \
1115 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1118 MLX5_CMD_STAT_OK = 0x0,
1119 MLX5_CMD_STAT_INT_ERR = 0x1,
1120 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1121 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1122 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1123 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1124 MLX5_CMD_STAT_RES_BUSY = 0x6,
1125 MLX5_CMD_STAT_LIM_ERR = 0x8,
1126 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1127 MLX5_CMD_STAT_IX_ERR = 0xa,
1128 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1129 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1130 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1131 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1132 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1133 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1137 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1138 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1139 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1140 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1141 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1142 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1143 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1144 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1145 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1146 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1150 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1153 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1155 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1157 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1160 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1161 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1162 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1163 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1164 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1165 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1167 #endif /* MLX5_DEVICE_H */