1 /* SPDX-License-Identifier: GPL-2.0 */
3 #ifndef _WCD934X_REGISTERS_H
4 #define _WCD934X_REGISTERS_H
6 #define WCD934X_CODEC_RPM_CLK_GATE 0x0002
7 #define WCD934X_CODEC_RPM_CLK_GATE_MASK GENMASK(1, 0)
8 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG 0x0003
9 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0)
10 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(1)
11 #define WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0)
12 #define WCD934X_CODEC_RPM_RST_CTL 0x0009
13 #define WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL 0x0011
14 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0 0x0021
15 #define WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2 0x0023
16 #define WCD934X_CHIP_TIER_CTRL_EFUSE_CTL 0x0025
17 #define WCD934X_EFUSE_SENSE_STATE_MASK GENMASK(4, 1)
18 #define WCD934X_EFUSE_SENSE_STATE_DEF 0x10
19 #define WCD934X_EFUSE_SENSE_EN_MASK BIT(0)
20 #define WCD934X_EFUSE_SENSE_ENABLE BIT(0)
21 #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037
22 #define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038
23 #define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039
24 #define WCD934X_DATA_HUB_SB_TX10_INP_CFG 0x006b
25 #define WCD934X_DATA_HUB_SB_TX11_INP_CFG 0x006c
26 #define WCD934X_DATA_HUB_SB_TX13_INP_CFG 0x006e
27 #define WCD934X_CPE_FLL_CONFIG_CTL_2 0x0111
28 #define WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD 0x0213
29 #define WCD934X_CPE_SS_SVA_CFG 0x0214
30 #define WCD934X_CPE_SS_DMIC0_CTL 0x0218
31 #define WCD934X_CPE_SS_DMIC1_CTL 0x0219
32 #define WCD934X_DMIC_RATE_MASK GENMASK(3, 1)
33 #define WCD934X_CPE_SS_DMIC2_CTL 0x021a
34 #define WCD934X_CPE_SS_DMIC_CFG 0x021b
35 #define WCD934X_CPE_SS_DMIC_CFG 0x021b
36 #define WCD934X_CPE_SS_CPAR_CFG 0x021c
37 #define WCD934X_INTR_PIN1_MASK0 0x0409
38 #define WCD934X_INTR_PIN1_STATUS0 0x0411
39 #define WCD934X_INTR_PIN1_CLEAR0 0x0419
40 #define WCD934X_INTR_PIN2_CLEAR3 0x0434
41 #define WCD934X_INTR_LEVEL0 0x0461
43 #define WCD934X_IRQ_SLIMBUS 0
44 #define WCD934X_IRQ_MISC 1
45 #define WCD934X_IRQ_HPH_PA_OCPL_FAULT 2
46 #define WCD934X_IRQ_HPH_PA_OCPR_FAULT 3
47 #define WCD934X_IRQ_EAR_PA_OCP_FAULT 4
48 #define WCD934X_IRQ_HPH_PA_CNPL_COMPLETE 5
49 #define WCD934X_IRQ_HPH_PA_CNPR_COMPLETE 6
50 #define WCD934X_IRQ_EAR_PA_CNP_COMPLETE 7
52 #define WCD934X_IRQ_MBHC_SW_DET 8
53 #define WCD934X_IRQ_MBHC_ELECT_INS_REM_DET 9
54 #define WCD934X_IRQ_MBHC_BUTTON_PRESS_DET 10
55 #define WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET 11
56 #define WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12
57 #define WCD934X_IRQ_RESERVED_0 13
58 #define WCD934X_IRQ_RESERVED_1 14
59 #define WCD934X_IRQ_RESERVED_2 15
61 #define WCD934X_IRQ_LINE_PA1_CNP_COMPLETE 16
62 #define WCD934X_IRQ_LINE_PA2_CNP_COMPLETE 17
63 #define WCD934X_IRQ_SLNQ_ANALOG_ERROR 18
64 #define WCD934X_IRQ_RESERVED_3 19
65 #define WCD934X_IRQ_SOUNDWIRE 20
66 #define WCD934X_IRQ_VDD_DIG_RAMP_COMPLETE 21
67 #define WCD934X_IRQ_RCO_ERROR 22
68 #define WCD934X_IRQ_CPE_ERROR 23
70 #define WCD934X_IRQ_MAD_AUDIO 24
71 #define WCD934X_IRQ_MAD_BEACON 25
72 #define WCD934X_IRQ_MAD_ULTRASOUND 26
73 #define WCD934X_IRQ_VBAT_ATTACK 27
74 #define WCD934X_IRQ_VBAT_RESTORE 28
75 #define WCD934X_IRQ_CPE1_INTR 29
76 #define WCD934X_IRQ_RESERVED_4 30
77 #define WCD934X_IRQ_SLNQ_DIGITAL 31
78 #define WCD934X_NUM_IRQS 32
79 #define WCD934X_ANA_BIAS 0x0601
80 #define WCD934X_ANA_BIAS_EN_MASK BIT(7)
81 #define WCD934X_ANA_BIAS_EN BIT(7)
82 #define WCD934X_ANA_PRECHRG_EN_MASK BIT(6)
83 #define WCD934X_ANA_PRECHRG_EN BIT(6)
84 #define WCD934X_ANA_PRECHRG_MODE_MASK BIT(5)
85 #define WCD934X_ANA_PRECHRG_MODE_AUTO BIT(5)
86 #define WCD934X_ANA_RCO 0x0603
87 #define WCD934X_ANA_RCO_BG_EN_MASK BIT(7)
88 #define WCD934X_ANA_RCO_BG_ENABLE BIT(7)
89 #define WCD934X_ANA_BUCK_CTL 0x0606
90 #define WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK GENMASK(1, 0)
91 #define WCD934X_ANA_BUCK_PRE_EN2_MASK BIT(0)
92 #define WCD934X_ANA_BUCK_PRE_EN2_ENABLE BIT(0)
93 #define WCD934X_ANA_BUCK_PRE_EN1_MASK BIT(1)
94 #define WCD934X_ANA_BUCK_PRE_EN1_ENABLE BIT(1)
95 #define WCD934X_ANA_BUCK_HI_ACCU_EN_MASK BIT(2)
96 #define WCD934X_ANA_BUCK_HI_ACCU_ENABLE BIT(2)
97 #define WCD934X_ANA_RX_SUPPLIES 0x0608
98 #define WCD934X_ANA_HPH 0x0609
99 #define WCD934X_ANA_EAR 0x060a
100 #define WCD934X_ANA_LO_1_2 0x060b
101 #define WCD934X_ANA_AMIC1 0x060e
102 #define WCD934X_ANA_AMIC2 0x060f
103 #define WCD934X_ANA_AMIC3 0x0610
104 #define WCD934X_ANA_AMIC4 0x0611
105 #define WCD934X_ANA_MBHC_MECH 0x0614
106 #define WCD934X_ANA_MBHC_ELECT 0x0615
107 #define WCD934X_ANA_MBHC_ZDET 0x0616
108 #define WCD934X_ANA_MBHC_RESULT_1 0x0617
109 #define WCD934X_ANA_MBHC_RESULT_2 0x0618
110 #define WCD934X_ANA_MBHC_RESULT_3 0x0619
111 #define WCD934X_ANA_MICB1 0x0622
112 #define WCD934X_MICB_VAL_MASK GENMASK(5, 0)
113 #define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6)
114 #define WCD934X_ANA_MICB_PULL_UP 0x80
115 #define WCD934X_ANA_MICB_ENABLE 0x40
116 #define WCD934X_ANA_MICB_DISABLE 0x0
117 #define WCD934X_ANA_MICB2 0x0623
118 #define WCD934X_ANA_MICB3 0x0625
119 #define WCD934X_ANA_MICB4 0x0626
120 #define WCD934X_BIAS_VBG_FINE_ADJ 0x0629
121 #define WCD934X_MICB1_TEST_CTL_1 0x066b
122 #define WCD934X_MICB1_TEST_CTL_2 0x066c
123 #define WCD934X_MICB2_TEST_CTL_1 0x066e
124 #define WCD934X_MICB3_TEST_CTL_1 0x0671
125 #define WCD934X_MICB4_TEST_CTL_1 0x0674
126 #define WCD934X_CLASSH_MODE_1 0x0697
127 #define WCD934X_CLASSH_MODE_2 0x0698
128 #define WCD934X_CLASSH_MODE_3 0x0699
129 #define WCD934X_CLASSH_CTRL_VCL_1 0x069a
130 #define WCD934X_CLASSH_CTRL_VCL_2 0x069b
131 #define WCD934X_CLASSH_CTRL_CCL_1 0x069c
132 #define WCD934X_CLASSH_CTRL_CCL_2 0x069d
133 #define WCD934X_CLASSH_CTRL_CCL_3 0x069e
134 #define WCD934X_CLASSH_CTRL_CCL_4 0x069f
135 #define WCD934X_CLASSH_CTRL_CCL_5 0x06a0
136 #define WCD934X_CLASSH_BUCK_TMUX_A_D 0x06a1
137 #define WCD934X_CLASSH_BUCK_SW_DRV_CNTL 0x06a2
138 #define WCD934X_RX_OCP_CTL 0x06b6
139 #define WCD934X_RX_OCP_COUNT 0x06b7
140 #define WCD934X_HPH_CNP_EN 0x06cb
141 #define WCD934X_HPH_CNP_WG_CTL 0x06cc
142 #define WCD934X_HPH_GM3_BOOST_EN_MASK BIT(7)
143 #define WCD934X_HPH_GM3_BOOST_ENABLE BIT(7)
144 #define WCD934X_HPH_OCP_CTL 0x06ce
145 #define WCD934X_HPH_L_EN 0x06d3
146 #define WCD934X_HPH_GAIN_SRC_SEL_MASK BIT(5)
147 #define WCD934X_HPH_GAIN_SRC_SEL_COMPANDER 0
148 #define WCD934X_HPH_GAIN_SRC_SEL_REGISTER BIT(5)
149 #define WCD934X_HPH_L_TEST 0x06d4
150 #define WCD934X_HPH_R_EN 0x06d6
151 #define WCD934X_HPH_R_TEST 0x06d7
152 #define WCD934X_HPH_OCP_DET_MASK BIT(0)
153 #define WCD934X_HPH_OCP_DET_ENABLE BIT(0)
154 #define WCD934X_HPH_OCP_DET_DISABLE 0
155 #define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea
156 #define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb
157 #define WCD934X_CLK_SYS_MCLK_PRG 0x0711
158 #define WCD934X_EXT_CLK_BUF_EN_MASK BIT(7)
159 #define WCD934X_EXT_CLK_BUF_EN BIT(7)
160 #define WCD934X_EXT_CLK_DIV_RATIO_MASK GENMASK(5, 4)
161 #define WCD934X_EXT_CLK_DIV_BY_2 0x10
162 #define WCD934X_MCLK_SRC_MASK BIT(1)
163 #define WCD934X_MCLK_SRC_EXT_CLK 0
164 #define WCD934X_MCLK_SRC_MASK BIT(1)
165 #define WCD934X_MCLK_EN_MASK BIT(0)
166 #define WCD934X_MCLK_EN BIT(0)
167 #define WCD934X_CLK_SYS_MCLK2_PRG1 0x0712
168 #define WCD934X_CLK_SYS_MCLK2_PRG2 0x0713
169 #define WCD934X_SIDO_NEW_VOUT_A_STARTUP 0x071b
170 #define WCD934X_SIDO_NEW_VOUT_D_STARTUP 0x071c
171 #define WCD934X_SIDO_NEW_VOUT_D_FREQ1 0x071d
172 #define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e
173 #define WCD934X_SIDO_RIPPLE_FREQ_EN_MASK BIT(0)
174 #define WCD934X_SIDO_RIPPLE_FREQ_ENABLE BIT(0)
175 #define WCD934X_MBHC_NEW_CTL_2 0x0721
176 #define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727
177 #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733
178 #define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735
179 #define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R 0x0736
180 #define WCD934X_HPH_NEW_INT_HPH_TIMER1 0x073a
181 #define WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK BIT(1)
182 #define WCD934X_HPH_AUTOCHOP_TIMER_ENABLE BIT(1)
183 #define WCD934X_CDC_TX0_TX_PATH_CTL 0x0a31
184 #define WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0)
185 #define WCD934X_CDC_TX_PATH_CTL(dec) (0xa31 + dec * 0x10)
186 #define WCD934X_CDC_TX0_TX_PATH_CFG0 0x0a32
187 #define WCD934X_CDC_TX0_TX_PATH_CFG1 0x0a33
188 #define WCD934X_CDC_TX0_TX_VOL_CTL 0x0a34
189 #define WCD934X_CDC_TX0_TX_PATH_192_CTL 0x0a35
190 #define WCD934X_CDC_TX0_TX_PATH_192_CFG 0x0a36
191 #define WCD934X_CDC_TX0_TX_PATH_SEC2 0x0a39
192 #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK BIT(1)
193 #define WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ BIT(1)
194 #define WCD934X_CDC_TX1_TX_PATH_CTL 0x0a41
195 #define WCD934X_CDC_TX1_TX_PATH_CFG0 0x0a42
196 #define WCD934X_CDC_TX1_TX_PATH_CFG1 0x0a43
197 #define WCD934X_CDC_TX1_TX_VOL_CTL 0x0a44
198 #define WCD934X_CDC_TX2_TX_PATH_CTL 0x0a51
199 #define WCD934X_CDC_TX2_TX_PATH_CFG0 0x0a52
200 #define WCD934X_CDC_TX2_TX_PATH_CFG1 0x0a53
201 #define WCD934X_CDC_TX2_TX_VOL_CTL 0x0a54
202 #define WCD934X_CDC_TX3_TX_PATH_CTL 0x0a61
203 #define WCD934X_CDC_TX3_TX_PATH_CFG0 0x0a62
204 #define WCD934X_CDC_TX3_TX_PATH_CFG1 0x0a63
205 #define WCD934X_CDC_TX3_TX_VOL_CTL 0x0a64
206 #define WCD934X_CDC_TX3_TX_PATH_192_CTL 0x0a65
207 #define WCD934X_CDC_TX3_TX_PATH_192_CFG 0x0a66
208 #define WCD934X_CDC_TX4_TX_PATH_CTL 0x0a71
209 #define WCD934X_CDC_TX4_TX_PATH_CFG0 0x0a72
210 #define WCD934X_CDC_TX4_TX_PATH_CFG1 0x0a73
211 #define WCD934X_CDC_TX4_TX_VOL_CTL 0x0a74
212 #define WCD934X_CDC_TX4_TX_PATH_192_CTL 0x0a75
213 #define WCD934X_CDC_TX4_TX_PATH_192_CFG 0x0a76
214 #define WCD934X_CDC_TX5_TX_PATH_CTL 0x0a81
215 #define WCD934X_CDC_TX5_TX_PATH_CFG0 0x0a82
216 #define WCD934X_CDC_TX5_TX_PATH_CFG1 0x0a83
217 #define WCD934X_CDC_TX5_TX_VOL_CTL 0x0a84
218 #define WCD934X_CDC_TX5_TX_PATH_192_CTL 0x0a85
219 #define WCD934X_CDC_TX5_TX_PATH_192_CFG 0x0a86
220 #define WCD934X_CDC_TX6_TX_PATH_CTL 0x0a91
221 #define WCD934X_CDC_TX6_TX_PATH_CFG0 0x0a92
222 #define WCD934X_CDC_TX6_TX_PATH_CFG1 0x0a93
223 #define WCD934X_CDC_TX6_TX_VOL_CTL 0x0a94
224 #define WCD934X_CDC_TX6_TX_PATH_192_CTL 0x0a95
225 #define WCD934X_CDC_TX6_TX_PATH_192_CFG 0x0a96
226 #define WCD934X_CDC_TX7_TX_PATH_CTL 0x0aa1
227 #define WCD934X_CDC_TX7_TX_PATH_CFG0 0x0aa2
228 #define WCD934X_CDC_TX7_TX_PATH_CFG1 0x0aa3
229 #define WCD934X_CDC_TX7_TX_VOL_CTL 0x0aa4
230 #define WCD934X_CDC_TX7_TX_PATH_192_CTL 0x0aa5
231 #define WCD934X_CDC_TX7_TX_PATH_192_CFG 0x0aa6
232 #define WCD934X_CDC_TX8_TX_PATH_CTL 0x0ab1
233 #define WCD934X_CDC_TX8_TX_PATH_CFG0 0x0ab2
234 #define WCD934X_CDC_TX8_TX_PATH_CFG1 0x0ab3
235 #define WCD934X_CDC_TX8_TX_VOL_CTL 0x0ab4
236 #define WCD934X_CDC_TX8_TX_PATH_192_CTL 0x0ab5
237 #define WCD934X_CDC_TX8_TX_PATH_192_CFG 0x0ab6
238 #define WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0 0x0ac3
239 #define WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0 0x0ac7
240 #define WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0 0x0acb
241 #define WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0 0x0acf
242 #define WCD934X_CDC_COMPANDER1_CTL0 0x0b01
243 #define WCD934X_COMP_CLK_EN_MASK BIT(0)
244 #define WCD934X_COMP_CLK_ENABLE BIT(0)
245 #define WCD934X_COMP_SOFT_RST_MASK BIT(1)
246 #define WCD934X_COMP_SOFT_RST_ENABLE BIT(1)
247 #define WCD934X_COMP_HALT_MASK BIT(2)
248 #define WCD934X_COMP_HALT BIT(2)
249 #define WCD934X_COMP_SOFT_RST_DISABLE 0
250 #define WCD934X_CDC_COMPANDER1_CTL7 0x0b08
251 #define WCD934X_HPH_LOW_PWR_MODE_EN_MASK BIT(5)
252 #define WCD934X_CDC_COMPANDER2_CTL7 0x0b10
253 #define WCD934X_CDC_COMPANDER7_CTL3 0x0b34
254 #define WCD934X_CDC_COMPANDER7_CTL7 0x0b38
255 #define WCD934X_CDC_COMPANDER8_CTL3 0x0b3c
256 #define WCD934X_CDC_COMPANDER8_CTL7 0x0b40
257 #define WCD934X_CDC_RX0_RX_PATH_CTL 0x0b41
258 #define WCD934X_CDC_RX_PGA_MUTE_EN_MASK BIT(4)
259 #define WCD934X_CDC_RX_PGA_MUTE_ENABLE BIT(4)
260 #define WCD934X_CDC_RX_PGA_MUTE_DISABLE 0
261 #define WCD934X_RX_CLK_EN_MASK BIT(5)
262 #define WCD934X_RX_CLK_ENABLE BIT(5)
263 #define WCD934X_RX_RESET_MASK BIT(6)
264 #define WCD934X_RX_RESET_ENABLE BIT(6)
265 #define WCD934X_RX_RESET_DISABLE 0
266 #define WCD934X_RX_PCM_RATE_MASK GENMASK(3, 0)
267 #define WCD934X_RX_PCM_RATE_F_48K 0x04
268 #define WCD934X_CDC_RX_PATH_CTL(rx) (0xb41 + rx * 0x14)
269 #define WCD934X_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0)
270 #define WCD934X_CDC_RX0_RX_PATH_CFG0 0x0b42
271 #define WCD934X_RX_DLY_ZN_EN_MASK BIT(3)
272 #define WCD934X_RX_DLY_ZN_ENABLE BIT(3)
273 #define WCD934X_RX_DLY_ZN_DISABLE 0
274 #define WCD934X_CDC_RX0_RX_PATH_CFG1 0x0b43
275 #define WCD934X_CDC_RX0_RX_PATH_CFG2 0x0b44
276 #define WCD934X_CDC_RX0_RX_VOL_CTL 0x0b45
277 #define WCD934X_CDC_RX0_RX_PATH_MIX_CTL 0x0b46
278 #define WCD934X_CDC_RX_MIX_CLK_EN_MASK BIT(5)
279 #define WCD934X_CDC_RX_MIX_CLK_ENABLE BIT(5)
280 #define WCD934X_CDC_RX_PATH_MIX_CTL(rx) (0xb46 + rx * 0x14)
281 #define WCD934X_CDC_RX0_RX_PATH_MIX_CFG 0x0b47
282 #define WCD934X_CDC_RX0_RX_VOL_MIX_CTL 0x0b48
283 #define WCD934X_CDC_RX0_RX_PATH_SEC0 0x0b49
284 #define WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL 0x0b53
285 #define WCD934X_CDC_RX1_RX_PATH_CTL 0x0b55
286 #define WCD934X_RX_PATH_PGA_MUTE_EN_MASK BIT(4)
287 #define WCD934X_RX_PATH_PGA_MUTE_ENABLE BIT(4)
288 #define WCD934X_CDC_RX_PATH_PGA_MUTE_DISABLE 0
289 #define WCD934X_CDC_RX_PATH_CLK_EN_MASK BIT(5)
290 #define WCD934X_CDC_RX_PATH_CLK_ENABLE BIT(5)
291 #define WCD934X_CDC_RX_PATH_CLK_DISABLE 0
292 #define WCD934X_CDC_RX1_RX_PATH_CFG0 0x0b56
293 #define WCD934X_HPH_CMP_EN_MASK BIT(1)
294 #define WCD934X_HPH_CMP_ENABLE BIT(1)
295 #define WCD934X_HPH_CMP_DISABLE 0
296 #define WCD934X_CDC_RX1_RX_PATH_CFG2 0x0b58
297 #define WCD934X_CDC_RX1_RX_VOL_CTL 0x0b59
298 #define WCD934X_CDC_RX1_RX_PATH_MIX_CTL 0x0b5a
299 #define WCD934X_CDC_RX1_RX_PATH_MIX_CFG 0x0b5b
300 #define WCD934X_CDC_RX1_RX_VOL_MIX_CTL 0x0b5c
301 #define WCD934X_CDC_RX1_RX_PATH_SEC0 0x0b5d
302 #define WCD934X_CDC_RX1_RX_PATH_SEC3 0x0b60
303 #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2)
304 #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125 0x14
305 #define WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0
306 #define WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL 0x0b67
307 #define WCD934X_CDC_RX2_RX_PATH_CTL 0x0b69
308 #define WCD934X_CDC_RX2_RX_PATH_CFG0 0x0b6a
309 #define WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2)
310 #define WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2)
311 #define WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE 0
312 #define WCD934X_CDC_RX2_RX_PATH_CFG2 0x0b6c
313 #define WCD934X_CDC_RX2_RX_VOL_CTL 0x0b6d
314 #define WCD934X_CDC_RX2_RX_PATH_MIX_CTL 0x0b6e
315 #define WCD934X_CDC_RX2_RX_PATH_MIX_CFG 0x0b6f
316 #define WCD934X_CDC_RX2_RX_VOL_MIX_CTL 0x0b70
317 #define WCD934X_CDC_RX2_RX_PATH_SEC0 0x0b71
318 #define WCD934X_CDC_RX2_RX_PATH_SEC3 0x0b74
319 #define WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL 0x0b7b
320 #define WCD934X_CDC_RX3_RX_PATH_CTL 0x0b7d
321 #define WCD934X_CDC_RX3_RX_PATH_CFG0 0x0b6e
322 #define WCD934X_CDC_RX3_RX_PATH_CFG2 0x0b80
323 #define WCD934X_CDC_RX3_RX_VOL_CTL 0x0b81
324 #define WCD934X_CDC_RX3_RX_PATH_MIX_CTL 0x0b82
325 #define WCD934X_CDC_RX3_RX_PATH_MIX_CFG 0x0b83
326 #define WCD934X_CDC_RX3_RX_VOL_MIX_CTL 0x0b84
327 #define WCD934X_CDC_RX3_RX_PATH_SEC0 0x0b85
328 #define WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL 0x0b8f
329 #define WCD934X_CDC_RX4_RX_PATH_CTL 0x0b91
330 #define WCD934X_CDC_RX4_RX_PATH_CFG0 0x0b92
331 #define WCD934X_CDC_RX4_RX_PATH_CFG2 0x0b94
332 #define WCD934X_CDC_RX4_RX_VOL_CTL 0x0b95
333 #define WCD934X_CDC_RX4_RX_PATH_MIX_CTL 0x0b96
334 #define WCD934X_CDC_RX4_RX_PATH_MIX_CFG 0x0b97
335 #define WCD934X_CDC_RX4_RX_VOL_MIX_CTL 0x0b98
336 #define WCD934X_CDC_RX4_RX_PATH_SEC0 0x0b99
337 #define WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL 0x0ba3
338 #define WCD934X_CDC_RX7_RX_PATH_CTL 0x0bcd
339 #define WCD934X_CDC_RX7_RX_PATH_CFG0 0x0bce
340 #define WCD934X_CDC_RX7_RX_PATH_CFG1 0x0bcf
341 #define WCD934X_CDC_RX7_RX_PATH_CFG2 0x0bd0
342 #define WCD934X_CDC_RX7_RX_VOL_CTL 0x0bd1
343 #define WCD934X_CDC_RX7_RX_PATH_MIX_CTL 0x0bd2
344 #define WCD934X_CDC_RX7_RX_PATH_MIX_CFG 0x0bd3
345 #define WCD934X_CDC_RX7_RX_VOL_MIX_CTL 0x0bd4
346 #define WCD934X_CDC_RX7_RX_PATH_SEC1 0x0bd6
347 #define WCD934X_CDC_RX7_RX_PATH_MIX_SEC0 0x0bdd
348 #define WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL 0x0bdf
349 #define WCD934X_CDC_RX8_RX_PATH_CTL 0x0be1
350 #define WCD934X_CDC_RX8_RX_PATH_CFG0 0x0be2
351 #define WCD934X_CDC_RX8_RX_PATH_CFG1 0x0be3
352 #define WCD934X_RX_SMART_BOOST_EN_MASK BIT(0)
353 #define WCD934X_RX_SMART_BOOST_ENABLE BIT(0)
354 #define WCD934X_RX_SMART_BOOST_DISABLE 0
355 #define WCD934X_CDC_RX8_RX_PATH_CFG2 0x0be4
356 #define WCD934X_CDC_RX8_RX_VOL_CTL 0x0be5
357 #define WCD934X_CDC_RX8_RX_PATH_MIX_CTL 0x0be6
358 #define WCD934X_CDC_RX8_RX_PATH_MIX_CFG 0x0be7
359 #define WCD934X_CDC_RX8_RX_VOL_MIX_CTL 0x0be8
360 #define WCD934X_CDC_RX8_RX_PATH_SEC1 0x0bea
361 #define WCD934X_CDC_RX8_RX_PATH_MIX_SEC0 0x0bf1
362 #define WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL 0x0bf3
363 #define WCD934X_CDC_CLSH_DECAY_CTRL 0x0c03
364 #define WCD934X_CDC_CLSH_K2_MSB 0x0c0a
365 #define WCD934X_CDC_CLSH_K2_LSB 0x0c0b
366 #define WCD934X_CDC_CLSH_TEST0 0x0c0f
367 #define WCD934X_CDC_BOOST0_BOOST_PATH_CTL 0x0c19
368 #define WCD934X_BOOST_PATH_CLK_EN_MASK BIT(4)
369 #define WCD934X_BOOST_PATH_CLK_ENABLE BIT(4)
370 #define WCD934X_BOOST_PATH_CLK_DISABLE 0
371 #define WCD934X_CDC_BOOST0_BOOST_CTL 0x0c1a
372 #define WCD934X_CDC_BOOST0_BOOST_CFG1 0x0c1b
373 #define WCD934X_CDC_BOOST0_BOOST_CFG2 0x0c1c
374 #define WCD934X_CDC_BOOST1_BOOST_PATH_CTL 0x0c21
375 #define WCD934X_CDC_BOOST1_BOOST_CTL 0x0c22
376 #define WCD934X_CDC_BOOST1_BOOST_CFG1 0x0c23
377 #define WCD934X_CDC_BOOST1_BOOST_CFG2 0x0c24
378 #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_0 0x0c91
379 #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_1 0x0c92
380 #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_2 0x0c93
381 #define WCD934X_SWR_AHB_BRIDGE_RD_DATA_3 0x0c94
382 #define WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS 0x0c96
383 #define WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL 0x0cb5
384 #define WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL 0x0cb9
385 #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0 0x0d01
386 #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(i) (0xd01 + i * 0x2)
387 #define WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0)
388 #define WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1 0x0d02
389 #define WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(i) (0xd02 + i * 0x2)
390 #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0 0x0d03
391 #define WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1 0x0d04
392 #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0 0x0d05
393 #define WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1 0x0d06
394 #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0 0x0d07
395 #define WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1 0x0d08
396 #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0 0x0d09
397 #define WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1 0x0d0a
398 #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0 0x0d0f
399 #define WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1 0x0d10
400 #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0 0x0d11
401 #define WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1 0x0d12
402 #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0 0x0d13
403 #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1 0x0d14
404 #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2 0x0d15
405 #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3 0x0d16
406 #define WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4 0x0d17
407 #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 0x0d18
408 #define WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1 0x0d19
409 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 0x0d1d
410 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 0x0d1e
411 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0 0x0d1f
412 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1 0x0d20
413 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0 0x0d21
414 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1 0x0d22
415 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0 0x0d23
416 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1 0x0d25
417 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 0x0d26
418 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0 0x0d27
419 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0 0x0d28
420 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0 0x0d29
421 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0 0x0d2a
422 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0 0x0d2b
423 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0 0x0d2c
424 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0 0x0d2d
425 #define WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0 0x0d2e
426 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0 0x0d31
427 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1 0x0d32
428 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2 0x0d33
429 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3 0x0d34
430 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0 0x0d35
431 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1 0x0d36
432 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2 0x0d37
433 #define WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3 0x0d38
434 #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0 0x0d3a
435 #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1 0x0d3b
436 #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2 0x0d3c
437 #define WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3 0x0d3d
438 #define WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL 0x0d41
439 #define WCD934X_CDC_MCLK_EN_MASK BIT(0)
440 #define WCD934X_CDC_MCLK_EN_ENABLE BIT(0)
441 #define WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL 0x0d42
442 #define WCD934X_CDC_FS_MCLK_CNT_EN_MASK BIT(0)
443 #define WCD934X_CDC_FS_MCLK_CNT_ENABLE BIT(0)
444 #define WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL 0x0d43
445 #define WCD934X_CDC_SWR_CLK_EN_MASK BIT(0)
446 #define WCD934X_CDC_SWR_CLK_ENABLE BIT(0)
447 #define WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL 0x0d44
448 #define WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL 0x0d45
449 #define WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL 0x0d46
450 #define WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL 0x0d55
451 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL 0x0d56
452 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL 0x0d57
453 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL 0x0d58
454 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL 0x0d59
455 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL 0x0d5a
456 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL 0x0d5b
457 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL 0x0d5c
458 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL 0x0d5d
459 #define WCD934X_CDC_SIDETONE_IIR0_IIR_CTL 0x0d5e
460 #define WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL 0x0d5f
461 #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL 0x0d60
462 #define WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL 0x0d61
463 #define WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL 0x0d65
464 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL 0x0d66
465 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL 0x0d67
466 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL 0x0d68
467 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL 0x0d69
468 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL 0x0d6a
469 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL 0x0d6b
470 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL 0x0d6c
471 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL 0x0d6d
472 #define WCD934X_CDC_SIDETONE_IIR1_IIR_CTL 0x0d6e
473 #define WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL 0x0d6f
474 #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL 0x0d70
475 #define WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL 0x0d71
476 #define WCD934X_CDC_TOP_TOP_CFG1 0x0d82
477 #define WCD934X_CDC_TOP_TOP_CFG7 0x0d88
478 #define WCD934X_CDC_TOP_HPHL_COMP_LUT 0x0d8b
479 #define WCD934X_CDC_TOP_HPHR_COMP_LUT 0x0d90
480 #define WCD934X_HPH_LUT_BYPASS_MASK BIT(7)
481 #define WCD934X_HPH_LUT_BYPASS_ENABLE BIT(7)
482 #define WCD934X_HPH_LUT_BYPASS_DISABLE 0
483 #define WCD934X_CODEC_CPR_WR_DATA_0 0x5001
484 #define WCD934X_CODEC_CPR_WR_ADDR_0 0x5005
485 #define WCD934X_CODEC_CPR_SVS_CX_VDD 0x5022
486 #define WCD934X_CODEC_CPR_SVS2_CX_VDD 0x5023
487 #define WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD 0x5027
488 #define WCD934X_TLMM_DMIC1_CLK_PINCFG 0x8015
489 #define WCD934X_TLMM_DMIC1_DATA_PINCFG 0x8016
490 #define WCD934X_TLMM_DMIC2_CLK_PINCFG 0x8017
491 #define WCD934X_TLMM_DMIC2_DATA_PINCFG 0x8018
492 #define WCD934X_TLMM_DMIC3_CLK_PINCFG 0x8019
493 #define WCD934X_TLMM_DMIC3_DATA_PINCFG 0x801a
494 #define WCD934X_TEST_DEBUG_PAD_DRVCTL_0 0x803b
495 #define WCD934X_TEST_DEBUG_NPL_DLY_TEST_1 0x803e
497 #define WCD934X_MAX_REGISTER 0xffff
498 #define WCD934X_SEL_REGISTER 0x800
499 #define WCD934X_SEL_MASK 0xff
500 #define WCD934X_SEL_SHIFT 0x0
501 #define WCD934X_WINDOW_START 0x800
502 #define WCD934X_WINDOW_LENGTH 0x100
504 /* SLIMBUS Slave Registers */
505 #define WCD934X_SLIM_PGD_PORT_INT_EN0 0x30
506 #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0 0x34
507 #define WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_1 0x35
508 #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_0 0x36
509 #define WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1 0x37
510 #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 0x38
511 #define WCD934X_SLIM_PGD_PORT_INT_CLR_RX_1 0x39
512 #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_0 0x3A
513 #define WCD934X_SLIM_PGD_PORT_INT_CLR_TX_1 0x3B
514 #define WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 0x60
515 #define WCD934X_SLIM_PGD_PORT_INT_TX_SOURCE0 0x70
516 #define WCD934X_SLIM_PGD_RX_PORT_CFG(p) (0x30 + p)
517 #define WCD934X_SLIM_PGD_PORT_CFG(p) (0x40 + p)
518 #define WCD934X_SLIM_PGD_TX_PORT_CFG(p) (0x50 + p)
519 #define WCD934X_SLIM_PGD_PORT_INT_SRC(p) (0x60 + p)
520 #define WCD934X_SLIM_PGD_PORT_INT_STATUS(p) (0x80 + p)
521 #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) (0x100 + 4 * p)
522 /* ports range from 10-16 */
523 #define WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) (0x101 + 4 * p)
524 #define WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) (0x140 + 4 * p)
526 #define SLIM_MANF_ID_QCOM 0x217
527 #define SLIM_PROD_CODE_WCD9340 0x250
528 #define SLIM_DEV_IDX_WCD9340 0x1
529 #define SLIM_DEV_INSTANCE_ID_WCD9340 0