include/linux/mfd/rk808.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Register definitions for Rockchip's RK808/RK818 PMIC
   4  *
   5  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   6  *
   7  * Author: Chris Zhong <zyw@rock-chips.com>
   8  * Author: Zhang Qing <zhangqing@rock-chips.com>
   9  *
  10  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
  11  *
  12  * Author: Wadim Egorov <w.egorov@phytec.de>
  13  */
  14
  15 #ifndef __LINUX_REGULATOR_RK808_H
  16 #define __LINUX_REGULATOR_RK808_H
  17
  18 #include <linux/regulator/machine.h>
  19 #include <linux/regmap.h>
  20
  21 /*
  22  * rk808 Global Register Map.
  23  */
  24
  25 #define RK808_DCDC1     0 /* (0+RK808_START) */
  26 #define RK808_LDO1      4 /* (4+RK808_START) */
  27 #define RK808_NUM_REGULATORS    14
  28
  29 enum rk808_reg {
  30         RK808_ID_DCDC1,
  31         RK808_ID_DCDC2,
  32         RK808_ID_DCDC3,
  33         RK808_ID_DCDC4,
  34         RK808_ID_LDO1,
  35         RK808_ID_LDO2,
  36         RK808_ID_LDO3,
  37         RK808_ID_LDO4,
  38         RK808_ID_LDO5,
  39         RK808_ID_LDO6,
  40         RK808_ID_LDO7,
  41         RK808_ID_LDO8,
  42         RK808_ID_SWITCH1,
  43         RK808_ID_SWITCH2,
  44 };
  45
  46 #define RK808_SECONDS_REG       0x00
  47 #define RK808_MINUTES_REG       0x01
  48 #define RK808_HOURS_REG         0x02
  49 #define RK808_DAYS_REG          0x03
  50 #define RK808_MONTHS_REG        0x04
  51 #define RK808_YEARS_REG         0x05
  52 #define RK808_WEEKS_REG         0x06
  53 #define RK808_ALARM_SECONDS_REG 0x08
  54 #define RK808_ALARM_MINUTES_REG 0x09
  55 #define RK808_ALARM_HOURS_REG   0x0a
  56 #define RK808_ALARM_DAYS_REG    0x0b
  57 #define RK808_ALARM_MONTHS_REG  0x0c
  58 #define RK808_ALARM_YEARS_REG   0x0d
  59 #define RK808_RTC_CTRL_REG      0x10
  60 #define RK808_RTC_STATUS_REG    0x11
  61 #define RK808_RTC_INT_REG       0x12
  62 #define RK808_RTC_COMP_LSB_REG  0x13
  63 #define RK808_RTC_COMP_MSB_REG  0x14
  64 #define RK808_ID_MSB            0x17
  65 #define RK808_ID_LSB            0x18
  66 #define RK808_CLK32OUT_REG      0x20
  67 #define RK808_VB_MON_REG        0x21
  68 #define RK808_THERMAL_REG       0x22
  69 #define RK808_DCDC_EN_REG       0x23
  70 #define RK808_LDO_EN_REG        0x24
  71 #define RK808_SLEEP_SET_OFF_REG1        0x25
  72 #define RK808_SLEEP_SET_OFF_REG2        0x26
  73 #define RK808_DCDC_UV_STS_REG   0x27
  74 #define RK808_DCDC_UV_ACT_REG   0x28
  75 #define RK808_LDO_UV_STS_REG    0x29
  76 #define RK808_LDO_UV_ACT_REG    0x2a
  77 #define RK808_DCDC_PG_REG       0x2b
  78 #define RK808_LDO_PG_REG        0x2c
  79 #define RK808_VOUT_MON_TDB_REG  0x2d
  80 #define RK808_BUCK1_CONFIG_REG          0x2e
  81 #define RK808_BUCK1_ON_VSEL_REG         0x2f
  82 #define RK808_BUCK1_SLP_VSEL_REG        0x30
  83 #define RK808_BUCK1_DVS_VSEL_REG        0x31
  84 #define RK808_BUCK2_CONFIG_REG          0x32
  85 #define RK808_BUCK2_ON_VSEL_REG         0x33
  86 #define RK808_BUCK2_SLP_VSEL_REG        0x34
  87 #define RK808_BUCK2_DVS_VSEL_REG        0x35
  88 #define RK808_BUCK3_CONFIG_REG          0x36
  89 #define RK808_BUCK4_CONFIG_REG          0x37
  90 #define RK808_BUCK4_ON_VSEL_REG         0x38
  91 #define RK808_BUCK4_SLP_VSEL_REG        0x39
  92 #define RK808_BOOST_CONFIG_REG          0x3a
  93 #define RK808_LDO1_ON_VSEL_REG          0x3b
  94 #define RK808_LDO1_SLP_VSEL_REG         0x3c
  95 #define RK808_LDO2_ON_VSEL_REG          0x3d
  96 #define RK808_LDO2_SLP_VSEL_REG         0x3e
  97 #define RK808_LDO3_ON_VSEL_REG          0x3f
  98 #define RK808_LDO3_SLP_VSEL_REG         0x40
  99 #define RK808_LDO4_ON_VSEL_REG          0x41
 100 #define RK808_LDO4_SLP_VSEL_REG         0x42
 101 #define RK808_LDO5_ON_VSEL_REG          0x43
 102 #define RK808_LDO5_SLP_VSEL_REG         0x44
 103 #define RK808_LDO6_ON_VSEL_REG          0x45
 104 #define RK808_LDO6_SLP_VSEL_REG         0x46
 105 #define RK808_LDO7_ON_VSEL_REG          0x47
 106 #define RK808_LDO7_SLP_VSEL_REG         0x48
 107 #define RK808_LDO8_ON_VSEL_REG          0x49
 108 #define RK808_LDO8_SLP_VSEL_REG         0x4a
 109 #define RK808_DEVCTRL_REG       0x4b
 110 #define RK808_INT_STS_REG1      0x4c
 111 #define RK808_INT_STS_MSK_REG1  0x4d
 112 #define RK808_INT_STS_REG2      0x4e
 113 #define RK808_INT_STS_MSK_REG2  0x4f
 114 #define RK808_IO_POL_REG        0x50
 115
 116 /* RK818 */
 117 #define RK818_DCDC1                     0
 118 #define RK818_LDO1                      4
 119 #define RK818_NUM_REGULATORS            17
 120
 121 enum rk818_reg {
 122         RK818_ID_DCDC1,
 123         RK818_ID_DCDC2,
 124         RK818_ID_DCDC3,
 125         RK818_ID_DCDC4,
 126         RK818_ID_BOOST,
 127         RK818_ID_LDO1,
 128         RK818_ID_LDO2,
 129         RK818_ID_LDO3,
 130         RK818_ID_LDO4,
 131         RK818_ID_LDO5,
 132         RK818_ID_LDO6,
 133         RK818_ID_LDO7,
 134         RK818_ID_LDO8,
 135         RK818_ID_LDO9,
 136         RK818_ID_SWITCH,
 137         RK818_ID_HDMI_SWITCH,
 138         RK818_ID_OTG_SWITCH,
 139 };
 140
 141 #define RK818_DCDC_EN_REG               0x23
 142 #define RK818_LDO_EN_REG                0x24
 143 #define RK818_SLEEP_SET_OFF_REG1        0x25
 144 #define RK818_SLEEP_SET_OFF_REG2        0x26
 145 #define RK818_DCDC_UV_STS_REG           0x27
 146 #define RK818_DCDC_UV_ACT_REG           0x28
 147 #define RK818_LDO_UV_STS_REG            0x29
 148 #define RK818_LDO_UV_ACT_REG            0x2a
 149 #define RK818_DCDC_PG_REG               0x2b
 150 #define RK818_LDO_PG_REG                0x2c
 151 #define RK818_VOUT_MON_TDB_REG          0x2d
 152 #define RK818_BUCK1_CONFIG_REG          0x2e
 153 #define RK818_BUCK1_ON_VSEL_REG         0x2f
 154 #define RK818_BUCK1_SLP_VSEL_REG        0x30
 155 #define RK818_BUCK2_CONFIG_REG          0x32
 156 #define RK818_BUCK2_ON_VSEL_REG         0x33
 157 #define RK818_BUCK2_SLP_VSEL_REG        0x34
 158 #define RK818_BUCK3_CONFIG_REG          0x36
 159 #define RK818_BUCK4_CONFIG_REG          0x37
 160 #define RK818_BUCK4_ON_VSEL_REG         0x38
 161 #define RK818_BUCK4_SLP_VSEL_REG        0x39
 162 #define RK818_BOOST_CONFIG_REG          0x3a
 163 #define RK818_LDO1_ON_VSEL_REG          0x3b
 164 #define RK818_LDO1_SLP_VSEL_REG         0x3c
 165 #define RK818_LDO2_ON_VSEL_REG          0x3d
 166 #define RK818_LDO2_SLP_VSEL_REG         0x3e
 167 #define RK818_LDO3_ON_VSEL_REG          0x3f
 168 #define RK818_LDO3_SLP_VSEL_REG         0x40
 169 #define RK818_LDO4_ON_VSEL_REG          0x41
 170 #define RK818_LDO4_SLP_VSEL_REG         0x42
 171 #define RK818_LDO5_ON_VSEL_REG          0x43
 172 #define RK818_LDO5_SLP_VSEL_REG         0x44
 173 #define RK818_LDO6_ON_VSEL_REG          0x45
 174 #define RK818_LDO6_SLP_VSEL_REG         0x46
 175 #define RK818_LDO7_ON_VSEL_REG          0x47
 176 #define RK818_LDO7_SLP_VSEL_REG         0x48
 177 #define RK818_LDO8_ON_VSEL_REG          0x49
 178 #define RK818_LDO8_SLP_VSEL_REG         0x4a
 179 #define RK818_BOOST_LDO9_ON_VSEL_REG    0x54
 180 #define RK818_BOOST_LDO9_SLP_VSEL_REG   0x55
 181 #define RK818_DEVCTRL_REG               0x4b
 182 #define RK818_INT_STS_REG1              0X4c
 183 #define RK818_INT_STS_MSK_REG1          0x4d
 184 #define RK818_INT_STS_REG2              0x4e
 185 #define RK818_INT_STS_MSK_REG2          0x4f
 186 #define RK818_IO_POL_REG                0x50
 187 #define RK818_H5V_EN_REG                0x52
 188 #define RK818_SLEEP_SET_OFF_REG3        0x53
 189 #define RK818_BOOST_LDO9_ON_VSEL_REG    0x54
 190 #define RK818_BOOST_LDO9_SLP_VSEL_REG   0x55
 191 #define RK818_BOOST_CTRL_REG            0x56
 192 #define RK818_DCDC_ILMAX                0x90
 193 #define RK818_USB_CTRL_REG              0xa1
 194
 195 #define RK818_H5V_EN                    BIT(0)
 196 #define RK818_REF_RDY_CTRL              BIT(1)
 197 #define RK818_USB_ILIM_SEL_MASK         0xf
 198 #define RK818_USB_ILMIN_2000MA          0x7
 199 #define RK818_USB_CHG_SD_VSEL_MASK      0x70
 200
 201 /* RK805 */
 202 enum rk805_reg {
 203         RK805_ID_DCDC1,
 204         RK805_ID_DCDC2,
 205         RK805_ID_DCDC3,
 206         RK805_ID_DCDC4,
 207         RK805_ID_LDO1,
 208         RK805_ID_LDO2,
 209         RK805_ID_LDO3,
 210 };
 211
 212 /* CONFIG REGISTER */
 213 #define RK805_VB_MON_REG                0x21
 214 #define RK805_THERMAL_REG               0x22
 215
 216 /* POWER CHANNELS ENABLE REGISTER */
 217 #define RK805_DCDC_EN_REG               0x23
 218 #define RK805_SLP_DCDC_EN_REG           0x25
 219 #define RK805_SLP_LDO_EN_REG            0x26
 220 #define RK805_LDO_EN_REG                0x27
 221
 222 /* BUCK AND LDO CONFIG REGISTER */
 223 #define RK805_BUCK_LDO_SLP_LP_EN_REG    0x2A
 224 #define RK805_BUCK1_CONFIG_REG          0x2E
 225 #define RK805_BUCK1_ON_VSEL_REG         0x2F
 226 #define RK805_BUCK1_SLP_VSEL_REG        0x30
 227 #define RK805_BUCK2_CONFIG_REG          0x32
 228 #define RK805_BUCK2_ON_VSEL_REG         0x33
 229 #define RK805_BUCK2_SLP_VSEL_REG        0x34
 230 #define RK805_BUCK3_CONFIG_REG          0x36
 231 #define RK805_BUCK4_CONFIG_REG          0x37
 232 #define RK805_BUCK4_ON_VSEL_REG         0x38
 233 #define RK805_BUCK4_SLP_VSEL_REG        0x39
 234 #define RK805_LDO1_ON_VSEL_REG          0x3B
 235 #define RK805_LDO1_SLP_VSEL_REG         0x3C
 236 #define RK805_LDO2_ON_VSEL_REG          0x3D
 237 #define RK805_LDO2_SLP_VSEL_REG         0x3E
 238 #define RK805_LDO3_ON_VSEL_REG          0x3F
 239 #define RK805_LDO3_SLP_VSEL_REG         0x40
 240
 241 /* INTERRUPT REGISTER */
 242 #define RK805_PWRON_LP_INT_TIME_REG     0x47
 243 #define RK805_PWRON_DB_REG              0x48
 244 #define RK805_DEV_CTRL_REG              0x4B
 245 #define RK805_INT_STS_REG               0x4C
 246 #define RK805_INT_STS_MSK_REG           0x4D
 247 #define RK805_GPIO_IO_POL_REG           0x50
 248 #define RK805_OUT_REG                   0x52
 249 #define RK805_ON_SOURCE_REG             0xAE
 250 #define RK805_OFF_SOURCE_REG            0xAF
 251
 252 #define RK805_NUM_REGULATORS            7
 253
 254 #define RK805_PWRON_FALL_RISE_INT_EN    0x0
 255 #define RK805_PWRON_FALL_RISE_INT_MSK   0x81
 256
 257 /* RK805 IRQ Definitions */
 258 #define RK805_IRQ_PWRON_RISE            0
 259 #define RK805_IRQ_VB_LOW                1
 260 #define RK805_IRQ_PWRON                 2
 261 #define RK805_IRQ_PWRON_LP              3
 262 #define RK805_IRQ_HOTDIE                4
 263 #define RK805_IRQ_RTC_ALARM             5
 264 #define RK805_IRQ_RTC_PERIOD            6
 265 #define RK805_IRQ_PWRON_FALL            7
 266
 267 #define RK805_IRQ_PWRON_RISE_MSK        BIT(0)
 268 #define RK805_IRQ_VB_LOW_MSK            BIT(1)
 269 #define RK805_IRQ_PWRON_MSK             BIT(2)
 270 #define RK805_IRQ_PWRON_LP_MSK          BIT(3)
 271 #define RK805_IRQ_HOTDIE_MSK            BIT(4)
 272 #define RK805_IRQ_RTC_ALARM_MSK         BIT(5)
 273 #define RK805_IRQ_RTC_PERIOD_MSK        BIT(6)
 274 #define RK805_IRQ_PWRON_FALL_MSK        BIT(7)
 275
 276 #define RK805_PWR_RISE_INT_STATUS       BIT(0)
 277 #define RK805_VB_LOW_INT_STATUS         BIT(1)
 278 #define RK805_PWRON_INT_STATUS          BIT(2)
 279 #define RK805_PWRON_LP_INT_STATUS       BIT(3)
 280 #define RK805_HOTDIE_INT_STATUS         BIT(4)
 281 #define RK805_ALARM_INT_STATUS          BIT(5)
 282 #define RK805_PERIOD_INT_STATUS         BIT(6)
 283 #define RK805_PWR_FALL_INT_STATUS       BIT(7)
 284
 285 #define RK805_BUCK1_2_ILMAX_MASK        (3 << 6)
 286 #define RK805_BUCK3_4_ILMAX_MASK        (3 << 3)
 287 #define RK805_RTC_PERIOD_INT_MASK       (1 << 6)
 288 #define RK805_RTC_ALARM_INT_MASK        (1 << 5)
 289 #define RK805_INT_ALARM_EN              (1 << 3)
 290 #define RK805_INT_TIMER_EN              (1 << 2)
 291
 292 /* RK808 IRQ Definitions */
 293 #define RK808_IRQ_VOUT_LO       0
 294 #define RK808_IRQ_VB_LO         1
 295 #define RK808_IRQ_PWRON         2
 296 #define RK808_IRQ_PWRON_LP      3
 297 #define RK808_IRQ_HOTDIE        4
 298 #define RK808_IRQ_RTC_ALARM     5
 299 #define RK808_IRQ_RTC_PERIOD    6
 300 #define RK808_IRQ_PLUG_IN_INT   7
 301 #define RK808_IRQ_PLUG_OUT_INT  8
 302 #define RK808_NUM_IRQ           9
 303
 304 #define RK808_IRQ_VOUT_LO_MSK           BIT(0)
 305 #define RK808_IRQ_VB_LO_MSK             BIT(1)
 306 #define RK808_IRQ_PWRON_MSK             BIT(2)
 307 #define RK808_IRQ_PWRON_LP_MSK          BIT(3)
 308 #define RK808_IRQ_HOTDIE_MSK            BIT(4)
 309 #define RK808_IRQ_RTC_ALARM_MSK         BIT(5)
 310 #define RK808_IRQ_RTC_PERIOD_MSK        BIT(6)
 311 #define RK808_IRQ_PLUG_IN_INT_MSK       BIT(0)
 312 #define RK808_IRQ_PLUG_OUT_INT_MSK      BIT(1)
 313
 314 /* RK818 IRQ Definitions */
 315 #define RK818_IRQ_VOUT_LO       0
 316 #define RK818_IRQ_VB_LO         1
 317 #define RK818_IRQ_PWRON         2
 318 #define RK818_IRQ_PWRON_LP      3
 319 #define RK818_IRQ_HOTDIE        4
 320 #define RK818_IRQ_RTC_ALARM     5
 321 #define RK818_IRQ_RTC_PERIOD    6
 322 #define RK818_IRQ_USB_OV        7
 323 #define RK818_IRQ_PLUG_IN       8
 324 #define RK818_IRQ_PLUG_OUT      9
 325 #define RK818_IRQ_CHG_OK        10
 326 #define RK818_IRQ_CHG_TE        11
 327 #define RK818_IRQ_CHG_TS1       12
 328 #define RK818_IRQ_TS2           13
 329 #define RK818_IRQ_CHG_CVTLIM    14
 330 #define RK818_IRQ_DISCHG_ILIM   15
 331
 332 #define RK818_IRQ_VOUT_LO_MSK           BIT(0)
 333 #define RK818_IRQ_VB_LO_MSK             BIT(1)
 334 #define RK818_IRQ_PWRON_MSK             BIT(2)
 335 #define RK818_IRQ_PWRON_LP_MSK          BIT(3)
 336 #define RK818_IRQ_HOTDIE_MSK            BIT(4)
 337 #define RK818_IRQ_RTC_ALARM_MSK         BIT(5)
 338 #define RK818_IRQ_RTC_PERIOD_MSK        BIT(6)
 339 #define RK818_IRQ_USB_OV_MSK            BIT(7)
 340 #define RK818_IRQ_PLUG_IN_MSK           BIT(0)
 341 #define RK818_IRQ_PLUG_OUT_MSK          BIT(1)
 342 #define RK818_IRQ_CHG_OK_MSK            BIT(2)
 343 #define RK818_IRQ_CHG_TE_MSK            BIT(3)
 344 #define RK818_IRQ_CHG_TS1_MSK           BIT(4)
 345 #define RK818_IRQ_TS2_MSK               BIT(5)
 346 #define RK818_IRQ_CHG_CVTLIM_MSK        BIT(6)
 347 #define RK818_IRQ_DISCHG_ILIM_MSK       BIT(7)
 348
 349 #define RK818_NUM_IRQ           16
 350
 351 #define RK808_VBAT_LOW_2V8      0x00
 352 #define RK808_VBAT_LOW_2V9      0x01
 353 #define RK808_VBAT_LOW_3V0      0x02
 354 #define RK808_VBAT_LOW_3V1      0x03
 355 #define RK808_VBAT_LOW_3V2      0x04
 356 #define RK808_VBAT_LOW_3V3      0x05
 357 #define RK808_VBAT_LOW_3V4      0x06
 358 #define RK808_VBAT_LOW_3V5      0x07
 359 #define VBAT_LOW_VOL_MASK       (0x07 << 0)
 360 #define EN_VABT_LOW_SHUT_DOWN   (0x00 << 4)
 361 #define EN_VBAT_LOW_IRQ         (0x1 << 4)
 362 #define VBAT_LOW_ACT_MASK       (0x1 << 4)
 363
 364 #define BUCK_ILMIN_MASK         (7 << 0)
 365 #define BOOST_ILMIN_MASK        (7 << 0)
 366 #define BUCK1_RATE_MASK         (3 << 3)
 367 #define BUCK2_RATE_MASK         (3 << 3)
 368 #define MASK_ALL        0xff
 369
 370 #define BUCK_UV_ACT_MASK        0x0f
 371 #define BUCK_UV_ACT_DISABLE     0
 372
 373 #define SWITCH2_EN      BIT(6)
 374 #define SWITCH1_EN      BIT(5)
 375 #define DEV_OFF_RST     BIT(3)
 376 #define DEV_RST         BIT(2)
 377 #define DEV_OFF         BIT(0)
 378 #define RTC_STOP        BIT(0)
 379
 380 #define VB_LO_ACT               BIT(4)
 381 #define VB_LO_SEL_3500MV        (7 << 0)
 382
 383 #define VOUT_LO_INT     BIT(0)
 384 #define CLK32KOUT2_EN   BIT(0)
 385
 386 #define TEMP115C                        0x0c
 387 #define TEMP_HOTDIE_MSK                 0x0c
 388 #define SLP_SD_MSK                      (0x3 << 2)
 389 #define SHUTDOWN_FUN                    (0x2 << 2)
 390 #define SLEEP_FUN                       (0x1 << 2)
 391 #define RK8XX_ID_MSK                    0xfff0
 392 #define PWM_MODE_MSK                    BIT(7)
 393 #define FPWM_MODE                       BIT(7)
 394 #define AUTO_PWM_MODE                   0
 395
 396 enum rk817_reg_id {
 397         RK817_ID_DCDC1 = 0,
 398         RK817_ID_DCDC2,
 399         RK817_ID_DCDC3,
 400         RK817_ID_DCDC4,
 401         RK817_ID_LDO1,
 402         RK817_ID_LDO2,
 403         RK817_ID_LDO3,
 404         RK817_ID_LDO4,
 405         RK817_ID_LDO5,
 406         RK817_ID_LDO6,
 407         RK817_ID_LDO7,
 408         RK817_ID_LDO8,
 409         RK817_ID_LDO9,
 410         RK817_ID_BOOST,
 411         RK817_ID_BOOST_OTG_SW,
 412         RK817_NUM_REGULATORS
 413 };
 414
 415 enum rk809_reg_id {
 416         RK809_ID_DCDC5 = RK817_ID_BOOST,
 417         RK809_ID_SW1,
 418         RK809_ID_SW2,
 419         RK809_NUM_REGULATORS
 420 };
 421
 422 #define RK817_SECONDS_REG               0x00
 423 #define RK817_MINUTES_REG               0x01
 424 #define RK817_HOURS_REG                 0x02
 425 #define RK817_DAYS_REG                  0x03
 426 #define RK817_MONTHS_REG                0x04
 427 #define RK817_YEARS_REG                 0x05
 428 #define RK817_WEEKS_REG                 0x06
 429 #define RK817_ALARM_SECONDS_REG         0x07
 430 #define RK817_ALARM_MINUTES_REG         0x08
 431 #define RK817_ALARM_HOURS_REG           0x09
 432 #define RK817_ALARM_DAYS_REG            0x0a
 433 #define RK817_ALARM_MONTHS_REG          0x0b
 434 #define RK817_ALARM_YEARS_REG           0x0c
 435 #define RK817_RTC_CTRL_REG              0xd
 436 #define RK817_RTC_STATUS_REG            0xe
 437 #define RK817_RTC_INT_REG               0xf
 438 #define RK817_RTC_COMP_LSB_REG          0x10
 439 #define RK817_RTC_COMP_MSB_REG          0x11
 440
 441 /* RK817 Codec Registers */
 442 #define RK817_CODEC_DTOP_VUCTL          0x12
 443 #define RK817_CODEC_DTOP_VUCTIME        0x13
 444 #define RK817_CODEC_DTOP_LPT_SRST       0x14
 445 #define RK817_CODEC_DTOP_DIGEN_CLKE     0x15
 446 #define RK817_CODEC_AREF_RTCFG0         0x16
 447 #define RK817_CODEC_AREF_RTCFG1         0x17
 448 #define RK817_CODEC_AADC_CFG0           0x18
 449 #define RK817_CODEC_AADC_CFG1           0x19
 450 #define RK817_CODEC_DADC_VOLL           0x1a
 451 #define RK817_CODEC_DADC_VOLR           0x1b
 452 #define RK817_CODEC_DADC_SR_ACL0        0x1e
 453 #define RK817_CODEC_DADC_ALC1           0x1f
 454 #define RK817_CODEC_DADC_ALC2           0x20
 455 #define RK817_CODEC_DADC_NG             0x21
 456 #define RK817_CODEC_DADC_HPF            0x22
 457 #define RK817_CODEC_DADC_RVOLL          0x23
 458 #define RK817_CODEC_DADC_RVOLR          0x24
 459 #define RK817_CODEC_AMIC_CFG0           0x27
 460 #define RK817_CODEC_AMIC_CFG1           0x28
 461 #define RK817_CODEC_DMIC_PGA_GAIN       0x29
 462 #define RK817_CODEC_DMIC_LMT1           0x2a
 463 #define RK817_CODEC_DMIC_LMT2           0x2b
 464 #define RK817_CODEC_DMIC_NG1            0x2c
 465 #define RK817_CODEC_DMIC_NG2            0x2d
 466 #define RK817_CODEC_ADAC_CFG0           0x2e
 467 #define RK817_CODEC_ADAC_CFG1           0x2f
 468 #define RK817_CODEC_DDAC_POPD_DACST     0x30
 469 #define RK817_CODEC_DDAC_VOLL           0x31
 470 #define RK817_CODEC_DDAC_VOLR           0x32
 471 #define RK817_CODEC_DDAC_SR_LMT0        0x35
 472 #define RK817_CODEC_DDAC_LMT1           0x36
 473 #define RK817_CODEC_DDAC_LMT2           0x37
 474 #define RK817_CODEC_DDAC_MUTE_MIXCTL    0x38
 475 #define RK817_CODEC_DDAC_RVOLL          0x39
 476 #define RK817_CODEC_DDAC_RVOLR          0x3a
 477 #define RK817_CODEC_AHP_ANTI0           0x3b
 478 #define RK817_CODEC_AHP_ANTI1           0x3c
 479 #define RK817_CODEC_AHP_CFG0            0x3d
 480 #define RK817_CODEC_AHP_CFG1            0x3e
 481 #define RK817_CODEC_AHP_CP              0x3f
 482 #define RK817_CODEC_ACLASSD_CFG1        0x40
 483 #define RK817_CODEC_ACLASSD_CFG2        0x41
 484 #define RK817_CODEC_APLL_CFG0           0x42
 485 #define RK817_CODEC_APLL_CFG1           0x43
 486 #define RK817_CODEC_APLL_CFG2           0x44
 487 #define RK817_CODEC_APLL_CFG3           0x45
 488 #define RK817_CODEC_APLL_CFG4           0x46
 489 #define RK817_CODEC_APLL_CFG5           0x47
 490 #define RK817_CODEC_DI2S_CKM            0x48
 491 #define RK817_CODEC_DI2S_RSD            0x49
 492 #define RK817_CODEC_DI2S_RXCR1          0x4a
 493 #define RK817_CODEC_DI2S_RXCR2          0x4b
 494 #define RK817_CODEC_DI2S_RXCMD_TSD      0x4c
 495 #define RK817_CODEC_DI2S_TXCR1          0x4d
 496 #define RK817_CODEC_DI2S_TXCR2          0x4e
 497 #define RK817_CODEC_DI2S_TXCR3_TXCMD    0x4f
 498
 499 /* RK817_CODEC_DI2S_CKM */
 500 #define RK817_I2S_MODE_MASK             (0x1 << 0)
 501 #define RK817_I2S_MODE_MST              (0x1 << 0)
 502 #define RK817_I2S_MODE_SLV              (0x0 << 0)
 503
 504 /* RK817_CODEC_DDAC_MUTE_MIXCTL */
 505 #define DACMT_MASK                      (0x1 << 0)
 506 #define DACMT_ENABLE                    (0x1 << 0)
 507 #define DACMT_DISABLE                   (0x0 << 0)
 508
 509 /* RK817_CODEC_DI2S_RXCR2 */
 510 #define VDW_RX_24BITS                   (0x17)
 511 #define VDW_RX_16BITS                   (0x0f)
 512
 513 /* RK817_CODEC_DI2S_TXCR2 */
 514 #define VDW_TX_24BITS                   (0x17)
 515 #define VDW_TX_16BITS                   (0x0f)
 516
 517 /* RK817_CODEC_AMIC_CFG0 */
 518 #define MIC_DIFF_MASK                   (0x1 << 7)
 519 #define MIC_DIFF_DIS                    (0x0 << 7)
 520 #define MIC_DIFF_EN                     (0x1 << 7)
 521
 522 #define RK817_POWER_EN_REG(i)           (0xb1 + (i))
 523 #define RK817_POWER_SLP_EN_REG(i)       (0xb5 + (i))
 524
 525 #define RK817_POWER_CONFIG              (0xb9)
 526
 527 #define RK817_BUCK_CONFIG_REG(i)        (0xba + (i) * 3)
 528
 529 #define RK817_BUCK1_ON_VSEL_REG         0xBB
 530 #define RK817_BUCK1_SLP_VSEL_REG        0xBC
 531
 532 #define RK817_BUCK2_CONFIG_REG          0xBD
 533 #define RK817_BUCK2_ON_VSEL_REG         0xBE
 534 #define RK817_BUCK2_SLP_VSEL_REG        0xBF
 535
 536 #define RK817_BUCK3_CONFIG_REG          0xC0
 537 #define RK817_BUCK3_ON_VSEL_REG         0xC1
 538 #define RK817_BUCK3_SLP_VSEL_REG        0xC2
 539
 540 #define RK817_BUCK4_CONFIG_REG          0xC3
 541 #define RK817_BUCK4_ON_VSEL_REG         0xC4
 542 #define RK817_BUCK4_SLP_VSEL_REG        0xC5
 543
 544 #define RK817_LDO_ON_VSEL_REG(idx)      (0xcc + (idx) * 2)
 545 #define RK817_BOOST_OTG_CFG             (0xde)
 546
 547 #define RK817_ID_MSB                    0xed
 548 #define RK817_ID_LSB                    0xee
 549
 550 #define RK817_SYS_STS                   0xf0
 551 #define RK817_SYS_CFG(i)                (0xf1 + (i))
 552
 553 #define RK817_ON_SOURCE_REG             0xf5
 554 #define RK817_OFF_SOURCE_REG            0xf6
 555
 556 /* INTERRUPT REGISTER */
 557 #define RK817_INT_STS_REG0              0xf8
 558 #define RK817_INT_STS_MSK_REG0          0xf9
 559 #define RK817_INT_STS_REG1              0xfa
 560 #define RK817_INT_STS_MSK_REG1          0xfb
 561 #define RK817_INT_STS_REG2              0xfc
 562 #define RK817_INT_STS_MSK_REG2          0xfd
 563 #define RK817_GPIO_INT_CFG              0xfe
 564
 565 /* IRQ Definitions */
 566 #define RK817_IRQ_PWRON_FALL            0
 567 #define RK817_IRQ_PWRON_RISE            1
 568 #define RK817_IRQ_PWRON                 2
 569 #define RK817_IRQ_PWMON_LP              3
 570 #define RK817_IRQ_HOTDIE                4
 571 #define RK817_IRQ_RTC_ALARM             5
 572 #define RK817_IRQ_RTC_PERIOD            6
 573 #define RK817_IRQ_VB_LO                 7
 574 #define RK817_IRQ_PLUG_IN               8
 575 #define RK817_IRQ_PLUG_OUT              9
 576 #define RK817_IRQ_CHRG_TERM             10
 577 #define RK817_IRQ_CHRG_TIME             11
 578 #define RK817_IRQ_CHRG_TS               12
 579 #define RK817_IRQ_USB_OV                13
 580 #define RK817_IRQ_CHRG_IN_CLMP          14
 581 #define RK817_IRQ_BAT_DIS_ILIM          15
 582 #define RK817_IRQ_GATE_GPIO             16
 583 #define RK817_IRQ_TS_GPIO               17
 584 #define RK817_IRQ_CODEC_PD              18
 585 #define RK817_IRQ_CODEC_PO              19
 586 #define RK817_IRQ_CLASSD_MUTE_DONE      20
 587 #define RK817_IRQ_CLASSD_OCP            21
 588 #define RK817_IRQ_BAT_OVP               22
 589 #define RK817_IRQ_CHRG_BAT_HI           23
 590 #define RK817_IRQ_END                   (RK817_IRQ_CHRG_BAT_HI + 1)
 591
 592 /*
 593  * rtc_ctrl 0xd
 594  * same as 808, except bit4
 595  */
 596 #define RK817_RTC_CTRL_RSV4             BIT(4)
 597
 598 /* power config 0xb9 */
 599 #define RK817_BUCK3_FB_RES_MSK          BIT(6)
 600 #define RK817_BUCK3_FB_RES_INTER        BIT(6)
 601 #define RK817_BUCK3_FB_RES_EXT          0
 602
 603 /* buck config 0xba */
 604 #define RK817_RAMP_RATE_OFFSET          6
 605 #define RK817_RAMP_RATE_MASK            (0x3 << RK817_RAMP_RATE_OFFSET)
 606 #define RK817_RAMP_RATE_3MV_PER_US      (0x0 << RK817_RAMP_RATE_OFFSET)
 607 #define RK817_RAMP_RATE_6_3MV_PER_US    (0x1 << RK817_RAMP_RATE_OFFSET)
 608 #define RK817_RAMP_RATE_12_5MV_PER_US   (0x2 << RK817_RAMP_RATE_OFFSET)
 609 #define RK817_RAMP_RATE_25MV_PER_US     (0x3 << RK817_RAMP_RATE_OFFSET)
 610
 611 /* sys_cfg1 0xf2 */
 612 #define RK817_HOTDIE_TEMP_MSK           (0x3 << 4)
 613 #define RK817_HOTDIE_85                 (0x0 << 4)
 614 #define RK817_HOTDIE_95                 (0x1 << 4)
 615 #define RK817_HOTDIE_105                (0x2 << 4)
 616 #define RK817_HOTDIE_115                (0x3 << 4)
 617
 618 #define RK817_TSD_TEMP_MSK              BIT(6)
 619 #define RK817_TSD_140                   0
 620 #define RK817_TSD_160                   BIT(6)
 621
 622 #define RK817_CLK32KOUT2_EN             BIT(7)
 623
 624 /* sys_cfg3 0xf4 */
 625 #define RK817_SLPPIN_FUNC_MSK           (0x3 << 3)
 626 #define SLPPIN_NULL_FUN                 (0x0 << 3)
 627 #define SLPPIN_SLP_FUN                  (0x1 << 3)
 628 #define SLPPIN_DN_FUN                   (0x2 << 3)
 629 #define SLPPIN_RST_FUN                  (0x3 << 3)
 630
 631 #define RK817_RST_FUNC_MSK              (0x3 << 6)
 632 #define RK817_RST_FUNC_SFT              (6)
 633 #define RK817_RST_FUNC_CNT              (3)
 634 #define RK817_RST_FUNC_DEV              (0) /* reset the dev */
 635 #define RK817_RST_FUNC_REG              (0x1 << 6) /* reset the reg only */
 636
 637 #define RK817_SLPPOL_MSK                BIT(5)
 638 #define RK817_SLPPOL_H                  BIT(5)
 639 #define RK817_SLPPOL_L                  (0)
 640
 641 /* gpio&int 0xfe */
 642 #define RK817_INT_POL_MSK               BIT(1)
 643 #define RK817_INT_POL_H                 BIT(1)
 644 #define RK817_INT_POL_L                 0
 645 #define RK809_BUCK5_CONFIG(i)           (RK817_BOOST_OTG_CFG + (i) * 1)
 646
 647 enum {
 648         BUCK_ILMIN_50MA,
 649         BUCK_ILMIN_100MA,
 650         BUCK_ILMIN_150MA,
 651         BUCK_ILMIN_200MA,
 652         BUCK_ILMIN_250MA,
 653         BUCK_ILMIN_300MA,
 654         BUCK_ILMIN_350MA,
 655         BUCK_ILMIN_400MA,
 656 };
 657
 658 enum {
 659         BOOST_ILMIN_75MA,
 660         BOOST_ILMIN_100MA,
 661         BOOST_ILMIN_125MA,
 662         BOOST_ILMIN_150MA,
 663         BOOST_ILMIN_175MA,
 664         BOOST_ILMIN_200MA,
 665         BOOST_ILMIN_225MA,
 666         BOOST_ILMIN_250MA,
 667 };
 668
 669 enum {
 670         RK805_BUCK1_2_ILMAX_2500MA,
 671         RK805_BUCK1_2_ILMAX_3000MA,
 672         RK805_BUCK1_2_ILMAX_3500MA,
 673         RK805_BUCK1_2_ILMAX_4000MA,
 674 };
 675
 676 enum {
 677         RK805_BUCK3_ILMAX_1500MA,
 678         RK805_BUCK3_ILMAX_2000MA,
 679         RK805_BUCK3_ILMAX_2500MA,
 680         RK805_BUCK3_ILMAX_3000MA,
 681 };
 682
 683 enum {
 684         RK805_BUCK4_ILMAX_2000MA,
 685         RK805_BUCK4_ILMAX_2500MA,
 686         RK805_BUCK4_ILMAX_3000MA,
 687         RK805_BUCK4_ILMAX_3500MA,
 688 };
 689
 690 enum {
 691         RK805_ID = 0x8050,
 692         RK808_ID = 0x0000,
 693         RK809_ID = 0x8090,
 694         RK817_ID = 0x8170,
 695         RK818_ID = 0x8180,
 696 };
 697
 698 struct rk808 {
 699         struct i2c_client               *i2c;
 700         struct regmap_irq_chip_data     *irq_data;
 701         struct regmap                   *regmap;
 702         long                            variant;
 703         const struct regmap_config      *regmap_cfg;
 704         const struct regmap_irq_chip    *regmap_irq_chip;
 705 };
 706 #endif /* __LINUX_REGULATOR_RK808_H */