include/linux/mfd/lochnagar1_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Lochnagar1 register definitions
   4  *
   5  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
   6  *                         Cirrus Logic International Semiconductor Ltd.
   7  *
   8  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
   9  */
  10
  11 #ifndef LOCHNAGAR1_REGISTERS_H
  12 #define LOCHNAGAR1_REGISTERS_H
  13
  14 /* Register Addresses */
  15 #define LOCHNAGAR1_CDC_AIF1_SEL                       0x0008
  16 #define LOCHNAGAR1_CDC_AIF2_SEL                       0x0009
  17 #define LOCHNAGAR1_CDC_AIF3_SEL                       0x000A
  18 #define LOCHNAGAR1_CDC_MCLK1_SEL                      0x000B
  19 #define LOCHNAGAR1_CDC_MCLK2_SEL                      0x000C
  20 #define LOCHNAGAR1_CDC_AIF_CTRL1                      0x000D
  21 #define LOCHNAGAR1_CDC_AIF_CTRL2                      0x000E
  22 #define LOCHNAGAR1_EXT_AIF_CTRL                       0x000F
  23 #define LOCHNAGAR1_DSP_AIF1_SEL                       0x0010
  24 #define LOCHNAGAR1_DSP_AIF2_SEL                       0x0011
  25 #define LOCHNAGAR1_DSP_CLKIN_SEL                      0x0012
  26 #define LOCHNAGAR1_DSP_AIF                            0x0013
  27 #define LOCHNAGAR1_GF_AIF1                            0x0014
  28 #define LOCHNAGAR1_GF_AIF2                            0x0015
  29 #define LOCHNAGAR1_PSIA_AIF                           0x0016
  30 #define LOCHNAGAR1_PSIA1_SEL                          0x0017
  31 #define LOCHNAGAR1_PSIA2_SEL                          0x0018
  32 #define LOCHNAGAR1_SPDIF_AIF_SEL                      0x0019
  33 #define LOCHNAGAR1_GF_AIF3_SEL                        0x001C
  34 #define LOCHNAGAR1_GF_AIF4_SEL                        0x001D
  35 #define LOCHNAGAR1_GF_CLKOUT1_SEL                     0x001E
  36 #define LOCHNAGAR1_GF_AIF1_SEL                        0x001F
  37 #define LOCHNAGAR1_GF_AIF2_SEL                        0x0020
  38 #define LOCHNAGAR1_GF_GPIO2                           0x0026
  39 #define LOCHNAGAR1_GF_GPIO3                           0x0027
  40 #define LOCHNAGAR1_GF_GPIO7                           0x0028
  41 #define LOCHNAGAR1_RST                                0x0029
  42 #define LOCHNAGAR1_LED1                               0x002A
  43 #define LOCHNAGAR1_LED2                               0x002B
  44 #define LOCHNAGAR1_I2C_CTRL                           0x0046
  45
  46 /*
  47  * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020)
  48  * CDC_AIF1_SEL - GF_AIF2_SEL
  49  */
  50 #define LOCHNAGAR1_SRC_MASK                             0xFF
  51 #define LOCHNAGAR1_SRC_SHIFT                               0
  52
  53 /* (0x000D)  CDC_AIF_CTRL1 */
  54 #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK              0x40
  55 #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT                6
  56 #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK               0x20
  57 #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT                 5
  58 #define LOCHNAGAR1_CDC_AIF2_ENA_MASK                    0x10
  59 #define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT                      4
  60 #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK              0x04
  61 #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT                2
  62 #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK               0x02
  63 #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT                 1
  64 #define LOCHNAGAR1_CDC_AIF1_ENA_MASK                    0x01
  65 #define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT                      0
  66
  67 /* (0x000E)  CDC_AIF_CTRL2 */
  68 #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK              0x40
  69 #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT                6
  70 #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK               0x20
  71 #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT                 5
  72 #define LOCHNAGAR1_CDC_AIF3_ENA_MASK                    0x10
  73 #define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT                      4
  74 #define LOCHNAGAR1_CDC_MCLK1_ENA_MASK                   0x02
  75 #define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT                     1
  76 #define LOCHNAGAR1_CDC_MCLK2_ENA_MASK                   0x01
  77 #define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT                     0
  78
  79 /* (0x000F)  EXT_AIF_CTRL */
  80 #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK             0x20
  81 #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT               5
  82 #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK              0x10
  83 #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT                4
  84 #define LOCHNAGAR1_SPDIF_AIF_ENA_MASK                   0x08
  85 #define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT                     3
  86
  87 /* (0x0013)  DSP_AIF */
  88 #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK              0x40
  89 #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT                6
  90 #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK               0x20
  91 #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT                 5
  92 #define LOCHNAGAR1_DSP_AIF2_ENA_MASK                    0x10
  93 #define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT                      4
  94 #define LOCHNAGAR1_DSP_CLKIN_ENA_MASK                   0x08
  95 #define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT                     3
  96 #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK              0x04
  97 #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT                2
  98 #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK               0x02
  99 #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT                 1
 100 #define LOCHNAGAR1_DSP_AIF1_ENA_MASK                    0x01
 101 #define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT                      0
 102
 103 /* (0x0014)  GF_AIF1 */
 104 #define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK                  0x40
 105 #define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT                    6
 106 #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK               0x20
 107 #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT                 5
 108 #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK                0x10
 109 #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT                  4
 110 #define LOCHNAGAR1_GF_AIF3_ENA_MASK                     0x08
 111 #define LOCHNAGAR1_GF_AIF3_ENA_SHIFT                       3
 112 #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK               0x04
 113 #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT                 2
 114 #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK                0x02
 115 #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT                  1
 116 #define LOCHNAGAR1_GF_AIF1_ENA_MASK                     0x01
 117 #define LOCHNAGAR1_GF_AIF1_ENA_SHIFT                       0
 118
 119 /* (0x0015)  GF_AIF2 */
 120 #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK               0x20
 121 #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT                 5
 122 #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK                0x10
 123 #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT                  4
 124 #define LOCHNAGAR1_GF_AIF4_ENA_MASK                     0x08
 125 #define LOCHNAGAR1_GF_AIF4_ENA_SHIFT                       3
 126 #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK               0x04
 127 #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT                 2
 128 #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK                0x02
 129 #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT                  1
 130 #define LOCHNAGAR1_GF_AIF2_ENA_MASK                     0x01
 131 #define LOCHNAGAR1_GF_AIF2_ENA_SHIFT                       0
 132
 133 /* (0x0016)  PSIA_AIF */
 134 #define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK                 0x40
 135 #define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT                   6
 136 #define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK                  0x20
 137 #define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT                    5
 138 #define LOCHNAGAR1_PSIA2_ENA_MASK                       0x10
 139 #define LOCHNAGAR1_PSIA2_ENA_SHIFT                         4
 140 #define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK                 0x04
 141 #define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT                   2
 142 #define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK                  0x02
 143 #define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT                    1
 144 #define LOCHNAGAR1_PSIA1_ENA_MASK                       0x01
 145 #define LOCHNAGAR1_PSIA1_ENA_SHIFT                         0
 146
 147 /* (0x0029)  RST */
 148 #define LOCHNAGAR1_DSP_RESET_MASK                       0x02
 149 #define LOCHNAGAR1_DSP_RESET_SHIFT                         1
 150 #define LOCHNAGAR1_CDC_RESET_MASK                       0x01
 151 #define LOCHNAGAR1_CDC_RESET_SHIFT                         0
 152
 153 /* (0x0046)  I2C_CTRL */
 154 #define LOCHNAGAR1_CDC_CIF_MODE_MASK                    0x01
 155 #define LOCHNAGAR1_CDC_CIF_MODE_SHIFT                      0
 156
 157 #endif