1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) ST Ericsson SA 2011
10 #include <linux/interrupt.h>
11 #include <linux/notifier.h>
12 #include <linux/err.h>
14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
16 /* Offset for the firmware version within the TCPM */
17 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
18 #define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
20 /* PRCMU Wakeup defines */
21 enum prcmu_wakeup_index {
22 PRCMU_WAKEUP_INDEX_RTC,
23 PRCMU_WAKEUP_INDEX_RTT0,
24 PRCMU_WAKEUP_INDEX_RTT1,
25 PRCMU_WAKEUP_INDEX_HSI0,
26 PRCMU_WAKEUP_INDEX_HSI1,
27 PRCMU_WAKEUP_INDEX_USB,
28 PRCMU_WAKEUP_INDEX_ABB,
29 PRCMU_WAKEUP_INDEX_ABB_FIFO,
30 PRCMU_WAKEUP_INDEX_ARM,
31 PRCMU_WAKEUP_INDEX_CD_IRQ,
32 NUM_PRCMU_WAKEUP_INDICES
34 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
36 /* EPOD (power domain) IDs */
40 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
41 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
42 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
43 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
44 * - EPOD_ID_SGA: power domain for SGA
45 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
46 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
47 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
48 * - NUM_EPOD_ID: number of power domains
50 * TODO: These should be prefixed.
52 #define EPOD_ID_SVAMMDSP 0
53 #define EPOD_ID_SVAPIPE 1
54 #define EPOD_ID_SIAMMDSP 2
55 #define EPOD_ID_SIAPIPE 3
57 #define EPOD_ID_B2R2_MCDE 5
58 #define EPOD_ID_ESRAM12 6
59 #define EPOD_ID_ESRAM34 7
63 * state definition for EPOD (power domain)
64 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
65 * - EPOD_STATE_OFF: The EPOD is switched off
66 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
68 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
69 * - EPOD_STATE_ON: Same as above, but with clock enabled
71 #define EPOD_STATE_NO_CHANGE 0x00
72 #define EPOD_STATE_OFF 0x01
73 #define EPOD_STATE_RAMRET 0x02
74 #define EPOD_STATE_ON_CLK_OFF 0x03
75 #define EPOD_STATE_ON 0x04
80 #define PRCMU_CLKSRC_CLK38M 0x00
81 #define PRCMU_CLKSRC_ACLK 0x01
82 #define PRCMU_CLKSRC_SYSCLK 0x02
83 #define PRCMU_CLKSRC_LCDCLK 0x03
84 #define PRCMU_CLKSRC_SDMMCCLK 0x04
85 #define PRCMU_CLKSRC_TVCLK 0x05
86 #define PRCMU_CLKSRC_TIMCLK 0x06
87 #define PRCMU_CLKSRC_CLK009 0x07
88 /* These are only valid for CLKOUT1: */
89 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
90 #define PRCMU_CLKSRC_I2CCLK 0x41
91 #define PRCMU_CLKSRC_MSP02CLK 0x42
92 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
93 #define PRCMU_CLKSRC_HSIRXCLK 0x44
94 #define PRCMU_CLKSRC_HSITXCLK 0x45
95 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
96 #define PRCMU_CLKSRC_HDMICLK 0x47
99 * enum prcmu_wdog_id - PRCMU watchdog IDs
100 * @PRCMU_WDOG_ALL: use all timers
101 * @PRCMU_WDOG_CPU1: use first CPU timer only
102 * @PRCMU_WDOG_CPU2: use second CPU timer conly
105 PRCMU_WDOG_ALL = 0x00,
106 PRCMU_WDOG_CPU1 = 0x01,
107 PRCMU_WDOG_CPU2 = 0x02,
111 * enum ape_opp - APE OPP states definition
113 * @APE_NO_CHANGE: The APE operating point is unchanged
114 * @APE_100_OPP: The new APE operating point is ape100opp
116 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
120 APE_NO_CHANGE = 0x01,
123 APE_50_PARTLY_25_OPP = 0xFF,
127 * enum arm_opp - ARM OPP states definition
129 * @ARM_NO_CHANGE: The ARM operating point is unchanged
130 * @ARM_100_OPP: The new ARM operating point is arm100opp
131 * @ARM_50_OPP: The new ARM operating point is arm50opp
132 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
133 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
134 * @ARM_EXTCLK: The new ARM operating point is armExtClk
138 ARM_NO_CHANGE = 0x01,
142 ARM_MAX_FREQ100OPP = 0x05,
147 * enum ddr_opp - DDR OPP states definition
148 * @DDR_100_OPP: The new DDR operating point is ddr100opp
149 * @DDR_50_OPP: The new DDR operating point is ddr50opp
150 * @DDR_25_OPP: The new DDR operating point is ddr25opp
159 * Definitions for controlling ESRAM0 in deep sleep.
161 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
162 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
165 * enum ddr_pwrst - DDR power states definition
166 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
168 * @DDR_PWR_STATE_OFFLOWLAT:
169 * @DDR_PWR_STATE_OFFHIGHLAT:
172 DDR_PWR_STATE_UNCHANGED = 0x00,
173 DDR_PWR_STATE_ON = 0x01,
174 DDR_PWR_STATE_OFFLOWLAT = 0x02,
175 DDR_PWR_STATE_OFFHIGHLAT = 0x03
178 #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
180 #define PRCMU_FW_PROJECT_U8500 2
181 #define PRCMU_FW_PROJECT_U8400 3
182 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
183 #define PRCMU_FW_PROJECT_U8500_MBB 5
184 #define PRCMU_FW_PROJECT_U8500_C1 6
185 #define PRCMU_FW_PROJECT_U8500_C2 7
186 #define PRCMU_FW_PROJECT_U8500_C3 8
187 #define PRCMU_FW_PROJECT_U8500_C4 9
188 #define PRCMU_FW_PROJECT_U9500_MBL 10
189 #define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
190 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
191 #define PRCMU_FW_PROJECT_U8520 13
192 #define PRCMU_FW_PROJECT_U8420 14
193 #define PRCMU_FW_PROJECT_A9420 20
194 /* [32..63] 9540 and derivatives */
195 #define PRCMU_FW_PROJECT_U9540 32
196 /* [64..95] 8540 and derivatives */
197 #define PRCMU_FW_PROJECT_L8540 64
198 /* [96..126] 8580 and derivatives */
199 #define PRCMU_FW_PROJECT_L8580 96
201 #define PRCMU_FW_PROJECT_NAME_LEN 20
202 struct prcmu_fw_version {
203 u32 project; /* Notice, project shifted with 8 on ux540 */
207 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
210 #include <linux/mfd/db8500-prcmu.h>
212 #if defined(CONFIG_UX500_SOC_DB8500)
214 static inline void prcmu_early_init(u32 phy_base, u32 size)
216 return db8500_prcmu_early_init(phy_base, size);
219 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
222 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
226 static inline u8 prcmu_get_power_state_result(void)
228 return db8500_prcmu_get_power_state_result();
231 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
233 return db8500_prcmu_set_epod(epod_id, epod_state);
236 static inline void prcmu_enable_wakeups(u32 wakeups)
238 db8500_prcmu_enable_wakeups(wakeups);
241 static inline void prcmu_disable_wakeups(void)
243 prcmu_enable_wakeups(0);
246 static inline void prcmu_config_abb_event_readout(u32 abb_events)
248 db8500_prcmu_config_abb_event_readout(abb_events);
251 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
253 db8500_prcmu_get_abb_event_buffer(buf);
256 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
257 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
258 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
260 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
262 static inline int prcmu_request_clock(u8 clock, bool enable)
264 return db8500_prcmu_request_clock(clock, enable);
267 unsigned long prcmu_clock_rate(u8 clock);
268 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
269 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
271 static inline int prcmu_get_ddr_opp(void)
273 return db8500_prcmu_get_ddr_opp();
276 static inline int prcmu_set_arm_opp(u8 opp)
278 return db8500_prcmu_set_arm_opp(opp);
281 static inline int prcmu_get_arm_opp(void)
283 return db8500_prcmu_get_arm_opp();
286 static inline int prcmu_set_ape_opp(u8 opp)
288 return db8500_prcmu_set_ape_opp(opp);
291 static inline int prcmu_get_ape_opp(void)
293 return db8500_prcmu_get_ape_opp();
296 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
298 return db8500_prcmu_request_ape_opp_100_voltage(enable);
301 static inline void prcmu_system_reset(u16 reset_code)
303 return db8500_prcmu_system_reset(reset_code);
306 static inline u16 prcmu_get_reset_code(void)
308 return db8500_prcmu_get_reset_code();
311 int prcmu_ac_wake_req(void);
312 void prcmu_ac_sleep_req(void);
313 static inline void prcmu_modem_reset(void)
315 return db8500_prcmu_modem_reset();
318 static inline bool prcmu_is_ac_wake_requested(void)
320 return db8500_prcmu_is_ac_wake_requested();
323 static inline int prcmu_set_display_clocks(void)
325 return db8500_prcmu_set_display_clocks();
328 static inline int prcmu_disable_dsipll(void)
330 return db8500_prcmu_disable_dsipll();
333 static inline int prcmu_enable_dsipll(void)
335 return db8500_prcmu_enable_dsipll();
338 static inline int prcmu_config_esram0_deep_sleep(u8 state)
340 return db8500_prcmu_config_esram0_deep_sleep(state);
343 static inline int prcmu_config_hotdog(u8 threshold)
345 return db8500_prcmu_config_hotdog(threshold);
348 static inline int prcmu_config_hotmon(u8 low, u8 high)
350 return db8500_prcmu_config_hotmon(low, high);
353 static inline int prcmu_start_temp_sense(u16 cycles32k)
355 return db8500_prcmu_start_temp_sense(cycles32k);
358 static inline int prcmu_stop_temp_sense(void)
360 return db8500_prcmu_stop_temp_sense();
363 static inline u32 prcmu_read(unsigned int reg)
365 return db8500_prcmu_read(reg);
368 static inline void prcmu_write(unsigned int reg, u32 value)
370 db8500_prcmu_write(reg, value);
373 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
375 db8500_prcmu_write_masked(reg, mask, value);
378 static inline int prcmu_enable_a9wdog(u8 id)
380 return db8500_prcmu_enable_a9wdog(id);
383 static inline int prcmu_disable_a9wdog(u8 id)
385 return db8500_prcmu_disable_a9wdog(id);
388 static inline int prcmu_kick_a9wdog(u8 id)
390 return db8500_prcmu_kick_a9wdog(id);
393 static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
395 return db8500_prcmu_load_a9wdog(id, timeout);
398 static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
400 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
404 static inline void prcmu_early_init(u32 phy_base, u32 size) {}
406 static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
412 static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
417 static inline void prcmu_enable_wakeups(u32 wakeups) {}
419 static inline void prcmu_disable_wakeups(void) {}
421 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
426 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
431 static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
437 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
442 static inline int prcmu_request_clock(u8 clock, bool enable)
447 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
452 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
457 static inline unsigned long prcmu_clock_rate(u8 clock)
462 static inline int prcmu_set_ape_opp(u8 opp)
467 static inline int prcmu_get_ape_opp(void)
472 static inline int prcmu_request_ape_opp_100_voltage(bool enable)
477 static inline int prcmu_set_arm_opp(u8 opp)
482 static inline int prcmu_get_arm_opp(void)
487 static inline int prcmu_get_ddr_opp(void)
492 static inline void prcmu_system_reset(u16 reset_code) {}
494 static inline u16 prcmu_get_reset_code(void)
499 static inline int prcmu_ac_wake_req(void)
504 static inline void prcmu_ac_sleep_req(void) {}
506 static inline void prcmu_modem_reset(void) {}
508 static inline bool prcmu_is_ac_wake_requested(void)
513 static inline int prcmu_set_display_clocks(void)
518 static inline int prcmu_disable_dsipll(void)
523 static inline int prcmu_enable_dsipll(void)
528 static inline int prcmu_config_esram0_deep_sleep(u8 state)
533 static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
535 static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
540 static inline int prcmu_config_hotdog(u8 threshold)
545 static inline int prcmu_config_hotmon(u8 low, u8 high)
550 static inline int prcmu_start_temp_sense(u16 cycles32k)
555 static inline int prcmu_stop_temp_sense(void)
560 static inline u32 prcmu_read(unsigned int reg)
565 static inline void prcmu_write(unsigned int reg, u32 value) {}
567 static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
571 static inline void prcmu_set(unsigned int reg, u32 bits)
573 prcmu_write_masked(reg, bits, bits);
576 static inline void prcmu_clear(unsigned int reg, u32 bits)
578 prcmu_write_masked(reg, bits, 0);
581 /* PRCMU QoS APE OPP class */
582 #define PRCMU_QOS_APE_OPP 1
583 #define PRCMU_QOS_DDR_OPP 2
584 #define PRCMU_QOS_ARM_OPP 3
585 #define PRCMU_QOS_DEFAULT_VALUE -1
587 #ifdef CONFIG_DBX500_PRCMU_QOS_POWER
589 unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
590 void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
591 void prcmu_qos_force_opp(int, s32);
592 int prcmu_qos_requirement(int pm_qos_class);
593 int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
594 int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
595 void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
596 int prcmu_qos_add_notifier(int prcmu_qos_class,
597 struct notifier_block *notifier);
598 int prcmu_qos_remove_notifier(int prcmu_qos_class,
599 struct notifier_block *notifier);
603 static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
608 static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
610 static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
612 static inline int prcmu_qos_requirement(int prcmu_qos_class)
617 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
618 char *name, s32 value)
623 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
624 char *name, s32 new_value)
629 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
633 static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
634 struct notifier_block *notifier)
638 static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
639 struct notifier_block *notifier)
646 #endif /* __MACH_PRCMU_H */