2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
22 * Distributor registers. We assume we're running non-secure, with ARE
23 * being set. Secure-only and non-ARE registers are not described.
25 #define GICD_CTLR 0x0000
26 #define GICD_TYPER 0x0004
27 #define GICD_IIDR 0x0008
28 #define GICD_STATUSR 0x0010
29 #define GICD_SETSPI_NSR 0x0040
30 #define GICD_CLRSPI_NSR 0x0048
31 #define GICD_SETSPI_SR 0x0050
32 #define GICD_CLRSPI_SR 0x0058
33 #define GICD_SEIR 0x0068
34 #define GICD_IGROUPR 0x0080
35 #define GICD_ISENABLER 0x0100
36 #define GICD_ICENABLER 0x0180
37 #define GICD_ISPENDR 0x0200
38 #define GICD_ICPENDR 0x0280
39 #define GICD_ISACTIVER 0x0300
40 #define GICD_ICACTIVER 0x0380
41 #define GICD_IPRIORITYR 0x0400
42 #define GICD_ICFGR 0x0C00
43 #define GICD_IGRPMODR 0x0D00
44 #define GICD_NSACR 0x0E00
45 #define GICD_IROUTER 0x6000
46 #define GICD_IDREGS 0xFFD0
47 #define GICD_PIDR2 0xFFE8
50 * Those registers are actually from GICv2, but the spec demands that they
51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
53 #define GICD_ITARGETSR 0x0800
54 #define GICD_SGIR 0x0F00
55 #define GICD_CPENDSGIR 0x0F10
56 #define GICD_SPENDSGIR 0x0F20
58 #define GICD_CTLR_RWP (1U << 31)
59 #define GICD_CTLR_DS (1U << 6)
60 #define GICD_CTLR_ARE_NS (1U << 4)
61 #define GICD_CTLR_ENABLE_G1A (1U << 1)
62 #define GICD_CTLR_ENABLE_G1 (1U << 0)
65 * In systems with a single security state (what we emulate in KVM)
66 * the meaning of the interrupt group enable bits is slightly different
68 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
69 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
71 #define GICD_TYPER_RSS (1U << 26)
72 #define GICD_TYPER_LPIS (1U << 17)
73 #define GICD_TYPER_MBIS (1U << 16)
75 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
76 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
78 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
79 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
81 #define GIC_PIDR2_ARCH_MASK 0xf0
82 #define GIC_PIDR2_ARCH_GICv3 0x30
83 #define GIC_PIDR2_ARCH_GICv4 0x40
85 #define GIC_V3_DIST_SIZE 0x10000
88 * Re-Distributor registers, offsets from RD_base
90 #define GICR_CTLR GICD_CTLR
91 #define GICR_IIDR 0x0004
92 #define GICR_TYPER 0x0008
93 #define GICR_STATUSR GICD_STATUSR
94 #define GICR_WAKER 0x0014
95 #define GICR_SETLPIR 0x0040
96 #define GICR_CLRLPIR 0x0048
97 #define GICR_SEIR GICD_SEIR
98 #define GICR_PROPBASER 0x0070
99 #define GICR_PENDBASER 0x0078
100 #define GICR_INVLPIR 0x00A0
101 #define GICR_INVALLR 0x00B0
102 #define GICR_SYNCR 0x00C0
103 #define GICR_MOVLPIR 0x0100
104 #define GICR_MOVALLR 0x0110
105 #define GICR_IDREGS GICD_IDREGS
106 #define GICR_PIDR2 GICD_PIDR2
108 #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
109 #define GICR_CTLR_RWP (1UL << 3)
111 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
113 #define GICR_WAKER_ProcessorSleep (1U << 1)
114 #define GICR_WAKER_ChildrenAsleep (1U << 2)
116 #define GIC_BASER_CACHE_nCnB 0ULL
117 #define GIC_BASER_CACHE_SameAsInner 0ULL
118 #define GIC_BASER_CACHE_nC 1ULL
119 #define GIC_BASER_CACHE_RaWt 2ULL
120 #define GIC_BASER_CACHE_RaWb 3ULL
121 #define GIC_BASER_CACHE_WaWt 4ULL
122 #define GIC_BASER_CACHE_WaWb 5ULL
123 #define GIC_BASER_CACHE_RaWaWt 6ULL
124 #define GIC_BASER_CACHE_RaWaWb 7ULL
125 #define GIC_BASER_CACHE_MASK 7ULL
126 #define GIC_BASER_NonShareable 0ULL
127 #define GIC_BASER_InnerShareable 1ULL
128 #define GIC_BASER_OuterShareable 2ULL
129 #define GIC_BASER_SHAREABILITY_MASK 3ULL
131 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
132 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
134 #define GIC_BASER_SHAREABILITY(reg, type) \
135 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
137 /* encode a size field of width @w containing @n - 1 units */
138 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
140 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
141 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
142 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
143 #define GICR_PROPBASER_SHAREABILITY_MASK \
144 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
145 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
146 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
147 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
148 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
149 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
151 #define GICR_PROPBASER_InnerShareable \
152 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
154 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
155 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
156 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
157 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
158 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
159 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
160 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
161 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
163 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
164 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
165 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
167 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
168 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
169 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
170 #define GICR_PENDBASER_SHAREABILITY_MASK \
171 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
172 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
173 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
174 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
175 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
176 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
178 #define GICR_PENDBASER_InnerShareable \
179 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
181 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
182 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
183 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
184 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
185 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
186 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
187 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
188 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
190 #define GICR_PENDBASER_PTZ BIT_ULL(62)
193 * Re-Distributor registers, offsets from SGI_base
195 #define GICR_IGROUPR0 GICD_IGROUPR
196 #define GICR_ISENABLER0 GICD_ISENABLER
197 #define GICR_ICENABLER0 GICD_ICENABLER
198 #define GICR_ISPENDR0 GICD_ISPENDR
199 #define GICR_ICPENDR0 GICD_ICPENDR
200 #define GICR_ISACTIVER0 GICD_ISACTIVER
201 #define GICR_ICACTIVER0 GICD_ICACTIVER
202 #define GICR_IPRIORITYR0 GICD_IPRIORITYR
203 #define GICR_ICFGR0 GICD_ICFGR
204 #define GICR_IGRPMODR0 GICD_IGRPMODR
205 #define GICR_NSACR GICD_NSACR
207 #define GICR_TYPER_PLPIS (1U << 0)
208 #define GICR_TYPER_VLPIS (1U << 1)
209 #define GICR_TYPER_DirectLPIS (1U << 3)
210 #define GICR_TYPER_LAST (1U << 4)
212 #define GIC_V3_REDIST_SIZE 0x20000
214 #define LPI_PROP_GROUP1 (1 << 1)
215 #define LPI_PROP_ENABLED (1 << 0)
218 * Re-Distributor registers, offsets from VLPI_base
220 #define GICR_VPROPBASER 0x0070
222 #define GICR_VPROPBASER_IDBITS_MASK 0x1f
224 #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10)
225 #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7)
226 #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56)
228 #define GICR_VPROPBASER_SHAREABILITY_MASK \
229 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK)
230 #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \
231 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
232 #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \
233 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
234 #define GICR_VPROPBASER_CACHEABILITY_MASK \
235 GICR_VPROPBASER_INNER_CACHEABILITY_MASK
237 #define GICR_VPROPBASER_InnerShareable \
238 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable)
240 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
241 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
242 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
243 #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
244 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
245 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
246 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
247 #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
249 #define GICR_VPENDBASER 0x0078
251 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10)
252 #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7)
253 #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56)
254 #define GICR_VPENDBASER_SHAREABILITY_MASK \
255 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK)
256 #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \
257 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
258 #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \
259 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
260 #define GICR_VPENDBASER_CACHEABILITY_MASK \
261 GICR_VPENDBASER_INNER_CACHEABILITY_MASK
263 #define GICR_VPENDBASER_NonShareable \
264 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
266 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
267 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
268 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
269 #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
270 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
271 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
272 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
273 #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb)
275 #define GICR_VPENDBASER_Dirty (1ULL << 60)
276 #define GICR_VPENDBASER_PendingLast (1ULL << 61)
277 #define GICR_VPENDBASER_IDAI (1ULL << 62)
278 #define GICR_VPENDBASER_Valid (1ULL << 63)
281 * ITS registers, offsets from ITS_base
283 #define GITS_CTLR 0x0000
284 #define GITS_IIDR 0x0004
285 #define GITS_TYPER 0x0008
286 #define GITS_CBASER 0x0080
287 #define GITS_CWRITER 0x0088
288 #define GITS_CREADR 0x0090
289 #define GITS_BASER 0x0100
290 #define GITS_IDREGS_BASE 0xffd0
291 #define GITS_PIDR0 0xffe0
292 #define GITS_PIDR1 0xffe4
293 #define GITS_PIDR2 GICR_PIDR2
294 #define GITS_PIDR4 0xffd0
295 #define GITS_CIDR0 0xfff0
296 #define GITS_CIDR1 0xfff4
297 #define GITS_CIDR2 0xfff8
298 #define GITS_CIDR3 0xfffc
300 #define GITS_TRANSLATER 0x10040
302 #define GITS_CTLR_ENABLE (1U << 0)
303 #define GITS_CTLR_ImDe (1U << 1)
304 #define GITS_CTLR_ITS_NUMBER_SHIFT 4
305 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
306 #define GITS_CTLR_QUIESCENT (1U << 31)
308 #define GITS_TYPER_PLPIS (1UL << 0)
309 #define GITS_TYPER_VLPIS (1UL << 1)
310 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
311 #define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
312 #define GITS_TYPER_IDBITS_SHIFT 8
313 #define GITS_TYPER_DEVBITS_SHIFT 13
314 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
315 #define GITS_TYPER_PTA (1UL << 19)
316 #define GITS_TYPER_HCC_SHIFT 24
317 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
318 #define GITS_TYPER_VMOVP (1ULL << 37)
320 #define GITS_IIDR_REV_SHIFT 12
321 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
322 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
323 #define GITS_IIDR_PRODUCTID_SHIFT 24
325 #define GITS_CBASER_VALID (1ULL << 63)
326 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
327 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
328 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
329 #define GITS_CBASER_SHAREABILITY_MASK \
330 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
331 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
332 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
333 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \
334 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
335 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
337 #define GITS_CBASER_InnerShareable \
338 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
340 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
341 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
342 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
343 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
344 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
345 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
346 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
347 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
349 #define GITS_BASER_NR_REGS 8
351 #define GITS_BASER_VALID (1ULL << 63)
352 #define GITS_BASER_INDIRECT (1ULL << 62)
354 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
355 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
356 #define GITS_BASER_INNER_CACHEABILITY_MASK \
357 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
358 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
359 #define GITS_BASER_OUTER_CACHEABILITY_MASK \
360 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
361 #define GITS_BASER_SHAREABILITY_MASK \
362 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
364 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
365 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
366 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
367 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
368 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
369 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
370 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
371 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
373 #define GITS_BASER_TYPE_SHIFT (56)
374 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
375 #define GITS_BASER_ENTRY_SIZE_SHIFT (48)
376 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
377 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
378 #define GITS_BASER_PHYS_52_to_48(phys) \
379 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
380 #define GITS_BASER_SHAREABILITY_SHIFT (10)
381 #define GITS_BASER_InnerShareable \
382 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
383 #define GITS_BASER_PAGE_SIZE_SHIFT (8)
384 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
385 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
386 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
387 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
388 #define GITS_BASER_PAGES_MAX 256
389 #define GITS_BASER_PAGES_SHIFT (0)
390 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
392 #define GITS_BASER_TYPE_NONE 0
393 #define GITS_BASER_TYPE_DEVICE 1
394 #define GITS_BASER_TYPE_VCPU 2
395 #define GITS_BASER_TYPE_RESERVED3 3
396 #define GITS_BASER_TYPE_COLLECTION 4
397 #define GITS_BASER_TYPE_RESERVED5 5
398 #define GITS_BASER_TYPE_RESERVED6 6
399 #define GITS_BASER_TYPE_RESERVED7 7
401 #define GITS_LVL1_ENTRY_SIZE (8UL)
406 #define GITS_CMD_MAPD 0x08
407 #define GITS_CMD_MAPC 0x09
408 #define GITS_CMD_MAPTI 0x0a
409 #define GITS_CMD_MAPI 0x0b
410 #define GITS_CMD_MOVI 0x01
411 #define GITS_CMD_DISCARD 0x0f
412 #define GITS_CMD_INV 0x0c
413 #define GITS_CMD_MOVALL 0x0e
414 #define GITS_CMD_INVALL 0x0d
415 #define GITS_CMD_INT 0x03
416 #define GITS_CMD_CLEAR 0x04
417 #define GITS_CMD_SYNC 0x05
420 * GICv4 ITS specific commands
422 #define GITS_CMD_GICv4(x) ((x) | 0x20)
423 #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL)
424 #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC)
425 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
426 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
427 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
428 /* VMOVP is the odd one, as it doesn't have a physical counterpart */
429 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
434 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
435 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
436 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
437 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
438 #define E_ITS_MAPD_DEVICE_OOR 0x010801
439 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802
440 #define E_ITS_MAPC_PROCNUM_OOR 0x010902
441 #define E_ITS_MAPC_COLLECTION_OOR 0x010903
442 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
443 #define E_ITS_MAPTI_ID_OOR 0x010a05
444 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
445 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
446 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
447 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
448 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
451 * CPU interface registers
453 #define ICC_CTLR_EL1_EOImode_SHIFT (1)
454 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
455 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
456 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
457 #define ICC_CTLR_EL1_CBPR_SHIFT 0
458 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
459 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
460 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
461 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11
462 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
463 #define ICC_CTLR_EL1_SEIS_SHIFT 14
464 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
465 #define ICC_CTLR_EL1_A3V_SHIFT 15
466 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
467 #define ICC_CTLR_EL1_RSS (0x1 << 18)
468 #define ICC_PMR_EL1_SHIFT 0
469 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
470 #define ICC_BPR0_EL1_SHIFT 0
471 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
472 #define ICC_BPR1_EL1_SHIFT 0
473 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
474 #define ICC_IGRPEN0_EL1_SHIFT 0
475 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
476 #define ICC_IGRPEN1_EL1_SHIFT 0
477 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
478 #define ICC_SRE_EL1_DIB (1U << 2)
479 #define ICC_SRE_EL1_DFB (1U << 1)
480 #define ICC_SRE_EL1_SRE (1U << 0)
483 * Hypervisor interface registers (SRE only)
485 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
487 #define ICH_LR_EOI (1ULL << 41)
488 #define ICH_LR_GROUP (1ULL << 60)
489 #define ICH_LR_HW (1ULL << 61)
490 #define ICH_LR_STATE (3ULL << 62)
491 #define ICH_LR_PENDING_BIT (1ULL << 62)
492 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
493 #define ICH_LR_PHYS_ID_SHIFT 32
494 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
495 #define ICH_LR_PRIORITY_SHIFT 48
496 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
498 /* These are for GICv2 emulation only */
499 #define GICH_LR_VIRTUALID (0x3ffUL << 0)
500 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
501 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
503 #define ICH_MISR_EOI (1 << 0)
504 #define ICH_MISR_U (1 << 1)
506 #define ICH_HCR_EN (1 << 0)
507 #define ICH_HCR_UIE (1 << 1)
508 #define ICH_HCR_NPIE (1 << 3)
509 #define ICH_HCR_TC (1 << 10)
510 #define ICH_HCR_TALL0 (1 << 11)
511 #define ICH_HCR_TALL1 (1 << 12)
512 #define ICH_HCR_EOIcount_SHIFT 27
513 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
515 #define ICH_VMCR_ACK_CTL_SHIFT 2
516 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
517 #define ICH_VMCR_FIQ_EN_SHIFT 3
518 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
519 #define ICH_VMCR_CBPR_SHIFT 4
520 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
521 #define ICH_VMCR_EOIM_SHIFT 9
522 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
523 #define ICH_VMCR_BPR1_SHIFT 18
524 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
525 #define ICH_VMCR_BPR0_SHIFT 21
526 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
527 #define ICH_VMCR_PMR_SHIFT 24
528 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
529 #define ICH_VMCR_ENG0_SHIFT 0
530 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
531 #define ICH_VMCR_ENG1_SHIFT 1
532 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
534 #define ICH_VTR_PRI_BITS_SHIFT 29
535 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
536 #define ICH_VTR_ID_BITS_SHIFT 23
537 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
538 #define ICH_VTR_SEIS_SHIFT 22
539 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
540 #define ICH_VTR_A3V_SHIFT 21
541 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
543 #define ICC_IAR1_EL1_SPURIOUS 0x3ff
545 #define ICC_SRE_EL2_SRE (1 << 0)
546 #define ICC_SRE_EL2_ENABLE (1 << 3)
548 #define ICC_SGI1R_TARGET_LIST_SHIFT 0
549 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
550 #define ICC_SGI1R_AFFINITY_1_SHIFT 16
551 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
552 #define ICC_SGI1R_SGI_ID_SHIFT 24
553 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
554 #define ICC_SGI1R_AFFINITY_2_SHIFT 32
555 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
556 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
557 #define ICC_SGI1R_RS_SHIFT 44
558 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
559 #define ICC_SGI1R_AFFINITY_3_SHIFT 48
560 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
562 #include <asm/arch_gicv3.h>
567 * We need a value to serve as a irq-type for LPIs. Choose one that will
568 * hopefully pique the interest of the reviewer.
570 #define GIC_IRQ_TYPE_LPI 0xa110c8ed
574 void __iomem *rd_base;
575 struct page *pend_page;
576 phys_addr_t phys_base;
578 struct page *prop_page;
586 struct fwnode_handle;
587 int its_cpu_init(void);
588 int its_init(struct fwnode_handle *handle, struct rdists *rdists,
589 struct irq_domain *domain);
590 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
592 static inline bool gic_enable_sre(void)
596 val = gic_read_sre();
597 if (val & ICC_SRE_EL1_SRE)
600 val |= ICC_SRE_EL1_SRE;
602 val = gic_read_sre();
604 return !!(val & ICC_SRE_EL1_SRE);