2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
22 * Distributor registers. We assume we're running non-secure, with ARE
23 * being set. Secure-only and non-ARE registers are not described.
25 #define GICD_CTLR 0x0000
26 #define GICD_TYPER 0x0004
27 #define GICD_IIDR 0x0008
28 #define GICD_STATUSR 0x0010
29 #define GICD_SETSPI_NSR 0x0040
30 #define GICD_CLRSPI_NSR 0x0048
31 #define GICD_SETSPI_SR 0x0050
32 #define GICD_CLRSPI_SR 0x0058
33 #define GICD_SEIR 0x0068
34 #define GICD_IGROUPR 0x0080
35 #define GICD_ISENABLER 0x0100
36 #define GICD_ICENABLER 0x0180
37 #define GICD_ISPENDR 0x0200
38 #define GICD_ICPENDR 0x0280
39 #define GICD_ISACTIVER 0x0300
40 #define GICD_ICACTIVER 0x0380
41 #define GICD_IPRIORITYR 0x0400
42 #define GICD_ICFGR 0x0C00
43 #define GICD_IGRPMODR 0x0D00
44 #define GICD_NSACR 0x0E00
45 #define GICD_IROUTER 0x6000
46 #define GICD_IDREGS 0xFFD0
47 #define GICD_PIDR2 0xFFE8
50 * Those registers are actually from GICv2, but the spec demands that they
51 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
53 #define GICD_ITARGETSR 0x0800
54 #define GICD_SGIR 0x0F00
55 #define GICD_CPENDSGIR 0x0F10
56 #define GICD_SPENDSGIR 0x0F20
58 #define GICD_CTLR_RWP (1U << 31)
59 #define GICD_CTLR_DS (1U << 6)
60 #define GICD_CTLR_ARE_NS (1U << 4)
61 #define GICD_CTLR_ENABLE_G1A (1U << 1)
62 #define GICD_CTLR_ENABLE_G1 (1U << 0)
64 #define GICD_IIDR_IMPLEMENTER_SHIFT 0
65 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
66 #define GICD_IIDR_REVISION_SHIFT 12
67 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
68 #define GICD_IIDR_VARIANT_SHIFT 16
69 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
70 #define GICD_IIDR_PRODUCT_ID_SHIFT 24
71 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
75 * In systems with a single security state (what we emulate in KVM)
76 * the meaning of the interrupt group enable bits is slightly different
78 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
79 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
81 #define GICD_TYPER_RSS (1U << 26)
82 #define GICD_TYPER_LPIS (1U << 17)
83 #define GICD_TYPER_MBIS (1U << 16)
85 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
86 #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
87 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
89 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
90 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
92 #define GIC_PIDR2_ARCH_MASK 0xf0
93 #define GIC_PIDR2_ARCH_GICv3 0x30
94 #define GIC_PIDR2_ARCH_GICv4 0x40
96 #define GIC_V3_DIST_SIZE 0x10000
99 * Re-Distributor registers, offsets from RD_base
101 #define GICR_CTLR GICD_CTLR
102 #define GICR_IIDR 0x0004
103 #define GICR_TYPER 0x0008
104 #define GICR_STATUSR GICD_STATUSR
105 #define GICR_WAKER 0x0014
106 #define GICR_SETLPIR 0x0040
107 #define GICR_CLRLPIR 0x0048
108 #define GICR_SEIR GICD_SEIR
109 #define GICR_PROPBASER 0x0070
110 #define GICR_PENDBASER 0x0078
111 #define GICR_INVLPIR 0x00A0
112 #define GICR_INVALLR 0x00B0
113 #define GICR_SYNCR 0x00C0
114 #define GICR_MOVLPIR 0x0100
115 #define GICR_MOVALLR 0x0110
116 #define GICR_IDREGS GICD_IDREGS
117 #define GICR_PIDR2 GICD_PIDR2
119 #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
120 #define GICR_CTLR_RWP (1UL << 3)
122 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
124 #define GICR_WAKER_ProcessorSleep (1U << 1)
125 #define GICR_WAKER_ChildrenAsleep (1U << 2)
127 #define GIC_BASER_CACHE_nCnB 0ULL
128 #define GIC_BASER_CACHE_SameAsInner 0ULL
129 #define GIC_BASER_CACHE_nC 1ULL
130 #define GIC_BASER_CACHE_RaWt 2ULL
131 #define GIC_BASER_CACHE_RaWb 3ULL
132 #define GIC_BASER_CACHE_WaWt 4ULL
133 #define GIC_BASER_CACHE_WaWb 5ULL
134 #define GIC_BASER_CACHE_RaWaWt 6ULL
135 #define GIC_BASER_CACHE_RaWaWb 7ULL
136 #define GIC_BASER_CACHE_MASK 7ULL
137 #define GIC_BASER_NonShareable 0ULL
138 #define GIC_BASER_InnerShareable 1ULL
139 #define GIC_BASER_OuterShareable 2ULL
140 #define GIC_BASER_SHAREABILITY_MASK 3ULL
142 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
143 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
145 #define GIC_BASER_SHAREABILITY(reg, type) \
146 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
148 /* encode a size field of width @w containing @n - 1 units */
149 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
151 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
152 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
153 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
154 #define GICR_PROPBASER_SHAREABILITY_MASK \
155 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
156 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
157 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
158 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
159 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
160 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
162 #define GICR_PROPBASER_InnerShareable \
163 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
165 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
166 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
167 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
168 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
169 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
170 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
171 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
172 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
174 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
175 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
176 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
178 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
179 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
180 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
181 #define GICR_PENDBASER_SHAREABILITY_MASK \
182 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
183 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
184 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
185 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
186 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
187 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
189 #define GICR_PENDBASER_InnerShareable \
190 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
192 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
193 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
194 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
195 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
196 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
197 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
198 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
199 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
201 #define GICR_PENDBASER_PTZ BIT_ULL(62)
204 * Re-Distributor registers, offsets from SGI_base
206 #define GICR_IGROUPR0 GICD_IGROUPR
207 #define GICR_ISENABLER0 GICD_ISENABLER
208 #define GICR_ICENABLER0 GICD_ICENABLER
209 #define GICR_ISPENDR0 GICD_ISPENDR
210 #define GICR_ICPENDR0 GICD_ICPENDR
211 #define GICR_ISACTIVER0 GICD_ISACTIVER
212 #define GICR_ICACTIVER0 GICD_ICACTIVER
213 #define GICR_IPRIORITYR0 GICD_IPRIORITYR
214 #define GICR_ICFGR0 GICD_ICFGR
215 #define GICR_IGRPMODR0 GICD_IGRPMODR
216 #define GICR_NSACR GICD_NSACR
218 #define GICR_TYPER_PLPIS (1U << 0)
219 #define GICR_TYPER_VLPIS (1U << 1)
220 #define GICR_TYPER_DirectLPIS (1U << 3)
221 #define GICR_TYPER_LAST (1U << 4)
223 #define GIC_V3_REDIST_SIZE 0x20000
225 #define LPI_PROP_GROUP1 (1 << 1)
226 #define LPI_PROP_ENABLED (1 << 0)
229 * Re-Distributor registers, offsets from VLPI_base
231 #define GICR_VPROPBASER 0x0070
233 #define GICR_VPROPBASER_IDBITS_MASK 0x1f
235 #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10)
236 #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7)
237 #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56)
239 #define GICR_VPROPBASER_SHAREABILITY_MASK \
240 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK)
241 #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \
242 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
243 #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \
244 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
245 #define GICR_VPROPBASER_CACHEABILITY_MASK \
246 GICR_VPROPBASER_INNER_CACHEABILITY_MASK
248 #define GICR_VPROPBASER_InnerShareable \
249 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable)
251 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
252 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
253 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
254 #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
255 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
256 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
257 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
258 #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
260 #define GICR_VPENDBASER 0x0078
262 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10)
263 #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7)
264 #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56)
265 #define GICR_VPENDBASER_SHAREABILITY_MASK \
266 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK)
267 #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \
268 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
269 #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \
270 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
271 #define GICR_VPENDBASER_CACHEABILITY_MASK \
272 GICR_VPENDBASER_INNER_CACHEABILITY_MASK
274 #define GICR_VPENDBASER_NonShareable \
275 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
277 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
278 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
279 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
280 #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
281 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
282 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
283 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
284 #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb)
286 #define GICR_VPENDBASER_Dirty (1ULL << 60)
287 #define GICR_VPENDBASER_PendingLast (1ULL << 61)
288 #define GICR_VPENDBASER_IDAI (1ULL << 62)
289 #define GICR_VPENDBASER_Valid (1ULL << 63)
292 * ITS registers, offsets from ITS_base
294 #define GITS_CTLR 0x0000
295 #define GITS_IIDR 0x0004
296 #define GITS_TYPER 0x0008
297 #define GITS_CBASER 0x0080
298 #define GITS_CWRITER 0x0088
299 #define GITS_CREADR 0x0090
300 #define GITS_BASER 0x0100
301 #define GITS_IDREGS_BASE 0xffd0
302 #define GITS_PIDR0 0xffe0
303 #define GITS_PIDR1 0xffe4
304 #define GITS_PIDR2 GICR_PIDR2
305 #define GITS_PIDR4 0xffd0
306 #define GITS_CIDR0 0xfff0
307 #define GITS_CIDR1 0xfff4
308 #define GITS_CIDR2 0xfff8
309 #define GITS_CIDR3 0xfffc
311 #define GITS_TRANSLATER 0x10040
313 #define GITS_CTLR_ENABLE (1U << 0)
314 #define GITS_CTLR_ImDe (1U << 1)
315 #define GITS_CTLR_ITS_NUMBER_SHIFT 4
316 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
317 #define GITS_CTLR_QUIESCENT (1U << 31)
319 #define GITS_TYPER_PLPIS (1UL << 0)
320 #define GITS_TYPER_VLPIS (1UL << 1)
321 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
322 #define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
323 #define GITS_TYPER_IDBITS_SHIFT 8
324 #define GITS_TYPER_DEVBITS_SHIFT 13
325 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
326 #define GITS_TYPER_PTA (1UL << 19)
327 #define GITS_TYPER_HCC_SHIFT 24
328 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
329 #define GITS_TYPER_VMOVP (1ULL << 37)
331 #define GITS_IIDR_REV_SHIFT 12
332 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
333 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
334 #define GITS_IIDR_PRODUCTID_SHIFT 24
336 #define GITS_CBASER_VALID (1ULL << 63)
337 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
338 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
339 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
340 #define GITS_CBASER_SHAREABILITY_MASK \
341 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
342 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
343 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
344 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \
345 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
346 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
348 #define GITS_CBASER_InnerShareable \
349 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
351 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
352 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
353 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
354 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
355 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
356 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
357 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
358 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
360 #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))
362 #define GITS_BASER_NR_REGS 8
364 #define GITS_BASER_VALID (1ULL << 63)
365 #define GITS_BASER_INDIRECT (1ULL << 62)
367 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
368 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
369 #define GITS_BASER_INNER_CACHEABILITY_MASK \
370 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
371 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
372 #define GITS_BASER_OUTER_CACHEABILITY_MASK \
373 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
374 #define GITS_BASER_SHAREABILITY_MASK \
375 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
377 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
378 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
379 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
380 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
381 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
382 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
383 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
384 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
386 #define GITS_BASER_TYPE_SHIFT (56)
387 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
388 #define GITS_BASER_ENTRY_SIZE_SHIFT (48)
389 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
390 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
391 #define GITS_BASER_PHYS_52_to_48(phys) \
392 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
393 #define GITS_BASER_ADDR_48_to_52(baser) \
394 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
396 #define GITS_BASER_SHAREABILITY_SHIFT (10)
397 #define GITS_BASER_InnerShareable \
398 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
399 #define GITS_BASER_PAGE_SIZE_SHIFT (8)
400 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
401 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
402 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
403 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
404 #define GITS_BASER_PAGES_MAX 256
405 #define GITS_BASER_PAGES_SHIFT (0)
406 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
408 #define GITS_BASER_TYPE_NONE 0
409 #define GITS_BASER_TYPE_DEVICE 1
410 #define GITS_BASER_TYPE_VCPU 2
411 #define GITS_BASER_TYPE_RESERVED3 3
412 #define GITS_BASER_TYPE_COLLECTION 4
413 #define GITS_BASER_TYPE_RESERVED5 5
414 #define GITS_BASER_TYPE_RESERVED6 6
415 #define GITS_BASER_TYPE_RESERVED7 7
417 #define GITS_LVL1_ENTRY_SIZE (8UL)
422 #define GITS_CMD_MAPD 0x08
423 #define GITS_CMD_MAPC 0x09
424 #define GITS_CMD_MAPTI 0x0a
425 #define GITS_CMD_MAPI 0x0b
426 #define GITS_CMD_MOVI 0x01
427 #define GITS_CMD_DISCARD 0x0f
428 #define GITS_CMD_INV 0x0c
429 #define GITS_CMD_MOVALL 0x0e
430 #define GITS_CMD_INVALL 0x0d
431 #define GITS_CMD_INT 0x03
432 #define GITS_CMD_CLEAR 0x04
433 #define GITS_CMD_SYNC 0x05
436 * GICv4 ITS specific commands
438 #define GITS_CMD_GICv4(x) ((x) | 0x20)
439 #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL)
440 #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC)
441 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
442 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
443 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
444 /* VMOVP is the odd one, as it doesn't have a physical counterpart */
445 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
450 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
451 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
452 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
453 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
454 #define E_ITS_MAPD_DEVICE_OOR 0x010801
455 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802
456 #define E_ITS_MAPC_PROCNUM_OOR 0x010902
457 #define E_ITS_MAPC_COLLECTION_OOR 0x010903
458 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
459 #define E_ITS_MAPTI_ID_OOR 0x010a05
460 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
461 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
462 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
463 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
464 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
467 * CPU interface registers
469 #define ICC_CTLR_EL1_EOImode_SHIFT (1)
470 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
471 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
472 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
473 #define ICC_CTLR_EL1_CBPR_SHIFT 0
474 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
475 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
476 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
477 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11
478 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
479 #define ICC_CTLR_EL1_SEIS_SHIFT 14
480 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
481 #define ICC_CTLR_EL1_A3V_SHIFT 15
482 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
483 #define ICC_CTLR_EL1_RSS (0x1 << 18)
484 #define ICC_PMR_EL1_SHIFT 0
485 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
486 #define ICC_BPR0_EL1_SHIFT 0
487 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
488 #define ICC_BPR1_EL1_SHIFT 0
489 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
490 #define ICC_IGRPEN0_EL1_SHIFT 0
491 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
492 #define ICC_IGRPEN1_EL1_SHIFT 0
493 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
494 #define ICC_SRE_EL1_DIB (1U << 2)
495 #define ICC_SRE_EL1_DFB (1U << 1)
496 #define ICC_SRE_EL1_SRE (1U << 0)
499 * Hypervisor interface registers (SRE only)
501 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
503 #define ICH_LR_EOI (1ULL << 41)
504 #define ICH_LR_GROUP (1ULL << 60)
505 #define ICH_LR_HW (1ULL << 61)
506 #define ICH_LR_STATE (3ULL << 62)
507 #define ICH_LR_PENDING_BIT (1ULL << 62)
508 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
509 #define ICH_LR_PHYS_ID_SHIFT 32
510 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
511 #define ICH_LR_PRIORITY_SHIFT 48
512 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
514 /* These are for GICv2 emulation only */
515 #define GICH_LR_VIRTUALID (0x3ffUL << 0)
516 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
517 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
519 #define ICH_MISR_EOI (1 << 0)
520 #define ICH_MISR_U (1 << 1)
522 #define ICH_HCR_EN (1 << 0)
523 #define ICH_HCR_UIE (1 << 1)
524 #define ICH_HCR_NPIE (1 << 3)
525 #define ICH_HCR_TC (1 << 10)
526 #define ICH_HCR_TALL0 (1 << 11)
527 #define ICH_HCR_TALL1 (1 << 12)
528 #define ICH_HCR_EOIcount_SHIFT 27
529 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
531 #define ICH_VMCR_ACK_CTL_SHIFT 2
532 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
533 #define ICH_VMCR_FIQ_EN_SHIFT 3
534 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
535 #define ICH_VMCR_CBPR_SHIFT 4
536 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
537 #define ICH_VMCR_EOIM_SHIFT 9
538 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
539 #define ICH_VMCR_BPR1_SHIFT 18
540 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
541 #define ICH_VMCR_BPR0_SHIFT 21
542 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
543 #define ICH_VMCR_PMR_SHIFT 24
544 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
545 #define ICH_VMCR_ENG0_SHIFT 0
546 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
547 #define ICH_VMCR_ENG1_SHIFT 1
548 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
550 #define ICH_VTR_PRI_BITS_SHIFT 29
551 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
552 #define ICH_VTR_ID_BITS_SHIFT 23
553 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
554 #define ICH_VTR_SEIS_SHIFT 22
555 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
556 #define ICH_VTR_A3V_SHIFT 21
557 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
559 #define ICC_IAR1_EL1_SPURIOUS 0x3ff
561 #define ICC_SRE_EL2_SRE (1 << 0)
562 #define ICC_SRE_EL2_ENABLE (1 << 3)
564 #define ICC_SGI1R_TARGET_LIST_SHIFT 0
565 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
566 #define ICC_SGI1R_AFFINITY_1_SHIFT 16
567 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
568 #define ICC_SGI1R_SGI_ID_SHIFT 24
569 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
570 #define ICC_SGI1R_AFFINITY_2_SHIFT 32
571 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
572 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
573 #define ICC_SGI1R_RS_SHIFT 44
574 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
575 #define ICC_SGI1R_AFFINITY_3_SHIFT 48
576 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
578 #include <asm/arch_gicv3.h>
583 * We need a value to serve as a irq-type for LPIs. Choose one that will
584 * hopefully pique the interest of the reviewer.
586 #define GIC_IRQ_TYPE_LPI 0xa110c8ed
590 void __iomem *rd_base;
591 struct page *pend_page;
592 phys_addr_t phys_base;
595 phys_addr_t prop_table_pa;
604 struct fwnode_handle;
605 int its_cpu_init(void);
606 int its_init(struct fwnode_handle *handle, struct rdists *rdists,
607 struct irq_domain *domain);
608 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
610 static inline bool gic_enable_sre(void)
614 val = gic_read_sre();
615 if (val & ICC_SRE_EL1_SRE)
618 val |= ICC_SRE_EL1_SRE;
620 val = gic_read_sre();
622 return !!(val & ICC_SRE_EL1_SRE);