1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
7 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
10 * Distributor registers. We assume we're running non-secure, with ARE
11 * being set. Secure-only and non-ARE registers are not described.
13 #define GICD_CTLR 0x0000
14 #define GICD_TYPER 0x0004
15 #define GICD_IIDR 0x0008
16 #define GICD_STATUSR 0x0010
17 #define GICD_SETSPI_NSR 0x0040
18 #define GICD_CLRSPI_NSR 0x0048
19 #define GICD_SETSPI_SR 0x0050
20 #define GICD_CLRSPI_SR 0x0058
21 #define GICD_SEIR 0x0068
22 #define GICD_IGROUPR 0x0080
23 #define GICD_ISENABLER 0x0100
24 #define GICD_ICENABLER 0x0180
25 #define GICD_ISPENDR 0x0200
26 #define GICD_ICPENDR 0x0280
27 #define GICD_ISACTIVER 0x0300
28 #define GICD_ICACTIVER 0x0380
29 #define GICD_IPRIORITYR 0x0400
30 #define GICD_ICFGR 0x0C00
31 #define GICD_IGRPMODR 0x0D00
32 #define GICD_NSACR 0x0E00
33 #define GICD_IROUTER 0x6000
34 #define GICD_IDREGS 0xFFD0
35 #define GICD_PIDR2 0xFFE8
38 * Those registers are actually from GICv2, but the spec demands that they
39 * are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
41 #define GICD_ITARGETSR 0x0800
42 #define GICD_SGIR 0x0F00
43 #define GICD_CPENDSGIR 0x0F10
44 #define GICD_SPENDSGIR 0x0F20
46 #define GICD_CTLR_RWP (1U << 31)
47 #define GICD_CTLR_DS (1U << 6)
48 #define GICD_CTLR_ARE_NS (1U << 4)
49 #define GICD_CTLR_ENABLE_G1A (1U << 1)
50 #define GICD_CTLR_ENABLE_G1 (1U << 0)
52 #define GICD_IIDR_IMPLEMENTER_SHIFT 0
53 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT)
54 #define GICD_IIDR_REVISION_SHIFT 12
55 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT)
56 #define GICD_IIDR_VARIANT_SHIFT 16
57 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT)
58 #define GICD_IIDR_PRODUCT_ID_SHIFT 24
59 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT)
63 * In systems with a single security state (what we emulate in KVM)
64 * the meaning of the interrupt group enable bits is slightly different
66 #define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
67 #define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
69 #define GICD_TYPER_RSS (1U << 26)
70 #define GICD_TYPER_LPIS (1U << 17)
71 #define GICD_TYPER_MBIS (1U << 16)
73 #define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
74 #define GICD_TYPER_NUM_LPIS(typer) ((((typer) >> 11) & 0x1f) + 1)
75 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
77 #define GICD_IROUTER_SPI_MODE_ONE (0U << 31)
78 #define GICD_IROUTER_SPI_MODE_ANY (1U << 31)
80 #define GIC_PIDR2_ARCH_MASK 0xf0
81 #define GIC_PIDR2_ARCH_GICv3 0x30
82 #define GIC_PIDR2_ARCH_GICv4 0x40
84 #define GIC_V3_DIST_SIZE 0x10000
87 * Re-Distributor registers, offsets from RD_base
89 #define GICR_CTLR GICD_CTLR
90 #define GICR_IIDR 0x0004
91 #define GICR_TYPER 0x0008
92 #define GICR_STATUSR GICD_STATUSR
93 #define GICR_WAKER 0x0014
94 #define GICR_SETLPIR 0x0040
95 #define GICR_CLRLPIR 0x0048
96 #define GICR_SEIR GICD_SEIR
97 #define GICR_PROPBASER 0x0070
98 #define GICR_PENDBASER 0x0078
99 #define GICR_INVLPIR 0x00A0
100 #define GICR_INVALLR 0x00B0
101 #define GICR_SYNCR 0x00C0
102 #define GICR_MOVLPIR 0x0100
103 #define GICR_MOVALLR 0x0110
104 #define GICR_IDREGS GICD_IDREGS
105 #define GICR_PIDR2 GICD_PIDR2
107 #define GICR_CTLR_ENABLE_LPIS (1UL << 0)
108 #define GICR_CTLR_RWP (1UL << 3)
110 #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff)
112 #define GICR_WAKER_ProcessorSleep (1U << 1)
113 #define GICR_WAKER_ChildrenAsleep (1U << 2)
115 #define GIC_BASER_CACHE_nCnB 0ULL
116 #define GIC_BASER_CACHE_SameAsInner 0ULL
117 #define GIC_BASER_CACHE_nC 1ULL
118 #define GIC_BASER_CACHE_RaWt 2ULL
119 #define GIC_BASER_CACHE_RaWb 3ULL
120 #define GIC_BASER_CACHE_WaWt 4ULL
121 #define GIC_BASER_CACHE_WaWb 5ULL
122 #define GIC_BASER_CACHE_RaWaWt 6ULL
123 #define GIC_BASER_CACHE_RaWaWb 7ULL
124 #define GIC_BASER_CACHE_MASK 7ULL
125 #define GIC_BASER_NonShareable 0ULL
126 #define GIC_BASER_InnerShareable 1ULL
127 #define GIC_BASER_OuterShareable 2ULL
128 #define GIC_BASER_SHAREABILITY_MASK 3ULL
130 #define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
131 (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
133 #define GIC_BASER_SHAREABILITY(reg, type) \
134 (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
136 /* encode a size field of width @w containing @n - 1 units */
137 #define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
139 #define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
140 #define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
141 #define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
142 #define GICR_PROPBASER_SHAREABILITY_MASK \
143 GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
144 #define GICR_PROPBASER_INNER_CACHEABILITY_MASK \
145 GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
146 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
147 GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
148 #define GICR_PROPBASER_CACHEABILITY_MASK GICR_PROPBASER_INNER_CACHEABILITY_MASK
150 #define GICR_PROPBASER_InnerShareable \
151 GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable)
153 #define GICR_PROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nCnB)
154 #define GICR_PROPBASER_nC GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, nC)
155 #define GICR_PROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWt)
156 #define GICR_PROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb)
157 #define GICR_PROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWt)
158 #define GICR_PROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, WaWb)
159 #define GICR_PROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWt)
160 #define GICR_PROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWaWb)
162 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
163 #define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
164 #define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
166 #define GICR_PENDBASER_SHAREABILITY_SHIFT (10)
167 #define GICR_PENDBASER_INNER_CACHEABILITY_SHIFT (7)
168 #define GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT (56)
169 #define GICR_PENDBASER_SHAREABILITY_MASK \
170 GIC_BASER_SHAREABILITY(GICR_PENDBASER, SHAREABILITY_MASK)
171 #define GICR_PENDBASER_INNER_CACHEABILITY_MASK \
172 GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, MASK)
173 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK \
174 GIC_BASER_CACHEABILITY(GICR_PENDBASER, OUTER, MASK)
175 #define GICR_PENDBASER_CACHEABILITY_MASK GICR_PENDBASER_INNER_CACHEABILITY_MASK
177 #define GICR_PENDBASER_InnerShareable \
178 GIC_BASER_SHAREABILITY(GICR_PENDBASER, InnerShareable)
180 #define GICR_PENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nCnB)
181 #define GICR_PENDBASER_nC GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, nC)
182 #define GICR_PENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWt)
183 #define GICR_PENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWb)
184 #define GICR_PENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWt)
185 #define GICR_PENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, WaWb)
186 #define GICR_PENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWt)
187 #define GICR_PENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_PENDBASER, INNER, RaWaWb)
189 #define GICR_PENDBASER_PTZ BIT_ULL(62)
192 * Re-Distributor registers, offsets from SGI_base
194 #define GICR_IGROUPR0 GICD_IGROUPR
195 #define GICR_ISENABLER0 GICD_ISENABLER
196 #define GICR_ICENABLER0 GICD_ICENABLER
197 #define GICR_ISPENDR0 GICD_ISPENDR
198 #define GICR_ICPENDR0 GICD_ICPENDR
199 #define GICR_ISACTIVER0 GICD_ISACTIVER
200 #define GICR_ICACTIVER0 GICD_ICACTIVER
201 #define GICR_IPRIORITYR0 GICD_IPRIORITYR
202 #define GICR_ICFGR0 GICD_ICFGR
203 #define GICR_IGRPMODR0 GICD_IGRPMODR
204 #define GICR_NSACR GICD_NSACR
206 #define GICR_TYPER_PLPIS (1U << 0)
207 #define GICR_TYPER_VLPIS (1U << 1)
208 #define GICR_TYPER_DirectLPIS (1U << 3)
209 #define GICR_TYPER_LAST (1U << 4)
211 #define GIC_V3_REDIST_SIZE 0x20000
213 #define LPI_PROP_GROUP1 (1 << 1)
214 #define LPI_PROP_ENABLED (1 << 0)
217 * Re-Distributor registers, offsets from VLPI_base
219 #define GICR_VPROPBASER 0x0070
221 #define GICR_VPROPBASER_IDBITS_MASK 0x1f
223 #define GICR_VPROPBASER_SHAREABILITY_SHIFT (10)
224 #define GICR_VPROPBASER_INNER_CACHEABILITY_SHIFT (7)
225 #define GICR_VPROPBASER_OUTER_CACHEABILITY_SHIFT (56)
227 #define GICR_VPROPBASER_SHAREABILITY_MASK \
228 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, SHAREABILITY_MASK)
229 #define GICR_VPROPBASER_INNER_CACHEABILITY_MASK \
230 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, MASK)
231 #define GICR_VPROPBASER_OUTER_CACHEABILITY_MASK \
232 GIC_BASER_CACHEABILITY(GICR_VPROPBASER, OUTER, MASK)
233 #define GICR_VPROPBASER_CACHEABILITY_MASK \
234 GICR_VPROPBASER_INNER_CACHEABILITY_MASK
236 #define GICR_VPROPBASER_InnerShareable \
237 GIC_BASER_SHAREABILITY(GICR_VPROPBASER, InnerShareable)
239 #define GICR_VPROPBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nCnB)
240 #define GICR_VPROPBASER_nC GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, nC)
241 #define GICR_VPROPBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWt)
242 #define GICR_VPROPBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWb)
243 #define GICR_VPROPBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWt)
244 #define GICR_VPROPBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, WaWb)
245 #define GICR_VPROPBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWt)
246 #define GICR_VPROPBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPROPBASER, INNER, RaWaWb)
248 #define GICR_VPENDBASER 0x0078
250 #define GICR_VPENDBASER_SHAREABILITY_SHIFT (10)
251 #define GICR_VPENDBASER_INNER_CACHEABILITY_SHIFT (7)
252 #define GICR_VPENDBASER_OUTER_CACHEABILITY_SHIFT (56)
253 #define GICR_VPENDBASER_SHAREABILITY_MASK \
254 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, SHAREABILITY_MASK)
255 #define GICR_VPENDBASER_INNER_CACHEABILITY_MASK \
256 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, MASK)
257 #define GICR_VPENDBASER_OUTER_CACHEABILITY_MASK \
258 GIC_BASER_CACHEABILITY(GICR_VPENDBASER, OUTER, MASK)
259 #define GICR_VPENDBASER_CACHEABILITY_MASK \
260 GICR_VPENDBASER_INNER_CACHEABILITY_MASK
262 #define GICR_VPENDBASER_NonShareable \
263 GIC_BASER_SHAREABILITY(GICR_VPENDBASER, NonShareable)
265 #define GICR_VPENDBASER_nCnB GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nCnB)
266 #define GICR_VPENDBASER_nC GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, nC)
267 #define GICR_VPENDBASER_RaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWt)
268 #define GICR_VPENDBASER_RaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWb)
269 #define GICR_VPENDBASER_WaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWt)
270 #define GICR_VPENDBASER_WaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, WaWb)
271 #define GICR_VPENDBASER_RaWaWt GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWt)
272 #define GICR_VPENDBASER_RaWaWb GIC_BASER_CACHEABILITY(GICR_VPENDBASER, INNER, RaWaWb)
274 #define GICR_VPENDBASER_Dirty (1ULL << 60)
275 #define GICR_VPENDBASER_PendingLast (1ULL << 61)
276 #define GICR_VPENDBASER_IDAI (1ULL << 62)
277 #define GICR_VPENDBASER_Valid (1ULL << 63)
280 * ITS registers, offsets from ITS_base
282 #define GITS_CTLR 0x0000
283 #define GITS_IIDR 0x0004
284 #define GITS_TYPER 0x0008
285 #define GITS_CBASER 0x0080
286 #define GITS_CWRITER 0x0088
287 #define GITS_CREADR 0x0090
288 #define GITS_BASER 0x0100
289 #define GITS_IDREGS_BASE 0xffd0
290 #define GITS_PIDR0 0xffe0
291 #define GITS_PIDR1 0xffe4
292 #define GITS_PIDR2 GICR_PIDR2
293 #define GITS_PIDR4 0xffd0
294 #define GITS_CIDR0 0xfff0
295 #define GITS_CIDR1 0xfff4
296 #define GITS_CIDR2 0xfff8
297 #define GITS_CIDR3 0xfffc
299 #define GITS_TRANSLATER 0x10040
301 #define GITS_CTLR_ENABLE (1U << 0)
302 #define GITS_CTLR_ImDe (1U << 1)
303 #define GITS_CTLR_ITS_NUMBER_SHIFT 4
304 #define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT)
305 #define GITS_CTLR_QUIESCENT (1U << 31)
307 #define GITS_TYPER_PLPIS (1UL << 0)
308 #define GITS_TYPER_VLPIS (1UL << 1)
309 #define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
310 #define GITS_TYPER_ITT_ENTRY_SIZE(r) ((((r) >> GITS_TYPER_ITT_ENTRY_SIZE_SHIFT) & 0xf) + 1)
311 #define GITS_TYPER_IDBITS_SHIFT 8
312 #define GITS_TYPER_DEVBITS_SHIFT 13
313 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
314 #define GITS_TYPER_PTA (1UL << 19)
315 #define GITS_TYPER_HCC_SHIFT 24
316 #define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff)
317 #define GITS_TYPER_VMOVP (1ULL << 37)
319 #define GITS_IIDR_REV_SHIFT 12
320 #define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
321 #define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
322 #define GITS_IIDR_PRODUCTID_SHIFT 24
324 #define GITS_CBASER_VALID (1ULL << 63)
325 #define GITS_CBASER_SHAREABILITY_SHIFT (10)
326 #define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
327 #define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
328 #define GITS_CBASER_SHAREABILITY_MASK \
329 GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
330 #define GITS_CBASER_INNER_CACHEABILITY_MASK \
331 GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
332 #define GITS_CBASER_OUTER_CACHEABILITY_MASK \
333 GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
334 #define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
336 #define GITS_CBASER_InnerShareable \
337 GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
339 #define GITS_CBASER_nCnB GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nCnB)
340 #define GITS_CBASER_nC GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, nC)
341 #define GITS_CBASER_RaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWt)
342 #define GITS_CBASER_RaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWb)
343 #define GITS_CBASER_WaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWt)
344 #define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
345 #define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
346 #define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
348 #define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))
350 #define GITS_BASER_NR_REGS 8
352 #define GITS_BASER_VALID (1ULL << 63)
353 #define GITS_BASER_INDIRECT (1ULL << 62)
355 #define GITS_BASER_INNER_CACHEABILITY_SHIFT (59)
356 #define GITS_BASER_OUTER_CACHEABILITY_SHIFT (53)
357 #define GITS_BASER_INNER_CACHEABILITY_MASK \
358 GIC_BASER_CACHEABILITY(GITS_BASER, INNER, MASK)
359 #define GITS_BASER_CACHEABILITY_MASK GITS_BASER_INNER_CACHEABILITY_MASK
360 #define GITS_BASER_OUTER_CACHEABILITY_MASK \
361 GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, MASK)
362 #define GITS_BASER_SHAREABILITY_MASK \
363 GIC_BASER_SHAREABILITY(GITS_BASER, SHAREABILITY_MASK)
365 #define GITS_BASER_nCnB GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nCnB)
366 #define GITS_BASER_nC GIC_BASER_CACHEABILITY(GITS_BASER, INNER, nC)
367 #define GITS_BASER_RaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWt)
368 #define GITS_BASER_RaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb)
369 #define GITS_BASER_WaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWt)
370 #define GITS_BASER_WaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, WaWb)
371 #define GITS_BASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWt)
372 #define GITS_BASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWaWb)
374 #define GITS_BASER_TYPE_SHIFT (56)
375 #define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
376 #define GITS_BASER_ENTRY_SIZE_SHIFT (48)
377 #define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
378 #define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
379 #define GITS_BASER_PHYS_52_to_48(phys) \
380 (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
381 #define GITS_BASER_ADDR_48_to_52(baser) \
382 (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
384 #define GITS_BASER_SHAREABILITY_SHIFT (10)
385 #define GITS_BASER_InnerShareable \
386 GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
387 #define GITS_BASER_PAGE_SIZE_SHIFT (8)
388 #define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT)
389 #define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT)
390 #define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT)
391 #define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT)
392 #define GITS_BASER_PAGES_MAX 256
393 #define GITS_BASER_PAGES_SHIFT (0)
394 #define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
396 #define GITS_BASER_TYPE_NONE 0
397 #define GITS_BASER_TYPE_DEVICE 1
398 #define GITS_BASER_TYPE_VCPU 2
399 #define GITS_BASER_TYPE_RESERVED3 3
400 #define GITS_BASER_TYPE_COLLECTION 4
401 #define GITS_BASER_TYPE_RESERVED5 5
402 #define GITS_BASER_TYPE_RESERVED6 6
403 #define GITS_BASER_TYPE_RESERVED7 7
405 #define GITS_LVL1_ENTRY_SIZE (8UL)
410 #define GITS_CMD_MAPD 0x08
411 #define GITS_CMD_MAPC 0x09
412 #define GITS_CMD_MAPTI 0x0a
413 #define GITS_CMD_MAPI 0x0b
414 #define GITS_CMD_MOVI 0x01
415 #define GITS_CMD_DISCARD 0x0f
416 #define GITS_CMD_INV 0x0c
417 #define GITS_CMD_MOVALL 0x0e
418 #define GITS_CMD_INVALL 0x0d
419 #define GITS_CMD_INT 0x03
420 #define GITS_CMD_CLEAR 0x04
421 #define GITS_CMD_SYNC 0x05
424 * GICv4 ITS specific commands
426 #define GITS_CMD_GICv4(x) ((x) | 0x20)
427 #define GITS_CMD_VINVALL GITS_CMD_GICv4(GITS_CMD_INVALL)
428 #define GITS_CMD_VMAPP GITS_CMD_GICv4(GITS_CMD_MAPC)
429 #define GITS_CMD_VMAPTI GITS_CMD_GICv4(GITS_CMD_MAPTI)
430 #define GITS_CMD_VMOVI GITS_CMD_GICv4(GITS_CMD_MOVI)
431 #define GITS_CMD_VSYNC GITS_CMD_GICv4(GITS_CMD_SYNC)
432 /* VMOVP is the odd one, as it doesn't have a physical counterpart */
433 #define GITS_CMD_VMOVP GITS_CMD_GICv4(2)
438 #define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
439 #define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
440 #define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
441 #define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
442 #define E_ITS_MAPD_DEVICE_OOR 0x010801
443 #define E_ITS_MAPD_ITTSIZE_OOR 0x010802
444 #define E_ITS_MAPC_PROCNUM_OOR 0x010902
445 #define E_ITS_MAPC_COLLECTION_OOR 0x010903
446 #define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
447 #define E_ITS_MAPTI_ID_OOR 0x010a05
448 #define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
449 #define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
450 #define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
451 #define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
452 #define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
455 * CPU interface registers
457 #define ICC_CTLR_EL1_EOImode_SHIFT (1)
458 #define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
459 #define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
460 #define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
461 #define ICC_CTLR_EL1_CBPR_SHIFT 0
462 #define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
463 #define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
464 #define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
465 #define ICC_CTLR_EL1_ID_BITS_SHIFT 11
466 #define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
467 #define ICC_CTLR_EL1_SEIS_SHIFT 14
468 #define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
469 #define ICC_CTLR_EL1_A3V_SHIFT 15
470 #define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
471 #define ICC_CTLR_EL1_RSS (0x1 << 18)
472 #define ICC_PMR_EL1_SHIFT 0
473 #define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
474 #define ICC_BPR0_EL1_SHIFT 0
475 #define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
476 #define ICC_BPR1_EL1_SHIFT 0
477 #define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
478 #define ICC_IGRPEN0_EL1_SHIFT 0
479 #define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
480 #define ICC_IGRPEN1_EL1_SHIFT 0
481 #define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
482 #define ICC_SRE_EL1_DIB (1U << 2)
483 #define ICC_SRE_EL1_DFB (1U << 1)
484 #define ICC_SRE_EL1_SRE (1U << 0)
487 * Hypervisor interface registers (SRE only)
489 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
491 #define ICH_LR_EOI (1ULL << 41)
492 #define ICH_LR_GROUP (1ULL << 60)
493 #define ICH_LR_HW (1ULL << 61)
494 #define ICH_LR_STATE (3ULL << 62)
495 #define ICH_LR_PENDING_BIT (1ULL << 62)
496 #define ICH_LR_ACTIVE_BIT (1ULL << 63)
497 #define ICH_LR_PHYS_ID_SHIFT 32
498 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
499 #define ICH_LR_PRIORITY_SHIFT 48
500 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
502 /* These are for GICv2 emulation only */
503 #define GICH_LR_VIRTUALID (0x3ffUL << 0)
504 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
505 #define GICH_LR_PHYSID_CPUID (7UL << GICH_LR_PHYSID_CPUID_SHIFT)
507 #define ICH_MISR_EOI (1 << 0)
508 #define ICH_MISR_U (1 << 1)
510 #define ICH_HCR_EN (1 << 0)
511 #define ICH_HCR_UIE (1 << 1)
512 #define ICH_HCR_NPIE (1 << 3)
513 #define ICH_HCR_TC (1 << 10)
514 #define ICH_HCR_TALL0 (1 << 11)
515 #define ICH_HCR_TALL1 (1 << 12)
516 #define ICH_HCR_EOIcount_SHIFT 27
517 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
519 #define ICH_VMCR_ACK_CTL_SHIFT 2
520 #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
521 #define ICH_VMCR_FIQ_EN_SHIFT 3
522 #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
523 #define ICH_VMCR_CBPR_SHIFT 4
524 #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
525 #define ICH_VMCR_EOIM_SHIFT 9
526 #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
527 #define ICH_VMCR_BPR1_SHIFT 18
528 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
529 #define ICH_VMCR_BPR0_SHIFT 21
530 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
531 #define ICH_VMCR_PMR_SHIFT 24
532 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
533 #define ICH_VMCR_ENG0_SHIFT 0
534 #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
535 #define ICH_VMCR_ENG1_SHIFT 1
536 #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
538 #define ICH_VTR_PRI_BITS_SHIFT 29
539 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
540 #define ICH_VTR_ID_BITS_SHIFT 23
541 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
542 #define ICH_VTR_SEIS_SHIFT 22
543 #define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
544 #define ICH_VTR_A3V_SHIFT 21
545 #define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
547 #define ICC_IAR1_EL1_SPURIOUS 0x3ff
549 #define ICC_SRE_EL2_SRE (1 << 0)
550 #define ICC_SRE_EL2_ENABLE (1 << 3)
552 #define ICC_SGI1R_TARGET_LIST_SHIFT 0
553 #define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
554 #define ICC_SGI1R_AFFINITY_1_SHIFT 16
555 #define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
556 #define ICC_SGI1R_SGI_ID_SHIFT 24
557 #define ICC_SGI1R_SGI_ID_MASK (0xfULL << ICC_SGI1R_SGI_ID_SHIFT)
558 #define ICC_SGI1R_AFFINITY_2_SHIFT 32
559 #define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_2_SHIFT)
560 #define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
561 #define ICC_SGI1R_RS_SHIFT 44
562 #define ICC_SGI1R_RS_MASK (0xfULL << ICC_SGI1R_RS_SHIFT)
563 #define ICC_SGI1R_AFFINITY_3_SHIFT 48
564 #define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_3_SHIFT)
566 #include <asm/arch_gicv3.h>
571 * We need a value to serve as a irq-type for LPIs. Choose one that will
572 * hopefully pique the interest of the reviewer.
574 #define GIC_IRQ_TYPE_LPI 0xa110c8ed
578 void __iomem *rd_base;
579 struct page *pend_page;
580 phys_addr_t phys_base;
583 phys_addr_t prop_table_pa;
592 struct fwnode_handle;
593 int its_cpu_init(void);
594 int its_init(struct fwnode_handle *handle, struct rdists *rdists,
595 struct irq_domain *domain);
596 int mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent);
598 static inline bool gic_enable_sre(void)
602 val = gic_read_sre();
603 if (val & ICC_SRE_EL1_SRE)
606 val |= ICC_SRE_EL1_SRE;
608 val = gic_read_sre();
610 return !!(val & ICC_SRE_EL1_SRE);