2 * Copyright © 2006-2015, Intel Corporation.
4 * Authors: Ashok Raj <ashok.raj@intel.com>
5 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
6 * David Woodhouse <David.Woodhouse@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
22 #ifndef _INTEL_IOMMU_H_
23 #define _INTEL_IOMMU_H_
25 #include <linux/types.h>
26 #include <linux/iova.h>
28 #include <linux/idr.h>
29 #include <linux/mmu_notifier.h>
30 #include <linux/list.h>
31 #include <linux/iommu.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <linux/dmar.h>
35 #include <asm/cacheflush.h>
36 #include <asm/iommu.h>
39 * VT-d hardware uses 4KiB page size regardless of host page size.
41 #define VTD_PAGE_SHIFT (12)
42 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
43 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
44 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
46 #define VTD_STRIDE_SHIFT (9)
47 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
49 #define DMA_PTE_READ (1)
50 #define DMA_PTE_WRITE (2)
51 #define DMA_PTE_LARGE_PAGE (1 << 7)
52 #define DMA_PTE_SNP (1 << 11)
54 #define CONTEXT_TT_MULTI_LEVEL 0
55 #define CONTEXT_TT_DEV_IOTLB 1
56 #define CONTEXT_TT_PASS_THROUGH 2
57 /* Extended context entry types */
58 #define CONTEXT_TT_PT_PASID 4
59 #define CONTEXT_TT_PT_PASID_DEV_IOTLB 5
60 #define CONTEXT_TT_MASK (7ULL << 2)
62 #define CONTEXT_DINVE (1ULL << 8)
63 #define CONTEXT_PRS (1ULL << 9)
64 #define CONTEXT_PASIDE (1ULL << 11)
67 * Intel IOMMU register specification per version 1.0 public spec.
69 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
70 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
71 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
72 #define DMAR_GCMD_REG 0x18 /* Global command register */
73 #define DMAR_GSTS_REG 0x1c /* Global status register */
74 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
75 #define DMAR_CCMD_REG 0x28 /* Context command reg */
76 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
77 #define DMAR_FECTL_REG 0x38 /* Fault control register */
78 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
79 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
80 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
81 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
82 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
83 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
84 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
85 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
86 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
87 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
88 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
89 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
90 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
91 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
92 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
93 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
94 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
95 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
96 #define DMAR_PRS_REG 0xdc /* Page request status register */
97 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
98 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
99 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
100 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
101 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
102 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
103 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
104 #define DMAR_MTRR_FIX16K_80000_REG 0x128
105 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
106 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
107 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
108 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
109 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
110 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
111 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
112 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
113 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
114 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
115 #define DMAR_MTRR_PHYSMASK0_REG 0x188
116 #define DMAR_MTRR_PHYSBASE1_REG 0x190
117 #define DMAR_MTRR_PHYSMASK1_REG 0x198
118 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
119 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
120 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
121 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
122 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
123 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
124 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
125 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
126 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
127 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
128 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
129 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
130 #define DMAR_MTRR_PHYSBASE8_REG 0x200
131 #define DMAR_MTRR_PHYSMASK8_REG 0x208
132 #define DMAR_MTRR_PHYSBASE9_REG 0x210
133 #define DMAR_MTRR_PHYSMASK9_REG 0x218
134 #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */
135 #define DMAR_VCMD_REG 0xe10 /* Virtual command register */
136 #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */
138 #define OFFSET_STRIDE (9)
140 #define dmar_readq(a) readq(a)
141 #define dmar_writeq(a,v) writeq(v,a)
143 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
144 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
147 * Decoding Capability Register
149 #define cap_5lp_support(c) (((c) >> 60) & 1)
150 #define cap_pi_support(c) (((c) >> 59) & 1)
151 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
152 #define cap_read_drain(c) (((c) >> 55) & 1)
153 #define cap_write_drain(c) (((c) >> 54) & 1)
154 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
155 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
156 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
158 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
159 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
160 * OFFSET_STRIDE) + 21)
162 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
163 #define cap_max_fault_reg_offset(c) \
164 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
166 #define cap_zlr(c) (((c) >> 22) & 1)
167 #define cap_isoch(c) (((c) >> 23) & 1)
168 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
169 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
170 #define cap_caching_mode(c) (((c) >> 7) & 1)
171 #define cap_phmr(c) (((c) >> 6) & 1)
172 #define cap_plmr(c) (((c) >> 5) & 1)
173 #define cap_rwbf(c) (((c) >> 4) & 1)
174 #define cap_afl(c) (((c) >> 3) & 1)
175 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
177 * Extended Capability Register
180 #define ecap_smpwc(e) (((e) >> 48) & 0x1)
181 #define ecap_slts(e) (((e) >> 46) & 0x1)
182 #define ecap_smts(e) (((e) >> 43) & 0x1)
183 #define ecap_dit(e) ((e >> 41) & 0x1)
184 #define ecap_pasid(e) ((e >> 40) & 0x1)
185 #define ecap_pss(e) ((e >> 35) & 0x1f)
186 #define ecap_eafs(e) ((e >> 34) & 0x1)
187 #define ecap_nwfs(e) ((e >> 33) & 0x1)
188 #define ecap_srs(e) ((e >> 31) & 0x1)
189 #define ecap_ers(e) ((e >> 30) & 0x1)
190 #define ecap_prs(e) ((e >> 29) & 0x1)
191 #define ecap_broken_pasid(e) ((e >> 28) & 0x1)
192 #define ecap_dis(e) ((e >> 27) & 0x1)
193 #define ecap_nest(e) ((e >> 26) & 0x1)
194 #define ecap_mts(e) ((e >> 25) & 0x1)
195 #define ecap_ecs(e) ((e >> 24) & 0x1)
196 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
197 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
198 #define ecap_coherent(e) ((e) & 0x1)
199 #define ecap_qis(e) ((e) & 0x2)
200 #define ecap_pass_through(e) ((e >> 6) & 0x1)
201 #define ecap_eim_support(e) ((e >> 4) & 0x1)
202 #define ecap_ir_support(e) ((e >> 3) & 0x1)
203 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
204 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
205 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
208 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
209 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
210 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
211 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
212 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
213 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
214 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
215 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
216 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
217 #define DMA_TLB_IVT (((u64)1) << 63)
218 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
219 #define DMA_TLB_MAX_SIZE (0x3f)
222 #define DMA_CCMD_INVL_GRANU_OFFSET 61
223 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
224 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
225 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
226 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
227 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
228 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
229 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
230 #define DMA_ID_TLB_ADDR(addr) (addr)
231 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
234 #define DMA_PMEN_EPM (((u32)1)<<31)
235 #define DMA_PMEN_PRS (((u32)1)<<0)
238 #define DMA_GCMD_TE (((u32)1) << 31)
239 #define DMA_GCMD_SRTP (((u32)1) << 30)
240 #define DMA_GCMD_SFL (((u32)1) << 29)
241 #define DMA_GCMD_EAFL (((u32)1) << 28)
242 #define DMA_GCMD_WBF (((u32)1) << 27)
243 #define DMA_GCMD_QIE (((u32)1) << 26)
244 #define DMA_GCMD_SIRTP (((u32)1) << 24)
245 #define DMA_GCMD_IRE (((u32) 1) << 25)
246 #define DMA_GCMD_CFI (((u32) 1) << 23)
249 #define DMA_GSTS_TES (((u32)1) << 31)
250 #define DMA_GSTS_RTPS (((u32)1) << 30)
251 #define DMA_GSTS_FLS (((u32)1) << 29)
252 #define DMA_GSTS_AFLS (((u32)1) << 28)
253 #define DMA_GSTS_WBFS (((u32)1) << 27)
254 #define DMA_GSTS_QIES (((u32)1) << 26)
255 #define DMA_GSTS_IRTPS (((u32)1) << 24)
256 #define DMA_GSTS_IRES (((u32)1) << 25)
257 #define DMA_GSTS_CFIS (((u32)1) << 23)
260 #define DMA_RTADDR_RTT (((u64)1) << 11)
263 #define DMA_CCMD_ICC (((u64)1) << 63)
264 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
265 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
266 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
267 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
268 #define DMA_CCMD_MASK_NOBIT 0
269 #define DMA_CCMD_MASK_1BIT 1
270 #define DMA_CCMD_MASK_2BIT 2
271 #define DMA_CCMD_MASK_3BIT 3
272 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
273 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
276 #define DMA_FECTL_IM (((u32)1) << 31)
279 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
280 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
281 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
282 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
283 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
284 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
285 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
287 /* FRCD_REG, 32 bits access */
288 #define DMA_FRCD_F (((u32)1) << 31)
289 #define dma_frcd_type(d) ((d >> 30) & 1)
290 #define dma_frcd_fault_reason(c) (c & 0xff)
291 #define dma_frcd_source_id(c) (c & 0xffff)
293 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
296 #define DMA_PRS_PPR ((u32)1)
298 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
300 cycles_t start_time = get_cycles(); \
302 sts = op(iommu->reg + offset); \
305 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
306 panic("DMAR hardware is malfunctioning\n"); \
311 #define QI_LENGTH 256 /* queue length */
320 #define QI_CC_TYPE 0x1
321 #define QI_IOTLB_TYPE 0x2
322 #define QI_DIOTLB_TYPE 0x3
323 #define QI_IEC_TYPE 0x4
324 #define QI_IWD_TYPE 0x5
325 #define QI_EIOTLB_TYPE 0x6
326 #define QI_PC_TYPE 0x7
327 #define QI_DEIOTLB_TYPE 0x8
328 #define QI_PGRP_RESP_TYPE 0x9
329 #define QI_PSTRM_RESP_TYPE 0xa
331 #define QI_IEC_SELECTIVE (((u64)1) << 4)
332 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
333 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
335 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
336 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
338 #define QI_IOTLB_DID(did) (((u64)did) << 16)
339 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
340 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
341 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
342 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
343 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
344 #define QI_IOTLB_AM(am) (((u8)am))
346 #define QI_CC_FM(fm) (((u64)fm) << 48)
347 #define QI_CC_SID(sid) (((u64)sid) << 32)
348 #define QI_CC_DID(did) (((u64)did) << 16)
349 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
351 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
352 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
353 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
354 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
355 #define QI_DEV_IOTLB_SIZE 1
356 #define QI_DEV_IOTLB_MAX_INVS 32
358 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
359 #define QI_PC_DID(did) (((u64)did) << 16)
360 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
362 #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
363 #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
365 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
366 #define QI_EIOTLB_GL(gl) (((u64)gl) << 7)
367 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
368 #define QI_EIOTLB_AM(am) (((u64)am))
369 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
370 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
371 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
373 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
374 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
375 #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
376 #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
377 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
378 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
379 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | ((u64)(pfsid & 0xfff) << 52))
380 #define QI_DEV_EIOTLB_MAX_INVS 32
382 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55)
383 #define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32)
384 #define QI_PGRP_RESP_CODE(res) ((u64)(res))
385 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
386 #define QI_PGRP_DID(did) (((u64)(did)) << 16)
387 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
389 #define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK)
390 #define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4)
391 #define QI_PSTRM_RESP_CODE(res) ((u64)(res))
392 #define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55)
393 #define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32)
394 #define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24)
395 #define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4)
397 #define QI_RESP_SUCCESS 0x0
398 #define QI_RESP_INVALID 0x1
399 #define QI_RESP_FAILURE 0xf
401 #define QI_GRAN_ALL_ALL 0
402 #define QI_GRAN_NONG_ALL 1
403 #define QI_GRAN_NONG_PASID 2
404 #define QI_GRAN_PSI_PASID 3
406 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
416 raw_spinlock_t q_lock;
417 void *desc; /* invalidation queue */
418 int *desc_status; /* desc status */
419 int free_head; /* first free entry */
420 int free_tail; /* last free entry */
424 #ifdef CONFIG_IRQ_REMAP
425 /* 1MB - maximum possible interrupt remapping table size */
426 #define INTR_REMAP_PAGE_ORDER 8
427 #define INTR_REMAP_TABLE_REG_SIZE 0xf
428 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
430 #define INTR_REMAP_TABLE_ENTRIES 65536
436 unsigned long *bitmap;
441 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
443 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
444 unsigned int size_order, u64 type);
455 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
456 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
459 struct pasid_state_entry;
465 * 12-63: Context Ptr (12 - (haw-1))
476 * 1: fault processing disable
477 * 2-3: translation type
478 * 12-63: address space root
484 struct context_entry {
490 int nid; /* node id */
492 unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
493 /* Refcount of devices per iommu */
496 u16 iommu_did[DMAR_UNITS_SUPPORTED];
497 /* Domain ids per IOMMU. Use u16 since
498 * domain ids are 16 bit wide according
499 * to VT-d spec, section 9.3 */
501 bool has_iotlb_device;
502 struct list_head devices; /* all devices' list */
503 struct iova_domain iovad; /* iova's that belong to this domain */
505 struct dma_pte *pgd; /* virtual address */
506 int gaw; /* max guest address width */
508 /* adjusted guest address width, 0 is level 2 30-bit */
511 int flags; /* flags to find out type of domain */
513 int iommu_coherency;/* indicate coherency of iommu access */
514 int iommu_snooping; /* indicate snooping control feature*/
515 int iommu_count; /* reference count of iommu */
516 int iommu_superpage;/* Level of superpages supported:
517 0 == 4KiB (no superpages), 1 == 2MiB,
518 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
519 u64 max_addr; /* maximum mapped address */
521 struct iommu_domain domain; /* generic domain data structure for
526 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
527 u64 reg_phys; /* physical address of hw register set */
528 u64 reg_size; /* size of hw register set */
531 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
532 raw_spinlock_t register_lock; /* protect register handling */
533 int seq_id; /* sequence id of the iommu */
534 int agaw; /* agaw of this iommu */
535 int msagaw; /* max sagaw of this iommu */
536 unsigned int irq, pr_irq;
537 u16 segment; /* PCI segment# */
538 unsigned char name[13]; /* Device Name */
540 #ifdef CONFIG_INTEL_IOMMU
541 unsigned long *domain_ids; /* bitmap of domains */
542 struct dmar_domain ***domains; /* ptr to domains */
543 spinlock_t lock; /* protect context, domain ids */
544 struct root_entry *root_entry; /* virtual address */
546 struct iommu_flush flush;
548 #ifdef CONFIG_INTEL_IOMMU_SVM
549 /* These are large and need to be contiguous, so we allocate just
550 * one for now. We'll maybe want to rethink that if we truly give
551 * devices away to userspace processes (e.g. for DPDK) and don't
552 * want to trust that userspace will use *only* the PASID it was
553 * told to. But while it's all driver-arbitrated, we're fine. */
554 struct pasid_state_entry *pasid_state_table;
555 struct page_req_dsc *prq;
556 unsigned char prq_name[16]; /* Name for PRQ interrupt */
559 struct q_inval *qi; /* Queued invalidation info */
560 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
562 #ifdef CONFIG_IRQ_REMAP
563 struct ir_table *ir_table; /* Interrupt remapping info */
564 struct irq_domain *ir_domain;
565 struct irq_domain *ir_msi_domain;
567 struct iommu_device iommu; /* IOMMU core code handle */
569 u32 flags; /* Software defined flags */
572 /* PCI domain-device relationship */
573 struct device_domain_info {
574 struct list_head link; /* link to domain siblings */
575 struct list_head global; /* link to global list */
576 struct list_head table; /* link to pasid table */
577 u8 bus; /* PCI bus number */
578 u8 devfn; /* PCI devfn number */
579 u16 pfsid; /* SRIOV physical function source ID */
580 u8 pasid_supported:3;
587 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
588 struct intel_iommu *iommu; /* IOMMU used by this device */
589 struct dmar_domain *domain; /* pointer to domain */
590 struct pasid_table *pasid_table; /* pasid table */
593 static inline void __iommu_flush_cache(
594 struct intel_iommu *iommu, void *addr, int size)
596 if (!ecap_coherent(iommu->ecap))
597 clflush_cache_range(addr, size);
607 * 12-63: Host physcial address
613 static inline void dma_clear_pte(struct dma_pte *pte)
618 static inline u64 dma_pte_addr(struct dma_pte *pte)
621 return pte->val & VTD_PAGE_MASK;
623 /* Must have a full atomic 64-bit read */
624 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
628 static inline bool dma_pte_present(struct dma_pte *pte)
630 return (pte->val & 3) != 0;
633 static inline bool dma_pte_superpage(struct dma_pte *pte)
635 return (pte->val & DMA_PTE_LARGE_PAGE);
638 static inline int first_pte_in_page(struct dma_pte *pte)
640 return !((unsigned long)pte & ~VTD_PAGE_MASK);
643 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
644 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
646 extern int dmar_enable_qi(struct intel_iommu *iommu);
647 extern void dmar_disable_qi(struct intel_iommu *iommu);
648 extern int dmar_reenable_qi(struct intel_iommu *iommu);
649 extern void qi_global_iec(struct intel_iommu *iommu);
651 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
653 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
654 unsigned int size_order, u64 type);
655 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
656 u16 qdep, u64 addr, unsigned mask);
657 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
659 extern int dmar_ir_support(void);
661 struct dmar_domain *get_valid_domain_for_dev(struct device *dev);
662 void *alloc_pgtable_page(int node);
663 void free_pgtable_page(void *vaddr);
664 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
665 int for_each_device_domain(int (*fn)(struct device_domain_info *info,
666 void *data), void *data);
667 void iommu_flush_write_buffer(struct intel_iommu *iommu);
669 #ifdef CONFIG_INTEL_IOMMU_SVM
670 int intel_svm_init(struct intel_iommu *iommu);
671 int intel_svm_exit(struct intel_iommu *iommu);
672 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
673 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
677 struct intel_svm_dev {
678 struct list_head list;
681 struct svm_dev_ops *ops;
689 struct mmu_notifier notifier;
690 struct mm_struct *mm;
691 struct intel_iommu *iommu;
694 struct list_head devs;
695 struct list_head list;
698 extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev);
699 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
702 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
703 void intel_iommu_debugfs_init(void);
705 static inline void intel_iommu_debugfs_init(void) {}
706 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
708 extern const struct attribute_group *intel_iommu_groups[];
709 bool context_present(struct context_entry *context);
710 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
711 u8 devfn, int alloc);
713 #ifdef CONFIG_INTEL_IOMMU
714 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
715 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
716 extern int dmar_disabled;
717 extern int intel_iommu_enabled;
718 extern int intel_iommu_tboot_noforce;
720 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
724 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
728 #define dmar_disabled (1)
729 #define intel_iommu_enabled (0)