1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
21 enum gpio_lookup_flags;
25 #define GPIO_LINE_DIRECTION_IN 1
26 #define GPIO_LINE_DIRECTION_OUT 0
29 * struct gpio_irq_chip - GPIO interrupt controller
31 struct gpio_irq_chip {
35 * GPIO IRQ chip implementation, provided by GPIO driver.
37 struct irq_chip *chip;
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
45 struct irq_domain *domain;
50 * Table of interrupt domain operations for this IRQ chip.
52 const struct irq_domain_ops *domain_ops;
54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
61 struct fwnode_handle *fwnode;
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
71 struct irq_domain *parent_domain;
74 * @child_to_parent_hwirq:
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
97 * @populate_parent_alloc_arg :
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
110 * @child_offset_to_irq:
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
121 * @child_irq_domain_ops:
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
128 struct irq_domain_ops child_irq_domain_ops;
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
137 irq_flow_handler_t handler;
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
145 unsigned int default_type;
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 struct lock_class_key *lock_key;
157 * Per GPIO IRQ chip lockdep class for IRQ request.
159 struct lock_class_key *request_key;
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
167 irq_flow_handler_t parent_handler;
170 * @parent_handler_data:
172 * If @per_parent_data is false, @parent_handler_data is a single
173 * pointer used as the data associated with every parent interrupt.
175 * @parent_handler_data_array:
177 * If @per_parent_data is true, @parent_handler_data_array is
178 * an array of @num_parents pointers, and is used to associate
179 * different data for each parent. This cannot be NULL if
180 * @per_parent_data is true.
183 void *parent_handler_data;
184 void **parent_handler_data_array;
190 * The number of interrupt parents of a GPIO chip.
192 unsigned int num_parents;
197 * A list of interrupt parents of a GPIO chip. This is owned by the
198 * driver, so the core will only reference this list, not modify it.
200 unsigned int *parents;
205 * A list of interrupt parents for each line of a GPIO chip.
212 * True if set the interrupt handling uses nested threads.
219 * True if parent_handler_data_array describes a @num_parents
220 * sized array to be used as parent data.
222 bool per_parent_data;
227 * Flag to track GPIO chip irq member's initialization.
228 * This flag will make sure GPIO chip irq members are not used
229 * before they are initialized.
234 * @init_hw: optional routine to initialize hardware before
235 * an IRQ chip will be added. This is quite useful when
236 * a particular driver wants to clear IRQ related registers
237 * in order to avoid undesired events.
239 int (*init_hw)(struct gpio_chip *gc);
242 * @init_valid_mask: optional routine to initialize @valid_mask, to be
243 * used if not all GPIO lines are valid interrupts. Sometimes some
244 * lines just cannot fire interrupts, and this routine, when defined,
245 * is passed a bitmap in "valid_mask" and it will have ngpios
246 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
247 * then directly set some bits to "0" if they cannot be used for
250 void (*init_valid_mask)(struct gpio_chip *gc,
251 unsigned long *valid_mask,
252 unsigned int ngpios);
257 * If not %NULL, holds bitmask of GPIOs which are valid to be included
258 * in IRQ domain of the chip.
260 unsigned long *valid_mask;
265 * Required for static IRQ allocation. If set, irq_domain_add_simple()
266 * will allocate and map all IRQs during initialization.
273 * Store old irq_chip irq_enable callback
275 void (*irq_enable)(struct irq_data *data);
280 * Store old irq_chip irq_disable callback
282 void (*irq_disable)(struct irq_data *data);
286 * Store old irq_chip irq_unmask callback
288 void (*irq_unmask)(struct irq_data *data);
293 * Store old irq_chip irq_mask callback
295 void (*irq_mask)(struct irq_data *data);
299 * struct gpio_chip - abstract a GPIO controller
300 * @label: a functional name for the GPIO device, such as a part
301 * number or the name of the SoC IP-block implementing it.
302 * @gpiodev: the internal state holder, opaque struct
303 * @parent: optional parent device providing the GPIOs
304 * @fwnode: optional fwnode providing this controller's properties
305 * @owner: helps prevent removal of modules exporting active GPIOs
306 * @request: optional hook for chip-specific activation, such as
307 * enabling module power and clock; may sleep
308 * @free: optional hook for chip-specific deactivation, such as
309 * disabling module power and clock; may sleep
310 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
311 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
312 * or negative error. It is recommended to always implement this
313 * function, even on input-only or output-only gpio chips.
314 * @direction_input: configures signal "offset" as input, or returns error
315 * This can be omitted on input-only or output-only gpio chips.
316 * @direction_output: configures signal "offset" as output, or returns error
317 * This can be omitted on input-only or output-only gpio chips.
318 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
319 * @get_multiple: reads values for multiple signals defined by "mask" and
320 * stores them in "bits", returns 0 on success or negative error
321 * @set: assigns output value for signal "offset"
322 * @set_multiple: assigns output values for multiple signals defined by "mask"
323 * @set_config: optional hook for all kinds of settings. Uses the same
324 * packed config format as generic pinconf.
325 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
326 * implementation may not sleep
327 * @dbg_show: optional routine to show contents in debugfs; default code
328 * will be used when this is omitted, but custom code can show extra
329 * state (such as pullup/pulldown configuration).
330 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
331 * not all GPIOs are valid.
332 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
333 * requires special mapping of the pins that provides GPIO functionality.
334 * It is called after adding GPIO chip and before adding IRQ chip.
335 * @base: identifies the first GPIO number handled by this chip;
336 * or, if negative during registration, requests dynamic ID allocation.
337 * DEPRECATION: providing anything non-negative and nailing the base
338 * offset of GPIO chips is deprecated. Please pass -1 as base to
339 * let gpiolib select the chip base in all possible cases. We want to
340 * get rid of the static GPIO number space in the long run.
341 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
342 * handled is (base + ngpio - 1).
343 * @offset: when multiple gpio chips belong to the same device this
344 * can be used as offset within the device so friendly names can
345 * be properly assigned.
346 * @names: if set, must be an array of strings to use as alternative
347 * names for the GPIOs in this chip. Any entry in the array
348 * may be NULL if there is no alias for the GPIO, however the
349 * array must be @ngpio entries long. A name can include a single printk
350 * format specifier for an unsigned int. It is substituted by the actual
351 * number of the gpio.
352 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
353 * must while accessing GPIO expander chips over I2C or SPI. This
354 * implies that if the chip supports IRQs, these IRQs need to be threaded
355 * as the chip access may sleep when e.g. reading out the IRQ status
357 * @read_reg: reader function for generic GPIO
358 * @write_reg: writer function for generic GPIO
359 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
360 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
361 * generic GPIO core. It is for internal housekeeping only.
362 * @reg_dat: data (in) register for generic GPIO
363 * @reg_set: output set register (out=high) for generic GPIO
364 * @reg_clr: output clear register (out=low) for generic GPIO
365 * @reg_dir_out: direction out setting register for generic GPIO
366 * @reg_dir_in: direction in setting register for generic GPIO
367 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
368 * be read and we need to rely on out internal state tracking.
369 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
370 * <register width> * 8
371 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
372 * shadowed and real data registers writes together.
373 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
375 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
376 * direction safely. A "1" in this word means the line is set as
379 * A gpio_chip can help platforms abstract various sources of GPIOs so
380 * they can all be accessed through a common programming interface.
381 * Example sources would be SOC controllers, FPGAs, multifunction
382 * chips, dedicated GPIO expanders, and so on.
384 * Each chip controls a number of signals, identified in method calls
385 * by "offset" values in the range 0..(@ngpio - 1). When those signals
386 * are referenced through calls like gpio_get_value(gpio), the offset
387 * is calculated by subtracting @base from the gpio number.
391 struct gpio_device *gpiodev;
392 struct device *parent;
393 struct fwnode_handle *fwnode;
394 struct module *owner;
396 int (*request)(struct gpio_chip *gc,
397 unsigned int offset);
398 void (*free)(struct gpio_chip *gc,
399 unsigned int offset);
400 int (*get_direction)(struct gpio_chip *gc,
401 unsigned int offset);
402 int (*direction_input)(struct gpio_chip *gc,
403 unsigned int offset);
404 int (*direction_output)(struct gpio_chip *gc,
405 unsigned int offset, int value);
406 int (*get)(struct gpio_chip *gc,
407 unsigned int offset);
408 int (*get_multiple)(struct gpio_chip *gc,
410 unsigned long *bits);
411 void (*set)(struct gpio_chip *gc,
412 unsigned int offset, int value);
413 void (*set_multiple)(struct gpio_chip *gc,
415 unsigned long *bits);
416 int (*set_config)(struct gpio_chip *gc,
418 unsigned long config);
419 int (*to_irq)(struct gpio_chip *gc,
420 unsigned int offset);
422 void (*dbg_show)(struct seq_file *s,
423 struct gpio_chip *gc);
425 int (*init_valid_mask)(struct gpio_chip *gc,
426 unsigned long *valid_mask,
427 unsigned int ngpios);
429 int (*add_pin_ranges)(struct gpio_chip *gc);
434 const char *const *names;
437 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
438 unsigned long (*read_reg)(void __iomem *reg);
439 void (*write_reg)(void __iomem *reg, unsigned long data);
441 void __iomem *reg_dat;
442 void __iomem *reg_set;
443 void __iomem *reg_clr;
444 void __iomem *reg_dir_out;
445 void __iomem *reg_dir_in;
446 bool bgpio_dir_unreadable;
448 spinlock_t bgpio_lock;
449 unsigned long bgpio_data;
450 unsigned long bgpio_dir;
451 #endif /* CONFIG_GPIO_GENERIC */
453 #ifdef CONFIG_GPIOLIB_IRQCHIP
455 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
456 * to handle IRQs for most practical cases.
462 * Integrates interrupt chip functionality with the GPIO chip. Can be
463 * used to handle IRQs for most practical cases.
465 struct gpio_irq_chip irq;
466 #endif /* CONFIG_GPIOLIB_IRQCHIP */
471 * If not %NULL, holds bitmask of GPIOs which are valid to be used
474 unsigned long *valid_mask;
476 #if defined(CONFIG_OF_GPIO)
478 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
479 * the device tree automatically may have an OF translation
485 * Pointer to a device tree node representing this GPIO controller.
487 struct device_node *of_node;
492 * Number of cells used to form the GPIO specifier.
494 unsigned int of_gpio_n_cells;
499 * Callback to translate a device tree GPIO specifier into a chip-
500 * relative GPIO number and flags.
502 int (*of_xlate)(struct gpio_chip *gc,
503 const struct of_phandle_args *gpiospec, u32 *flags);
504 #endif /* CONFIG_OF_GPIO */
507 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
508 unsigned int offset);
511 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
512 * @chip: the chip to query
514 * @base: first GPIO in the range
515 * @size: amount of GPIOs to check starting from @base
516 * @label: label of current GPIO
518 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
519 for (i = 0; i < size; i++) \
520 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
522 /* Iterates over all requested GPIO of the given @chip */
523 #define for_each_requested_gpio(chip, i, label) \
524 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
526 /* add/remove chips */
527 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
528 struct lock_class_key *lock_key,
529 struct lock_class_key *request_key);
532 * gpiochip_add_data() - register a gpio_chip
533 * @gc: the chip to register, with gc->base initialized
534 * @data: driver-private data associated with this chip
536 * Context: potentially before irqs will work
538 * When gpiochip_add_data() is called very early during boot, so that GPIOs
539 * can be freely used, the gc->parent device must be registered before
540 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
541 * for GPIOs will fail rudely.
543 * gpiochip_add_data() must only be called after gpiolib initialization,
544 * i.e. after core_initcall().
546 * If gc->base is negative, this requests dynamic assignment of
547 * a range of valid GPIOs.
550 * A negative errno if the chip can't be registered, such as because the
551 * gc->base is invalid or already associated with a different chip.
552 * Otherwise it returns zero as a success code.
554 #ifdef CONFIG_LOCKDEP
555 #define gpiochip_add_data(gc, data) ({ \
556 static struct lock_class_key lock_key; \
557 static struct lock_class_key request_key; \
558 gpiochip_add_data_with_key(gc, data, &lock_key, \
561 #define devm_gpiochip_add_data(dev, gc, data) ({ \
562 static struct lock_class_key lock_key; \
563 static struct lock_class_key request_key; \
564 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
568 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
569 #define devm_gpiochip_add_data(dev, gc, data) \
570 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
571 #endif /* CONFIG_LOCKDEP */
573 static inline int gpiochip_add(struct gpio_chip *gc)
575 return gpiochip_add_data(gc, NULL);
577 extern void gpiochip_remove(struct gpio_chip *gc);
578 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
579 struct lock_class_key *lock_key,
580 struct lock_class_key *request_key);
582 extern struct gpio_chip *gpiochip_find(void *data,
583 int (*match)(struct gpio_chip *gc, void *data));
585 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
586 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
587 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
588 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
589 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
591 /* Line status inquiry for drivers */
592 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
593 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
595 /* Sleep persistence inquiry for drivers */
596 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
597 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
599 /* get driver data */
600 void *gpiochip_get_data(struct gpio_chip *gc);
608 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
610 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
611 unsigned int parent_hwirq,
612 unsigned int parent_type);
613 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
614 unsigned int parent_hwirq,
615 unsigned int parent_type);
619 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
620 unsigned int parent_hwirq,
621 unsigned int parent_type)
626 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
627 unsigned int parent_hwirq,
628 unsigned int parent_type)
633 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
635 int bgpio_init(struct gpio_chip *gc, struct device *dev,
636 unsigned long sz, void __iomem *dat, void __iomem *set,
637 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
638 unsigned long flags);
640 #define BGPIOF_BIG_ENDIAN BIT(0)
641 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
642 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
643 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
644 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
645 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
646 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
648 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
649 irq_hw_number_t hwirq);
650 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
652 int gpiochip_irq_domain_activate(struct irq_domain *domain,
653 struct irq_data *data, bool reserve);
654 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
655 struct irq_data *data);
657 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
658 unsigned int offset);
660 #ifdef CONFIG_GPIOLIB_IRQCHIP
661 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
662 struct irq_domain *domain);
664 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
665 struct irq_domain *domain)
672 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
673 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
674 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
675 unsigned long config);
678 * struct gpio_pin_range - pin range controlled by a gpio chip
679 * @node: list for maintaining set of pin ranges, used internally
680 * @pctldev: pinctrl device which handles corresponding pins
681 * @range: actual range of pins controlled by a gpio controller
683 struct gpio_pin_range {
684 struct list_head node;
685 struct pinctrl_dev *pctldev;
686 struct pinctrl_gpio_range range;
689 #ifdef CONFIG_PINCTRL
691 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
692 unsigned int gpio_offset, unsigned int pin_offset,
694 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
695 struct pinctrl_dev *pctldev,
696 unsigned int gpio_offset, const char *pin_group);
697 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
699 #else /* ! CONFIG_PINCTRL */
702 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
703 unsigned int gpio_offset, unsigned int pin_offset,
709 gpiochip_add_pingroup_range(struct gpio_chip *gc,
710 struct pinctrl_dev *pctldev,
711 unsigned int gpio_offset, const char *pin_group)
717 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
721 #endif /* CONFIG_PINCTRL */
723 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
726 enum gpio_lookup_flags lflags,
727 enum gpiod_flags dflags);
728 void gpiochip_free_own_desc(struct gpio_desc *desc);
730 #ifdef CONFIG_GPIOLIB
732 /* lock/unlock as IRQ */
733 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
734 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
737 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
739 #else /* CONFIG_GPIOLIB */
741 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
743 /* GPIO can never have been requested */
745 return ERR_PTR(-ENODEV);
748 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
755 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
760 #endif /* CONFIG_GPIOLIB */
762 #endif /* __LINUX_GPIO_DRIVER_H */