1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
24 #ifdef CONFIG_GPIOLIB_IRQCHIP
26 * struct gpio_irq_chip - GPIO interrupt controller
28 struct gpio_irq_chip {
32 * GPIO IRQ chip implementation, provided by GPIO driver.
34 struct irq_chip *chip;
39 * Interrupt translation domain; responsible for mapping between GPIO
40 * hwirq number and Linux IRQ number.
42 struct irq_domain *domain;
47 * Table of interrupt domain operations for this IRQ chip.
49 const struct irq_domain_ops *domain_ops;
54 * The IRQ handler to use (often a predefined IRQ core function) for
55 * GPIO IRQs, provided by GPIO driver.
57 irq_flow_handler_t handler;
62 * Default IRQ triggering type applied during GPIO driver
63 * initialization, provided by GPIO driver.
65 unsigned int default_type;
70 * Per GPIO IRQ chip lockdep class for IRQ lock.
72 struct lock_class_key *lock_key;
77 * Per GPIO IRQ chip lockdep class for IRQ request.
79 struct lock_class_key *request_key;
84 * The interrupt handler for the GPIO chip's parent interrupts, may be
85 * NULL if the parent interrupts are nested rather than cascaded.
87 irq_flow_handler_t parent_handler;
90 * @parent_handler_data:
92 * Data associated, and passed to, the handler for the parent
95 void *parent_handler_data;
100 * The number of interrupt parents of a GPIO chip.
102 unsigned int num_parents;
107 * For use by gpiochip_set_cascaded_irqchip()
109 unsigned int parent_irq;
114 * A list of interrupt parents of a GPIO chip. This is owned by the
115 * driver, so the core will only reference this list, not modify it.
117 unsigned int *parents;
122 * A list of interrupt parents for each line of a GPIO chip.
129 * True if set the interrupt handling uses nested threads.
136 * If set core allocates @valid_mask with all bits set to one.
138 bool need_valid_mask;
143 * If not %NULL holds bitmask of GPIOs which are valid to be included
144 * in IRQ domain of the chip.
146 unsigned long *valid_mask;
151 * Required for static IRQ allocation. If set, irq_domain_add_simple()
152 * will allocate and map all IRQs during initialization.
159 * Store old irq_chip irq_enable callback
161 void (*irq_enable)(struct irq_data *data);
166 * Store old irq_chip irq_disable callback
168 void (*irq_disable)(struct irq_data *data);
173 * struct gpio_chip - abstract a GPIO controller
174 * @label: a functional name for the GPIO device, such as a part
175 * number or the name of the SoC IP-block implementing it.
176 * @gpiodev: the internal state holder, opaque struct
177 * @parent: optional parent device providing the GPIOs
178 * @owner: helps prevent removal of modules exporting active GPIOs
179 * @request: optional hook for chip-specific activation, such as
180 * enabling module power and clock; may sleep
181 * @free: optional hook for chip-specific deactivation, such as
182 * disabling module power and clock; may sleep
183 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
184 * (same as GPIOF_DIR_XXX), or negative error.
185 * It is recommended to always implement this function, even on
186 * input-only or output-only gpio chips.
187 * @direction_input: configures signal "offset" as input, or returns error
188 * This can be omitted on input-only or output-only gpio chips.
189 * @direction_output: configures signal "offset" as output, or returns error
190 * This can be omitted on input-only or output-only gpio chips.
191 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
192 * @get_multiple: reads values for multiple signals defined by "mask" and
193 * stores them in "bits", returns 0 on success or negative error
194 * @set: assigns output value for signal "offset"
195 * @set_multiple: assigns output values for multiple signals defined by "mask"
196 * @set_config: optional hook for all kinds of settings. Uses the same
197 * packed config format as generic pinconf.
198 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
199 * implementation may not sleep
200 * @dbg_show: optional routine to show contents in debugfs; default code
201 * will be used when this is omitted, but custom code can show extra
202 * state (such as pullup/pulldown configuration).
203 * @base: identifies the first GPIO number handled by this chip;
204 * or, if negative during registration, requests dynamic ID allocation.
205 * DEPRECATION: providing anything non-negative and nailing the base
206 * offset of GPIO chips is deprecated. Please pass -1 as base to
207 * let gpiolib select the chip base in all possible cases. We want to
208 * get rid of the static GPIO number space in the long run.
209 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
210 * handled is (base + ngpio - 1).
211 * @names: if set, must be an array of strings to use as alternative
212 * names for the GPIOs in this chip. Any entry in the array
213 * may be NULL if there is no alias for the GPIO, however the
214 * array must be @ngpio entries long. A name can include a single printk
215 * format specifier for an unsigned int. It is substituted by the actual
216 * number of the gpio.
217 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
218 * must while accessing GPIO expander chips over I2C or SPI. This
219 * implies that if the chip supports IRQs, these IRQs need to be threaded
220 * as the chip access may sleep when e.g. reading out the IRQ status
222 * @read_reg: reader function for generic GPIO
223 * @write_reg: writer function for generic GPIO
224 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
225 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
226 * generic GPIO core. It is for internal housekeeping only.
227 * @reg_dat: data (in) register for generic GPIO
228 * @reg_set: output set register (out=high) for generic GPIO
229 * @reg_clr: output clear register (out=low) for generic GPIO
230 * @reg_dir_out: direction out setting register for generic GPIO
231 * @reg_dir_in: direction in setting register for generic GPIO
232 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
233 * be read and we need to rely on out internal state tracking.
234 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
235 * <register width> * 8
236 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
237 * shadowed and real data registers writes together.
238 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
240 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
241 * direction safely. A "1" in this word means the line is set as
244 * A gpio_chip can help platforms abstract various sources of GPIOs so
245 * they can all be accessed through a common programing interface.
246 * Example sources would be SOC controllers, FPGAs, multifunction
247 * chips, dedicated GPIO expanders, and so on.
249 * Each chip controls a number of signals, identified in method calls
250 * by "offset" values in the range 0..(@ngpio - 1). When those signals
251 * are referenced through calls like gpio_get_value(gpio), the offset
252 * is calculated by subtracting @base from the gpio number.
256 struct gpio_device *gpiodev;
257 struct device *parent;
258 struct module *owner;
260 int (*request)(struct gpio_chip *chip,
262 void (*free)(struct gpio_chip *chip,
264 int (*get_direction)(struct gpio_chip *chip,
266 int (*direction_input)(struct gpio_chip *chip,
268 int (*direction_output)(struct gpio_chip *chip,
269 unsigned offset, int value);
270 int (*get)(struct gpio_chip *chip,
272 int (*get_multiple)(struct gpio_chip *chip,
274 unsigned long *bits);
275 void (*set)(struct gpio_chip *chip,
276 unsigned offset, int value);
277 void (*set_multiple)(struct gpio_chip *chip,
279 unsigned long *bits);
280 int (*set_config)(struct gpio_chip *chip,
282 unsigned long config);
283 int (*to_irq)(struct gpio_chip *chip,
286 void (*dbg_show)(struct seq_file *s,
287 struct gpio_chip *chip);
289 int (*init_valid_mask)(struct gpio_chip *chip);
293 const char *const *names;
296 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
297 unsigned long (*read_reg)(void __iomem *reg);
298 void (*write_reg)(void __iomem *reg, unsigned long data);
300 void __iomem *reg_dat;
301 void __iomem *reg_set;
302 void __iomem *reg_clr;
303 void __iomem *reg_dir_out;
304 void __iomem *reg_dir_in;
305 bool bgpio_dir_unreadable;
307 spinlock_t bgpio_lock;
308 unsigned long bgpio_data;
309 unsigned long bgpio_dir;
312 #ifdef CONFIG_GPIOLIB_IRQCHIP
314 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
315 * to handle IRQs for most practical cases.
321 * Integrates interrupt chip functionality with the GPIO chip. Can be
322 * used to handle IRQs for most practical cases.
324 struct gpio_irq_chip irq;
330 * If set core allocates @valid_mask with all its values initialized
331 * with init_valid_mask() or set to one if init_valid_mask() is not
334 bool need_valid_mask;
339 * If not %NULL holds bitmask of GPIOs which are valid to be used
342 unsigned long *valid_mask;
344 #if defined(CONFIG_OF_GPIO)
346 * If CONFIG_OF is enabled, then all GPIO controllers described in the
347 * device tree automatically may have an OF translation
353 * Pointer to a device tree node representing this GPIO controller.
355 struct device_node *of_node;
360 * Number of cells used to form the GPIO specifier.
362 unsigned int of_gpio_n_cells;
367 * Callback to translate a device tree GPIO specifier into a chip-
368 * relative GPIO number and flags.
370 int (*of_xlate)(struct gpio_chip *gc,
371 const struct of_phandle_args *gpiospec, u32 *flags);
375 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
378 /* add/remove chips */
379 extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
380 struct lock_class_key *lock_key,
381 struct lock_class_key *request_key);
384 * gpiochip_add_data() - register a gpio_chip
385 * @chip: the chip to register, with chip->base initialized
386 * @data: driver-private data associated with this chip
388 * Context: potentially before irqs will work
390 * When gpiochip_add_data() is called very early during boot, so that GPIOs
391 * can be freely used, the chip->parent device must be registered before
392 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
393 * for GPIOs will fail rudely.
395 * gpiochip_add_data() must only be called after gpiolib initialization,
396 * ie after core_initcall().
398 * If chip->base is negative, this requests dynamic assignment of
399 * a range of valid GPIOs.
402 * A negative errno if the chip can't be registered, such as because the
403 * chip->base is invalid or already associated with a different chip.
404 * Otherwise it returns zero as a success code.
406 #ifdef CONFIG_LOCKDEP
407 #define gpiochip_add_data(chip, data) ({ \
408 static struct lock_class_key lock_key; \
409 static struct lock_class_key request_key; \
410 gpiochip_add_data_with_key(chip, data, &lock_key, \
414 #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL)
417 static inline int gpiochip_add(struct gpio_chip *chip)
419 return gpiochip_add_data(chip, NULL);
421 extern void gpiochip_remove(struct gpio_chip *chip);
422 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
425 extern struct gpio_chip *gpiochip_find(void *data,
426 int (*match)(struct gpio_chip *chip, void *data));
428 /* lock/unlock as IRQ */
429 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
430 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
431 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
432 int gpiochip_reqres_irq(struct gpio_chip *chip, unsigned int offset);
433 void gpiochip_relres_irq(struct gpio_chip *chip, unsigned int offset);
434 void gpiochip_disable_irq(struct gpio_chip *chip, unsigned int offset);
435 void gpiochip_enable_irq(struct gpio_chip *chip, unsigned int offset);
437 /* Line status inquiry for drivers */
438 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
439 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
441 /* Sleep persistence inquiry for drivers */
442 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
443 bool gpiochip_line_is_valid(const struct gpio_chip *chip, unsigned int offset);
445 /* get driver data */
446 void *gpiochip_get_data(struct gpio_chip *chip);
448 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
456 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
458 int bgpio_init(struct gpio_chip *gc, struct device *dev,
459 unsigned long sz, void __iomem *dat, void __iomem *set,
460 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
461 unsigned long flags);
463 #define BGPIOF_BIG_ENDIAN BIT(0)
464 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
465 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
466 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
467 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
468 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
472 #ifdef CONFIG_GPIOLIB_IRQCHIP
474 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
475 irq_hw_number_t hwirq);
476 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
478 int gpiochip_irq_domain_activate(struct irq_domain *domain,
479 struct irq_data *data, bool reserve);
480 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
481 struct irq_data *data);
483 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
484 struct irq_chip *irqchip,
485 unsigned int parent_irq,
486 irq_flow_handler_t parent_handler);
488 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
489 struct irq_chip *irqchip,
490 unsigned int parent_irq);
492 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
493 struct irq_chip *irqchip,
494 unsigned int first_irq,
495 irq_flow_handler_t handler,
498 struct lock_class_key *lock_key,
499 struct lock_class_key *request_key);
501 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
502 unsigned int offset);
504 #ifdef CONFIG_LOCKDEP
507 * Lockdep requires that each irqchip instance be created with a
508 * unique key so as to avoid unnecessary warnings. This upfront
509 * boilerplate static inlines provides such a key for each
512 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
513 struct irq_chip *irqchip,
514 unsigned int first_irq,
515 irq_flow_handler_t handler,
518 static struct lock_class_key lock_key;
519 static struct lock_class_key request_key;
521 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
522 handler, type, false,
523 &lock_key, &request_key);
526 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
527 struct irq_chip *irqchip,
528 unsigned int first_irq,
529 irq_flow_handler_t handler,
533 static struct lock_class_key lock_key;
534 static struct lock_class_key request_key;
536 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
538 &lock_key, &request_key);
541 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
542 struct irq_chip *irqchip,
543 unsigned int first_irq,
544 irq_flow_handler_t handler,
547 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
548 handler, type, false, NULL, NULL);
551 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
552 struct irq_chip *irqchip,
553 unsigned int first_irq,
554 irq_flow_handler_t handler,
557 return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
558 handler, type, true, NULL, NULL);
560 #endif /* CONFIG_LOCKDEP */
562 #endif /* CONFIG_GPIOLIB_IRQCHIP */
564 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
565 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
566 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
567 unsigned long config);
569 #ifdef CONFIG_PINCTRL
572 * struct gpio_pin_range - pin range controlled by a gpio chip
573 * @node: list for maintaining set of pin ranges, used internally
574 * @pctldev: pinctrl device which handles corresponding pins
575 * @range: actual range of pins controlled by a gpio controller
577 struct gpio_pin_range {
578 struct list_head node;
579 struct pinctrl_dev *pctldev;
580 struct pinctrl_gpio_range range;
583 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
584 unsigned int gpio_offset, unsigned int pin_offset,
586 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
587 struct pinctrl_dev *pctldev,
588 unsigned int gpio_offset, const char *pin_group);
589 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
594 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
595 unsigned int gpio_offset, unsigned int pin_offset,
601 gpiochip_add_pingroup_range(struct gpio_chip *chip,
602 struct pinctrl_dev *pctldev,
603 unsigned int gpio_offset, const char *pin_group)
609 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
613 #endif /* CONFIG_PINCTRL */
615 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
617 enum gpiod_flags flags);
618 void gpiochip_free_own_desc(struct gpio_desc *desc);
620 void devprop_gpiochip_set_names(struct gpio_chip *chip,
621 const struct fwnode_handle *fwnode);
623 #else /* CONFIG_GPIOLIB */
625 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
627 /* GPIO can never have been requested */
629 return ERR_PTR(-ENODEV);
632 #endif /* CONFIG_GPIOLIB */