1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __LINUX_GPIO_DRIVER_H
3 #define __LINUX_GPIO_DRIVER_H
5 #include <linux/device.h>
6 #include <linux/types.h>
8 #include <linux/irqchip/chained_irq.h>
9 #include <linux/irqdomain.h>
10 #include <linux/lockdep.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinconf-generic.h>
15 struct of_phandle_args;
21 enum gpio_lookup_flags;
25 #define GPIO_LINE_DIRECTION_IN 1
26 #define GPIO_LINE_DIRECTION_OUT 0
29 * struct gpio_irq_chip - GPIO interrupt controller
31 struct gpio_irq_chip {
35 * GPIO IRQ chip implementation, provided by GPIO driver.
37 struct irq_chip *chip;
42 * Interrupt translation domain; responsible for mapping between GPIO
43 * hwirq number and Linux IRQ number.
45 struct irq_domain *domain;
50 * Table of interrupt domain operations for this IRQ chip.
52 const struct irq_domain_ops *domain_ops;
54 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
58 * Firmware node corresponding to this gpiochip/irqchip, necessary
59 * for hierarchical irqdomain support.
61 struct fwnode_handle *fwnode;
66 * If non-NULL, will be set as the parent of this GPIO interrupt
67 * controller's IRQ domain to establish a hierarchical interrupt
68 * domain. The presence of this will activate the hierarchical
71 struct irq_domain *parent_domain;
74 * @child_to_parent_hwirq:
76 * This callback translates a child hardware IRQ offset to a parent
77 * hardware IRQ offset on a hierarchical interrupt chip. The child
78 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
79 * ngpio field of struct gpio_chip) and the corresponding parent
80 * hardware IRQ and type (such as IRQ_TYPE_*) shall be returned by
81 * the driver. The driver can calculate this from an offset or using
82 * a lookup table or whatever method is best for this chip. Return
83 * 0 on successful translation in the driver.
85 * If some ranges of hardware IRQs do not have a corresponding parent
86 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
87 * @need_valid_mask to make these GPIO lines unavailable for
90 int (*child_to_parent_hwirq)(struct gpio_chip *gc,
91 unsigned int child_hwirq,
92 unsigned int child_type,
93 unsigned int *parent_hwirq,
94 unsigned int *parent_type);
97 * @populate_parent_alloc_arg :
99 * This optional callback allocates and populates the specific struct
100 * for the parent's IRQ domain. If this is not specified, then
101 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
102 * variant named &gpiochip_populate_parent_fwspec_fourcell is also
105 void *(*populate_parent_alloc_arg)(struct gpio_chip *gc,
106 unsigned int parent_hwirq,
107 unsigned int parent_type);
110 * @child_offset_to_irq:
112 * This optional callback is used to translate the child's GPIO line
113 * offset on the GPIO chip to an IRQ number for the GPIO to_irq()
114 * callback. If this is not specified, then a default callback will be
115 * provided that returns the line offset.
117 unsigned int (*child_offset_to_irq)(struct gpio_chip *gc,
121 * @child_irq_domain_ops:
123 * The IRQ domain operations that will be used for this GPIO IRQ
124 * chip. If no operations are provided, then default callbacks will
125 * be populated to setup the IRQ hierarchy. Some drivers need to
126 * supply their own translate function.
128 struct irq_domain_ops child_irq_domain_ops;
134 * The IRQ handler to use (often a predefined IRQ core function) for
135 * GPIO IRQs, provided by GPIO driver.
137 irq_flow_handler_t handler;
142 * Default IRQ triggering type applied during GPIO driver
143 * initialization, provided by GPIO driver.
145 unsigned int default_type;
150 * Per GPIO IRQ chip lockdep class for IRQ lock.
152 struct lock_class_key *lock_key;
157 * Per GPIO IRQ chip lockdep class for IRQ request.
159 struct lock_class_key *request_key;
164 * The interrupt handler for the GPIO chip's parent interrupts, may be
165 * NULL if the parent interrupts are nested rather than cascaded.
167 irq_flow_handler_t parent_handler;
170 * @parent_handler_data:
172 * If @per_parent_data is false, @parent_handler_data is a single
173 * pointer used as the data associated with every parent interrupt.
175 * @parent_handler_data_array:
177 * If @per_parent_data is true, @parent_handler_data_array is
178 * an array of @num_parents pointers, and is used to associate
179 * different data for each parent. This cannot be NULL if
180 * @per_parent_data is true.
183 void *parent_handler_data;
184 void **parent_handler_data_array;
190 * The number of interrupt parents of a GPIO chip.
192 unsigned int num_parents;
197 * A list of interrupt parents of a GPIO chip. This is owned by the
198 * driver, so the core will only reference this list, not modify it.
200 unsigned int *parents;
205 * A list of interrupt parents for each line of a GPIO chip.
212 * True if set the interrupt handling uses nested threads.
219 * True if parent_handler_data_array describes a @num_parents
220 * sized array to be used as parent data.
222 bool per_parent_data;
225 * @init_hw: optional routine to initialize hardware before
226 * an IRQ chip will be added. This is quite useful when
227 * a particular driver wants to clear IRQ related registers
228 * in order to avoid undesired events.
230 int (*init_hw)(struct gpio_chip *gc);
233 * @init_valid_mask: optional routine to initialize @valid_mask, to be
234 * used if not all GPIO lines are valid interrupts. Sometimes some
235 * lines just cannot fire interrupts, and this routine, when defined,
236 * is passed a bitmap in "valid_mask" and it will have ngpios
237 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
238 * then directly set some bits to "0" if they cannot be used for
241 void (*init_valid_mask)(struct gpio_chip *gc,
242 unsigned long *valid_mask,
243 unsigned int ngpios);
248 * If not %NULL, holds bitmask of GPIOs which are valid to be included
249 * in IRQ domain of the chip.
251 unsigned long *valid_mask;
256 * Required for static IRQ allocation. If set, irq_domain_add_simple()
257 * will allocate and map all IRQs during initialization.
264 * Store old irq_chip irq_enable callback
266 void (*irq_enable)(struct irq_data *data);
271 * Store old irq_chip irq_disable callback
273 void (*irq_disable)(struct irq_data *data);
277 * Store old irq_chip irq_unmask callback
279 void (*irq_unmask)(struct irq_data *data);
284 * Store old irq_chip irq_mask callback
286 void (*irq_mask)(struct irq_data *data);
290 * struct gpio_chip - abstract a GPIO controller
291 * @label: a functional name for the GPIO device, such as a part
292 * number or the name of the SoC IP-block implementing it.
293 * @gpiodev: the internal state holder, opaque struct
294 * @parent: optional parent device providing the GPIOs
295 * @fwnode: optional fwnode providing this controller's properties
296 * @owner: helps prevent removal of modules exporting active GPIOs
297 * @request: optional hook for chip-specific activation, such as
298 * enabling module power and clock; may sleep
299 * @free: optional hook for chip-specific deactivation, such as
300 * disabling module power and clock; may sleep
301 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
302 * (same as GPIO_LINE_DIRECTION_OUT / GPIO_LINE_DIRECTION_IN),
303 * or negative error. It is recommended to always implement this
304 * function, even on input-only or output-only gpio chips.
305 * @direction_input: configures signal "offset" as input, or returns error
306 * This can be omitted on input-only or output-only gpio chips.
307 * @direction_output: configures signal "offset" as output, or returns error
308 * This can be omitted on input-only or output-only gpio chips.
309 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
310 * @get_multiple: reads values for multiple signals defined by "mask" and
311 * stores them in "bits", returns 0 on success or negative error
312 * @set: assigns output value for signal "offset"
313 * @set_multiple: assigns output values for multiple signals defined by "mask"
314 * @set_config: optional hook for all kinds of settings. Uses the same
315 * packed config format as generic pinconf.
316 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
317 * implementation may not sleep
318 * @dbg_show: optional routine to show contents in debugfs; default code
319 * will be used when this is omitted, but custom code can show extra
320 * state (such as pullup/pulldown configuration).
321 * @init_valid_mask: optional routine to initialize @valid_mask, to be used if
322 * not all GPIOs are valid.
323 * @add_pin_ranges: optional routine to initialize pin ranges, to be used when
324 * requires special mapping of the pins that provides GPIO functionality.
325 * It is called after adding GPIO chip and before adding IRQ chip.
326 * @base: identifies the first GPIO number handled by this chip;
327 * or, if negative during registration, requests dynamic ID allocation.
328 * DEPRECATION: providing anything non-negative and nailing the base
329 * offset of GPIO chips is deprecated. Please pass -1 as base to
330 * let gpiolib select the chip base in all possible cases. We want to
331 * get rid of the static GPIO number space in the long run.
332 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
333 * handled is (base + ngpio - 1).
334 * @offset: when multiple gpio chips belong to the same device this
335 * can be used as offset within the device so friendly names can
336 * be properly assigned.
337 * @names: if set, must be an array of strings to use as alternative
338 * names for the GPIOs in this chip. Any entry in the array
339 * may be NULL if there is no alias for the GPIO, however the
340 * array must be @ngpio entries long. A name can include a single printk
341 * format specifier for an unsigned int. It is substituted by the actual
342 * number of the gpio.
343 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
344 * must while accessing GPIO expander chips over I2C or SPI. This
345 * implies that if the chip supports IRQs, these IRQs need to be threaded
346 * as the chip access may sleep when e.g. reading out the IRQ status
348 * @read_reg: reader function for generic GPIO
349 * @write_reg: writer function for generic GPIO
350 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
351 * line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
352 * generic GPIO core. It is for internal housekeeping only.
353 * @reg_dat: data (in) register for generic GPIO
354 * @reg_set: output set register (out=high) for generic GPIO
355 * @reg_clr: output clear register (out=low) for generic GPIO
356 * @reg_dir_out: direction out setting register for generic GPIO
357 * @reg_dir_in: direction in setting register for generic GPIO
358 * @bgpio_dir_unreadable: indicates that the direction register(s) cannot
359 * be read and we need to rely on out internal state tracking.
360 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
361 * <register width> * 8
362 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
363 * shadowed and real data registers writes together.
364 * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
366 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
367 * direction safely. A "1" in this word means the line is set as
370 * A gpio_chip can help platforms abstract various sources of GPIOs so
371 * they can all be accessed through a common programming interface.
372 * Example sources would be SOC controllers, FPGAs, multifunction
373 * chips, dedicated GPIO expanders, and so on.
375 * Each chip controls a number of signals, identified in method calls
376 * by "offset" values in the range 0..(@ngpio - 1). When those signals
377 * are referenced through calls like gpio_get_value(gpio), the offset
378 * is calculated by subtracting @base from the gpio number.
382 struct gpio_device *gpiodev;
383 struct device *parent;
384 struct fwnode_handle *fwnode;
385 struct module *owner;
387 int (*request)(struct gpio_chip *gc,
388 unsigned int offset);
389 void (*free)(struct gpio_chip *gc,
390 unsigned int offset);
391 int (*get_direction)(struct gpio_chip *gc,
392 unsigned int offset);
393 int (*direction_input)(struct gpio_chip *gc,
394 unsigned int offset);
395 int (*direction_output)(struct gpio_chip *gc,
396 unsigned int offset, int value);
397 int (*get)(struct gpio_chip *gc,
398 unsigned int offset);
399 int (*get_multiple)(struct gpio_chip *gc,
401 unsigned long *bits);
402 void (*set)(struct gpio_chip *gc,
403 unsigned int offset, int value);
404 void (*set_multiple)(struct gpio_chip *gc,
406 unsigned long *bits);
407 int (*set_config)(struct gpio_chip *gc,
409 unsigned long config);
410 int (*to_irq)(struct gpio_chip *gc,
411 unsigned int offset);
413 void (*dbg_show)(struct seq_file *s,
414 struct gpio_chip *gc);
416 int (*init_valid_mask)(struct gpio_chip *gc,
417 unsigned long *valid_mask,
418 unsigned int ngpios);
420 int (*add_pin_ranges)(struct gpio_chip *gc);
425 const char *const *names;
428 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
429 unsigned long (*read_reg)(void __iomem *reg);
430 void (*write_reg)(void __iomem *reg, unsigned long data);
432 void __iomem *reg_dat;
433 void __iomem *reg_set;
434 void __iomem *reg_clr;
435 void __iomem *reg_dir_out;
436 void __iomem *reg_dir_in;
437 bool bgpio_dir_unreadable;
439 spinlock_t bgpio_lock;
440 unsigned long bgpio_data;
441 unsigned long bgpio_dir;
442 #endif /* CONFIG_GPIO_GENERIC */
444 #ifdef CONFIG_GPIOLIB_IRQCHIP
446 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
447 * to handle IRQs for most practical cases.
453 * Integrates interrupt chip functionality with the GPIO chip. Can be
454 * used to handle IRQs for most practical cases.
456 struct gpio_irq_chip irq;
457 #endif /* CONFIG_GPIOLIB_IRQCHIP */
462 * If not %NULL, holds bitmask of GPIOs which are valid to be used
465 unsigned long *valid_mask;
467 #if defined(CONFIG_OF_GPIO)
469 * If CONFIG_OF_GPIO is enabled, then all GPIO controllers described in
470 * the device tree automatically may have an OF translation
476 * Pointer to a device tree node representing this GPIO controller.
478 struct device_node *of_node;
483 * Number of cells used to form the GPIO specifier.
485 unsigned int of_gpio_n_cells;
490 * Callback to translate a device tree GPIO specifier into a chip-
491 * relative GPIO number and flags.
493 int (*of_xlate)(struct gpio_chip *gc,
494 const struct of_phandle_args *gpiospec, u32 *flags);
495 #endif /* CONFIG_OF_GPIO */
498 extern const char *gpiochip_is_requested(struct gpio_chip *gc,
499 unsigned int offset);
502 * for_each_requested_gpio_in_range - iterates over requested GPIOs in a given range
503 * @chip: the chip to query
505 * @base: first GPIO in the range
506 * @size: amount of GPIOs to check starting from @base
507 * @label: label of current GPIO
509 #define for_each_requested_gpio_in_range(chip, i, base, size, label) \
510 for (i = 0; i < size; i++) \
511 if ((label = gpiochip_is_requested(chip, base + i)) == NULL) {} else
513 /* Iterates over all requested GPIO of the given @chip */
514 #define for_each_requested_gpio(chip, i, label) \
515 for_each_requested_gpio_in_range(chip, i, 0, chip->ngpio, label)
517 /* add/remove chips */
518 extern int gpiochip_add_data_with_key(struct gpio_chip *gc, void *data,
519 struct lock_class_key *lock_key,
520 struct lock_class_key *request_key);
523 * gpiochip_add_data() - register a gpio_chip
524 * @gc: the chip to register, with gc->base initialized
525 * @data: driver-private data associated with this chip
527 * Context: potentially before irqs will work
529 * When gpiochip_add_data() is called very early during boot, so that GPIOs
530 * can be freely used, the gc->parent device must be registered before
531 * the gpio framework's arch_initcall(). Otherwise sysfs initialization
532 * for GPIOs will fail rudely.
534 * gpiochip_add_data() must only be called after gpiolib initialization,
535 * i.e. after core_initcall().
537 * If gc->base is negative, this requests dynamic assignment of
538 * a range of valid GPIOs.
541 * A negative errno if the chip can't be registered, such as because the
542 * gc->base is invalid or already associated with a different chip.
543 * Otherwise it returns zero as a success code.
545 #ifdef CONFIG_LOCKDEP
546 #define gpiochip_add_data(gc, data) ({ \
547 static struct lock_class_key lock_key; \
548 static struct lock_class_key request_key; \
549 gpiochip_add_data_with_key(gc, data, &lock_key, \
552 #define devm_gpiochip_add_data(dev, gc, data) ({ \
553 static struct lock_class_key lock_key; \
554 static struct lock_class_key request_key; \
555 devm_gpiochip_add_data_with_key(dev, gc, data, &lock_key, \
559 #define gpiochip_add_data(gc, data) gpiochip_add_data_with_key(gc, data, NULL, NULL)
560 #define devm_gpiochip_add_data(dev, gc, data) \
561 devm_gpiochip_add_data_with_key(dev, gc, data, NULL, NULL)
562 #endif /* CONFIG_LOCKDEP */
564 static inline int gpiochip_add(struct gpio_chip *gc)
566 return gpiochip_add_data(gc, NULL);
568 extern void gpiochip_remove(struct gpio_chip *gc);
569 extern int devm_gpiochip_add_data_with_key(struct device *dev, struct gpio_chip *gc, void *data,
570 struct lock_class_key *lock_key,
571 struct lock_class_key *request_key);
573 extern struct gpio_chip *gpiochip_find(void *data,
574 int (*match)(struct gpio_chip *gc, void *data));
576 bool gpiochip_line_is_irq(struct gpio_chip *gc, unsigned int offset);
577 int gpiochip_reqres_irq(struct gpio_chip *gc, unsigned int offset);
578 void gpiochip_relres_irq(struct gpio_chip *gc, unsigned int offset);
579 void gpiochip_disable_irq(struct gpio_chip *gc, unsigned int offset);
580 void gpiochip_enable_irq(struct gpio_chip *gc, unsigned int offset);
582 /* Line status inquiry for drivers */
583 bool gpiochip_line_is_open_drain(struct gpio_chip *gc, unsigned int offset);
584 bool gpiochip_line_is_open_source(struct gpio_chip *gc, unsigned int offset);
586 /* Sleep persistence inquiry for drivers */
587 bool gpiochip_line_is_persistent(struct gpio_chip *gc, unsigned int offset);
588 bool gpiochip_line_is_valid(const struct gpio_chip *gc, unsigned int offset);
590 /* get driver data */
591 void *gpiochip_get_data(struct gpio_chip *gc);
599 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
601 void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
602 unsigned int parent_hwirq,
603 unsigned int parent_type);
604 void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
605 unsigned int parent_hwirq,
606 unsigned int parent_type);
610 static inline void *gpiochip_populate_parent_fwspec_twocell(struct gpio_chip *gc,
611 unsigned int parent_hwirq,
612 unsigned int parent_type)
617 static inline void *gpiochip_populate_parent_fwspec_fourcell(struct gpio_chip *gc,
618 unsigned int parent_hwirq,
619 unsigned int parent_type)
624 #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
626 int bgpio_init(struct gpio_chip *gc, struct device *dev,
627 unsigned long sz, void __iomem *dat, void __iomem *set,
628 void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
629 unsigned long flags);
631 #define BGPIOF_BIG_ENDIAN BIT(0)
632 #define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
633 #define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
634 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
635 #define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
636 #define BGPIOF_NO_OUTPUT BIT(5) /* only input */
637 #define BGPIOF_NO_SET_ON_INPUT BIT(6)
639 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
640 irq_hw_number_t hwirq);
641 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
643 int gpiochip_irq_domain_activate(struct irq_domain *domain,
644 struct irq_data *data, bool reserve);
645 void gpiochip_irq_domain_deactivate(struct irq_domain *domain,
646 struct irq_data *data);
648 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gc,
649 unsigned int offset);
651 #ifdef CONFIG_GPIOLIB_IRQCHIP
652 int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
653 struct irq_domain *domain);
655 static inline int gpiochip_irqchip_add_domain(struct gpio_chip *gc,
656 struct irq_domain *domain)
663 int gpiochip_generic_request(struct gpio_chip *gc, unsigned int offset);
664 void gpiochip_generic_free(struct gpio_chip *gc, unsigned int offset);
665 int gpiochip_generic_config(struct gpio_chip *gc, unsigned int offset,
666 unsigned long config);
669 * struct gpio_pin_range - pin range controlled by a gpio chip
670 * @node: list for maintaining set of pin ranges, used internally
671 * @pctldev: pinctrl device which handles corresponding pins
672 * @range: actual range of pins controlled by a gpio controller
674 struct gpio_pin_range {
675 struct list_head node;
676 struct pinctrl_dev *pctldev;
677 struct pinctrl_gpio_range range;
680 #ifdef CONFIG_PINCTRL
682 int gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
683 unsigned int gpio_offset, unsigned int pin_offset,
685 int gpiochip_add_pingroup_range(struct gpio_chip *gc,
686 struct pinctrl_dev *pctldev,
687 unsigned int gpio_offset, const char *pin_group);
688 void gpiochip_remove_pin_ranges(struct gpio_chip *gc);
690 #else /* ! CONFIG_PINCTRL */
693 gpiochip_add_pin_range(struct gpio_chip *gc, const char *pinctl_name,
694 unsigned int gpio_offset, unsigned int pin_offset,
700 gpiochip_add_pingroup_range(struct gpio_chip *gc,
701 struct pinctrl_dev *pctldev,
702 unsigned int gpio_offset, const char *pin_group)
708 gpiochip_remove_pin_ranges(struct gpio_chip *gc)
712 #endif /* CONFIG_PINCTRL */
714 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *gc,
717 enum gpio_lookup_flags lflags,
718 enum gpiod_flags dflags);
719 void gpiochip_free_own_desc(struct gpio_desc *desc);
721 #ifdef CONFIG_GPIOLIB
723 /* lock/unlock as IRQ */
724 int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset);
725 void gpiochip_unlock_as_irq(struct gpio_chip *gc, unsigned int offset);
728 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
730 #else /* CONFIG_GPIOLIB */
732 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
734 /* GPIO can never have been requested */
736 return ERR_PTR(-ENODEV);
739 static inline int gpiochip_lock_as_irq(struct gpio_chip *gc,
746 static inline void gpiochip_unlock_as_irq(struct gpio_chip *gc,
751 #endif /* CONFIG_GPIOLIB */
753 #endif /* __LINUX_GPIO_DRIVER_H */