include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2019 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #define ZYNQMP_PM_VERSION_MAJOR 1
  17 #define ZYNQMP_PM_VERSION_MINOR 0
  18
  19 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  20                                         ZYNQMP_PM_VERSION_MINOR)
  21
  22 #define ZYNQMP_TZ_VERSION_MAJOR 1
  23 #define ZYNQMP_TZ_VERSION_MINOR 0
  24
  25 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  26                                         ZYNQMP_TZ_VERSION_MINOR)
  27
  28 /* SMC SIP service Call Function Identifier Prefix */
  29 #define PM_SIP_SVC                      0xC2000000
  30 #define PM_GET_TRUSTZONE_VERSION        0xa03
  31 #define PM_SET_SUSPEND_MODE             0xa02
  32 #define GET_CALLBACK_DATA               0xa01
  33
  34 /* Number of 32bits values in payload */
  35 #define PAYLOAD_ARG_CNT 4U
  36
  37 /* Number of arguments for a callback */
  38 #define CB_ARG_CNT     4
  39
  40 /* Payload size (consists of callback API ID + arguments) */
  41 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  42
  43 #define ZYNQMP_PM_MAX_QOS               100U
  44
  45 /* Node capabilities */
  46 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  47 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  48 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  49 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  50
  51 /* Feature check status */
  52 #define PM_FEATURE_INVALID              -1
  53 #define PM_FEATURE_UNCHECKED            0
  54
  55 /*
  56  * Firmware FPGA Manager flags
  57  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  58  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  59  */
  60 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  61 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  62
  63 enum pm_api_id {
  64         PM_GET_API_VERSION = 1,
  65         PM_REQUEST_NODE = 13,
  66         PM_RELEASE_NODE,
  67         PM_SET_REQUIREMENT,
  68         PM_RESET_ASSERT = 17,
  69         PM_RESET_GET_STATUS,
  70         PM_PM_INIT_FINALIZE = 21,
  71         PM_FPGA_LOAD,
  72         PM_FPGA_GET_STATUS,
  73         PM_GET_CHIPID = 24,
  74         PM_IOCTL = 34,
  75         PM_QUERY_DATA,
  76         PM_CLOCK_ENABLE,
  77         PM_CLOCK_DISABLE,
  78         PM_CLOCK_GETSTATE,
  79         PM_CLOCK_SETDIVIDER,
  80         PM_CLOCK_GETDIVIDER,
  81         PM_CLOCK_SETRATE,
  82         PM_CLOCK_GETRATE,
  83         PM_CLOCK_SETPARENT,
  84         PM_CLOCK_GETPARENT,
  85         PM_SECURE_AES = 47,
  86         PM_FEATURE_CHECK = 63,
  87         PM_API_MAX,
  88 };
  89
  90 /* PMU-FW return status codes */
  91 enum pm_ret_status {
  92         XST_PM_SUCCESS = 0,
  93         XST_PM_NO_FEATURE = 19,
  94         XST_PM_INTERNAL = 2000,
  95         XST_PM_CONFLICT,
  96         XST_PM_NO_ACCESS,
  97         XST_PM_INVALID_NODE,
  98         XST_PM_DOUBLE_REQ,
  99         XST_PM_ABORT_SUSPEND,
 100         XST_PM_MULT_USER = 2008,
 101 };
 102
 103 enum pm_ioctl_id {
 104         IOCTL_SD_DLL_RESET = 6,
 105         IOCTL_SET_SD_TAPDELAY,
 106         IOCTL_SET_PLL_FRAC_MODE,
 107         IOCTL_GET_PLL_FRAC_MODE,
 108         IOCTL_SET_PLL_FRAC_DATA,
 109         IOCTL_GET_PLL_FRAC_DATA,
 110 };
 111
 112 enum pm_query_id {
 113         PM_QID_INVALID,
 114         PM_QID_CLOCK_GET_NAME,
 115         PM_QID_CLOCK_GET_TOPOLOGY,
 116         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
 117         PM_QID_CLOCK_GET_PARENTS,
 118         PM_QID_CLOCK_GET_ATTRIBUTES,
 119         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 120         PM_QID_CLOCK_GET_MAX_DIVISOR,
 121 };
 122
 123 enum zynqmp_pm_reset_action {
 124         PM_RESET_ACTION_RELEASE,
 125         PM_RESET_ACTION_ASSERT,
 126         PM_RESET_ACTION_PULSE,
 127 };
 128
 129 enum zynqmp_pm_reset {
 130         ZYNQMP_PM_RESET_START = 1000,
 131         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 132         ZYNQMP_PM_RESET_PCIE_BRIDGE,
 133         ZYNQMP_PM_RESET_PCIE_CTRL,
 134         ZYNQMP_PM_RESET_DP,
 135         ZYNQMP_PM_RESET_SWDT_CRF,
 136         ZYNQMP_PM_RESET_AFI_FM5,
 137         ZYNQMP_PM_RESET_AFI_FM4,
 138         ZYNQMP_PM_RESET_AFI_FM3,
 139         ZYNQMP_PM_RESET_AFI_FM2,
 140         ZYNQMP_PM_RESET_AFI_FM1,
 141         ZYNQMP_PM_RESET_AFI_FM0,
 142         ZYNQMP_PM_RESET_GDMA,
 143         ZYNQMP_PM_RESET_GPU_PP1,
 144         ZYNQMP_PM_RESET_GPU_PP0,
 145         ZYNQMP_PM_RESET_GPU,
 146         ZYNQMP_PM_RESET_GT,
 147         ZYNQMP_PM_RESET_SATA,
 148         ZYNQMP_PM_RESET_ACPU3_PWRON,
 149         ZYNQMP_PM_RESET_ACPU2_PWRON,
 150         ZYNQMP_PM_RESET_ACPU1_PWRON,
 151         ZYNQMP_PM_RESET_ACPU0_PWRON,
 152         ZYNQMP_PM_RESET_APU_L2,
 153         ZYNQMP_PM_RESET_ACPU3,
 154         ZYNQMP_PM_RESET_ACPU2,
 155         ZYNQMP_PM_RESET_ACPU1,
 156         ZYNQMP_PM_RESET_ACPU0,
 157         ZYNQMP_PM_RESET_DDR,
 158         ZYNQMP_PM_RESET_APM_FPD,
 159         ZYNQMP_PM_RESET_SOFT,
 160         ZYNQMP_PM_RESET_GEM0,
 161         ZYNQMP_PM_RESET_GEM1,
 162         ZYNQMP_PM_RESET_GEM2,
 163         ZYNQMP_PM_RESET_GEM3,
 164         ZYNQMP_PM_RESET_QSPI,
 165         ZYNQMP_PM_RESET_UART0,
 166         ZYNQMP_PM_RESET_UART1,
 167         ZYNQMP_PM_RESET_SPI0,
 168         ZYNQMP_PM_RESET_SPI1,
 169         ZYNQMP_PM_RESET_SDIO0,
 170         ZYNQMP_PM_RESET_SDIO1,
 171         ZYNQMP_PM_RESET_CAN0,
 172         ZYNQMP_PM_RESET_CAN1,
 173         ZYNQMP_PM_RESET_I2C0,
 174         ZYNQMP_PM_RESET_I2C1,
 175         ZYNQMP_PM_RESET_TTC0,
 176         ZYNQMP_PM_RESET_TTC1,
 177         ZYNQMP_PM_RESET_TTC2,
 178         ZYNQMP_PM_RESET_TTC3,
 179         ZYNQMP_PM_RESET_SWDT_CRL,
 180         ZYNQMP_PM_RESET_NAND,
 181         ZYNQMP_PM_RESET_ADMA,
 182         ZYNQMP_PM_RESET_GPIO,
 183         ZYNQMP_PM_RESET_IOU_CC,
 184         ZYNQMP_PM_RESET_TIMESTAMP,
 185         ZYNQMP_PM_RESET_RPU_R50,
 186         ZYNQMP_PM_RESET_RPU_R51,
 187         ZYNQMP_PM_RESET_RPU_AMBA,
 188         ZYNQMP_PM_RESET_OCM,
 189         ZYNQMP_PM_RESET_RPU_PGE,
 190         ZYNQMP_PM_RESET_USB0_CORERESET,
 191         ZYNQMP_PM_RESET_USB1_CORERESET,
 192         ZYNQMP_PM_RESET_USB0_HIBERRESET,
 193         ZYNQMP_PM_RESET_USB1_HIBERRESET,
 194         ZYNQMP_PM_RESET_USB0_APB,
 195         ZYNQMP_PM_RESET_USB1_APB,
 196         ZYNQMP_PM_RESET_IPI,
 197         ZYNQMP_PM_RESET_APM_LPD,
 198         ZYNQMP_PM_RESET_RTC,
 199         ZYNQMP_PM_RESET_SYSMON,
 200         ZYNQMP_PM_RESET_AFI_FM6,
 201         ZYNQMP_PM_RESET_LPD_SWDT,
 202         ZYNQMP_PM_RESET_FPD,
 203         ZYNQMP_PM_RESET_RPU_DBG1,
 204         ZYNQMP_PM_RESET_RPU_DBG0,
 205         ZYNQMP_PM_RESET_DBG_LPD,
 206         ZYNQMP_PM_RESET_DBG_FPD,
 207         ZYNQMP_PM_RESET_APLL,
 208         ZYNQMP_PM_RESET_DPLL,
 209         ZYNQMP_PM_RESET_VPLL,
 210         ZYNQMP_PM_RESET_IOPLL,
 211         ZYNQMP_PM_RESET_RPLL,
 212         ZYNQMP_PM_RESET_GPO3_PL_0,
 213         ZYNQMP_PM_RESET_GPO3_PL_1,
 214         ZYNQMP_PM_RESET_GPO3_PL_2,
 215         ZYNQMP_PM_RESET_GPO3_PL_3,
 216         ZYNQMP_PM_RESET_GPO3_PL_4,
 217         ZYNQMP_PM_RESET_GPO3_PL_5,
 218         ZYNQMP_PM_RESET_GPO3_PL_6,
 219         ZYNQMP_PM_RESET_GPO3_PL_7,
 220         ZYNQMP_PM_RESET_GPO3_PL_8,
 221         ZYNQMP_PM_RESET_GPO3_PL_9,
 222         ZYNQMP_PM_RESET_GPO3_PL_10,
 223         ZYNQMP_PM_RESET_GPO3_PL_11,
 224         ZYNQMP_PM_RESET_GPO3_PL_12,
 225         ZYNQMP_PM_RESET_GPO3_PL_13,
 226         ZYNQMP_PM_RESET_GPO3_PL_14,
 227         ZYNQMP_PM_RESET_GPO3_PL_15,
 228         ZYNQMP_PM_RESET_GPO3_PL_16,
 229         ZYNQMP_PM_RESET_GPO3_PL_17,
 230         ZYNQMP_PM_RESET_GPO3_PL_18,
 231         ZYNQMP_PM_RESET_GPO3_PL_19,
 232         ZYNQMP_PM_RESET_GPO3_PL_20,
 233         ZYNQMP_PM_RESET_GPO3_PL_21,
 234         ZYNQMP_PM_RESET_GPO3_PL_22,
 235         ZYNQMP_PM_RESET_GPO3_PL_23,
 236         ZYNQMP_PM_RESET_GPO3_PL_24,
 237         ZYNQMP_PM_RESET_GPO3_PL_25,
 238         ZYNQMP_PM_RESET_GPO3_PL_26,
 239         ZYNQMP_PM_RESET_GPO3_PL_27,
 240         ZYNQMP_PM_RESET_GPO3_PL_28,
 241         ZYNQMP_PM_RESET_GPO3_PL_29,
 242         ZYNQMP_PM_RESET_GPO3_PL_30,
 243         ZYNQMP_PM_RESET_GPO3_PL_31,
 244         ZYNQMP_PM_RESET_RPU_LS,
 245         ZYNQMP_PM_RESET_PS_ONLY,
 246         ZYNQMP_PM_RESET_PL,
 247         ZYNQMP_PM_RESET_PS_PL0,
 248         ZYNQMP_PM_RESET_PS_PL1,
 249         ZYNQMP_PM_RESET_PS_PL2,
 250         ZYNQMP_PM_RESET_PS_PL3,
 251         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 252 };
 253
 254 enum zynqmp_pm_suspend_reason {
 255         SUSPEND_POWER_REQUEST = 201,
 256         SUSPEND_ALERT,
 257         SUSPEND_SYSTEM_SHUTDOWN,
 258 };
 259
 260 enum zynqmp_pm_request_ack {
 261         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 262         ZYNQMP_PM_REQUEST_ACK_BLOCKING,
 263         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
 264 };
 265
 266 enum pm_node_id {
 267         NODE_SD_0 = 39,
 268         NODE_SD_1,
 269 };
 270
 271 enum tap_delay_type {
 272         PM_TAPDELAY_INPUT = 0,
 273         PM_TAPDELAY_OUTPUT,
 274 };
 275
 276 enum dll_reset_type {
 277         PM_DLL_RESET_ASSERT,
 278         PM_DLL_RESET_RELEASE,
 279         PM_DLL_RESET_PULSE,
 280 };
 281
 282 /**
 283  * struct zynqmp_pm_query_data - PM query data
 284  * @qid:        query ID
 285  * @arg1:       Argument 1 of query data
 286  * @arg2:       Argument 2 of query data
 287  * @arg3:       Argument 3 of query data
 288  */
 289 struct zynqmp_pm_query_data {
 290         u32 qid;
 291         u32 arg1;
 292         u32 arg2;
 293         u32 arg3;
 294 };
 295
 296 struct zynqmp_eemi_ops {
 297         int (*get_api_version)(u32 *version);
 298         int (*get_chipid)(u32 *idcode, u32 *version);
 299         int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
 300         int (*fpga_get_status)(u32 *value);
 301         int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
 302         int (*clock_enable)(u32 clock_id);
 303         int (*clock_disable)(u32 clock_id);
 304         int (*clock_getstate)(u32 clock_id, u32 *state);
 305         int (*clock_setdivider)(u32 clock_id, u32 divider);
 306         int (*clock_getdivider)(u32 clock_id, u32 *divider);
 307         int (*clock_setrate)(u32 clock_id, u64 rate);
 308         int (*clock_getrate)(u32 clock_id, u64 *rate);
 309         int (*clock_setparent)(u32 clock_id, u32 parent_id);
 310         int (*clock_getparent)(u32 clock_id, u32 *parent_id);
 311         int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
 312         int (*reset_assert)(const enum zynqmp_pm_reset reset,
 313                             const enum zynqmp_pm_reset_action assert_flag);
 314         int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
 315         int (*init_finalize)(void);
 316         int (*set_suspend_mode)(u32 mode);
 317         int (*request_node)(const u32 node,
 318                             const u32 capabilities,
 319                             const u32 qos,
 320                             const enum zynqmp_pm_request_ack ack);
 321         int (*release_node)(const u32 node);
 322         int (*set_requirement)(const u32 node,
 323                                const u32 capabilities,
 324                                const u32 qos,
 325                                const enum zynqmp_pm_request_ack ack);
 326         int (*aes)(const u64 address, u32 *out);
 327 };
 328
 329 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 330                         u32 arg2, u32 arg3, u32 *ret_payload);
 331
 332 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 333 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
 334 #else
 335 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 336 {
 337         return ERR_PTR(-ENODEV);
 338 }
 339 #endif
 340
 341 #endif /* __FIRMWARE_ZYNQMP_H__ */