include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2019 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #include <linux/err.h>
  17
  18 #define ZYNQMP_PM_VERSION_MAJOR 1
  19 #define ZYNQMP_PM_VERSION_MINOR 0
  20
  21 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  22                                         ZYNQMP_PM_VERSION_MINOR)
  23
  24 #define ZYNQMP_TZ_VERSION_MAJOR 1
  25 #define ZYNQMP_TZ_VERSION_MINOR 0
  26
  27 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  28                                         ZYNQMP_TZ_VERSION_MINOR)
  29
  30 /* SMC SIP service Call Function Identifier Prefix */
  31 #define PM_SIP_SVC                      0xC2000000
  32 #define PM_GET_TRUSTZONE_VERSION        0xa03
  33 #define PM_SET_SUSPEND_MODE             0xa02
  34 #define GET_CALLBACK_DATA               0xa01
  35
  36 /* Number of 32bits values in payload */
  37 #define PAYLOAD_ARG_CNT 4U
  38
  39 /* Number of arguments for a callback */
  40 #define CB_ARG_CNT     4
  41
  42 /* Payload size (consists of callback API ID + arguments) */
  43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  44
  45 #define ZYNQMP_PM_MAX_QOS               100U
  46
  47 #define GSS_NUM_REGS    (4)
  48
  49 /* Node capabilities */
  50 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  51 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  52 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  53 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  54
  55 /* Loader commands */
  56 #define PM_LOAD_PDI     0x701
  57 #define PDI_SRC_DDR     0xF
  58
  59 /*
  60  * Firmware FPGA Manager flags
  61  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  62  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  63  */
  64 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  65 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  66
  67 enum pm_api_id {
  68         PM_GET_API_VERSION = 1,
  69         PM_SYSTEM_SHUTDOWN = 12,
  70         PM_REQUEST_NODE = 13,
  71         PM_RELEASE_NODE = 14,
  72         PM_SET_REQUIREMENT = 15,
  73         PM_RESET_ASSERT = 17,
  74         PM_RESET_GET_STATUS = 18,
  75         PM_MMIO_WRITE = 19,
  76         PM_MMIO_READ = 20,
  77         PM_PM_INIT_FINALIZE = 21,
  78         PM_FPGA_LOAD = 22,
  79         PM_FPGA_GET_STATUS = 23,
  80         PM_GET_CHIPID = 24,
  81         PM_PINCTRL_REQUEST = 28,
  82         PM_PINCTRL_RELEASE = 29,
  83         PM_PINCTRL_GET_FUNCTION = 30,
  84         PM_PINCTRL_SET_FUNCTION = 31,
  85         PM_PINCTRL_CONFIG_PARAM_GET = 32,
  86         PM_PINCTRL_CONFIG_PARAM_SET = 33,
  87         PM_IOCTL = 34,
  88         PM_QUERY_DATA = 35,
  89         PM_CLOCK_ENABLE = 36,
  90         PM_CLOCK_DISABLE = 37,
  91         PM_CLOCK_GETSTATE = 38,
  92         PM_CLOCK_SETDIVIDER = 39,
  93         PM_CLOCK_GETDIVIDER = 40,
  94         PM_CLOCK_SETRATE = 41,
  95         PM_CLOCK_GETRATE = 42,
  96         PM_CLOCK_SETPARENT = 43,
  97         PM_CLOCK_GETPARENT = 44,
  98         PM_SECURE_AES = 47,
  99         PM_FEATURE_CHECK = 63,
 100 };
 101
 102 /* PMU-FW return status codes */
 103 enum pm_ret_status {
 104         XST_PM_SUCCESS = 0,
 105         XST_PM_NO_FEATURE = 19,
 106         XST_PM_INTERNAL = 2000,
 107         XST_PM_CONFLICT = 2001,
 108         XST_PM_NO_ACCESS = 2002,
 109         XST_PM_INVALID_NODE = 2003,
 110         XST_PM_DOUBLE_REQ = 2004,
 111         XST_PM_ABORT_SUSPEND = 2005,
 112         XST_PM_MULT_USER = 2008,
 113 };
 114
 115 enum pm_ioctl_id {
 116         IOCTL_SD_DLL_RESET = 6,
 117         IOCTL_SET_SD_TAPDELAY = 7,
 118         IOCTL_SET_PLL_FRAC_MODE = 8,
 119         IOCTL_GET_PLL_FRAC_MODE = 9,
 120         IOCTL_SET_PLL_FRAC_DATA = 10,
 121         IOCTL_GET_PLL_FRAC_DATA = 11,
 122         IOCTL_WRITE_GGS = 12,
 123         IOCTL_READ_GGS = 13,
 124         IOCTL_WRITE_PGGS = 14,
 125         IOCTL_READ_PGGS = 15,
 126         /* Set healthy bit value */
 127         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 128         IOCTL_OSPI_MUX_SELECT = 21,
 129 };
 130
 131 enum pm_query_id {
 132         PM_QID_INVALID = 0,
 133         PM_QID_CLOCK_GET_NAME = 1,
 134         PM_QID_CLOCK_GET_TOPOLOGY = 2,
 135         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
 136         PM_QID_CLOCK_GET_PARENTS = 4,
 137         PM_QID_CLOCK_GET_ATTRIBUTES = 5,
 138         PM_QID_PINCTRL_GET_NUM_PINS = 6,
 139         PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
 140         PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
 141         PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
 142         PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
 143         PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
 144         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 145         PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 146 };
 147
 148 enum zynqmp_pm_reset_action {
 149         PM_RESET_ACTION_RELEASE = 0,
 150         PM_RESET_ACTION_ASSERT = 1,
 151         PM_RESET_ACTION_PULSE = 2,
 152 };
 153
 154 enum zynqmp_pm_reset {
 155         ZYNQMP_PM_RESET_START = 1000,
 156         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 157         ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
 158         ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
 159         ZYNQMP_PM_RESET_DP = 1003,
 160         ZYNQMP_PM_RESET_SWDT_CRF = 1004,
 161         ZYNQMP_PM_RESET_AFI_FM5 = 1005,
 162         ZYNQMP_PM_RESET_AFI_FM4 = 1006,
 163         ZYNQMP_PM_RESET_AFI_FM3 = 1007,
 164         ZYNQMP_PM_RESET_AFI_FM2 = 1008,
 165         ZYNQMP_PM_RESET_AFI_FM1 = 1009,
 166         ZYNQMP_PM_RESET_AFI_FM0 = 1010,
 167         ZYNQMP_PM_RESET_GDMA = 1011,
 168         ZYNQMP_PM_RESET_GPU_PP1 = 1012,
 169         ZYNQMP_PM_RESET_GPU_PP0 = 1013,
 170         ZYNQMP_PM_RESET_GPU = 1014,
 171         ZYNQMP_PM_RESET_GT = 1015,
 172         ZYNQMP_PM_RESET_SATA = 1016,
 173         ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
 174         ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
 175         ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
 176         ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
 177         ZYNQMP_PM_RESET_APU_L2 = 1021,
 178         ZYNQMP_PM_RESET_ACPU3 = 1022,
 179         ZYNQMP_PM_RESET_ACPU2 = 1023,
 180         ZYNQMP_PM_RESET_ACPU1 = 1024,
 181         ZYNQMP_PM_RESET_ACPU0 = 1025,
 182         ZYNQMP_PM_RESET_DDR = 1026,
 183         ZYNQMP_PM_RESET_APM_FPD = 1027,
 184         ZYNQMP_PM_RESET_SOFT = 1028,
 185         ZYNQMP_PM_RESET_GEM0 = 1029,
 186         ZYNQMP_PM_RESET_GEM1 = 1030,
 187         ZYNQMP_PM_RESET_GEM2 = 1031,
 188         ZYNQMP_PM_RESET_GEM3 = 1032,
 189         ZYNQMP_PM_RESET_QSPI = 1033,
 190         ZYNQMP_PM_RESET_UART0 = 1034,
 191         ZYNQMP_PM_RESET_UART1 = 1035,
 192         ZYNQMP_PM_RESET_SPI0 = 1036,
 193         ZYNQMP_PM_RESET_SPI1 = 1037,
 194         ZYNQMP_PM_RESET_SDIO0 = 1038,
 195         ZYNQMP_PM_RESET_SDIO1 = 1039,
 196         ZYNQMP_PM_RESET_CAN0 = 1040,
 197         ZYNQMP_PM_RESET_CAN1 = 1041,
 198         ZYNQMP_PM_RESET_I2C0 = 1042,
 199         ZYNQMP_PM_RESET_I2C1 = 1043,
 200         ZYNQMP_PM_RESET_TTC0 = 1044,
 201         ZYNQMP_PM_RESET_TTC1 = 1045,
 202         ZYNQMP_PM_RESET_TTC2 = 1046,
 203         ZYNQMP_PM_RESET_TTC3 = 1047,
 204         ZYNQMP_PM_RESET_SWDT_CRL = 1048,
 205         ZYNQMP_PM_RESET_NAND = 1049,
 206         ZYNQMP_PM_RESET_ADMA = 1050,
 207         ZYNQMP_PM_RESET_GPIO = 1051,
 208         ZYNQMP_PM_RESET_IOU_CC = 1052,
 209         ZYNQMP_PM_RESET_TIMESTAMP = 1053,
 210         ZYNQMP_PM_RESET_RPU_R50 = 1054,
 211         ZYNQMP_PM_RESET_RPU_R51 = 1055,
 212         ZYNQMP_PM_RESET_RPU_AMBA = 1056,
 213         ZYNQMP_PM_RESET_OCM = 1057,
 214         ZYNQMP_PM_RESET_RPU_PGE = 1058,
 215         ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
 216         ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
 217         ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
 218         ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
 219         ZYNQMP_PM_RESET_USB0_APB = 1063,
 220         ZYNQMP_PM_RESET_USB1_APB = 1064,
 221         ZYNQMP_PM_RESET_IPI = 1065,
 222         ZYNQMP_PM_RESET_APM_LPD = 1066,
 223         ZYNQMP_PM_RESET_RTC = 1067,
 224         ZYNQMP_PM_RESET_SYSMON = 1068,
 225         ZYNQMP_PM_RESET_AFI_FM6 = 1069,
 226         ZYNQMP_PM_RESET_LPD_SWDT = 1070,
 227         ZYNQMP_PM_RESET_FPD = 1071,
 228         ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
 229         ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
 230         ZYNQMP_PM_RESET_DBG_LPD = 1074,
 231         ZYNQMP_PM_RESET_DBG_FPD = 1075,
 232         ZYNQMP_PM_RESET_APLL = 1076,
 233         ZYNQMP_PM_RESET_DPLL = 1077,
 234         ZYNQMP_PM_RESET_VPLL = 1078,
 235         ZYNQMP_PM_RESET_IOPLL = 1079,
 236         ZYNQMP_PM_RESET_RPLL = 1080,
 237         ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
 238         ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
 239         ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
 240         ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
 241         ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
 242         ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
 243         ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
 244         ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
 245         ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
 246         ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
 247         ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
 248         ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
 249         ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
 250         ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
 251         ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
 252         ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
 253         ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
 254         ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
 255         ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
 256         ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
 257         ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
 258         ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
 259         ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
 260         ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
 261         ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
 262         ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
 263         ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
 264         ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
 265         ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
 266         ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
 267         ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
 268         ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
 269         ZYNQMP_PM_RESET_RPU_LS = 1113,
 270         ZYNQMP_PM_RESET_PS_ONLY = 1114,
 271         ZYNQMP_PM_RESET_PL = 1115,
 272         ZYNQMP_PM_RESET_PS_PL0 = 1116,
 273         ZYNQMP_PM_RESET_PS_PL1 = 1117,
 274         ZYNQMP_PM_RESET_PS_PL2 = 1118,
 275         ZYNQMP_PM_RESET_PS_PL3 = 1119,
 276         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 277 };
 278
 279 enum zynqmp_pm_suspend_reason {
 280         SUSPEND_POWER_REQUEST = 201,
 281         SUSPEND_ALERT = 202,
 282         SUSPEND_SYSTEM_SHUTDOWN = 203,
 283 };
 284
 285 enum zynqmp_pm_request_ack {
 286         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 287         ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
 288         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
 289 };
 290
 291 enum pm_node_id {
 292         NODE_SD_0 = 39,
 293         NODE_SD_1 = 40,
 294 };
 295
 296 enum tap_delay_type {
 297         PM_TAPDELAY_INPUT = 0,
 298         PM_TAPDELAY_OUTPUT = 1,
 299 };
 300
 301 enum dll_reset_type {
 302         PM_DLL_RESET_ASSERT = 0,
 303         PM_DLL_RESET_RELEASE = 1,
 304         PM_DLL_RESET_PULSE = 2,
 305 };
 306
 307 enum pm_pinctrl_config_param {
 308         PM_PINCTRL_CONFIG_SLEW_RATE = 0,
 309         PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
 310         PM_PINCTRL_CONFIG_PULL_CTRL = 2,
 311         PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
 312         PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
 313         PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
 314         PM_PINCTRL_CONFIG_TRI_STATE = 6,
 315         PM_PINCTRL_CONFIG_MAX = 7,
 316 };
 317
 318 enum pm_pinctrl_slew_rate {
 319         PM_PINCTRL_SLEW_RATE_FAST = 0,
 320         PM_PINCTRL_SLEW_RATE_SLOW = 1,
 321 };
 322
 323 enum pm_pinctrl_bias_status {
 324         PM_PINCTRL_BIAS_DISABLE = 0,
 325         PM_PINCTRL_BIAS_ENABLE = 1,
 326 };
 327
 328 enum pm_pinctrl_pull_ctrl {
 329         PM_PINCTRL_BIAS_PULL_DOWN = 0,
 330         PM_PINCTRL_BIAS_PULL_UP = 1,
 331 };
 332
 333 enum pm_pinctrl_schmitt_cmos {
 334         PM_PINCTRL_INPUT_TYPE_CMOS = 0,
 335         PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
 336 };
 337
 338 enum pm_pinctrl_drive_strength {
 339         PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
 340         PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
 341         PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
 342         PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
 343 };
 344
 345 enum zynqmp_pm_shutdown_type {
 346         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
 347         ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
 348         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
 349 };
 350
 351 enum zynqmp_pm_shutdown_subtype {
 352         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
 353         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
 354         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
 355 };
 356
 357 enum ospi_mux_select_type {
 358         PM_OSPI_MUX_SEL_DMA = 0,
 359         PM_OSPI_MUX_SEL_LINEAR = 1,
 360 };
 361
 362 /**
 363  * struct zynqmp_pm_query_data - PM query data
 364  * @qid:        query ID
 365  * @arg1:       Argument 1 of query data
 366  * @arg2:       Argument 2 of query data
 367  * @arg3:       Argument 3 of query data
 368  */
 369 struct zynqmp_pm_query_data {
 370         u32 qid;
 371         u32 arg1;
 372         u32 arg2;
 373         u32 arg3;
 374 };
 375
 376 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 377                         u32 arg2, u32 arg3, u32 *ret_payload);
 378
 379 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 380 int zynqmp_pm_get_api_version(u32 *version);
 381 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 382 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 383 int zynqmp_pm_clock_enable(u32 clock_id);
 384 int zynqmp_pm_clock_disable(u32 clock_id);
 385 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 386 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 387 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 388 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 389 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 390 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 391 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 392 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 393 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 394 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 395 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 396 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 397 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 398 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
 399 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 400                            const enum zynqmp_pm_reset_action assert_flag);
 401 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 402 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
 403 int zynqmp_pm_bootmode_write(u32 ps_mode);
 404 int zynqmp_pm_init_finalize(void);
 405 int zynqmp_pm_set_suspend_mode(u32 mode);
 406 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 407                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 408 int zynqmp_pm_release_node(const u32 node);
 409 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 410                               const u32 qos,
 411                               const enum zynqmp_pm_request_ack ack);
 412 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 413 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 414 int zynqmp_pm_fpga_get_status(u32 *value);
 415 int zynqmp_pm_write_ggs(u32 index, u32 value);
 416 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 417 int zynqmp_pm_write_pggs(u32 index, u32 value);
 418 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 419 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 420 int zynqmp_pm_set_boot_health_status(u32 value);
 421 int zynqmp_pm_pinctrl_request(const u32 pin);
 422 int zynqmp_pm_pinctrl_release(const u32 pin);
 423 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
 424 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
 425 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 426                                  u32 *value);
 427 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 428                                  u32 value);
 429 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
 430 #else
 431 static inline int zynqmp_pm_get_api_version(u32 *version)
 432 {
 433         return -ENODEV;
 434 }
 435
 436 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 437 {
 438         return -ENODEV;
 439 }
 440
 441 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 442                                        u32 *out)
 443 {
 444         return -ENODEV;
 445 }
 446
 447 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 448 {
 449         return -ENODEV;
 450 }
 451
 452 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 453 {
 454         return -ENODEV;
 455 }
 456
 457 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 458 {
 459         return -ENODEV;
 460 }
 461
 462 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 463 {
 464         return -ENODEV;
 465 }
 466
 467 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 468 {
 469         return -ENODEV;
 470 }
 471
 472 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 473 {
 474         return -ENODEV;
 475 }
 476
 477 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 478 {
 479         return -ENODEV;
 480 }
 481
 482 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 483 {
 484         return -ENODEV;
 485 }
 486
 487 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 488 {
 489         return -ENODEV;
 490 }
 491
 492 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 493 {
 494         return -ENODEV;
 495 }
 496
 497 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 498 {
 499         return -ENODEV;
 500 }
 501
 502 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 503 {
 504         return -ENODEV;
 505 }
 506
 507 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 508 {
 509         return -ENODEV;
 510 }
 511
 512 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 513 {
 514         return -ENODEV;
 515 }
 516
 517 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 518 {
 519         return -ENODEV;
 520 }
 521
 522 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
 523 {
 524         return -ENODEV;
 525 }
 526
 527 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 528                                          const enum zynqmp_pm_reset_action assert_flag)
 529 {
 530         return -ENODEV;
 531 }
 532
 533 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 534                                              u32 *status)
 535 {
 536         return -ENODEV;
 537 }
 538
 539 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
 540 {
 541         return -ENODEV;
 542 }
 543
 544 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
 545 {
 546         return -ENODEV;
 547 }
 548
 549 static inline int zynqmp_pm_init_finalize(void)
 550 {
 551         return -ENODEV;
 552 }
 553
 554 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 555 {
 556         return -ENODEV;
 557 }
 558
 559 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 560                                          const u32 qos,
 561                                          const enum zynqmp_pm_request_ack ack)
 562 {
 563         return -ENODEV;
 564 }
 565
 566 static inline int zynqmp_pm_release_node(const u32 node)
 567 {
 568         return -ENODEV;
 569 }
 570
 571 static inline int zynqmp_pm_set_requirement(const u32 node,
 572                                             const u32 capabilities,
 573                                             const u32 qos,
 574                                             const enum zynqmp_pm_request_ack ack)
 575 {
 576         return -ENODEV;
 577 }
 578
 579 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 580 {
 581         return -ENODEV;
 582 }
 583
 584 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 585                                       const u32 flags)
 586 {
 587         return -ENODEV;
 588 }
 589
 590 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 591 {
 592         return -ENODEV;
 593 }
 594
 595 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 596 {
 597         return -ENODEV;
 598 }
 599
 600 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 601 {
 602         return -ENODEV;
 603 }
 604
 605 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 606 {
 607         return -ENODEV;
 608 }
 609
 610 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 611 {
 612         return -ENODEV;
 613 }
 614
 615 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 616 {
 617         return -ENODEV;
 618 }
 619
 620 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 621 {
 622         return -ENODEV;
 623 }
 624
 625 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
 626 {
 627         return -ENODEV;
 628 }
 629
 630 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
 631 {
 632         return -ENODEV;
 633 }
 634
 635 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
 636 {
 637         return -ENODEV;
 638 }
 639
 640 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
 641 {
 642         return -ENODEV;
 643 }
 644
 645 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
 646                                                u32 *value)
 647 {
 648         return -ENODEV;
 649 }
 650
 651 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
 652                                                u32 value)
 653 {
 654         return -ENODEV;
 655 }
 656
 657 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
 658 {
 659         return -ENODEV;
 660 }
 661 #endif
 662
 663 #endif /* __FIRMWARE_ZYNQMP_H__ */