include/linux/firmware/xlnx-zynqmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Xilinx Zynq MPSoC Firmware layer
   4  *
   5  *  Copyright (C) 2014-2019 Xilinx
   6  *
   7  *  Michal Simek <michal.simek@xilinx.com>
   8  *  Davorin Mista <davorin.mista@aggios.com>
   9  *  Jolly Shah <jollys@xilinx.com>
  10  *  Rajan Vaja <rajanv@xilinx.com>
  11  */
  12
  13 #ifndef __FIRMWARE_ZYNQMP_H__
  14 #define __FIRMWARE_ZYNQMP_H__
  15
  16 #include <linux/err.h>
  17
  18 #define ZYNQMP_PM_VERSION_MAJOR 1
  19 #define ZYNQMP_PM_VERSION_MINOR 0
  20
  21 #define ZYNQMP_PM_VERSION       ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
  22                                         ZYNQMP_PM_VERSION_MINOR)
  23
  24 #define ZYNQMP_TZ_VERSION_MAJOR 1
  25 #define ZYNQMP_TZ_VERSION_MINOR 0
  26
  27 #define ZYNQMP_TZ_VERSION       ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
  28                                         ZYNQMP_TZ_VERSION_MINOR)
  29
  30 /* SMC SIP service Call Function Identifier Prefix */
  31 #define PM_SIP_SVC                      0xC2000000
  32 #define PM_GET_TRUSTZONE_VERSION        0xa03
  33 #define PM_SET_SUSPEND_MODE             0xa02
  34 #define GET_CALLBACK_DATA               0xa01
  35
  36 /* Number of 32bits values in payload */
  37 #define PAYLOAD_ARG_CNT 4U
  38
  39 /* Number of arguments for a callback */
  40 #define CB_ARG_CNT     4
  41
  42 /* Payload size (consists of callback API ID + arguments) */
  43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
  44
  45 #define ZYNQMP_PM_MAX_QOS               100U
  46
  47 #define GSS_NUM_REGS    (4)
  48
  49 /* Node capabilities */
  50 #define ZYNQMP_PM_CAPABILITY_ACCESS     0x1U
  51 #define ZYNQMP_PM_CAPABILITY_CONTEXT    0x2U
  52 #define ZYNQMP_PM_CAPABILITY_WAKEUP     0x4U
  53 #define ZYNQMP_PM_CAPABILITY_UNUSABLE   0x8U
  54
  55 /* Feature check status */
  56 #define PM_FEATURE_INVALID              -1
  57 #define PM_FEATURE_UNCHECKED            0
  58
  59 /*
  60  * Firmware FPGA Manager flags
  61  * XILINX_ZYNQMP_PM_FPGA_FULL:  FPGA full reconfiguration
  62  * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
  63  */
  64 #define XILINX_ZYNQMP_PM_FPGA_FULL      0x0U
  65 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL   BIT(0)
  66
  67 enum pm_api_id {
  68         PM_GET_API_VERSION = 1,
  69         PM_SYSTEM_SHUTDOWN = 12,
  70         PM_REQUEST_NODE = 13,
  71         PM_RELEASE_NODE,
  72         PM_SET_REQUIREMENT,
  73         PM_RESET_ASSERT = 17,
  74         PM_RESET_GET_STATUS,
  75         PM_PM_INIT_FINALIZE = 21,
  76         PM_FPGA_LOAD,
  77         PM_FPGA_GET_STATUS,
  78         PM_GET_CHIPID = 24,
  79         PM_IOCTL = 34,
  80         PM_QUERY_DATA,
  81         PM_CLOCK_ENABLE,
  82         PM_CLOCK_DISABLE,
  83         PM_CLOCK_GETSTATE,
  84         PM_CLOCK_SETDIVIDER,
  85         PM_CLOCK_GETDIVIDER,
  86         PM_CLOCK_SETRATE,
  87         PM_CLOCK_GETRATE,
  88         PM_CLOCK_SETPARENT,
  89         PM_CLOCK_GETPARENT,
  90         PM_SECURE_AES = 47,
  91         PM_FEATURE_CHECK = 63,
  92         PM_API_MAX,
  93 };
  94
  95 /* PMU-FW return status codes */
  96 enum pm_ret_status {
  97         XST_PM_SUCCESS = 0,
  98         XST_PM_NO_FEATURE = 19,
  99         XST_PM_INTERNAL = 2000,
 100         XST_PM_CONFLICT,
 101         XST_PM_NO_ACCESS,
 102         XST_PM_INVALID_NODE,
 103         XST_PM_DOUBLE_REQ,
 104         XST_PM_ABORT_SUSPEND,
 105         XST_PM_MULT_USER = 2008,
 106 };
 107
 108 enum pm_ioctl_id {
 109         IOCTL_SD_DLL_RESET = 6,
 110         IOCTL_SET_SD_TAPDELAY,
 111         IOCTL_SET_PLL_FRAC_MODE,
 112         IOCTL_GET_PLL_FRAC_MODE,
 113         IOCTL_SET_PLL_FRAC_DATA,
 114         IOCTL_GET_PLL_FRAC_DATA,
 115         IOCTL_WRITE_GGS = 12,
 116         IOCTL_READ_GGS = 13,
 117         IOCTL_WRITE_PGGS = 14,
 118         IOCTL_READ_PGGS = 15,
 119         /* Set healthy bit value */
 120         IOCTL_SET_BOOT_HEALTH_STATUS = 17,
 121 };
 122
 123 enum pm_query_id {
 124         PM_QID_INVALID,
 125         PM_QID_CLOCK_GET_NAME,
 126         PM_QID_CLOCK_GET_TOPOLOGY,
 127         PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
 128         PM_QID_CLOCK_GET_PARENTS,
 129         PM_QID_CLOCK_GET_ATTRIBUTES,
 130         PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
 131         PM_QID_CLOCK_GET_MAX_DIVISOR,
 132 };
 133
 134 enum zynqmp_pm_reset_action {
 135         PM_RESET_ACTION_RELEASE,
 136         PM_RESET_ACTION_ASSERT,
 137         PM_RESET_ACTION_PULSE,
 138 };
 139
 140 enum zynqmp_pm_reset {
 141         ZYNQMP_PM_RESET_START = 1000,
 142         ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
 143         ZYNQMP_PM_RESET_PCIE_BRIDGE,
 144         ZYNQMP_PM_RESET_PCIE_CTRL,
 145         ZYNQMP_PM_RESET_DP,
 146         ZYNQMP_PM_RESET_SWDT_CRF,
 147         ZYNQMP_PM_RESET_AFI_FM5,
 148         ZYNQMP_PM_RESET_AFI_FM4,
 149         ZYNQMP_PM_RESET_AFI_FM3,
 150         ZYNQMP_PM_RESET_AFI_FM2,
 151         ZYNQMP_PM_RESET_AFI_FM1,
 152         ZYNQMP_PM_RESET_AFI_FM0,
 153         ZYNQMP_PM_RESET_GDMA,
 154         ZYNQMP_PM_RESET_GPU_PP1,
 155         ZYNQMP_PM_RESET_GPU_PP0,
 156         ZYNQMP_PM_RESET_GPU,
 157         ZYNQMP_PM_RESET_GT,
 158         ZYNQMP_PM_RESET_SATA,
 159         ZYNQMP_PM_RESET_ACPU3_PWRON,
 160         ZYNQMP_PM_RESET_ACPU2_PWRON,
 161         ZYNQMP_PM_RESET_ACPU1_PWRON,
 162         ZYNQMP_PM_RESET_ACPU0_PWRON,
 163         ZYNQMP_PM_RESET_APU_L2,
 164         ZYNQMP_PM_RESET_ACPU3,
 165         ZYNQMP_PM_RESET_ACPU2,
 166         ZYNQMP_PM_RESET_ACPU1,
 167         ZYNQMP_PM_RESET_ACPU0,
 168         ZYNQMP_PM_RESET_DDR,
 169         ZYNQMP_PM_RESET_APM_FPD,
 170         ZYNQMP_PM_RESET_SOFT,
 171         ZYNQMP_PM_RESET_GEM0,
 172         ZYNQMP_PM_RESET_GEM1,
 173         ZYNQMP_PM_RESET_GEM2,
 174         ZYNQMP_PM_RESET_GEM3,
 175         ZYNQMP_PM_RESET_QSPI,
 176         ZYNQMP_PM_RESET_UART0,
 177         ZYNQMP_PM_RESET_UART1,
 178         ZYNQMP_PM_RESET_SPI0,
 179         ZYNQMP_PM_RESET_SPI1,
 180         ZYNQMP_PM_RESET_SDIO0,
 181         ZYNQMP_PM_RESET_SDIO1,
 182         ZYNQMP_PM_RESET_CAN0,
 183         ZYNQMP_PM_RESET_CAN1,
 184         ZYNQMP_PM_RESET_I2C0,
 185         ZYNQMP_PM_RESET_I2C1,
 186         ZYNQMP_PM_RESET_TTC0,
 187         ZYNQMP_PM_RESET_TTC1,
 188         ZYNQMP_PM_RESET_TTC2,
 189         ZYNQMP_PM_RESET_TTC3,
 190         ZYNQMP_PM_RESET_SWDT_CRL,
 191         ZYNQMP_PM_RESET_NAND,
 192         ZYNQMP_PM_RESET_ADMA,
 193         ZYNQMP_PM_RESET_GPIO,
 194         ZYNQMP_PM_RESET_IOU_CC,
 195         ZYNQMP_PM_RESET_TIMESTAMP,
 196         ZYNQMP_PM_RESET_RPU_R50,
 197         ZYNQMP_PM_RESET_RPU_R51,
 198         ZYNQMP_PM_RESET_RPU_AMBA,
 199         ZYNQMP_PM_RESET_OCM,
 200         ZYNQMP_PM_RESET_RPU_PGE,
 201         ZYNQMP_PM_RESET_USB0_CORERESET,
 202         ZYNQMP_PM_RESET_USB1_CORERESET,
 203         ZYNQMP_PM_RESET_USB0_HIBERRESET,
 204         ZYNQMP_PM_RESET_USB1_HIBERRESET,
 205         ZYNQMP_PM_RESET_USB0_APB,
 206         ZYNQMP_PM_RESET_USB1_APB,
 207         ZYNQMP_PM_RESET_IPI,
 208         ZYNQMP_PM_RESET_APM_LPD,
 209         ZYNQMP_PM_RESET_RTC,
 210         ZYNQMP_PM_RESET_SYSMON,
 211         ZYNQMP_PM_RESET_AFI_FM6,
 212         ZYNQMP_PM_RESET_LPD_SWDT,
 213         ZYNQMP_PM_RESET_FPD,
 214         ZYNQMP_PM_RESET_RPU_DBG1,
 215         ZYNQMP_PM_RESET_RPU_DBG0,
 216         ZYNQMP_PM_RESET_DBG_LPD,
 217         ZYNQMP_PM_RESET_DBG_FPD,
 218         ZYNQMP_PM_RESET_APLL,
 219         ZYNQMP_PM_RESET_DPLL,
 220         ZYNQMP_PM_RESET_VPLL,
 221         ZYNQMP_PM_RESET_IOPLL,
 222         ZYNQMP_PM_RESET_RPLL,
 223         ZYNQMP_PM_RESET_GPO3_PL_0,
 224         ZYNQMP_PM_RESET_GPO3_PL_1,
 225         ZYNQMP_PM_RESET_GPO3_PL_2,
 226         ZYNQMP_PM_RESET_GPO3_PL_3,
 227         ZYNQMP_PM_RESET_GPO3_PL_4,
 228         ZYNQMP_PM_RESET_GPO3_PL_5,
 229         ZYNQMP_PM_RESET_GPO3_PL_6,
 230         ZYNQMP_PM_RESET_GPO3_PL_7,
 231         ZYNQMP_PM_RESET_GPO3_PL_8,
 232         ZYNQMP_PM_RESET_GPO3_PL_9,
 233         ZYNQMP_PM_RESET_GPO3_PL_10,
 234         ZYNQMP_PM_RESET_GPO3_PL_11,
 235         ZYNQMP_PM_RESET_GPO3_PL_12,
 236         ZYNQMP_PM_RESET_GPO3_PL_13,
 237         ZYNQMP_PM_RESET_GPO3_PL_14,
 238         ZYNQMP_PM_RESET_GPO3_PL_15,
 239         ZYNQMP_PM_RESET_GPO3_PL_16,
 240         ZYNQMP_PM_RESET_GPO3_PL_17,
 241         ZYNQMP_PM_RESET_GPO3_PL_18,
 242         ZYNQMP_PM_RESET_GPO3_PL_19,
 243         ZYNQMP_PM_RESET_GPO3_PL_20,
 244         ZYNQMP_PM_RESET_GPO3_PL_21,
 245         ZYNQMP_PM_RESET_GPO3_PL_22,
 246         ZYNQMP_PM_RESET_GPO3_PL_23,
 247         ZYNQMP_PM_RESET_GPO3_PL_24,
 248         ZYNQMP_PM_RESET_GPO3_PL_25,
 249         ZYNQMP_PM_RESET_GPO3_PL_26,
 250         ZYNQMP_PM_RESET_GPO3_PL_27,
 251         ZYNQMP_PM_RESET_GPO3_PL_28,
 252         ZYNQMP_PM_RESET_GPO3_PL_29,
 253         ZYNQMP_PM_RESET_GPO3_PL_30,
 254         ZYNQMP_PM_RESET_GPO3_PL_31,
 255         ZYNQMP_PM_RESET_RPU_LS,
 256         ZYNQMP_PM_RESET_PS_ONLY,
 257         ZYNQMP_PM_RESET_PL,
 258         ZYNQMP_PM_RESET_PS_PL0,
 259         ZYNQMP_PM_RESET_PS_PL1,
 260         ZYNQMP_PM_RESET_PS_PL2,
 261         ZYNQMP_PM_RESET_PS_PL3,
 262         ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
 263 };
 264
 265 enum zynqmp_pm_suspend_reason {
 266         SUSPEND_POWER_REQUEST = 201,
 267         SUSPEND_ALERT,
 268         SUSPEND_SYSTEM_SHUTDOWN,
 269 };
 270
 271 enum zynqmp_pm_request_ack {
 272         ZYNQMP_PM_REQUEST_ACK_NO = 1,
 273         ZYNQMP_PM_REQUEST_ACK_BLOCKING,
 274         ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
 275 };
 276
 277 enum pm_node_id {
 278         NODE_SD_0 = 39,
 279         NODE_SD_1,
 280 };
 281
 282 enum tap_delay_type {
 283         PM_TAPDELAY_INPUT = 0,
 284         PM_TAPDELAY_OUTPUT,
 285 };
 286
 287 enum dll_reset_type {
 288         PM_DLL_RESET_ASSERT,
 289         PM_DLL_RESET_RELEASE,
 290         PM_DLL_RESET_PULSE,
 291 };
 292
 293 enum zynqmp_pm_shutdown_type {
 294         ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
 295         ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
 296         ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
 297 };
 298
 299 enum zynqmp_pm_shutdown_subtype {
 300         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
 301         ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
 302         ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
 303 };
 304
 305 /**
 306  * struct zynqmp_pm_query_data - PM query data
 307  * @qid:        query ID
 308  * @arg1:       Argument 1 of query data
 309  * @arg2:       Argument 2 of query data
 310  * @arg3:       Argument 3 of query data
 311  */
 312 struct zynqmp_pm_query_data {
 313         u32 qid;
 314         u32 arg1;
 315         u32 arg2;
 316         u32 arg3;
 317 };
 318
 319 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
 320                         u32 arg2, u32 arg3, u32 *ret_payload);
 321
 322 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
 323 int zynqmp_pm_get_api_version(u32 *version);
 324 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
 325 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
 326 int zynqmp_pm_clock_enable(u32 clock_id);
 327 int zynqmp_pm_clock_disable(u32 clock_id);
 328 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
 329 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
 330 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
 331 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
 332 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
 333 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
 334 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
 335 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
 336 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
 337 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
 338 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
 339 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
 340 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
 341 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 342                            const enum zynqmp_pm_reset_action assert_flag);
 343 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
 344 int zynqmp_pm_init_finalize(void);
 345 int zynqmp_pm_set_suspend_mode(u32 mode);
 346 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 347                            const u32 qos, const enum zynqmp_pm_request_ack ack);
 348 int zynqmp_pm_release_node(const u32 node);
 349 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
 350                               const u32 qos,
 351                               const enum zynqmp_pm_request_ack ack);
 352 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
 353 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
 354 int zynqmp_pm_fpga_get_status(u32 *value);
 355 int zynqmp_pm_write_ggs(u32 index, u32 value);
 356 int zynqmp_pm_read_ggs(u32 index, u32 *value);
 357 int zynqmp_pm_write_pggs(u32 index, u32 value);
 358 int zynqmp_pm_read_pggs(u32 index, u32 *value);
 359 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
 360 int zynqmp_pm_set_boot_health_status(u32 value);
 361 #else
 362 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
 363 {
 364         return ERR_PTR(-ENODEV);
 365 }
 366 static inline int zynqmp_pm_get_api_version(u32 *version)
 367 {
 368         return -ENODEV;
 369 }
 370 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
 371 {
 372         return -ENODEV;
 373 }
 374 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
 375                                        u32 *out)
 376 {
 377         return -ENODEV;
 378 }
 379 static inline int zynqmp_pm_clock_enable(u32 clock_id)
 380 {
 381         return -ENODEV;
 382 }
 383 static inline int zynqmp_pm_clock_disable(u32 clock_id)
 384 {
 385         return -ENODEV;
 386 }
 387 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
 388 {
 389         return -ENODEV;
 390 }
 391 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
 392 {
 393         return -ENODEV;
 394 }
 395 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
 396 {
 397         return -ENODEV;
 398 }
 399 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
 400 {
 401         return -ENODEV;
 402 }
 403 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
 404 {
 405         return -ENODEV;
 406 }
 407 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
 408 {
 409         return -ENODEV;
 410 }
 411 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
 412 {
 413         return -ENODEV;
 414 }
 415 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
 416 {
 417         return -ENODEV;
 418 }
 419 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
 420 {
 421         return -ENODEV;
 422 }
 423 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
 424 {
 425         return -ENODEV;
 426 }
 427 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
 428 {
 429         return -ENODEV;
 430 }
 431 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
 432 {
 433         return -ENODEV;
 434 }
 435 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
 436 {
 437         return -ENODEV;
 438 }
 439 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
 440                            const enum zynqmp_pm_reset_action assert_flag)
 441 {
 442         return -ENODEV;
 443 }
 444 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
 445                                              u32 *status)
 446 {
 447         return -ENODEV;
 448 }
 449 static inline int zynqmp_pm_init_finalize(void)
 450 {
 451         return -ENODEV;
 452 }
 453 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
 454 {
 455         return -ENODEV;
 456 }
 457 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
 458                                          const u32 qos,
 459                                          const enum zynqmp_pm_request_ack ack)
 460 {
 461         return -ENODEV;
 462 }
 463 static inline int zynqmp_pm_release_node(const u32 node)
 464 {
 465         return -ENODEV;
 466 }
 467 static inline int zynqmp_pm_set_requirement(const u32 node,
 468                                         const u32 capabilities,
 469                                         const u32 qos,
 470                                         const enum zynqmp_pm_request_ack ack)
 471 {
 472         return -ENODEV;
 473 }
 474 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
 475 {
 476         return -ENODEV;
 477 }
 478 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
 479                                       const u32 flags)
 480 {
 481         return -ENODEV;
 482 }
 483 static inline int zynqmp_pm_fpga_get_status(u32 *value)
 484 {
 485         return -ENODEV;
 486 }
 487 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
 488 {
 489         return -ENODEV;
 490 }
 491 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
 492 {
 493         return -ENODEV;
 494 }
 495 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
 496 {
 497         return -ENODEV;
 498 }
 499 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
 500 {
 501         return -ENODEV;
 502 }
 503 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
 504 {
 505         return -ENODEV;
 506 }
 507 static inline int zynqmp_pm_set_boot_health_status(u32 value)
 508 {
 509         return -ENODEV;
 510 }
 511 #endif
 512
 513 #endif /* __FIRMWARE_ZYNQMP_H__ */