1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4 * Copyright (c) 2023 Intel and affiliates
10 #include <uapi/linux/dpll.h>
11 #include <linux/device.h>
12 #include <linux/netlink.h>
13 #include <linux/netdevice.h>
14 #include <linux/rtnetlink.h>
19 struct dpll_device_ops {
20 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
21 enum dpll_mode *mode, struct netlink_ext_ack *extack);
22 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
23 enum dpll_lock_status *status,
24 struct netlink_ext_ack *extack);
25 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
26 s32 *temp, struct netlink_ext_ack *extack);
30 int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
31 const struct dpll_device *dpll, void *dpll_priv,
33 struct netlink_ext_ack *extack);
34 int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
35 const struct dpll_device *dpll, void *dpll_priv,
36 u64 *frequency, struct netlink_ext_ack *extack);
37 int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
38 const struct dpll_device *dpll, void *dpll_priv,
39 const enum dpll_pin_direction direction,
40 struct netlink_ext_ack *extack);
41 int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
42 const struct dpll_device *dpll, void *dpll_priv,
43 enum dpll_pin_direction *direction,
44 struct netlink_ext_ack *extack);
45 int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
46 const struct dpll_pin *parent_pin,
47 void *parent_pin_priv,
48 enum dpll_pin_state *state,
49 struct netlink_ext_ack *extack);
50 int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
51 const struct dpll_device *dpll,
52 void *dpll_priv, enum dpll_pin_state *state,
53 struct netlink_ext_ack *extack);
54 int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
55 const struct dpll_pin *parent_pin,
56 void *parent_pin_priv,
57 const enum dpll_pin_state state,
58 struct netlink_ext_ack *extack);
59 int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
60 const struct dpll_device *dpll,
62 const enum dpll_pin_state state,
63 struct netlink_ext_ack *extack);
64 int (*prio_get)(const struct dpll_pin *pin, void *pin_priv,
65 const struct dpll_device *dpll, void *dpll_priv,
66 u32 *prio, struct netlink_ext_ack *extack);
67 int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
68 const struct dpll_device *dpll, void *dpll_priv,
69 const u32 prio, struct netlink_ext_ack *extack);
70 int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
71 const struct dpll_device *dpll, void *dpll_priv,
73 struct netlink_ext_ack *extack);
74 int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
75 const struct dpll_device *dpll, void *dpll_priv,
77 struct netlink_ext_ack *extack);
78 int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
79 const struct dpll_device *dpll, void *dpll_priv,
80 const s32 phase_adjust,
81 struct netlink_ext_ack *extack);
82 int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
83 const struct dpll_device *dpll, void *dpll_priv,
84 s64 *ffo, struct netlink_ext_ack *extack);
87 struct dpll_pin_frequency {
92 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max) \
98 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
99 #define DPLL_PIN_FREQUENCY_1PPS \
100 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
101 #define DPLL_PIN_FREQUENCY_10MHZ \
102 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
103 #define DPLL_PIN_FREQUENCY_IRIG_B \
104 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
105 #define DPLL_PIN_FREQUENCY_DCF77 \
106 DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
108 struct dpll_pin_phase_adjust_range {
113 struct dpll_pin_properties {
114 const char *board_label;
115 const char *panel_label;
116 const char *package_label;
117 enum dpll_pin_type type;
118 unsigned long capabilities;
119 u32 freq_supported_num;
120 struct dpll_pin_frequency *freq_supported;
121 struct dpll_pin_phase_adjust_range phase_range;
124 #if IS_ENABLED(CONFIG_DPLL)
125 void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
126 void dpll_netdev_pin_clear(struct net_device *dev);
128 size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
129 int dpll_netdev_add_pin_handle(struct sk_buff *msg,
130 const struct net_device *dev);
133 dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
134 static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
136 static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
142 dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
149 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module);
151 void dpll_device_put(struct dpll_device *dpll);
153 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
154 const struct dpll_device_ops *ops, void *priv);
156 void dpll_device_unregister(struct dpll_device *dpll,
157 const struct dpll_device_ops *ops, void *priv);
160 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
161 const struct dpll_pin_properties *prop);
163 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
164 const struct dpll_pin_ops *ops, void *priv);
166 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
167 const struct dpll_pin_ops *ops, void *priv);
169 void dpll_pin_put(struct dpll_pin *pin);
171 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
172 const struct dpll_pin_ops *ops, void *priv);
174 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
175 const struct dpll_pin_ops *ops, void *priv);
177 int dpll_device_change_ntf(struct dpll_device *dpll);
179 int dpll_pin_change_ntf(struct dpll_pin *pin);