1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
5 #ifndef LINUX_DMAENGINE_H
6 #define LINUX_DMAENGINE_H
8 #include <linux/device.h>
10 #include <linux/uio.h>
11 #include <linux/bug.h>
12 #include <linux/scatterlist.h>
13 #include <linux/bitmap.h>
14 #include <linux/types.h>
18 * typedef dma_cookie_t - an opaque DMA cookie
20 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
22 typedef s32 dma_cookie_t;
23 #define DMA_MIN_COOKIE 1
25 static inline int dma_submit_error(dma_cookie_t cookie)
27 return cookie < 0 ? cookie : 0;
31 * enum dma_status - DMA transaction status
32 * @DMA_COMPLETE: transaction completed
33 * @DMA_IN_PROGRESS: transaction not yet processed
34 * @DMA_PAUSED: transaction is paused
35 * @DMA_ERROR: transaction failed
45 * enum dma_transaction_type - DMA transaction types/indexes
47 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
48 * automatically set as dma devices are registered.
50 enum dma_transaction_type {
66 /* last transaction type for creation of the capabilities mask */
71 * enum dma_transfer_direction - dma transfer mode and direction indicator
72 * @DMA_MEM_TO_MEM: Async/Memcpy mode
73 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
74 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
75 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
77 enum dma_transfer_direction {
86 * Interleaved Transfer Request
87 * ----------------------------
88 * A chunk is collection of contiguous bytes to be transferred.
89 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
90 * ICGs may or may not change between chunks.
91 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
92 * that when repeated an integral number of times, specifies the transfer.
93 * A transfer template is specification of a Frame, the number of times
94 * it is to be repeated and other per-transfer attributes.
96 * Practically, a client driver would have ready a template for each
97 * type of transfer it is going to need during its lifetime and
98 * set only 'src_start' and 'dst_start' before submitting the requests.
101 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
102 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
109 * struct data_chunk - Element of scatter-gather list that makes a frame.
110 * @size: Number of bytes to read from source.
111 * size_dst := fn(op, size_src), so doesn't mean much for destination.
112 * @icg: Number of bytes to jump after last src/dst address of this
113 * chunk and before first src/dst address for next chunk.
114 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
115 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
116 * @dst_icg: Number of bytes to jump after last dst address of this
117 * chunk and before the first dst address for next chunk.
118 * Ignored if dst_inc is true and dst_sgl is false.
119 * @src_icg: Number of bytes to jump after last src address of this
120 * chunk and before the first src address for next chunk.
121 * Ignored if src_inc is true and src_sgl is false.
131 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
133 * @src_start: Bus address of source for the first chunk.
134 * @dst_start: Bus address of destination for the first chunk.
135 * @dir: Specifies the type of Source and Destination.
136 * @src_inc: If the source address increments after reading from it.
137 * @dst_inc: If the destination address increments after writing to it.
138 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
139 * Otherwise, source is read contiguously (icg ignored).
140 * Ignored if src_inc is false.
141 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
142 * Otherwise, destination is filled contiguously (icg ignored).
143 * Ignored if dst_inc is false.
144 * @numf: Number of frames in this template.
145 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
146 * @sgl: Array of {chunk,icg} pairs that make up a frame.
148 struct dma_interleaved_template {
149 dma_addr_t src_start;
150 dma_addr_t dst_start;
151 enum dma_transfer_direction dir;
158 struct data_chunk sgl[];
162 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
163 * control completion, and communicate status.
164 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
166 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
167 * acknowledges receipt, i.e. has has a chance to establish any dependency
169 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
170 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
171 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
172 * sources that were the result of a previous operation, in the case of a PQ
173 * operation it continues the calculation with new sources
174 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
175 * on the result of this operation
176 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
178 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
179 * data and the descriptor should be in different format from normal
181 * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
182 * repeated when it ends until a transaction is issued on the same channel
183 * with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
184 * interleaved transactions and is ignored for all other transaction types.
185 * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
186 * active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
187 * repeated transaction ends. Not setting this flag when the previously queued
188 * transaction is marked with DMA_PREP_REPEAT will cause the new transaction
189 * to never be processed and stay in the issued queue forever. The flag is
190 * ignored if the previous transaction is not a repeated transaction.
192 enum dma_ctrl_flags {
193 DMA_PREP_INTERRUPT = (1 << 0),
194 DMA_CTRL_ACK = (1 << 1),
195 DMA_PREP_PQ_DISABLE_P = (1 << 2),
196 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
197 DMA_PREP_CONTINUE = (1 << 4),
198 DMA_PREP_FENCE = (1 << 5),
199 DMA_CTRL_REUSE = (1 << 6),
200 DMA_PREP_CMD = (1 << 7),
201 DMA_PREP_REPEAT = (1 << 8),
202 DMA_PREP_LOAD_EOT = (1 << 9),
206 * enum sum_check_bits - bit position of pq_check_flags
208 enum sum_check_bits {
214 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
215 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
216 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
218 enum sum_check_flags {
219 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
220 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
225 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
226 * See linux/cpumask.h
228 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
231 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
232 * @memcpy_count: transaction counter
233 * @bytes_transferred: byte counter
237 * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
238 * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
239 * client driver and it is attached (via the dmaengine_desc_attach_metadata()
240 * helper) to the descriptor.
242 * Client drivers interested to use this mode can follow:
243 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
244 * 1. prepare the descriptor (dmaengine_prep_*)
245 * construct the metadata in the client's buffer
246 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
248 * 3. submit the transfer
250 * 1. prepare the descriptor (dmaengine_prep_*)
251 * 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
253 * 3. submit the transfer
254 * 4. when the transfer is completed, the metadata should be available in the
257 * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
258 * driver. The client driver can ask for the pointer, maximum size and the
259 * currently used size of the metadata and can directly update or read it.
260 * dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
261 * provided as helper functions.
263 * Note: the metadata area for the descriptor is no longer valid after the
264 * transfer has been completed (valid up to the point when the completion
265 * callback returns if used).
267 * Client drivers interested to use this mode can follow:
268 * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
269 * 1. prepare the descriptor (dmaengine_prep_*)
270 * 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
272 * 3. update the metadata at the pointer
273 * 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
274 * of data the client has placed into the metadata buffer
275 * 5. submit the transfer
277 * 1. prepare the descriptor (dmaengine_prep_*)
278 * 2. submit the transfer
279 * 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
280 * pointer to the engine's metadata area
281 * 4. Read out the metadata from the pointer
283 * Note: the two mode is not compatible and clients must use one mode for a
286 enum dma_desc_metadata_mode {
287 DESC_METADATA_NONE = 0,
288 DESC_METADATA_CLIENT = BIT(0),
289 DESC_METADATA_ENGINE = BIT(1),
292 struct dma_chan_percpu {
294 unsigned long memcpy_count;
295 unsigned long bytes_transferred;
299 * struct dma_router - DMA router structure
300 * @dev: pointer to the DMA router device
301 * @route_free: function to be called when the route can be disconnected
305 void (*route_free)(struct device *dev, void *route_data);
309 * struct dma_chan - devices supply DMA channels, clients use them
310 * @device: ptr to the dma device who supplies this channel, always !%NULL
311 * @slave: ptr to the device using this channel
312 * @cookie: last cookie value returned to client
313 * @completed_cookie: last completed cookie for this channel
314 * @chan_id: channel ID for sysfs
315 * @dev: class device for sysfs
316 * @name: backlink name for sysfs
317 * @dbg_client_name: slave name for debugfs in format:
318 * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
319 * @device_node: used to add this to the device chan list
320 * @local: per-cpu pointer to a struct dma_chan_percpu
321 * @client_count: how many clients are using this channel
322 * @table_count: number of appearances in the mem-to-mem allocation table
323 * @router: pointer to the DMA router structure
324 * @route_data: channel specific data for the router
325 * @private: private data for certain client-channel associations
328 struct dma_device *device;
329 struct device *slave;
331 dma_cookie_t completed_cookie;
335 struct dma_chan_dev *dev;
337 #ifdef CONFIG_DEBUG_FS
338 char *dbg_client_name;
341 struct list_head device_node;
342 struct dma_chan_percpu __percpu *local;
347 struct dma_router *router;
354 * struct dma_chan_dev - relate sysfs device node to backing channel device
355 * @chan: driver channel device
356 * @device: sysfs device
357 * @dev_id: parent dma_device dev_id
359 struct dma_chan_dev {
360 struct dma_chan *chan;
361 struct device device;
366 * enum dma_slave_buswidth - defines bus width of the DMA slave
367 * device, source or target buses
369 enum dma_slave_buswidth {
370 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
371 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
372 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
373 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
374 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
375 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
376 DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
377 DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
378 DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
382 * struct dma_slave_config - dma slave channel runtime config
383 * @direction: whether the data shall go in or out on this slave
384 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
385 * legal values. DEPRECATED, drivers should use the direction argument
386 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
387 * the dir field in the dma_interleaved_template structure.
388 * @src_addr: this is the physical address where DMA slave data
389 * should be read (RX), if the source is memory this argument is
391 * @dst_addr: this is the physical address where DMA slave data
392 * should be written (TX), if the source is memory this argument
394 * @src_addr_width: this is the width in bytes of the source (RX)
395 * register where DMA data shall be read. If the source
396 * is memory this may be ignored depending on architecture.
397 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
398 * @dst_addr_width: same as src_addr_width but for destination
399 * target (TX) mutatis mutandis.
400 * @src_maxburst: the maximum number of words (note: words, as in
401 * units of the src_addr_width member, not bytes) that can be sent
402 * in one burst to the device. Typically something like half the
403 * FIFO depth on I/O peripherals so you don't overflow it. This
404 * may or may not be applicable on memory sources.
405 * @dst_maxburst: same as src_maxburst but for destination target
407 * @src_port_window_size: The length of the register area in words the data need
408 * to be accessed on the device side. It is only used for devices which is using
409 * an area instead of a single register to receive the data. Typically the DMA
410 * loops in this area in order to transfer the data.
411 * @dst_port_window_size: same as src_port_window_size but for the destination
413 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
414 * with 'true' if peripheral should be flow controller. Direction will be
415 * selected at Runtime.
416 * @slave_id: Slave requester id. Only valid for slave channels. The dma
417 * slave peripheral will have unique id as dma requester which need to be
418 * pass as slave config.
420 * This struct is passed in as configuration data to a DMA engine
421 * in order to set up a certain channel for DMA transport at runtime.
422 * The DMA device/engine has to provide support for an additional
423 * callback in the dma_device structure, device_config and this struct
424 * will then be passed in as an argument to the function.
426 * The rationale for adding configuration information to this struct is as
427 * follows: if it is likely that more than one DMA slave controllers in
428 * the world will support the configuration option, then make it generic.
429 * If not: if it is fixed so that it be sent in static from the platform
430 * data, then prefer to do that.
432 struct dma_slave_config {
433 enum dma_transfer_direction direction;
434 phys_addr_t src_addr;
435 phys_addr_t dst_addr;
436 enum dma_slave_buswidth src_addr_width;
437 enum dma_slave_buswidth dst_addr_width;
440 u32 src_port_window_size;
441 u32 dst_port_window_size;
443 unsigned int slave_id;
447 * enum dma_residue_granularity - Granularity of the reported transfer residue
448 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
449 * DMA channel is only able to tell whether a descriptor has been completed or
450 * not, which means residue reporting is not supported by this channel. The
451 * residue field of the dma_tx_state field will always be 0.
452 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
453 * completed segment of the transfer (For cyclic transfers this is after each
454 * period). This is typically implemented by having the hardware generate an
455 * interrupt after each transferred segment and then the drivers updates the
456 * outstanding residue by the size of the segment. Another possibility is if
457 * the hardware supports scatter-gather and the segment descriptor has a field
458 * which gets set after the segment has been completed. The driver then counts
459 * the number of segments without the flag set to compute the residue.
460 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
461 * burst. This is typically only supported if the hardware has a progress
462 * register of some sort (E.g. a register with the current read/write address
463 * or a register with the amount of bursts/beats/bytes that have been
464 * transferred or still need to be transferred).
466 enum dma_residue_granularity {
467 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
468 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
469 DMA_RESIDUE_GRANULARITY_BURST = 2,
473 * struct dma_slave_caps - expose capabilities of a slave channel only
474 * @src_addr_widths: bit mask of src addr widths the channel supports.
475 * Width is specified in bytes, e.g. for a channel supporting
476 * a width of 4 the mask should have BIT(4) set.
477 * @dst_addr_widths: bit mask of dst addr widths the channel supports
478 * @directions: bit mask of slave directions the channel supports.
479 * Since the enum dma_transfer_direction is not defined as bit flag for
480 * each type, the dma controller should set BIT(<TYPE>) and same
481 * should be checked by controller as well
482 * @max_burst: max burst capability per-transfer
483 * @cmd_pause: true, if pause is supported (i.e. for reading residue or
485 * @cmd_resume: true, if resume is supported
486 * @cmd_terminate: true, if terminate cmd is supported
487 * @residue_granularity: granularity of the reported transfer residue
488 * @descriptor_reuse: if a descriptor can be reused by client and
489 * resubmitted multiple times
491 struct dma_slave_caps {
499 enum dma_residue_granularity residue_granularity;
500 bool descriptor_reuse;
503 static inline const char *dma_chan_name(struct dma_chan *chan)
505 return dev_name(&chan->dev->device);
508 void dma_chan_cleanup(struct kref *kref);
511 * typedef dma_filter_fn - callback filter for dma_request_channel
512 * @chan: channel to be reviewed
513 * @filter_param: opaque parameter passed through dma_request_channel
515 * When this optional parameter is specified in a call to dma_request_channel a
516 * suitable channel is passed to this routine for further dispositioning before
517 * being returned. Where 'suitable' indicates a non-busy channel that
518 * satisfies the given capability mask. It returns 'true' to indicate that the
519 * channel is suitable.
521 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
523 typedef void (*dma_async_tx_callback)(void *dma_async_param);
525 enum dmaengine_tx_result {
526 DMA_TRANS_NOERROR = 0, /* SUCCESS */
527 DMA_TRANS_READ_FAILED, /* Source DMA read failed */
528 DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */
529 DMA_TRANS_ABORTED, /* Op never submitted / aborted */
532 struct dmaengine_result {
533 enum dmaengine_tx_result result;
537 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
538 const struct dmaengine_result *result);
540 struct dmaengine_unmap_data {
541 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
555 struct dma_async_tx_descriptor;
557 struct dma_descriptor_metadata_ops {
558 int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
561 void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
562 size_t *payload_len, size_t *max_len);
563 int (*set_len)(struct dma_async_tx_descriptor *desc,
568 * struct dma_async_tx_descriptor - async transaction descriptor
569 * ---dma generic offload fields---
570 * @cookie: tracking cookie for this transaction, set to -EBUSY if
571 * this tx is sitting on a dependency list
572 * @flags: flags to augment operation preparation, control completion, and
574 * @phys: physical address of the descriptor
575 * @chan: target channel for this operation
576 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
577 * descriptor pending. To be pushed on .issue_pending() call
578 * @callback: routine to call after this operation is complete
579 * @callback_param: general parameter to pass to the callback routine
580 * @desc_metadata_mode: core managed metadata mode to protect mixed use of
581 * DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
583 * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
584 * DMA driver if metadata mode is supported with the descriptor
585 * ---async_tx api specific fields---
586 * @next: at completion submit this descriptor
587 * @parent: pointer to the next level up in the dependency chain
588 * @lock: protect the parent and next pointers
590 struct dma_async_tx_descriptor {
592 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
594 struct dma_chan *chan;
595 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
596 int (*desc_free)(struct dma_async_tx_descriptor *tx);
597 dma_async_tx_callback callback;
598 dma_async_tx_callback_result callback_result;
599 void *callback_param;
600 struct dmaengine_unmap_data *unmap;
601 enum dma_desc_metadata_mode desc_metadata_mode;
602 struct dma_descriptor_metadata_ops *metadata_ops;
603 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
604 struct dma_async_tx_descriptor *next;
605 struct dma_async_tx_descriptor *parent;
610 #ifdef CONFIG_DMA_ENGINE
611 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
612 struct dmaengine_unmap_data *unmap)
614 kref_get(&unmap->kref);
618 struct dmaengine_unmap_data *
619 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
620 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
622 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
623 struct dmaengine_unmap_data *unmap)
626 static inline struct dmaengine_unmap_data *
627 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
631 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
636 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
641 dmaengine_unmap_put(tx->unmap);
645 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
646 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
649 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
652 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
656 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
659 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
662 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
666 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
672 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
674 spin_lock_bh(&txd->lock);
676 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
678 spin_unlock_bh(&txd->lock);
680 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
685 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
689 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
693 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
697 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
704 * struct dma_tx_state - filled in to report the status of
706 * @last: last completed DMA cookie
707 * @used: last issued DMA cookie (i.e. the one in progress)
708 * @residue: the remaining number of bytes left to transmit
709 * on the selected transfer for states DMA_IN_PROGRESS and
710 * DMA_PAUSED if this is implemented in the driver, else 0
711 * @in_flight_bytes: amount of data in bytes cached by the DMA.
713 struct dma_tx_state {
721 * enum dmaengine_alignment - defines alignment of the DMA async tx
724 enum dmaengine_alignment {
725 DMAENGINE_ALIGN_1_BYTE = 0,
726 DMAENGINE_ALIGN_2_BYTES = 1,
727 DMAENGINE_ALIGN_4_BYTES = 2,
728 DMAENGINE_ALIGN_8_BYTES = 3,
729 DMAENGINE_ALIGN_16_BYTES = 4,
730 DMAENGINE_ALIGN_32_BYTES = 5,
731 DMAENGINE_ALIGN_64_BYTES = 6,
735 * struct dma_slave_map - associates slave device and it's slave channel with
736 * parameter to be used by a filter function
737 * @devname: name of the device
738 * @slave: slave channel name
739 * @param: opaque parameter to pass to struct dma_filter.fn
741 struct dma_slave_map {
748 * struct dma_filter - information for slave device/channel to filter_fn/param
750 * @fn: filter function callback
751 * @mapcnt: number of slave device/channel in the map
752 * @map: array of channel to filter mapping data
757 const struct dma_slave_map *map;
761 * struct dma_device - info on the entity supplying DMA services
762 * @chancnt: how many DMA channels are supported
763 * @privatecnt: how many DMA channels are requested by dma_request_channel
764 * @channels: the list of struct dma_chan
765 * @global_node: list_head for global dma_device_list
766 * @filter: information for device/slave to filter function/param mapping
767 * @cap_mask: one or more dma_capability flags
768 * @desc_metadata_modes: supported metadata modes by the DMA device
769 * @max_xor: maximum number of xor sources, 0 if no capability
770 * @max_pq: maximum number of PQ sources and PQ-continue capability
771 * @copy_align: alignment shift for memcpy operations
772 * @xor_align: alignment shift for xor operations
773 * @pq_align: alignment shift for pq operations
774 * @fill_align: alignment shift for memset operations
775 * @dev_id: unique device ID
776 * @dev: struct device reference for dma mapping api
777 * @owner: owner module (automatically set based on the provided dev)
778 * @src_addr_widths: bit mask of src addr widths the device supports
779 * Width is specified in bytes, e.g. for a device supporting
780 * a width of 4 the mask should have BIT(4) set.
781 * @dst_addr_widths: bit mask of dst addr widths the device supports
782 * @directions: bit mask of slave directions the device supports.
783 * Since the enum dma_transfer_direction is not defined as bit flag for
784 * each type, the dma controller should set BIT(<TYPE>) and same
785 * should be checked by controller as well
786 * @max_burst: max burst capability per-transfer
787 * @residue_granularity: granularity of the transfer residue reported
789 * @device_alloc_chan_resources: allocate resources and return the
790 * number of allocated descriptors
791 * @device_free_chan_resources: release DMA channel's resources
792 * @device_prep_dma_memcpy: prepares a memcpy operation
793 * @device_prep_dma_xor: prepares a xor operation
794 * @device_prep_dma_xor_val: prepares a xor validation operation
795 * @device_prep_dma_pq: prepares a pq operation
796 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
797 * @device_prep_dma_memset: prepares a memset operation
798 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
799 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
800 * @device_prep_slave_sg: prepares a slave dma operation
801 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
802 * The function takes a buffer of size buf_len. The callback function will
803 * be called after period_len bytes have been transferred.
804 * @device_prep_interleaved_dma: Transfer expression in a generic way.
805 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
806 * @device_config: Pushes a new configuration to a channel, return 0 or an error
808 * @device_pause: Pauses any transfer happening on a channel. Returns
810 * @device_resume: Resumes any transfer on a channel previously
811 * paused. Returns 0 or an error code
812 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
814 * @device_synchronize: Synchronizes the termination of a transfers to the
816 * @device_tx_status: poll for transaction completion, the optional
817 * txstate parameter can be supplied with a pointer to get a
818 * struct with auxiliary transfer status information, otherwise the call
819 * will just return a simple status code
820 * @device_issue_pending: push pending transactions to hardware
821 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
822 * @device_release: called sometime atfer dma_async_device_unregister() is
823 * called and there are no further references to this structure. This
824 * must be implemented to free resources however many existing drivers
825 * do not and are therefore not safe to unbind while in use.
826 * @dbg_summary_show: optional routine to show contents in debugfs; default code
827 * will be used when this is omitted, but custom code can show extra,
828 * controller specific information.
832 unsigned int chancnt;
833 unsigned int privatecnt;
834 struct list_head channels;
835 struct list_head global_node;
836 struct dma_filter filter;
837 dma_cap_mask_t cap_mask;
838 enum dma_desc_metadata_mode desc_metadata_modes;
839 unsigned short max_xor;
840 unsigned short max_pq;
841 enum dmaengine_alignment copy_align;
842 enum dmaengine_alignment xor_align;
843 enum dmaengine_alignment pq_align;
844 enum dmaengine_alignment fill_align;
845 #define DMA_HAS_PQ_CONTINUE (1 << 15)
849 struct module *owner;
851 struct mutex chan_mutex; /* to protect chan_ida */
857 bool descriptor_reuse;
858 enum dma_residue_granularity residue_granularity;
860 int (*device_alloc_chan_resources)(struct dma_chan *chan);
861 void (*device_free_chan_resources)(struct dma_chan *chan);
863 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
864 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
865 size_t len, unsigned long flags);
866 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
867 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
868 unsigned int src_cnt, size_t len, unsigned long flags);
869 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
870 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
871 size_t len, enum sum_check_flags *result, unsigned long flags);
872 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
873 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
874 unsigned int src_cnt, const unsigned char *scf,
875 size_t len, unsigned long flags);
876 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
877 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
878 unsigned int src_cnt, const unsigned char *scf, size_t len,
879 enum sum_check_flags *pqres, unsigned long flags);
880 struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
881 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
882 unsigned long flags);
883 struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
884 struct dma_chan *chan, struct scatterlist *sg,
885 unsigned int nents, int value, unsigned long flags);
886 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
887 struct dma_chan *chan, unsigned long flags);
889 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
890 struct dma_chan *chan, struct scatterlist *sgl,
891 unsigned int sg_len, enum dma_transfer_direction direction,
892 unsigned long flags, void *context);
893 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
894 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
895 size_t period_len, enum dma_transfer_direction direction,
896 unsigned long flags);
897 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
898 struct dma_chan *chan, struct dma_interleaved_template *xt,
899 unsigned long flags);
900 struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
901 struct dma_chan *chan, dma_addr_t dst, u64 data,
902 unsigned long flags);
904 int (*device_config)(struct dma_chan *chan,
905 struct dma_slave_config *config);
906 int (*device_pause)(struct dma_chan *chan);
907 int (*device_resume)(struct dma_chan *chan);
908 int (*device_terminate_all)(struct dma_chan *chan);
909 void (*device_synchronize)(struct dma_chan *chan);
911 enum dma_status (*device_tx_status)(struct dma_chan *chan,
913 struct dma_tx_state *txstate);
914 void (*device_issue_pending)(struct dma_chan *chan);
915 void (*device_release)(struct dma_device *dev);
916 /* debugfs support */
917 #ifdef CONFIG_DEBUG_FS
918 void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
919 struct dentry *dbg_dev_root;
923 static inline int dmaengine_slave_config(struct dma_chan *chan,
924 struct dma_slave_config *config)
926 if (chan->device->device_config)
927 return chan->device->device_config(chan, config);
932 static inline bool is_slave_direction(enum dma_transfer_direction direction)
934 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
937 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
938 struct dma_chan *chan, dma_addr_t buf, size_t len,
939 enum dma_transfer_direction dir, unsigned long flags)
941 struct scatterlist sg;
942 sg_init_table(&sg, 1);
943 sg_dma_address(&sg) = buf;
944 sg_dma_len(&sg) = len;
946 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
949 return chan->device->device_prep_slave_sg(chan, &sg, 1,
953 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
954 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
955 enum dma_transfer_direction dir, unsigned long flags)
957 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
960 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
964 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
966 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
967 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
968 enum dma_transfer_direction dir, unsigned long flags,
969 struct rio_dma_ext *rio_ext)
971 if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
974 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
975 dir, flags, rio_ext);
979 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
980 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
981 size_t period_len, enum dma_transfer_direction dir,
984 if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
987 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
988 period_len, dir, flags);
991 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
992 struct dma_chan *chan, struct dma_interleaved_template *xt,
995 if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
997 if (flags & DMA_PREP_REPEAT &&
998 !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
1001 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
1004 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
1005 struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
1006 unsigned long flags)
1008 if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
1011 return chan->device->device_prep_dma_memset(chan, dest, value,
1015 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
1016 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1017 size_t len, unsigned long flags)
1019 if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
1022 return chan->device->device_prep_dma_memcpy(chan, dest, src,
1026 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
1027 enum dma_desc_metadata_mode mode)
1032 return !!(chan->device->desc_metadata_modes & mode);
1035 #ifdef CONFIG_DMA_ENGINE
1036 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
1037 void *data, size_t len);
1038 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
1039 size_t *payload_len, size_t *max_len);
1040 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
1041 size_t payload_len);
1042 #else /* CONFIG_DMA_ENGINE */
1043 static inline int dmaengine_desc_attach_metadata(
1044 struct dma_async_tx_descriptor *desc, void *data, size_t len)
1048 static inline void *dmaengine_desc_get_metadata_ptr(
1049 struct dma_async_tx_descriptor *desc, size_t *payload_len,
1054 static inline int dmaengine_desc_set_metadata_len(
1055 struct dma_async_tx_descriptor *desc, size_t payload_len)
1059 #endif /* CONFIG_DMA_ENGINE */
1062 * dmaengine_terminate_all() - Terminate all active DMA transfers
1063 * @chan: The channel for which to terminate the transfers
1065 * This function is DEPRECATED use either dmaengine_terminate_sync() or
1066 * dmaengine_terminate_async() instead.
1068 static inline int dmaengine_terminate_all(struct dma_chan *chan)
1070 if (chan->device->device_terminate_all)
1071 return chan->device->device_terminate_all(chan);
1077 * dmaengine_terminate_async() - Terminate all active DMA transfers
1078 * @chan: The channel for which to terminate the transfers
1080 * Calling this function will terminate all active and pending descriptors
1081 * that have previously been submitted to the channel. It is not guaranteed
1082 * though that the transfer for the active descriptor has stopped when the
1083 * function returns. Furthermore it is possible the complete callback of a
1084 * submitted transfer is still running when this function returns.
1086 * dmaengine_synchronize() needs to be called before it is safe to free
1087 * any memory that is accessed by previously submitted descriptors or before
1088 * freeing any resources accessed from within the completion callback of any
1089 * previously submitted descriptors.
1091 * This function can be called from atomic context as well as from within a
1092 * complete callback of a descriptor submitted on the same channel.
1094 * If none of the two conditions above apply consider using
1095 * dmaengine_terminate_sync() instead.
1097 static inline int dmaengine_terminate_async(struct dma_chan *chan)
1099 if (chan->device->device_terminate_all)
1100 return chan->device->device_terminate_all(chan);
1106 * dmaengine_synchronize() - Synchronize DMA channel termination
1107 * @chan: The channel to synchronize
1109 * Synchronizes to the DMA channel termination to the current context. When this
1110 * function returns it is guaranteed that all transfers for previously issued
1111 * descriptors have stopped and it is safe to free the memory associated
1112 * with them. Furthermore it is guaranteed that all complete callback functions
1113 * for a previously submitted descriptor have finished running and it is safe to
1114 * free resources accessed from within the complete callbacks.
1116 * The behavior of this function is undefined if dma_async_issue_pending() has
1117 * been called between dmaengine_terminate_async() and this function.
1119 * This function must only be called from non-atomic context and must not be
1120 * called from within a complete callback of a descriptor submitted on the same
1123 static inline void dmaengine_synchronize(struct dma_chan *chan)
1127 if (chan->device->device_synchronize)
1128 chan->device->device_synchronize(chan);
1132 * dmaengine_terminate_sync() - Terminate all active DMA transfers
1133 * @chan: The channel for which to terminate the transfers
1135 * Calling this function will terminate all active and pending transfers
1136 * that have previously been submitted to the channel. It is similar to
1137 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1138 * stopped and that all complete callbacks have finished running when the
1141 * This function must only be called from non-atomic context and must not be
1142 * called from within a complete callback of a descriptor submitted on the same
1145 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1149 ret = dmaengine_terminate_async(chan);
1153 dmaengine_synchronize(chan);
1158 static inline int dmaengine_pause(struct dma_chan *chan)
1160 if (chan->device->device_pause)
1161 return chan->device->device_pause(chan);
1166 static inline int dmaengine_resume(struct dma_chan *chan)
1168 if (chan->device->device_resume)
1169 return chan->device->device_resume(chan);
1174 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1175 dma_cookie_t cookie, struct dma_tx_state *state)
1177 return chan->device->device_tx_status(chan, cookie, state);
1180 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1182 return desc->tx_submit(desc);
1185 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1186 size_t off1, size_t off2, size_t len)
1188 return !(((1 << align) - 1) & (off1 | off2 | len));
1191 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1192 size_t off2, size_t len)
1194 return dmaengine_check_align(dev->copy_align, off1, off2, len);
1197 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1198 size_t off2, size_t len)
1200 return dmaengine_check_align(dev->xor_align, off1, off2, len);
1203 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1204 size_t off2, size_t len)
1206 return dmaengine_check_align(dev->pq_align, off1, off2, len);
1209 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1210 size_t off2, size_t len)
1212 return dmaengine_check_align(dev->fill_align, off1, off2, len);
1216 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1218 dma->max_pq = maxpq;
1219 if (has_pq_continue)
1220 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1223 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1225 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1228 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1230 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1232 return (flags & mask) == mask;
1235 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1237 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1240 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1242 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1245 /* dma_maxpq - reduce maxpq in the face of continued operations
1246 * @dma - dma device with PQ capability
1247 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1249 * When an engine does not support native continuation we need 3 extra
1250 * source slots to reuse P and Q with the following coefficients:
1251 * 1/ {00} * P : remove P from Q', but use it as a source for P'
1252 * 2/ {01} * Q : use Q to continue Q' calculation
1253 * 3/ {00} * Q : subtract Q from P' to cancel (2)
1255 * In the case where P is disabled we only need 1 extra source:
1256 * 1/ {01} * Q : use Q to continue Q' calculation
1258 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1260 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1261 return dma_dev_to_maxpq(dma);
1262 if (dmaf_p_disabled_continue(flags))
1263 return dma_dev_to_maxpq(dma) - 1;
1264 if (dmaf_continue(flags))
1265 return dma_dev_to_maxpq(dma) - 3;
1269 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1282 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1283 struct data_chunk *chunk)
1285 return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1286 chunk->icg, chunk->dst_icg);
1289 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1290 struct data_chunk *chunk)
1292 return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1293 chunk->icg, chunk->src_icg);
1296 /* --- public DMA engine API --- */
1298 #ifdef CONFIG_DMA_ENGINE
1299 void dmaengine_get(void);
1300 void dmaengine_put(void);
1302 static inline void dmaengine_get(void)
1305 static inline void dmaengine_put(void)
1310 #ifdef CONFIG_ASYNC_TX_DMA
1311 #define async_dmaengine_get() dmaengine_get()
1312 #define async_dmaengine_put() dmaengine_put()
1313 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1314 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1316 #define async_dma_find_channel(type) dma_find_channel(type)
1317 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1319 static inline void async_dmaengine_get(void)
1322 static inline void async_dmaengine_put(void)
1325 static inline struct dma_chan *
1326 async_dma_find_channel(enum dma_transaction_type type)
1330 #endif /* CONFIG_ASYNC_TX_DMA */
1331 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1332 struct dma_chan *chan);
1334 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1336 tx->flags |= DMA_CTRL_ACK;
1339 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1341 tx->flags &= ~DMA_CTRL_ACK;
1344 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1346 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1349 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1351 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1353 set_bit(tx_type, dstp->bits);
1356 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1358 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1360 clear_bit(tx_type, dstp->bits);
1363 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
1364 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1366 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1369 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1371 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1373 return test_bit(tx_type, srcp->bits);
1376 #define for_each_dma_cap_mask(cap, mask) \
1377 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1380 * dma_async_issue_pending - flush pending transactions to HW
1381 * @chan: target DMA channel
1383 * This allows drivers to push copies to HW in batches,
1384 * reducing MMIO writes where possible.
1386 static inline void dma_async_issue_pending(struct dma_chan *chan)
1388 chan->device->device_issue_pending(chan);
1392 * dma_async_is_tx_complete - poll for transaction completion
1393 * @chan: DMA channel
1394 * @cookie: transaction identifier to check status of
1395 * @last: returns last completed cookie, can be NULL
1396 * @used: returns last issued cookie, can be NULL
1398 * If @last and @used are passed in, upon return they reflect the driver
1399 * internal state and can be used with dma_async_is_complete() to check
1400 * the status of multiple cookies without re-checking hardware state.
1402 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1403 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1405 struct dma_tx_state state;
1406 enum dma_status status;
1408 status = chan->device->device_tx_status(chan, cookie, &state);
1417 * dma_async_is_complete - test a cookie against chan state
1418 * @cookie: transaction identifier to test status of
1419 * @last_complete: last know completed transaction
1420 * @last_used: last cookie value handed out
1422 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1423 * the test logic is separated for lightweight testing of multiple cookies
1425 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1426 dma_cookie_t last_complete, dma_cookie_t last_used)
1428 if (last_complete <= last_used) {
1429 if ((cookie <= last_complete) || (cookie > last_used))
1430 return DMA_COMPLETE;
1432 if ((cookie <= last_complete) && (cookie > last_used))
1433 return DMA_COMPLETE;
1435 return DMA_IN_PROGRESS;
1439 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1446 st->residue = residue;
1449 #ifdef CONFIG_DMA_ENGINE
1450 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1451 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1452 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1453 void dma_issue_pending_all(void);
1454 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1455 dma_filter_fn fn, void *fn_param,
1456 struct device_node *np);
1457 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1459 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1460 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1462 void dma_release_channel(struct dma_chan *chan);
1463 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1465 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1469 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1471 return DMA_COMPLETE;
1473 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1475 return DMA_COMPLETE;
1477 static inline void dma_issue_pending_all(void)
1480 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1483 struct device_node *np)
1487 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1492 static inline struct dma_chan *dma_request_chan(struct device *dev,
1495 return ERR_PTR(-ENODEV);
1497 static inline struct dma_chan *dma_request_chan_by_mask(
1498 const dma_cap_mask_t *mask)
1500 return ERR_PTR(-ENODEV);
1502 static inline void dma_release_channel(struct dma_chan *chan)
1505 static inline int dma_get_slave_caps(struct dma_chan *chan,
1506 struct dma_slave_caps *caps)
1512 #define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
1514 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1516 struct dma_slave_caps caps;
1519 ret = dma_get_slave_caps(tx->chan, &caps);
1523 if (!caps.descriptor_reuse)
1526 tx->flags |= DMA_CTRL_REUSE;
1530 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1532 tx->flags &= ~DMA_CTRL_REUSE;
1535 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1537 return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1540 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1542 /* this is supported for reusable desc, so check that */
1543 if (!dmaengine_desc_test_reuse(desc))
1546 return desc->desc_free(desc);
1549 /* --- DMA device --- */
1551 int dma_async_device_register(struct dma_device *device);
1552 int dmaenginem_async_device_register(struct dma_device *device);
1553 void dma_async_device_unregister(struct dma_device *device);
1554 int dma_async_device_channel_register(struct dma_device *device,
1555 struct dma_chan *chan);
1556 void dma_async_device_channel_unregister(struct dma_device *device,
1557 struct dma_chan *chan);
1558 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1559 #define dma_request_channel(mask, x, y) \
1560 __dma_request_channel(&(mask), x, y, NULL)
1562 static inline struct dma_chan
1563 *dma_request_slave_channel_compat(const dma_cap_mask_t mask,
1564 dma_filter_fn fn, void *fn_param,
1565 struct device *dev, const char *name)
1567 struct dma_chan *chan;
1569 chan = dma_request_slave_channel(dev, name);
1573 if (!fn || !fn_param)
1576 return __dma_request_channel(&mask, fn, fn_param, NULL);
1579 static inline char *
1580 dmaengine_get_direction_text(enum dma_transfer_direction dir)
1583 case DMA_DEV_TO_MEM:
1584 return "DEV_TO_MEM";
1585 case DMA_MEM_TO_DEV:
1586 return "MEM_TO_DEV";
1587 case DMA_MEM_TO_MEM:
1588 return "MEM_TO_MEM";
1589 case DMA_DEV_TO_DEV:
1590 return "DEV_TO_DEV";
1595 #endif /* DMAENGINE_H */