1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
9 #include <linux/device.h>
10 #include <linux/perf_event.h>
11 #include <linux/sched.h>
13 /* Peripheral id registers (0xFD0-0xFEC) */
14 #define CORESIGHT_PERIPHIDR4 0xfd0
15 #define CORESIGHT_PERIPHIDR5 0xfd4
16 #define CORESIGHT_PERIPHIDR6 0xfd8
17 #define CORESIGHT_PERIPHIDR7 0xfdC
18 #define CORESIGHT_PERIPHIDR0 0xfe0
19 #define CORESIGHT_PERIPHIDR1 0xfe4
20 #define CORESIGHT_PERIPHIDR2 0xfe8
21 #define CORESIGHT_PERIPHIDR3 0xfeC
22 /* Component id registers (0xFF0-0xFFC) */
23 #define CORESIGHT_COMPIDR0 0xff0
24 #define CORESIGHT_COMPIDR1 0xff4
25 #define CORESIGHT_COMPIDR2 0xff8
26 #define CORESIGHT_COMPIDR3 0xffC
28 #define ETM_ARCH_V3_3 0x23
29 #define ETM_ARCH_V3_5 0x25
30 #define PFT_ARCH_V1_0 0x30
31 #define PFT_ARCH_V1_1 0x31
33 #define CORESIGHT_UNLOCK 0xc5acce55
35 extern struct bus_type coresight_bustype;
37 enum coresight_dev_type {
38 CORESIGHT_DEV_TYPE_NONE,
39 CORESIGHT_DEV_TYPE_SINK,
40 CORESIGHT_DEV_TYPE_LINK,
41 CORESIGHT_DEV_TYPE_LINKSINK,
42 CORESIGHT_DEV_TYPE_SOURCE,
43 CORESIGHT_DEV_TYPE_HELPER,
44 CORESIGHT_DEV_TYPE_ECT,
47 enum coresight_dev_subtype_sink {
48 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
49 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
50 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
53 enum coresight_dev_subtype_link {
54 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
55 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
56 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
57 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
60 enum coresight_dev_subtype_source {
61 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
62 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
63 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
64 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
67 enum coresight_dev_subtype_helper {
68 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
69 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
72 /* Embedded Cross Trigger (ECT) sub-types */
73 enum coresight_dev_subtype_ect {
74 CORESIGHT_DEV_SUBTYPE_ECT_NONE,
75 CORESIGHT_DEV_SUBTYPE_ECT_CTI,
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
81 * by @coresight_dev_subtype_sink.
82 * @link_subtype: type of link this component is, as defined
83 * by @coresight_dev_subtype_link.
84 * @source_subtype: type of source this component is, as defined
85 * by @coresight_dev_subtype_source.
86 * @helper_subtype: type of helper this component is, as defined
87 * by @coresight_dev_subtype_helper.
88 * @ect_subtype: type of cross trigger this component is, as
89 * defined by @coresight_dev_subtype_ect
91 union coresight_dev_subtype {
92 /* We have some devices which acts as LINK and SINK */
94 enum coresight_dev_subtype_sink sink_subtype;
95 enum coresight_dev_subtype_link link_subtype;
97 enum coresight_dev_subtype_source source_subtype;
98 enum coresight_dev_subtype_helper helper_subtype;
99 enum coresight_dev_subtype_ect ect_subtype;
103 * struct coresight_platform_data - data harvested from the DT specification
104 * @nr_inport: number of input ports for this component.
105 * @nr_outport: number of output ports for this component.
106 * @conns: Array of nr_outport connections from this component
108 struct coresight_platform_data {
111 struct coresight_connection *conns;
115 * struct coresight_desc - description of a component required from drivers
116 * @type: as defined by @coresight_dev_type.
117 * @subtype: as defined by @coresight_dev_subtype.
118 * @ops: generic operations for this component, as defined
120 * @pdata: platform data collected from DT.
121 * @dev: The device entity associated to this component.
122 * @groups: operations specific to this component. These will end up
123 * in the component's sysfs sub-directory.
124 * @name: name for the coresight device, also shown under sysfs.
126 struct coresight_desc {
127 enum coresight_dev_type type;
128 union coresight_dev_subtype subtype;
129 const struct coresight_ops *ops;
130 struct coresight_platform_data *pdata;
132 const struct attribute_group **groups;
137 * struct coresight_connection - representation of a single connection
138 * @outport: a connection's output port number.
139 * @child_port: remote component's port number @output is connected to.
140 * @chid_fwnode: remote component's fwnode handle.
141 * @child_dev: a @coresight_device representation of the component
142 connected to @outport.
144 struct coresight_connection {
147 struct fwnode_handle *child_fwnode;
148 struct coresight_device *child_dev;
152 * struct coresight_device - representation of a device as used by the framework
153 * @pdata: Platform data with device connections associated to this device.
154 * @type: as defined by @coresight_dev_type.
155 * @subtype: as defined by @coresight_dev_subtype.
156 * @ops: generic operations for this component, as defined
158 * @dev: The device entity associated to this component.
159 * @refcnt: keep track of what is in use.
160 * @orphan: true if the component has connections that haven't been linked.
161 * @enable: 'true' if component is currently part of an active path.
162 * @activated: 'true' only if a _sink_ has been activated. A sink can be
163 * activated but not yet enabled. Enabling for a _sink_
164 * appens when a source has been selected for that it.
165 * @ea: Device attribute for sink representation under PMU directory.
166 * @ect_dev: Associated cross trigger device. Not part of the trace data
167 * path or connections.
169 struct coresight_device {
170 struct coresight_platform_data *pdata;
171 enum coresight_dev_type type;
172 union coresight_dev_subtype subtype;
173 const struct coresight_ops *ops;
177 bool enable; /* true only if configured as part of a path */
178 /* sink specific fields */
179 bool activated; /* true only if a sink is part of a path */
180 struct dev_ext_attribute *ea;
181 /* cross trigger handling */
182 struct coresight_device *ect_dev;
186 * coresight_dev_list - Mapping for devices to "name" index for device
189 * @nr_idx: Number of entries already allocated.
190 * @pfx: Prefix pattern for device name.
191 * @fwnode_list: Array of fwnode_handles associated with each allocated
192 * index, upto nr_idx entries.
194 struct coresight_dev_list {
197 struct fwnode_handle **fwnode_list;
200 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
201 static struct coresight_dev_list (var) = { \
204 .fwnode_list = NULL, \
207 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
209 #define source_ops(csdev) csdev->ops->source_ops
210 #define sink_ops(csdev) csdev->ops->sink_ops
211 #define link_ops(csdev) csdev->ops->link_ops
212 #define helper_ops(csdev) csdev->ops->helper_ops
213 #define ect_ops(csdev) csdev->ops->ect_ops
216 * struct coresight_ops_sink - basic operations for a sink
217 * Operations available for sinks
218 * @enable: enables the sink.
219 * @disable: disables the sink.
220 * @alloc_buffer: initialises perf's ring buffer for trace collection.
221 * @free_buffer: release memory allocated in @get_config.
222 * @update_buffer: update buffer pointers after a trace session.
224 struct coresight_ops_sink {
225 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
226 int (*disable)(struct coresight_device *csdev);
227 void *(*alloc_buffer)(struct coresight_device *csdev,
228 struct perf_event *event, void **pages,
229 int nr_pages, bool overwrite);
230 void (*free_buffer)(void *config);
231 unsigned long (*update_buffer)(struct coresight_device *csdev,
232 struct perf_output_handle *handle,
237 * struct coresight_ops_link - basic operations for a link
238 * Operations available for links.
239 * @enable: enables flow between iport and oport.
240 * @disable: disables flow between iport and oport.
242 struct coresight_ops_link {
243 int (*enable)(struct coresight_device *csdev, int iport, int oport);
244 void (*disable)(struct coresight_device *csdev, int iport, int oport);
248 * struct coresight_ops_source - basic operations for a source
249 * Operations available for sources.
250 * @cpu_id: returns the value of the CPU number this component
252 * @trace_id: returns the value of the component's trace ID as known
254 * @enable: enables tracing for a source.
255 * @disable: disables tracing for a source.
257 struct coresight_ops_source {
258 int (*cpu_id)(struct coresight_device *csdev);
259 int (*trace_id)(struct coresight_device *csdev);
260 int (*enable)(struct coresight_device *csdev,
261 struct perf_event *event, u32 mode);
262 void (*disable)(struct coresight_device *csdev,
263 struct perf_event *event);
267 * struct coresight_ops_helper - Operations for a helper device.
269 * All operations could pass in a device specific data, which could
270 * help the helper device to determine what to do.
272 * @enable : Enable the device
273 * @disable : Disable the device
275 struct coresight_ops_helper {
276 int (*enable)(struct coresight_device *csdev, void *data);
277 int (*disable)(struct coresight_device *csdev, void *data);
281 * struct coresight_ops_ect - Ops for an embedded cross trigger device
283 * @enable : Enable the device
284 * @disable : Disable the device
286 struct coresight_ops_ect {
287 int (*enable)(struct coresight_device *csdev);
288 int (*disable)(struct coresight_device *csdev);
291 struct coresight_ops {
292 const struct coresight_ops_sink *sink_ops;
293 const struct coresight_ops_link *link_ops;
294 const struct coresight_ops_source *source_ops;
295 const struct coresight_ops_helper *helper_ops;
296 const struct coresight_ops_ect *ect_ops;
299 #ifdef CONFIG_CORESIGHT
300 extern struct coresight_device *
301 coresight_register(struct coresight_desc *desc);
302 extern void coresight_unregister(struct coresight_device *csdev);
303 extern int coresight_enable(struct coresight_device *csdev);
304 extern void coresight_disable(struct coresight_device *csdev);
305 extern int coresight_timeout(void __iomem *addr, u32 offset,
306 int position, int value);
308 extern int coresight_claim_device(void __iomem *base);
309 extern int coresight_claim_device_unlocked(void __iomem *base);
311 extern void coresight_disclaim_device(void __iomem *base);
312 extern void coresight_disclaim_device_unlocked(void __iomem *base);
313 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
316 extern bool coresight_loses_context_with_cpu(struct device *dev);
318 static inline struct coresight_device *
319 coresight_register(struct coresight_desc *desc) { return NULL; }
320 static inline void coresight_unregister(struct coresight_device *csdev) {}
322 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
323 static inline void coresight_disable(struct coresight_device *csdev) {}
324 static inline int coresight_timeout(void __iomem *addr, u32 offset,
325 int position, int value) { return 1; }
326 static inline int coresight_claim_device_unlocked(void __iomem *base)
331 static inline int coresight_claim_device(void __iomem *base)
336 static inline void coresight_disclaim_device(void __iomem *base) {}
337 static inline void coresight_disclaim_device_unlocked(void __iomem *base) {}
339 static inline bool coresight_loses_context_with_cpu(struct device *dev)
345 extern int coresight_get_cpu(struct device *dev);
347 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);