1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
9 #include <linux/device.h>
11 #include <linux/perf_event.h>
12 #include <linux/sched.h>
14 /* Peripheral id registers (0xFD0-0xFEC) */
15 #define CORESIGHT_PERIPHIDR4 0xfd0
16 #define CORESIGHT_PERIPHIDR5 0xfd4
17 #define CORESIGHT_PERIPHIDR6 0xfd8
18 #define CORESIGHT_PERIPHIDR7 0xfdC
19 #define CORESIGHT_PERIPHIDR0 0xfe0
20 #define CORESIGHT_PERIPHIDR1 0xfe4
21 #define CORESIGHT_PERIPHIDR2 0xfe8
22 #define CORESIGHT_PERIPHIDR3 0xfeC
23 /* Component id registers (0xFF0-0xFFC) */
24 #define CORESIGHT_COMPIDR0 0xff0
25 #define CORESIGHT_COMPIDR1 0xff4
26 #define CORESIGHT_COMPIDR2 0xff8
27 #define CORESIGHT_COMPIDR3 0xffC
29 #define ETM_ARCH_V3_3 0x23
30 #define ETM_ARCH_V3_5 0x25
31 #define PFT_ARCH_V1_0 0x30
32 #define PFT_ARCH_V1_1 0x31
34 #define CORESIGHT_UNLOCK 0xc5acce55
36 extern struct bus_type coresight_bustype;
38 enum coresight_dev_type {
39 CORESIGHT_DEV_TYPE_NONE,
40 CORESIGHT_DEV_TYPE_SINK,
41 CORESIGHT_DEV_TYPE_LINK,
42 CORESIGHT_DEV_TYPE_LINKSINK,
43 CORESIGHT_DEV_TYPE_SOURCE,
44 CORESIGHT_DEV_TYPE_HELPER,
45 CORESIGHT_DEV_TYPE_ECT,
48 enum coresight_dev_subtype_sink {
49 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
50 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
51 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
52 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
55 enum coresight_dev_subtype_link {
56 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
57 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
58 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
59 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
62 enum coresight_dev_subtype_source {
63 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
64 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
65 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
66 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
69 enum coresight_dev_subtype_helper {
70 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
71 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
74 /* Embedded Cross Trigger (ECT) sub-types */
75 enum coresight_dev_subtype_ect {
76 CORESIGHT_DEV_SUBTYPE_ECT_NONE,
77 CORESIGHT_DEV_SUBTYPE_ECT_CTI,
81 * union coresight_dev_subtype - further characterisation of a type
82 * @sink_subtype: type of sink this component is, as defined
83 * by @coresight_dev_subtype_sink.
84 * @link_subtype: type of link this component is, as defined
85 * by @coresight_dev_subtype_link.
86 * @source_subtype: type of source this component is, as defined
87 * by @coresight_dev_subtype_source.
88 * @helper_subtype: type of helper this component is, as defined
89 * by @coresight_dev_subtype_helper.
90 * @ect_subtype: type of cross trigger this component is, as
91 * defined by @coresight_dev_subtype_ect
93 union coresight_dev_subtype {
94 /* We have some devices which acts as LINK and SINK */
96 enum coresight_dev_subtype_sink sink_subtype;
97 enum coresight_dev_subtype_link link_subtype;
99 enum coresight_dev_subtype_source source_subtype;
100 enum coresight_dev_subtype_helper helper_subtype;
101 enum coresight_dev_subtype_ect ect_subtype;
105 * struct coresight_platform_data - data harvested from the firmware
108 * @nr_inport: Number of elements for the input connections.
109 * @nr_outport: Number of elements for the output connections.
110 * @conns: Sparse array of nr_outport connections from this component.
112 struct coresight_platform_data {
115 struct coresight_connection *conns;
119 * struct csdev_access - Abstraction of a CoreSight device access.
121 * @io_mem : True if the device has memory mapped I/O
122 * @base : When io_mem == true, base address of the component
123 * @read : Read from the given "offset" of the given instance.
124 * @write : Write "val" to the given "offset".
126 struct csdev_access {
131 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
132 void (*write)(u64 val, u32 offset, bool relaxed,
138 #define CSDEV_ACCESS_IOMEM(_addr) \
139 ((struct csdev_access) { \
145 * struct coresight_desc - description of a component required from drivers
146 * @type: as defined by @coresight_dev_type.
147 * @subtype: as defined by @coresight_dev_subtype.
148 * @ops: generic operations for this component, as defined
150 * @pdata: platform data collected from DT.
151 * @dev: The device entity associated to this component.
152 * @groups: operations specific to this component. These will end up
153 * in the component's sysfs sub-directory.
154 * @name: name for the coresight device, also shown under sysfs.
155 * @access: Describe access to the device
157 struct coresight_desc {
158 enum coresight_dev_type type;
159 union coresight_dev_subtype subtype;
160 const struct coresight_ops *ops;
161 struct coresight_platform_data *pdata;
163 const struct attribute_group **groups;
165 struct csdev_access access;
169 * struct coresight_connection - representation of a single connection
170 * @outport: a connection's output port number.
171 * @child_port: remote component's port number @output is connected to.
172 * @chid_fwnode: remote component's fwnode handle.
173 * @child_dev: a @coresight_device representation of the component
174 connected to @outport.
175 * @link: Representation of the connection as a sysfs link.
177 struct coresight_connection {
180 struct fwnode_handle *child_fwnode;
181 struct coresight_device *child_dev;
182 struct coresight_sysfs_link *link;
186 * struct coresight_sysfs_link - representation of a connection in sysfs.
187 * @orig: Originating (master) coresight device for the link.
188 * @orig_name: Name to use for the link orig->target.
189 * @target: Target (slave) coresight device for the link.
190 * @target_name: Name to use for the link target->orig.
192 struct coresight_sysfs_link {
193 struct coresight_device *orig;
194 const char *orig_name;
195 struct coresight_device *target;
196 const char *target_name;
200 * struct coresight_device - representation of a device as used by the framework
201 * @pdata: Platform data with device connections associated to this device.
202 * @type: as defined by @coresight_dev_type.
203 * @subtype: as defined by @coresight_dev_subtype.
204 * @ops: generic operations for this component, as defined
206 * @access: Device i/o access abstraction for this device.
207 * @dev: The device entity associated to this component.
208 * @refcnt: keep track of what is in use.
209 * @orphan: true if the component has connections that haven't been linked.
210 * @enable: 'true' if component is currently part of an active path.
211 * @activated: 'true' only if a _sink_ has been activated. A sink can be
212 * activated but not yet enabled. Enabling for a _sink_
213 * happens when a source has been selected and a path is enabled
214 * from source to that sink.
215 * @ea: Device attribute for sink representation under PMU directory.
216 * @def_sink: cached reference to default sink found for this device.
217 * @ect_dev: Associated cross trigger device. Not part of the trace data
218 * path or connections.
219 * @nr_links: number of sysfs links created to other components from this
220 * device. These will appear in the "connections" group.
221 * @has_conns_grp: Have added a "connections" group for sysfs links.
223 struct coresight_device {
224 struct coresight_platform_data *pdata;
225 enum coresight_dev_type type;
226 union coresight_dev_subtype subtype;
227 const struct coresight_ops *ops;
228 struct csdev_access access;
232 bool enable; /* true only if configured as part of a path */
233 /* sink specific fields */
234 bool activated; /* true only if a sink is part of a path */
235 struct dev_ext_attribute *ea;
236 struct coresight_device *def_sink;
237 /* cross trigger handling */
238 struct coresight_device *ect_dev;
239 /* sysfs links between components */
242 bool ect_enabled; /* true only if associated ect device is enabled */
246 * coresight_dev_list - Mapping for devices to "name" index for device
249 * @nr_idx: Number of entries already allocated.
250 * @pfx: Prefix pattern for device name.
251 * @fwnode_list: Array of fwnode_handles associated with each allocated
252 * index, upto nr_idx entries.
254 struct coresight_dev_list {
257 struct fwnode_handle **fwnode_list;
260 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
261 static struct coresight_dev_list (var) = { \
264 .fwnode_list = NULL, \
267 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
269 #define source_ops(csdev) csdev->ops->source_ops
270 #define sink_ops(csdev) csdev->ops->sink_ops
271 #define link_ops(csdev) csdev->ops->link_ops
272 #define helper_ops(csdev) csdev->ops->helper_ops
273 #define ect_ops(csdev) csdev->ops->ect_ops
276 * struct coresight_ops_sink - basic operations for a sink
277 * Operations available for sinks
278 * @enable: enables the sink.
279 * @disable: disables the sink.
280 * @alloc_buffer: initialises perf's ring buffer for trace collection.
281 * @free_buffer: release memory allocated in @get_config.
282 * @update_buffer: update buffer pointers after a trace session.
284 struct coresight_ops_sink {
285 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
286 int (*disable)(struct coresight_device *csdev);
287 void *(*alloc_buffer)(struct coresight_device *csdev,
288 struct perf_event *event, void **pages,
289 int nr_pages, bool overwrite);
290 void (*free_buffer)(void *config);
291 unsigned long (*update_buffer)(struct coresight_device *csdev,
292 struct perf_output_handle *handle,
297 * struct coresight_ops_link - basic operations for a link
298 * Operations available for links.
299 * @enable: enables flow between iport and oport.
300 * @disable: disables flow between iport and oport.
302 struct coresight_ops_link {
303 int (*enable)(struct coresight_device *csdev, int iport, int oport);
304 void (*disable)(struct coresight_device *csdev, int iport, int oport);
308 * struct coresight_ops_source - basic operations for a source
309 * Operations available for sources.
310 * @cpu_id: returns the value of the CPU number this component
312 * @trace_id: returns the value of the component's trace ID as known
314 * @enable: enables tracing for a source.
315 * @disable: disables tracing for a source.
317 struct coresight_ops_source {
318 int (*cpu_id)(struct coresight_device *csdev);
319 int (*trace_id)(struct coresight_device *csdev);
320 int (*enable)(struct coresight_device *csdev,
321 struct perf_event *event, u32 mode);
322 void (*disable)(struct coresight_device *csdev,
323 struct perf_event *event);
327 * struct coresight_ops_helper - Operations for a helper device.
329 * All operations could pass in a device specific data, which could
330 * help the helper device to determine what to do.
332 * @enable : Enable the device
333 * @disable : Disable the device
335 struct coresight_ops_helper {
336 int (*enable)(struct coresight_device *csdev, void *data);
337 int (*disable)(struct coresight_device *csdev, void *data);
341 * struct coresight_ops_ect - Ops for an embedded cross trigger device
343 * @enable : Enable the device
344 * @disable : Disable the device
346 struct coresight_ops_ect {
347 int (*enable)(struct coresight_device *csdev);
348 int (*disable)(struct coresight_device *csdev);
351 struct coresight_ops {
352 const struct coresight_ops_sink *sink_ops;
353 const struct coresight_ops_link *link_ops;
354 const struct coresight_ops_source *source_ops;
355 const struct coresight_ops_helper *helper_ops;
356 const struct coresight_ops_ect *ect_ops;
359 #if IS_ENABLED(CONFIG_CORESIGHT)
361 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
364 if (likely(csa->io_mem))
365 return readl_relaxed(csa->base + offset);
367 return csa->read(offset, true, false);
370 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
372 if (likely(csa->io_mem))
373 return readl(csa->base + offset);
375 return csa->read(offset, false, false);
378 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
381 if (likely(csa->io_mem))
382 writel_relaxed(val, csa->base + offset);
384 csa->write(val, offset, true, false);
387 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
389 if (likely(csa->io_mem))
390 writel(val, csa->base + offset);
392 csa->write(val, offset, false, false);
397 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
400 if (likely(csa->io_mem))
401 return readq_relaxed(csa->base + offset);
403 return csa->read(offset, true, true);
406 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
408 if (likely(csa->io_mem))
409 return readq(csa->base + offset);
411 return csa->read(offset, false, true);
414 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
417 if (likely(csa->io_mem))
418 writeq_relaxed(val, csa->base + offset);
420 csa->write(val, offset, true, true);
423 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
425 if (likely(csa->io_mem))
426 writeq(val, csa->base + offset);
428 csa->write(val, offset, false, true);
431 #else /* !CONFIG_64BIT */
433 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
440 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
446 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
452 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
456 #endif /* CONFIG_64BIT */
458 extern struct coresight_device *
459 coresight_register(struct coresight_desc *desc);
460 extern void coresight_unregister(struct coresight_device *csdev);
461 extern int coresight_enable(struct coresight_device *csdev);
462 extern void coresight_disable(struct coresight_device *csdev);
463 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
464 int position, int value);
466 extern int coresight_claim_device(struct coresight_device *csdev);
467 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
469 extern void coresight_disclaim_device(struct coresight_device *csdev);
470 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
471 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
474 extern bool coresight_loses_context_with_cpu(struct device *dev);
476 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
477 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
478 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
479 void coresight_relaxed_write32(struct coresight_device *csdev,
480 u32 val, u32 offset);
481 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
482 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
483 void coresight_relaxed_write64(struct coresight_device *csdev,
484 u64 val, u32 offset);
485 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
488 static inline struct coresight_device *
489 coresight_register(struct coresight_desc *desc) { return NULL; }
490 static inline void coresight_unregister(struct coresight_device *csdev) {}
492 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
493 static inline void coresight_disable(struct coresight_device *csdev) {}
495 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
496 int position, int value)
501 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
506 static inline int coresight_claim_device(struct coresight_device *csdev)
511 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
512 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
514 static inline bool coresight_loses_context_with_cpu(struct device *dev)
519 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
525 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
531 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
535 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
540 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
547 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
553 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
558 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
562 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */
564 extern int coresight_get_cpu(struct device *dev);
566 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
568 #endif /* _LINUX_COREISGHT_H */