1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
9 #include <linux/device.h>
11 #include <linux/perf_event.h>
12 #include <linux/sched.h>
14 /* Peripheral id registers (0xFD0-0xFEC) */
15 #define CORESIGHT_PERIPHIDR4 0xfd0
16 #define CORESIGHT_PERIPHIDR5 0xfd4
17 #define CORESIGHT_PERIPHIDR6 0xfd8
18 #define CORESIGHT_PERIPHIDR7 0xfdC
19 #define CORESIGHT_PERIPHIDR0 0xfe0
20 #define CORESIGHT_PERIPHIDR1 0xfe4
21 #define CORESIGHT_PERIPHIDR2 0xfe8
22 #define CORESIGHT_PERIPHIDR3 0xfeC
23 /* Component id registers (0xFF0-0xFFC) */
24 #define CORESIGHT_COMPIDR0 0xff0
25 #define CORESIGHT_COMPIDR1 0xff4
26 #define CORESIGHT_COMPIDR2 0xff8
27 #define CORESIGHT_COMPIDR3 0xffC
29 #define ETM_ARCH_V3_3 0x23
30 #define ETM_ARCH_V3_5 0x25
31 #define PFT_ARCH_V1_0 0x30
32 #define PFT_ARCH_V1_1 0x31
34 #define CORESIGHT_UNLOCK 0xc5acce55
36 extern struct bus_type coresight_bustype;
38 enum coresight_dev_type {
39 CORESIGHT_DEV_TYPE_NONE,
40 CORESIGHT_DEV_TYPE_SINK,
41 CORESIGHT_DEV_TYPE_LINK,
42 CORESIGHT_DEV_TYPE_LINKSINK,
43 CORESIGHT_DEV_TYPE_SOURCE,
44 CORESIGHT_DEV_TYPE_HELPER,
45 CORESIGHT_DEV_TYPE_ECT,
48 enum coresight_dev_subtype_sink {
49 CORESIGHT_DEV_SUBTYPE_SINK_NONE,
50 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
51 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
52 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
53 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
56 enum coresight_dev_subtype_link {
57 CORESIGHT_DEV_SUBTYPE_LINK_NONE,
58 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
59 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
60 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
63 enum coresight_dev_subtype_source {
64 CORESIGHT_DEV_SUBTYPE_SOURCE_NONE,
65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
70 enum coresight_dev_subtype_helper {
71 CORESIGHT_DEV_SUBTYPE_HELPER_NONE,
72 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
75 /* Embedded Cross Trigger (ECT) sub-types */
76 enum coresight_dev_subtype_ect {
77 CORESIGHT_DEV_SUBTYPE_ECT_NONE,
78 CORESIGHT_DEV_SUBTYPE_ECT_CTI,
82 * union coresight_dev_subtype - further characterisation of a type
83 * @sink_subtype: type of sink this component is, as defined
84 * by @coresight_dev_subtype_sink.
85 * @link_subtype: type of link this component is, as defined
86 * by @coresight_dev_subtype_link.
87 * @source_subtype: type of source this component is, as defined
88 * by @coresight_dev_subtype_source.
89 * @helper_subtype: type of helper this component is, as defined
90 * by @coresight_dev_subtype_helper.
91 * @ect_subtype: type of cross trigger this component is, as
92 * defined by @coresight_dev_subtype_ect
94 union coresight_dev_subtype {
95 /* We have some devices which acts as LINK and SINK */
97 enum coresight_dev_subtype_sink sink_subtype;
98 enum coresight_dev_subtype_link link_subtype;
100 enum coresight_dev_subtype_source source_subtype;
101 enum coresight_dev_subtype_helper helper_subtype;
102 enum coresight_dev_subtype_ect ect_subtype;
106 * struct coresight_platform_data - data harvested from the firmware
109 * @nr_inport: Number of elements for the input connections.
110 * @nr_outport: Number of elements for the output connections.
111 * @conns: Sparse array of nr_outport connections from this component.
113 struct coresight_platform_data {
116 struct coresight_connection *conns;
120 * struct csdev_access - Abstraction of a CoreSight device access.
122 * @io_mem : True if the device has memory mapped I/O
123 * @base : When io_mem == true, base address of the component
124 * @read : Read from the given "offset" of the given instance.
125 * @write : Write "val" to the given "offset".
127 struct csdev_access {
132 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
133 void (*write)(u64 val, u32 offset, bool relaxed,
139 #define CSDEV_ACCESS_IOMEM(_addr) \
140 ((struct csdev_access) { \
146 * struct coresight_desc - description of a component required from drivers
147 * @type: as defined by @coresight_dev_type.
148 * @subtype: as defined by @coresight_dev_subtype.
149 * @ops: generic operations for this component, as defined
151 * @pdata: platform data collected from DT.
152 * @dev: The device entity associated to this component.
153 * @groups: operations specific to this component. These will end up
154 * in the component's sysfs sub-directory.
155 * @name: name for the coresight device, also shown under sysfs.
156 * @access: Describe access to the device
158 struct coresight_desc {
159 enum coresight_dev_type type;
160 union coresight_dev_subtype subtype;
161 const struct coresight_ops *ops;
162 struct coresight_platform_data *pdata;
164 const struct attribute_group **groups;
166 struct csdev_access access;
170 * struct coresight_connection - representation of a single connection
171 * @outport: a connection's output port number.
172 * @child_port: remote component's port number @output is connected to.
173 * @chid_fwnode: remote component's fwnode handle.
174 * @child_dev: a @coresight_device representation of the component
175 connected to @outport.
176 * @link: Representation of the connection as a sysfs link.
178 struct coresight_connection {
181 struct fwnode_handle *child_fwnode;
182 struct coresight_device *child_dev;
183 struct coresight_sysfs_link *link;
187 * struct coresight_sysfs_link - representation of a connection in sysfs.
188 * @orig: Originating (master) coresight device for the link.
189 * @orig_name: Name to use for the link orig->target.
190 * @target: Target (slave) coresight device for the link.
191 * @target_name: Name to use for the link target->orig.
193 struct coresight_sysfs_link {
194 struct coresight_device *orig;
195 const char *orig_name;
196 struct coresight_device *target;
197 const char *target_name;
201 * struct coresight_device - representation of a device as used by the framework
202 * @pdata: Platform data with device connections associated to this device.
203 * @type: as defined by @coresight_dev_type.
204 * @subtype: as defined by @coresight_dev_subtype.
205 * @ops: generic operations for this component, as defined
207 * @access: Device i/o access abstraction for this device.
208 * @dev: The device entity associated to this component.
209 * @refcnt: keep track of what is in use.
210 * @orphan: true if the component has connections that haven't been linked.
211 * @enable: 'true' if component is currently part of an active path.
212 * @activated: 'true' only if a _sink_ has been activated. A sink can be
213 * activated but not yet enabled. Enabling for a _sink_
214 * happens when a source has been selected and a path is enabled
215 * from source to that sink.
216 * @ea: Device attribute for sink representation under PMU directory.
217 * @def_sink: cached reference to default sink found for this device.
218 * @ect_dev: Associated cross trigger device. Not part of the trace data
219 * path or connections.
220 * @nr_links: number of sysfs links created to other components from this
221 * device. These will appear in the "connections" group.
222 * @has_conns_grp: Have added a "connections" group for sysfs links.
224 struct coresight_device {
225 struct coresight_platform_data *pdata;
226 enum coresight_dev_type type;
227 union coresight_dev_subtype subtype;
228 const struct coresight_ops *ops;
229 struct csdev_access access;
233 bool enable; /* true only if configured as part of a path */
234 /* sink specific fields */
235 bool activated; /* true only if a sink is part of a path */
236 struct dev_ext_attribute *ea;
237 struct coresight_device *def_sink;
238 /* cross trigger handling */
239 struct coresight_device *ect_dev;
240 /* sysfs links between components */
243 bool ect_enabled; /* true only if associated ect device is enabled */
247 * coresight_dev_list - Mapping for devices to "name" index for device
250 * @nr_idx: Number of entries already allocated.
251 * @pfx: Prefix pattern for device name.
252 * @fwnode_list: Array of fwnode_handles associated with each allocated
253 * index, upto nr_idx entries.
255 struct coresight_dev_list {
258 struct fwnode_handle **fwnode_list;
261 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
262 static struct coresight_dev_list (var) = { \
265 .fwnode_list = NULL, \
268 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
270 #define source_ops(csdev) csdev->ops->source_ops
271 #define sink_ops(csdev) csdev->ops->sink_ops
272 #define link_ops(csdev) csdev->ops->link_ops
273 #define helper_ops(csdev) csdev->ops->helper_ops
274 #define ect_ops(csdev) csdev->ops->ect_ops
277 * struct coresight_ops_sink - basic operations for a sink
278 * Operations available for sinks
279 * @enable: enables the sink.
280 * @disable: disables the sink.
281 * @alloc_buffer: initialises perf's ring buffer for trace collection.
282 * @free_buffer: release memory allocated in @get_config.
283 * @update_buffer: update buffer pointers after a trace session.
285 struct coresight_ops_sink {
286 int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
287 int (*disable)(struct coresight_device *csdev);
288 void *(*alloc_buffer)(struct coresight_device *csdev,
289 struct perf_event *event, void **pages,
290 int nr_pages, bool overwrite);
291 void (*free_buffer)(void *config);
292 unsigned long (*update_buffer)(struct coresight_device *csdev,
293 struct perf_output_handle *handle,
298 * struct coresight_ops_link - basic operations for a link
299 * Operations available for links.
300 * @enable: enables flow between iport and oport.
301 * @disable: disables flow between iport and oport.
303 struct coresight_ops_link {
304 int (*enable)(struct coresight_device *csdev, int iport, int oport);
305 void (*disable)(struct coresight_device *csdev, int iport, int oport);
309 * struct coresight_ops_source - basic operations for a source
310 * Operations available for sources.
311 * @cpu_id: returns the value of the CPU number this component
313 * @trace_id: returns the value of the component's trace ID as known
315 * @enable: enables tracing for a source.
316 * @disable: disables tracing for a source.
318 struct coresight_ops_source {
319 int (*cpu_id)(struct coresight_device *csdev);
320 int (*trace_id)(struct coresight_device *csdev);
321 int (*enable)(struct coresight_device *csdev,
322 struct perf_event *event, u32 mode);
323 void (*disable)(struct coresight_device *csdev,
324 struct perf_event *event);
328 * struct coresight_ops_helper - Operations for a helper device.
330 * All operations could pass in a device specific data, which could
331 * help the helper device to determine what to do.
333 * @enable : Enable the device
334 * @disable : Disable the device
336 struct coresight_ops_helper {
337 int (*enable)(struct coresight_device *csdev, void *data);
338 int (*disable)(struct coresight_device *csdev, void *data);
342 * struct coresight_ops_ect - Ops for an embedded cross trigger device
344 * @enable : Enable the device
345 * @disable : Disable the device
347 struct coresight_ops_ect {
348 int (*enable)(struct coresight_device *csdev);
349 int (*disable)(struct coresight_device *csdev);
352 struct coresight_ops {
353 const struct coresight_ops_sink *sink_ops;
354 const struct coresight_ops_link *link_ops;
355 const struct coresight_ops_source *source_ops;
356 const struct coresight_ops_helper *helper_ops;
357 const struct coresight_ops_ect *ect_ops;
360 #if IS_ENABLED(CONFIG_CORESIGHT)
362 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
365 if (likely(csa->io_mem))
366 return readl_relaxed(csa->base + offset);
368 return csa->read(offset, true, false);
371 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
373 if (likely(csa->io_mem))
374 return readl(csa->base + offset);
376 return csa->read(offset, false, false);
379 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
382 if (likely(csa->io_mem))
383 writel_relaxed(val, csa->base + offset);
385 csa->write(val, offset, true, false);
388 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
390 if (likely(csa->io_mem))
391 writel(val, csa->base + offset);
393 csa->write(val, offset, false, false);
398 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
401 if (likely(csa->io_mem))
402 return readq_relaxed(csa->base + offset);
404 return csa->read(offset, true, true);
407 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
409 if (likely(csa->io_mem))
410 return readq(csa->base + offset);
412 return csa->read(offset, false, true);
415 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
418 if (likely(csa->io_mem))
419 writeq_relaxed(val, csa->base + offset);
421 csa->write(val, offset, true, true);
424 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
426 if (likely(csa->io_mem))
427 writeq(val, csa->base + offset);
429 csa->write(val, offset, false, true);
432 #else /* !CONFIG_64BIT */
434 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
441 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
447 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
453 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
457 #endif /* CONFIG_64BIT */
459 static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
461 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
462 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
465 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
467 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
468 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
471 extern struct coresight_device *
472 coresight_register(struct coresight_desc *desc);
473 extern void coresight_unregister(struct coresight_device *csdev);
474 extern int coresight_enable(struct coresight_device *csdev);
475 extern void coresight_disable(struct coresight_device *csdev);
476 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
477 int position, int value);
479 extern int coresight_claim_device(struct coresight_device *csdev);
480 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
482 extern void coresight_disclaim_device(struct coresight_device *csdev);
483 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
484 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
487 extern bool coresight_loses_context_with_cpu(struct device *dev);
489 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
490 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
491 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
492 void coresight_relaxed_write32(struct coresight_device *csdev,
493 u32 val, u32 offset);
494 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
495 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
496 void coresight_relaxed_write64(struct coresight_device *csdev,
497 u64 val, u32 offset);
498 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
501 static inline struct coresight_device *
502 coresight_register(struct coresight_desc *desc) { return NULL; }
503 static inline void coresight_unregister(struct coresight_device *csdev) {}
505 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
506 static inline void coresight_disable(struct coresight_device *csdev) {}
508 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
509 int position, int value)
514 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
519 static inline int coresight_claim_device(struct coresight_device *csdev)
524 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
525 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
527 static inline bool coresight_loses_context_with_cpu(struct device *dev)
532 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
538 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
544 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
548 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
553 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
560 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
566 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
571 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
575 #endif /* IS_ENABLED(CONFIG_CORESIGHT) */
577 extern int coresight_get_cpu(struct device *dev);
579 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
581 #endif /* _LINUX_COREISGHT_H */