1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
11 #include <linux/of_clk.h>
13 #ifdef CONFIG_COMMON_CLK
16 * flags used across common struct clk. these flags should only affect the
17 * top-level framework. custom flags for dealing with hardware specifics
18 * belong in struct clk_foo
20 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
22 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
23 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
24 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
28 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
29 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
30 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
31 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
32 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
33 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
34 /* parents need enable during gate/ungate, set rate and re-parent */
35 #define CLK_OPS_PARENT_ENABLE BIT(12)
36 /* duty cycle call may be forwarded to the parent clock */
37 #define CLK_DUTY_CYCLE_PARENT BIT(13)
45 * struct clk_rate_request - Structure encoding the clk constraints that
46 * a clock user might require.
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
53 * requested constraints.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
55 * requested constraints.
58 struct clk_rate_request {
60 unsigned long min_rate;
61 unsigned long max_rate;
62 unsigned long best_parent_rate;
63 struct clk_hw *best_parent_hw;
67 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
69 * @num: Numerator of the duty cycle ratio
70 * @den: Denominator of the duty cycle ratio
78 * struct clk_ops - Callback operations for hardware clocks; these are to
79 * be provided by the clock implementation, and will be called by drivers
80 * through the clk_* api.
82 * @prepare: Prepare the clock for enabling. This must not return until
83 * the clock is fully prepared, and it's safe to call clk_enable.
84 * This callback is intended to allow clock implementations to
85 * do any initialisation that may sleep. Called with
88 * @unprepare: Release the clock from its prepared state. This will typically
89 * undo any work done in the @prepare callback. Called with
92 * @is_prepared: Queries the hardware to determine if the clock is prepared.
93 * This function is allowed to sleep. Optional, if this op is not
94 * set then the prepare count will be used.
96 * @unprepare_unused: Unprepare the clock atomically. Only called from
97 * clk_disable_unused for prepare clocks with special needs.
98 * Called with prepare mutex held. This function may sleep.
100 * @enable: Enable the clock atomically. This must not return until the
101 * clock is generating a valid clock signal, usable by consumer
102 * devices. Called with enable_lock held. This function must not
105 * @disable: Disable the clock atomically. Called with enable_lock held.
106 * This function must not sleep.
108 * @is_enabled: Queries the hardware to determine if the clock is enabled.
109 * This function must not sleep. Optional, if this op is not
110 * set then the enable count will be used.
112 * @disable_unused: Disable the clock atomically. Only called from
113 * clk_disable_unused for gate clocks with special needs.
114 * Called with enable_lock held. This function must not
117 * @save_context: Save the context of the clock in prepration for poweroff.
119 * @restore_context: Restore the context of the clock after a restoration
122 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
123 * parent rate is an input parameter. It is up to the caller to
124 * ensure that the prepare_mutex is held across this call.
125 * Returns the calculated rate. Optional, but recommended - if
126 * this op is not set then clock rate will be initialized to 0.
128 * @round_rate: Given a target rate as input, returns the closest rate actually
129 * supported by the clock. The parent rate is an input/output
132 * @determine_rate: Given a target rate as input, returns the closest rate
133 * actually supported by the clock, and optionally the parent clock
134 * that should be used to provide the clock rate.
136 * @set_parent: Change the input source of this clock; for clocks with multiple
137 * possible parents specify a new parent by passing in the index
138 * as a u8 corresponding to the parent in either the .parent_names
139 * or .parents arrays. This function in affect translates an
140 * array index into the value programmed into the hardware.
141 * Returns 0 on success, -EERROR otherwise.
143 * @get_parent: Queries the hardware to determine the parent of a clock. The
144 * return value is a u8 which specifies the index corresponding to
145 * the parent clock. This index can be applied to either the
146 * .parent_names or .parents arrays. In short, this function
147 * translates the parent value read from hardware into an array
148 * index. Currently only called when the clock is initialized by
149 * __clk_init. This callback is mandatory for clocks with
150 * multiple parents. It is optional (and unnecessary) for clocks
151 * with 0 or 1 parents.
153 * @set_rate: Change the rate of this clock. The requested rate is specified
154 * by the second argument, which should typically be the return
155 * of .round_rate call. The third argument gives the parent rate
156 * which is likely helpful for most .set_rate implementation.
157 * Returns 0 on success, -EERROR otherwise.
159 * @set_rate_and_parent: Change the rate and the parent of this clock. The
160 * requested rate is specified by the second argument, which
161 * should typically be the return of .round_rate call. The
162 * third argument gives the parent rate which is likely helpful
163 * for most .set_rate_and_parent implementation. The fourth
164 * argument gives the parent index. This callback is optional (and
165 * unnecessary) for clocks with 0 or 1 parents as well as
166 * for clocks that can tolerate switching the rate and the parent
167 * separately via calls to .set_parent and .set_rate.
168 * Returns 0 on success, -EERROR otherwise.
170 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
171 * is expressed in ppb (parts per billion). The parent accuracy is
172 * an input parameter.
173 * Returns the calculated accuracy. Optional - if this op is not
174 * set then clock accuracy will be initialized to parent accuracy
175 * or 0 (perfect clock) if clock has no parent.
177 * @get_phase: Queries the hardware to get the current phase of a clock.
178 * Returned values are 0-359 degrees on success, negative
179 * error codes on failure.
181 * @set_phase: Shift the phase this clock signal in degrees specified
182 * by the second argument. Valid values for degrees are
183 * 0-359. Return 0 on success, otherwise -EERROR.
185 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
186 * of a clock. Returned values denominator cannot be 0 and must be
187 * superior or equal to the numerator.
189 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
190 * the numerator (2nd argurment) and denominator (3rd argument).
191 * Argument must be a valid ratio (denominator > 0
192 * and >= numerator) Return 0 on success, otherwise -EERROR.
194 * @init: Perform platform-specific initialization magic.
195 * This is not not used by any of the basic clock types.
196 * Please consider other ways of solving initialization problems
197 * before using this callback, as its use is discouraged.
199 * @debug_init: Set up type-specific debugfs entries for this clock. This
200 * is called once, after the debugfs directory entry for this
201 * clock has been created. The dentry pointer representing that
202 * directory is provided as an argument. Called with
203 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
206 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
207 * implementations to split any work between atomic (enable) and sleepable
208 * (prepare) contexts. If enabling a clock requires code that might sleep,
209 * this must be done in clk_prepare. Clock enable code that will never be
210 * called in a sleepable context may be implemented in clk_enable.
212 * Typically, drivers will call clk_prepare when a clock may be needed later
213 * (eg. when a device is opened), and clk_enable when the clock is actually
214 * required (eg. from an interrupt). Note that clk_prepare MUST have been
215 * called before clk_enable.
218 int (*prepare)(struct clk_hw *hw);
219 void (*unprepare)(struct clk_hw *hw);
220 int (*is_prepared)(struct clk_hw *hw);
221 void (*unprepare_unused)(struct clk_hw *hw);
222 int (*enable)(struct clk_hw *hw);
223 void (*disable)(struct clk_hw *hw);
224 int (*is_enabled)(struct clk_hw *hw);
225 void (*disable_unused)(struct clk_hw *hw);
226 int (*save_context)(struct clk_hw *hw);
227 void (*restore_context)(struct clk_hw *hw);
228 unsigned long (*recalc_rate)(struct clk_hw *hw,
229 unsigned long parent_rate);
230 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
231 unsigned long *parent_rate);
232 int (*determine_rate)(struct clk_hw *hw,
233 struct clk_rate_request *req);
234 int (*set_parent)(struct clk_hw *hw, u8 index);
235 u8 (*get_parent)(struct clk_hw *hw);
236 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
237 unsigned long parent_rate);
238 int (*set_rate_and_parent)(struct clk_hw *hw,
240 unsigned long parent_rate, u8 index);
241 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
242 unsigned long parent_accuracy);
243 int (*get_phase)(struct clk_hw *hw);
244 int (*set_phase)(struct clk_hw *hw, int degrees);
245 int (*get_duty_cycle)(struct clk_hw *hw,
246 struct clk_duty *duty);
247 int (*set_duty_cycle)(struct clk_hw *hw,
248 struct clk_duty *duty);
249 void (*init)(struct clk_hw *hw);
250 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
254 * struct clk_parent_data - clk parent information
255 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
256 * @fw_name: parent name local to provider registering clk
257 * @name: globally unique parent name (used as a fallback)
258 * @index: parent index local to provider registering clk (if @fw_name absent)
260 struct clk_parent_data {
261 const struct clk_hw *hw;
268 * struct clk_init_data - holds init data that's common to all clocks and is
269 * shared between the clock provider and the common clock framework.
272 * @ops: operations this clock supports
273 * @parent_names: array of string names for all possible parents
274 * @parent_data: array of parent data for all possible parents (when some
275 * parents are external to the clk controller)
276 * @parent_hws: array of pointers to all possible parents (when all parents
277 * are internal to the clk controller)
278 * @num_parents: number of possible parents
279 * @flags: framework-level hints and quirks
281 struct clk_init_data {
283 const struct clk_ops *ops;
284 /* Only one of the following three should be assigned */
285 const char * const *parent_names;
286 const struct clk_parent_data *parent_data;
287 const struct clk_hw **parent_hws;
293 * struct clk_hw - handle for traversing from a struct clk to its corresponding
294 * hardware-specific structure. struct clk_hw should be declared within struct
295 * clk_foo and then referenced by the struct clk instance that uses struct
298 * @core: pointer to the struct clk_core instance that points back to this
299 * struct clk_hw instance
301 * @clk: pointer to the per-user struct clk instance that can be used to call
304 * @init: pointer to struct clk_init_data that contains the init data shared
305 * with the common clock framework.
308 struct clk_core *core;
310 const struct clk_init_data *init;
314 * DOC: Basic clock implementations common to many platforms
316 * Each basic clock hardware type is comprised of a structure describing the
317 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
318 * unique flags for that hardware type, a registration function and an
319 * alternative macro for static initialization
323 * struct clk_fixed_rate - fixed-rate clock
324 * @hw: handle between common and hardware-specific interfaces
325 * @fixed_rate: constant frequency of clock
327 struct clk_fixed_rate {
329 unsigned long fixed_rate;
330 unsigned long fixed_accuracy;
333 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
335 extern const struct clk_ops clk_fixed_rate_ops;
336 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
337 const char *parent_name, unsigned long flags,
338 unsigned long fixed_rate);
339 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
340 const char *parent_name, unsigned long flags,
341 unsigned long fixed_rate);
342 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
343 const char *name, const char *parent_name, unsigned long flags,
344 unsigned long fixed_rate, unsigned long fixed_accuracy);
345 void clk_unregister_fixed_rate(struct clk *clk);
346 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
347 const char *name, const char *parent_name, unsigned long flags,
348 unsigned long fixed_rate, unsigned long fixed_accuracy);
349 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
351 void of_fixed_clk_setup(struct device_node *np);
354 * struct clk_gate - gating clock
356 * @hw: handle between common and hardware-specific interfaces
357 * @reg: register controlling gate
358 * @bit_idx: single bit controlling gate
359 * @flags: hardware-specific flags
360 * @lock: register lock
362 * Clock which can gate its output. Implements .enable & .disable
365 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
366 * enable the clock. Setting this flag does the opposite: setting the bit
367 * disable the clock and clearing it enables the clock
368 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
369 * of this register, and mask of gate bits are in higher 16-bit of this
370 * register. While setting the gate bits, higher 16-bit should also be
371 * updated to indicate changing gate bits.
372 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
373 * the gate register. Setting this flag makes the register accesses big
384 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
386 #define CLK_GATE_SET_TO_DISABLE BIT(0)
387 #define CLK_GATE_HIWORD_MASK BIT(1)
388 #define CLK_GATE_BIG_ENDIAN BIT(2)
390 extern const struct clk_ops clk_gate_ops;
391 struct clk *clk_register_gate(struct device *dev, const char *name,
392 const char *parent_name, unsigned long flags,
393 void __iomem *reg, u8 bit_idx,
394 u8 clk_gate_flags, spinlock_t *lock);
395 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
396 const char *parent_name, unsigned long flags,
397 void __iomem *reg, u8 bit_idx,
398 u8 clk_gate_flags, spinlock_t *lock);
399 void clk_unregister_gate(struct clk *clk);
400 void clk_hw_unregister_gate(struct clk_hw *hw);
401 int clk_gate_is_enabled(struct clk_hw *hw);
403 struct clk_div_table {
409 * struct clk_divider - adjustable divider clock
411 * @hw: handle between common and hardware-specific interfaces
412 * @reg: register containing the divider
413 * @shift: shift to the divider bit field
414 * @width: width of the divider bit field
415 * @table: array of value/divider pairs, last entry should have div = 0
416 * @lock: register lock
418 * Clock with an adjustable divider affecting its output frequency. Implements
419 * .recalc_rate, .set_rate and .round_rate
422 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
423 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
424 * the raw value read from the register, with the value of zero considered
425 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
426 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
427 * the hardware register
428 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
429 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
430 * Some hardware implementations gracefully handle this case and allow a
431 * zero divisor by not modifying their input clock
432 * (divide by one / bypass).
433 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
434 * of this register, and mask of divider bits are in higher 16-bit of this
435 * register. While setting the divider bits, higher 16-bit should also be
436 * updated to indicate changing divider bits.
437 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
438 * to the closest integer instead of the up one.
439 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
440 * not be changed by the clock framework.
441 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
442 * except when the value read from the register is zero, the divisor is
443 * 2^width of the field.
444 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
445 * for the divider register. Setting this flag makes the register accesses
454 const struct clk_div_table *table;
458 #define clk_div_mask(width) ((1 << (width)) - 1)
459 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
461 #define CLK_DIVIDER_ONE_BASED BIT(0)
462 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
463 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
464 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
465 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
466 #define CLK_DIVIDER_READ_ONLY BIT(5)
467 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
468 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
470 extern const struct clk_ops clk_divider_ops;
471 extern const struct clk_ops clk_divider_ro_ops;
473 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
474 unsigned int val, const struct clk_div_table *table,
475 unsigned long flags, unsigned long width);
476 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
477 unsigned long rate, unsigned long *prate,
478 const struct clk_div_table *table,
479 u8 width, unsigned long flags);
480 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
481 unsigned long rate, unsigned long *prate,
482 const struct clk_div_table *table, u8 width,
483 unsigned long flags, unsigned int val);
484 int divider_get_val(unsigned long rate, unsigned long parent_rate,
485 const struct clk_div_table *table, u8 width,
486 unsigned long flags);
488 struct clk *clk_register_divider(struct device *dev, const char *name,
489 const char *parent_name, unsigned long flags,
490 void __iomem *reg, u8 shift, u8 width,
491 u8 clk_divider_flags, spinlock_t *lock);
492 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
493 const char *parent_name, unsigned long flags,
494 void __iomem *reg, u8 shift, u8 width,
495 u8 clk_divider_flags, spinlock_t *lock);
496 struct clk *clk_register_divider_table(struct device *dev, const char *name,
497 const char *parent_name, unsigned long flags,
498 void __iomem *reg, u8 shift, u8 width,
499 u8 clk_divider_flags, const struct clk_div_table *table,
501 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
502 const char *name, const char *parent_name, unsigned long flags,
503 void __iomem *reg, u8 shift, u8 width,
504 u8 clk_divider_flags, const struct clk_div_table *table,
506 void clk_unregister_divider(struct clk *clk);
507 void clk_hw_unregister_divider(struct clk_hw *hw);
510 * struct clk_mux - multiplexer clock
512 * @hw: handle between common and hardware-specific interfaces
513 * @reg: register controlling multiplexer
514 * @table: array of register values corresponding to the parent index
515 * @shift: shift to multiplexer bit field
516 * @mask: mask of mutliplexer bit field
517 * @flags: hardware-specific flags
518 * @lock: register lock
520 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
524 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
525 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
526 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
527 * register, and mask of mux bits are in higher 16-bit of this register.
528 * While setting the mux bits, higher 16-bit should also be updated to
529 * indicate changing mux bits.
530 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
531 * .get_parent clk_op.
532 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
534 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
535 * the mux register. Setting this flag makes the register accesses big
548 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
550 #define CLK_MUX_INDEX_ONE BIT(0)
551 #define CLK_MUX_INDEX_BIT BIT(1)
552 #define CLK_MUX_HIWORD_MASK BIT(2)
553 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
554 #define CLK_MUX_ROUND_CLOSEST BIT(4)
555 #define CLK_MUX_BIG_ENDIAN BIT(5)
557 extern const struct clk_ops clk_mux_ops;
558 extern const struct clk_ops clk_mux_ro_ops;
560 struct clk *clk_register_mux(struct device *dev, const char *name,
561 const char * const *parent_names, u8 num_parents,
563 void __iomem *reg, u8 shift, u8 width,
564 u8 clk_mux_flags, spinlock_t *lock);
565 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
566 const char * const *parent_names, u8 num_parents,
568 void __iomem *reg, u8 shift, u8 width,
569 u8 clk_mux_flags, spinlock_t *lock);
571 struct clk *clk_register_mux_table(struct device *dev, const char *name,
572 const char * const *parent_names, u8 num_parents,
574 void __iomem *reg, u8 shift, u32 mask,
575 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
576 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
577 const char * const *parent_names, u8 num_parents,
579 void __iomem *reg, u8 shift, u32 mask,
580 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
582 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
584 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
586 void clk_unregister_mux(struct clk *clk);
587 void clk_hw_unregister_mux(struct clk_hw *hw);
589 void of_fixed_factor_clk_setup(struct device_node *node);
592 * struct clk_fixed_factor - fixed multiplier and divider clock
594 * @hw: handle between common and hardware-specific interfaces
598 * Clock with a fixed multiplier and divider. The output frequency is the
599 * parent clock rate divided by div and multiplied by mult.
600 * Implements .recalc_rate, .set_rate and .round_rate
603 struct clk_fixed_factor {
609 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
611 extern const struct clk_ops clk_fixed_factor_ops;
612 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
613 const char *parent_name, unsigned long flags,
614 unsigned int mult, unsigned int div);
615 void clk_unregister_fixed_factor(struct clk *clk);
616 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
617 const char *name, const char *parent_name, unsigned long flags,
618 unsigned int mult, unsigned int div);
619 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
622 * struct clk_fractional_divider - adjustable fractional divider clock
624 * @hw: handle between common and hardware-specific interfaces
625 * @reg: register containing the divider
626 * @mshift: shift to the numerator bit field
627 * @mwidth: width of the numerator bit field
628 * @nshift: shift to the denominator bit field
629 * @nwidth: width of the denominator bit field
630 * @lock: register lock
632 * Clock with adjustable fractional divider affecting its output frequency.
635 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
636 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
637 * is set then the numerator and denominator are both the value read
639 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
640 * used for the divider register. Setting this flag makes the register
641 * accesses big endian.
643 struct clk_fractional_divider {
653 void (*approximation)(struct clk_hw *hw,
654 unsigned long rate, unsigned long *parent_rate,
655 unsigned long *m, unsigned long *n);
659 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
661 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
662 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
664 extern const struct clk_ops clk_fractional_divider_ops;
665 struct clk *clk_register_fractional_divider(struct device *dev,
666 const char *name, const char *parent_name, unsigned long flags,
667 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
668 u8 clk_divider_flags, spinlock_t *lock);
669 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
670 const char *name, const char *parent_name, unsigned long flags,
671 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
672 u8 clk_divider_flags, spinlock_t *lock);
673 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
676 * struct clk_multiplier - adjustable multiplier clock
678 * @hw: handle between common and hardware-specific interfaces
679 * @reg: register containing the multiplier
680 * @shift: shift to the multiplier bit field
681 * @width: width of the multiplier bit field
682 * @lock: register lock
684 * Clock with an adjustable multiplier affecting its output frequency.
685 * Implements .recalc_rate, .set_rate and .round_rate
688 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
689 * from the register, with 0 being a valid value effectively
690 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
691 * set, then a null multiplier will be considered as a bypass,
692 * leaving the parent rate unmodified.
693 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
694 * rounded to the closest integer instead of the down one.
695 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
696 * used for the multiplier register. Setting this flag makes the register
697 * accesses big endian.
699 struct clk_multiplier {
708 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
710 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
711 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
712 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
714 extern const struct clk_ops clk_multiplier_ops;
717 * struct clk_composite - aggregate clock of mux, divider and gate clocks
719 * @hw: handle between common and hardware-specific interfaces
720 * @mux_hw: handle between composite and hardware-specific mux clock
721 * @rate_hw: handle between composite and hardware-specific rate clock
722 * @gate_hw: handle between composite and hardware-specific gate clock
723 * @mux_ops: clock ops for mux
724 * @rate_ops: clock ops for rate
725 * @gate_ops: clock ops for gate
727 struct clk_composite {
731 struct clk_hw *mux_hw;
732 struct clk_hw *rate_hw;
733 struct clk_hw *gate_hw;
735 const struct clk_ops *mux_ops;
736 const struct clk_ops *rate_ops;
737 const struct clk_ops *gate_ops;
740 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
742 struct clk *clk_register_composite(struct device *dev, const char *name,
743 const char * const *parent_names, int num_parents,
744 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
745 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
746 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
747 unsigned long flags);
748 void clk_unregister_composite(struct clk *clk);
749 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
750 const char * const *parent_names, int num_parents,
751 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
752 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
753 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
754 unsigned long flags);
755 void clk_hw_unregister_composite(struct clk_hw *hw);
758 * struct clk_gpio - gpio gated clock
760 * @hw: handle between common and hardware-specific interfaces
761 * @gpiod: gpio descriptor
763 * Clock with a gpio control for enabling and disabling the parent clock
764 * or switching between two parents by asserting or deasserting the gpio.
766 * Implements .enable, .disable and .is_enabled or
767 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
772 struct gpio_desc *gpiod;
775 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
777 extern const struct clk_ops clk_gpio_gate_ops;
778 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
779 const char *parent_name, struct gpio_desc *gpiod,
780 unsigned long flags);
781 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
782 const char *parent_name, struct gpio_desc *gpiod,
783 unsigned long flags);
784 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
786 extern const struct clk_ops clk_gpio_mux_ops;
787 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
788 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
789 unsigned long flags);
790 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
791 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
792 unsigned long flags);
793 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
795 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
796 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
798 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
799 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
800 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
802 void clk_unregister(struct clk *clk);
803 void devm_clk_unregister(struct device *dev, struct clk *clk);
805 void clk_hw_unregister(struct clk_hw *hw);
806 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
808 /* helper functions */
809 const char *__clk_get_name(const struct clk *clk);
810 const char *clk_hw_get_name(const struct clk_hw *hw);
811 struct clk_hw *__clk_get_hw(struct clk *clk);
812 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
813 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
814 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
816 unsigned int __clk_get_enable_count(struct clk *clk);
817 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
818 unsigned long __clk_get_flags(struct clk *clk);
819 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
820 #define clk_hw_can_set_rate_parent(hw) \
821 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
823 bool clk_hw_is_prepared(const struct clk_hw *hw);
824 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
825 bool clk_hw_is_enabled(const struct clk_hw *hw);
826 bool __clk_is_enabled(struct clk *clk);
827 struct clk *__clk_lookup(const char *name);
828 int __clk_mux_determine_rate(struct clk_hw *hw,
829 struct clk_rate_request *req);
830 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
831 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
832 struct clk_rate_request *req);
833 int clk_mux_determine_rate_flags(struct clk_hw *hw,
834 struct clk_rate_request *req,
835 unsigned long flags);
836 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
837 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
838 unsigned long max_rate);
840 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
843 dst->core = src->core;
846 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
847 unsigned long *prate,
848 const struct clk_div_table *table,
849 u8 width, unsigned long flags)
851 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
852 rate, prate, table, width, flags);
855 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
856 unsigned long *prate,
857 const struct clk_div_table *table,
858 u8 width, unsigned long flags,
861 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
862 rate, prate, table, width, flags,
867 * FIXME clock api without lock protection
869 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
873 struct clk_onecell_data {
875 unsigned int clk_num;
878 struct clk_hw_onecell_data {
880 struct clk_hw *hws[];
883 extern struct of_device_id __clk_of_table;
885 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
888 * Use this macro when you have a driver that requires two initialization
889 * routines, one at of_clk_init(), and one at platform device probe
891 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
892 static void __init name##_of_clk_init_driver(struct device_node *np) \
894 of_node_clear_flag(np, OF_POPULATED); \
897 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
899 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
900 (&(struct clk_init_data) { \
903 .parent_names = (const char *[]) { _parent }, \
908 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
909 (&(struct clk_init_data) { \
912 .parent_names = _parents, \
913 .num_parents = ARRAY_SIZE(_parents), \
917 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
918 (&(struct clk_init_data) { \
921 .parent_names = NULL, \
926 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
927 _div, _mult, _flags) \
928 struct clk_fixed_factor _struct = { \
931 .hw.init = CLK_HW_INIT(_name, \
933 &clk_fixed_factor_ops, \
938 int of_clk_add_provider(struct device_node *np,
939 struct clk *(*clk_src_get)(struct of_phandle_args *args,
942 int of_clk_add_hw_provider(struct device_node *np,
943 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
946 int devm_of_clk_add_hw_provider(struct device *dev,
947 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
950 void of_clk_del_provider(struct device_node *np);
951 void devm_of_clk_del_provider(struct device *dev);
952 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
954 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
956 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
957 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
959 int of_clk_parent_fill(struct device_node *np, const char **parents,
961 int of_clk_detect_critical(struct device_node *np, int index,
962 unsigned long *flags);
964 #else /* !CONFIG_OF */
966 static inline int of_clk_add_provider(struct device_node *np,
967 struct clk *(*clk_src_get)(struct of_phandle_args *args,
973 static inline int of_clk_add_hw_provider(struct device_node *np,
974 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
980 static inline int devm_of_clk_add_hw_provider(struct device *dev,
981 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
987 static inline void of_clk_del_provider(struct device_node *np) {}
988 static inline void devm_of_clk_del_provider(struct device *dev) {}
989 static inline struct clk *of_clk_src_simple_get(
990 struct of_phandle_args *clkspec, void *data)
992 return ERR_PTR(-ENOENT);
994 static inline struct clk_hw *
995 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
997 return ERR_PTR(-ENOENT);
999 static inline struct clk *of_clk_src_onecell_get(
1000 struct of_phandle_args *clkspec, void *data)
1002 return ERR_PTR(-ENOENT);
1004 static inline struct clk_hw *
1005 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1007 return ERR_PTR(-ENOENT);
1009 static inline int of_clk_parent_fill(struct device_node *np,
1010 const char **parents, unsigned int size)
1014 static inline int of_clk_detect_critical(struct device_node *np, int index,
1015 unsigned long *flags)
1019 #endif /* CONFIG_OF */
1021 void clk_gate_restore_context(struct clk_hw *hw);
1023 #endif /* CONFIG_COMMON_CLK */
1024 #endif /* CLK_PROVIDER_H */