1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_BRCMPHY_H
3 #define _LINUX_BRCMPHY_H
7 /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
8 * to configure the switch internal registers via MDIO accesses.
10 #define BRCM_PSEUDO_PHY_ADDR 30
12 #define PHY_ID_BCM50610 0x0143bd60
13 #define PHY_ID_BCM50610M 0x0143bd70
14 #define PHY_ID_BCM5241 0x0143bc30
15 #define PHY_ID_BCMAC131 0x0143bc70
16 #define PHY_ID_BCM5481 0x0143bca0
17 #define PHY_ID_BCM5395 0x0143bcf0
18 #define PHY_ID_BCM54810 0x03625d00
19 #define PHY_ID_BCM5482 0x0143bcb0
20 #define PHY_ID_BCM5411 0x00206070
21 #define PHY_ID_BCM5421 0x002060e0
22 #define PHY_ID_BCM54210E 0x600d84a0
23 #define PHY_ID_BCM5464 0x002060b0
24 #define PHY_ID_BCM5461 0x002060c0
25 #define PHY_ID_BCM54612E 0x03625e60
26 #define PHY_ID_BCM54616S 0x03625d10
27 #define PHY_ID_BCM57780 0x03625d90
28 #define PHY_ID_BCM89610 0x03625cd0
30 #define PHY_ID_BCM7250 0xae025280
31 #define PHY_ID_BCM7255 0xae025120
32 #define PHY_ID_BCM7260 0xae025190
33 #define PHY_ID_BCM7268 0xae025090
34 #define PHY_ID_BCM7271 0xae0253b0
35 #define PHY_ID_BCM7278 0xae0251a0
36 #define PHY_ID_BCM7364 0xae025260
37 #define PHY_ID_BCM7366 0x600d8490
38 #define PHY_ID_BCM7346 0x600d8650
39 #define PHY_ID_BCM7362 0x600d84b0
40 #define PHY_ID_BCM7425 0x600d86b0
41 #define PHY_ID_BCM7429 0x600d8730
42 #define PHY_ID_BCM7435 0x600d8750
43 #define PHY_ID_BCM74371 0xae0252e0
44 #define PHY_ID_BCM7439 0x600d8480
45 #define PHY_ID_BCM7439_2 0xae025080
46 #define PHY_ID_BCM7445 0x600d8510
48 #define PHY_ID_BCM_CYGNUS 0xae025200
49 #define PHY_ID_BCM_OMEGA 0xae025100
51 #define PHY_BCM_OUI_MASK 0xfffffc00
52 #define PHY_BCM_OUI_1 0x00206000
53 #define PHY_BCM_OUI_2 0x0143bc00
54 #define PHY_BCM_OUI_3 0x03625c00
55 #define PHY_BCM_OUI_4 0x600d8400
56 #define PHY_BCM_OUI_5 0x03625e00
57 #define PHY_BCM_OUI_6 0xae025000
59 #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001
60 #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002
61 #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010
62 #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020
63 #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100
64 #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200
65 #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400
66 #define PHY_BRCM_STD_IBND_DISABLE 0x00000800
67 #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000
68 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
69 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
70 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
71 #define PHY_BRCM_EN_MASTER_MODE 0x00010000
73 /* Broadcom BCM7xxx specific workarounds */
74 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
75 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
76 #define PHY_BCM_FLAGS_VALID 0x80000000
78 /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */
79 #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
80 #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
81 #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
83 #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
84 #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
86 #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
87 #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
88 #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
89 #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
90 #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */
92 #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
93 #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
94 #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
95 #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
96 #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
97 #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
98 #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
99 #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
100 #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
101 #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
102 #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
103 #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
104 #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
105 #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
106 #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
107 #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
108 #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
109 #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
111 #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
112 #define MII_BCM54XX_SHD_WRITE 0x8000
113 #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
114 #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
117 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
119 #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00
120 #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
121 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
123 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07
124 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010
125 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100
126 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
127 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
129 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
130 #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
133 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
134 * BCM5482, and possibly some others.
136 #define BCM_LED_SRC_LINKSPD1 0x0
137 #define BCM_LED_SRC_LINKSPD2 0x1
138 #define BCM_LED_SRC_XMITLED 0x2
139 #define BCM_LED_SRC_ACTIVITYLED 0x3
140 #define BCM_LED_SRC_FDXLED 0x4
141 #define BCM_LED_SRC_SLAVE 0x5
142 #define BCM_LED_SRC_INTR 0x6
143 #define BCM_LED_SRC_QUALITY 0x7
144 #define BCM_LED_SRC_RCVLED 0x8
145 #define BCM_LED_SRC_WIRESPEED 0x9
146 #define BCM_LED_SRC_MULTICOLOR1 0xa
147 #define BCM_LED_SRC_OPENSHORT 0xb
148 #define BCM_LED_SRC_OFF 0xe /* Tied high */
149 #define BCM_LED_SRC_ON 0xf /* Tied low */
152 * Broadcom Multicolor LED configurations (expansion register 4)
154 #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04)
155 #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8)
156 #define BCM_LED_MULTICOLOR_LINK_ACT 0x0
157 #define BCM_LED_MULTICOLOR_SPEED 0x1
158 #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2
159 #define BCM_LED_MULTICOLOR_FDX 0x3
160 #define BCM_LED_MULTICOLOR_OFF 0x4
161 #define BCM_LED_MULTICOLOR_ON 0x5
162 #define BCM_LED_MULTICOLOR_ALT 0x6
163 #define BCM_LED_MULTICOLOR_FLASH 0x7
164 #define BCM_LED_MULTICOLOR_LINK 0x8
165 #define BCM_LED_MULTICOLOR_ACT 0x9
166 #define BCM_LED_MULTICOLOR_PROGRAM 0xa
169 * BCM5482: Shadow registers
170 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
171 * register to access.
174 /* 00100: Reserved control register 2 */
175 #define BCM54XX_SHD_SCR2 0x04
176 #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100
177 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2
178 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2
179 #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7
181 /* 00101: Spare Control Register 3 */
182 #define BCM54XX_SHD_SCR3 0x05
183 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
184 #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
185 #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
187 /* 01010: Auto Power-Down */
188 #define BCM54XX_SHD_APD 0x0a
189 #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */
190 #define BCM54XX_SHD_APD_EN 0x0020
191 #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */
192 #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */
194 #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
195 /* LED3 / ~LINKSPD[2] selector */
196 #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
197 /* LED1 / ~LINKSPD[1] selector */
198 #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
199 #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
200 #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
201 #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
202 #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
204 /* 10011: SerDes 100-FX Control Register */
205 #define BCM54616S_SHD_100FX_CTRL 0x13
206 #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */
208 /* 11111: Mode Control Register */
209 #define BCM54XX_SHD_MODE 0x1f
210 #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */
211 #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */
214 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
216 #define MII_BCM54XX_EXP_AADJ1CH0 0x001f
217 #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
218 #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
219 #define MII_BCM54XX_EXP_AADJ1CH3 0x601f
220 #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
221 #define MII_BCM54XX_EXP_EXP08 0x0F08
222 #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
223 #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
224 #define MII_BCM54XX_EXP_EXP75 0x0f75
225 #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
226 #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
227 #define MII_BCM54XX_EXP_EXP96 0x0f96
228 #define MII_BCM54XX_EXP_EXP96_MYST 0x0010
229 #define MII_BCM54XX_EXP_EXP97 0x0f97
230 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
233 * BCM5482: Secondary SerDes registers
235 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
236 #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
237 #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
238 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
239 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
241 /* BCM54810 Registers */
242 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
243 #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
244 #define BCM54810_SHD_CLK_CTL 0x3
245 #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
247 /* BCM54612E Registers */
248 #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34)
249 #define BCM54612E_LED4_CLK125OUT_EN (1 << 1)
251 /*****************************************************************************/
252 /* Fast Ethernet Transceiver definitions. */
253 /*****************************************************************************/
255 #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
256 #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
257 #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
258 #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
259 #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
260 #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
262 #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
263 #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
266 /*** Shadow register definitions ***/
268 #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
269 #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
271 #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
272 #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
273 #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
275 #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
276 #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
278 #define BRCM_CL45VEN_EEE_CONTROL 0x803d
279 #define LPI_FEATURE_EN 0x8000
280 #define LPI_FEATURE_EN_DIG1000X 0x4000
282 /* Core register definitions*/
283 #define MII_BRCM_CORE_BASE12 0x12
284 #define MII_BRCM_CORE_BASE13 0x13
285 #define MII_BRCM_CORE_BASE14 0x14
286 #define MII_BRCM_CORE_BASE1E 0x1E
287 #define MII_BRCM_CORE_EXPB0 0xB0
288 #define MII_BRCM_CORE_EXPB1 0xB1
290 #endif /* _LINUX_BRCMPHY_H */