1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2015 Linaro Ltd.
4 * Author: Shannon Zhao <shannon.zhao@linaro.org>
7 #ifndef __ASM_ARM_KVM_PMU_H
8 #define __ASM_ARM_KVM_PMU_H
10 #include <linux/perf_event.h>
11 #include <linux/perf/arm_pmuv3.h>
13 #define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
15 #ifdef CONFIG_HW_PERF_EVENTS
18 u8 idx; /* index into the pmu->pmc array */
19 struct perf_event *perf_event;
22 struct kvm_pmu_events {
28 struct irq_work overflow_work;
29 struct kvm_pmu_events events;
30 struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
36 struct arm_pmu_entry {
37 struct list_head entry;
38 struct arm_pmu *arm_pmu;
41 DECLARE_STATIC_KEY_FALSE(kvm_arm_pmu_available);
43 static __always_inline bool kvm_arm_support_pmu_v3(void)
45 return static_branch_likely(&kvm_arm_pmu_available);
48 #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
49 u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
50 void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
51 u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
52 u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1);
53 void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
54 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
55 void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
56 void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
57 void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
58 void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
59 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
60 bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
61 void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
62 void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
63 void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
64 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
66 int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
67 struct kvm_device_attr *attr);
68 int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
69 struct kvm_device_attr *attr);
70 int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
71 struct kvm_device_attr *attr);
72 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
74 struct kvm_pmu_events *kvm_get_pmu_events(void);
75 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
76 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
78 #define kvm_vcpu_has_pmu(vcpu) \
79 (test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
82 * Updates the vcpu's view of the pmu events for this cpu.
83 * Must be called before every vcpu run after disabling interrupts, to ensure
84 * that an interrupt cannot fire and update the structure.
86 #define kvm_pmu_update_vcpu_events(vcpu) \
88 if (!has_vhe() && kvm_vcpu_has_pmu(vcpu)) \
89 vcpu->arch.pmu.events = *kvm_get_pmu_events(); \
93 * Evaluates as true when emulating PMUv3p5, and false otherwise.
95 #define kvm_pmu_is_3p5(vcpu) ({ \
96 u64 val = IDREG(vcpu->kvm, SYS_ID_AA64DFR0_EL1); \
97 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); \
99 pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5; \
102 u8 kvm_arm_pmu_get_pmuver_limit(void);
108 static inline bool kvm_arm_support_pmu_v3(void)
113 #define kvm_arm_pmu_irq_initialized(v) (false)
114 static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
119 static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
120 u64 select_idx, u64 val) {}
121 static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
125 static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
126 static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
127 static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
128 static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
129 static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
130 static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
131 static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
132 static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
136 static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
137 static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
138 static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
139 static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
140 u64 data, u64 select_idx) {}
141 static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
142 struct kvm_device_attr *attr)
146 static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
147 struct kvm_device_attr *attr)
151 static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
152 struct kvm_device_attr *attr)
156 static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
160 static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1)
165 #define kvm_vcpu_has_pmu(vcpu) ({ false; })
166 #define kvm_pmu_is_3p5(vcpu) ({ false; })
167 static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {}
168 static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {}
169 static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {}
170 static inline u8 kvm_arm_pmu_get_pmuver_limit(void)