2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
26 /* sclk gates (special clocks) */
40 #define SCLK_TIMER0 85
41 #define SCLK_TIMER1 86
42 #define SCLK_TIMER2 87
43 #define SCLK_TIMER3 88
44 #define SCLK_TIMER4 89
45 #define SCLK_TIMER5 90
46 #define SCLK_I2S_OUT 113
47 #define SCLK_SDMMC_DRV 114
48 #define SCLK_SDIO_DRV 115
49 #define SCLK_EMMC_DRV 117
50 #define SCLK_SDMMC_SAMPLE 118
51 #define SCLK_SDIO_SAMPLE 119
52 #define SCLK_SDIO_SRC 120
53 #define SCLK_EMMC_SAMPLE 121
55 #define SCLK_HDMI_HDCP 123
56 #define SCLK_MAC_SRC 124
57 #define SCLK_MAC_EXTCLK 125
59 #define SCLK_MAC_REFOUT 127
60 #define SCLK_MAC_REF 128
61 #define SCLK_MAC_RX 129
62 #define SCLK_MAC_TX 130
63 #define SCLK_MAC_PHY 131
64 #define SCLK_MAC_OUT 132
65 #define SCLK_VDEC_CABAC 133
66 #define SCLK_VDEC_CORE 134
69 #define SCLK_HDMI_CEC 137
70 #define SCLK_CRYPTO 138
72 #define SCLK_HSADC 140
74 #define SCLK_OTGPHY0 142
75 #define SCLK_OTGPHY1 143
76 #define SCLK_HDMI_PHY 144
80 #define DCLK_HDMI_PHY 191
85 #define ACLK_VPU_PRE 196
86 #define ACLK_RKVDEC_PRE 197
87 #define ACLK_RGA_PRE 198
88 #define ACLK_IEP_PRE 199
89 #define ACLK_HDCP_PRE 200
90 #define ACLK_VOP_PRE 201
92 #define ACLK_RKVDEC 203
102 #define PCLK_GPIO0 320
103 #define PCLK_GPIO1 321
104 #define PCLK_GPIO2 322
105 #define PCLK_GPIO3 323
106 #define PCLK_VIO_H2P 324
107 #define PCLK_HDCP 325
108 #define PCLK_EFUSE_1024 326
109 #define PCLK_EFUSE_256 327
111 #define PCLK_I2C0 332
112 #define PCLK_I2C1 333
113 #define PCLK_I2C2 334
114 #define PCLK_I2C3 335
115 #define PCLK_SPI0 338
116 #define PCLK_UART0 341
117 #define PCLK_UART1 342
118 #define PCLK_UART2 343
119 #define PCLK_TSADC 344
121 #define PCLK_TIMER 353
123 #define PCLK_PERI 363
124 #define PCLK_HDMI_CTRL 364
125 #define PCLK_HDMI_PHY 365
126 #define PCLK_GMAC 367
129 #define HCLK_I2S0_8CH 442
130 #define HCLK_I2S1_8CH 443
131 #define HCLK_I2S2_2CH 444
132 #define HCLK_SPDIF_8CH 445
134 #define HCLK_NANDC 453
135 #define HCLK_SDMMC 456
136 #define HCLK_SDIO 457
137 #define HCLK_EMMC 459
139 #define HCLK_VPU_PRE 461
140 #define HCLK_RKVDEC_PRE 462
141 #define HCLK_VIO_PRE 463
143 #define HCLK_RKVDEC 465
147 #define HCLK_VIO_H2P 469
148 #define HCLK_HDCP_MMU 470
149 #define HCLK_HOST0 471
150 #define HCLK_HOST1 472
151 #define HCLK_HOST2 473
154 #define HCLK_M_CRYPTO 476
155 #define HCLK_S_CRYPTO 477
156 #define HCLK_PERI 478
158 #define CLK_NR_CLKS (HCLK_PERI + 1)
160 /* soft-reset indices */
161 #define SRST_CORE0_PO 0
162 #define SRST_CORE1_PO 1
163 #define SRST_CORE2_PO 2
164 #define SRST_CORE3_PO 3
169 #define SRST_CORE0_DBG 8
170 #define SRST_CORE1_DBG 9
171 #define SRST_CORE2_DBG 10
172 #define SRST_CORE3_DBG 11
173 #define SRST_TOPDBG 12
174 #define SRST_ACLK_CORE 13
178 #define SRST_CPUSYS_H 18
179 #define SRST_BUSSYS_H 19
180 #define SRST_SPDIF 20
181 #define SRST_INTMEM 21
183 #define SRST_OTG_ADP 23
187 #define SRST_ACODEC_P 27
188 #define SRST_DFIMON 28
190 #define SRST_EFUSE1024 30
191 #define SRST_EFUSE256 31
193 #define SRST_GPIO0 32
194 #define SRST_GPIO1 33
195 #define SRST_GPIO2 34
196 #define SRST_GPIO3 35
197 #define SRST_PERIPH_NOC_A 36
198 #define SRST_PERIPH_NOC_BUS_H 37
199 #define SRST_PERIPH_NOC_P 38
200 #define SRST_UART0 39
201 #define SRST_UART1 40
202 #define SRST_UART2 41
203 #define SRST_PHYNOC 42
210 #define SRST_A53_GIC 49
212 #define SRST_DAP_NOC 52
213 #define SRST_CRYPTO 53
217 #define SRST_PERIPH_NOC_H 58
218 #define SRST_MACPHY 63
221 #define SRST_NANDC 68
222 #define SRST_USBOTG 69
224 #define SRST_USBHOST0 71
225 #define SRST_HOST_CTRL0 72
226 #define SRST_USBHOST1 73
227 #define SRST_HOST_CTRL1 74
228 #define SRST_USBHOST2 75
229 #define SRST_HOST_CTRL2 76
230 #define SRST_USBPOR0 77
231 #define SRST_USBPOR1 78
232 #define SRST_DDRMSCH 79
234 #define SRST_SMART_CARD 80
235 #define SRST_SDMMC 81
239 #define SRST_TSP_H 85
241 #define SRST_TSADC 87
242 #define SRST_DDRPHY 88
243 #define SRST_DDRPHY_P 89
244 #define SRST_DDRCTRL 90
245 #define SRST_DDRCTRL_P 91
246 #define SRST_HOST0_ECHI 92
247 #define SRST_HOST1_ECHI 93
248 #define SRST_HOST2_ECHI 94
249 #define SRST_VOP_NOC_A 95
251 #define SRST_HDMI_P 96
252 #define SRST_VIO_ARBI_H 97
253 #define SRST_IEP_NOC_A 98
254 #define SRST_VIO_NOC_H 99
255 #define SRST_VOP_A 100
256 #define SRST_VOP_H 101
257 #define SRST_VOP_D 102
258 #define SRST_UTMI0 103
259 #define SRST_UTMI1 104
260 #define SRST_UTMI2 105
261 #define SRST_UTMI3 106
263 #define SRST_RGA_NOC_A 108
264 #define SRST_RGA_A 109
265 #define SRST_RGA_H 110
266 #define SRST_HDCP_A 111
268 #define SRST_VPU_A 112
269 #define SRST_VPU_H 113
270 #define SRST_VPU_NOC_A 116
271 #define SRST_VPU_NOC_H 117
272 #define SRST_RKVDEC_A 118
273 #define SRST_RKVDEC_NOC_A 119
274 #define SRST_RKVDEC_H 120
275 #define SRST_RKVDEC_NOC_H 121
276 #define SRST_RKVDEC_CORE 122
277 #define SRST_RKVDEC_CABAC 123
278 #define SRST_IEP_A 124
279 #define SRST_IEP_H 125
280 #define SRST_GPU_A 126
281 #define SRST_GPU_NOC_A 127
283 #define SRST_CORE_DBG 128
284 #define SRST_DBG_P 129
285 #define SRST_TIMER0 130
286 #define SRST_TIMER1 131
287 #define SRST_TIMER2 132
288 #define SRST_TIMER3 133
289 #define SRST_TIMER4 134
290 #define SRST_TIMER5 135
291 #define SRST_VIO_H2P 136
292 #define SRST_HDMIPHY 139
293 #define SRST_VDAC 140
294 #define SRST_TIMER_6CH_P 141