include/dt-bindings/clock/qcom,gcc-sm8250.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
   7 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
   8
   9 /* GCC clocks */
  10 #define GPLL0                                                   0
  11 #define GPLL0_OUT_EVEN                                          1
  12 #define GPLL4                                                   2
  13 #define GPLL9                                                   3
  14 #define GCC_AGGRE_NOC_PCIE_TBU_CLK                              4
  15 #define GCC_AGGRE_UFS_CARD_AXI_CLK                              5
  16 #define GCC_AGGRE_UFS_PHY_AXI_CLK                               6
  17 #define GCC_AGGRE_USB3_PRIM_AXI_CLK                             7
  18 #define GCC_AGGRE_USB3_SEC_AXI_CLK                              8
  19 #define GCC_BOOT_ROM_AHB_CLK                                    9
  20 #define GCC_CAMERA_AHB_CLK                                      10
  21 #define GCC_CAMERA_HF_AXI_CLK                                   11
  22 #define GCC_CAMERA_SF_AXI_CLK                                   12
  23 #define GCC_CAMERA_XO_CLK                                       13
  24 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           14
  25 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK                            15
  26 #define GCC_CPUSS_AHB_CLK                                       16
  27 #define GCC_CPUSS_AHB_CLK_SRC                                   17
  28 #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC                           18
  29 #define GCC_CPUSS_DVM_BUS_CLK                                   19
  30 #define GCC_CPUSS_RBCPR_CLK                                     20
  31 #define GCC_DDRSS_GPU_AXI_CLK                                   21
  32 #define GCC_DDRSS_PCIE_SF_TBU_CLK                               22
  33 #define GCC_DISP_AHB_CLK                                        23
  34 #define GCC_DISP_HF_AXI_CLK                                     24
  35 #define GCC_DISP_SF_AXI_CLK                                     25
  36 #define GCC_DISP_XO_CLK                                         26
  37 #define GCC_GP1_CLK                                             27
  38 #define GCC_GP1_CLK_SRC                                         28
  39 #define GCC_GP2_CLK                                             29
  40 #define GCC_GP2_CLK_SRC                                         30
  41 #define GCC_GP3_CLK                                             31
  42 #define GCC_GP3_CLK_SRC                                         32
  43 #define GCC_GPU_CFG_AHB_CLK                                     33
  44 #define GCC_GPU_GPLL0_CLK_SRC                                   34
  45 #define GCC_GPU_GPLL0_DIV_CLK_SRC                               35
  46 #define GCC_GPU_IREF_EN                                         36
  47 #define GCC_GPU_MEMNOC_GFX_CLK                                  37
  48 #define GCC_GPU_SNOC_DVM_GFX_CLK                                38
  49 #define GCC_NPU_AXI_CLK                                         39
  50 #define GCC_NPU_BWMON_AXI_CLK                                   40
  51 #define GCC_NPU_BWMON_CFG_AHB_CLK                               41
  52 #define GCC_NPU_CFG_AHB_CLK                                     42
  53 #define GCC_NPU_DMA_CLK                                         43
  54 #define GCC_NPU_GPLL0_CLK_SRC                                   44
  55 #define GCC_NPU_GPLL0_DIV_CLK_SRC                               45
  56 #define GCC_PCIE0_PHY_REFGEN_CLK                                46
  57 #define GCC_PCIE1_PHY_REFGEN_CLK                                47
  58 #define GCC_PCIE2_PHY_REFGEN_CLK                                48
  59 #define GCC_PCIE_0_AUX_CLK                                      49
  60 #define GCC_PCIE_0_AUX_CLK_SRC                                  50
  61 #define GCC_PCIE_0_CFG_AHB_CLK                                  51
  62 #define GCC_PCIE_0_MSTR_AXI_CLK                                 52
  63 #define GCC_PCIE_0_PIPE_CLK                                     53
  64 #define GCC_PCIE_0_SLV_AXI_CLK                                  54
  65 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              55
  66 #define GCC_PCIE_1_AUX_CLK                                      56
  67 #define GCC_PCIE_1_AUX_CLK_SRC                                  57
  68 #define GCC_PCIE_1_CFG_AHB_CLK                                  58
  69 #define GCC_PCIE_1_MSTR_AXI_CLK                                 59
  70 #define GCC_PCIE_1_PIPE_CLK                                     60
  71 #define GCC_PCIE_1_SLV_AXI_CLK                                  61
  72 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              62
  73 #define GCC_PCIE_2_AUX_CLK                                      63
  74 #define GCC_PCIE_2_AUX_CLK_SRC                                  64
  75 #define GCC_PCIE_2_CFG_AHB_CLK                                  65
  76 #define GCC_PCIE_2_MSTR_AXI_CLK                                 66
  77 #define GCC_PCIE_2_PIPE_CLK                                     67
  78 #define GCC_PCIE_2_SLV_AXI_CLK                                  68
  79 #define GCC_PCIE_2_SLV_Q2A_AXI_CLK                              69
  80 #define GCC_PCIE_MDM_CLKREF_EN                                  70
  81 #define GCC_PCIE_PHY_AUX_CLK                                    71
  82 #define GCC_PCIE_PHY_REFGEN_CLK_SRC                             72
  83 #define GCC_PCIE_WIFI_CLKREF_EN                                 73
  84 #define GCC_PCIE_WIGIG_CLKREF_EN                                74
  85 #define GCC_PDM2_CLK                                            75
  86 #define GCC_PDM2_CLK_SRC                                        76
  87 #define GCC_PDM_AHB_CLK                                         77
  88 #define GCC_PDM_XO4_CLK                                         78
  89 #define GCC_PRNG_AHB_CLK                                        79
  90 #define GCC_QMIP_CAMERA_NRT_AHB_CLK                             80
  91 #define GCC_QMIP_CAMERA_RT_AHB_CLK                              81
  92 #define GCC_QMIP_DISP_AHB_CLK                                   82
  93 #define GCC_QMIP_VIDEO_CVP_AHB_CLK                              83
  94 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK                           84
  95 #define GCC_QUPV3_WRAP0_CORE_2X_CLK                             85
  96 #define GCC_QUPV3_WRAP0_CORE_CLK                                86
  97 #define GCC_QUPV3_WRAP0_S0_CLK                                  87
  98 #define GCC_QUPV3_WRAP0_S0_CLK_SRC                              88
  99 #define GCC_QUPV3_WRAP0_S1_CLK                                  89
 100 #define GCC_QUPV3_WRAP0_S1_CLK_SRC                              90
 101 #define GCC_QUPV3_WRAP0_S2_CLK                                  91
 102 #define GCC_QUPV3_WRAP0_S2_CLK_SRC                              92
 103 #define GCC_QUPV3_WRAP0_S3_CLK                                  93
 104 #define GCC_QUPV3_WRAP0_S3_CLK_SRC                              94
 105 #define GCC_QUPV3_WRAP0_S4_CLK                                  95
 106 #define GCC_QUPV3_WRAP0_S4_CLK_SRC                              96
 107 #define GCC_QUPV3_WRAP0_S5_CLK                                  97
 108 #define GCC_QUPV3_WRAP0_S5_CLK_SRC                              98
 109 #define GCC_QUPV3_WRAP0_S6_CLK                                  99
 110 #define GCC_QUPV3_WRAP0_S6_CLK_SRC                              100
 111 #define GCC_QUPV3_WRAP0_S7_CLK                                  101
 112 #define GCC_QUPV3_WRAP0_S7_CLK_SRC                              102
 113 #define GCC_QUPV3_WRAP1_CORE_2X_CLK                             103
 114 #define GCC_QUPV3_WRAP1_CORE_CLK                                104
 115 #define GCC_QUPV3_WRAP1_S0_CLK                                  105
 116 #define GCC_QUPV3_WRAP1_S0_CLK_SRC                              106
 117 #define GCC_QUPV3_WRAP1_S1_CLK                                  107
 118 #define GCC_QUPV3_WRAP1_S1_CLK_SRC                              108
 119 #define GCC_QUPV3_WRAP1_S2_CLK                                  109
 120 #define GCC_QUPV3_WRAP1_S2_CLK_SRC                              110
 121 #define GCC_QUPV3_WRAP1_S3_CLK                                  111
 122 #define GCC_QUPV3_WRAP1_S3_CLK_SRC                              112
 123 #define GCC_QUPV3_WRAP1_S4_CLK                                  113
 124 #define GCC_QUPV3_WRAP1_S4_CLK_SRC                              114
 125 #define GCC_QUPV3_WRAP1_S5_CLK                                  115
 126 #define GCC_QUPV3_WRAP1_S5_CLK_SRC                              116
 127 #define GCC_QUPV3_WRAP2_CORE_2X_CLK                             117
 128 #define GCC_QUPV3_WRAP2_CORE_CLK                                118
 129 #define GCC_QUPV3_WRAP2_S0_CLK                                  119
 130 #define GCC_QUPV3_WRAP2_S0_CLK_SRC                              120
 131 #define GCC_QUPV3_WRAP2_S1_CLK                                  121
 132 #define GCC_QUPV3_WRAP2_S1_CLK_SRC                              122
 133 #define GCC_QUPV3_WRAP2_S2_CLK                                  123
 134 #define GCC_QUPV3_WRAP2_S2_CLK_SRC                              124
 135 #define GCC_QUPV3_WRAP2_S3_CLK                                  125
 136 #define GCC_QUPV3_WRAP2_S3_CLK_SRC                              126
 137 #define GCC_QUPV3_WRAP2_S4_CLK                                  127
 138 #define GCC_QUPV3_WRAP2_S4_CLK_SRC                              128
 139 #define GCC_QUPV3_WRAP2_S5_CLK                                  129
 140 #define GCC_QUPV3_WRAP2_S5_CLK_SRC                              130
 141 #define GCC_QUPV3_WRAP_0_M_AHB_CLK                              131
 142 #define GCC_QUPV3_WRAP_0_S_AHB_CLK                              132
 143 #define GCC_QUPV3_WRAP_1_M_AHB_CLK                              133
 144 #define GCC_QUPV3_WRAP_1_S_AHB_CLK                              134
 145 #define GCC_QUPV3_WRAP_2_M_AHB_CLK                              135
 146 #define GCC_QUPV3_WRAP_2_S_AHB_CLK                              136
 147 #define GCC_SDCC2_AHB_CLK                                       137
 148 #define GCC_SDCC2_APPS_CLK                                      138
 149 #define GCC_SDCC2_APPS_CLK_SRC                                  139
 150 #define GCC_SDCC4_AHB_CLK                                       140
 151 #define GCC_SDCC4_APPS_CLK                                      141
 152 #define GCC_SDCC4_APPS_CLK_SRC                                  142
 153 #define GCC_SYS_NOC_CPUSS_AHB_CLK                               143
 154 #define GCC_TSIF_AHB_CLK                                        144
 155 #define GCC_TSIF_INACTIVITY_TIMERS_CLK                          145
 156 #define GCC_TSIF_REF_CLK                                        146
 157 #define GCC_TSIF_REF_CLK_SRC                                    147
 158 #define GCC_UFS_1X_CLKREF_EN                                    148
 159 #define GCC_UFS_CARD_AHB_CLK                                    149
 160 #define GCC_UFS_CARD_AXI_CLK                                    150
 161 #define GCC_UFS_CARD_AXI_CLK_SRC                                151
 162 #define GCC_UFS_CARD_ICE_CORE_CLK                               152
 163 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC                           153
 164 #define GCC_UFS_CARD_PHY_AUX_CLK                                154
 165 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC                            155
 166 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK                            156
 167 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK                            157
 168 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK                            158
 169 #define GCC_UFS_CARD_UNIPRO_CORE_CLK                            159
 170 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC                        160
 171 #define GCC_UFS_PHY_AHB_CLK                                     161
 172 #define GCC_UFS_PHY_AXI_CLK                                     162
 173 #define GCC_UFS_PHY_AXI_CLK_SRC                                 163
 174 #define GCC_UFS_PHY_ICE_CORE_CLK                                164
 175 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            165
 176 #define GCC_UFS_PHY_PHY_AUX_CLK                                 166
 177 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             167
 178 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             168
 179 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             169
 180 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             170
 181 #define GCC_UFS_PHY_UNIPRO_CORE_CLK                             171
 182 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         172
 183 #define GCC_USB30_PRIM_MASTER_CLK                               173
 184 #define GCC_USB30_PRIM_MASTER_CLK_SRC                           174
 185 #define GCC_USB30_PRIM_MOCK_UTMI_CLK                            175
 186 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        176
 187 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC                177
 188 #define GCC_USB30_PRIM_SLEEP_CLK                                178
 189 #define GCC_USB30_SEC_MASTER_CLK                                179
 190 #define GCC_USB30_SEC_MASTER_CLK_SRC                            180
 191 #define GCC_USB30_SEC_MOCK_UTMI_CLK                             181
 192 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC                         182
 193 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC                 183
 194 #define GCC_USB30_SEC_SLEEP_CLK                                 184
 195 #define GCC_USB3_PRIM_PHY_AUX_CLK                               185
 196 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           186
 197 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           187
 198 #define GCC_USB3_PRIM_PHY_PIPE_CLK                              188
 199 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC                          189
 200 #define GCC_USB3_SEC_CLKREF_EN                                  190
 201 #define GCC_USB3_SEC_PHY_AUX_CLK                                191
 202 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC                            192
 203 #define GCC_USB3_SEC_PHY_COM_AUX_CLK                            193
 204 #define GCC_USB3_SEC_PHY_PIPE_CLK                               194
 205 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC                           195
 206 #define GCC_VIDEO_AHB_CLK                                       196
 207 #define GCC_VIDEO_AXI0_CLK                                      197
 208 #define GCC_VIDEO_AXI1_CLK                                      198
 209 #define GCC_VIDEO_XO_CLK                                        199
 210
 211 /* GCC resets */
 212 #define GCC_GPU_BCR                                             0
 213 #define GCC_MMSS_BCR                                            1
 214 #define GCC_NPU_BWMON_BCR                                       2
 215 #define GCC_NPU_BCR                                             3
 216 #define GCC_PCIE_0_BCR                                          4
 217 #define GCC_PCIE_0_LINK_DOWN_BCR                                5
 218 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR                            6
 219 #define GCC_PCIE_0_PHY_BCR                                      7
 220 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR                        8
 221 #define GCC_PCIE_1_BCR                                          9
 222 #define GCC_PCIE_1_LINK_DOWN_BCR                                10
 223 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR                            11
 224 #define GCC_PCIE_1_PHY_BCR                                      12
 225 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR                        13
 226 #define GCC_PCIE_2_BCR                                          14
 227 #define GCC_PCIE_2_LINK_DOWN_BCR                                15
 228 #define GCC_PCIE_2_NOCSR_COM_PHY_BCR                            16
 229 #define GCC_PCIE_2_PHY_BCR                                      17
 230 #define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR                        18
 231 #define GCC_PCIE_PHY_BCR                                        19
 232 #define GCC_PCIE_PHY_CFG_AHB_BCR                                20
 233 #define GCC_PCIE_PHY_COM_BCR                                    21
 234 #define GCC_PDM_BCR                                             22
 235 #define GCC_PRNG_BCR                                            23
 236 #define GCC_QUPV3_WRAPPER_0_BCR                                 24
 237 #define GCC_QUPV3_WRAPPER_1_BCR                                 25
 238 #define GCC_QUPV3_WRAPPER_2_BCR                                 26
 239 #define GCC_QUSB2PHY_PRIM_BCR                                   27
 240 #define GCC_QUSB2PHY_SEC_BCR                                    28
 241 #define GCC_SDCC2_BCR                                           29
 242 #define GCC_SDCC4_BCR                                           30
 243 #define GCC_TSIF_BCR                                            31
 244 #define GCC_UFS_CARD_BCR                                        32
 245 #define GCC_UFS_PHY_BCR                                         33
 246 #define GCC_USB30_PRIM_BCR                                      34
 247 #define GCC_USB30_SEC_BCR                                       35
 248 #define GCC_USB3_DP_PHY_PRIM_BCR                                36
 249 #define GCC_USB3_DP_PHY_SEC_BCR                                 37
 250 #define GCC_USB3_PHY_PRIM_BCR                                   38
 251 #define GCC_USB3_PHY_SEC_BCR                                    39
 252 #define GCC_USB3PHY_PHY_PRIM_BCR                                40
 253 #define GCC_USB3PHY_PHY_SEC_BCR                                 41
 254 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             42
 255 #define GCC_VIDEO_AXI0_CLK_ARES                                 43
 256 #define GCC_VIDEO_AXI1_CLK_ARES                                 44
 257
 258 /* GCC power domains */
 259 #define PCIE_0_GDSC                                             0
 260 #define PCIE_1_GDSC                                             1
 261 #define PCIE_2_GDSC                                             2
 262 #define UFS_CARD_GDSC                                           3
 263 #define UFS_PHY_GDSC                                            4
 264 #define USB30_PRIM_GDSC                                         5
 265 #define USB30_SEC_GDSC                                          6
 266 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC                       7
 267 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC                       8
 268 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC                       9
 269 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC                       10
 270
 271 #endif