include/dt-bindings/clock/qcom,gcc-sc7280.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
   7 #define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H
   8
   9 /* GCC clocks */
  10 #define GCC_GPLL0                                       0
  11 #define GCC_GPLL0_OUT_EVEN                              1
  12 #define GCC_GPLL0_OUT_ODD                               2
  13 #define GCC_GPLL1                                       3
  14 #define GCC_GPLL10                                      4
  15 #define GCC_GPLL4                                       5
  16 #define GCC_GPLL9                                       6
  17 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK                    7
  18 #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK                    8
  19 #define GCC_AGGRE_UFS_PHY_AXI_CLK                       9
  20 #define GCC_AGGRE_USB3_PRIM_AXI_CLK                     10
  21 #define GCC_CAMERA_AHB_CLK                              11
  22 #define GCC_CAMERA_HF_AXI_CLK                           12
  23 #define GCC_CAMERA_SF_AXI_CLK                           13
  24 #define GCC_CAMERA_XO_CLK                               14
  25 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                   15
  26 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK                    16
  27 #define GCC_CPUSS_AHB_CLK                               17
  28 #define GCC_CPUSS_AHB_CLK_SRC                           18
  29 #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC                   19
  30 #define GCC_DDRSS_GPU_AXI_CLK                           20
  31 #define GCC_DDRSS_PCIE_SF_CLK                           21
  32 #define GCC_DISP_AHB_CLK                                22
  33 #define GCC_DISP_GPLL0_CLK_SRC                          23
  34 #define GCC_DISP_HF_AXI_CLK                             24
  35 #define GCC_DISP_SF_AXI_CLK                             25
  36 #define GCC_DISP_XO_CLK                                 26
  37 #define GCC_GP1_CLK                                     27
  38 #define GCC_GP1_CLK_SRC                                 28
  39 #define GCC_GP2_CLK                                     29
  40 #define GCC_GP2_CLK_SRC                                 30
  41 #define GCC_GP3_CLK                                     31
  42 #define GCC_GP3_CLK_SRC                                 32
  43 #define GCC_GPU_CFG_AHB_CLK                             33
  44 #define GCC_GPU_GPLL0_CLK_SRC                           34
  45 #define GCC_GPU_GPLL0_DIV_CLK_SRC                       35
  46 #define GCC_GPU_IREF_EN                                 36
  47 #define GCC_GPU_MEMNOC_GFX_CLK                          37
  48 #define GCC_GPU_SNOC_DVM_GFX_CLK                        38
  49 #define GCC_PCIE0_PHY_RCHNG_CLK                         39
  50 #define GCC_PCIE1_PHY_RCHNG_CLK                         40
  51 #define GCC_PCIE_0_AUX_CLK                              41
  52 #define GCC_PCIE_0_AUX_CLK_SRC                          42
  53 #define GCC_PCIE_0_CFG_AHB_CLK                          43
  54 #define GCC_PCIE_0_MSTR_AXI_CLK                         44
  55 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC                    45
  56 #define GCC_PCIE_0_PIPE_CLK                             46
  57 #define GCC_PCIE_0_PIPE_CLK_SRC                         47
  58 #define GCC_PCIE_0_SLV_AXI_CLK                          48
  59 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK                      49
  60 #define GCC_PCIE_1_AUX_CLK                              50
  61 #define GCC_PCIE_1_AUX_CLK_SRC                          51
  62 #define GCC_PCIE_1_CFG_AHB_CLK                          52
  63 #define GCC_PCIE_1_MSTR_AXI_CLK                         53
  64 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC                    54
  65 #define GCC_PCIE_1_PIPE_CLK                             55
  66 #define GCC_PCIE_1_PIPE_CLK_SRC                         56
  67 #define GCC_PCIE_1_SLV_AXI_CLK                          57
  68 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK                      58
  69 #define GCC_PCIE_THROTTLE_CORE_CLK                      59
  70 #define GCC_PDM2_CLK                                    60
  71 #define GCC_PDM2_CLK_SRC                                61
  72 #define GCC_PDM_AHB_CLK                                 62
  73 #define GCC_PDM_XO4_CLK                                 63
  74 #define GCC_QMIP_CAMERA_NRT_AHB_CLK                     64
  75 #define GCC_QMIP_CAMERA_RT_AHB_CLK                      65
  76 #define GCC_QMIP_DISP_AHB_CLK                           66
  77 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK                   67
  78 #define GCC_QUPV3_WRAP0_CORE_2X_CLK                     68
  79 #define GCC_QUPV3_WRAP0_CORE_CLK                        69
  80 #define GCC_QUPV3_WRAP0_S0_CLK                          70
  81 #define GCC_QUPV3_WRAP0_S0_CLK_SRC                      71
  82 #define GCC_QUPV3_WRAP0_S1_CLK                          72
  83 #define GCC_QUPV3_WRAP0_S1_CLK_SRC                      73
  84 #define GCC_QUPV3_WRAP0_S2_CLK                          74
  85 #define GCC_QUPV3_WRAP0_S2_CLK_SRC                      75
  86 #define GCC_QUPV3_WRAP0_S3_CLK                          76
  87 #define GCC_QUPV3_WRAP0_S3_CLK_SRC                      77
  88 #define GCC_QUPV3_WRAP0_S4_CLK                          78
  89 #define GCC_QUPV3_WRAP0_S4_CLK_SRC                      79
  90 #define GCC_QUPV3_WRAP0_S5_CLK                          80
  91 #define GCC_QUPV3_WRAP0_S5_CLK_SRC                      81
  92 #define GCC_QUPV3_WRAP0_S6_CLK                          82
  93 #define GCC_QUPV3_WRAP0_S6_CLK_SRC                      83
  94 #define GCC_QUPV3_WRAP0_S7_CLK                          84
  95 #define GCC_QUPV3_WRAP0_S7_CLK_SRC                      85
  96 #define GCC_QUPV3_WRAP1_CORE_2X_CLK                     86
  97 #define GCC_QUPV3_WRAP1_CORE_CLK                        87
  98 #define GCC_QUPV3_WRAP1_S0_CLK                          88
  99 #define GCC_QUPV3_WRAP1_S0_CLK_SRC                      89
 100 #define GCC_QUPV3_WRAP1_S1_CLK                          90
 101 #define GCC_QUPV3_WRAP1_S1_CLK_SRC                      91
 102 #define GCC_QUPV3_WRAP1_S2_CLK                          92
 103 #define GCC_QUPV3_WRAP1_S2_CLK_SRC                      93
 104 #define GCC_QUPV3_WRAP1_S3_CLK                          94
 105 #define GCC_QUPV3_WRAP1_S3_CLK_SRC                      95
 106 #define GCC_QUPV3_WRAP1_S4_CLK                          96
 107 #define GCC_QUPV3_WRAP1_S4_CLK_SRC                      97
 108 #define GCC_QUPV3_WRAP1_S5_CLK                          98
 109 #define GCC_QUPV3_WRAP1_S5_CLK_SRC                      99
 110 #define GCC_QUPV3_WRAP1_S6_CLK                          100
 111 #define GCC_QUPV3_WRAP1_S6_CLK_SRC                      101
 112 #define GCC_QUPV3_WRAP1_S7_CLK                          102
 113 #define GCC_QUPV3_WRAP1_S7_CLK_SRC                      103
 114 #define GCC_QUPV3_WRAP_0_M_AHB_CLK                      104
 115 #define GCC_QUPV3_WRAP_0_S_AHB_CLK                      105
 116 #define GCC_QUPV3_WRAP_1_M_AHB_CLK                      106
 117 #define GCC_QUPV3_WRAP_1_S_AHB_CLK                      107
 118 #define GCC_SDCC1_AHB_CLK                               108
 119 #define GCC_SDCC1_APPS_CLK                              109
 120 #define GCC_SDCC1_APPS_CLK_SRC                          110
 121 #define GCC_SDCC1_ICE_CORE_CLK                          111
 122 #define GCC_SDCC1_ICE_CORE_CLK_SRC                      112
 123 #define GCC_SDCC2_AHB_CLK                               113
 124 #define GCC_SDCC2_APPS_CLK                              114
 125 #define GCC_SDCC2_APPS_CLK_SRC                          115
 126 #define GCC_SDCC4_AHB_CLK                               116
 127 #define GCC_SDCC4_APPS_CLK                              117
 128 #define GCC_SDCC4_APPS_CLK_SRC                          118
 129 #define GCC_SYS_NOC_CPUSS_AHB_CLK                       119
 130 #define GCC_THROTTLE_PCIE_AHB_CLK                       120
 131 #define GCC_TITAN_NRT_THROTTLE_CORE_CLK                 121
 132 #define GCC_TITAN_RT_THROTTLE_CORE_CLK                  122
 133 #define GCC_UFS_1_CLKREF_EN                             123
 134 #define GCC_UFS_PHY_AHB_CLK                             124
 135 #define GCC_UFS_PHY_AXI_CLK                             125
 136 #define GCC_UFS_PHY_AXI_CLK_SRC                         126
 137 #define GCC_UFS_PHY_ICE_CORE_CLK                        127
 138 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC                    128
 139 #define GCC_UFS_PHY_PHY_AUX_CLK                         129
 140 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC                     130
 141 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK                     131
 142 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC                 132
 143 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK                     133
 144 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC                 134
 145 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK                     135
 146 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC                 136
 147 #define GCC_UFS_PHY_UNIPRO_CORE_CLK                     137
 148 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                 138
 149 #define GCC_USB30_PRIM_MASTER_CLK                       139
 150 #define GCC_USB30_PRIM_MASTER_CLK_SRC                   140
 151 #define GCC_USB30_PRIM_MOCK_UTMI_CLK                    141
 152 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                142
 153 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC        143
 154 #define GCC_USB30_PRIM_SLEEP_CLK                        144
 155 #define GCC_USB30_SEC_MASTER_CLK                        145
 156 #define GCC_USB30_SEC_MASTER_CLK_SRC                    146
 157 #define GCC_USB30_SEC_MOCK_UTMI_CLK                     147
 158 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC                 148
 159 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC         149
 160 #define GCC_USB30_SEC_SLEEP_CLK                         150
 161 #define GCC_USB3_PRIM_PHY_AUX_CLK                       151
 162 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                   152
 163 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK                   153
 164 #define GCC_USB3_PRIM_PHY_PIPE_CLK                      154
 165 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC                  155
 166 #define GCC_USB3_SEC_PHY_AUX_CLK                        156
 167 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC                    157
 168 #define GCC_USB3_SEC_PHY_COM_AUX_CLK                    158
 169 #define GCC_USB3_SEC_PHY_PIPE_CLK                       159
 170 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC                   160
 171 #define GCC_VIDEO_AHB_CLK                               161
 172 #define GCC_VIDEO_AXI0_CLK                              162
 173 #define GCC_VIDEO_MVP_THROTTLE_CORE_CLK                 163
 174 #define GCC_VIDEO_XO_CLK                                164
 175 #define GCC_GPLL0_MAIN_DIV_CDIV                         165
 176 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK                    166
 177 #define GCC_QSPI_CORE_CLK                               167
 178 #define GCC_QSPI_CORE_CLK_SRC                           168
 179 #define GCC_CFG_NOC_LPASS_CLK                           169
 180 #define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC                  170
 181 #define GCC_MSS_CFG_AHB_CLK                             171
 182 #define GCC_MSS_OFFLINE_AXI_CLK                         172
 183 #define GCC_MSS_SNOC_AXI_CLK                            173
 184 #define GCC_MSS_Q6_MEMNOC_AXI_CLK                       174
 185 #define GCC_MSS_Q6SS_BOOT_CLK_SRC                       175
 186 #define GCC_AGGRE_USB3_SEC_AXI_CLK                      176
 187 #define GCC_AGGRE_NOC_PCIE_TBU_CLK                      177
 188 #define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK            178
 189 #define GCC_PCIE_CLKREF_EN                              179
 190 #define GCC_WPSS_AHB_CLK                                180
 191 #define GCC_WPSS_AHB_BDG_MST_CLK                        181
 192 #define GCC_WPSS_RSCP_CLK                               182
 193 #define GCC_EDP_CLKREF_EN                               183
 194 #define GCC_SEC_CTRL_CLK_SRC                            184
 195
 196 /* GCC power domains */
 197 #define GCC_PCIE_0_GDSC                                 0
 198 #define GCC_PCIE_1_GDSC                                 1
 199 #define GCC_UFS_PHY_GDSC                                2
 200 #define GCC_USB30_PRIM_GDSC                             3
 201 #define GCC_USB30_SEC_GDSC                              4
 202 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC               5
 203 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC               6
 204 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC               7
 205 #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC                 8
 206 #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC                 9
 207
 208 /* GCC resets */
 209 #define GCC_PCIE_0_BCR                                  0
 210 #define GCC_PCIE_0_PHY_BCR                              1
 211 #define GCC_PCIE_1_BCR                                  2
 212 #define GCC_PCIE_1_PHY_BCR                              3
 213 #define GCC_QUSB2PHY_PRIM_BCR                           4
 214 #define GCC_QUSB2PHY_SEC_BCR                            5
 215 #define GCC_SDCC1_BCR                                   6
 216 #define GCC_SDCC2_BCR                                   7
 217 #define GCC_SDCC4_BCR                                   8
 218 #define GCC_UFS_PHY_BCR                                 9
 219 #define GCC_USB30_PRIM_BCR                              10
 220 #define GCC_USB30_SEC_BCR                               11
 221 #define GCC_USB3_DP_PHY_PRIM_BCR                        12
 222 #define GCC_USB3_PHY_PRIM_BCR                           13
 223 #define GCC_USB3PHY_PHY_PRIM_BCR                        14
 224 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                     15
 225
 226 #endif